A high-speed column readout circuit and method for CMOS image sensor

Abstract

The present invention relates to a column readout circuit for a CMOS image sensor, and more specifically, to a high-speed column readout circuit for a CMOS image sensor. This circuit solves the technical problems of existing column readout circuits, such as slow signal readout speed, inability to output two-terminal voltage signals, and inability to externally adjust the output range. The present invention comprises m branches, a holding and amplifying circuit, and a multiplexer, and has a two-stage amplification function. The multiplexer is used to implement time-sharing readout of sampling signals from the m branches. The branches include a column buffer circuit and a correlated double sampling circuit. The column buffer circuit utilizes fixed capacitors, and by varying the proportional relationship between the two fixed capacitors, different amplification factors are achieved to implement first-stage amplification. The correlated double sampling circuit and the holding and amplifying circuit utilize programmable capacitors, which are combined to form a gain amplifier to implement second-stage amplification. The proportional relationship of the programmable capacitors is changed through external control, causing the amplification factor of the column readout circuit to change accordingly, thereby flexibly adjusting the output range.

Description

Technical Field

[0001] The present invention relates to a column readout circuit of a CMOS image sensor, and in particular to a high-speed column readout circuit and method for a CMOS image sensor. Background Art

[0002] CMOS image sensors are widely used in smartphones, industry, medicine, and scientific research. In CMOS image sensors, the readout circuitry sits between the pixel array and the analog-to-digital converter, playing a crucial role in noise suppression and signal amplification. Readout circuits can generally be categorized into three types: pixel-serial readout, column-parallel readout, and pixel-parallel readout. Column-parallel readout is the most widely used readout circuit architecture in CMOS image sensors because it offers a good compromise between speed, area, and power consumption.

[0003] With the continuous development of CMOS image sensors, higher requirements are also being placed on the performance of column readout circuits: first, in order to increase the frame frequency of CMOS image sensors, the column readout circuit is required to have a high signal readout speed; second, the column readout circuit must have a correlated double sampling function to eliminate the fixed-mode noise of the pixel circuit; third, the column readout circuit must have a signal amplification function to expand the dynamic range of the CMOS image sensor; fourth, due to the limited area within the CMOS image sensor chip, the column readout circuit is required to achieve as high accuracy and speed as possible within the limited space.

[0004] Traditional column readout circuits generally balance and comprehensively optimize multiple performance parameters, but often still face the following problems or requirements:

[0005] (1) The source follower in the pixel generally has a weak driving capability, and directly connecting it to the sampling capacitor will result in a slow signal readout speed;

[0006] (2) Since the output of the column readout circuit is directly connected to the input of the analog-to-digital converter, most current analog-to-digital converter designs use analog differential input to suppress circuit noise. Therefore, the column readout circuit is required to be able to convert the single-ended voltage signal output by the pixel into a two-terminal analog differential voltage signal;

[0007] (3) In order to ensure that the analog-to-digital converter can output full-scale, the output range of the column readout circuit must match the input range of the analog-to-digital converter. However, circuit design deviations often make this requirement difficult to achieve. Therefore, the output range of the column readout circuit needs to be externally adjustable. Summary of the Invention

[0008] The present invention aims to solve the technical problems of slow signal readout speed, inability to output two-terminal analog differential voltage signals, and inability to externally adjust the output range of existing column readout circuits, and to provide a high-speed column readout circuit and method for CMOS image sensors.

[0009] To achieve the above object, the technical solution adopted by the present invention is:

[0010] A high-speed column readout circuit for a CMOS image sensor, which is special in that it includes m branches for buffering sampling, a holding and amplifying circuit, and a multiplexer, where m is an integer greater than or equal to 1;

[0011] The branch includes a column buffer circuit and a correlated double sampling circuit;

[0012] The input ends of the m column buffer circuits are all connected to the output ends of the pixel circuit, and are used to buffer and amplify the photogenerated signal and reset signal of the pixel circuit to improve the pixel signal reading speed; the output ends of the m column buffer circuits are respectively connected to the data input ends of the m correlated double sampling circuits;

[0013] m correlated double sampling circuits respectively sample the photogenerated signals and reset signals output by the m column buffer circuits, and subtract the photogenerated signals from the reset signals through charge sharing to eliminate the fixed-mode noise of the pixel circuit; the m correlated double sampling circuits use amplifiers with adjustable gains, and their outputs are connected to the inputs of the holding and amplification circuits;

[0014] The output end of the multiplexer is connected to the control input end of m correlated double sampling circuits respectively, and is used to read out the signals of the correlated double sampling circuits in the m branches to the holding and amplifying circuit in a time-sharing manner;

[0015] The holding and amplifying circuit is used to hold and amplify the signals sampled and output by m related dual circuits, and uses a gain-adjustable amplifier to convert a single-ended unipolar voltage signal into a double-ended bipolar voltage signal and output it.

[0016] Furthermore, the column buffer circuit includes a single-ended amplifier AMP, three switches S1 to S3, and two capacitors C1 and C2;

[0017] One end of each of the m switches S1 is connected to the output end of the pixel circuit, and the other end of the switch S1 is connected to the left plate of the capacitor C1 and one end of the switch S2 respectively;

[0018] The right plate of capacitor C1 is connected to the input terminal of the single-ended amplifier AMP, the left plate of capacitor C2 and one end of switch S3;

[0019] The output end of the single-ended amplifier AMP is connected to the right plate of the capacitor C2, the other end of the switch S3 and the other end of the switch S2; the output end of the single-ended amplifier AMP is connected to the input end of the correlated double sampling circuit of the corresponding branch.

[0020] Furthermore, the correlated double sampling circuit includes seven switches S4 to S10 and two adjustable capacitors C3 and C4;

[0021] One end of the switch S4 and one end of the switch S5 are both connected to the output end of the single-ended amplifier AMP of the column buffer circuit in the corresponding branch;

[0022] The other end of the switch S4 is connected to one end of the switch S8 and the left plate of the adjustable capacitor C3; the right plate of the adjustable capacitor C3 is connected to one end of the switch S6 and one end of the switch S9, and the other end of the switch S6 is connected to the external input reference voltage signal VREF;

[0023] The other end of the switch S5 is connected to the other end of the switch S8 and the left plate of the adjustable capacitor C4; the right plate of the adjustable capacitor C4 is connected to one end of the switch S7 and one end of the switch S10, and the other end of the switch S7 is grounded;

[0024] The other ends of the m switches S9 are connected to one input end of the holding and amplifying circuit, and the other ends of the m switches S10 are connected to the other input end of the holding and amplifying circuit;

[0025] The multiplexer includes three selectors with m outputs;

[0026] The m outputs of the three selectors are respectively connected to the switches S8, S9, and S10 of the correlated double sampling circuits in the m branches, and are used to respectively control the closing and closing of the switches S8, S9, and S10 in the m correlated double sampling circuit branches, and read out the signals of the correlated double sampling circuits in the m branches to the holding and amplification circuits in a time-sharing manner.

[0027] Furthermore, the holding and amplifying circuit includes a fully differential operational amplifier OP-AMP, seven switches S11 to S17, and two adjustable capacitors C5 and C6;

[0028] One end of the switch S11 is connected to the other ends of the m switches S9, and is also connected to the non-inverting input of the fully differential operational amplifier OP-AMP and the left plate of the adjustable capacitor C5;

[0029] One end of the switch S12 is connected to the other ends of the m switches S10, and is also connected to the inverting input of the fully differential operational amplifier OP-AMP and the left plate of the adjustable capacitor C6;

[0030] The inverting output terminal VOUTN of the fully differential operational amplifier OP-AMP is connected to one end of the switch S15 and one end of the switch S17, the non-inverting output terminal VOUTP is connected to one end of the switch S16 and the other end of the switch S17, the input common-mode voltage signal VCMI is connected to the other end of the switch S11 and the other end of the switch S12, and the output common-mode voltage signal VCMO is connected to one end of the switch S13 and one end of the switch S14;

[0031] The right plate of the adjustable capacitor C5 is connected to the other end of the switch S15 and the other end of the switch S13, and the right plate of the adjustable capacitor C6 is connected to the other end of the switch S16 and the other end of the switch S14;

[0032] The positive-phase output terminal VOUTP and the negative-phase output terminal VOUTN of the fully differential operational amplifier OP-AMP are used to output bipolar voltage signals.

[0033] Furthermore, the capacitor C3, the capacitor C4, the capacitor C5 and the capacitor C6 are programmable capacitors.

[0034] Furthermore, the capacitance value of the capacitor C3 is equal to the capacitance value of the capacitor C4;

[0035] The capacitance value of the capacitor C5 is equal to the capacitance value of the capacitor C6.

[0036] Furthermore, the external input reference voltage signal VREF is adjustable.

[0037] Furthermore, the operation timing of the switches S1 to S17 is as follows:

[0038] At time t0: the switches S2 and S3 of all branches are closed, and the remaining switches are turned off to reset the column buffer circuit.

[0039] At time t1: the switches S1, S4, and S6 of all branches are closed, and the remaining switches are turned off to sample the pixel light-generated signal.

[0040] At time t2: the switches S2 and S3 of all branches are closed, and the remaining switches are turned off to reset the column buffer circuit.

[0041] At time t3: the switches S1, S5, and S7 of all branches are closed, and the remaining switches are turned off to sample the pixel reset signal.

[0042] At time t4-1: switches S11, S12, S13, S14, and S17 are closed, and the remaining switches are turned off to reset the holding and amplification circuits.

[0043] At t5-1: the switches S8, S9, S10, S15, and S16 of branch 1 are closed, and the remaining switches are turned off to read the sampled signal.

[0044] At t4-2: the switches S11, S12, S13, S14, and S17 are closed, and the remaining switches are turned off to reset the holding and amplifying circuits.

[0045] At t5-2: the switches S8, S9, S10, S15, and S16 of branch 2 are closed, and the remaining switches are turned off to read the sampled signal.

[0046] …

[0047] At time t4-m: switches S11, S12, S13, S14, and S17 are closed, and the remaining switches are turned off to reset the holding and amplification circuits.

[0048] At time t5-m: the switches S8, S9, S10, S15 and S16 of branch m are closed, and the remaining switches are turned off to read the sampling signal.

[0049] A high-speed column readout method for a CMOS image sensor is based on the above-mentioned high-speed column readout circuit for a CMOS image sensor and has the following features:

[0050] Step 1: Adjust the states of m column buffer circuits and reset them;

[0051] Step 2: Turn on the row selection transistor ROW_SEL in the pixel circuit, and adjust the states of the m column buffer circuits to be in an amplification state, and sample the light-generated signal Vsig of the pixel circuit;

[0052] Step 3: Reset the floating diffusion point capacitor CFD of the pixel circuit, adjust the states of the m column buffer circuits, and reset the m column buffer circuits again;

[0053] Step 4: Adjust the states of the m column buffer circuits to be in an amplifying state, and sample the reset signal Vrst of the pixel circuit;

[0054] Step 5: Adjust the state of the holding and amplifying circuits and reset them;

[0055] Step 6: Select branch 1 through the multiplexer, adjust the state of the correlated double sampling circuit of the branch, and adjust the state of the holding and amplification circuit to complete the reading of the photogenerated signal and reset signal of branch 1;

[0056] Step 7: Reset the holding and amplifying circuit, select the next branch through the multiplexer, and return to step 6 until the reading of the photogenerated signals and reset signals of the m branches is completed, thereby realizing a single column readout of the sampling signal of the CMOS image sensor.

[0057] Compared with the prior art, the present invention has the following beneficial technical effects:

[0058] 1. The present invention solves the problem of weak driving capability of the source follower of the pixel circuit by adding a column buffer circuit module between the pixel circuit and the correlated double sampling circuit, thereby further improving the signal readout speed and being applicable to high frame rate CMOS image sensors;

[0059] 2. The present invention adopts a holding and amplifying circuit to realize the output of a double-terminal bipolar voltage signal;

[0060] 3. The correlated double sampling circuit and the holding and amplifying circuit combination in the present invention all use amplifiers with adjustable gain, and the output voltage range of the column readout circuit can be externally adjusted by adjusting the amplification factor;

[0061] 4. In the present invention, the ratio of the number of column buffer circuits, correlated double sampling circuits, and holding and amplifying circuits is m:m:1, where m is greater than or equal to 1. This makes it applicable to analog-to-digital converter circuits with various input ranges and sizes, thereby increasing the application flexibility of the column readout circuit.

[0062] 5. The correlated double sampling circuit and the holding and amplifying circuit of the present invention can cooperate to implement a programmable gain amplification function for the read voltage signal. Compared with the traditional design in which the correlated double sampling circuit and the programmable gain amplifying circuit are separated, at least two capacitors can be reduced, thereby simplifying the area of the column readout circuit.

[0063] 6. The external input reference voltage signal VREF in the present invention is adjustable, and by adjusting the capacitance values of the adjustable capacitors C3, C4, C5 and C6, the adjustment range of the output voltage of the column readout circuit is further increased. BRIEF DESCRIPTION OF THE DRAWINGS

[0064] Figure 1 Schematic diagram of the high-speed column readout circuit structure for CMOS image sensors according to the present invention;

[0065] Figure 2 The figure is a schematic diagram of the working timing of the high-speed column readout circuit for CMOS image sensors according to the present invention. DETAILED DESCRIPTION

[0066] To make the objects, advantages and features of the present invention more clear, a high-speed column readout circuit for a CMOS image sensor proposed by the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0067] A high-speed column readout circuit for a CMOS image sensor, such as Figure 1 As shown, the system includes m branches for buffering and sampling, holding and amplifying circuits, and a multiplexer. m is an integer greater than or equal to 1. The branches include column buffer circuits and correlated double sampling circuits. The value of m can be adjusted based on the frame frequency requirements of the CMOS image sensor and the size parameters of the analog-to-digital converter.

[0068] The input ends of m column buffer circuits are all connected to the output ends of the pixel circuits, and are used to buffer and amplify the pixel circuit's photogenerated signals and reset signals, thereby improving the pixel signal reading speed. The column buffer circuits include a single-ended amplifier AMP, three switches S1 to S3, and two fixed capacitors C1 and C2. One end of each of the m switches S1 is connected to the output end of the pixel circuit, and the other end of switch S1 is respectively connected to the left plate of fixed capacitor C1 and one end of switch S2. The right plate of fixed capacitor C1 is connected to the input end of the single-ended amplifier AMP, the left plate of fixed capacitor C2, and one end of switch S3. The other end of switch S2, the output end of the single-ended amplifier AMP, and the right plate of fixed capacitor C2 are connected to the other end of switch S3. The column buffer circuit has two operating states: when S2 and S3 are closed and S1 is closed, the circuit is in a reset state; when S2 and S3 are closed and S1 is closed, the circuit is in an amplification state.

[0069] m correlated double sampling circuits respectively sample the photogenerated signals and reset signals output by m column buffer circuits, and achieve subtraction of the photogenerated signals and reset signals through charge sharing to eliminate fixed-mode noise in the pixel circuit. The circuits include seven switches S4 to S10 and two programmable capacitors C3 and C4. The output ends of the m single-ended amplifiers AMP are connected to one end of the m switches S4 and one end of the m switches S5; the other end of the switch S4 is connected to one end of the switch S8 and the left plate of the adjustable capacitor C3; the right plate of the adjustable capacitor C3 is connected to one end of the switch S6 and one end of the switch S9, and the other end of the switch S6 is connected to an external input reference voltage signal VREF; the other end of the switch S5 is connected to the other end of the switch S8 and the left plate of the adjustable capacitor C4; the right plate of the adjustable capacitor C4 is connected to one end of the switch S7 and one end of the switch S10, and the other end of the switch S7 is grounded.

[0070] The multiplexer includes three multiplexers with m outputs, and the m outputs of the three multiplexers are respectively connected to switches S8, S9, and S10 of the correlated double sampling circuits in the m branches, so as to respectively control the closing and closing of switches S8, S9, and S10 in the m correlated double sampling circuit branches, and read out the signals of the correlated double sampling circuits in the m branches to the holding and amplification circuits in a time-sharing manner.

[0071] The holding and amplification circuit is used to hold and amplify the signals sampled and output by m related dual circuits. It uses an amplifier with adjustable gain to convert the single-ended unipolar voltage signal into a two-ended bipolar voltage signal and output it. It includes a fully differential operational amplifier OP-AMP, seven switches S11 to S17, and two programmable capacitors C5 and C6. The non-inverting input terminal of the fully differential operational amplifier OP-AMP is connected to one end of switch S11, the other end of m switches S9 in the correlated double sampling circuit, and the left plate of the programmable capacitor C5. The inverting input terminal is connected to one end of switch S12, the other end of m switches S10 in the correlated double sampling circuit, and the left plate of the programmable capacitor C6. The inverting output terminal VOUTN is connected to one end of switch S15 and one end of switch S17. The non-inverting output terminal VOUTP is connected to one end of switch S16 and the other end of switch S17. The input common-mode voltage signal VCMI is connected to the other end of switch S11 and switch S12, and the output common-mode voltage signal VCMO is connected to one end of switch S13 and switch S14. The right plate of the programmable capacitor C5 is connected to the other end of switch S15 and the other end of switch S13. The right plate of the programmable capacitor C6 is connected to the other end of switch S16 and the other end of switch S14.

[0072] The high-speed column readout circuit provided by the present invention has two-stage amplification functions. The first stage is the amplification function of the column buffer circuit. Changing the ratio of fixed capacitors C2 and C1 can achieve different amplification factors. Once designed, this amplification factor cannot be changed externally. The correlated double sampling circuit and the hold and amplify circuit combine to form a programmable gain amplifier, which implements the second stage of amplification of the column readout circuit. The ratio of programmable capacitors C5 and C6 to programmable capacitors C3 and C4 can be changed through external control, thereby changing the amplification factor of the column readout circuit. An external input reference voltage VREF can change the output range of the column readout circuit. In combination with the programmable gain amplification function of the correlated double sampling circuit and the hold and amplify circuit, the output range of the column readout circuit can be flexibly adjusted according to the input signal range requirements of the analog-to-digital converter.

[0073] like Figure 2 FIG. 1 is a schematic diagram showing the operation timing of switches S1 to S17 of a high-speed column readout circuit when multiple column buffer circuits and a correlated double sampling circuit are provided. The operation timing of switches S1 to S17 is as follows:

[0074] At time t0: the switches S2 and S3 of all branches are closed, and the remaining switches are turned off to reset the column buffer circuit.

[0075] At time t1: the switches S1, S4, and S6 of all branches are closed, and the remaining switches are turned off to sample the pixel light-generated signal.

[0076] At time t2: the switches S2 and S3 of all branches are closed, and the remaining switches are turned off to reset the column buffer circuit.

[0077] At time t3: the switches S1, S5, and S7 of all branches are closed, and the remaining switches are turned off to sample the pixel reset signal.

[0078] At time t4-1: switches S11, S12, S13, S14, and S17 are closed, and the remaining switches are turned off to reset the holding and amplification circuits.

[0079] At t5-1: the switches S8, S9, S10, S15, and S16 of branch 1 are closed, and the remaining switches are turned off to read the sampled signal.

[0080] At t4-2: the switches S11, S12, S13, S14, and S17 are closed, and the remaining switches are turned off to reset the holding and amplifying circuits.

[0081] At t5-2: the switches S8, S9, S10, S15, and S16 of branch 2 are closed, and the remaining switches are turned off to read the sampled signal.

[0082] …

[0083] At time t4-m: switches S11, S12, S13, S14, and S17 are closed, and the remaining switches are turned off to reset the holding and amplification circuits.

[0084] At time t5-m: the switches S8, S9, S10, S15 and S16 of branch m are closed, and the remaining switches are turned off to read the sampling signal.

[0085] Here's how it works:

[0086] After exposure is completed, the pixel circuit transfers the photogenerated charge to the floating diffusion point capacitor CFD. Before reading the CFD voltage signal, the column buffer circuit is reset. That is, at time t0, switches S2 and S3 are closed at the same time, and the other switches are turned off. The column buffer circuit is in a reset state. At this time, the input and output terminals of the single-ended amplifier AMP are short-circuited, and its input voltage and output voltage are equal to the common-mode voltage Vo of the single-ended amplifier AMP.

[0087] At time t1, the row select transistor ROW_SEL in the pixel circuit is turned on, and switches S1, S4, and S6 are closed. Switches S2 and S3 are turned off. The right plate of capacitor C3 is connected to the external input reference voltage VREF, and the pixel signal Vsig is sampled onto the left plate of capacitor C3. The voltage VC3L on the left plate of capacitor C3 is calculated by the following formula:

[0088] VC3L=Vo-(Vsig-Vo)*C2 / C1

[0089] Wherein, Vsig is a pixel signal, C1 is a capacitance value of capacitor C1, and C2 is a capacitance value of capacitor C2.

[0090] At time t2, the floating diffusion point capacitor CFD of the pixel circuit is reset, and at the same time, switches S2 and S3 are closed, and the remaining switches are turned off, and the column buffer circuit is reset again. The input and output voltages of the single-ended amplifier AMP are Vo.

[0091] After the floating diffusion capacitor CFD and the column buffer circuit are reset, at time t3, switches S1, S5, and S7 are closed, and switches S2 and S3 are turned off. The right plate of capacitor C4 is grounded, and the reset signal Vrst of the floating diffusion capacitor is sampled onto the left plate of capacitor C4. The left plate voltage VC4L of capacitor C4 is calculated using the following formula:

[0092] VC4L=Vo-(Vrst-Vo)*C2 / C1.

[0093] The above operations complete the sampling of the pixel signal and the reset signal. After that, the sampled pixel signal and the reset signal need to be subtracted, amplified, and converted into a double-ended differential signal for output.

[0094] When the ratio of the number of column buffer circuits, correlated double sampling circuits and holding and amplifying circuits is m:m:1, the sampling signals of the m branches are output to the holding and amplifying circuits respectively through the multiplexer.

[0095] For the first branch, at time t4_1, switches S11, S12, S13, S14, and S17 of the holding and amplifying circuit are closed, and the remaining switches are turned off, so that the left plates of capacitors C5 and C6 are connected to the input common-mode voltage signal VCMI of the fully differential operational amplifier OP-AMP, and the right plates of capacitors C5 and C6 are connected to the output common-mode voltage signal VCMO of the fully differential operational amplifier OP-AMP;

[0096] At time t5_1, switches S8, S9, and S10 of branch 1 and S15 and S16 of the holding and amplification circuit are closed, and the remaining switches are turned off. The left plates of capacitors C3 and C4 are short-circuited to achieve charge sharing, while the right plates of capacitors C3 and C4 are connected to the non-inverting input and inverting input of the fully differential operational amplifier OP-AMP, respectively. Ideally, the voltage on the right plates of capacitors C3 and C4 is equal to the voltage of the input common-mode voltage signal VCMI of the fully differential operational amplifier OP-AMP. Therefore, the voltage signal change on the left plates of capacitors C3 and C4 will be transferred to the right plates of capacitors C5 and C6, as well as the inverting output and non-inverting output of the fully differential operational amplifier OP-AMP. Generally, the capacitor values are set to C3 = C4 and C5 = C6. At this time, the differential relationship of the output voltage is:

[0097]

[0098] Among them, VOUTP is the positive output terminal voltage, VOUTN is the negative output terminal voltage, VC4L is the left plate voltage of capacitor C4, VC3L is the left plate voltage of capacitor C3, VREF is the external input reference voltage, Vsig is the pixel signal, Vrst is the floating diffusion point capacitor reset signal, C1, C2, C3, and C5 are the capacitance values of capacitors C1, C2, C3, and C5 respectively.

[0099] As can be seen from the above formula, the read range of the column readout circuit can be controlled by VREF, C3 / C5, and C2 / C1, where VREF and C3 / C5 can be adjusted by external input, making the output range of the high-speed column readout circuit of the present invention flexible and adjustable.

[0100] After completing the reading of the sampling signal of branch 1, the reading of the sampling signals of m branches is completed one by one in a similar manner.

[0101] This embodiment further provides a high-speed column readout method for a CMOS image sensor, based on the above-mentioned high-speed column readout circuit for a CMOS image sensor, comprising the following steps:

[0102] Step 1: Close switches S2 and S3 simultaneously, and turn off the other switches, so that the input and output terminals of the single-ended amplifier AMP are short-circuited. The input voltage and output voltage of the single-ended amplifier AMP are equal to the common-mode voltage Vo of the single-ended amplifier AMP, and the column buffer circuit is reset.

[0103] Step 2: Turn on the row selection transistor ROW_SEL in the pixel circuit, and simultaneously close switches S1, S4, and S6, and turn off switches S2 and S3. The right plate of the adjustable capacitor C3 is connected to the external input reference voltage VREF, so that the column buffer circuit is in an amplifying state, and the photogenerated signal Vsig of the pixel circuit is sampled onto the left plate of the adjustable capacitor C3.

[0104] Step 3: Reset the floating diffusion point capacitor CFD of the pixel circuit, close switches S2 and S3 at the same time, turn off the remaining switches, and reset the column buffer circuit again;

[0105] Step 4: Close switches S1, S5, and S7, and turn off switches S2 and S3. The right plate of capacitor C4 is grounded, so that the column buffer circuit is in an amplifying state, and the reset signal Vrst of the pixel circuit is sampled to the left plate of adjustable capacitor C4.

[0106] Step 5: Close switches S11, S12, S13, S14, and S17 of the holding and amplifying circuit, and turn off the remaining switches, so that the left plate of the adjustable capacitor C5 and the left plate of the adjustable capacitor C6 are connected to the input common-mode voltage signal VCMI of the fully differential operational amplifier OP-AMP, and the right plate of the adjustable capacitor C5 and the right plate of the adjustable capacitor C6 are connected to the output common-mode voltage signal VCMO of the fully differential operational amplifier OP-AMP, thereby resetting the holding and amplifying circuit;

[0107] Step 6: Select branch 1 through the multiplexer, close switches S8, S9, and S10 of branch 1 and switches S15 and S16 of the holding and amplification circuit, and turn off the remaining switches. The left plate of the adjustable capacitor C3 and the left plate of the adjustable capacitor C4 are short-circuited to achieve charge sharing. The right plate of the adjustable capacitor C3 and the right plate of the adjustable capacitor C4 are respectively connected to the non-inverting input terminal VOUTP and the inverting input terminal VOUTN of the fully differential operational amplifier OP-AMP. The photogenerated signal Vsig on the left plate of the adjustable capacitor C3 and the reset signal Vrst on the left plate of the adjustable capacitor C4 are transferred to the right plate of the adjustable capacitor C5 and the right plate of the adjustable capacitor C6, as well as the inverting output terminal VOUTN and the non-inverting output terminal VOUTP of the fully differential operational amplifier OP-AMP, thereby completing the reading of the photogenerated signal and reset signal of branch 1;

[0108] Step 7: Reset the holding and amplifying circuit, select the next branch through the multiplexer, and return to step 6 until the reading of the photogenerated signals and reset signals of the m branches is completed, thereby realizing a single column readout of the sampling signal of the CMOS image sensor.

[0109] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the present invention.

Claims

1. A high-speed column readout circuit for a CMOS image sensor, characterized in that: The method comprises m branches for buffering sampling, a holding and amplifying circuit, and a multiplexer, where m is an integer greater than or equal to 1; The branch includes a column buffer circuit and a correlated double sampling circuit; The input ends of the m column buffer circuits are all connected to the output ends of the pixel circuit, and are used to buffer and amplify the photogenerated signal and reset signal of the pixel circuit to improve the pixel signal reading speed; the output ends of the m column buffer circuits are respectively connected to the data input ends of the m correlated double sampling circuits; m correlated double sampling circuits respectively sample the photogenerated signals and reset signals output by the m column buffer circuits, and subtract the photogenerated signals from the reset signals through charge sharing to eliminate the fixed-mode noise of the pixel circuit; the m correlated double sampling circuits use amplifiers with adjustable gains, and their outputs are connected to the inputs of the holding and amplification circuits; The output end of the multiplexer is connected to the control input end of m correlated double sampling circuits respectively, and is used to control the correlated double sampling circuits in the m branches and read out the sampled signals to the holding and amplifying circuit in a time-sharing manner; The holding and amplifying circuit is used to hold and amplify the signals sampled and output by m related dual circuits, and uses an amplifier with adjustable gain to convert the single-ended unipolar voltage signal into a double-ended bipolar voltage signal and output it; The column buffer circuit includes a single-ended amplifier AMP, three switches S1 to S3, and two capacitors C1 and C2; One end of each of the m switches S1 is connected to the output end of the pixel circuit, and the other end of the switch S1 is connected to the left plate of the capacitor C1 and one end of the switch S2 respectively; The right plate of capacitor C1 is connected to the input terminal of the single-ended amplifier AMP, the left plate of capacitor C2 and one end of switch S3; The output end of the single-ended amplifier AMP is connected to the right plate of the capacitor C2, the other end of the switch S3, and the other end of the switch S2; the output end of the single-ended amplifier AMP is connected to the input end of the correlated double sampling circuit of the corresponding branch; The correlated double sampling circuit includes seven switches S4 to S10 and two adjustable capacitors C3 and C4; One end of the switch S4 and one end of the switch S5 are both connected to the output end of the single-ended amplifier AMP of the column buffer circuit in the corresponding branch; The other end of the switch S4 is connected to one end of the switch S8 and the left plate of the adjustable capacitor C3; the right plate of the adjustable capacitor C3 is connected to one end of the switch S6 and one end of the switch S9, and the other end of the switch S6 is connected to the external input reference voltage signal VREF; The other end of the switch S5 is connected to the other end of the switch S8 and the left plate of the adjustable capacitor C4; the right plate of the adjustable capacitor C4 is connected to one end of the switch S7 and one end of the switch S10, and the other end of the switch S7 is grounded; The other ends of the m switches S9 are connected to one input end of the holding and amplifying circuit, and the other ends of the m switches S10 are connected to the other input end of the holding and amplifying circuit; The multiplexer includes three selectors with m outputs; The m outputs of the three selectors are respectively connected to the switches S8, S9, and S10 of the correlated double sampling circuits in the m branches, and are used to respectively control the closing and closing of the switches S8, S9, and S10 in the m correlated double sampling circuit branches, and read out the signals of the correlated double sampling circuits in the m branches to the holding and amplification circuits in a time-sharing manner.

2. The high-speed column readout circuit for a CMOS image sensor according to claim 1, wherein: The holding and amplifying circuit includes a fully differential operational amplifier OP-AMP, seven switches S11 to S17, and two adjustable capacitors C5 and C6; One end of the switch S11 is connected to the other ends of the m switches S9, and is also connected to the non-inverting input of the fully differential operational amplifier OP-AMP and the left plate of the adjustable capacitor C5; One end of the switch S12 is connected to the other ends of the m switches S10, and is also connected to the inverting input of the fully differential operational amplifier OP-AMP and the left plate of the adjustable capacitor C6; The inverting output terminal VOUTN of the fully differential operational amplifier OP-AMP is connected to one end of the switch S15 and one end of the switch S17, the non-inverting output terminal VOUTP is connected to one end of the switch S16 and the other end of the switch S17, the input common-mode voltage signal VCMI is connected to the other end of the switch S11 and the other end of the switch S12, and the output common-mode voltage signal VCMO is connected to one end of the switch S13 and one end of the switch S14; The right plate of the adjustable capacitor C5 is connected to the other end of the switch S15 and the other end of the switch S13, and the right plate of the adjustable capacitor C6 is connected to the other end of the switch S16 and the other end of the switch S14; The positive-phase output terminal VOUTP and the negative-phase output terminal VOUTN of the fully differential operational amplifier OP-AMP are used to output bipolar voltage signals.

3. The high-speed column readout circuit for a CMOS image sensor according to claim 2, wherein: The capacitor C3 , capacitor C4 , capacitor C5 and capacitor C6 are programmable capacitors.

4. The high-speed column readout circuit for a CMOS image sensor according to claim 3, wherein: The capacitance value of the capacitor C3 is equal to the capacitance value of the capacitor C4; The capacitance value of the capacitor C5 is equal to the capacitance value of the capacitor C6.

5. The high-speed column readout circuit for a CMOS image sensor according to claim 4, wherein: The external input reference voltage signal VREF is adjustable.

6. The high-speed column readout circuit for a CMOS image sensor according to claim 5, wherein: The operation timing of the switches S1 to S17 is as follows: At time t0: the switches S2 and S3 of all branches are closed, and the remaining switches are turned off to reset the column buffer circuit. At time t1: the switches S1, S4, and S6 of all branches are closed, and the remaining switches are turned off to sample the pixel light-generated signal. At time t2: the switches S2 and S3 of all branches are closed, and the remaining switches are turned off to reset the column buffer circuit. At time t3: the switches S1, S5, and S7 of all branches are closed, and the remaining switches are turned off to sample the pixel reset signal. At time t4-1: switches S11, S12, S13, S14, and S17 are closed, and the remaining switches are turned off to reset the holding and amplification circuits. At t5-1: the switches S8, S9, S10, S15, and S16 of branch 1 are closed, and the remaining switches are turned off to read the sampled signal. At t4-2: the switches S11, S12, S13, S14, and S17 are closed, and the remaining switches are turned off to reset the holding and amplifying circuits. At t5-2: the switches S8, S9, S10, S15, and S16 of branch 2 are closed, and the remaining switches are turned off to read the sampled signal. At time t4-m: switches S11, S12, S13, S14, and S17 are closed, and the remaining switches are turned off to reset the holding and amplification circuits. At time t5-m: the switches S8, S9, S10, S15 and S16 of branch m are closed, and the remaining switches are turned off to read the sampling signal.

7. A high-speed column readout method for a CMOS image sensor, based on the high-speed column readout circuit for a CMOS image sensor according to any one of claims 1 to 6, characterized in that: The following steps are involved: Step 1: Adjust the states of m column buffer circuits and reset them; Step 2: Turn on the row selection transistor ROW_SEL in the pixel circuit, and adjust the states of the m column buffer circuits to be in an amplification state, and sample the light-generated signal Vsig of the pixel circuit; Step 3: Reset the floating diffusion point capacitor CFD of the pixel circuit, adjust the states of the m column buffer circuits, and reset the m column buffer circuits again; Step 4: Adjust the states of the m column buffer circuits to be in an amplifying state, and sample the reset signal Vrst of the pixel circuit; Step 5: Adjust the state of the holding and amplifying circuits and reset them; Step 6: Select branch 1 through the multiplexer, adjust the state of the correlated double sampling circuit of the branch, and adjust the state of the holding and amplification circuit to complete the reading of the photogenerated signal and reset signal of branch 1; Step 7: Reset the holding and amplifying circuit, select the next branch through the multiplexer, and return to step 6 until the reading of the photogenerated signals and reset signals of the m branches is completed, thereby realizing a single column readout of the sampling signal of the CMOS image sensor.

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