Multiple antenna path-based signal transmission device and method in wireless communication system

Abstract

The present disclosure relates to a 5G or 6G communication system for supporting a higher data transmission rate. A method performed by a radio unit (RU) in a wireless communication system, according to various embodiments of the present disclosure, may comprise the steps of: performing an inverse fast Fourier transform (IFFT) shift for frequency domain (FD) downlink (DL) symbol data; rearranging, in reverse order, IFFT points of the FD DL symbol data for which the IFFT shift has been performed; performing IFFT based on FD DL symbol data units of multiple antenna paths in order to convert the FD DL symbol data, for which the IFFT shift and the rearrangement have been performed, into time domain (TD) DL symbol data; applying cyclic delay diversity (CDD) to the TD DL symbol data; adding a cyclic prefix (CP) to the CDD-applied TD DL symbol data; and transmitting a signal generated on the basis of the TD DL symbol data for which the CDD application and the CP addition have been performed.

Description

Device and method for transmitting signals based on multiple antenna paths in a wireless communication system

[0001] The present disclosure relates generally to wireless communication systems, and more particularly to devices and methods for transmitting signals based on multiple antenna paths in a wireless communication system.

[0002] 5G mobile communication technology defines a wide frequency band to enable fast transmission speeds and new services, and can be implemented not only in the sub-6GHz frequency band such as 3.5 gigahertz (3.5GHz), but also in the ultra-high frequency band called millimeter wave (mmWave) such as 28GHz and 39GHz ('Above 6GHz'). In addition, for 6G mobile communication technology, which is called the system after 5G communication (Beyond 5G), implementation in the terahertz (THz) band (for example, 3 THz band at 95GHz) is being considered to achieve a transmission speed that is 50 times faster than 5G mobile communication technology and an ultra-low latency time that is reduced to one-tenth.

[0003] In the early stages of 5G mobile communication technology, the goal is to support services and satisfy performance requirements for enhanced Mobile Broadband (eMBB), Ultra-Reliable Low-Latency Communications (URLLC), and massive Machine-Type Communications (mMTC). These include beamforming and massive MIMO to mitigate path loss of radio waves in ultra-high frequency bands and increase the transmission distance of radio waves, support for various numerologies (such as operation of multiple subcarrier intervals) and dynamic operation of slot formats for efficient use of ultra-high frequency resources, initial access technology to support multi-beam transmission and wideband, definition and operation of BWP (Bidth Part), new channel coding methods such as LDPC (Low Density Parity Check) codes for large-capacity data transmission and Polar Code for reliable transmission of control information, and L2 pre-processing (L2). Standardization has been made for network slicing, which provides dedicated networks specialized for specific services, and pre-processing.

[0004] Currently, discussions are underway to improve and enhance the initial 5G mobile communication technology in consideration of the services that 5G mobile communication technology was intended to support, and physical layer standardization is in progress for technologies such as V2X (Vehicle-to-Everything) to help autonomous vehicles make driving decisions and increase user convenience based on their own location and status information transmitted by vehicles, NR-U (New Radio Unlicensed) for the purpose of system operation that complies with various regulatory requirements in unlicensed bands, NR terminal low power consumption technology (UE Power Saving), Non-Terrestrial Network (NTN), which is direct terminal-satellite communication to secure coverage in areas where communication with terrestrial networks is impossible, and Positioning.

[0005] In addition, standardization of wireless interface architecture / protocols is in progress for technologies such as intelligent factories (Industrial Internet of Things, IIoT) to support new services through linkage and convergence with other industries, Integrated Access and Backhaul (IAB) that provides nodes for expanding network service areas by integrating wireless backhaul links and access links, Mobility Enhancement technology including Conditional Handover and Dual Active Protocol Stack (DAPS) handover, and 2-step random access (2-step RACH for NR) that simplifies random access procedures. Standardization is also in progress for system architecture / services such as 5G baseline architecture (e.g., Service-based Architecture, Service-based Interface) for grafting Network Functions Virtualization (NFV) and Software-Defined Networking (SDN) technologies, and Mobile Edge Computing (MEC) that provides services based on the location of the terminal.

[0006] Once these 5G mobile communication systems are commercialized, an explosive increase in connected devices will be connected to the communication network, necessitating enhanced functionality and performance of 5G mobile communication systems and integrated operation of these connected devices. To this end, new research will be conducted on improving 5G performance and reducing complexity, supporting AI services, supporting metaverse services, and drone communications by utilizing eXtended Reality (XR), Artificial Intelligence (AI), and Machine Learning (ML) to efficiently support Augmented Reality (AR), Virtual Reality (VR), and Mixed Reality (MR).

[0007] In addition, the development of these 5G mobile communication systems includes new waveforms to ensure coverage in the terahertz band of 6G mobile communication technology, multi-antenna transmission technologies such as Full Dimensional MIMO (FD-MIMO), Array Antenna, and Large Scale Antenna, metamaterial-based lenses and antennas to improve the coverage of terahertz band signals, high-dimensional spatial multiplexing technology using Orbital Angular Momentum (OAM), Reconfigurable Intelligent Surface (RIS) technology, as well as full duplex technology to improve the frequency efficiency and system network of 6G mobile communication technology, satellite, AI (Artificial Intelligence) from the design stage and AI-based communication technology that realizes system optimization by internalizing end-to-end AI support functions, and ultra-high-performance communication and computing resources to provide services with complexity that exceeds the limits of terminal computing capabilities. It can serve as a basis for the development of next-generation distributed computing technologies that can be realized by utilizing them.

[0008] As transmission capacity increases in wireless communication systems, functional splitting, which separates base stations functionally, is being implemented. This functional splitting allows base stations to be divided into digital units (DUs) and radio units (RUs). A fronthaul for communication between the DUs and RUs is defined, and architectures and technologies supporting beamforming for fronthaul transmission are required.

[0009] Based on the discussion as described above, the present disclosure provides a method and apparatus for transmitting a signal based on multiple antenna paths performed in an RU.

[0010] In addition, the present disclosure provides a method and apparatus for effectively optimizing memory for performing IFFT based on multiple antenna paths in a wireless communication system.

[0011] According to various embodiments of the present disclosure, in a wireless communication system, a method performed by a radio unit (RU) comprises the steps of: performing an inverse fast Fourier transform (IFFT) shift on frequency domain (FD) downlink (DL) symbol data; rearranging IFFT points of the FD DL symbol data on which the IFFT shift has been performed in reverse order; performing an IFFT based on FD DL symbol data units of multiple antenna paths to convert the FD DL symbol data on which the IFFT shift and the rearrangement have been performed into time domain (TD) DL symbol data; applying CDD (Cyclic Delay Diversity) to the TD DL symbol data; adding a CP (Cyclic Prefix) to the TD DL symbol data to which the CDD has been applied; And it may include a step of transmitting a signal generated based on the TD DL symbol data on which the CDD application and CP insertion are performed.

[0012] According to various embodiments of the present disclosure, a radio unit (RU) includes a transceiver, and a controller coupled to the transceiver, wherein the controller performs an inverse fast Fourier transform (IFFT) shift on frequency domain (FD) downlink (DL) symbol data, a step of rearranging IFFT points of the FD DL symbol data on which the IFFT shift has been performed in reverse order, a step of performing an IFFT based on FD DL symbol data units of multiple antenna paths to convert the FD DL symbol data on which the IFFT shift and the rearrangement have been performed into time domain (TD) DL symbol data, a step of applying CDD (Cyclic Delay Diversity) to the TD DL symbol data, and a step of applying CDD to the TD DL symbol data to which the CDD has been applied. It may be configured to perform a step of inserting a CP (Cyclic Prefix), and a step of transmitting a signal generated based on the TD DL symbol data on which the CDD application and CP insertion are performed.

[0013] Methods and devices according to various embodiments of the present disclosure enable optimization of the usage of time domain DL symbol memory.

[0014] The effects that can be obtained from the present disclosure are not limited to the effects mentioned above, and other effects that are not mentioned can be clearly understood by a person having ordinary skill in the art to which the present disclosure belongs from the description below.

[0015] FIG. 1A illustrates a wireless communication system according to various embodiments of the present disclosure.

[0016] FIG. 1b illustrates an example of a fronthaul structure according to functional split of a base station according to various embodiments of the present disclosure.

[0017] FIG. 2 illustrates the configuration of a distributed unit (DU) according to various embodiments of the present disclosure.

[0018] FIG. 3 illustrates the configuration of a radio unit (RU) according to various embodiments of the present disclosure.

[0019] FIG. 4 illustrates an example of function split according to various embodiments of the present disclosure.

[0020] FIG. 5 illustrates an example of a connection between a DU and a RU according to various embodiments of the present disclosure.

[0021] FIG. 6 illustrates the structure of a downlink chain block of an RU according to various embodiments of the present disclosure.

[0022] FIG. 7 illustrates an example of a frequency spectrum for an inverse fast Fourier transform (IFFT) according to various embodiments of the present disclosure.

[0023] FIG. 8 is a diagram showing an example of the logical structure of 2-DFT according to various embodiments of the present disclosure.

[0024] FIG. 9 is a diagram showing an example of a hardware structure of a 2-DFT and an operation timing diagram according to various embodiments of the present disclosure.

[0025] FIG. 10 illustrates an example of timing for a path multiplexer (MUX) in various embodiments of the present disclosure.

[0026] FIG. 11 illustrates the structure of a downlink chain block of an RU according to various embodiments of the present disclosure.

[0027] FIG. 12 is a diagram showing an example of a read operation of a DL memory according to various embodiments of the present disclosure.

[0028] FIG. 13 is a diagram illustrating an LPHY-DL structure according to various embodiments of the present disclosure.

[0029] FIG. 14 is a timing diagram showing an example of timing of operations according to various embodiments of the present disclosure.

[0030] FIG. 15 is a diagram illustrating an example of a DLFD memory according to various embodiments of the present disclosure.

[0031] FIG. 16 is a diagram illustrating an example of an operation of changing a bit natural order to a bit inversion order according to various embodiments of the present disclosure.

[0032] FIG. 17 is a diagram showing an example of a hardware structure of a 2-DFT and an operation timing diagram according to various embodiments of the present disclosure.

[0033] FIG. 18 is a diagram showing an example of a hardware structure of a 4-DFT and an operation timing diagram according to various embodiments of the present disclosure.

[0034] FIG. 19 is a diagram showing an example of an N-point DIT IFFT structure according to various embodiments of the present disclosure.

[0035] FIG. 20 is a diagram showing an example of an N-point DIT IFFT structure according to various embodiments of the present disclosure.

[0036] FIG. 21 is a diagram showing an example of an N-point DIT IFFT structure according to various embodiments of the present disclosure.

[0037] FIG. 22 is a timing diagram showing the operation timing of an N-point DIT IFFT structure according to various embodiments of the present disclosure.

[0038] FIG. 23 and FIG. 24 are timing diagrams showing an example of the internal operation of a DLTD memory according to various embodiments of the present disclosure.

[0039] FIG. 25 is a diagram illustrating an example of a DLTD memory according to various embodiments of the present disclosure.

[0040] FIG. 26 and FIG. 27 are timing diagrams showing an example of the internal operation of a DLTD memory according to various embodiments of the present disclosure.

[0041] FIG. 28 is a diagram illustrating an example of a DLTD memory according to various embodiments of the present disclosure.

[0042] FIG. 29 is a timing diagram illustrating an example of the internal operation of a DLTD memory according to various embodiments of the present disclosure.

[0043] FIG. 30 is a flowchart illustrating an example of a method performed in an RU according to various embodiments of the present disclosure.

[0044] The terms used in this disclosure are used only to describe specific embodiments and may not be intended to limit the scope of other embodiments. The singular expression may include plural expressions unless the context clearly indicates otherwise. Terms used herein, including technical or scientific terms, may have the same meaning as commonly understood by those of ordinary skill in the art described in this disclosure. Terms defined in general dictionaries among the terms used in this disclosure may be interpreted as having the same or similar meaning in the context of the relevant technology, and shall not be interpreted in an idealized or overly formal sense unless explicitly defined in this disclosure. In some cases, even if a term is defined in this disclosure, it cannot be interpreted to exclude embodiments of the present disclosure.

[0045] The various embodiments of the present disclosure described below illustrate a hardware-based approach as an example. However, since the various embodiments of the present disclosure include techniques utilizing both hardware and software, the various embodiments of the present disclosure do not exclude a software-based approach.

[0046] In the following description, terms referring to signals (e.g., message, information, preamble, signal, signaling, sequence, stream), terms referring to resources (e.g., symbol, slot, subframe, radio frame, subcarrier, RE (resource element), RB (resource block), PRB (physical resource block), BWP (bandwidth part), occasion), terms for operational states (e.g., step, operation, procedure), terms referring to data (e.g., packet, user stream, information, bit, symbol, codeword), terms referring to channels, terms referring to control information (e.g., downlink control information (DCI), medium access control control element (MAC CE), radio resource control (RRC) signaling), terms referring to network entities, terms referring to components of devices, etc. are used for convenience of explanation. Therefore, the present disclosure is not limited to the terms described below, and other terms having equivalent technical meanings may be used.

[0047] Additionally, in the present disclosure, expressions such as "more than" or "less than" may be used to determine whether a specific condition is satisfied or fulfilled. However, this is merely a description for expressing an example and does not exclude descriptions of "more than" or "less than." Conditions described as "more than" may be replaced with "more than," conditions described as "less than" may be replaced with "less than," and conditions described as "more than and less than" may be replaced with "more than and less than."

[0048] Additionally, although the present disclosure describes various embodiments using terms used in some communication standards (e.g., 3rd Generation Partnership Project (3GPP), extensible radio access network (xRAN), open-radio access network (O-RAN), etc.), these are merely examples for explanation. The various embodiments of the present disclosure can be easily modified and applied to other communication systems.

[0049] FIG. 1A illustrates a wireless communication system according to various embodiments of the present disclosure. FIG. 1A illustrates a base station (110), a terminal (120), and a terminal (130) as some of the nodes utilizing a wireless channel in the wireless communication system. While FIG. 1 illustrates only one base station, other base stations identical to or similar to base station (110) may be included.

[0050] The base station (110) is a network infrastructure that provides wireless access to terminals (120, 130). The base station (110) has coverage defined as a certain geographical area based on the distance at which a signal can be transmitted. In addition to the base station, the base station (110) may be referred to as an 'access point (AP)', 'eNodeB (eNB)', '5th generation node', 'next generation nodeB (gNB)', 'wireless point', 'transmission / reception point (TRP)', or other terms having equivalent technical meanings.

[0051] Each of the terminal (120) and the terminal (130) is a device used by a user and communicates with the base station (110) via a wireless channel. The link from the base station (110) to the terminal (120) or the terminal (130) is referred to as a downlink (DL), and the link from the terminal (120) or the terminal (130) to the base station (110) is referred to as an uplink (UL). In addition, the terminal (120) and the terminal (130) may communicate with each other via a wireless channel. At this time, the link (device-to-device link, D2D) between the terminals (120) and (130) is referred to as a sidelink, and the sidelink may be used interchangeably with the PC5 interface. In some cases, at least one of the terminals (120) and the terminal (130) may be operated without the intervention of the user. That is, at least one of the terminal (120) and the terminal (130) is a device that performs machine type communication (MTC) and may not be carried by the user. Each of the terminal (120) and the terminal (130) may be referred to as a 'user equipment (UE)', a 'mobile station', a 'subscriber station', a 'remote terminal', a 'wireless terminal', a 'user device', or other terms having an equivalent technical meaning.

[0052] The base station (110), the terminal (120), and the terminal (130) can perform beamforming. The base station and the terminal can transmit and receive wireless signals in a relatively low frequency band (e.g., frequency range 1 (FR1) of NR). In addition, the base station and the terminal can transmit and receive wireless signals in a relatively high frequency band (e.g., FR2 of NR, millimeter wave (mmWave) band (e.g., 28 GHz, 30 GHz, 38 GHz, 60 GHz)). In some embodiments, the base station (110) can communicate with the terminal (120) within a frequency range corresponding to FR1. In some embodiments, the base station can communicate with the terminal (120) within a frequency range corresponding to FR2. At this time, in order to improve channel gain, the base station (110), the terminal (120), and the terminal (130) can perform beamforming. Here, beamforming may include transmission beamforming and reception beamforming. That is, the base station (110), terminal (120), and terminal (130) may provide directionality to a transmission signal or a reception signal. To this end, the base station (110) and terminals (120, 130) may select serving beams (112, 113, 121, 131) through a beam search or beam management procedure. After the serving beams (112, 113, 121, 131) are selected, subsequent communication may be performed through resources that are in a quasi-co-located (QCL) relationship with the resources that transmitted the serving beams (112, 113, 121, 131).

[0053] If large-scale characteristics of a channel carrying a symbol on a first antenna port can be inferred from a channel carrying a symbol on a second antenna port, the first antenna port and the second antenna port can be evaluated to have a QCL relationship. For example, the large-scale characteristics may include at least one of delay spread, Doppler spread, Doppler shift, average gain, average delay, and a spatial receiver parameter.

[0054] Although both the base station and the terminal are depicted as performing beamforming in FIG. 1A, the various embodiments of the present disclosure are not necessarily limited thereto. In some embodiments, the terminal may or may not perform beamforming. Furthermore, the base station may or may not perform beamforming. That is, either only one of the base station and the terminal may perform beamforming, or neither the base station nor the terminal may perform beamforming.

[0055] In the present disclosure, a beam refers to a spatial flow of a signal in a wireless channel, and is formed by one or more antennas (or antenna elements), and this forming process may be referred to as beamforming. Beamforming may include analog beamforming and digital beamforming (e.g., precoding). Reference signals transmitted based on beamforming may include, for example, a demodulation-reference signal (DM-RS), a channel state information-reference signal (CSI-RS), a synchronization signal / physical broadcast channel (SS / PBCH), and a sounding reference signal (SRS). In addition, as a configuration for each reference signal, an IE such as a CSI-RS resource or an SRS-resource may be used, and this configuration may include information associated with the beam. Information associated with a beam may mean whether the configuration (e.g., a CSI-RS resource) uses the same spatial domain filter as another configuration (e.g., another CSI-RS resource within the same CSI-RS resource set) or a different spatial domain filter, or whether it is quasi-co-located (QCL) with a reference signal, and if so, what type it is (e.g., QCL type A, B, C, D).

[0056] In the past, in communication systems with relatively large cell radius of base stations, each base station was installed such that each base station included the functions of a digital processing unit (or DU (digital unit)) and a radio frequency (RF) processing unit (or RU (radio unit)). However, as higher frequency bands are used in 4G (4th generation) and / or later communication systems and the cell radius of base stations becomes smaller, the number of base stations to cover a specific area has increased, and the burden of installation costs on operators for installing the increased number of base stations has increased. In order to minimize the installation cost of base stations, a structure has been proposed in which the DU and RU of the base station are separated, one or more RUs are connected to one DU via a wired network, and one or more RUs are geographically distributed to cover a specific area. Hereinafter, the deployment structure and expansion examples of base stations according to various embodiments of the present disclosure are described through FIG. 1b.

[0057] FIG. 1B illustrates an example of a fronthaul structure according to functional separation of a base station according to various embodiments of the present disclosure. Unlike the backhaul between the base station and the core network, fronthaul refers to the space between entities between a wireless LAN and the base station. Although FIG. 1B illustrates DU and RU, the present disclosure is not limited thereto, and according to various embodiments of the present disclosure, DU and RU may respectively mean O-DU and O-RU, which are terms in the O-RAN standard, and the above-described terms may be used interchangeably in the description. FIG. 1B illustrates an example of a fronthaul structure between a DU (160) and one RU (180), but this is merely for convenience of explanation and the present disclosure is not limited thereto. In other words, the present disclosure can also be applied to a fronthaul structure between one O-DU and multiple O-RUs, as shown in FIG. 5. For example, the present disclosure can be applied to a fronthaul structure between one O-DU and two O-RUs. Additionally, the embodiments of the present disclosure can also be applied to a fronthaul structure between one O-DU and three O-RUs.

[0058] Referring to FIG. 1B, a base station (110) may include a DU (160) and an RU (180). A fronthaul (170) between the DU (160) and the RU (180) may be operated via an Fx interface. Various fronthaul interfaces defined in the standard (e.g., enhanced common public radio interface (eCPRI), radio over ethernet (ROE)) may be used for operation of the fronthaul (170).

[0059] As communications technology advances, mobile data traffic increases, significantly increasing the bandwidth requirements for the fronthaul between the digital unit and the radio unit. In deployments such as C-RAN (centralized / cloud radio access network), the DU performs functions for the packet data convergence protocol (PDCP), radio link control (RLC), media access control (MAC), and physical layer (PHY), while the RU can be implemented to perform additional functions for the PHY layer in addition to its radio frequency (RF) functions.

[0060] DU (160) may be responsible for upper layer functions of a wireless network. For example, DU (160) may perform functions of the MAC layer and a part of the PHY layer. Here, a part of the PHY layer refers to functions performed at a higher level among the functions of the PHY layer, and may include, for example, channel encoding (or channel decoding), scrambling (or descrambling), modulation (or demodulation), and layer mapping (or layer demapping). According to an embodiment, if DU (160) complies with the O-RAN standard, it may be referred to as O-DU (O-RAN DU).

[0061] The RU (180) may be responsible for lower layer functions of a wireless network. For example, the RU (180) may perform a part of the PHY layer, an RF function. Here, a part of the PHY layer refers to functions of the PHY layer that are performed at a relatively lower level than the DU (160), and may include, for example, inverse fast Fourier transform (IFFT) conversion (or fast Fourier transform (FFT) conversion), cyclic prefix (CP) insertion (CP removal), and digital beamforming. An example of such specific functional separation is described in detail in FIG. 4. The RU (180) may be referred to as an 'access unit (AU)', an 'access point (AP)', a 'transmission / reception point (TRP)', a 'remote radio head (RRH)', a 'radio unit (RU)', or other terms having an equivalent technical meaning thereto. In one embodiment, if the RU (180) complies with the O-RAN standard, it may be referred to as an O-RU (O-RAN RU).

[0062] Although FIG. 1B illustrates a base station including a DU and an RU, various embodiments of the present disclosure are not limited thereto. In some embodiments, the base station may be implemented in a distributed deployment according to a centralized unit (CU) configured to perform functions of upper layers of an access network (e.g., packet data convergence protocol (RRC) (PDCP)) and a distributed unit (DU) configured to perform functions of lower layers. In this case, the distributed unit (DU) may include a digital unit (DU) and a radio unit (RU) of FIG. 1B. Between a core (e.g., 5GC (5G core) or NGC (next generation core)) network and a radio network (RAN), the base station may be implemented in a structure in which the CU, DU, and RU are arranged in that order. The interface between the CU and the distributed unit (DU) may be referred to as an F1 interface.

[0063] A centralized unit (CU) can be connected to one or more DUs and can be responsible for functions of a higher layer than the DU. For example, the CU can be responsible for functions of the RRC (radio resource control) and PDCP (packet data convergence protocol) layers, and the DU and RU can be responsible for functions of lower layers. The DU can perform some functions (high PHY) of the RLC (radio link control), MAC (media access control), and PHY (physical) layers, and the RU can be responsible for the remaining functions (low PHY) of the PHY layer. In addition, as an example, a DU (digital unit) can be included in a DU (distributed unit) depending on the implementation of a distributed deployment of a base station. Hereinafter, in the present disclosure, a DU (digital unit) can be understood to have the same meaning as a DU (distributed unit) that does not include an RU for convenience of explanation. Additionally, DU (digital unit) (or DU (distributed unit)) can be understood to have the same meaning as O-DU (O-RAN digital unit) or O-DU (O-RAN distributed unit).

[0064] FIG. 2 illustrates the configuration of a DU (distributed unit) in a wireless communication system according to various embodiments of the present disclosure. The configuration illustrated in FIG. 2 may be understood as the configuration of the DU (160) of FIG. 1B as part of a base station. Terms such as "...unit" and "...unit" used hereinafter refer to a unit that processes at least one function or operation, and may be implemented using hardware, software, or a combination of hardware and software.

[0065] Referring to FIG. 2, DU (160) includes a communication unit (210), a storage unit (220), and a control unit (230).

[0066] The communication unit (210) may perform functions for transmitting and receiving signals in a wired communication environment. The communication unit (210) may include a wired interface for controlling direct connections between devices via a transmission medium (e.g., copper wire, optical fiber). For example, the communication unit (210) may transmit electrical signals to other devices via copper wire, or perform conversion between electrical signals and optical signals. The communication unit (210) may be connected to a radio unit (RU). The communication unit (210) may be connected to a core network or to a CU in a distributed arrangement.

[0067] The communication unit (210) may perform functions for transmitting and receiving signals in a wireless communication environment. For example, the communication unit (210) may perform a conversion function between a baseband signal and a bit stream according to the physical layer specifications of the system. For example, when transmitting data, the communication unit (210) generates complex symbols by encoding and modulating the transmission bit stream. In addition, when receiving data, the communication unit (210) restores the reception bit stream by demodulating and decoding the baseband signal. In addition, the communication unit (210) may include multiple transmission and reception paths. In addition, according to one embodiment, the communication unit (210) may be connected to the core network or other nodes (e.g., an integrated access backhaul (IAB).

[0068] The communication unit (210) can transmit and receive signals. To this end, the communication unit (210) may include at least one transceiver. For example, the communication unit (210) may transmit a synchronization signal, a reference signal, system information, a message, a control message, a stream, control information, or data.

[0069] The communication unit (210) transmits and receives signals as described above. Accordingly, all or part of the communication unit (210) may be referred to as a "transmitter," a "receiver," or a "transmitting and receiving unit." Furthermore, in the following description, transmission and reception performed via a wireless channel are used to mean that the communication unit (210) performs the processing described above.

[0070] Although not illustrated in FIG. 2, the communication unit (210) may further include a backhaul communication unit for connection to the core network or other base stations. The backhaul communication unit provides an interface for communicating with other nodes within the network. That is, the backhaul communication unit converts a bit stream transmitted from the base station to other nodes, such as other access nodes, other base stations, upper nodes, and the core network, into a physical signal, and converts a physical signal received from other nodes into a bit stream.

[0071] The storage unit (220) stores data such as basic programs, application programs, and setting information for the operation of the DU (160). The storage unit (220) may include memory. The storage unit (220) may be composed of volatile memory, nonvolatile memory, or a combination of volatile memory and nonvolatile memory. In addition, the storage unit (220) provides stored data upon request from the control unit (230).

[0072] The control unit (230) controls the overall operations of the DU (160). For example, the control unit (230) transmits and receives signals through the communication unit (210) (or through the backhaul communication unit). In addition, the control unit (230) records and reads data from the storage unit (220). In addition, the control unit (230) can perform the functions of the protocol stack required by the communication standard. To this end, the control unit (230) can include at least one processor.

[0073] The configuration of DU (160) illustrated in FIG. 2 is merely an example, and examples of DUs performing various embodiments of the present disclosure are not limited to the configuration illustrated in FIG. 2. According to various embodiments, some or the same configurations may be added, deleted, or changed.

[0074] FIG. 3 illustrates the configuration of a radio unit (RU) in a wireless communication system according to various embodiments of the present disclosure. The configuration illustrated in FIG. 3 may be understood as the configuration of the RU (180) of FIG. 1B as part of a base station. Terms such as "...unit" and "...unit" used hereinafter refer to a unit that processes at least one function or operation, and may be implemented using hardware, software, or a combination of hardware and software.

[0075] Referring to FIG. 3, RU (180) includes a communication unit (310), a storage unit (320), and a control unit (330).

[0076] The communication unit (310) performs functions for transmitting and receiving signals via a wireless channel. For example, the communication unit (310) upconverts a baseband signal into an RF band signal and then transmits the upconverted signal via an antenna, and downconverts an RF band signal received via the antenna into a baseband signal. For example, the communication unit (310) may include a transmission filter, a reception filter, an amplifier, a mixer, an oscillator, a DAC, an ADC, and the like.

[0077] In addition, the communication unit (310) may include a plurality of transmission and reception paths. Furthermore, the communication unit (310) may include an antenna unit. The communication unit (310) may include at least one antenna array composed of a plurality of antenna elements. In terms of hardware, the communication unit (310) may be composed of digital circuits and analog circuits (e.g., radio frequency integrated circuits (RFIC)). Here, the digital circuits and analog circuits may be implemented in a single package. In addition, the communication unit (310) may include a plurality of RF chains. The communication unit (310) may perform beamforming. The communication unit (310) may apply beamforming weights to a signal to be transmitted and received in order to impart directionality according to the settings of the control unit (330). According to one embodiment, the communication unit (310) may include an RF (radio frequency) block (or RF unit).

[0078] In addition, the communication unit (310) can transmit and receive signals. For this purpose, the communication unit (310) can include at least one transceiver. The communication unit (310) can transmit a downlink signal. The downlink signal can include a synchronization signal (SS), a reference signal (RS) (e.g., cell-specific reference signal (CRS), demodulation (DM)-RS), system information (e.g., MIB, SIB, remaining system information (RMSI), other system information (OSI)), a configuration message, control information, or downlink data. In addition, the communication unit (310) can receive an uplink signal. The uplink signal may include a random access related signal (e.g., a random access preamble (RAP) (or Msg1 (message 1)), Msg3 (message 3)), a reference signal (e.g., a sounding reference signal (SRS), DM-RS), or a power headroom report (PHR).

[0079] The communication unit (310) transmits and receives signals as described above. Accordingly, all or part of the communication unit (310) may be referred to as a "transmitter," a "receiver," or a "transmitting and receiving unit." Furthermore, in the following description, transmission and reception performed via a wireless channel are used to mean processing performed by the communication unit (310) as described above.

[0080] The storage unit (320) stores data such as basic programs, application programs, and setting information for the operation of the RU (180). The storage unit (320) may be configured as volatile memory, non-volatile memory, or a combination of volatile memory and non-volatile memory. In addition, the storage unit (320) provides the stored data upon request of the control unit (330). According to various embodiments of the present disclosure described below, the storage unit (320) may include a memory for performing operations for processing or IFFT transformation for beamforming weights.

[0081] The control unit (330) (processor or controller) controls the overall operations of the RU (180). For example, the control unit (330) transmits and receives signals through the communication unit (310). In addition, the control unit (330) records and reads data in the storage unit (320). In addition, the control unit (330) can perform functions of the protocol stack required by the communication standard. For this purpose, the control unit (330) can include at least one processor. In some embodiments, the control unit (330) can be configured to transmit an SRS to the DU (160) based on an antenna number. In addition, in some embodiments, the control unit (330) can be configured to transmit the SRS to the DU (160) after uplink transmission. The control unit (330) may be a set of commands or codes stored in the storage unit (320) as condition commands or setting values ​​according to the SRS transmission method, and may be commands / codes that are temporarily resided in the control unit (330) or a storage space that stores commands / codes, or may be a part of the circuitry constituting the control unit (330). In addition, the control unit (330) may include various modules for performing communication. According to various embodiments, the control unit (330) may control the RU (180) to perform operations according to various embodiments described below. For example, the control unit (330) may control the beamforming block, the IFFT block, and specific components included in each block included in the RU to operate according to various embodiments of the present disclosure described below.

[0082] According to various embodiments of the present disclosure, the above-described unit is only an example and is not limited thereto, and it is to be understood that the RU (180) may include various blocks or units according to various embodiments described below. For example, the RU may further include a block for precoding data or applying beamforming weights, a block for IFFT transformation, or a block for performing IFFT and inserting CP. Hereinafter, examples of more specific RU structures including various blocks are described, and the operations performed by the RU are described for convenience, and it is to be understood that each may mean an operation performed by a specific component of the RU.

[0083] FIG. 4 illustrates an example of function split in a wireless communication system according to various embodiments of the present disclosure. As wireless communication technology advances (e.g., introduction of 5G (5th generation) communication systems (or NR (new radio) communication systems), the frequency bands used have increased further, and the cell radius of base stations has become very small, leading to an increase in the number of RUs required for installation. Furthermore, in 5G communication systems, the amount of data transmitted has increased by a factor of up to ten, significantly increasing the transmission capacity of wired networks transmitted to the fronthaul. Due to these factors, the installation cost of wired networks in 5G communication systems may increase significantly. Therefore, in order to lower the transmission capacity of wired networks and reduce the installation cost of wired networks, technologies have been proposed to lower the transmission capacity of the fronthaul by transferring some of the modem functions of the DU to the RU, and these technologies may be referred to as 'function split'.

[0084] To reduce the burden on the DU, a method is being considered to expand the role of the RU, which is currently solely responsible for RF functions, to include some physical layer functions. In this case, as the RU performs higher-layer functions, its throughput increases, increasing transmission bandwidth in the fronthaul while simultaneously reducing latency requirements due to response processing. However, as the RU performs higher-layer functions, virtualization gains decrease and the RU size, weight, and cost increase. Considering the trade-offs between the aforementioned advantages and disadvantages, implementing an optimal functional separation is required.

[0085] Referring to FIG. 4, the functional separations in the physical layer below the MAC layer are illustrated. For the downlink (DL) that transmits signals to terminals through a wireless network, the base station can sequentially perform channel encoding / scrambling, modulation, layer mapping, antenna mapping, RE (resource element) mapping, digital beamforming (e.g., precoding), IFFT transform / CP insertion, and RF transform. For the uplink (UL) that receives signals from terminals through a wireless network, the base station can sequentially perform RF transform, FFT transform / CP removal, digital beamforming (pre-combining), RE demapping, channel estimation, layer demapping, demodulation, and decoding / descrambling. The separation of uplink and downlink functions can be defined in various types depending on the needs of vendors, discussions in standards, etc., according to the above-described trade-offs.

[0086] The first functional separation (405) may be the separation of the RF function and the PHY function. The first functional separation may be the separation of the PHY function in which the PHY function is not actually implemented in the RU, and may be referred to as Option 8, for example. The second functional separation (410) allows the RU to perform IFFT transform / CP insertion in the DL and FFT transform / CP removal in the UL of the PHY function, and the DU to perform the remaining PHY functions. As an example, the second functional separation (410) may be referred to as Option 7-1. The third functional separation (420a) allows the RU to perform IFFT transform / CP insertion in the DL and FFT transform / CP removal and digital beamforming in the UL of the PHY function, and the DU to perform the remaining PHY functions. As an example, the third functional separation (420a) may be referred to as Option 7-2x Category A. The fourth functional separation (420b) allows the RU to perform up to digital beamforming in both the DL and UL, and the DU to perform upper PHY functions after the digital beamforming. For example, the fourth functional separation (420b) may be referred to as Option 7-2x Category B. The fifth functional separation (425) allows the RU to perform up to RE mapping (or RE demapping) in both the DL and UL, and the DU to perform upper PHY functions after RE mapping (or RE demapping). For example, the fifth functional separation (425) may be referred to as Option 7-2. The sixth functional separation (430) allows the RU to perform up to modulation (or demodulation) in both the DL and UL, and the DU to perform up to modulation (or demodulation) and the upper PHY functions thereafter. For example, the sixth functional separation (430) may be referred to as Option 7-3. The seventh functional separation (440) allows the RU to perform encoding / scrambling (or decoding / descrambling) in both the DL and UL, and the DU to perform subsequent upper PHY functions up to modulation (or demodulation). For example, the seventh functional separation (440) may be referred to as Option 6.

[0087] In one embodiment, when a large amount of signal processing is expected, such as in the FR1 MMU, functional separation at a relatively high layer (e.g., the fourth functional separation (420b)) may be required to reduce fronthaul capacity. In addition, functional separation at too high a layer (e.g., the sixth functional separation (430)) may complicate the control interface and cause a burden on the implementation of the RU due to the inclusion of a large number of PHY processing blocks within the RU. Therefore, appropriate functional separation may be required depending on the arrangement and implementation method of the DU and the RU.

[0088] In one embodiment, if the precoding of data received from the DU cannot be processed (i.e., if the precoding capability of the RU is limited), the third functional separation (420a) or a lower functional separation (e.g., the second functional separation (410)) may be applied. Conversely, if the DU has the capability to process the precoding of data received from the DU, the fourth functional separation (420b) or a higher functional separation (e.g., the sixth functional separation (430)) may be applied.

[0089] Hereinafter, various embodiments in the present disclosure are described based on the third functional separation (420a) (category A) or the fourth functional separation (420b) (category B) for performing beamforming processing in the RU unless otherwise specified, but this does not exclude the configuration of embodiments through other functional separations. It goes without saying that the functional configuration, signaling, or operation of FIGS. 5 to 16 described below can be applied not only to the third functional separation (420a) or the fourth functional separation (420b), but also to other functional separations.

[0090] According to various embodiments of the present disclosure, the application protocol of the fronthaul between the DU and the RU may include a control plane (C-plane), a user plane (U-plane), a synchronization plane (S-plane), and a management plane (M-plane).

[0091] According to one embodiment, the control plane may be configured to provide scheduling information and beamforming information via control messages. According to one embodiment, the user plane may include downlink data (IQ (in-phase / quadrature-phase) data or SSB / RS), uplink data (IQ data or SRS / RS), or PRACH data of the user. The weight vector of the beamforming information described above may be multiplied by the user's data. According to one embodiment, the synchronization plane may be related to timing and synchronization. According to one embodiment, the management plane may be related to initial setup, non-realtime reset or reset, and non-realtime report.

[0092] In one embodiment, a Section Type is defined to define the type of message transmitted on the control plane. The Section Type may indicate the purpose of the control message transmitted on the control plane. For example, the purposes for each Section Type are as follows.

[0093] ● sectionType=0: DL idle / guard periods - Used for Tx blanking for power saving

[0094] ● sectionType=1: Maps BF index or weight (O-RAN mandatory BF method) to RE of DL / UL channel

[0095] ● sectionType=2: reserved

[0096] ● sectionType=3: Maps beamforming index or weight to RE of PRACH and mixed-numerology channels

[0097] ● sectionType=4: reserved

[0098] ● sectionType=5: Transmits UE scheduling information so that the RU can calculate BF weight in real time (O-RAN optional BF method)

[0099] ● sectionType=6: Periodically transmits UE channel information so that the RU can calculate BF weight in real time (O-RAN optional BF method)

[0100] ● sectionType=7: Used for LAA support

[0101] FIG. 5 illustrates examples of connections between DUs and RUs according to various embodiments of the present disclosure. In FIGS. 1 through 4 , a single RU connected to a single DU is described. However, embodiments according to the present disclosure can also be applied between multiple RUs (radio units) connected to a single DU (digital unit).

[0102] According to various embodiments of the present disclosure, O-DU (160) may refer to DU (160) of FIGS. 1B and 2, and O-RU (180) may refer to RU (180) of FIGS. 1B and 3.

[0103] Hereinafter, a method for reducing memory used to align a time domain within an LPHY (Low-PHY) DL block that processes downlink (DL) in a wireless mobile communication system according to various embodiments of the present disclosure is described.

[0104] In one embodiment, DL is a real-time OFDM symbol-by-symbol conversion of a frequency-domain signal into a time-domain signal via an Inverse Fast Fourier Transform (IFFT). This signal is then output via memory with Cyclic Delay Diversity (CDD) applied and a Cyclic Prefix (CP) inserted. For this purpose, a memory exists to store the time-domain symbol signal.

[0105] The present invention is a method for optimizing the required memory resources and power consumption for a time domain DL Symbol signal by enabling multi-channel processing in the DIT (Decimation In Time) structure of IFFT.

[0106] FIG. 6 illustrates the structure of a downlink chain block of an RU according to various embodiments of the present disclosure. Specifically, FIG. 6 relates to a downlink chain structure including blocks for converting a downlink digital signal into an analog signal and transmitting it.

[0107] The MMU / RU (hereinafter, RU) of a wireless communication system can process signals between a modem (e.g., including a DU) (611) and a terminal. More specifically, the LPHY-DL (610) of the RU can receive DL layer IQ data symbols in the frequency domain from the modem (611) through the user plane (U-plane). According to one embodiment, the LPHY-DL block of the RU can be configured such that input samples are in a form for applying IFFT in a block (613) for digital frequency domain signal processing.

[0108] According to one embodiment, the IFFT block (615) of the RU can convert the acquired OFDM (orthogonal frequency division multiplexing) frequency domain digital signal for each antenna into a time domain digital signal by applying IFFT in units of N-point symbols. The DL memory block (617) of the RU can add or insert CDD (Cyclic Delay Diversity) and CP (Cyclic Prefix) to the digital signal and transmit it to the digital time domain signal processing block (619). Thereafter, the time domain DL signal can be converted into an analog radio signal in the time domain digital signal processing block (619), can be radiated through an antenna, and the terminal can receive the radiated radio signal.

[0109] According to one embodiment, when the operating clock frequency of each block is an integer multiple higher than the sampling rate of the signal, signals of the integer multiple paths can be processed within the same time in one IFFT block (615). Here, the clock frequency may refer to the generation period of a clock pulse used to synchronize operations performed within the RU system. Here, the sampling rate may refer to the speed required to process conversion between an analog signal and a digital signal. That is, when the speed at which a signal can be processed within the RU system is n times higher than the speed required to process the signal, signals of the n-fold paths can be processed within the same time in one processing block (e.g., the IFFT block (615)).

[0110] Hereinafter, various examples of processing multiple signals (layer IQ data or antenna IQ data) by MUXing are described according to various embodiments of the present disclosure to reduce memory usage, but the present disclosure is not limited thereto and the operation and structure of various embodiments can be applied depending on the downlink structure.

[0111] FIG. 7 illustrates an example of a frequency spectrum for an inverse fast Fourier transform (IFFT) transform according to various embodiments of the present disclosure. Specifically, referring to FIG. 7, a spectrum in the frequency domain for performing an IFFT transform for IFFT processing of k tones within a sample rate (705) of a downlink signal is illustrated.

[0112] Hereinafter, specific examples of various operations for processing a signal in the frequency domain in an IFFT block according to various embodiments of the present disclosure are described.

[0113] In one embodiment, a signal in the frequency domain may have a spectrum that repeats on the frequency axis at a period of the sample rate. When performing an N-point IFFT transformation on k tones within the sample rate (705) (e.g., k ≤ N), the spectrum in the frequency domain may appear as illustrated in FIG. 7.

[0114] Referring to FIG. 7, fs may mean a sample rate (705). One tone may mean one sub-carrier spacing (scs), and when one symbol includes an N-point IFFT, fs may be derived as in Equation 1 below.

[0115]

[0116] In one embodiment, the signal in the frequency domain may have a spectrum that repeats along the frequency axis at a sampling rate. Accordingly, referring to FIG. 7, it can be expected that the signal of the Lower Side located in the (-fs / 2, 0) region (715) will appear repeatedly in the (fs / 2, fs) region (735).

[0117] At this time, since the physically implemented N-point IFFT block requires N point samples in the positive region (e.g., (0, fs) region (725)) for the IFFT operation, the k tones of the downlink signal need to have their order changed (e.g., IFFT shift) as shown in FIG. 7, and a memory for IFFT transformation can be used to perform this IFFT transformation.

[0118] For example, depending on the signal that repeats at a sample rate, it can be expected that the signal of the Lower Side located in the (-fs / 2, 0) area (715) is also repeated in the (fs / 2, fs) area (735), and accordingly, the N-point IFFT block that is required to operate using N point samples of the (0, fs) area (725, 735) can perform IFFT conversion based on the tones of the signal including the expected tones (e.g., the expected tones of the (fs / 2, fs) area (735)). To this end, before performing the IFFT operation, it is necessary to change the order of the signal of the Lower Side located in the (-fs / 2, 0) area (715) to the (fs / 2, fs) area (735), and memory for the IFFT conversion may be required in this process.

[0119] According to various embodiments of the present disclosure, as described above, the k tones illustrated in FIG. 7 may undergo IFFT transformation for IFFT processing. In this case, when the clock frequency of the system is n times greater than the sample rate (fs), symbols of layer IQ data or antenna IQ data of n paths may be processed within the same time.

[0120] IFFT sequentially processes DL Symbol Data (N-point Samples) of one path, and the structure can be configured as DIF (Decimation In Frequency) or DIT (Decimation in Time). First, in the case of the DIF structure, the input sample order is the natural order (i.e., sequential ascending order), but the output sample order is the bit-reversal order, and in the case of DIT, the input sample order is the bit-reversal order, and the output sample order is the natural order, as opposed to DIF.

[0121] Regarding the IFFT DIT structure, as an example, the IFFT input sample in the IFFT DIT structure can be configured as in the mathematical expression 2 below.

[0122]

[0123] Here, the above mathematical expression 2 is a normalized IFFT equation, and N is the length of N points where IFFT is performed. At this time, since the input samples in the IFFT DIT structure are configured in bit-reversal order, in the case of N-point IFFT, the entire input sample x[n] can be input to the IFFT block not in the order of bit 0, 1, 2, 3, ... N in decimal, but in the order of n values ​​0, NFFT / 2, NFFT / 4, ...

[0124] Also, in the case of N-point IFFT, when performing IFFT on input samples, the twiddle factor W multiplied by half (which may be odd or even) of the input samples in the N / 2-point DFT (Discrete Fourier Transform) process on half (which may be odd or even) of the input samples can be configured as in the following mathematical expression 3, and in particular, when k is 0, W becomes 1.

[0125]

[0126] FIG. 8 is a diagram showing an example of a logical structure of a 2-DFT according to various embodiments of the present disclosure. More specifically, FIG. 8 illustrates a 2-point IFFT, and input samples may be composed of two (x[0] and x[1]) (810). A 1-point DFT may be applied to the input sample x[0], and a rotator (811) may be multiplied after the 1-point DFT is applied to the input sample x[1]. At this time, since the value of the rotator is 1, the value obtained by multiplying the rotator (811) after the 1-point DFT is applied to the input sample x[1] may be the same as x[1]. The sum of the value to which 1-point DFT is applied to input sample x[0] and the value multiplied by the rotator (811) after applying 1-point DFT to input sample x[1] can be composed of IFFT output sample y[0] = x[0] + x[1]. In addition, the difference between the value to which 1-point DFT is applied to input sample x[0] and the value multiplied by the rotator (811) after applying 1-point DFT to input sample x[1] can be composed of IFFT output sample y[1] = x[0] - x[1].

[0127] FIG. 9 is a diagram showing an example of a hardware structure of a 2-DFT and an operation timing diagram thereof according to various embodiments of the present disclosure. More specifically, FIG. 9 illustrates a 2-point IFFT. Referring to the upper drawing of FIG. 9, 910 denotes a stage control signal for controlling a 2BF block for a 2-point IFFT operation, 911 denotes an input sample signal, 913 denotes a node for MUXing input samples at a specific point in time, and 915 denotes an output sample signal which is an output of the IFFT operation. In the upper drawing of FIG. 9, in an N-point IFFT, an input sample (Data) is delayed by SIZE / 2 depending on the SIZE value indicated by N, and a Register (Filp-Flop) or memory may be used depending on the size of Size. A timing diagram showing the values ​​that nodes corresponding to 910, 911, 913, and 915 at the top of Fig. 9 respectively represent at specific timings is shown at the bottom of Fig. 9.

[0128] By utilizing the 2-DFT structure described above, a larger 2k (k is a natural number)-DFT structure can be constructed. More specifically, k 2-DFT structures can be cascaded to form 2 k -DFT structures can be constructed. For example, a 4-DFT structure can be constructed by cascading two 2-DFT structures. In the case of a 4-DFT structure, two rotation factors can be used, and W4 according to the mathematical equation 3 described above 0 becomes 1, and W4 1 can be configured as shown in mathematical formula 4 below.

[0129]

[0130] Through the above mathematical equation 4, the rotation factor W4 1 It can be applied in the same way as mathematical expression 5 without using an additional HW multiplier.

[0131]

[0132] In one embodiment, referring to the 3GPP TS38.211 v16.2.0 “Physical Channels and modulation” specification, the length of a symbol can be defined as N-IFFT symbol + CP. Below, the relationship and related contents among the constant (K), numeral (u), and CP described in 3GPP TS38.211 v16.2.0 are described.

[0133]

[0134] As described above, the sizes of various fields in the time domain can generally be expressed in units inversely proportional to the subcarrier spacing and the number of samples N. In addition, information on the subcarrier spacing and CP for transmission of uplink or downlink signals can be obtained as upper layer parameters.

[0135]

[0136] According to one embodiment, a time-continuous signal S can be derived according to the formula described above, and accordingly, N of symbols according to CP can be derived. This is rearranged to calculate the symbol duration for each SCS, as shown in Table 1 below.

[0137]

[0138] Table 1 shows the symbol duration time per subcarrier spacing (scs) in N-point FFT / IFFT.

[0139] In one embodiment, for an LPHY-DL block supporting scs 30kHz, BW (bandwidth) 100M - 3276 Tones, 4096 point IFFT, 2 Path MUX may be performed to optimize hardware (HW) resources when the clock frequency of the system operates at 245.76MHz clock. For example, in case of scs 30kHz, 4096 point IFFT, the length of a symbol including CP (e.g., a general CP, not an extended CP) may be 35.677 [μs]. When the length of the above symbol is calculated based on a 245.76MHz clock, 8768 clock cycles (e.g., 35.677μs × 245.76MHz) may be derived. That is, when processing samples at each clock, data (2×4096) corresponding to two symbols can be processed simultaneously. However, this is only an example, and depending on various variables such as subcarrier spacing and clock frequency, the data processed at each clock may correspond to two or more symbols (for example, four). That is, according to various embodiments of the present disclosure, two or more signal data can be MUXed and processed without being limited to the above-described examples.

[0140] As described above, signal paths having two or more sample rates within a clock frequency can be processed by being MUXed, and an example of this represented through a time-series timing diagram is illustrated in FIG. 10.

[0141] FIG. 10 illustrates an example of timing for a path multiplexer (MUX) according to various embodiments of the present disclosure. Specifically, referring to FIG. 10 , an example of timing for the input and output of an IFFT block is illustrated when two paths are MUXed. Specifically, FIG. 10 illustrates an example of timing for a case where each layer IQ data is converted into antenna IQ data, and then the two antenna IQ data are multiplexed and IFFT-processed.

[0142] Referring to FIG. 10, one input symbol S (1010) may include antenna IQ data TX#0 (1011) and TX#1 (1012) corresponding to multiplexed antenna indices #0 and #1. TX#0 (1011) and TX#1 (1012) may each be data obtained based on layer IQ data on which IFFT transformation has been performed. According to one embodiment, after IFFT processing of the input symbol, one output symbol S (1020) may include IFFT processed antenna IQ data TX#0 (1021) and TX#1 (1022).

[0143] In one embodiment, referring to FIG. 10, when the clock frequency is twice the sample rate, signals for two antenna paths can be processed within one symbol duration. For example, during the input value count of symbol S, tones for TX#0 and tones for TX#1 can be processed. These can be processed and output as output antenna IQ data for TX#0 and output antenna IQ data for TX#1 during the output value count of symbol S.

[0144] That is, as described above, each layer IQ data to which IFFT transformation is applied can have precoding and beamforming weights applied, and each antenna IQ data obtained accordingly can be multiplexed (MUXed) between two or more paths and processed within one symbol count value.

[0145] According to one embodiment, antenna IQ data with beamforming weights applied, as described above, may be multiplexed for each path and transmitted to an IFFT block. In this case, the MUX rate (e.g., MUX ratio) may be derived according to the following mathematical expression (6).

[0146]

[0147] FIG. 11 illustrates the structure of a downlink chain block of an RU according to various embodiments of the present disclosure. Specifically, FIG. 11 relates to a downlink chain structure including blocks for converting a downlink digital signal into an analog signal and transmitting it when the MUX rate is 2.

[0148] The MMU / RU (hereinafter, RU) of a wireless communication system can process signals between a modem (e.g., including a DU) (1111) and a terminal. More specifically, the LPHY-DL (1110) of the RU can receive DL layer IQ data symbols in the frequency domain from the modem (1111) through the user plane (U-plane). According to one embodiment, the LPHY-DL block of the RU can be configured such that input samples are in a form for applying IFFT in a block (1113) for digital frequency domain signal processing. Since Fig. 11 exemplifies a case where the MUX rate is 2, between the digital frequency domain signal processing block (1113) and the IFFT block (1115) of Fig. 11, unlike the frequency domain signal processing block (613) and the IFFT block (615) of Fig. 6, frequency domain DL symbol data for two antenna paths (e.g., TX #0 and TX #1) can be sequentially input to the IFFT block (1115) and processed.

[0149] According to one embodiment, the IFFT block (1115) of the RU can convert the acquired OFDM (orthogonal frequency division multiplexing) frequency domain digital signal for each antenna into a time domain digital signal by applying IFFT in units of N-point symbols. The time domain DL symbol data of each antenna path of the output of the IFFT block (1115) is sequentially stored in the DL memory block (1117). The DL memory block (1117) of the RU can add or insert CDD (Cyclic Delay Diversity) and CP (Cyclic Prefix) to the digital signal and transmit it to the digital time domain signal processing block (1119). By adding or inserting CDD (Cyclic Delay Diversity), different delay values ​​can be applied to DL signals of multiple antennas, so that frequency selective diversity can be obtained, and by inserting CP (Cyclic Prefix), a signal resistant to ISI (Inter Symbol Interference) can be created.

[0150] Thereafter, the time domain DL signal can be converted into an analog radio signal in a time domain digital signal processing block (1119), and can be radiated through an antenna, and the terminal can receive the radiated radio signal.

[0151] Hereinafter, various examples of processing multiple signals (layer IQ data or antenna IQ data) by MUXing are described according to various embodiments of the present disclosure to reduce memory usage, but the present disclosure is not limited thereto and the operation and structure of various embodiments can be applied depending on the downlink structure.

[0152] FIG. 12 is a diagram illustrating an example of a read operation of a DL memory according to various embodiments of the present disclosure. More specifically, FIG. 12 is a diagram regarding a read operation of a memory for applying CDD and CP to a DL symbol time domain signal written to a DL memory after the DL symbol time domain signal, which is the output of an IFFT block, is completely written to the DL memory.

[0153] Referring to FIG. 12, buffering for IFFT output is performed in the DL memory (1210), and at this time, the entire N-IFFT points can be assigned indices having values ​​from 0 to nFFT-1. Here, the indices assigned to the IFFT points can be read addresses used when performing reading in the DL memory. Among these, CCD can be configured to be applied to IFFT points included from the IFFT point whose index corresponds to nFFT-1-CDD to the IFFT point whose index corresponds to nFFT-1. Thereafter, CDD shift (1220) is performed on the IFFT points configured to be applied with CCD, and the positions of the corresponding IFFT points can be changed to the front part of the entire IFFT points. As a result of the CDD shift, the IFFT output in the DL memory can be configured in such a way that the IFFT points included in the index from the IFFT point corresponding to nFFT-1-CDD to the IFFT point corresponding to the index nFFT-1 are located in the front, followed by the IFFT points corresponding to the index 0 to nFFT-CDD-1. Afterwards, a CP can be added / inserted (1230) to the IFFT output on which the CDD shift (1220) has been performed, and the IFFT points included in the index from the IFFT point corresponding to nFFT-CDD-1 to the IFFT point corresponding to the length of the CP can be configured as the CP. At this time, the IFFT points configured as the CP can be added / inserted to the front of the IFFT output on which the CDD shift has been performed. As a result of CP addition / insertion (1230), the IFFT output within the DL memory can be configured in such a way that the IFFT points corresponding to the CP length are located at the front, followed by the IFFT points corresponding to CDD, followed by the IFFT points corresponding to indices 0 to nFFT-CDD-CP-1, and finally, the IFFT points corresponding to the CP length are located.Afterwards, reading is performed (1240) for the IFFT output to which CDD and CP are applied. Reading can be performed sequentially from the very beginning of the IFFT output configured after the CP insertion described above, and this can be illustrated as 1240 of FIG. 12. That is, when reading from the DL memory for each symbol, reading can be performed starting from the IFFT point corresponding to the index (NFFT-CDD-CP) in the IFFT output to which CDD and CP are applied, and up to the IFFT point corresponding to (nFFT-CDD). This can be as many IFFT points as the CP length. Afterwards, reading can be performed from the IFFT point corresponding to the index (nFFT-CDD), which are IFFT points to which CDD is applied, to the IFFT point corresponding to the index (nFFT-1). Afterwards, the index (or read address) is initialized to 0, and then reading can be performed from the IFFT point corresponding to the index 0 to the IFFT point corresponding to the index (NFFT-CDD-1). At this time, among the IFFT points corresponding to the index 0 to the index (NFFT-CDD-1), the IFFT points from the index corresponding to the (nFFT-CDD-CP-1) to the IFFT points corresponding to the index (nFFT-CDD-1) may be IFFT points corresponding to the CP length. The IQ sample data read in this way can be DL time domain symbol data. Meanwhile, since the DL output must be performed in the entire DL section, while the output of the IFFT block is written to the DL memory at the time of Symbol #k, the sample written to the DL memory at the time of the symbol prior to Symbol #k corresponding to Symbol #(k-1) can be read so that it is output from the DL memory. For such operations, the DL time domain memory can be configured to have a size that can handle Double Symbols.

[0154] For the LPHY DL block, IFFT shift memory is required for IFFT processing, and regardless of whether the structure of the IFFT block follows the DIF structure or the DIT structure, memory may also be required for blocks included after the IFFT block to apply CDD and CP. More specifically, the [N_SIZE-CP_SIZE:N_SIZE-1] portion of the time-domain symbol data must be stored in memory, and when the time-domain symbol data is output, CP must be added to the front of the Symbol. In addition, when the IFFT block processes symbol data on two or more paths, each path is processed sequentially, but when the MMU / RU antenna is finally output, the time-domain symbol data of all paths must be synchronized to 1pps and output simultaneously, so memory may be required for the LPHY block. To this end, the DL memory must store the output of the IFFT block so that the DL memory can output the processing result for the output of the IFFT block in the DL memory after the IFFT block has processed the symbol data of all paths for each symbol.

[0155] From the structure of the LPHY-DL block as above, the memory usage in the structure of the LPHY-DL block can be predicted.

[0156] More specifically, the mathematical expression 7 below can represent the IFFT stage data memory size (bit amount) based on 4k IFFT.

[0157]

[0158] In addition, the mathematical expression 8 below can represent the time domain data memory size (bits) based on a 4k IFFT for applying CDD and CP.

[0159]

[0160] In the above mathematical expressions 7 and 8, T may mean the number of antennas.

[0161] As wireless mobile communication technology advances, the complexity of MMU / RU is increasing. For example, when using the Function Split 7-2x Category-B structure of the MMU / RU LPHY DL to reduce front-haul capacity, a large amount of memory is required to store the beamforming weight table for precoding operation. Another example is that when the number of antennas increases for MIMO operation, memory usage increases, as shown in Equations 7 and 8 above. Thus, with the advancement of mobile communication technology, significant memory usage is required, and if the memory usage of the digital logic device cannot accommodate this, the required significant memory usage can become a factor that limits features such as required capacity. Furthermore, even if expensive digital logic devices capable of accommodating the required memory usage are used, power consumption increases proportionally as memory usage increases, which can have a negative impact on the system.

[0162] The present disclosure proposes an LPHY-DL structure that optimizes the usage of time-domain DL symbol memory by changing the IFFT operation structure in LPHY-DL of a wireless mobile communication system, and describes specific operations and implementation methods thereof. In addition, according to the structure, operations, and implementation methods described in the present disclosure, resources required for hardware implementation can be optimized, and effects such as hardware miniaturization and cost reduction can be achieved due to reduced circuit power consumption and heat generation.

[0163] Referring to FIG. 13, the LPHY-DL structure proposed in the present disclosure is described.

[0164] Fig. 13 is a diagram illustrating an LPHY-DL structure according to various embodiments of the present disclosure. Fig. 13 exemplifies a case where the MUX rate is 2.

[0165] The MMU / RU (hereinafter, RU) of a wireless communication system can process signals between a modem (e.g., including a DU) (1311) and a terminal. More specifically, the LPHY-DL of the RU can receive DL layer IQ data symbols in a frequency domain from the modem (1111) through a user plane (U-plane). According to one embodiment, the LPHY-DL block of the RU can be configured such that input samples are in a form for applying IFFT in a block (1313) for digital frequency domain signal processing. The block (1313) for digital frequency domain signal processing can include at least one DL Frequency Domain (DLFD) memory, and an IFFT shift operation can be performed within the DLFD memory. More specifically, each of at least one DL Frequency Domain (DLFD) memories included in the block (1313) for digital frequency domain signal processing stores DL symbol data of the frequency domain in the memory, reads the frequency domain DL symbol data stored in the memory in an IFFT shift and bit reversal order to match the structure of the interface of the DL_IFFT block (1315), and transmits the same to the DL_IFFT block (1315). The DL Frequency Domain (DLFD) memory may be located in front of the Precoding block or in front of the DL IFFT, depending on the configuration of the LPHY DL block. A DLFD memory exists for each chain in which DL blocks are connected, and the size of the DLFD memory of one chain is as shown in the following mathematical expression 9.

[0166]

[0167] Since Fig. 11 exemplifies a case where the MUX rate is 2, between the digital frequency domain signal processing block (1113) and the IFFT block (1115) of Fig. 11, unlike the frequency domain signal processing block (613) and the IFFT block (615) of Fig. 6, frequency domain DL symbol data for two antenna paths (e.g., TX #0 and TX #1) can be sequentially input to the IFFT block (1115) and processed.

[0168] According to one embodiment, the IFFT block (1315) of the RU can convert the acquired OFDM (orthogonal frequency division multiplexing) frequency domain digital signal for each antenna into a time domain digital signal by applying IFFT in units of N-point symbols. In the case of the IFFT block of FIG. 13, unlike the existing IFFT block, it can process as many antenna DL symbols as (MUX Rate) simultaneously. In the case of the DIT structure, the sample order of the time domain DL symbol data, which is the IFFT output, can be obtained in a natural order. Unlike the existing IFFT block, the DL_IFFT block of the present disclosure changes the operation order in the last operation stage of the IFFT process, thereby shifting the order of half of the output time domain DL symbol data, so that the usage of the DL TD (Time Domain) memory (1317) located after the DL_IFFT (1315) block can be reduced.

[0169] The DLTD memory block (1317) can store the DL symbol data of the time domain, which is the output of the DL_IFFT block (1315), in the memory, apply CDD, insert CP to read the memory, and then output the final LPHY DL block. There is a DLTD memory for each chain in which DL blocks are connected. Thereafter, the time domain DL signal can be converted into an analog radio signal in the time domain digital signal processing block (1319), and can be radiated through an antenna through the analog time domain signal processing block (1321), and the terminal can receive the radiated radio signal. Unlike the configuration of the LPHY DL block that processes the 2-path MUX described in FIG. 11, in the LPHY DL block described in FIG. 13, the DL_IFFT block does not sequentially process the DL symbol data of one antenna path, but DL symbol data of as many as (MUX rate) paths can be processed.

[0170] The present disclosure describes a method for overcoming the following limitations 1), 2) and 3) existing in DLTD memory.

[0171] 1) When one IFFT block sequentially processes DL symbol data of the number of paths (MUX rate) symbol units, the final LPHY DL output must be performed in a form in which the DL symbol data of all paths are output at the same time, so the data of previously processed paths must be stored in memory until the DL symbol data of all paths are processed.

[0172] 2) Since the DLTD memory must store samples from the rear part of the time domain DL symbol data and insert them into the front part of the symbol as CPs, the previously processed data must be stored in the memory until all data corresponding to the CP part of the IFFT output is processed.

[0173] 3) Since the IFFT block processes DL symbol data for each symbol, the DLTD memory that stores the time-domain DL symbol data must be able to store two symbol data so that the data processed by the IFFT block can be received and written into the memory while reading and outputting it.

[0174] In the case of limitation 1) above, this limitation arises because the existing IFFT block sequentially processes DL symbol data in the frequency domain symbol by symbol. Therefore, to overcome limitation 1) above, the present disclosure uses a DLFD memory structure that supports a DL_IFFT and a DL_IFFT input interface capable of processing frequency domain DL symbol data of multiple paths.

[0175] In the case of the above limitation 2), the time domain DL symbol data corresponding to the CP portion is processed in the latter half of the IFFT operation, which is a limitation. Therefore, in order to overcome the above limitation 2), the present disclosure changes the operation order of the last stage in the IFFT of the DIT structure, so that the time domain DL symbol data corresponding to the CP portion is processed first.

[0176] To overcome the above limitation 3), the present disclosure configures a memory capable of storing one symbol data by changing the operation order of the last stage in the IFFT of the DIT structure.

[0177] In the following, for the convenience of explanation, it is assumed that the value of scs (subcarrier spacing) is 30 kHz, the BW (bandwidth) is 100 M (3276 Tones, 4096 point IFFT), and the LPHY-DL supporting 8 antennas operates with a 245.76 MHz clock. However, this is merely an assumption for the convenience of explanation and should not be construed as limiting the scope of application of the method described in the present disclosure.

[0178] Additionally, TM (Antenna MUX rate) mentioned for explanation below can be defined as in mathematical expression 10 below. That is, TM can be defined as a value obtained by dividing the clock frequency by the maximum sampling rate.

[0179]

[0180] To enable the DL_IFFT block to process frequency domain DL symbol data of multiple paths simultaneously, the timing interface between the DLFD memory and the DL_IFFT block is defined as shown in Figure 14.

[0181] Fig. 14 is a timing diagram showing an example of timing of operations according to various embodiments of the present disclosure. More specifically, Fig. 14 is a timing diagram showing timing of operations between a DLFD memory and a DL_IFFT. The DLFD memory performs an IFFT shift on DL symbol data and changes the order of DL symbol data to a bit reversal order to match the structure of the interface of the DL_IFFT block, then stores the same and transfers it to the DL_IFFT block. 1411, 1413, and 1415 of Fig. 14 indicate this.

[0182] FIG. 15 is a diagram illustrating an example of a DLFD memory according to various embodiments of the present disclosure. More specifically, the DLFD memory structure of FIG. 15 exemplifies a memory structure for generating the same operation timing as FIG. 14. Referring to FIG. 15, the DLFD memory may include a memory (1510) and an RDIF (1520). First, the memory (1510) of FIG. 15 writes DL symbol IQ data for each antenna path. The depth of the memory may be (2×NFFT×TM). The internal structure of the memory (1510) may be configured to be divided into parts for processing odd symbols and even symbols. At this time, symbol data (1513) for TM antenna paths may be stored for each tone (1511) of each symbol. In addition, the RDIF (1520) for operation control in the DLFD memory may be implemented according to a pseudocode as shown in the table below.

[0183]

[0184] To control operations in DLFD memory, the DLFD memory read address (RADDR) can be configured as follows.

[0185] - RADDR Bitwidth - log2(2×NFFT×TM), [log2(2×NFFT×TM)-1:0]

[0186] - RADDR[log2(TM)-1:0]: Antenna Index

[0187] - RADDR[log2(NFFT)-1:log2(TM)]: Bit Reversal Order NFFT index

[0188] - RADDR[log2(2×NFFT)-1: log2(NFFT)]: Symbol Count LSB

[0189] The RADDR[log2(NFFT)-1:log2(TM)] portion of the DLFD memory read address can be configured to have a bit-reversed order according to the DL_IFFT input format configured as a DIT structure.

[0190] FIG. 16 is a diagram illustrating an example of an operation of changing a bit natural order into a bit inversion order according to various embodiments of the present disclosure. Referring to FIG. 16, 1611 represents an order sorted in natural order before bit inversion is performed, and 1613 represents an order sorted after bit inversion is performed. 1615 represents a correspondence table between binary and decimal numbers according to the bit natural order of 1611, and 1617 represents a correspondence table between binary and decimal numbers according to the bit inversion order of 1613.

[0191] FIG. 17 is a diagram showing an example of a hardware structure of a 2-DFT and an operation timing diagram thereof according to various embodiments of the present disclosure. More specifically, FIG. 17 illustrates a 2-point IFFT. Referring to the upper drawing of FIG. 17, 1710 denotes a stage control signal for controlling a 2BF block for a 2-point IFFT operation, 1711 denotes an input sample signal, 1713 denotes a node for MUXing input samples at a specific point in time, and 1715 denotes an output sample signal which is an output of the IFFT operation. Unlike FIG. 9, in the upper drawing of FIG. 17, in an N-point IFFT, an input sample (Data) is delayed (1712) by (TM) * (SIZE / 2)-1 according to the SIZE value indicated by N and the value of the antenna path (TM), and a Register (Flip-Flop) or memory may be used depending on the size of Size. A timing diagram showing the values ​​that nodes corresponding to 1710, 1711, 1713, and 1715 at the top of Fig. 17 respectively represent at specific timings is illustrated at the bottom of Fig. 17. Compared with the example of Fig. 9, the Delay memory of Fig. 9 has a size of (SIZE / 2), whereas the Delay memory of Fig. 17 has a size of TM×(SIZE / 2). At this time, since the Delay TM of the stage following the MUX (1713) has a small size, it can be implemented as a Register instead of a memory. In addition, the Latency of Fig. 17 can increase by TM×(SIZE / 2) clocks in the Stage compared to the Latency of Fig. 9. However, since the Latency in Fig. 9 is the time required to process DL symbol data for one antenna, the Latency required to process TM antenna DL symbol data according to the structure of Fig. 9 is greater than the Latency in Fig. 17.

[0192] FIG. 18 is a diagram illustrating an example of a hardware structure of a 4-DFT and an operation timing diagram thereof according to various embodiments of the present disclosure. More specifically, FIG. 18 illustrates a 4-point IFFT. By utilizing the 2-DFT structure described above, a larger 2k (k is a natural number)-DFT structure can be constructed. More specifically, a 2k-DFT structure can be constructed by cascading k 2-DFT structures. For example, a 4-DFT structure can be constructed by cascading two 2-DFT structures.

[0193] Referring to Fig. 18, 1810 at the top of Fig. 18 represents an input sample of a 4-point IFFT structure, and the operation timing of the corresponding signal is illustrated at 1810 at the bottom of Fig. 18. In addition, the operation timing corresponding to 1820 at the top of Fig. 18 is illustrated as 1820 at the bottom of Fig. 18, and further, the operation timing corresponding to 1823 at the top of Fig. 18 is illustrated as 1830 at the bottom of Fig. 18. The output value of 1820 at the top of Fig. 18 can be used as the input of 1830 at the top of Fig. 18.

[0194] According to FIGS. 17 and 18, it can be seen that when the operation cycle of the control signal and sample count for each stage is changed in units of TM clock, signals of TM antenna paths can be processed simultaneously.

[0195] FIG. 19 is a diagram showing an example of an N-point DIT IFFT structure according to various embodiments of the present disclosure.

[0196] Referring to FIG. 19, each half of the N-point IFFT input (1910) configured in bit-reversed order can be input to each N / 2 point-DFT block (1921, 1923). Then, each N / 2 output values ​​(1931, 1933) can be output from each of the N / 2 point-DFT blocks (1921, 1923). Then, each IFFT output can be generated through an operation on each of the N / 2 output values ​​(1931, 1933) from each of the N / 2 point-DFT blocks (1921, 1923). More specifically, each of the output values ​​of the lower N / 2 point-DFT block (1923) of FIG. 19 can be multiplied by a twirl factor (1935). Thereafter, the sum of the output values ​​of the lower N / 2 point-DFT block (1923) of FIG. 19, which are multiplied by the rotator (1935) of each of the output values ​​of the upper N / 2 point-DFT block (1921) of FIG. 19, can be configured as N / 2 IFFT outputs (1951) corresponding to indices 0 to N / 2-1. In addition, the difference values ​​of the output values ​​of the lower N / 2 point-DFT block (1923) of FIG. 19, which are multiplied by the rotator (1935) of each of the output values ​​of the upper N / 2 point-DFT block (1921) of FIG. 19, can be configured as the remaining N / 2 IFFT outputs (1953) corresponding to indices N / 2 to N-1.

[0197] According to Fig. 19, if the order of the sum-difference operations in the last stage of the DIT IFFT structure is reversed, it can be seen that the time-domain Symbol IQ data in the latter part where CP exists can be obtained first. This will be explained in more detail with reference to Fig. 20.

[0198] FIG. 20 is a diagram showing an example of an N-point DIT IFFT structure according to various embodiments of the present disclosure.

[0199] Referring to FIG. 20, each half of the N-point IFFT input (2010) configured in bit-reversed order can be input to each N / 2 point-DFT block (2021, 2023). Then, each N / 2 output values ​​(2031, 2033) can be output from each of the N / 2 point-DFT blocks (2021, 2023). Then, each IFFT output can be generated through an operation on each of the N / 2 output values ​​(2031, 2033) from each of the N / 2 point-DFT blocks (2021, 2023). More specifically, each of the output values ​​of the lower N / 2 point-DFT block (2023) of FIG. 20 can be multiplied by a twirl factor (2035). Thereafter, the difference values ​​for each of the output values ​​of the upper N / 2 point-DFT block (2021) of FIG. 20 and each of the output values ​​of the lower N / 2 point-DFT block (2023) of FIG. 20, which are multiplied by the rotator (2035), can be configured as N / 2 IFFT outputs (2051) corresponding to indices N / 2 to N-1. In addition, the sum of each of the output values ​​of the upper N / 2 point-DFT block (2021) of FIG. 20 and each of the output values ​​of the lower N / 2 point-DFT block (2023) of FIG. 20, which are multiplied by the rotator (2035), can be configured as the remaining N / 2 IFFT outputs (2053) corresponding to indices 0 to N / 2-1.

[0200] Fig. 21 is a diagram illustrating an example of an N-point DIT IFFT structure according to various embodiments of the present disclosure. More specifically, Fig. 21 is a HW block diagram of the structure of Fig. 20 configured in series with 4-BF sub-blocks. In order to change the order of sum-difference in the last operation stage, the last stage, 2-BF_LAST block, can confirm that the signs of the operators are opposite to those of the preceding 2-BF blocks (2130).

[0201] FIG. 22 is a timing diagram showing the operation timing of an N-point DIT IFFT structure according to various embodiments of the present disclosure. FIG. 22 exemplifies a case where the number of antenna paths is 2. Referring to FIG. 22, 2210 and 2220 represent input and output, respectively, and it can be seen that the output for input samples (2211) from 0 to N-1 is output as output (2223) from N / 2 to N-1 and output (2221) from 0 to N / 2-1.

[0202] The DLTD memory is located after the DL_IFFT block, and receives the DL_IFFT output, applies CDD, and inserts CP so that the DL symbol data of all antenna paths become the final output of the LPHY DL block at the same time. Below, the internal operating timing of the DLTD memory according to the range of CDD values ​​and the corresponding required memory size are described.

[0203] FIGS. 23 and 24 are timing diagrams illustrating an example of the internal operation of a DLTD memory according to various embodiments of the present disclosure. More specifically, FIGS. 23 and 24 are diagrams for the case where the CDD applied to all antennas is 0.

[0204] Referring to FIGS. 23 and 24, the sub-section of the (B) section (2310) shown in the input timing includes CP, and the (A) section (2320) appears subsequently. When the CDD is 0, the final output time domain DL Symbol IQ data is composed of the CP - (A) - (B) sections within the (B) section (2310), so the DLTD memory writes the (B) section (2310) to the memory and then reads it from the memory and outputs it when the (A) section (2320) ends. At this time, since the DLTD memory only needs to write the (B) section (2310) of the next symbol after reading the (B) section (2310) by the CP length, the Double memory configuration is not necessary. Therefore, when the CDD of all antennas has a value of 0, the size of the memory required in the DLTD memory block is as shown in the mathematical equation below.

[0205]

[0206] In mathematical expression 11, T represents the number of antennas.

[0207] FIG. 25 is a diagram illustrating an example of a DLTD memory according to various embodiments of the present disclosure. More specifically, FIG. 25 is a diagram regarding the structure of a DLTD memory block when the CDD of all antenna paths is 0.

[0208] Referring to FIG. 25, the DLFD memory may include a memory (2510), a WRIF (2520), an RDIF (2530), and a DLTD_CTRL (2540). First, the memory (2510) of FIG. 25 writes DL symbol IQ data for each antenna path. In addition, the WRIF (2520), the RDIF (2530), and the DLTD_CTRL (2540) for controlling operations in the DLTD memory may be implemented according to pseudocodes as shown in Tables 3 to 5 below, respectively.

[0209]

[0210]

[0211]

[0212] Next, when the range of CDD values ​​applied to all antennas is within (N point / 2-CP), the worst case of DLTD memory block operation is when the CDD value is (N point / 2-CP), so the case where the CDD value is (N point / 2-CP) is explained.

[0213] FIGS. 26 and 27 are timing diagrams illustrating an example of the internal operation of a DLTD memory according to various embodiments of the present disclosure. More specifically, FIGS. 26 and 27 are diagrams for the case where the CDD applied to all antennas is N point / 2-CP.

[0214] Referring to FIGS. 26 and 27, the sub-section of the (B) section (2610) shown in the input timing includes CP, and when the CDD value has a range between 0 and (N point / 2)-CP, the two extremes of the CDD value become 0 and (N point / 2)-CP. Since the CDD value may be different for each antenna, if the memory read starts from the time when the N-CP sample order of the (B) sub-section (2610) appears, all antenna paths can be output at the same time regardless of whether the CDD has any value within the range of 0 and (N point / 2)-CP. At this time, depending on the CDD value, the configuration of the final output time area DL Symbol IQ data becomes the (B)-(A)-(B) section, and while the (B) section (2610) is being read, the (A) section (2620) must be writeable, and when the reading of the (A) section (2620) is completed, the (B) section (2610) must be read, so the memory must be sized to store both (A) and (B). In the read operation area of ​​the second (B) section (2630) of Fig. 27, the DL_IFFT output of the (S+1) symbol must be writeable. In this case, since the reading of the memory area that was storing the (A) section (2620) is completed, if the memory write operation of the (B) section (2630) of the (S+1) symbol is performed in the area that stored the (A) section (2620) of the (S) symbol, the Double memory configuration is not necessary.

[0215] Therefore, if the CDD of all antennas has a value between 0 and (N point)-CP, the size of the memory required in the DLTD memory block is as shown in mathematical expression 12 below.

[0216]

[0217] In mathematical expression 12, T represents the number of antennas.

[0218] When the CDD of the above antenna path has a value within 0 and (N point / 2)-CP, the structure of the DLTD memory block is shown in Fig. 28.

[0219] FIG. 28 is a diagram illustrating an example of a DLTD memory according to various embodiments of the present disclosure. More specifically, FIG. 28 is a diagram regarding the structure of a DLTD memory block when the CDD of all antenna paths has a value within 0 and (N point / 2)-CP.

[0220] Referring to FIG. 28, the DLFD memory may include a memory (2810), a WRIF (2820), an RDIF (2830), and a DLTD_CTRL (2840). First, the memory (2810) of FIG. 28 writes DL symbol IQ data for each antenna path. In addition, the WRIF (2820), the RDIF (2830), and the DLTD_CTRL (2840) for controlling operations in the DLTD memory may be implemented according to pseudocodes as shown in Tables 6 to 8 below, respectively.

[0221]

[0222]

[0223]

[0224] Next, when the range of CDD values ​​applied to all antennas has a value within (N point), the worst case of DLTD memory block operation is when the CDD value is (N point / 2-CP+1), so the case where the CDD value is (N point / 2-CP+1) is explained.

[0225] FIG. 29 is a timing diagram illustrating an example of the internal operation of a DLTD memory according to various embodiments of the present disclosure. More specifically, FIG. 29 is a diagram for the case where the CDD applied to all antennas is (N points / 2-CP+1).

[0226] Referring to Fig. 29, when the CDD value has a range between (N point / 2) - CP+1 at the input timing, the last Sample of the CP to which the CDD value is applied becomes the last Sample of the (A) section (2920). Since all Samples calculated before the last Sample of the (A) section (2920) must be stored in the memory until it is output, the memory Read operation for each Symbol to which CDD and CP are applied operates after the IFFT operation is completed. When the memory Read for the CP section is completed, the IFFT time domain DL Symbol IQ data of the next Symbol is output, but since the memory Read area is not completed for both (A) (2920) and (B) sections (2910), a memory that can store the (C) section (2930) is required. Therefore, in this case, the size of the memory required in the DLTD memory block is as shown in Mathematical Expression 13 below.

[0227]

[0228] In mathematical expression 13, T represents the number of antennas.

[0229] Compared to Equation 9, which represents the existing time domain data memory size, Equation 13 above shows that only 75% of the size is required. However, considering the increase in memory size required to implement DL_IFFT that computes multiple paths, the present disclosure may be inefficient compared to the existing disclosure if the CDD value range is supported from 0 to (N point). Therefore, the present disclosure can be more preferably applied to two cases: the case where all CDD values ​​that can be set for each antenna are 0, and the case where the CDD value range is from 0 to (N point / 2)-CP.

[0230] effect

[0231] The memory usage reduction effect of the structure proposed in this disclosure compared to the existing structure is explained.

[0232] Table 9 below summarizes the memory usage by LPHY-DL structure.

[0233]

[0234] In the table above, each of the factors that determine the memory size is represented as follows.

[0235] IQ: DL Data IQ bitwidth

[0236] N: N-point IFFT

[0237] T: Number of Antennas

[0238] TM = (Clock Frequency) / (Max Sampling Rate)

[0239] Referring to Table 9, in terms of IFFT memory usage, compared to the existing structure that sequentially computes the DL symbol data of each path, it requires more memory usage by a multiple of the antenna MUX rate. However, since the DL time domain memory usage is reduced by 25% and 50% when CDD is all 0 and when CDD has a value within the range of 0 to N / 2-CP, respectively, referring to the total item in Table 9 above, overall, the structure described in the present disclosure can obtain a memory saving effect compared to the existing structure.

[0240] Table 10 below summarizes the memory reduction rates of the existing and improved structures when the LPHY-DL block of an MMU / RU supporting NR scs 30kHz Bandwidth 100M operates at a 245.76MHz clock. Table 10 also shows the memory reduction rates for each structure when TM=2.

[0241]

[0242] Reduction rate (%) = [{(existing structure) - (Type)} / (existing structure)] × 100%

[0243] In the case of operating CDD=0 in all antenna paths in an MMU / RU having a structure in which LPHY-DL exists, if (Improvement Structure 1) is applied, the memory used for IFFT and DL time domain Data memory blocks in LPHY-DL can be reduced by 40%.

[0244] By applying the memory saving method described in this disclosure, benefits such as reducing the cost required for power consumption and heat dissipation of the system, reducing costs by using small and inexpensive components, or alleviating limitations on system features due to limitations in using digital logic device resources can be obtained.

[0245] FIG. 30 is a flowchart illustrating an example of a method performed in an RU according to various embodiments of the present disclosure.

[0246] First, the RU can perform an inverse fast Fourier transform (IFFT) shift on frequency domain (FD) downlink (DL) symbol data (3010).

[0247] Next, the RU can rearrange the IFFT points of the FD DL symbol data on which the IFFT shift is performed in reverse order (3020).

[0248] Thereafter, the RU can perform IFFT based on FD DL symbol data units of multiple antenna paths to convert the FD DL symbol data on which the IFFT shift and rearrangement have been performed into time domain (TD) DL symbol data (3030).

[0249] Next, the RU can apply CDD (Cyclic Delay Diversity) to the TD DL symbol data (3040).

[0250] Next, the RU can insert (add) a CP (Cyclic Prefix) into the TD DL symbol data to which the CDD is applied (3050).

[0251] And, the RU can transmit a signal generated based on the TD DL symbol data on which the CDD application and CP insertion are performed (3060).

[0252] The methods according to the embodiments described in the claims or specification of the present disclosure may be implemented in the form of hardware, software, or a combination of hardware and software.

[0253] When implemented in software, a computer-readable storage medium storing one or more programs (software modules) may be provided. The one or more programs stored in the computer-readable storage medium are configured for execution by one or more processors within an electronic device. The one or more programs include instructions that cause the electronic device to execute methods according to the embodiments described in the claims or specification of the present disclosure.

[0254] These programs (software modules, software) may be stored in random access memory, non-volatile memory including flash memory, read only memory (ROM), electrically erasable programmable read only memory (EEPROM), magnetic disc storage devices, compact disc-ROM (CD-ROM), digital versatile discs (DVDs) or other forms of optical storage devices, magnetic cassettes, or may be stored in memories formed by a combination of some or all of these. In addition, each configuration memory may include multiple copies.

[0255] Additionally, the program may be stored on an attachable storage device that is accessible via a communication network, such as the Internet, an intranet, a local area network (LAN), a wide area network (WAN), a storage area network (SAN), or a combination thereof. Such a storage device may be connected to a device implementing an embodiment of the present disclosure via an external port. Additionally, a separate storage device on the communication network may be connected to a device implementing an embodiment of the present disclosure.

[0256] In the specific embodiments of the present disclosure described above, components included in the disclosure are expressed singularly or plurally, depending on the specific embodiment presented. However, the singular or plural expressions are selected to suit the presented situation for convenience of explanation, and the present disclosure is not limited to singular or plural components. Components expressed in plural may be composed of singular elements, or components expressed in singular may be composed of plural elements.

[0257] While the detailed description of this disclosure has described specific embodiments, it should be understood that various modifications are possible without departing from the scope of this disclosure. Therefore, the scope of this disclosure should not be limited to the described embodiments, but should be defined not only by the scope of the claims described below, but also by equivalents thereof.

Claims

1. A method performed by a RU (Radio Unit) in a wireless communication system, A step of performing an inverse fast Fourier transform (IFFT) shift on downlink (DL) symbol data in the frequency domain (FD); A step of rearranging the IFFT points of the FD DL symbol data on which the IFFT shift is performed in reverse order; A step of performing an IFFT based on FD DL symbol data units of multiple antenna paths to convert the FD DL symbol data on which the IFFT shift and rearrangement are performed into time domain (TD) DL symbol data; A step of applying CDD (Cyclic Delay Diversity) to the above TD DL symbol data; A step of inserting (adding) CP (Cyclic Prefix) into the TD DL symbol data to which the CDD is applied; and A method comprising the step of transmitting a signal generated based on the TD DL symbol data on which the CDD application and CP insertion are performed.

2. In paragraph 1, A method wherein the above IFFT is performed through at least one computational stage.

3. In paragraph 1, A method wherein the IFFT point order of the above TD DL symbol data is rearranged again in ascending order after the rearrangement of the IFFT points of the above FD DL symbol data.

4. In paragraph 3, In at least one of the above operation stages, in a operation stage prior to the last operation stage: A method wherein a first DFT (Discrete Fourier Transform) is applied to at least one first input sample corresponding to a front half of IFFT points among at least one input sample corresponding to the entire IFFT points of the FD DL symbol data on which the IFFT shift and the rearrangement are performed, and a second DFT is applied to at least one second input sample corresponding to a back half of IFFT points.

5. In paragraph 4, In at least one of the above operation stages, in the last operation stage: At least one difference, which is obtained by multiplying the values ​​of at least one first output to which the first DFT is applied and at least one second output to which the second DFT is applied by a twirl factor, is composed of a value corresponding to the latter half of the IFFT points among the entire IFFT points of the TD DL symbol data, A method wherein at least one sum of the values ​​obtained by multiplying at least one first output to which the first DFT is applied and at least one second output to which the second DFT is applied by a truncation factor is composed of values ​​corresponding to the first half of the IFFT points among the entire IFFT points of the TD DL symbol data.

6. In paragraph 1, A method wherein the number of the above multiple antenna paths is configured based on the clock frequency and the maximum sampling rate.

7. In the first paragraph, the method, Including a step of storing the TD DL symbol data generated based on the above IFFT, A method in which the size of the memory is configured based on the CDD value.

8. In paragraph 7, A method wherein the value of the above CDD is set to 0, or a value between 0 and the number of total IFFT points divided by 2 minus the value of the above CP.

9. In a wireless communication system, the RU (radio unit) is Transceiver; and Including a controller coupled with the above transceiver, The above controller, A step of performing an inverse fast Fourier transform (IFFT) shift on downlink (DL) symbol data in the frequency domain (FD). A step of rearranging the IFFT points of the FD DL symbol data on which the IFFT shift is performed in reverse order. A step of performing an IFFT based on FD DL symbol data units of multiple antenna paths to convert the FD DL symbol data on which the IFFT shift and rearrangement are performed into time domain (TD) DL symbol data, A step of applying CDD (Cyclic Delay Diversity) to the above TD DL symbol data, A step of inserting (adding) CP (Cyclic Prefix) into the TD DL symbol data to which the CDD is applied, and A RU configured to perform a step of transmitting a signal generated based on the TD DL symbol data on which the CDD application and CP insertion are performed.

10. In paragraph 9, The above IFFT is performed through at least one computational stage, RU.

11. In paragraph 9, The IFFT point order of the above TD DL symbol data is rearranged again after the above rearrangement of the IFFT points of the above FD DL symbol data and is configured in ascending order, RU.

12. In paragraph 11, In at least one of the above operation stages, in a operation stage prior to the last operation stage: An RU, wherein a first DFT (Discrete Fourier Transform) is applied to at least one first input sample corresponding to a front half of IFFT points among at least one input sample corresponding to the entire IFFT points of the FD DL symbol data on which the IFFT shift and the rearrangement are performed, and a second DFT is applied to at least one second input sample corresponding to a back half of IFFT points.

13. In paragraph 11, In at least one of the above operation stages, in the last operation stage: At least one difference, which is obtained by multiplying the values ​​of at least one first output to which the first DFT is applied and at least one second output to which the second DFT is applied by a twirl factor, is composed of a value corresponding to the latter half of the IFFT points among the entire IFFT points of the TD DL symbol data, A method wherein at least one sum of the values ​​obtained by multiplying at least one first output to which the first DFT is applied and at least one second output to which the second DFT is applied by a truncation factor is composed of values ​​corresponding to the first half of the IFFT points among the entire IFFT points of the TD DL symbol data.

14. In paragraph 9, The number of the above multiple antenna paths is configured based on the clock frequency and the maximum sampling rate, RU.

15. In the 9th paragraph, the controller, Further configured to perform a step of storing the TD DL symbol data generated based on the above IFFT, The size of the above memory is configured as RU based on the CDD value.

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