Data transmission method and apparatus, electronic device, and readable storage medium

Abstract

Embodiments of the present application relate to the technical field of computers, and provide a data transmission method and apparatus, an electronic device, and a readable storage medium. The method comprises: when a data acquisition condition is met, using a logic reading module to acquire target data in a mass storage unit; according to storage addresses of the target data in the mass storage unit, packaging the target data to obtain a target file, wherein in the target file, the target data has one-to-one correspondence to the storage addresses; and sending the target file to a target device, so that the target device parses the target file for use. The embodiments of the present application provide a feasible implementation mode for reading configuration data from a mass storage unit of a programmable logic chip and sending the configuration data to a target device, thereby improving the efficiency of reading the configuration data from the programmable logic chip and sending the configuration data to the target device.

Description

Data transmission method, device, electronic device and readable storage medium

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on October 17, 2023, with application number 202311345094.1 and invention name “A data transmission method, device, electronic device and readable storage medium”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of computer technology, and in particular to a data transmission method, device, electronic device, and readable storage medium. Background Art

[0003] Readback technology plays a key role in the design and verification of Field-Programmable Gate Arrays (FPGAs). It allows configuration data from FPGA chips to be read into simulation software for verification, debugging, and backup.

[0004] Currently, FPGA vendors typically provide FPGA development tools and command-line options that allow users to perform readback operations. These operations typically allow users to read configuration data from the FPGA into an external storage device for subsequent processing.

[0005] However, in addition to conventional logic configurations, FPGA chips may also contain some large-capacity storage units, such as Xilinx's UltraRAM (URAM). Current readback technology cannot read data from large-capacity storage units.

[0006] Summary of the Invention

[0007] The embodiments of the present application provide a data transmission method, device, electronic device and readable storage medium, which can solve the problem in the related art that data cannot be read from the large-capacity storage unit of the programmable logic chip.

[0008] To address the above-mentioned issues, an embodiment of the present application discloses a data transmission method, which is applied to a programmable logic chip. The programmable logic chip includes a design to be tested, a logic read module, and a large-capacity storage unit. The large-capacity storage unit is used to store configuration data of the design to be tested. The logic read module and the large-capacity storage unit are arranged in parallel and are jointly connected to a data output port of the design to be tested. The method includes:

[0009] When a data acquisition condition is met, the target data in the large-capacity storage unit is acquired by using the logic reading module;

[0010] Packing the target data according to the storage address of the target data in the large-capacity storage unit to obtain a target file; in the target file, the target data corresponds to the storage address one by one;

[0011] The target file is sent to a target device so that the target device can parse the target file.

[0012] On the other hand, an embodiment of the present application discloses a data transmission device, which is applied to a programmable logic chip. The programmable logic chip includes a design to be tested, a logic read module, and a large-capacity storage unit. The large-capacity storage unit is used to store configuration data of the design to be tested. The logic read module and the large-capacity storage unit are parallel and jointly connected to a data output port of the design to be tested. The device includes:

[0013] an acquisition module, configured to acquire target data in the large-capacity storage unit using the logic reading module when a data acquisition condition is met;

[0014] a packaging module, configured to package the target data according to the storage address of the target data in the large-capacity storage unit to obtain a target file; in the target file, the target data corresponds to the storage address in a one-to-one manner;

[0015] The sending module is used to send the target file to the target device so that the target device can parse the target file.

[0016] On the other hand, an embodiment of the present application further discloses an electronic device, which includes a processor, a memory, a communication interface and a communication bus, wherein the processor, the memory and the communication interface communicate with each other through the communication bus; the memory is used to store executable instructions, and the executable instructions enable the processor to execute the aforementioned data transmission method.

[0017] An embodiment of the present application further provides a computer program, comprising computer-readable code, which, when executed on a computing and processing device, causes the computing and processing device to execute the aforementioned data transmission method.

[0018] An embodiment of the present application further discloses a readable storage medium in which the aforementioned computer program is stored. When the instructions in the readable storage medium are executed by a processor of an electronic device, the electronic device is enabled to execute the aforementioned data transmission method.

[0019] The embodiments of the present application include the following advantages:

[0020] An embodiment of the present application provides a data transmission method. By adding a logic reading module to a programmable logic chip, the programmable logic chip can use the logic reading module to obtain target data from a large-capacity storage unit of the programmable logic chip when data acquisition conditions are met. The target data is packaged into a target file according to the storage address of the target data in the large-capacity storage unit, and the configuration data in the large-capacity storage unit is read to a target device in the form of the target file. This provides a practical and feasible implementation method for reading configuration data from the large-capacity storage unit of the programmable logic chip to the target device, thereby improving the efficiency of reading configuration data from the programmable logic chip to the target device.

[0021] The above description is only an overview of the technical solution of the present application. In order to more clearly understand the technical means of the present application, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments of the present application. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0023] FIG1 is a flowchart of a data transmission method according to an embodiment of the present invention;

[0024] FIG2 is a schematic diagram of the architecture of a data transmission system of the present application;

[0025] FIG3 is a schematic diagram of the architecture of another data transmission system of the present application;

[0026] FIG4 is a structural block diagram of a data transmission device of the present application;

[0027] FIG5 is a structural block diagram of an electronic device for data transmission provided by an example of the present application;

[0028] FIG6 schematically shows a block diagram of a computing and processing device for executing the method according to the present application;

[0029] FIG7 schematically shows a storage unit for storing or carrying program codes for implementing the method according to the present application. Specific embodiments

[0030] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0031] The terms "first", "second", etc. in the specification and claims of this application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first", "second", etc. are generally of one type, and the number of objects is not limited. For example, the first object can be one or more. In addition, the term "and / or" in the specification and claims is used to describe the association relationship of associated objects, indicating that three relationships can exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. In the embodiments of this application, the term "multiple" refers to two or more, and other quantifiers are similar.

[0032] Method Example

[0033] 1 , a flowchart of an embodiment of a data transmission method of the present application is shown. The method may specifically include the following steps:

[0034] Step 101: When a data acquisition condition is met, the target data in the large-capacity storage unit is acquired by using the logic reading module.

[0035] Step 102: Pack the target data according to the storage address of the target data in the large-capacity storage unit to obtain a target file; in the target file, the target data corresponds to the storage address one by one.

[0036] Step 103: Send the target file to the target device so that the target device can parse the target file.

[0037] The data transmission method provided in the embodiment of the present application can be applied to a programmable logic chip, which includes a design to be tested, a logic read module, and a large-capacity storage unit; the large-capacity storage unit is used to store the configuration data of the design to be tested, and the logic read module and the large-capacity storage unit are parallel and jointly connected to the data output port of the design to be tested. Among them, the programmable logic chip can be an FPGA chip, and the design to be tested (Design Under Test, DUT) is a hardware design running on the FPGA chip, which is the circuit design or implementation to be tested in the prototype verification. The large-capacity storage unit can be URAM, or it can be other large-capacity storage units provided by other FPGA manufacturers, and the embodiment of the present application does not specifically limit this.

[0038] The logic read module is a module for reading configuration data in a large-capacity storage unit in an embodiment of the present application. The logic read module is parallel to the large-capacity storage unit and is jointly connected to the data output port of the design to be tested. It is used to obtain the target data stored in the large-capacity storage unit by the design to be tested when the data acquisition conditions are met, and package the target data according to the storage address of the target data in the large-capacity storage unit to obtain the target file, and send the target file to the target device.

[0039] In an embodiment of the present application, the logic read module may include but is not limited to an integrated logic analyzer (ILA), SignalTap, a virtual input / output (VIO) port, a logic read (ReadLogic) device, etc. Among them, the virtual input / output port is set in conjunction with the logic read device, and the virtual input / output port is often used in programmable logic chips to test, debug and verify circuits. It allows designers to simulate and operate the input and output of the circuit in a software manner without actually connecting physical signals, providing a more flexible and efficient testing and debugging method. SignalTap is a hardware-based logic analysis tool that allows designers to monitor and analyze signals inside programmable logic chips in real time.

[0040] The target device may be a personal computer (PC) device installed with simulation software, or an external storage device other than a programmable logic chip, which is not specifically limited in the embodiments of the present application.

[0041] It should be noted that the programmable logic chip can establish a connection with the target device through any one of a Universal Serial Bus (USB) interface, an Ethernet interface, and an optical fiber interface.

[0042] 2 , which shows a schematic diagram of the architecture of a data transmission system of the present application, includes a programmable logic chip 20 and a target device 30 . The programmable logic chip 20 establishes a connection with the target device 30 to send a target file to the target device 30 .

[0043] The programmable logic chip 20 includes a design under test 201 , a large-capacity storage unit 202 and a logic read module 203 . The logic read module 203 and the large-capacity storage unit 202 are arranged in parallel and connected to the data output port of the design under test 201 .

[0044] In an embodiment of the present application, when the programmable logic chip meets the data acquisition conditions during operation, the logic read module can be used to obtain target data from the mass storage unit. The target data is part of or all of the data stored in the mass storage unit, and the data stored in the mass storage unit is the configuration data of the design to be tested.

[0045] Among them, a preset cache area corresponding to the logic read module can be set. After the programmable logic chip executes step 101 to obtain the target data, it can temporarily store the target data in the preset cache area. When the data sending conditions are met, step 102 is executed to obtain the target file, and step 103 is executed to send the target file to the target device; of course, the preset cache area can also be not set. After the programmable logic chip executes step 101 to obtain the target data, it can directly execute steps 102 and 103 to send the target file corresponding to the target data to the target device.

[0046] It should be noted that when a preset cache area is provided, the logic read module can be either an integrated logic analyzer or a SignalTap, and the preset cache area is the storage space allocated in the logic read module. When no preset cache area is provided, the logic read module can be a virtual input / output port and a logic read device configured in conjunction, wherein the virtual input / output port is connected to the mass storage unit via the logic read device.

[0047] The conditions for the programmable logic chip to execute step 102 and step 103, that is, the data acquisition conditions, may include but are not limited to: the programmable logic chip captures the read-back signal for the large-capacity storage unit, the programmable logic chip runs to a preset breakpoint, etc.

[0048] In an embodiment of the present application, when packaging target data according to the storage address of the target data in the large-capacity storage unit, the programmable logic chip can first determine the storage address of the target data in the large-capacity storage unit, and then package the target data and the storage address into a target file in a one-to-one correspondence.

[0049] The programmable logic chip can determine the storage address of the target data in the large-capacity storage unit based on the write signal when the design to be tested writes configuration data into the large-capacity storage unit, or it can determine the storage address of the target data in the large-capacity storage unit by traversing the large-capacity storage unit. The embodiment of the present application does not specifically limit the method by which the programmable logic chip determines the storage address.

[0050] In an embodiment of the present application, the programmable logic chip can package the target data into a file in csv format according to the storage address, or it can package the target data into a file in txt format or excel format. The specific file format of the target file can be determined based on the packaging logic provided by the programmable logic chip manufacturer, and the embodiment of the present application does not make any specific limitations on this.

[0051] After receiving the target file, the target device may parse the target file based on a parsing logic corresponding to the file format of the target file, and use the target data in the parsed target file.

[0052] In the case where the target device is a personal computer device installed with simulation software, the target device may include a parsing module, simulation software and a cache area corresponding to the simulation software (for example, a sys_tb.v file). The parsing module is used to parse the target file and store the target data and storage address in the parsed target file into the cache area, so that the simulation software can perform verification, debugging, backup and other operations on the design to be tested based on the target data. Specifically, when the target device receives the target file sent by the programmable logic chip, it first determines the file format of the target file and parses the target file into a target format supported by the simulation software based on the parsing logic corresponding to the file format; and writes the target data and storage address in the parsed target file into the cache area corresponding to the simulation software.

[0053] As an example, the simulation software installed in the target device is ModelSim, and the large-capacity storage unit is URAM. When the target device receives the target file sent by the programmable logic chip, it first determines that the file format of the target file is in csv format (for example, ila_uram-state.csv), and parses the target file into a target format supported by ModelSim (for example, uram_rb_dump.py) based on the parsing logic corresponding to the csv format; the target data and storage address in the parsed target file are written to the cache area corresponding to the simulation software. For example, the cache area can be a sys_tb.v file or other forms of cache areas, and the storage format of the target data and storage address in the cache area can be loan_en, rb_addr, rb_wdata. Referring to Table 1, the correspondence between the target data and storage address in the cache area corresponding to the simulation software in this application is shown.

[0054] Table 1

[0055] It should be noted that the correspondence between target data and storage addresses shown in Table 1 is only an example. In actual application scenarios, different target data may have different data contents and storage addresses.

[0056] In an embodiment of the present application, when the target device is an external storage device, the target device may include a parsing module and a storage area. The parsing module is used to parse the target file and store the target data and storage address in the parsed target file in the storage area.

[0057] The data transmission method provided in the embodiment of the present application adds a logic reading module to the programmable logic chip, so that when the data acquisition conditions are met, the programmable logic chip can use the logic reading module to obtain target data from the large-capacity storage unit of the programmable logic chip, and package the target data into a target file according to the storage address of the target data in the large-capacity storage unit, and read the configuration data in the large-capacity storage unit to the target device in the form of the target file. This provides a practical and feasible implementation method for reading configuration data from the large-capacity storage unit of the programmable logic chip to the target device, and improves the efficiency of reading configuration data from the programmable logic chip to the target device.

[0058] Optionally, the data acquisition condition includes at least one of the following:

[0059] A write signal corresponding to the large-capacity storage unit is captured, and the write signal is valid;

[0060] A readback signal for the mass storage unit is captured.

[0061] In the embodiment of the present application, when the write signal corresponding to the mass storage unit is valid, indicating that the configuration data of the design to be tested has been written to the mass storage unit, the programmable logic chip can use the logic read module to obtain the target data stored in the mass storage unit and the storage address of the target data in the mass storage unit based on the write signal. In this case, the target data is the configuration data corresponding to the write signal.

[0062] The readback signal can be a readback signal generated based on the Readback technology. Specifically, the readback signal can be a signal generated by the target device and sent to the programmable logic chip when the target data readback conditions are met. The readback signal can also be a signal generated by the programmable logic chip when the target data readback conditions are met. In this case, the target data is the configuration data corresponding to the readback signal.

[0063] The data write-back conditions include, but are not limited to: an error in the design under test, the running time of the design under test reaching a preset time period, etc.

[0064] It is understandable that the programmable logic chip can use the logic read module to obtain target data in the mass storage unit each time data is written to the mass storage unit or when data in the mass storage unit needs to be written back to the target device.

[0065] Specifically, the programmable logic chip can use the logic read module to obtain the target data in the mass storage unit each time it captures a write signal corresponding to the mass storage unit and the write signal is valid. The programmable logic chip can also use the logic read module to obtain the target data in the mass storage unit each time it captures a readback signal for the mass storage unit.

[0066] Among them, the programmable logic chip can capture the write signal or read back signal corresponding to the large-capacity storage unit through the logic read module; the programmable logic chip can also capture the write signal or read back signal corresponding to the large-capacity storage unit through other functional modules other than the logic read module, and the embodiments of the present application do not specifically limit this.

[0067] Optionally, in step 101, when a data acquisition condition is met, acquiring target data in the large-capacity storage unit by using the logic reading module includes:

[0068] Step 1011: When the data acquisition condition is that a write signal corresponding to the large-capacity storage unit is captured and the write signal is valid, use the logic read module to record the write address and the data to be written carried by the write signal.

[0069] Step 1012: Determine the data to be written as target data.

[0070] Step 1013: Determine the write address as the storage address of the target data in the large-capacity storage unit.

[0071] In an embodiment of the present application, a write signal carries the data to be written and the write address of the data to be written in the large-capacity storage unit. The write data and the write address correspond one-to-one, and a write signal can carry at least one set of data to be written and the write address corresponding to the data to be written.

[0072] It can be understood that when the data acquisition condition is to capture the write signal corresponding to the large-capacity storage unit and the write signal is valid, the logic read module can directly determine the target data and storage address based on the data to be written and the write address carried in the write signal, without having to obtain the target data and storage address by accessing the large-capacity storage unit, thereby improving the efficiency of using the logic read module to obtain the target data in the large-capacity storage unit.

[0073] Specifically, when the write signal corresponding to the large-capacity storage unit is captured and the write signal is valid, the logic read module can record the data to be written and the write address in the write signal according to the one-to-one correspondence between the data to be written and the write address, and determine the data to be written as the target data, and determine the write address corresponding to the data to be written as the storage address of the target data in the large-capacity storage unit.

[0074] Optionally, in step 101, when a data acquisition condition is met, acquiring target data in the large-capacity storage unit by using the logic reading module includes:

[0075] Step 1014: When the data acquisition condition is that a read-back signal for the large-capacity storage unit is captured, the large-capacity storage unit is traversed by the logic read module to read the target data stored in the large-capacity storage unit.

[0076] In the embodiment of the present application, the read-back signal may be used to instruct the logic read module to read part or all of the data stored in the large-capacity storage unit.

[0077] Specifically, when a read-back signal for a large-capacity storage unit is captured and the read-back signal is used to instruct the logic read module to read all the data stored in the large-capacity storage unit, the programmable logic chip can use the logic read module to traverse the large-capacity storage unit, read all the data stored in the large-capacity storage unit, and use all the read data as target data.

[0078] When a read back signal for a large-capacity storage unit is captured and the read back signal is used to instruct the logic read module to read part of the data stored in the large-capacity storage unit, the read back signal can carry the storage address corresponding to the target data to be read. The programmable logic chip can use the logic read module to traverse the large-capacity storage unit based on the storage address carried by the read back signal and read the target data from the storage address.

[0079] Optionally, the logic reading module is configured with a preset storage space; before packaging the target data according to the storage address of the target data in the large-capacity storage unit to obtain the target file in step 102, the method further includes:

[0080] Step S11 : storing the target data into the preset storage space according to the storage address of the target data in the large-capacity storage unit.

[0081] In this embodiment of the present application, if the logic read module is configured with a preset storage space, the programmable logic chip can use the logic read module to retrieve the target data from the mass storage unit and then store the target data in the preset storage space. Thereafter, if the conditions for executing steps 102 and 103 are met, the programmable logic chip uses the logic read module to read the target data from the preset storage space and executes steps 102 and 103.

[0082] The usage depth of the preset storage space is the same as the usage depth of the large-capacity storage unit. For example, when the usage depth of the large-capacity storage unit is 4096, the preset storage space with a usage depth of 4096 can be configured for the logical read module accordingly.

[0083] It should be noted that in step 101, while the programmable logic chip uses the logic reading module to obtain the target data in the large-capacity storage unit, it can also record the storage address corresponding to each group of target data, and store the target data and storage address in a preset storage space in a one-to-one correspondence.

[0084] In an embodiment of the present application, when the logic read module is an integrated logic analyzer or SignalTap, a preset storage space can be configured in the integrated logic analyzer or SignalTap; when the logic read module is a virtual input / output port and a logic read device that are arranged in conjunction with each other, a preset storage space can be configured in the logic read device.

[0085] Optionally, the logic read module includes a virtual input / output interface and a logic read device; and in step 101, when a data acquisition condition is met, acquiring target data in the large-capacity storage unit by using the logic read module includes:

[0086] Step 1015: When the data acquisition condition is met, use the logical read device to acquire the target data in the large-capacity storage unit.

[0087] Step 1016: Utilize the virtual input / output interface to obtain the target data from the logic read device according to a preset cycle.

[0088] The step 102 of packaging the target data according to the storage address of the target data in the large-capacity storage unit to obtain a target file includes:

[0089] Step 1021: Use the virtual input / output interface to package the target data and the storage address of the target data in the large-capacity storage unit to obtain a target file.

[0090] Step 103 of sending the target file to the target device includes:

[0091] Step 1031: Send the target file to the target device using the virtual input / output interface.

[0092] 3 shows a schematic diagram of the architecture of another data transmission system of the present invention. The system includes a programmable logic chip 20 and a target device 30. The programmable logic chip 20 includes a design under test 201, a mass storage unit 202, and a logic read module 203. The logic read module 203 includes a logic read device 2031 and an analog input / output port 2032.

[0093] Specifically, the logic read device is connected to the large-capacity storage unit and is used to obtain target data in the large-capacity storage unit when the data acquisition condition is met, so that the virtual input and output interface can obtain the target data from the logic read device according to a preset cycle.

[0094] Among them, the logic read device is configured with a preset storage space. After the programmable logic chip uses the logic read device to obtain the target data in the large-capacity storage unit, it can store the target data in the preset storage space; thereafter, the programmable logic chip can use the virtual input and output interface to obtain the target data from the preset storage space of the logic read device according to a preset cycle.

[0095] It should be noted that the preset period can be a clock period of the programmable logic chip, or a period consisting of multiple clock periods. In the embodiment of the present application, a preset breakpoint can be set at the preset period. When the programmable logic chip reaches the preset breakpoint, the programmable logic chip is interrupted and the programmable logic chip uses the virtual input and output interface to traverse the logic read device and obtain the target data from the logic read device.

[0096] In the embodiment of the present application, when the logic read module is an integrated logic analyzer or SignalTap, the logic read module occupies a relatively large circuit area due to the need to configure a preset storage space. Furthermore, due to the presence of the preset storage space, the logic read module can package the target data according to the storage address of the target data in the mass storage unit during normal operation of the programmable logic chip, obtain a target file, and send the target file to the target device. Therefore, no additional data readback time is required, resulting in high data readback efficiency.

[0097] In the case where the logic read module includes a virtual input / output port and a logic read device, there is no need to configure preset storage space for the virtual input / output interface, so the virtual input / output port occupies a smaller circuit area. However, when using the virtual input / output interface to obtain target data from the logic read device, the operation of the programmable logic chip needs to be interrupted, and the data read-back time is longer.

[0098] In actual application, the logic read module can be flexibly determined based on the circuit area of ​​the programmable logic chip and the efficiency requirement of reading data back to the target device, and the embodiments of the present application do not specifically limit this.

[0099] As an example, the design to be tested is NutShell. After comprehensive implementation, NutShell uses four integrated logic analyzers. These integrated logic analyzers all come from the array_3_ext module in TopMain.v. The programmable logic chip can capture the write signal corresponding to the large-capacity storage unit and, when the write signal is valid (write_enable), use the logic read module to obtain the target data in the large-capacity storage unit and the storage address (addr+data) corresponding to the target data. The specific implementation process is as follows:

[0100] As shown in the above code, the target data sent to the URAM by the design under test and the storage address of the target data can be easily intercepted through "reg[255:0]ram[4095:0]".

[0101] In summary, the embodiments of the present application provide a data transmission method. By adding a logic reading module in a programmable logic chip, the programmable logic chip can use the logic reading module to obtain target data from the large-capacity storage unit of the programmable logic chip when the data acquisition conditions are met, and package the target data into a target file according to the storage address of the target data in the large-capacity storage unit, and read the configuration data in the large-capacity storage unit to the target device in the form of the target file, which provides a practical and feasible implementation method for reading configuration data from the large-capacity storage unit of the programmable logic chip to the target device, and improves the efficiency of reading configuration data from the programmable logic chip to the target device.

[0102] It should be noted that for the method embodiments, for the sake of simplicity, they are all expressed as a series of action combinations, but those skilled in the art should be aware that the embodiments of the present application are not limited by the order of the actions described, because according to the embodiments of the present application, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions involved are not necessarily required by the embodiments of the present application.

[0103] Device embodiment

[0104] 4 shows a block diagram of a data transmission device of the present application, which is applied to a programmable logic chip. The programmable logic chip includes a design to be tested, a logic read module, and a large-capacity storage unit. The large-capacity storage unit is used to store configuration data of the design to be tested. The logic read module and the large-capacity storage unit are parallel and connected to the data output port of the design to be tested. The device may specifically include:

[0105] An acquisition module 401 is configured to acquire target data in the large-capacity storage unit using the logic reading module when a data acquisition condition is met;

[0106] A packing module 402 is configured to pack the target data according to the storage address of the target data in the large-capacity storage unit to obtain a target file; in the target file, the target data corresponds to the storage address in a one-to-one manner;

[0107] The sending module 403 is configured to send the target file to a target device so that the target device can parse the target file.

[0108] Optionally, the data acquisition condition includes at least one of the following:

[0109] A write signal corresponding to the large-capacity storage unit is captured, and the write signal is valid;

[0110] A readback signal for the mass storage unit is captured.

[0111] Optionally, the acquisition module 401 includes:

[0112] a recording submodule, configured to, when a data acquisition condition is that a write signal corresponding to the large-capacity storage unit is captured and the write signal is valid, use the logic reading module to record the write address and the data to be written carried by the write signal;

[0113] A first determining submodule, configured to determine the data to be written as target data;

[0114] The second determining submodule is configured to determine the write address as a storage address of the target data in the large-capacity storage unit.

[0115] Optionally, the acquisition module 401 includes:

[0116] The reading submodule is configured to, when the data acquisition condition is that a read-back signal for the large-capacity storage unit is captured, traverse the large-capacity storage unit using the logic reading module to read the target data stored in the large-capacity storage unit.

[0117] Optionally, the logic reading module is configured with a preset storage space; the device further includes:

[0118] The storage module is used to store the target data into the preset storage space according to the storage address of the target data in the large-capacity storage unit.

[0119] Optionally, the logic reading module includes a virtual input and output interface and a logic reading device; the acquisition module 401 includes:

[0120] A first acquisition submodule is configured to acquire target data in the large-capacity storage unit using the logic read device when a data acquisition condition is met;

[0121] A second acquisition submodule, configured to acquire the target data from the logic read device according to a preset period using the virtual input and output interface;

[0122] The packaging module 402 includes:

[0123] a packing submodule, configured to pack the target data and the storage address of the target data in the large-capacity storage unit using the virtual input and output interface to obtain a target file;

[0124] The sending module 403 includes:

[0125] The sending submodule is used to send the target file to the target device using the virtual input and output interface.

[0126] Optionally, the reading submodule is specifically used to:

[0127] When the read-back signal is used to instruct the logic read module to read all data stored in the large-capacity storage unit, the logic read module is used to traverse the large-capacity storage unit, read all data stored in the large-capacity storage unit, and use the read data as the target data.

[0128] Optionally, the reading submodule is specifically used to:

[0129] When the readback signal is used to instruct the logic read module to read part of the data stored in the large-capacity storage unit, the logic read module is used to traverse the large-capacity storage unit based on the storage address carried by the readback signal and read the target data from the storage address.

[0130] As for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0131] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, i.e., they may be located in one location or distributed across multiple network units. Some or all of the modules may be selected based on actual needs to achieve the objectives of the present embodiment. Persons of ordinary skill in the art will be able to understand and implement the present invention without inventive effort.

[0132] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0133] Regarding the processor in the above embodiment, the specific manner in which each module performs operations has been described in detail in the embodiment of the method and will not be elaborated here.

[0134] Referring to Figure 5, there is a block diagram of an electronic device for data transmission provided in an embodiment of the present application. As shown in Figure 5, the electronic device includes: a processor, a memory, a communication interface, and a communication bus. The processor, the memory, and the communication interface communicate with each other via the communication bus. The memory is used to store executable instructions, which enable the processor to execute the data transmission method of the aforementioned embodiment.

[0135] The processor may be a CPU (Central Processing Unit), a general-purpose processor, a DSP (Digital Signal Processor), an ASIC (Application Specific Integrated Circuit), an FPGA (Field Programmable Gate Array), or other programmable devices, transistor logic devices, hardware components, or any combination thereof. The processor may also be a combination that implements computing functions, such as a combination of one or more microprocessors, a combination of a DSP and a microprocessor, etc.

[0136] The communication bus may include a path for transmitting information between the memory and the communication interface. The communication bus may be a PCI (Peripheral Component Interconnect) bus or an EISA (Extended Industry Standard Architecture) bus, for example. The communication bus may be categorized as an address bus, a data bus, a control bus, etc. For ease of illustration, FIG5 shows only one line, but this does not imply that there is only one bus or only one type of bus.

[0137] The memory may be a ROM (Read Only Memory) or other types of static storage devices that can store static information and instructions, a RAM (Random Access Memory) or other types of dynamic storage devices that can store information and instructions, or an EEPROM (Electrically Erasable Programmable Read Only), a CD-ROM (Compact Disa Read Only), a magnetic tape, a floppy disk, an optical data storage device, etc.

[0138] The various component embodiments of the present application can be implemented in hardware, or in a software module running on one or more processors, or in a combination thereof. It will be appreciated by those skilled in the art that a microprocessor or a digital signal processor (DSP) can be used in practice to implement some or all of the functions of some or all of the components in the computing processing equipment according to the embodiment of the present application. The application can also be implemented as a device or apparatus program (for example, a computer program and a computer program product) for performing a part or all of the methods described herein. Such a program implementing the present application can be stored on a computer-readable medium, or can have the form of one or more signals. Such a signal can be downloaded from an Internet website, or provided on a carrier signal, or provided in any other form.

[0139] For example, FIG6 illustrates a computing device that can implement the methods according to the present application. The computing device typically includes a processor 1010 and a computer program product or computer-readable medium in the form of a memory 1020. Memory 1020 can be an electronic memory such as flash memory, EEPROM (Electrically Erasable Programmable Read-Only Memory), EPROM, a hard disk, or ROM. Memory 1020 has storage space 1030 for program code 1031 for executing any of the method steps described above. For example, storage space 1030 for program code can include individual program codes 1031 for implementing various steps in the method described above. These program codes can be read from or written to one or more computer program products. These computer program products include program code carriers such as hard disks, compact disks (CDs), memory cards, or floppy disks. Such computer program products are typically portable or fixed storage units, as described with reference to FIG7 . This storage unit can have storage segments, storage space, and the like arranged similarly to memory 1020 in the computing device of FIG6 . The program code can, for example, be compressed in a suitable form. Typically, the storage unit includes computer-readable codes 1031 ′, ie, codes that can be read by a processor such as 1010 , which, when executed by a computing device, cause the computing device to perform the steps of the method described above.

[0140] References herein to "one embodiment," "an embodiment," or "one or more embodiments" mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present application. Furthermore, please note that instances of the phrase "in one embodiment" do not necessarily all refer to the same embodiment.

[0141] In the description provided herein, a large number of specific details are described. However, it is understood that the embodiments of the present application can be practiced without these specific details. In some instances, well-known methods, structures, and techniques are not shown in detail so as not to obscure the understanding of this description.

[0142] In the claims, any reference signs placed between brackets shall not be construed as limiting the claim. The word "comprising" does not exclude the presence of elements or steps not listed in the claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The present application may be implemented by means of hardware comprising several different elements and by means of a suitably programmed computer. In a unit claim enumerating several means, several of these means may be embodied by one and the same item of hardware. The use of the words first, second, and third etc. does not indicate any order. These words may be interpreted as names.

[0143] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application.

[0144] An embodiment of the present application also provides a non-temporary computer-readable storage medium, which, when instructions in the storage medium are executed by a processor of an electronic device (server or terminal), enables the processor to execute the data transmission method shown in Figure 1.

[0145] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0146] Those skilled in the art will appreciate that the embodiments of the present application can be provided as methods, devices, or computer program products. Therefore, the present application can adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present application can adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0147] The present application embodiment is described with reference to the flow chart and / or block diagram of the method, terminal device (system), and computer program product according to the embodiment of the present application. It should be understood that each process and / or box in the flow chart and / or block diagram and the combination of the process and / or box in the flow chart and / or block diagram can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor or other programmable data processing terminal device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal device produce a device for realizing the function specified in one process or multiple processes and / or one box or multiple boxes of the flow chart.

[0148] These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing terminal device to operate in a predictable manner, so that the instructions stored in the computer-readable memory produce a manufactured product including an instruction device that implements the functions specified in one or more processes in the flowchart and / or one or more boxes in the block diagram.

[0149] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device so that a series of operating steps are executed on the computer or other programmable terminal device to produce computer-implemented processing, so that the instructions executed on the computer or other programmable terminal device provide steps for implementing the functions specified in one or more processes in the flowchart and / or one or more boxes in the block diagram.

[0150] Although preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they become aware of the basic inventive concepts. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present invention.

[0151] Finally, it should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or terminal device that includes a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or terminal device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or terminal device that includes the element.

[0152] The above is a detailed introduction to a data transmission method, device, electronic device and readable storage medium provided by the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for those skilled in the art, according to the ideas of the present application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A data transmission method, applied to a programmable logic chip, wherein the programmable logic chip includes a design to be tested, a logic read module, and a large-capacity storage unit, wherein the large-capacity storage unit is used to store configuration data of the design to be tested, and the logic read module and the large-capacity storage unit are parallel and jointly connected to a data output port of the design to be tested; the method comprises: When the data acquisition condition is met, the target data in the large-capacity storage unit is acquired by using the logic reading module; Packing the target data according to the storage address of the target data in the large-capacity storage unit to obtain a target file; In the target file, the target data corresponds to the storage address one by one; The target file is sent to a target device so that the target device can parse the target file.

2. The method according to claim 1, wherein: The data acquisition condition includes at least one of the following: A write signal corresponding to the large-capacity storage unit is captured, and the write signal is valid; A read back signal for the mass storage unit is captured.

3. The method according to claim 2, wherein: The method of acquiring the target data in the large-capacity storage unit by using the logic reading module when the data acquisition condition is met includes: When the data acquisition condition is that a write signal corresponding to the large-capacity storage unit is captured and the write signal is valid, using the logic read module to record the write address and the data to be written carried by the write signal; Determining the data to be written as the target data; The write address is determined as a storage address of the target data in the large-capacity storage unit.

4. The method according to claim 2, wherein: The method of acquiring the target data in the large-capacity storage unit by using the logic reading module when the data acquisition condition is met includes: When the data acquisition condition is capturing a read-back signal for the large-capacity storage unit, the large-capacity storage unit is traversed by the logic read module to read the target data stored in the large-capacity storage unit.

5. The method according to claim 3 or 4, wherein: The logic reading module is configured with a preset storage space; Before packaging the target data according to the storage address of the target data in the large-capacity storage unit to obtain the target file, the method further includes: According to the storage address of the target data in the large-capacity storage unit, the target data is stored in the preset storage space.

6. The method according to claim 2, wherein: The logic reading module includes a virtual input and output interface and a logic reading device; The method of acquiring the target data in the large-capacity storage unit by using the logic reading module when the data acquisition condition is met includes: When the data acquisition condition is met, using the logic read device to acquire the target data in the large-capacity storage unit; Using the virtual input / output interface, acquiring the target data from the logic read device according to a preset cycle; Packing the target data according to the storage address of the target data in the large-capacity storage unit to obtain a target file includes: Using the virtual input / output interface, the target data and the storage address of the target data in the large-capacity storage unit are packaged to obtain a target file; The sending the target file to the target device includes: The target file is sent to the target device using the virtual input and output interface.

7. The method according to claim 1, wherein: After acquiring the target data in the large-capacity storage unit by using the logic reading module when the data acquisition condition is met, the method further includes: Temporarily storing the target data in a preset cache area; When the data transmission conditions are met, the step of packaging the target data according to the storage address of the target data in the large-capacity storage unit to obtain the target file is executed.

8. The method according to claim 4, wherein: The step of traversing the large-capacity storage unit using the logic reading module to read the target data stored in the large-capacity storage unit includes: When the read-back signal is used to instruct the logic read module to read all data stored in the large-capacity storage unit, the logic read module is used to traverse the large-capacity storage unit, read all data stored in the large-capacity storage unit, and use the read data as the target data.

9. The method according to claim 4, wherein: The step of traversing the large-capacity storage unit using the logic reading module to read the target data stored in the large-capacity storage unit includes: When the read back signal is used to instruct the logic read module to read part of the data stored in the large capacity storage unit, the logic read module is used to traverse the large capacity storage unit based on the storage address carried by the read back signal to read the target data from the storage address.

10. A data transmission device, applied to a programmable logic chip, wherein the programmable logic chip comprises a design to be tested, a logic read module, and a large-capacity storage unit, wherein the large-capacity storage unit is used to store configuration data of the design to be tested, and the logic read module and the large-capacity storage unit are arranged in parallel and are connected to a data output port of the design to be tested; The device comprises: An acquisition module, configured to acquire target data in the large-capacity storage unit by using the logic reading module when a data acquisition condition is met; A packaging module, used for packaging the target data according to the storage address of the target data in the large-capacity storage unit to obtain a target file; in the target file, the target data and the storage address correspond one to one; The sending module is used to send the target file to the target device so that the target device can parse the target file.

11. The device according to claim 10, wherein: The data acquisition condition includes at least one of the following: A write signal corresponding to the large-capacity storage unit is captured, and the write signal is valid; A read back signal for the mass storage unit is captured.

12. The device according to claim 11, wherein The acquisition module comprises: a recording submodule, configured to, when the data acquisition condition is that a write signal corresponding to the large-capacity storage unit is captured and the write signal is valid, use the logic reading module to record the write address and the data to be written carried by the write signal; A first determining submodule, used to determine the data to be written as target data; The second determining submodule is used to determine the write address as the storage address of the target data in the large-capacity storage unit.

13. The device according to claim 11, wherein: The acquisition module comprises: The reading submodule is used to traverse the large-capacity storage unit using the logic reading module to read the target data stored in the large-capacity storage unit when the data acquisition condition is that the read-back signal for the large-capacity storage unit is captured.

14. The device according to claim 12 or 13, wherein: The logic reading module is configured with a preset storage space; the device also includes: The storage module is used to store the target data into the preset storage space according to the storage address of the target data in the large-capacity storage unit.

15. The device according to claim 11, wherein The logic reading module includes a virtual input and output interface and a logic reading device; The acquisition module comprises: A first acquisition submodule, configured to acquire target data in the large-capacity storage unit by using the logic read device when a data acquisition condition is met; A second acquisition submodule, used to acquire the target data from the logic read device according to a preset period using the virtual input and output interface; The packaging module includes: a packing submodule, used for packing the target data and the storage address of the target data in the large-capacity storage unit by using the virtual input and output interface to obtain a target file; The sending module comprises: The sending submodule is used to send the target file to the target device by using the virtual input and output interface.

16. The device according to claim 13, wherein: The reading submodule is specifically used for: When the read-back signal is used to instruct the logic read module to read all data stored in the large-capacity storage unit, the logic read module is used to traverse the large-capacity storage unit, read all data stored in the large-capacity storage unit, and use the read data as the target data.

17. The device according to claim 13, wherein: The reading submodule is specifically used for: When the read back signal is used to instruct the logic read module to read part of the data stored in the large capacity storage unit, the logic read module is used to traverse the large capacity storage unit based on the storage address carried by the read back signal to read the target data from the storage address.

18. An electronic device, comprising a processor, a memory, a communication interface and a communication bus, wherein the processor, the memory and the communication interface communicate with each other via the communication bus; the memory is used to store executable instructions, and the executable instructions enable the processor to execute the data transmission method as described in any one of claims 1 to 9.

19. A computer program comprising computer readable code which, when executed on a computing processing device, causes the computing processing device to execute the method according to any one of claims 1 to 9.

20. A readable storage medium storing the computer program according to claim 19, wherein when the instructions in the readable storage medium are executed by a processor of an electronic device, the processor is enabled to execute the data transmission method according to any one of claims 1 to 9.

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