Shift register, gate drive circuit, and display device

Abstract

A shift register, a gate drive circuit, and a display device. The shift register comprises: an input sub-circuit (1), configured to control the potentials of a first node and a second node in response to a first clock signal provided by a first clock signal line and a second clock signal provided by a second clock signal line; a first control sub-circuit (2), configured to control the potential of the first node in response to a signal of the second node and a third clock signal provided by a third clock signal line; a second control sub-circuit (3), configured to control the potential of a third node in response to a signal of the first node, the signal of the second node, and a fourth clock signal provided by a fourth clock signal line; and an output sub-circuit (4), configured to output a first output signal in response to the signal of the first node or output a second output signal in response to a signal of the third node.

Description

Shift register, gate drive circuit and display device Technical Field

[0001] The present disclosure belongs to the field of display technology, and particularly relates to a shift register, a gate driving circuit, and a display device. Background Art

[0002] In the field of display technology, a pixel array of a liquid crystal display panel or an organic light emitting diode (OLED) display panel typically includes multiple rows of gate lines and multiple columns of data lines interlaced with the gate lines. The gate lines can be driven by a bound integrated drive circuit.

[0003] Gate Drive on Array (GOA) technology, a commonly used technology in display panels, integrates row-scan drive signal circuitry on the array substrate to achieve progressive gate scanning. As resolution requirements for existing display products continue to increase, higher-resolution displays require more shift registers within their integrated gate drive circuits. This increases the capacitive and resistive loads on clock and power signal lines, affecting the display image.

[0004] Summary of the Invention

[0005] The present disclosure aims to solve at least one of the technical problems existing in the prior art and provides a shift register, a gate driving circuit and a display device.

[0006] In a first aspect, the technical solution adopted to solve the technical problem of the present disclosure is a shift register, comprising a first clock signal line, a second clock signal line, a third clock signal line, a fourth clock signal line, an input subcircuit, a first control subcircuit, a second control subcircuit, and an output subcircuit;

[0007] The input sub-circuit is configured to control the potentials of the first node and the second node in response to a first clock signal provided by the first clock signal line and a second clock signal provided by the second clock signal line;

[0008] The first control subcircuit is configured to control the potential of the first node in response to the signal of the second node and the third clock signal provided by the third clock signal line;

[0009] the second control subcircuit is configured to control the potential of the third node in response to the signal of the first node, the signal of the second node, and the fourth clock signal provided by the fourth clock signal line;

[0010] The output sub-circuit is configured to output a first output signal in response to a signal at the first node, or to output a second output signal in response to a signal at the third node.

[0011] In some embodiments, within one clock cycle, a pulse of the first clock signal precedes a pulse of the second clock signal, a pulse of the second clock signal precedes a pulse of the third clock signal, and a pulse of the third clock signal precedes a pulse of the fourth clock signal.

[0012] In some embodiments, within one clock cycle, a pulse of the first clock signal precedes a pulse of the second clock signal, a pulse of the second clock signal precedes a pulse of the fourth clock signal, and a pulse of the fourth clock signal precedes a pulse of the third clock signal.

[0013] In some embodiments, the first clock signal and the second clock signal have the same timing; the third clock signal has an opposite timing to the first clock signal; and the fourth clock signal and the third clock signal have the same timing.

[0014] In some embodiments, the first clock signal and the second clock signal include a first level; the potential of the first level of the first clock signal is different from the potential of the first level of the second clock signal; and / or,

[0015] The third clock signal and the fourth clock signal include a third level; a potential of the third level of the third clock signal is different from a potential of the third level of the fourth clock signal.

[0016] In some embodiments, the potential of the first level of the first clock signal is lower than the potential of the first level of the second clock signal; and / or,

[0017] The potential of the third level of the third clock signal is lower than the potential of the third level of the fourth clock signal.

[0018] In some embodiments, the first clock signal and the second clock signal further include a second level, the second level being different from the first level; the potential of the second level of the first clock signal is different from the potential of the second level of the second clock signal; and / or,

[0019] The third clock signal and the fourth clock signal further include a fourth level, and the fourth level is different from the third level; and a potential of the fourth level of the third clock signal is different from a potential of the fourth level of the fourth clock signal.

[0020] In some embodiments, the potential of the second level of the first clock signal is greater than the potential of the second level of the second clock signal; and / or,

[0021] The potential of the fourth level of the third clock signal is greater than the potential of the fourth level of the fourth clock signal.

[0022] In some embodiments, the shift register further includes a first power signal line, a second power signal line, a third power signal line, and a fourth power signal line;

[0023] The input subcircuit is electrically connected to the first power signal line, the first control subcircuit is electrically connected to the third power signal line, the second control subcircuit is electrically connected to the fourth power signal line, and the output subcircuit is electrically connected to the second power signal line and the third power signal line.

[0024] In some embodiments, the potential of the first power signal transmitted by the first power signal line is less than the potential of the second power signal transmitted by the second power signal line; the potential of the third power signal transmitted by the third power signal line is less than the potential of the fourth power signal transmitted by the fourth power signal line; and the potential of the second power signal is less than the potential of the third power signal.

[0025] In some embodiments, the potential of the first level of the first clock signal is equal to the potential of the first power signal, and the potential of the second level of the first clock signal is equal to the potential of the fourth power signal;

[0026] The potential of the first level of the second clock signal is equal to the potential of the second power signal, and the potential of the second level of the second clock signal is equal to the potential of the third power signal;

[0027] The potential of the third level of the third clock signal is equal to the potential of the first power signal, and the potential of the fourth level of the third clock signal is equal to the potential of the fourth power signal;

[0028] The potential of the third level of the fourth clock signal is equal to the potential of the second power signal, and the potential of the third level of the fourth clock signal is equal to the potential of the third power signal.

[0029] In some embodiments, the pulse width of the first level of the first clock signal is smaller than the pulse width of the second level; and / or the pulse width of the third level of the third clock signal is smaller than the pulse width of the fourth level.

[0030] In some embodiments, the input subcircuit includes a first transistor, a second transistor, and a third transistor;

[0031] The first electrode of the first transistor is electrically connected to the signal input terminal, the second electrode is electrically connected to the first node, and the control electrode is electrically connected to the first clock signal line;

[0032] A first electrode of the second transistor is electrically connected to the second clock signal line, a second electrode is electrically connected to the second node, and a control electrode is electrically connected to the first node;

[0033] The first electrode of the third transistor is electrically connected to the first power signal line, the second electrode is electrically connected to the second node, and the control electrode is electrically connected to the second clock signal line.

[0034] In some embodiments, the input subcircuit includes a first transistor, a second transistor, and a third transistor;

[0035] The first electrode of the first transistor is electrically connected to the signal input terminal, the second electrode is electrically connected to the first node, and the control electrode is electrically connected to the first clock signal line;

[0036] A first electrode of the second transistor is electrically connected to the first clock signal line, a second electrode is electrically connected to the second node, and a control electrode is electrically connected to the first node;

[0037] The first electrode of the third transistor is electrically connected to the first power signal line, the second electrode is electrically connected to the second node, and the control electrode is electrically connected to the second clock signal line.

[0038] In some embodiments, the input subcircuit includes a first transistor, a second transistor, and a third transistor;

[0039] The first electrode of the first transistor is electrically connected to the signal input terminal, the second electrode is electrically connected to the first node, and the control electrode is electrically connected to the first clock signal line;

[0040] A first electrode of the second transistor is electrically connected to the second clock signal line, a second electrode is electrically connected to the second node, and a control electrode is electrically connected to the first node;

[0041] The first electrode of the third transistor is electrically connected to the first power signal line, the second electrode is electrically connected to the second node, and the control electrode is electrically connected to the first clock signal line.

[0042] In some embodiments, the shift register further includes an isolation subcircuit;

[0043] the isolation subcircuit is configured to isolate the first node from the first control subcircuit electrically connected to the first node; isolate the first node from the output subcircuit electrically connected to the first node; and isolate the second node from the second control subcircuit electrically connected to the second node;

[0044] The first control subcircuit is electrically connected to the fifth node; the output subcircuit is electrically connected to the fifth node; and the second control subcircuit is electrically connected to the fourth node.

[0045] In some embodiments, the isolation subcircuit includes an eleventh transistor and a twelfth transistor;

[0046] The eleventh transistor has a first electrode electrically connected to the second node, a second electrode electrically connected to the fourth node, and a control electrode electrically connected to the first power signal line;

[0047] The first electrode of the twelfth transistor is electrically connected to the first node, the second electrode is electrically connected to the fifth node, and the control electrode is electrically connected to the second power signal line.

[0048] In some embodiments, the isolation subcircuit includes an eleventh transistor and a twelfth transistor;

[0049] The eleventh transistor has a first electrode electrically connected to the second node, a second electrode electrically connected to the fourth node, and a control electrode electrically connected to the first power signal line;

[0050] The first electrode of the twelfth transistor is electrically connected to the first node, the second electrode is electrically connected to the fifth node, and the control electrode is electrically connected to the first power signal line.

[0051] In some embodiments, the first control subcircuit includes a fourth transistor, a fifth transistor, and a third capacitor;

[0052] A first electrode of the fourth transistor is electrically connected to the third clock signal line, a second electrode is electrically connected to the second electrode of the fifth transistor, and a control electrode is electrically connected to the fifth node;

[0053] The first electrode of the fifth transistor is electrically connected to the third power signal line, the second electrode is electrically connected to the first plate of the third capacitor, and the control electrode is electrically connected to the second node;

[0054] The second plate of the third capacitor is electrically connected to the fifth node.

[0055] In some embodiments, the second control subcircuit includes a sixth transistor, a seventh transistor, an eighth transistor and a first capacitor;

[0056] A first electrode of the sixth transistor is electrically connected to the fourth clock signal line, a second electrode is electrically connected to the first electrode of the seventh transistor, and a control electrode is electrically connected to the fourth node and the first plate of the first capacitor;

[0057] A first electrode of the seventh transistor is electrically connected to the second plate of the first capacitor, a second electrode is electrically connected to the third node, and a control electrode is electrically connected to the fourth clock signal line;

[0058] The first electrode of the eighth transistor is electrically connected to the fourth power signal line, the second electrode is electrically connected to the third node, and the control electrode is electrically connected to the first node.

[0059] In some embodiments, the second control subcircuit includes a sixth transistor, a seventh transistor, an eighth transistor, a thirteenth transistor and a first capacitor;

[0060] The first electrode of the sixth transistor is electrically connected to the fourth clock signal line, the second electrode is electrically connected to the first electrode of the seventh transistor, and the control electrode is electrically connected to the fourth node and the first plate of the capacitor;

[0061] A first electrode of the seventh transistor is electrically connected to the second plate of the first capacitor, a second electrode is electrically connected to the third node, and a control electrode is electrically connected to the fourth clock signal line;

[0062] The first electrode of the eighth transistor is electrically connected to the fourth power signal line, the second electrode is electrically connected to the third node, and the control electrode is electrically connected to the first node;

[0063] The first electrode of the thirteenth transistor is electrically connected to the fourth power signal line, the second electrode is electrically connected to the first node, and the control electrode is electrically connected to the preset control terminal.

[0064] In some embodiments, the input subcircuit includes a first transistor, a second transistor, a third transistor, and a fourteenth transistor;

[0065] The first electrode of the first transistor is electrically connected to the signal input terminal, the second electrode is electrically connected to the first node, and the control electrode is electrically connected to the first clock signal line;

[0066] A first electrode of the second transistor is electrically connected to the second clock signal line, a second electrode is electrically connected to the second node, and a control electrode is electrically connected to the first node;

[0067] The first electrode of the third transistor is electrically connected to the first power signal line, the second electrode is electrically connected to the second node, and the control electrode is electrically connected to the second clock signal line;

[0068] The first electrode of the fourteenth transistor is electrically connected to the signal input terminal, the second electrode is electrically connected to the eighth node, and the control electrode is electrically connected to the first clock signal line.

[0069] In some embodiments, the shift register further includes an isolation subcircuit;

[0070] the isolation subcircuit being configured to isolate the first node from the first control subcircuit electrically connected to the first node; isolate the first node from the output subcircuit electrically connected to the first node; isolate the first node from the second control subcircuit electrically connected to the first node; and isolate the second node from the second control subcircuit electrically connected to the second node;

[0071] The first control subcircuit is electrically connected to the fifth node; the output subcircuit is electrically connected to the fifth node; and the second control subcircuit is electrically connected to the fourth node and the fifth node.

[0072] In some embodiments, the input subcircuit includes a first transistor, a second transistor, a third transistor, and a fourteenth transistor;

[0073] The first electrode of the first transistor is electrically connected to the signal input terminal, the second electrode is electrically connected to the first node, and the control electrode is electrically connected to the first clock signal line;

[0074] A first electrode of the second transistor is electrically connected to the first clock signal line, a second electrode is electrically connected to the second node, and a control electrode is electrically connected to the first node;

[0075] The first electrode of the third transistor is electrically connected to the first power signal line, the second electrode is electrically connected to the second node, and the control electrode is electrically connected to the second clock signal line;

[0076] The first electrode of the fourteenth transistor is electrically connected to the signal input terminal, the second electrode is electrically connected to the eighth node, and the control electrode is electrically connected to the second clock signal line.

[0077] In some embodiments, the first control subcircuit includes a fourth transistor, a fifth transistor, a fifteenth transistor, a sixteenth transistor, and a third capacitor;

[0078] A first electrode of the fourth transistor is electrically connected to the third clock signal line, a second electrode is electrically connected to the second electrode of the fifth transistor, and a control electrode is electrically connected to the second plate of the third capacitor;

[0079] The first electrode of the fifth transistor is electrically connected to the third power signal line, the second electrode is electrically connected to the first plate of the third capacitor, and the control electrode is electrically connected to the second node;

[0080] The first electrode of the fifteenth transistor is electrically connected to the eighth node, the second electrode is electrically connected to the first electrode of the sixteenth transistor and the control electrode of the sixteenth transistor, and the control electrode is electrically connected to the first power signal line;

[0081] The second electrode of the sixteenth transistor is electrically connected to the fifth node, and the control electrode is electrically connected to the control electrode of the fourth transistor.

[0082] In some embodiments, the second control subcircuit includes a sixth transistor, a seventh transistor, an eighth transistor, a thirteenth transistor and a first capacitor;

[0083] A first electrode of the sixth transistor is electrically connected to the fourth clock signal line, a second electrode is electrically connected to the first electrode of the seventh transistor, and a control electrode is electrically connected to the fourth node and the first plate of the first capacitor;

[0084] A first electrode of the seventh transistor is electrically connected to the second plate of the first capacitor, a second electrode is electrically connected to the third node, and a control electrode is electrically connected to the fourth clock signal line;

[0085] The first electrode of the eighth transistor is electrically connected to the fourth power signal line, the second electrode is electrically connected to the third node, and the control electrode is electrically connected to the fifth node;

[0086] The first electrode of the thirteenth transistor is electrically connected to the fourth power signal line, the second electrode is electrically connected to the fifth node, and the control electrode is electrically connected to the preset control terminal.

[0087] In some embodiments, the output sub-circuit includes a ninth transistor, a tenth transistor, and a second capacitor;

[0088] The first electrode of the ninth transistor is electrically connected to the third power signal line and the first plate of the second capacitor, the second electrode is electrically connected to the signal output terminal, and the control electrode is electrically connected to the third node;

[0089] The first electrode of the tenth transistor is electrically connected to the second power signal line, the second electrode is electrically connected to the signal output terminal, and the control electrode is electrically connected to the fifth node;

[0090] The second plate of the second capacitor is electrically connected to the third node.

[0091] In a second aspect, an embodiment of the present disclosure further provides a gate drive circuit comprising N cascaded shift registers; except for the first-stage shift register, the signal input end of the i+1-stage shift register is electrically connected to the signal output end of the i-stage shift register; N is a positive integer greater than 1, and i is a positive integer less than or equal to N.

[0092] In some embodiments, the first clock signal line in the shift register at the i-th level is multiplexed as the fourth clock signal line in the shift register at the i+1-th level, the second clock signal line in the shift register at the i-th level is multiplexed as the first clock signal line in the shift register at the i+1-th level, the third clock signal line in the shift register at the i-th level is multiplexed as the second clock signal line in the shift register at the i+1-th level, and the fourth clock signal line in the shift register at the i-th level is multiplexed as the third clock signal line in the shift register at the i+1-th level.

[0093] In some embodiments, the first clock signal line in the shift register at the i-th level is multiplexed as the third clock signal line in the shift register at the i+1-th level, the second clock signal line in the shift register at the i-th level is multiplexed as the fourth clock signal line in the shift register at the i+1-th level, the third clock signal line in the shift register at the i-th level is multiplexed as the first clock signal line in the shift register at the i+1-th level, and the fourth clock signal line in the shift register at the i-th level is multiplexed as the second clock signal line in the shift register at the i+1-th level.

[0094] In a third aspect, an embodiment of the present disclosure further provides a display device, comprising a pixel driving circuit and a gate driving circuit as described in any one of the second aspects, wherein the gate driving circuit is electrically connected to the pixel driving circuit to provide a gate control signal to the pixel driving circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0095] FIG1 is a schematic structural diagram of a shift register provided by an embodiment of the present disclosure;

[0096] FIG2 is a timing diagram of each clock signal line within a clock cycle of Example 1 provided by an embodiment of the present disclosure;

[0097] FIG3 is a timing diagram of each clock signal line within a clock cycle of Example 2 provided by an embodiment of the present disclosure;

[0098] FIG4 is a timing diagram of each clock signal line within a clock cycle of Example 3 provided by an embodiment of the present disclosure;

[0099] FIG5a is a schematic structural diagram of another shift register provided by an embodiment of the present disclosure;

[0100] FIG5 b is a schematic structural diagram of another shift register provided by an embodiment of the present disclosure;

[0101] FIG6 is a circuit diagram of a 12T3C circuit structure provided by an embodiment of the present disclosure;

[0102] FIG7 is a circuit diagram of another 12T3C circuit structure provided by an embodiment of the present disclosure;

[0103] FIG8 is a circuit diagram of a 13T3C circuit structure provided by an embodiment of the present disclosure;

[0104] FIG9 is a circuit diagram of another 13T3C circuit structure provided by an embodiment of the present disclosure;

[0105] FIG10 is a schematic structural diagram of another shift register provided by an embodiment of the present disclosure;

[0106] FIG11 is a circuit diagram of a 16T3C circuit structure provided by an embodiment of the present disclosure;

[0107] FIG12 is a circuit diagram of another 16T3C circuit structure provided by an embodiment of the present disclosure;

[0108] FIG13 is a timing diagram of an exemplary shift register provided by an embodiment of the present disclosure;

[0109] FIG14 is a timing diagram of another exemplary shift register provided in an embodiment of the present disclosure;

[0110] FIG15 is a timing diagram of another exemplary shift register provided in an embodiment of the present disclosure;

[0111] FIG16 is a schematic diagram of a gate driving circuit provided in an embodiment of the present disclosure;

[0112] FIG17 is a schematic diagram of another gate driving circuit provided by an embodiment of the present disclosure;

[0113] FIG18 is a circuit diagram of a cascaded shift register of the 12T3C circuit structure shown in FIG6 according to an embodiment of the present disclosure;

[0114] FIG19 is a circuit diagram of a cascaded shift register of the 13T3C circuit structure shown in FIG8 according to an embodiment of the present disclosure;

[0115] FIG20 is a circuit diagram of a cascaded shift register of the 16T3C circuit structure shown in FIG11 according to an embodiment of the present disclosure;

[0116] FIG21 is a circuit diagram of a cascaded shift register of the 12T3C circuit structure shown in FIG7 according to an embodiment of the present disclosure;

[0117] FIG22 is a circuit diagram of a cascaded shift register of the 13T3C circuit structure shown in FIG9 according to an embodiment of the present disclosure;

[0118] FIG23 is a circuit diagram of a cascade of shift registers of the 16T3C circuit structure shown in FIG12 provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0119] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. The components of the embodiments of the present disclosure generally described and shown in the drawings herein can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present disclosure provided in the drawings is not intended to limit the scope of the disclosure for which protection is sought, but merely represents selected embodiments of the present disclosure. Based on the embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present disclosure.

[0120] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by people with ordinary skills in the field to which this disclosure belongs. The "first", "second" and similar words used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, similar words such as "one", "an" or "the" do not indicate a quantitative limitation, but rather indicate the presence of at least one. Similar words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects.

[0121] In this disclosure, "multiple or several" refers to two or more. "And / or" describes the relationship between associated objects, indicating that three possible relationships exist. For example, "A and / or B" can mean: A exists alone, A and B exist simultaneously, or B exists alone. The character " / " generally indicates that the associated objects are in an "or" relationship.

[0122] In the related art, a shift register is connected to a set of clock signals with opposite timings, and the same clock signal line is used for transmission for clock signals with the same timings. For display products with higher resolution, the more stages of the shift register in the internally integrated gate drive circuit, the more capacitive and resistive loads on the same clock signal line will be. The increase in load will extend the time for the shift register to output the signal, thereby affecting the effective working time of the pixel, and then affecting the display screen. At the same time, the more stages of the shift register in the gate drive circuit, the more transistors are connected to the same clock signal line, and the greater the parasitic capacitance generated, further affecting the display screen. In addition, the more stages of the shift register in the gate drive circuit, the more transistors are connected to the same power signal line, and the increased load can easily cause the power signal transmitted by the power signal line to fluctuate, ultimately resulting in defects such as fine horizontal stripes on the display screen, affecting the display effect.

[0123] In view of this, an embodiment of the present disclosure provides a shift register, which includes a first clock signal line, a second clock signal line, a third clock signal line, a fourth clock signal line, an input sub-circuit, a first control sub-circuit, a second control sub-circuit and an output sub-circuit; the input sub-circuit is configured to control the potential of the first node and the second node in response to the first clock signal provided by the first clock signal line and the second clock signal provided by the second clock signal line; the first control sub-circuit is configured to control the potential of the first node in response to the signal of the second node and the third clock signal provided by the third clock signal line; the second control sub-circuit is configured to control the potential of the third node in response to the signal of the first node, the signal of the second node and the fourth clock signal provided by the fourth clock signal line; the output sub-circuit is configured to output a first output signal in response to the potential of the first node, or to output a second output signal in response to the potential of the third node.

[0124] The shift register provided in the embodiment of the present disclosure includes multiple clock signal lines, namely a first clock signal line, a second clock signal line, a third clock signal line, and a fourth clock signal line. Multiple clock signal lines are used to provide clock signals, dispersing the load on a single clock signal line in the above-mentioned related technologies, thereby reducing product power consumption and improving display effects.

[0125] The specific circuit structure of the shift register provided by the embodiment of the present disclosure is described in detail below.

[0126] Figure 1 is a structural schematic diagram of a shift register provided in an embodiment of the present disclosure. As shown in Figure 1, the shift register includes a first clock signal line CKL1, a second clock signal line CKL2, a third clock signal line CKL3, a fourth clock signal line CKL4, an input sub-circuit 1, a first control sub-circuit 2, a second control sub-circuit 3 and an output sub-circuit 4.

[0127] Among them, the input sub-circuit 1 is electrically connected to the first clock signal line CKL1, the second clock signal line CKL2, the first node N1 and the second node N2; on this basis, the input sub-circuit 1 is configured to control the potential of the first node N1 and the second node N2 in response to the first clock signal CK1 provided by the first clock signal line CKL1 and the second clock signal CK2 provided by the second clock signal line CKL2.

[0128] Exemplarily, as shown in FIG1 , the shift register further includes a signal input terminal Input and a signal output terminal OUT, which are electrically connected to a signal input line and a pixel driving circuit, respectively. The signal input line is used to provide an input signal. The shift register is configured to provide a gate row scanning signal to the pixel driving circuit.

[0129] As shown in FIG1 , the shift register further includes a first power signal line VGL1 for providing a first power signal. An input subcircuit 1 in the shift register is electrically connected to a signal input terminal Input and the first power signal line VGL1. Input subcircuit 1 is configured to respond to a first clock signal CK1 and a second clock signal CK2, and to control the potentials of a first node N1 and a second node N2 based on the input signal and the first power signal.

[0130] Continuing with the figure 1 , the first control sub-circuit 2 is electrically connected to the third clock signal line CKL3, the first node N1 and the second node N2; on this basis, the first control sub-circuit 2 is configured to control the potential of the first node N1 in response to the signal of the second node N2 and the third clock signal CK3 provided by the third clock signal line CKL3.

[0131] For example, as shown in FIG1 , the shift register further includes a third power signal line VGH1 for providing a third power signal. A first control subcircuit 2 in the shift register is electrically connected to the third power signal line VGH1. The first control subcircuit 2 is configured to control the potential of the first node N1 in response to a signal at the second node N2, based on the third clock signal CK3 and the third power signal.

[0132] Continuing with FIG1 , the second control sub-circuit 3 is electrically connected to the first node N1, the second node N2, the third node N3, and the fourth clock signal line CKL4. Based on this, the second control sub-circuit 3 is configured to control the potential of the third node N3 in response to the signal at the first node N1, the signal at the second node N2, and the fourth clock signal CK4 provided by the fourth clock signal line CKL4.

[0133] For example, as shown in FIG1 , the shift register further includes a fourth power signal line VGH2 for providing a fourth power signal. A second control subcircuit 3 in the shift register is electrically connected to the fourth power signal line VGH2. The second control subcircuit 3 is configured to respond to a signal at the first node N1, a signal at the second node N2, and a fourth clock signal CK4, and to control the potential of the third node N3 based on the fourth clock signal CK4 and the fourth power signal.

[0134] 1 , the output sub-circuit 4 is electrically connected to the first node N1 and the third node N3 , and is configured to output a first output signal in response to a signal at the first node N1 , or to output a second output signal in response to a signal at the third node N3 .

[0135] For example, as shown in FIG1 , the shift register further includes a second power signal line VGL2, which is used to provide a second power signal. An output sub-circuit 4 in the shift register is electrically connected to the second power signal line VGL2 and the third power signal line VGH1. The output sub-circuit 4 is configured to output a first output signal in response to a signal at the first node N1 and based on the second power signal. Alternatively, the output sub-circuit 4 is configured to output a second output signal in response to a signal at the third node N3 and based on the third power signal.

[0136] The first output signal and the second output signal can both be used as gate row scanning signals of the pixel driving circuit, and can also be used as input signals of the next stage shift register cascaded to the current stage shift register.

[0137] Exemplarily, the input signal is a pulse signal; the first output signal is a low-level signal, and the second output signal is a high-level signal.

[0138] Exemplarily, the first power signal line VGL1 and the second power signal line VGL2 are the same, and different from the third power signal line VGH1 and the fourth power signal line VGH2. That is, the first power signal and the second power signal are the same and can be transmitted using the same power signal line.

[0139] Exemplarily, the third power signal line VGH1 and the fourth power signal line VGH2 are the same and different from the first power signal line VGL1 and the second power signal line VGL2 .

[0140] For example, the first power signal line VGL1, the second power signal line VGL2, the third power signal line VGH1, and the fourth power signal line VGH2 are all different. In this case, the first power signal and the second power signal can be the same, and the third power signal and the fourth power signal can be the same, but are transmitted using different power signal lines.

[0141] For example, when the first power signal line VGL1, the second power signal line VGL2, the third power signal line VGH1, and the fourth power signal line VGH2 are all different, the first power signal and the second power signal may be the same or different. The third power signal and the fourth power signal may be the same or different. However, the potential of the first power signal and the potential of the second power signal are both lower than the potential of the third power signal and the potential of the fourth power signal.

[0142] The shift register provided by the embodiment of the present disclosure includes multiple clock signal lines, namely the first clock signal line, the second clock signal line, the third clock signal line, and the fourth clock signal line. The multiple clock signal lines are used to provide clock signals to disperse the load on the single clock signal line in the above-mentioned related art. In this way, the number of transistors connected to the single clock signal line can be reduced, so as to shorten the signal output time, reduce the power consumption of the product, and improve the uniformity of the large-screen display quality. In addition, for the same power supply signal, such as the first power supply signal and the second power supply signal, the same power supply signal line (that is, the first power supply signal line VGL1 and the second power supply signal line VGL2 are the same) can be used for transmission; for example, the third power supply signal and the fourth power supply signal can both be transmitted using the same power supply signal line (the third power supply signal line VGH1 and the fourth power supply signal line VGH2 are the same). In this way, the signal line layout space can be reduced, which is conducive to achieving a narrow frame. Alternatively, for the same power supply signal, different power supply signal lines are used for transmission. For example, the first power signal and the second power signal can both be transmitted using different first power signal lines VGL1 and second power signal lines VGL2; and the third power signal and the fourth power signal can both be transmitted using different third power signal lines VGH1 and fourth power signal lines VGH2. This can avoid signal fluctuations caused by excessive load on a single power signal line, which is conducive to improving the stability of signal output.

[0143] In some embodiments, Figure 2 is a timing diagram of each clock signal line within a clock cycle of Example 1 provided in an embodiment of the present disclosure. As shown in Figure 2, within a clock cycle T, the pulse of the first clock signal is before the pulse of the second clock signal, the pulse of the second clock signal is before the pulse of the third clock signal, and the pulse of the third clock signal is before the pulse of the fourth clock signal.

[0144] It should be noted that the "pulse" of the clock signal here refers to the trigger period of the effective level of a clock signal. This disclosure takes the effective level as a low level as an example. A low-level signal corresponding to a rising edge turning into a falling edge is recorded as a pulse of the clock signal.

[0145] Exemplarily, the pulse width of the effective level of the first clock signal, the pulse width of the effective level of the second clock signal, the pulse width of the effective level of the third clock signal, and the pulse width of the effective level of the fourth clock signal are consistent.

[0146] For example, within a clock cycle T, the effective level cut-off time of the first clock signal can be used as the triggering time of the effective level of the second clock signal; the effective level cut-off time of the second clock signal can be used as the triggering time of the effective level of the third clock signal; the effective level cut-off time of the third clock signal can be used as the triggering time of the effective level of the fourth clock signal.

[0147] Exemplarily, within a clock cycle T, there is a preset duration between the effective level cut-off moment of the first clock signal and the effective level triggering moment of the second clock signal; there is a preset duration between the effective level cut-off moment of the second clock signal and the effective level triggering moment of the third clock signal; there is a preset duration between the effective level cut-off moment of the third clock signal and the effective level triggering moment of the fourth clock signal; wherein, the preset duration is less than the duration of the effective level.

[0148] This embodiment uses clock signals with different timings. The timings of the first clock signal, the second clock signal, the third clock signal and the fourth clock signal are changed in sequence. Compared with the situation where the timings are the same, it is possible to avoid signal mutations caused by changing the timings at the same time, which may affect the display effect.

[0149] In some embodiments, Figure 3 is a timing diagram of each clock signal line within a clock cycle of Example 2 provided in an embodiment of the present disclosure. As shown in Figure 3, within a clock cycle T, the pulse of the first clock signal is before the pulse of the second clock signal, the pulse of the second clock signal is before the pulse of the fourth clock signal, and the pulse of the fourth clock signal is before the pulse of the third clock signal.

[0150] For example, within a clock cycle T, the effective level cut-off time of the first clock signal can be used as the triggering time of the effective level of the second clock signal; the effective level cut-off time of the second clock signal can be used as the triggering time of the effective level of the fourth clock signal; the effective level cut-off time of the fourth clock signal can be used as the triggering time of the effective level of the third clock signal.

[0151] Exemplarily, within a clock cycle T, there is a preset duration between the effective level cut-off moment of the first clock signal and the effective level triggering moment of the second clock signal; there is a preset duration between the effective level cut-off moment of the second clock signal and the effective level triggering moment of the fourth clock signal; there is a preset duration between the effective level cut-off moment of the fourth clock signal and the effective level triggering moment of the third clock signal; wherein, the preset duration is less than the duration of the effective level.

[0152] This embodiment uses clock signals with different timings. The timings of the first clock signal, the second clock signal, the fourth clock signal and the third clock signal are changed in sequence. Compared with the situation where the timings are the same, it is possible to avoid signal mutations caused by changing the timings at the same time, which may affect the display effect.

[0153] In some embodiments, as shown in FIG. 2 or FIG. 3 , the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal have the same potential at valid levels and the same potential at invalid levels.

[0154] In some embodiments, FIG4 is a timing diagram of each clock signal line within a clock cycle according to Example 3 of the present disclosure. As shown in FIG4 , the timing of the first clock signal CK1 and the second clock signal CK2 are the same. The timing of the fourth clock signal CK4 and the third clock signal CK3 are the same.

[0155] It should be noted that timing in a circuit refers to the time sequence in which a signal switches between high and low potentials. Having the same timing means that the potential transitions of the compared signals coincide at the same time nodes, but it does not mean that the potentials of the two signals are the same at the same time nodes.

[0156] As shown in Figure 4, the third clock signal CK3 and the first clock signal CK1 have opposite timing. Opposite timing means that within the same clock cycle T, the potential transition times of the compared signals are inconsistent. Alternatively, it can be understood that the first clock signal CK1 and the third clock signal CK3 have the same waveform throughout the entire operating scan phase, but the active level transition time of the third clock signal CK3 is later than the active level transition time of the first clock signal CK1 by a preset duration t'.

[0157] Here, the first clock signal line CKL1 , the second clock signal line CKL2 , the third clock signal line CKL3 , and the fourth clock signal line CKL4 are all different.

[0158] In the shift register provided in this embodiment, different clock signal lines, namely, the first clock signal line CKL1 and the second clock signal line CKL2, are used for transmission of the first clock signal CK1 and the second clock signal CK2 with the same timing; and the third clock signal CK3 and the fourth clock signal CK4 with the same timing are used for transmission of the third clock signal CKL3 and the fourth clock signal line CKL4. In this way, the number of transistors connected to a single clock signal line can be reduced, thereby reducing the load on each clock signal line, shortening the signal output time, and improving the uniformity of the image quality of large-screen displays.

[0159] In some embodiments, as shown in FIG. 4 , the first clock signal CK1 and the second clock signal CK2 include first levels; the potential of the first level of the first clock signal CK1 is different from the potential of the first level of the second clock signal CK2 .

[0160] Exemplarily, the clock periods T of the first clock signal CK1 and the second clock signal CK2 are the same in length.

[0161] Exemplarily, the first level is a low level (i.e., a valid level) in a clock cycle T, and the potential of the low level of the first clock signal CK1 is different from the potential of the low level of the second clock signal CK2. For example, the potential of the low level of the first clock signal CK1 may be greater than the potential of the low level of the second clock signal CK2, or may be less than the potential of the low level of the second clock signal CK2.

[0162] Exemplarily, the absolute value of the amplitude of the first clock signal CK1 is greater than the absolute value of the amplitude of the second clock signal CK2.

[0163] 4 , the third clock signal CK3 and the fourth clock signal CK4 include a third level; the potential of the third level of the third clock signal CK3 is different from the potential of the third level of the fourth clock signal CK4.

[0164] Exemplarily, the clock periods T of the third clock signal CK3 and the fourth clock signal CK4 are the same in length.

[0165] Exemplarily, as shown in FIG4 , the clock cycles T of the first clock signal CK1 , the second clock signal CK2 , the third clock signal CK3 and the fourth clock signal CK4 are all the same in length.

[0166] Exemplarily, the third level is a low level (i.e., a valid level) in the clock cycle T, and the potential of the low level of the third clock signal CK3 is different from the potential of the low level of the fourth clock signal CK4. For example, the potential of the low level of the third clock signal CK3 may be greater than the potential of the low level of the fourth clock signal CK4, or may be less than the potential of the low level of the fourth clock signal CK4.

[0167] Exemplarily, the absolute value of the amplitude of the third clock signal CK3 is greater than the absolute value of the amplitude of the fourth clock signal CK4.

[0168] In some embodiments, as shown in FIG4 , the first level of the first clock signal CK1 is lower than the first level of the second clock signal CK2 , thereby preventing hysteresis problems in at least some transistors in the input sub-circuit 1 and affecting transistor characteristics.

[0169] 4 , the third level of the third clock signal CK3 is lower than the third level of the fourth clock signal CK4 , reducing the impact of threshold loss on at least some transistors in the first control sub-circuit 2 and the second control sub-circuit 3 .

[0170] In some embodiments, as shown in FIG. 4 , the first clock signal CK1 and the second clock signal CK2 further include a second level, which is different from the first level; and the potential of the second level of the first clock signal CK1 is different from the potential of the second level of the second clock signal CK2.

[0171] Exemplarily, the second level is a high level (i.e., an inactive level) in the clock cycle T, and the potential of the high level of the first clock signal CK1 is different from the potential of the high level of the second clock signal CK2. For example, the potential of the high level of the first clock signal CK1 may be greater than the potential of the high level of the second clock signal CK2, or may be less than the potential of the high level of the second clock signal CK2.

[0172] 4 , the third clock signal CK3 and the fourth clock signal CK4 further include a fourth level, which is different from the third level; the potential of the fourth level of the third clock signal CK3 is different from the potential of the fourth level of the fourth clock signal CK4.

[0173] Exemplarily, the fourth level is a high level (i.e., an inactive level) in the clock cycle T, and the potential of the high level of the third clock signal CK3 is different from the potential of the high level of the fourth clock signal CK4. For example, the potential of the high level of the third clock signal CK3 may be greater than the potential of the high level of the fourth clock signal CK4, or may be less than the potential of the high level of the fourth clock signal CK4.

[0174] In some embodiments, as shown in Figure 4, the potential of the second level of the first clock signal CK1 is greater than the potential of the second level of the second clock signal CK2; and / or, the potential of the fourth level of the third clock signal CK3 is greater than the potential of the fourth level of the fourth clock signal CK4, thereby reducing the impact of threshold loss of some transistors in the shift register.

[0175] In some embodiments, the first power signal line VGL1, the second power signal line VGL2, the third power signal line VGH1, and the fourth power signal line VGH2 are all different. The first power signal and the second power signal are both low-level signals, but the potential of the first power signal is different from the potential of the second power signal. The third power signal and the fourth power signal are both high-level signals, but the potential of the third power signal is different from the potential of the fourth power signal. The potential of the low-level signal is lower than the potential of the high-level signal.

[0176] Exemplarily, considering the influence of threshold loss of some transistors in the shift register, the potential of the first power signal is set to be smaller than the potential of the second power signal.

[0177] Exemplarily, the potential of the third power signal is lower than the potential of the fourth power signal, thereby improving the turn-off characteristics of at least some transistors in the output sub-circuit 4 .

[0178] In some embodiments, as shown in Figure 4, the potential of the first level of the first clock signal CK1 is equal to the potential of the first power signal transmitted by the first power signal line VGL1, and the potential of the second level of the first clock signal CK1 is equal to the potential of the fourth power signal transmitted by the fourth power signal line VGH2; the potential of the first level of the second clock signal CK2 is equal to the potential of the second power signal transmitted by the second power signal line VGL2, and the potential of the second level of the second clock signal CK2 is equal to the potential of the third power signal transmitted by the third power signal line VGH1; the potential of the third level of the third clock signal CK3 is equal to the potential of the first power signal transmitted by the first power signal line VGL1, and the potential of the fourth level of the third clock signal CK3 is equal to the potential of the fourth power signal transmitted by the fourth power signal line VGH2; the potential of the third level of the fourth clock signal CK4 is equal to the potential of the second power signal transmitted by the second power signal line VGL2, and the potential of the fourth level of the fourth clock signal CK4 is equal to the potential of the third power signal transmitted by the third power signal line VGH1.

[0179] In some embodiments, as shown in FIG4 , the first level pulse width of the first clock signal CK1 is smaller than the second level pulse width; and / or the third level pulse width of the third clock signal CK3 is smaller than the fourth level pulse width.

[0180] Exemplarily, the first level is a low level during a clock cycle T, and the second level is a high level during a clock cycle T. The pulse width of the low level of the first clock signal CK1 is shorter than the pulse width of the high level. The first clock signal CK1 and the second clock signal CK2 have the same clock cycle T. Therefore, the pulse width of the low level of the second clock signal CK2 is shorter than the pulse width of the high level.

[0181] Exemplarily, the third level is a low level during a clock cycle T, and the fourth level is a high level during a clock cycle T. The pulse width of the low level of the third clock signal CK3 is shorter than the pulse width of the high level. The third clock signal CK3 and the fourth clock signal CK4 have the same clock cycle T. Therefore, the pulse width of the low level of the fourth clock signal CK4 is shorter than the pulse width of the high level.

[0182] In this embodiment, after the pulse width is widened, the first node N1 (or the fifth node N5) can be quickly pulled down, thereby ensuring that the output signal is output quickly to ensure the display quality.

[0183] Figure 5a is a schematic diagram of the structure of another shift register provided in an embodiment of the present disclosure; Figure 5b is a schematic diagram of the structure of another shift register provided in an embodiment of the present disclosure. In some embodiments, as shown in Figure 5a, the shift register further includes an isolation subcircuit 5; the isolation subcircuit 5 is configured to isolate the first node N1 from the first control subcircuit 2 electrically connected to the first node N1; isolate the first node N1 from the output subcircuit 4 electrically connected to the first node N1; and isolate the second node N2 from the second control subcircuit 3 electrically connected to the second node N2.

[0184] As shown in FIG5 a , the first control subcircuit 2 is electrically connected to the fifth node N5 ; the output subcircuit 4 is electrically connected to the fifth node N5 ; and the second control subcircuit 3 is electrically connected to the fourth node N4 and the first node N1 .

[0185] As shown in FIG5 a , the isolation sub-circuit 5 electrically connects the first node N1, the second node N2, the fourth node N4, the fifth node N5, the first power signal line VGL1, and the second power signal line VGL2. The isolation sub-circuit 5 is configured to connect the first node N1 and the fifth node N5 in response to the second power signal; and to connect the second node N2 and the fourth node N4 in response to the first power signal.

[0186] Alternatively, as shown in FIG5 b , the isolation sub-circuit 5 electrically connects the first node N1, the second node N2, the fourth node N4, the fifth node N5, and the first power signal line VGL1. The isolation sub-circuit 5 is configured to connect the first node N1 and the fifth node N5, and connect the second node N2 and the fourth node N4, in response to the first power signal.

[0187] In this embodiment, an isolation sub-circuit 5 is added to improve the stability of the output signal.

[0188] The above-mentioned shift register can adopt a circuit structure of 12T3C (i.e., 12 transistors and 3 capacitors); or, the shift register can also adopt a circuit structure of 13T3C (i.e., 13 transistors and 3 capacitors); or, the shift register can also adopt a circuit structure of 16T3C (i.e., 16 transistors and 3 capacitors).

[0189] It should be noted that the transistors in the embodiments of the present disclosure may be thin film transistors or field effect transistors or other switching devices with the same characteristics. The thin film transistors may include oxide semiconductor thin film transistors, amorphous silicon thin film transistors or polycrystalline silicon thin film transistors, etc. The source and drain of the transistor may be symmetrical in structure, so the source and drain may be indistinguishable in physical structure. In the embodiments of the present disclosure, in order to distinguish the transistors, except for the gate as the control electrode, one of the electrodes is directly described as the first electrode and the other electrode is directly described as the second electrode, so the first electrode and the second electrode of all or part of the transistors in the embodiments of the present disclosure can be interchangeable as needed.

[0190] It should be noted that thin-film transistors can be either N-type or P-type. An N-type thin-film transistor refers to a thin-film transistor with N-type ion doping in its active layer, while a P-type thin-film transistor refers to a thin-film transistor with P-type ion doping in its active layer. The operating level signal for an N-type thin-film transistor is a high-level signal, while the operating level signal for a P-type thin-film transistor is a low-level signal.

[0191] For ease of understanding, the present disclosure is described in the following embodiments by taking a P-type thin film transistor as an example, but the present disclosure is not limited to a P-type thin film transistor.

[0192] It should be noted that, in the embodiment of the present disclosure, the circuit structure inside the shift register may be a structure with other numbers of transistors in addition to the 12T3C, 13T3C and 16T3C listed above, and the embodiment of the present disclosure is not limited to this.

[0193] The shift registers of the circuit structures of 12T3C, 13T3C and 16T3C are described in detail below using different embodiments.

[0194] In some embodiments, a 12T3C circuit structure is used as an example for description. The 12T3C circuit structure adopts the timing control of the clock signal line shown in Figure 2 or Figure 3. Figure 6 is a circuit diagram of a 12T3C circuit structure provided in an embodiment of the present disclosure. As shown in Figure 6, the input subcircuit 1 includes a first transistor T1, a second transistor T2, and a third transistor T3. The first control subcircuit 2 includes a fourth transistor T4, a fifth transistor T5, and a third capacitor C3. The second control subcircuit 3 includes a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, and a first capacitor C1. The output subcircuit 4 includes a ninth transistor T9, a tenth transistor T10, and a second capacitor C2. The isolation subcircuit 5 includes an eleventh transistor T11 and a twelfth transistor T12.

[0195] Continuing with FIG6 , for input sub-circuit 1 , a first electrode of first transistor T1 is electrically connected to the signal input terminal Input, a second electrode is electrically connected to the first node N1, and a control electrode is electrically connected to the first clock signal line CKL1. A first electrode of second transistor T2 is electrically connected to the second clock signal line CKL2, a second electrode is electrically connected to the second node N2, and a control electrode is electrically connected to the first node N1. A first electrode of third transistor T3 is electrically connected to the first power signal line VGL1, a second electrode is electrically connected to the second node N2, and a control electrode is electrically connected to the second clock signal line CKL2. Specifically, the first clock signal CK1 can control the on / off of the first transistor T1. When the first transistor T1 responds to the first clock signal CK1 and turns on, the input signal can be transmitted to the first node N1. The signal at the first node N1 can control the on / off of the second transistor T2. When the second transistor T2 responds to the signal at the first node N1 and turns on, the second clock signal CK2 can be transmitted to the second node N2. The second clock signal CK2 controls the on and off of the third transistor T3. When the third transistor T3 responds to the second clock signal CK2 and is turned on, the first power signal can be transmitted to the second node N2.

[0196] Optionally, for the input sub-circuit 1 , the first electrode of the second transistor T2 may be electrically connected to the first clock signal line CKL1 .

[0197] Continuing with FIG6 , in the first control sub-circuit 2 , a first electrode of the fourth transistor T4 is electrically connected to the third clock signal line CKL3, a second electrode is electrically connected to the second electrode of the fifth transistor T5, and a control electrode is electrically connected to the fifth node N5. A first electrode of the fifth transistor T5 is electrically connected to the third power signal line VGH1, a second electrode is electrically connected to the first plate of the third capacitor C3, and a control electrode is electrically connected to the second node N2. The second plate of the third capacitor C3 is electrically connected to the fifth node N5. Specifically, a signal at the fifth node N5 can control the on / off switching of the fourth transistor T4. When the fourth transistor T4 is turned on in response to the signal at the fifth node N5, the third clock signal CK3 can be transmitted to the sixth node N6. A signal at the second node N2 can control the on / off switching of the fifth transistor T5. When the fifth transistor T5 is turned on in response to the signal at the second node N2, the third power signal can be transmitted to the sixth node N6.

[0198] The second electrode of the fourth transistor T4 , the second electrode of the fifth transistor T5 , and the first plate of the third capacitor C3 are all electrically connected to the sixth node N6 .

[0199] Continuing with FIG6 , in the second control sub-circuit 3 , a first electrode of the sixth transistor T6 is electrically connected to the fourth clock signal line CKL4, a second electrode is electrically connected to the first electrode of the seventh transistor T7, and a control electrode is electrically connected to the fourth node N4 and the first plate of the first capacitor C1. A first electrode of the seventh transistor T7 is electrically connected to the second plate of the first capacitor C1, a second electrode is electrically connected to the third node N3, and a control electrode is electrically connected to the fourth clock signal line CKL4. A first electrode of the eighth transistor T8 is electrically connected to the fourth power supply signal line VGH2, a second electrode is electrically connected to the third node N3, and a control electrode is electrically connected to the first node N1. Specifically, a signal at the fourth node N4 can control the on / off switching of the sixth transistor T6. When the sixth transistor T6 responds to the signal at the fourth node N4 and turns on, the fourth clock signal CK4 can be transmitted to the seventh node N7. The fourth clock signal CK4 can control the on / off switching of the seventh transistor T7. When the seventh transistor T7 responds to the fourth clock signal CK4 and turns on, the signal at the seventh node N7 can be transmitted to the third node N3. The signal of the first node N1 may control the eighth transistor T8 to be turned on. When the eighth transistor T8 responds to the signal of the first node N1 and is turned on, the fourth power signal may be transmitted to the third node N3.

[0200] The second electrode of the sixth transistor T6 , the first electrode of the seventh transistor T7 , and the second plate of the first capacitor C1 are all electrically connected to the seventh node N7 .

[0201] Continuing with FIG6 , in the output sub-circuit 4 , a first electrode of the ninth transistor T9 is electrically connected to the third power signal line VGH1 and the first plate of the second capacitor C2, a second electrode is electrically connected to the signal output terminal OUT, and a control electrode is electrically connected to the third node N3. A first electrode of the tenth transistor T10 is electrically connected to the second power signal line VGL2, a second electrode is electrically connected to the signal output terminal OUT, and a control electrode is electrically connected to the fifth node N5. The second plate of the second capacitor C2 is electrically connected to the third node N3. Specifically, the signal at the third node N3 controls the on / off switching of the ninth transistor T9. When the ninth transistor T9 is turned on in response to the signal at the third node N3, the third power signal is transmitted to the signal output terminal OUT, thereby outputting the second output signal. A signal at the fifth node N5 controls the on / off switching of the tenth transistor T10. When the tenth transistor T10 is turned on in response to the signal at the fifth node N5, the second power signal is output to the signal output terminal OUT, thereby outputting the first output signal.

[0202] Exemplarily, the potential of the third power signal is lower than the potential of the fourth power signal, which can improve the turn-off characteristics of the ninth transistor T9. For example, the potential of the third power signal is 7.5V, and the potential of the fourth power signal is 8V.

[0203] For example, the potential of the first power signal is lower than that of the second power signal, which can reduce the threshold loss of the tenth transistor T10 and ensure output. For example, the potential of the first power signal is -8V, and the potential of the fourth power signal is -7.5V.

[0204] Continuing with FIG6 , for the isolation sub-circuit 5 , the first electrode of the eleventh transistor T11 is electrically connected to the second node N2, the second electrode is electrically connected to the fourth node N4, and the control electrode is electrically connected to the first power signal line VGL1. The first electrode of the twelfth transistor T12 is electrically connected to the first node N1, the second electrode is electrically connected to the fifth node N5, and the control electrode is electrically connected to the first power signal line VGL1 (or the second power signal line VGL2). Specifically, the first power signal controls the on / off of the eleventh transistor T11 and the twelfth transistor T12. When the eleventh transistor T11 responds to the first power signal and turns on, it can transmit the signal at the second node N2 to the fourth node N4. When the twelfth transistor T12 responds to the first power signal and turns on, it can transmit the signal at the first node N1 to the fifth node N5.

[0205] This embodiment uses four clock signal lines with different timings and four power signal lines with different potentials. This reduces the number of transistors connected to a single clock signal line and a single power signal line, thereby reducing the load on each clock signal line and each power signal line, shortening the signal output time and improving the uniformity of large-screen display quality. At the same time, the timing of each clock signal line is different, avoiding the impact of simultaneous timing changes on the display effect. Furthermore, using different power signal lines can avoid signal fluctuations caused by excessive load on a single power signal line, which is beneficial to improving the stability of signal output.

[0206] In some embodiments, another 12T3C circuit structure is used as an example for description. This 12T3C circuit structure adopts the timing control of the clock signal line shown in Figure 4. Figure 7 is a circuit diagram of another 12T3C circuit structure provided by an embodiment of the present disclosure. As shown in Figure 7, the input subcircuit 1 includes a first transistor T1, a second transistor T2, and a third transistor T3. The first control subcircuit 2 includes a fourth transistor T4, a fifth transistor T5, and a third capacitor C3. The second control subcircuit 3 includes a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, and a first capacitor C1. The output subcircuit 4 includes a ninth transistor T9, a tenth transistor T10, and a second capacitor C2. The isolation subcircuit 5 includes an eleventh transistor T11 and a twelfth transistor T12.

[0207] Continuing with the figure 7 , for the input sub-circuit 1, the first electrode of the first transistor T1 is electrically connected to the signal input terminal Input, the second electrode is electrically connected to the first node N1, and the control electrode is electrically connected to the first clock signal line CKL1; the first electrode of the second transistor T2 is electrically connected to the first clock signal line CKL1, the second electrode is electrically connected to the second node N2, and the control electrode is electrically connected to the first node N1; the first electrode of the third transistor T3 is electrically connected to the first power signal line VGL1, the second electrode is electrically connected to the second node N2, and the control electrode is electrically connected to the second clock signal line CKL2.

[0208] For input sub-circuit 1, specifically, the first clock signal CK1 can control the on / off switching of the first transistor T1. When the first transistor T1 is turned on in response to the first clock signal CK1, the input signal can be transmitted to the first node N1. The signal at the first node N1 can control the on / off switching of the second transistor T2. When the second transistor T2 is turned on in response to the signal at the first node N1, the first clock signal CK1 can be transmitted to the second node N2. The second clock signal CK2 controls the on / off switching of the third transistor T3. When the third transistor T3 is turned on in response to the second clock signal CK2, the first power supply signal can be transmitted to the second node N2.

[0209] 4 , the first level of the first clock signal CK1 is different from the first level of the second clock signal CK2 ; the second level of the first clock signal CK1 is different from the second level of the second clock signal CK2 .

[0210] Continuing with the figure 7 , for the first control sub-circuit 2, the first electrode of the fourth transistor T4 is electrically connected to the third clock signal line CKL3, the second electrode is electrically connected to the second electrode of the fifth transistor T5, and the control electrode is electrically connected to the fifth node N5; the first electrode of the fifth transistor T5 is electrically connected to the third power signal line VGH1, the second electrode is electrically connected to the first plate of the third capacitor C3, and the control electrode is electrically connected to the second node N2; the second plate of the third capacitor C3 is electrically connected to the fifth node N5.

[0211] For the first control subcircuit 2, specifically, the signal at the fifth node N5 can control the on / off switching of the fourth transistor T4. When the fourth transistor T4 responds to the signal at the fifth node N5 and turns on, the third clock signal CK3 can be transmitted to the sixth node N6. The signal at the second node N2 can control the on / off switching of the fifth transistor T5. When the fifth transistor T5 responds to the signal at the second node N2 and turns on, the third power supply signal can be transmitted to the sixth node N6.

[0212] The second electrode of the fourth transistor T4 , the second electrode of the fifth transistor T5 , and the first plate of the third capacitor C3 are all electrically connected to the sixth node N6 .

[0213] Continuing with the figure 7 , for the second control sub-circuit 3, the first electrode of the sixth transistor T6 is electrically connected to the fourth clock signal line CKL4, the second electrode is electrically connected to the first electrode of the seventh transistor T7, and the control electrode is electrically connected to the fourth node N4 and the first plate of the first capacitor C1; the first electrode of the seventh transistor T7 is electrically connected to the second plate of the first capacitor C1, the second electrode is electrically connected to the third node N3, and the control electrode is electrically connected to the fourth clock signal line CKL4; the first electrode of the eighth transistor T8 is electrically connected to the fourth power supply signal line VGH2, the second electrode is electrically connected to the third node N3, and the control electrode is electrically connected to the first node N1.

[0214] For the second control sub-circuit 3, specifically, the signal at the fourth node N4 can control the on / off switching of the sixth transistor T6. When the sixth transistor T6 responds to the signal at the fourth node N4 and turns on, the fourth clock signal CK4 can be transmitted to the seventh node N7. The fourth clock signal CK4 can control the on / off switching of the seventh transistor T7. When the seventh transistor T7 responds to the fourth clock signal CK4 and turns on, the signal at the seventh node N7 can be transmitted to the third node N3. The signal at the first node N1 can control the on / off switching of the eighth transistor T8. When the eighth transistor T8 responds to the signal at the first node N1 and turns on, the fourth power supply signal can be transmitted to the third node N3.

[0215] The second electrode of the sixth transistor T6 , the first electrode of the seventh transistor T7 , and the second plate of the first capacitor C1 are all electrically connected to the seventh node N7 .

[0216] Continuing with FIG7 , for the output sub-circuit 4, a first electrode of the ninth transistor T9 is electrically connected to the third power signal line VGH1 and the first plate of the second capacitor C2, a second electrode is electrically connected to the signal output terminal OUT, and a control electrode is electrically connected to the third node N3; a first electrode of the tenth transistor T10 is electrically connected to the second power signal line VGL2, a second electrode is electrically connected to the signal output terminal OUT, and a control electrode is electrically connected to the fifth node N5; and a second plate of the second capacitor C2 is electrically connected to the third node N3.

[0217] In the output sub-circuit 4, the signal at the third node N3 controls the on / off switching of the ninth transistor T9. When the ninth transistor T9 is turned on in response to the signal at the third node N3, the third power supply signal is transmitted to the signal output terminal OUT, thereby outputting the second output signal. The signal at the fifth node N5 controls the on / off switching of the tenth transistor T10. When the tenth transistor T10 is turned on in response to the signal at the fifth node N5, the second power supply signal is output to the signal output terminal OUT, thereby outputting the first output signal.

[0218] Exemplarily, the potential of the third power signal is lower than the potential of the fourth power signal, which can improve the turn-off characteristic of the ninth transistor T9.

[0219] Exemplarily, the potential of the first power signal is lower than the potential of the second power signal, which can reduce the threshold loss of the tenth transistor T10 and ensure output.

[0220] Continuing with the figure 7 , for the isolation sub-circuit 5, the first electrode of the eleventh transistor T11 is electrically connected to the second node N2, the second electrode is electrically connected to the fourth node N4, and the control electrode is electrically connected to the first power signal line VGL1; the first electrode of the twelfth transistor T12 is electrically connected to the first node N1, the second electrode is electrically connected to the fifth node N5, and the control electrode is electrically connected to the second power signal line VGL2.

[0221] For example, in the isolation sub-circuit 5, the first power signal controls the on / off switching of the eleventh transistor T11. When the eleventh transistor T11 responds to the first power signal and turns on, the signal at the second node N2 can be transmitted to the fourth node N4. The second power signal controls the on / off switching of the twelfth transistor T12. When the twelfth transistor T12 responds to the second power signal and turns on, the signal at the first node N1 can be transmitted to the fifth node N5.

[0222] This embodiment uses four clock signal lines and four power signal lines with different potentials, reducing the number of transistors connected to a single clock signal line and a single power signal line. This reduces the load on each clock signal line and each power signal line, shortening signal output time and improving the uniformity of large-screen display quality. Furthermore, the first power signal line VGL1, the second power signal line VGL2, the third power signal line VGH1, and the fourth power signal line VGH2 are all different, which can avoid signal fluctuations caused by excessive load on a single power signal line, thereby improving signal output stability.

[0223] In some embodiments, a 13T3C circuit structure is used as an example for description. This 13T3C circuit structure uses the timing control of the clock signal line shown in Figure 2 or Figure 3. Figure 8 is a circuit diagram of a 13T3C circuit structure provided by an embodiment of the present disclosure. As shown in Figure 8, compared with the 12T3C circuit shown in Figure 6, this embodiment adds a thirteenth transistor T13 to the second control subcircuit 3 to improve the stability of the output signal and prevent flickering of the display effect.

[0224] As shown in Figure 8, the input subcircuit 1 includes a first transistor T1, a second transistor T2, and a third transistor T3. The first control subcircuit 2 includes a fourth transistor T4, a fifth transistor T5, and a third capacitor C3. The second control subcircuit 3 includes a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a thirteenth transistor T13, and a first capacitor C1. The output subcircuit 4 includes a ninth transistor T9, a tenth transistor T10, and a second capacitor C2. The isolation subcircuit 5 includes an eleventh transistor T11 and a twelfth transistor T12.

[0225] Among them, the circuit structure, connection relationship and operating principle of the input sub-circuit 1, the first control sub-circuit 2, the output sub-circuit 4 and the isolation sub-circuit 5 are the same as the circuit structure, connection relationship and operating principle of the input sub-circuit 1, the first control sub-circuit 2, the output sub-circuit 4 and the isolation sub-circuit 5 in the 12T3C circuit shown in Figure 6 above. For details, please refer to the above description and will not be repeated here.

[0226] Continuing with FIG8 , in the second control sub-circuit 3 , a first electrode of the sixth transistor T6 is electrically connected to the fourth clock signal line CKL4, a second electrode is electrically connected to the first electrode of the seventh transistor T7, and a control electrode is electrically connected to the fourth node N4 and the first plate of the first capacitor C1. A first electrode of the seventh transistor T7 is electrically connected to the second plate of the first capacitor C1, a second electrode is electrically connected to the third node N3, and a control electrode is electrically connected to the fourth clock signal line CKL4. A first electrode of the eighth transistor T8 is electrically connected to the fourth power signal line VGH2, a second electrode is electrically connected to the third node N3, and a control electrode is electrically connected to the first node N1. A first electrode of the thirteenth transistor T13 is electrically connected to the fourth power signal line VGH2, a second electrode is electrically connected to the first node N1, and a control electrode is electrically connected to the preset control terminal VEL. Specifically, the signal at the fourth node N4 can control the on / off of the sixth transistor T6. When the sixth transistor T6 is turned on in response to the signal at the fourth node N4, the fourth clock signal CK4 can be transmitted to the seventh node N7. The fourth clock signal CK4 can control the on / off switching of the seventh transistor T7. When the seventh transistor T7 is turned on in response to the fourth clock signal CK4, the signal at the seventh node N7 can be transmitted to the third node N3. The signal at the first node N1 can control the on / off switching of the eighth transistor T8. When the eighth transistor T8 is turned on in response to the signal at the first node N1, the fourth power signal can be transmitted to the third node N3. The preset control terminal VEL is connected to a preset control signal, which controls the on / off switching of the thirteenth transistor T13. When the thirteenth transistor T13 is turned on in response to the preset control signal, the fourth power signal can be transmitted to the first node N1.

[0227] It should be noted that, in the initialization phase before the shift register working phase, the preset control signal is a low level signal, and the thirteenth transistor T13 is turned on; in the formal working phase, the preset control signal is always a high level signal, and the thirteenth transistor T13 is turned off.

[0228] In some embodiments, another 13T3C circuit structure is used as an example for description. This 13T3C circuit structure adopts the timing control of the clock signal line shown in Figure 4. Figure 9 is a circuit diagram of another 13T3C circuit structure provided by an embodiment of the present disclosure. As shown in Figure 9, compared with the 12T3C circuit shown in Figure 7, this embodiment adds a thirteenth transistor T13 in the second control subcircuit 3 to improve the stability of the output signal and prevent flickering of the display effect.

[0229] As shown in Figure 9, the input subcircuit 1 includes a first transistor T1, a second transistor T2, and a third transistor T3. The first control subcircuit 2 includes a fourth transistor T4, a fifth transistor T5, and a third capacitor C3. The second control subcircuit 3 includes a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a thirteenth transistor T13, and a first capacitor C1. The output subcircuit 4 includes a ninth transistor T9, a tenth transistor T10, and a second capacitor C2. The isolation subcircuit 5 includes an eleventh transistor T11 and a twelfth transistor T12.

[0230] Continuing with the figure 9 , for the input sub-circuit 1, the first electrode of the first transistor T1 is electrically connected to the signal input terminal Input, the second electrode is electrically connected to the first node N1, and the control electrode is electrically connected to the first clock signal line CKL1; the first electrode of the second transistor T2 is electrically connected to the first clock signal line CKL1, the second electrode is electrically connected to the second node N2, and the control electrode is electrically connected to the first node N1; the first electrode of the third transistor T3 is electrically connected to the first power signal line VGL1, the second electrode is electrically connected to the second node N2, and the control electrode is electrically connected to the second clock signal line CKL2.

[0231] For input sub-circuit 1, specifically, the first clock signal CK1 can control the on / off switching of the first transistor T1. When the first transistor T1 is turned on in response to the first clock signal CK1, the input signal can be transmitted to the first node N1. The signal at the first node N1 can control the on / off switching of the second transistor T2. When the second transistor T2 is turned on in response to the signal at the first node N1, the first clock signal CK1 can be transmitted to the second node N2. The second clock signal CK2 controls the on / off switching of the third transistor T3. When the third transistor T3 is turned on in response to the second clock signal CK2, the first power supply signal can be transmitted to the second node N2.

[0232] Exemplarily, the potential of the first level of the first clock signal CK1 is different from the potential of the first level of the second clock signal CK2 ; the potential of the second level of the first clock signal CK1 is different from the potential of the second level of the second clock signal CK2 .

[0233] Continuing with the figure 9 , for the first control sub-circuit 2, the first electrode of the fourth transistor T4 is electrically connected to the third clock signal line CKL3, the second electrode is electrically connected to the second electrode of the fifth transistor T5, and the control electrode is electrically connected to the fifth node N5; the first electrode of the fifth transistor T5 is electrically connected to the third power signal line VGH1, the second electrode is electrically connected to the first plate of the third capacitor C3, and the control electrode is electrically connected to the second node N2; the second plate of the third capacitor C3 is electrically connected to the fifth node N5.

[0234] For the first control subcircuit 2, specifically, the signal at the fifth node N5 can control the on / off switching of the fourth transistor T4. When the fourth transistor T4 responds to the signal at the fifth node N5 and turns on, the third clock signal CK3 can be transmitted to the sixth node N6. The signal at the second node N2 can control the on / off switching of the fifth transistor T5. When the fifth transistor T5 responds to the signal at the second node N2 and turns on, the third power supply signal can be transmitted to the sixth node N6.

[0235] The second electrode of the fourth transistor T4 , the second electrode of the fifth transistor T5 , and the first plate of the third capacitor C3 are all electrically connected to the sixth node N6 .

[0236] Continuing with the figure, for the second control sub-circuit 3, the first electrode of the sixth transistor T6 is electrically connected to the fourth clock signal line CKL4, the second electrode is electrically connected to the first electrode of the seventh transistor T7, and the control electrode is electrically connected to the fourth node N4 and the first plate of the first capacitor C1; the first electrode of the seventh transistor T7 is electrically connected to the second plate of the first capacitor C1, the second electrode is electrically connected to the third node N3, and the control electrode is electrically connected to the fourth clock signal line CKL4; the first electrode of the eighth transistor T8 is electrically connected to the fourth power signal line VGH2, the second electrode is electrically connected to the third node N3, and the control electrode is electrically connected to the first node N1; the first electrode of the thirteenth transistor T13 is electrically connected to the fourth power signal line VGH2, the second electrode is electrically connected to the first node N1, and the control electrode is electrically connected to the preset control terminal VEL.

[0237] For the second control sub-circuit 3, specifically, the signal at the fourth node N4 can control the on / off switching of the sixth transistor T6. When the sixth transistor T6 responds to the signal at the fourth node N4 and turns on, the fourth clock signal CK4 can be transmitted to the seventh node N7. The fourth clock signal CK4 can control the on / off switching of the seventh transistor T7. When the seventh transistor T7 responds to the fourth clock signal CK4 and turns on, the signal at the seventh node N7 can be transmitted to the third node N3. The signal at the first node N1 can control the on / off switching of the eighth transistor T8. When the eighth transistor T8 responds to the signal at the first node N1 and turns on, the fourth power supply signal can be transmitted to the third node N3.

[0238] The preset control signal is connected to control the on / off of the thirteenth transistor T13 . When the thirteenth transistor T13 responds to the preset control signal and is turned on, the fourth power signal can be transmitted to the first node N1 .

[0239] It should be noted that, in the initialization phase before the shift register working phase, the preset control signal is a low level signal, and the thirteenth transistor T13 is turned on; in the formal working phase, the preset control signal is always a high level signal, and the thirteenth transistor T13 is turned off.

[0240] Continuing with FIG9 , for the output sub-circuit 4, a first electrode of the ninth transistor T9 is electrically connected to the third power signal line VGH1 and the first plate of the second capacitor C2, a second electrode is electrically connected to the signal output terminal OUT, and a control electrode is electrically connected to the third node N3; a first electrode of the tenth transistor T10 is electrically connected to the second power signal line VGL2, a second electrode is electrically connected to the signal output terminal OUT, and a control electrode is electrically connected to the fifth node N5; and a second plate of the second capacitor C2 is electrically connected to the third node N3.

[0241] In the output sub-circuit 4, the signal at the third node N3 controls the on / off switching of the ninth transistor T9. When the ninth transistor T9 is turned on in response to the signal at the third node N3, the third power supply signal is transmitted to the signal output terminal OUT, thereby outputting the second output signal. The signal at the fifth node N5 controls the on / off switching of the tenth transistor T10. When the tenth transistor T10 is turned on in response to the signal at the fifth node N5, the second power supply signal is output to the signal output terminal OUT, thereby outputting the first output signal.

[0242] Exemplarily, the potential of the third power signal is lower than the potential of the fourth power signal, which can improve the turn-off characteristic of the ninth transistor T9.

[0243] Exemplarily, the potential of the first power signal is lower than the potential of the second power signal, which can reduce the threshold loss of the tenth transistor T10 and ensure output.

[0244] Continuing with the figure 9 , for the isolation sub-circuit 5, the first electrode of the eleventh transistor T11 is electrically connected to the second node N2, the second electrode is electrically connected to the fourth node N4, and the control electrode is electrically connected to the first power signal line VGL1; the first electrode of the twelfth transistor T12 is electrically connected to the first node N1, the second electrode is electrically connected to the fifth node N5, and the control electrode is electrically connected to the second power signal line VGL2.

[0245] For example, in the isolation sub-circuit 5, the first power signal controls the on / off switching of the eleventh transistor T11. When the eleventh transistor T11 responds to the first power signal and turns on, the signal at the second node N2 can be transmitted to the fourth node N4. The second power signal controls the on / off switching of the twelfth transistor T12. When the twelfth transistor T12 responds to the second power signal and turns on, the signal at the first node N1 can be transmitted to the fifth node N5.

[0246] This embodiment uses four clock signal lines with different potentials and four power signal lines with different potentials to reduce the number of transistors connected to a single clock signal line and a single power signal line, thereby reducing the load on each clock signal line and each power signal line, thereby shortening the signal output time and improving the uniformity of the image quality of large-screen displays. At the same time, the first power signal line VGL1, the second power signal line VGL2, the third power signal line VGH1, and the fourth power signal line VGH2 are all different, which can avoid signal fluctuations caused by excessive load on a single power signal line, which is conducive to improving the stability of signal output. In addition, the load on each power signal line is balanced. For example, the first power signal line VGL1 is connected to the third transistor T3 and the eleventh transistor T11, the second power signal line VGL2 is connected to the tenth transistor T10 and the twelfth transistor T12; the third power signal line VGH1 is connected to the ninth transistor T9 and the fifth transistor T5, and the fourth power signal line VGH2 is connected to the eighth transistor T8 and the thirteenth transistor T13, which can further improve the display effect.

[0247] In some embodiments, Figure 10 is a structural schematic diagram of another shift register provided by an embodiment of the present disclosure. As shown in Figure 10, the shift register also includes an isolation sub-circuit 5; the isolation sub-circuit 5 is configured to isolate the first node N1 and the first control sub-circuit 2 electrically connected to the first node N1; isolate the first node N1 and the output sub-circuit 4 electrically connected to the first node N1; isolate the first node N1 and the second control sub-circuit 3 electrically connected to the first node N1; and isolate the second node N2 and the second control sub-circuit 3 electrically connected to the second node N2.

[0248] As shown in FIG10 , the first control subcircuit 2 is electrically connected to the fifth node N5 ; the output subcircuit 4 is electrically connected to the fifth node N5 ; and the second control subcircuit 3 is electrically connected to the fourth node N4 and the fifth node N5 .

[0249] As shown in FIG10 , the isolation sub-circuit 5 electrically connects the first node N1, the second node N2, the fourth node N4, the fifth node N5, the first power signal line VGL1, and the second power signal line VGL2. The isolation sub-circuit 5 is configured to connect the first node N1 and the fifth node N5 in response to the second power signal, and to connect the second node N2 and the fourth node N4 in response to the first power signal.

[0250] Alternatively, the isolation sub-circuit 5 electrically connects the first node N1, the second node N2, the fourth node N4, the fifth node N5, and the first power signal line VGL1. The isolation sub-circuit 5 is configured to connect the first node N1 and the fifth node N5, and connect the second node N2 and the fourth node N4, in response to the first power signal.

[0251] In this embodiment, an isolation sub-circuit 5 is added to improve the stability of the output signal.

[0252] A 16T3C circuit structure is used as an example for description. This 16T3C circuit structure uses the timing control of the clock signal line shown in Figure 2 or Figure 3. Figure 11 is a circuit diagram of a 16T3C circuit structure provided by an embodiment of the present disclosure. As shown in Figure 11, compared with the 13T3C circuit shown in Figure 8, this embodiment adds a fourteenth transistor T14 to the input subcircuit 1, and adds a fifteenth transistor T15 and a sixteenth transistor T16 to the first control subcircuit 2.

[0253] As shown in Figure 11, the input sub-circuit 1 includes a first transistor T1, a second transistor T2, a third transistor T3 and a fourteenth transistor T14; the first control sub-circuit 2 includes a fourth transistor T4, a fifth transistor T5, a fifteenth transistor T15, a sixteenth transistor T16 and a third capacitor C3; the second control sub-circuit 3 includes a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a thirteenth transistor T13 and a first capacitor C1; the output sub-circuit 4 includes a ninth transistor T9, a tenth transistor T10 and a second capacitor C2; and the isolation sub-circuit 5 includes an eleventh transistor T11 and a twelfth transistor T12.

[0254] Among them, the circuit structure, connection relationship and working principle of the second control sub-circuit 3, the output sub-circuit 4 and the isolation sub-circuit 5 are the same as the circuit structure, connection relationship and working principle of the second control sub-circuit 3, the output sub-circuit 4 and the isolation sub-circuit 5 in the 13T3C circuit shown in Figure 8 above. For details, please refer to the above description and will not be repeated here.

[0255] Continuing with FIG11 , for input sub-circuit 1 , a first electrode of first transistor T1 is electrically connected to signal input terminal Input, a second electrode is electrically connected to first node N1, and a control electrode is electrically connected to first clock signal line CKL1. A first electrode of second transistor T2 is electrically connected to second clock signal line CKL2, a second electrode is electrically connected to second node N2, and a control electrode is electrically connected to first node N1. A first electrode of third transistor T3 is electrically connected to first power signal line VGL1, a second electrode is electrically connected to second node N2, and a control electrode is electrically connected to second clock signal line CKL2. A first electrode of fourteenth transistor T14 is electrically connected to signal input terminal Input, a second electrode is electrically connected to eighth node N8, and a control electrode is electrically connected to first clock signal line CKL1. Specifically, a first clock signal CK1 can control the on / off switching of first transistor T1. When first transistor T1 is turned on in response to the first clock signal CK1, the input signal can be transmitted to first node N1. A signal at first node N1 can control the on / off switching of second transistor T2. When second transistor T2 is turned on in response to the signal at first node N1, the second clock signal CK2 can be transmitted to second node N2. The second clock signal CK2 controls the on / off of the third transistor T3. When the third transistor T3 responds to the second clock signal CK2 and turns on, the first power signal can be transmitted to the second node N2. The first clock signal CK1 can also control the on / off of the fourteenth transistor T14. When the fourteenth transistor T14 responds to the first clock signal CK1 and turns on, the input signal can be transmitted to the eighth node N8.

[0256] Continuing with FIG11 , in the first control sub-circuit 2 , a first electrode of the fourth transistor T4 is electrically connected to the third clock signal line CKL3, a second electrode is electrically connected to the second electrode of the fifth transistor T5, and a control electrode is electrically connected to the second plate of the third capacitor C3. A first electrode of the fifth transistor T5 is electrically connected to the third power supply signal line VGH1, a second electrode is electrically connected to the first plate of the third capacitor C3, and a control electrode is electrically connected to the second node N2. A first electrode of the fifteenth transistor T15 is electrically connected to the eighth node N8, a second electrode is electrically connected to the first electrode of the sixteenth transistor T16 and the control electrode of the sixteenth transistor T16, and the control electrode is electrically connected to the first power supply signal line VGL1. A second electrode of the sixteenth transistor T16 is electrically connected to the fifth node N5, and a control electrode is electrically connected to the control electrode of the fourth transistor T4. Specifically, a signal at the fifth node N5 can control the on / off switching of the fourth transistor T4. When the fourth transistor T4 is turned on in response to the signal at the fifth node N5, the third clock signal CK3 can be transmitted to the sixth node N6. The signal at the second node N2 can control the on / off of the fifth transistor T5. When the fifth transistor T5 responds to the signal at the second node N2 and turns on, the third power supply signal can be transmitted to the sixth node N6. The first power supply signal can control the on / off of the fifteenth transistor T15. When the fifteenth transistor T15 responds to the first power supply signal and turns on, the signal at the eighth node N8 can be transmitted to the ninth node N9. The signal at the ninth node N9 can control the on / off of the sixteenth transistor T16. When the sixteenth transistor T16 responds to the signal at the ninth node N9 and turns on, the signal at the ninth node N9 can be transmitted to the fifth node N5.

[0257] In this embodiment, four clock signal lines with different timings and four power signal lines with different potentials are used to reduce the number of transistors connected to a single clock signal line and a single power signal line, thereby reducing the load on each clock signal line and each power signal line, thereby shortening the signal output time and improving the uniformity of the image quality of the large-screen display. At the same time, the timing of each clock signal line is different, avoiding the impact of changing the timing at the same time on the display effect. In addition, the use of different power signal lines can avoid the signal fluctuation caused by excessive load on a single power signal line, which is conducive to improving the stability of the signal output. In addition, the load on each power signal line is balanced. For example, the third power signal line VGH1 is connected to the ninth transistor T9 and the fifth transistor T5, and the fourth power signal line VGH2 is connected to the eighth transistor T8 and the thirteenth transistor T13, which can further improve the display effect.

[0258] Optionally, for the first control sub-circuit 2 , the first electrode of the fifth transistor T5 may be electrically connected to the fourth power signal line VGH2 .

[0259] In some embodiments, another 16T3C circuit structure is used as an example for description. This 16T3C circuit structure adopts the timing control of the clock signal line shown in Figure 4. Figure 12 is a circuit diagram of another 16T3C circuit structure provided by an embodiment of the present disclosure. As shown in Figure 12, compared with the 13T3C circuit shown in Figure 9, this embodiment adds a fourteenth transistor T14 to the input sub-circuit 1, and adds a fifteenth transistor T15 and a sixteenth transistor T16 to the first control sub-circuit 2.

[0260] As shown in Figure 12, the input sub-circuit 1 includes a first transistor T1, a second transistor T2, a third transistor T3 and a fourteenth transistor T14; the first control sub-circuit 2 includes a fourth transistor T4, a fifth transistor T5, a fifteenth transistor T15, a sixteenth transistor T16 and a third capacitor C3; the second control sub-circuit 3 includes a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a thirteenth transistor T13 and a first capacitor C1; the output sub-circuit 4 includes a ninth transistor T9, a tenth transistor T10 and a second capacitor C2; and the isolation sub-circuit 5 includes an eleventh transistor T11 and a twelfth transistor T12.

[0261] Continuing with the figure 12 , for the input sub-circuit 1, the first electrode of the first transistor T1 is electrically connected to the signal input terminal Input, the second electrode is electrically connected to the first node N1, and the control electrode is electrically connected to the first clock signal line CKL1; the first electrode of the second transistor T2 is electrically connected to the first clock signal line CKL1, the second electrode is electrically connected to the second node N2, and the control electrode is electrically connected to the first node N1; the first electrode of the third transistor T3 is electrically connected to the first power signal line VGL1, the second electrode is electrically connected to the second node N2, and the control electrode is electrically connected to the second clock signal line CKL2; the first electrode of the fourteenth transistor T14 is electrically connected to the signal input terminal Input, the second electrode is electrically connected to the eighth node N8, and the control electrode is electrically connected to the second clock signal line CKL2.

[0262] For input sub-circuit 1, specifically, the first clock signal CK1 can control the on / off switching of the first transistor T1. When the first transistor T1 is turned on in response to the first clock signal CK1, the input signal can be transmitted to the first node N1. The signal at the first node N1 can control the on / off switching of the second transistor T2. When the second transistor T2 is turned on in response to the signal at the first node N1, the first clock signal CK1 can be transmitted to the second node N2. The second clock signal CK2 controls the on / off switching of the third transistor T3. When the third transistor T3 is turned on in response to the second clock signal CK2, the first power supply signal can be transmitted to the second node N2. The second clock signal CK2 can also control the on / off switching of the fourteenth transistor T14. When the fourteenth transistor T14 is turned on in response to the second clock signal CK2, the input signal can be transmitted to the eighth node N8.

[0263] For example, as shown in FIG4 , the potential of the first level of the first clock signal CK1 is different from the potential of the first level of the second clock signal CK2; the potential of the second level of the first clock signal CK1 is different from the potential of the second level of the second clock signal CK2. This can avoid problems such as transistor hysteresis caused by the gate-source electrodes of the third transistor T3 and the first transistor T1 being at the same voltage difference for a long time, and the gate-source electrodes of the fourteenth transistor T14 and the first transistor T1 being at the same voltage difference for a long time, thereby affecting the transistor characteristics.

[0264] Continuing with the figure 12 , for the first control sub-circuit 2, the first electrode of the fourth transistor T4 is electrically connected to the third clock signal line CKL3, the second electrode is electrically connected to the second electrode of the fifth transistor T5, and the control electrode is electrically connected to the second plate of the third capacitor C3; the first electrode of the fifth transistor T5 is electrically connected to the third power signal line VGH1, the second electrode is electrically connected to the first plate of the third capacitor C3, and the control electrode is electrically connected to the second node N2; the first electrode of the fifteenth transistor T15 is electrically connected to the eighth node N8, the second electrode is electrically connected to the first electrode of the sixteenth transistor T16 and the control electrode of the sixteenth transistor T16, and the control electrode is electrically connected to the first power signal line VGL1; the second electrode of the sixteenth transistor T16 is electrically connected to the fifth node N5, and the control electrode is electrically connected to the control electrode of the fourth transistor T4.

[0265] For the first control sub-circuit 2, specifically, the signal at the fifth node N5 can control the on / off of the fourth transistor T4. When the fourth transistor T4 responds to the signal at the fifth node N5 and turns on, the third clock signal CK3 can be transmitted to the sixth node N6. The signal at the second node N2 can control the on / off of the fifth transistor T5. When the fifth transistor T5 responds to the signal at the second node N2 and turns on, the third power signal can be transmitted to the sixth node N6. The first power signal can control the on / off of the fifteenth transistor T15. When the fifteenth transistor T15 responds to the first power signal and turns on, the signal at the eighth node N8 can be transmitted to the ninth node N9. The signal at the ninth node N9 can control the on / off of the sixteenth transistor T16. When the sixteenth transistor T16 responds to the signal at the ninth node N9 and turns on, the signal at the ninth node N9 can be transmitted to the fifth node N5.

[0266] The control electrode of the fourth transistor T4, the second plate of the third capacitor C3, the second electrode of the fifteenth transistor T15, the second electrode of the sixteenth transistor T16, and the control electrode of the sixteenth transistor T16 are all electrically connected to the ninth node N9.

[0267] Continuing with the figure 12 , for the second control sub-circuit 3, the first electrode of the sixth transistor T6 is electrically connected to the fourth clock signal line CKL4, the second electrode is electrically connected to the first electrode of the seventh transistor T7, and the control electrode is electrically connected to the fourth node N4 and the first plate of the first capacitor C1; the first electrode of the seventh transistor T7 is electrically connected to the second plate of the first capacitor C1, the second electrode is electrically connected to the third node N3, and the control electrode is electrically connected to the fourth clock signal line CKL4; the first electrode of the eighth transistor T8 is electrically connected to the fourth power signal line VGH2, the second electrode is electrically connected to the third node N3, and the control electrode is electrically connected to the fifth node N5; the first electrode of the thirteenth transistor T13 is electrically connected to the fourth power signal line VGH2, the second electrode is electrically connected to the fifth node N5, and the control electrode is electrically connected to the preset control terminal VEL.

[0268] For the second control sub-circuit 3, specifically, the signal at the fourth node N4 can control the on / off switching of the sixth transistor T6. When the sixth transistor T6 responds to the signal at the fourth node N4 and turns on, the fourth clock signal CK4 can be transmitted to the seventh node N7. The fourth clock signal CK4 can control the on / off switching of the seventh transistor T7. When the seventh transistor T7 responds to the fourth clock signal CK4 and turns on, the signal at the seventh node N7 can be transmitted to the third node N3. The signal at the fifth node N5 can control the on / off switching of the eighth transistor T8. When the eighth transistor T8 responds to the signal at the fifth node N5 and turns on, the fourth power supply signal can be transmitted to the third node N3.

[0269] The preset control signal is connected to control the on / off of the thirteenth transistor T13 . When the thirteenth transistor T13 responds to the preset control signal and is turned on, the fourth power signal can be transmitted to the fifth node N5 .

[0270] Continuing with FIG12 , for the output sub-circuit 4, a first electrode of the ninth transistor T9 is electrically connected to the third power signal line VGH1 and the first plate of the second capacitor C2, a second electrode is electrically connected to the signal output terminal OUT, and a control electrode is electrically connected to the third node N3; a first electrode of the tenth transistor T10 is electrically connected to the second power signal line VGL2, a second electrode is electrically connected to the signal output terminal OUT, and a control electrode is electrically connected to the fifth node N5; and a second plate of the second capacitor C2 is electrically connected to the third node N3.

[0271] In the output sub-circuit 4, the signal at the third node N3 controls the on / off switching of the ninth transistor T9. When the ninth transistor T9 is turned on in response to the signal at the third node N3, the third power supply signal is transmitted to the signal output terminal OUT, thereby outputting the second output signal. The signal at the fifth node N5 controls the on / off switching of the tenth transistor T10. When the tenth transistor T10 is turned on in response to the signal at the fifth node N5, the second power supply signal is output to the signal output terminal OUT, thereby outputting the first output signal.

[0272] Exemplarily, the potential of the third power signal is lower than the potential of the fourth power signal, which can improve the turn-off characteristic of the ninth transistor T9.

[0273] Exemplarily, the potential of the first power signal is lower than the potential of the second power signal, which can reduce the threshold loss of the tenth transistor T10 and ensure output.

[0274] Continuing with the figure 12 , for the isolation sub-circuit 5, the first electrode of the eleventh transistor T11 is electrically connected to the second node N2, the second electrode is electrically connected to the fourth node N4, and the control electrode is electrically connected to the first power signal line VGL1; the first electrode of the twelfth transistor T12 is electrically connected to the first node N1, the second electrode is electrically connected to the fifth node N5, and the control electrode is electrically connected to the second power signal line VGL2.

[0275] For example, in the isolation sub-circuit 5, the first power signal controls the on / off switching of the eleventh transistor T11. When the eleventh transistor T11 responds to the first power signal and turns on, the signal at the second node N2 can be transmitted to the fourth node N4. The second power signal controls the on / off switching of the twelfth transistor T12. When the twelfth transistor T12 responds to the second power signal and turns on, the signal at the first node N1 can be transmitted to the fifth node N5.

[0276] This embodiment uses four clock signal lines with different potentials and four power signal lines with different potentials, reducing the number of transistors connected to a single clock signal line and a single power signal line, thereby reducing the load on each clock signal line and each power signal line, shortening the signal output time and improving the uniformity of large-screen display quality. At the same time, the first power signal line VGL1, the second power signal line VGL2, the third power signal line VGH1, and the fourth power signal line VGH2 are all different, which can avoid signal fluctuations caused by excessive load on a single power signal line, which is conducive to improving the stability of signal output. In addition, the load on each power signal line is balanced. For example, the third power signal line VGH1 is connected to the ninth transistor T9 and the fifth transistor T5, and the fourth power signal line VGH2 is connected to the eighth transistor T8 and the thirteenth transistor T13, which can further improve the display effect.

[0277] In some embodiments, the first transistor T1 and the third transistor T3 in the input sub-circuit 1 in the circuit structures of 12T3C as shown in FIG. 7 , 13T3C as shown in FIG. 9 , and 16T3C as shown in FIG. 12 can be connected to the same first clock signal line CKL1 , and the second transistor T2 can be connected to the second clock signal line CKL2 .

[0278] Exemplarily, the input sub-circuit 1 includes a first transistor T1, a second transistor T2 and a third transistor T3; the first electrode of the first transistor T1 is electrically connected to the signal input terminal Input, the second electrode is electrically connected to the first node N1, and the control electrode is electrically connected to the first clock signal line CKL1; the first electrode of the second transistor T2 is electrically connected to the second clock signal line CKL2, the second electrode is electrically connected to the second node N2, and the control electrode is electrically connected to the first node N1; the first electrode of the third transistor T3 is electrically connected to the first power signal line VGL1, the second electrode is electrically connected to the second node N2, and the control electrode is electrically connected to the first clock signal line CKL1.

[0279] In some embodiments, the eleventh transistor T11 and the twelfth transistor T12 in the isolation sub-circuit 5 in the circuit structures of 12T3C as shown in FIG7 , 13T3C as shown in FIG9 , and 16T3C as shown in FIG12 may also be connected to the same first power signal line VGL1 to ensure the stability of the output signal during the isolation process.

[0280] The working principle of the shift register provided by the embodiment of the present disclosure is described in further detail below.

[0281] In some embodiments, FIG13 is a timing diagram of an exemplary shift register provided in an embodiment of the present disclosure. As shown in FIG13 , a 12T3C circuit structure using the timing control of the clock signal line shown in FIG2 (that is, the 12T3C circuit structure shown in FIG6 ) is used as an example for description. Its working stages specifically include a first stage t1, a second stage t2, a third stage t3, a fourth stage t4, a fifth stage t5, a sixth stage t6, a seventh stage t7, an eighth stage t8, a ninth stage t9, a tenth stage t10, an eleventh stage t11, and a twelfth stage t12, wherein:

[0282] In the first phase t1, the input signal transmitted by the signal input terminal Input is a high-level signal, the first clock signal CK1 is at an active level, which can be understood as a low level, and the second clock signal CK2, the third clock signal CK3, and the fourth clock signal CK4 are at an inactive level, which can be understood as a high level. The eleventh transistor T11 and the twelfth transistor T12 are normally on. At this time, the first transistor T1 is turned on, the first node N1 and the fifth node N5 are written with a high-level signal, the second transistor T2, the fourth transistor T4, the eighth transistor T8, and the tenth transistor T10 are all turned off, the third node N3 maintains the high potential of the previous phase, and the ninth transistor T9 is turned off. At this time, the output signal remains the same as the previous phase, and the signal output terminal OUT outputs the first output signal at a low potential.

[0283] In the second phase t2, the input signal transmitted by the signal input terminal Input is a high-level signal, the second clock signal CK2 is at an active level, which can be understood as a low level, and the first clock signal CK1, the third clock signal CK3, and the fourth clock signal CK4 are at an inactive level, which can be understood as a high level. The eleventh transistor T11 and the twelfth transistor T12 are normally on. At this time, the third transistor T3 is turned on, a low-level signal is written to the second node N2, the fifth transistor T5 is turned on, a high-level signal is written to the sixth node N6, the sixth transistor T6 is turned on, and a high-level signal is written to the seventh node N7. The first node N1 and the fifth node N5 maintain the high potential of the previous phase. The second transistor T2, the fourth transistor T4, the eighth transistor T8, and the tenth transistor T10 are all turned off, and the seventh transistor T7 is also in the off state. The third node N3 maintains the high potential of the previous phase, and the ninth transistor T9 is turned off. The output signal at this time remains the same as the previous phase, and the signal output terminal OUT outputs the first output signal at a low potential.

[0284] In the third phase t3, the input signal transmitted by the signal input terminal Input is a high-level signal, the third clock signal CK3 is at an active level, which can be understood as a low level, and the first clock signal CK1, the second clock signal CK2, and the fourth clock signal CK4 are at an inactive level, which can be understood as a high level. The eleventh transistor T11 and the twelfth transistor T12 are normally on. At this time, the first node N1 and the fifth node N5 maintain the high potential of the previous phase, and the second transistor T2, the fourth transistor T4, the eighth transistor T8, and the tenth transistor T10 are all turned off. The second node N2 and the fourth node N4 maintain the low potential of the previous phase, the sixth transistor T6 is turned on, and a high-level signal is written to the seventh node N7. However, the seventh transistor T7 remains off, so the third node N3 maintains the high potential of the previous phase, and the ninth transistor T9 is turned off. The output signal at this time remains the same as the previous phase, and the signal output terminal OUT outputs the first output signal at a low potential.

[0285] In the fourth stage t4, the input signal transmitted by the signal input terminal Input is a high-level signal, the fourth clock signal CK4 is at an active level, which can be understood as a low level, and the first clock signal CK1, the second clock signal CK2, and the third clock signal CK3 are at an inactive level, which can be understood as a high level. The eleventh transistor T11 and the twelfth transistor T12 are normally on. At this time, the first node N1 and the fifth node N5 both maintain the high potential of the previous stage, and the second transistor T2, the eighth transistor T8, and the tenth transistor T10 are all turned off. The second node N2 maintains the low potential of the previous stage, the fifth transistor T5 is turned on, and a high-level signal is written to the sixth node N6. The fourth node N4 maintains the low potential of the previous stage, the sixth transistor T6 is turned on, a low-level signal is written to the seventh node N7, and at the same time, the seventh transistor T7 is turned on, a low-level signal is written to the third node N3, and the ninth transistor T9 is turned on. At this time, the signal output terminal OUT outputs the second output signal with a high potential.

[0286] In the fifth stage t5, the input signal transmitted by the signal input terminal Input is a high-level signal, the first clock signal CK1 is at an active level, which can be understood as a low level, and the second clock signal CK2, the third clock signal CK3, and the fourth clock signal CK4 are at an inactive level, which can be understood as a high level. The eleventh transistor T11 and the twelfth transistor T12 are normally on. At this time, the first transistor T1 is turned on, the first node N1 and the fifth node N5 are written with a high-level signal, the second transistor T2, the fourth transistor T4, the eighth transistor T8, and the tenth transistor T10 are all turned off, the third node N3 maintains the low potential of the previous stage, and the ninth transistor T9 is turned on. At this time, the signal output terminal OUT outputs the second output signal with a high potential.

[0287] In the sixth stage t6, the input signal transmitted by the signal input terminal Input is a high-level signal, the second clock signal CK2 is at an active level, which can be understood as a low level, and the first clock signal CK1, the third clock signal CK3, and the fourth clock signal CK4 are at an inactive level, which can be understood as a high level. The eleventh transistor T11 and the twelfth transistor T12 are normally on. At this time, the third transistor T3 is turned on, a low-level signal is written to the second node N2, the fifth transistor T5 is turned on, a high-level signal is written to the sixth node N6, the sixth transistor T6 is turned on, and a high-level signal is written to the seventh node N7. The first node N1 and the fifth node N5 maintain the high potential of the previous stage, the second transistor T2, the fourth transistor T4, the eighth transistor T8, and the tenth transistor T10 are all turned off, and the seventh transistor T7 is also in the off state. The third node N3 maintains the low potential of the previous stage, and the ninth transistor T9 is turned on. At this time, the signal output terminal OUT outputs the second output signal at a high potential.

[0288] In the seventh stage t7, the input signal transmitted by the signal input terminal Input is a high-level signal, the third clock signal CK3 is at an active level, which can be understood as a low level, and the first clock signal CK1, the second clock signal CK2, and the fourth clock signal CK4 are at an inactive level, which can be understood as a high level. The eleventh transistor T11 and the twelfth transistor T12 are normally on. At this time, the first node N1 and the fifth node N5 both maintain the high potential of the previous stage, and the second transistor T2, the fourth transistor T4, the eighth transistor T8, and the tenth transistor T10 are all turned off. The second node N2 and the fourth node N4 maintain the low potential of the previous stage, the sixth transistor T6 is turned on, and a high-level signal is written to the seventh node N7. However, the seventh transistor T7 remains off, so the third node N3 maintains the high potential of the previous stage, the third node N3 maintains the low potential of the previous stage, and the ninth transistor T9 is turned on. At this time, the signal output terminal OUT outputs the second output signal with a high potential.

[0289] The operating state of the eighth stage t8 is the same as that of the fourth stage t4. Specifically, in the eighth stage t8, the input signal transmitted by the signal input terminal Input is a high-level signal, the fourth clock signal CK4 is at an active level, which can be understood as a low level, and the first clock signal CK1, the second clock signal CK2, and the third clock signal CK3 are at an inactive level, which can be understood as a high level. The eleventh transistor T11 and the twelfth transistor T12 are normally on. At this time, the first node N1 and the fifth node N5 both maintain the high potential of the previous stage, and the second transistor T2, the fourth transistor T4, the eighth transistor T8, and the tenth transistor T10 are all off. The second node N2 maintains the low potential of the previous stage, the fifth transistor T5 is turned on, and a high-level signal is written to the sixth node N6. The fourth node N4 maintains the low potential of the previous stage, the sixth transistor T6 is turned on, a low-level signal is written to the seventh node N7, and the seventh transistor T7 is turned on. A low-level signal is written to the third node N3, and the ninth transistor T9 is turned on. At this time, the signal output terminal OUT outputs the second output signal at a high potential.

[0290] In the ninth stage t9, the input signal transmitted by the signal input terminal Input is a low-level signal, the first clock signal CK1 is at an active level, which can be understood as a low level, and the second clock signal CK2, the third clock signal CK3, and the fourth clock signal CK4 are at an inactive level, which can be understood as a high level. The eleventh transistor T11 and the twelfth transistor T12 are normally on. At this time, the first transistor T1 is turned on, a low-level signal is written to the first node N1, the second transistor T2 is turned on, a high-level signal is written to the second node N2, and the fifth transistor T5 and the sixth transistor T6 are turned off. Simultaneously, the fourth transistor T4 is turned on, and a high-level signal is written to the sixth node N6. Simultaneously, the eighth transistor T8 is turned on, a high-level signal is written to the third node N3, and the ninth transistor T9 is turned off. The fifth node N5 is connected to the first node N1 and is now at a low potential V1. The tenth transistor T10 is turned on, and the signal output terminal OUT outputs the low-level first output signal.

[0291] In the tenth stage t10, the input signal transmitted by the signal input terminal Input is a low-level signal, the second clock signal CK2 is at an active level, which can be understood as a low level, and the first clock signal CK1, the third clock signal CK3, and the fourth clock signal CK4 are at an inactive level, which can be understood as a high level. The eleventh transistor T11 and the twelfth transistor T12 are normally on. At this time, the first node N1 and the fifth node N5 maintain the low potential V1 of the previous stage, the eighth transistor T8 remains on, the third node N3 continues to be written with a high-level signal, the ninth transistor T9 remains off, the tenth transistor T10 remains on, and the signal output terminal OUT continues to output the low-level first output signal.

[0292] In the eleventh stage t11, the input signal transmitted by the signal input terminal Input is a low-level signal, the third clock signal CK3 is at an active level, which can be understood as a low level, and the first clock signal CK1, the second clock signal CK2, and the fourth clock signal CK4 are at an inactive level, which can be understood as a high level. The eleventh transistor T11 and the twelfth transistor T12 are normally on. At this time, the first node N1 maintains the low potential V1 of the previous stage, the second transistor T2 is turned on, a high-level signal is written to the second node N2, and the fifth transistor T5 and the sixth transistor T6 are turned off. Simultaneously, the eighth transistor T8 is turned on, a high-level signal is written to the third node N3, and the ninth transistor T9 is turned off. Simultaneously, the fourth transistor T4 is turned on, a low-level signal is written to the sixth node N6, and the third capacitor C3 is used to further pull the low potential V1 of the fifth node N5 down to the low potential V2. The tenth transistor T10 remains on, and the signal output terminal OUT outputs the low-level first output signal.

[0293] In the twelfth stage t12, the input signal transmitted by the signal input terminal Input is a high-level signal, the fourth clock signal CK4 is at an active level, which can be understood as a low level, and the first clock signal CK1, the second clock signal CK2, and the third clock signal CK3 are at an inactive level, which can be understood as a high level. The eleventh transistor T11 and the twelfth transistor T12 are normally on. At this time, the first node N1 maintains the low potential V1 of the previous stage, the second transistor T2 is turned on, a high-level signal is written to the second node N2, and the fifth transistor T5 and the sixth transistor T6 are turned off. Simultaneously, the fourth transistor T4 is turned on, and a high-level signal is written to the sixth node N6. Simultaneously, the eighth transistor T8 is turned on, a high-level signal is written to the third node N3, and the ninth transistor T9 is turned off. The fifth node N5 is connected to the first node N1 and is now at a low potential V1. The tenth transistor T10 is turned on, and the signal output terminal OUT outputs a low-level first output signal (i.e., OUT1 in FIG13 ). OUT2 in FIG13 represents the signal output by the signal output terminal OUT of the next cascaded shift register.

[0294] In some embodiments, Figure 14 is a timing diagram of another exemplary shift register provided in an embodiment of the present disclosure. As shown in Figure 14, the 12T3C circuit structure using the timing control of the clock signal line shown in Figure 3 (that is, the 12T3C circuit structure shown in Figure 6) is used as an example for illustration, and its working stages specifically include the first stage t_1, the second stage t_2, the third stage t_3, the fourth stage t_4, the fifth stage t_5, the sixth stage t_6, the seventh stage t_7, the eighth stage t_8, the ninth stage t_9, the tenth stage t_10, the eleventh stage t_11, and the twelfth stage t_12.

[0295] The difference here from the timing shown in FIG13 is that: in the third stage t_3, the seventh stage t_7, and the eleventh stage t_11, the fourth clock signal CK4 is at a valid level, and the first clock signal CK1, the second clock signal CK2, and the third clock signal CK3 are at an invalid level; in the fourth stage t_4, the eighth stage t_8, and the twelfth stage t_12, the third clock signal CK3 is at a valid level, and the first clock signal CK1, the second clock signal CK2, and the fourth clock signal CK4 are at an invalid level.

[0296] The working principles of the first stage t_1 are the same as the first stage t1, the second stage t_2 is the second stage t2, the fifth stage t_5 is the fifth stage t5, the sixth stage t_6 is the sixth stage t6, the ninth stage t_9 is the ninth stage t9, and the tenth stage t_10 is the tenth stage t10, and the repeated parts are not repeated here.

[0297] As shown in Figure 14, in the eleventh stage t11, the input signal transmitted by the signal input terminal Input is a high-level signal, the fourth clock signal CK4 is at an active level, which can be understood as a low level, and the first clock signal CK1, the second clock signal CK2, and the third clock signal CK3 are at an inactive level, which can be understood as a high level. The eleventh transistor T11 and the twelfth transistor T12 are normally on. At this time, the first node N1 maintains the low potential V1 of the previous stage, the second transistor T2 is turned on, a high-level signal is written to the second node N2, and the fifth transistor T5 and the sixth transistor T6 are turned off. Simultaneously, the fourth transistor T4 is turned on, and a high-level signal is written to the sixth node N6. Simultaneously, the eighth transistor T8 is turned on, a high-level signal is written to the third node N3, and the ninth transistor T9 is turned off. The fifth node N5 is connected to the first node N1 and is now at a low potential V1. The tenth transistor T10 is turned on, and the signal output terminal OUT outputs the low-level first output signal.

[0298] As shown in Figure 14, in the twelfth stage t_12, the input signal transmitted by the signal input terminal Input is a low-level signal, the third clock signal CK3 is at an active level, which can be understood as a low level, and the first clock signal CK1, the second clock signal CK2, and the fourth clock signal CK4 are at an inactive level, which can be understood as a high level. The eleventh transistor T11 and the twelfth transistor T12 are normally on. At this time, the first node N1 maintains the low potential V1 of the previous stage, the second transistor T2 is turned on, a high-level signal is written to the second node N2, and the fifth transistor T5 and the sixth transistor T6 are turned off. Simultaneously, the eighth transistor T8 is turned on, a high-level signal is written to the third node N3, and the ninth transistor T9 is turned off. Simultaneously, the fourth transistor T4 is turned on, a low-level signal is written to the sixth node N6, and the third capacitor C3 is used to further pull the low potential V1 of the fifth node N5 down to the low potential V2. The tenth transistor T10 is continuously turned on, and the signal output terminal OUT outputs the low-level first output signal.

[0299] In some embodiments, FIG15 is a timing diagram of another exemplary shift register provided in an embodiment of the present disclosure. As shown in FIG15 , a 12T3C circuit structure using the timing control of the clock signal line shown in FIG4 (that is, the 12T3C circuit structure shown in FIG7 ) is used as an example for description. Its working stages specifically include a first stage t_21, a second stage t_22, a third stage t_23, a fourth stage t_24, a fifth stage t_25, and a sixth stage t_26, wherein:

[0300] In the first phase t_21, the input signal transmitted by the signal input terminal Input is a high-level signal, the first clock signal CK1 is at the first level, and the second clock signal CK2 is at the first level, which can be understood as a low level; the third clock signal CK3 is at the fourth level, and the fourth clock signal CK4 is at the fourth level, which can be understood as a high level. At this time, the seventh transistor T7 is turned off, and the first transistor T1 and the third transistor T3 are turned on, so that the input signal is transmitted to the fifth node N5 through the first transistor T1 and the normally-on twelfth transistor T12, thereby controlling the potentials of the first node N1 and the fifth node N5 to be high. At the same time, the first power supply signal is a low-level signal, and the first power supply signal is transmitted to the fourth node N4 through the third transistor T3 and the normally-on eleventh transistor T11, thereby controlling the potentials of the second node N2 and the fourth node N4 to be low. Accordingly, the second transistor T2, the fourth transistor T4, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, and the tenth transistor T10 are all turned off. At this time, the output signal remains at the previous phase, as shown in Figure 8, maintaining the low potential output of the previous phase.

[0301] In the second phase t_22, the first clock signal CK1 is at the second level, the second clock signal CK2 is at the second level, which can be understood as a high level; the third clock signal CK3 is at the third level, and the fourth clock signal CK4 is at the third level, which can be understood as a low level. At this time, the first transistor T1 and the third transistor T3 are turned off, the seventh transistor T7 is turned on, the first node N1 and the fifth node N5 maintain the high potential of the previous phase, and the second node N2 and the fourth node N4 maintain the low potential of the previous phase. Accordingly, the second transistor T2, the fourth transistor T4, the eighth transistor T8, and the tenth transistor T10 are all turned off, the fifth transistor T5 and the sixth transistor T6 are turned on, and the fourth clock signal CK4 is transmitted to the third node N3 through the turned-on sixth transistor T6 and the turned-on seventh transistor T7. The potential of the third node N3 is now low, and the ninth transistor T9 is turned on, thereby outputting the second output signal, that is, the high potential third power supply signal.

[0302] In the third phase t_23, the input signal is a high-level signal. The first clock signal CK1 is at the first level, and the second clock signal CK2 is at the first level, which can be understood as a low level. The third clock signal CK3 is at the fourth level, and the fourth clock signal CK4 is at the fourth level, which can be understood as a high level. At this time, the seventh transistor T7 is turned off, and the potential of the third node N3 remains stably at the low potential of the previous phase. At this time, the ninth transistor T9 can remain on, thereby outputting the second output signal, that is, the high-potential third power supply signal.

[0303] In the fourth stage t_24, the input signal is a low-level signal, the first clock signal CK1 is at the second level, and the second clock signal CK2 is at the second level, which can be understood as a high level; the third clock signal CK3 is at the third level, and the fourth clock signal CK4 is at the third level, which can be understood as a low level. At this time, the first transistor T1 and the third transistor T3 are turned off, the seventh transistor T7 is turned on, and under the storage effect of the second capacitor C2, the first node N1 and the fifth node N5 maintain the high potential of the previous stage, and the second node N2 and the fourth node N4 maintain the low potential of the previous stage. Correspondingly, the second transistor T2, the fourth transistor T4, the eighth transistor T8, and the tenth transistor T10 are all turned off, the fifth transistor T5 and the sixth transistor T6 are turned on, and the fourth clock signal CK4 is transmitted to the third node N3 through the turned-on sixth transistor T6 and the turned-on seventh transistor T7. The potential of the third node N3 is now low, and the ninth transistor T9 is turned on, thereby outputting the second output signal, that is, the high-potential third power supply signal.

[0304] In the fifth phase t_25, the input signal is a low-level signal, the first clock signal CK1 is at the first level, and the second clock signal CK2 is at the first level, which can be understood as a low level; the third clock signal CK3 is at the fourth level, and the fourth clock signal CK4 is at the fourth level, which can be understood as a high level. At this time, the seventh transistor T7 is turned off, and the first transistor T1 and the second transistor T2 are turned on, so that the input signal is transmitted to the fifth node N5 through the first transistor T1 and the normally-on twelfth transistor T12, thereby controlling the potentials of the first node N1 and the fifth node N5 to a low level. At the same time, the first power supply signal is a low-level signal, and the first power supply signal is transmitted to the fourth node N4 through the third transistor T3 and the normally-on eleventh transistor T11, thereby controlling the potentials of the second node N2 and the fourth node N4 to a low level. Accordingly, the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the eighth transistor T8, and the tenth transistor T10 are turned on. Since the eighth transistor T8 is turned on, the third node N3 is at a high level, and therefore the ninth transistor T9 is turned off. At the same time, affected by threshold loss, the potential of the fifth node N5 is slightly higher than the potential of the second power signal. At this time, the tenth transistor T10 is not fully turned on, so the potential of the first output signal will be slightly higher than the potential of the second power signal.

[0305] In the sixth stage t_26, the input signal is a low-level signal, the first clock signal CK1 is at the second level, and the second clock signal CK2 is at the second level, which can be understood as a high level; the third clock signal CK3 is at the third level, and the fourth clock signal CK4 is at the third level, which can be understood as a low level. At this time, the first transistor T1 and the third transistor T3 are turned off, the seventh transistor T7 is turned on, and under the storage effect of the second capacitor C2, the first node N1 and the fifth node N5 maintain the low potential of the previous stage, and the second node N2 and the fourth node N4 maintain the low potential of the previous stage. Correspondingly, the eighth transistor T8 and the tenth transistor T10 are turned on, and the fourth power supply signal is transmitted to the third node N3 through the turned-on eighth transistor T8, raising the potential of the third node N3 to a high potential. At this time, the ninth transistor T9 is turned off. At the same time, the potential of the fifth node N5 can be reduced to a potential lower than the second power supply signal through coupling with the second capacitor C2. At this time, the tenth transistor T10 is fully turned on, and the potential of the signal output terminal OUT is reduced to the potential of the second power supply signal, that is, the first output signal.

[0306] The above is a complete introduction to the shift register provided by the embodiments of the present disclosure.

[0307] In addition, an embodiment of the present disclosure also provides a gate drive circuit, comprising N cascaded shift registers; in addition to the first-stage shift register, the signal input terminal Input of the i+1-stage shift register is electrically connected to the signal output terminal OUT of the i-stage shift register; N is a positive integer greater than 1, and i is a positive integer less than or equal to N.

[0308] In some embodiments, Figure 16 is a schematic diagram of a gate drive circuit provided in an embodiment of the present disclosure. As shown in Figure 16, the first clock signal line CKL1 in the i-th stage shift register is multiplexed as the fourth clock signal line CKL4 in the i+1-th stage shift register, the second clock signal line CKL2 in the i-th stage shift register is multiplexed as the first clock signal line CKL1 in the i+1-th stage shift register, the third clock signal line CKL3 in the i-th stage shift register is multiplexed as the second clock signal line CKL2 in the i+1-th stage shift register, and the fourth clock signal line CKL4 in the i-th stage shift register is multiplexed as the third clock signal line CKL3 in the i+1-th stage shift register.

[0309] The gate driving circuit shown in FIG16 is suitable for the driving timing shown in FIG2 or FIG3.

[0310] In some embodiments, Figure 17 is a schematic diagram of another gate drive circuit provided in an embodiment of the present disclosure. As shown in Figure 17, the first clock signal line CKL1 in the i-th stage shift register is multiplexed as the third clock signal line CKL3 in the i+1-th stage shift register, the second clock signal line CKL2 in the i-th stage shift register is multiplexed as the fourth clock signal line CKL4 in the i+1-th stage shift register, the third clock signal line CKL3 in the i-th stage shift register is multiplexed as the first clock signal line CKL1 in the i+1-th stage shift register, and the fourth clock signal line CKL4 in the i-th stage shift register is multiplexed as the second clock signal line CKL2 in the i+1-th stage shift register.

[0311] The gate driving circuit shown in FIG17 is suitable for the driving timing shown in FIG4 .

[0312] Figure 18 is a circuit diagram of the shift register cascade of the 12T3C circuit structure shown in Figure 6 provided by an embodiment of the present disclosure, Figure 19 is a circuit diagram of the shift register cascade of the 13T3C circuit structure shown in Figure 8 provided by an embodiment of the present disclosure, and Figure 20 is a circuit diagram of the shift register cascade of the 16T3C circuit structure shown in Figure 11 provided by an embodiment of the present disclosure.

[0313] In some embodiments, as shown in FIG18 or FIG19 , for the i-th stage shift register, the control electrode of the first transistor T1 is electrically connected to the first clock signal line CKL1; the first electrode of the second transistor T2 is electrically connected to the second clock signal line CKL2; the control electrode of the third transistor T3 is electrically connected to the second clock signal line CKL2; the first electrode of the fourth transistor T4 is electrically connected to the third clock signal line CKL3; the first electrode of the sixth transistor T6 is electrically connected to the fourth clock signal line CKL4; and the control electrode of the seventh transistor T7 is electrically connected to the fourth clock signal line CKL4. For the (i+1)-th stage shift register cascaded with the i-th stage shift register, the control electrode of the first transistor T1 is electrically connected to the fourth clock signal line CKL4; the first electrode of the second transistor T2 is electrically connected to the first clock signal line CKL1; the control electrode of the third transistor T3 is electrically connected to the first clock signal line CKL1; the first electrode of the fourth transistor T4 is electrically connected to the second clock signal line CKL2; the first electrode of the sixth transistor T6 is electrically connected to the third clock signal line CKL3; and the control electrode of the seventh transistor T7 is electrically connected to the third clock signal line CKL3.

[0314] The timing sequence of the output signal terminal OUT of the i-th stage shift register is as shown in FIG13 OUT signal, and the timing sequence of the output signal terminal OUT2 of the i+1-th stage shift register is as shown in FIG13 OUT2 signal. Alternatively, the timing sequence of the output signal terminal OUT of the i-th stage shift register is as shown in FIG14 OUT signal, and the timing sequence of the output signal terminal OUT2 of the i+1-th stage shift register is as shown in FIG14 OUT2 signal.

[0315] In some embodiments, as shown in Figure 20, for the i-th stage shift register, the control electrode of the first transistor T1 is electrically connected to the first clock signal line CKL1; the first electrode of the second transistor T2 is electrically connected to the second clock signal line CKL2; the control electrode of the third transistor T3 is electrically connected to the second clock signal line CKL2; the control electrode of the fourteenth transistor T14 is electrically connected to the first clock signal line CKL1; the first electrode of the fourth transistor T4 is electrically connected to the third clock signal line CKL3; the first electrode of the sixth transistor T6 is electrically connected to the fourth clock signal line CKL4; and the control electrode of the seventh transistor T7 is electrically connected to the fourth clock signal line CKL4. For the i+1th stage shift register cascaded with the i-th stage shift register, the control electrode of the first transistor T1 is electrically connected to the fourth clock signal line CKL4; the first electrode of the second transistor T2 is electrically connected to the first clock signal line CKL1; the control electrode of the third transistor T3 is electrically connected to the first clock signal line CKL1; the control electrode of the fourteenth transistor T14 is electrically connected to the fourth clock signal line CKL4; the first electrode of the fourth transistor T4 is electrically connected to the second clock signal line CKL2; the first electrode of the sixth transistor T6 is electrically connected to the third clock signal line CKL3; and the control electrode of the seventh transistor T7 is electrically connected to the third clock signal line CKL3.

[0316] Figure 21 is a circuit diagram of the shift register cascade of the 12T3C circuit structure shown in Figure 7 provided by an embodiment of the present disclosure, Figure 22 is a circuit diagram of the shift register cascade of the 13T3C circuit structure shown in Figure 9 provided by an embodiment of the present disclosure, and Figure 23 is a circuit diagram of the shift register cascade of the 16T3C circuit structure shown in Figure 12 provided by an embodiment of the present disclosure.

[0317] In some embodiments, as shown in FIG21 or FIG22 , for the i-th stage shift register, the control electrode of the first transistor T1 is electrically connected to the first clock signal line CKL1; the first electrode of the second transistor T2 is electrically connected to the first clock signal line CKL1; the control electrode of the third transistor T3 is electrically connected to the second clock signal line CKL2; the first electrode of the fourth transistor T4 is electrically connected to the third clock signal line CKL3; the first electrode of the sixth transistor T6 is electrically connected to the fourth clock signal line CKL4; and the control electrode of the seventh transistor T7 is electrically connected to the fourth clock signal line CKL4. For the (i+1)-th stage shift register cascaded with the i-th stage shift register, the control electrode of the first transistor T1 is electrically connected to the third clock signal line CKL3; the first electrode of the second transistor T2 is electrically connected to the third clock signal line CKL3; the control electrode of the third transistor T3 is electrically connected to the fourth clock signal line CKL4; the first electrode of the fourth transistor T4 is electrically connected to the first clock signal line CKL1; the first electrode of the sixth transistor T6 is electrically connected to the second clock signal line CKL2; and the control electrode of the seventh transistor T7 is electrically connected to the second clock signal line CKL2.

[0318] In some embodiments, as shown in Figure 23, for the i-th stage shift register, the control electrode of the first transistor T1 is electrically connected to the first clock signal line CKL1; the first electrode of the second transistor T2 is electrically connected to the first clock signal line CKL1; the control electrode of the third transistor T3 is electrically connected to the second clock signal line CKL2; the control electrode of the fourteenth transistor T14 is electrically connected to the second clock signal line CKL2; the first electrode of the fourth transistor T4 is electrically connected to the third clock signal line CKL3; the first electrode of the sixth transistor T6 is electrically connected to the fourth clock signal line CKL4; and the control electrode of the seventh transistor T7 is electrically connected to the fourth clock signal line CKL4. For the i+1th stage shift register cascaded with the i-th stage shift register, the control electrode of the first transistor T1 is electrically connected to the third clock signal line CKL3; the first electrode of the second transistor T2 is electrically connected to the third clock signal line CKL3; the control electrode of the third transistor T3 is electrically connected to the fourth clock signal line CKL4; the control electrode of the fourteenth transistor T14 is electrically connected to the fourth clock signal line CKL4; the first electrode of the fourth transistor T4 is electrically connected to the first clock signal line CKL1; the first electrode of the sixth transistor T6 is electrically connected to the second clock signal line CKL2; and the control electrode of the seventh transistor T7 is electrically connected to the second clock signal line CKL2.

[0319] Since the i-th stage shift register and the i+1-th stage shift register cascaded with each other in the gate drive circuit are respectively electrically connected to a set of clock signals with different timings, that is, the first clock signal CK1 and the second clock signal CK2, which are different from the timings of the third clock signal CK3 and the fourth clock signal CK4, the timings of the two are not affected.

[0320] In addition, an embodiment of the present disclosure further provides a display device, which includes a pixel driving circuit and a gate driving circuit as described above, wherein the gate driving circuit is electrically connected to the pixel driving circuit to provide a gate control signal to the pixel driving circuit.

[0321] For example, the display device can be any product with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, or an in-vehicle device. Other essential components of the display device are well understood by those skilled in the art and are not described here in detail, nor should they be construed as limiting the present disclosure.

[0322] It is understood that the above embodiments are merely exemplary embodiments for illustrating the principles of the present disclosure, and the present disclosure is not limited thereto. Those skilled in the art may make various modifications and improvements without departing from the spirit and substance of the present disclosure, and such modifications and improvements are also considered to be within the scope of protection of the present disclosure.

Claims

1. A shift register, characterized in that: comprising a first clock signal line, a second clock signal line, a third clock signal line, a fourth clock signal line, an input subcircuit, a first control subcircuit, a second control subcircuit and an output subcircuit; The input subcircuit is configured to control the potentials of the first node and the second node in response to a first clock signal provided by the first clock signal line and a second clock signal provided by the second clock signal line; The first control subcircuit is configured to control the potential of the first node in response to the signal of the second node and the third clock signal provided by the third clock signal line; The second control subcircuit is configured to control the potential of the third node in response to the signal of the first node, the signal of the second node and the fourth clock signal provided by the fourth clock signal line; The output sub-circuit is configured to output a first output signal in response to a signal at the first node, or to output a second output signal in response to a signal at the third node.

2. The shift register according to claim 1, characterized in that: In one clock cycle, a pulse of the first clock signal precedes a pulse of the second clock signal, a pulse of the second clock signal precedes a pulse of the third clock signal, and a pulse of the third clock signal precedes a pulse of the fourth clock signal.

3. The shift register according to claim 1, wherein: In one clock cycle, a pulse of the first clock signal precedes a pulse of the second clock signal, a pulse of the second clock signal precedes a pulse of the fourth clock signal, and a pulse of the fourth clock signal precedes a pulse of the third clock signal.

4. The shift register according to claim 1, wherein: The first clock signal and the second clock signal have the same timing; the third clock signal and the first clock signal have opposite timing; the fourth clock signal and the third clock signal have the same timing.

5. The shift register according to claim 4, characterized in that: The first clock signal and the second clock signal include a first level; a potential of the first level of the first clock signal is different from a potential of the first level of the second clock signal; and / or, The third clock signal and the fourth clock signal include a third level; a potential of the third level of the third clock signal is different from a potential of the third level of the fourth clock signal.

6. The shift register according to claim 5, characterized in that: The potential of the first level of the first clock signal is lower than the potential of the first level of the second clock signal; and / or, The potential of the third level of the third clock signal is lower than the potential of the third level of the fourth clock signal.

7. The shift register according to claim 5, characterized in that: The first clock signal and the second clock signal further include a second level, the second level being different from the first level; The potential of the second level of the first clock signal is different from the potential of the second level of the second clock signal; and / or, The third clock signal and the fourth clock signal further include a fourth level, and the fourth level is different from the third level; A potential of a fourth level of the third clock signal is different from a potential of a fourth level of the fourth clock signal.

8. The shift register according to claim 7, characterized in that: The potential of the second level of the first clock signal is greater than the potential of the second level of the second clock signal; and / or, The potential of the fourth level of the third clock signal is greater than the potential of the fourth level of the fourth clock signal.

9. The shift register according to any one of claims 1 to 8, characterized in that: The shift register further includes a first power signal line, a second power signal line, a third power signal line and a fourth power signal line; The input subcircuit is electrically connected to the first power signal line, the first control subcircuit is electrically connected to the third power signal line, the second control subcircuit is electrically connected to the fourth power signal line, and the output subcircuit is electrically connected to the second power signal line and the third power signal line.

10. The shift register according to claim 9, characterized in that: The potential of the first power signal transmitted by the first power signal line is lower than the potential of the second power signal transmitted by the second power signal line; the potential of the third power signal transmitted by the third power signal line is lower than the potential of the fourth power signal transmitted by the fourth power signal line; The potential of the second power signal is lower than the potential of the third power signal.

11. The shift register according to claim 10, characterized in that: The potential of the first level of the first clock signal is equal to the potential of the first power signal, and the potential of the second level of the first clock signal is equal to the potential of the fourth power signal; The potential of the first level of the second clock signal is equal to the potential of the second power signal, and the potential of the second level of the second clock signal is equal to the potential of the third power signal; The potential of the third level of the third clock signal is equal to the potential of the first power signal, and the potential of the fourth level of the third clock signal is equal to the potential of the fourth power signal; The potential of the third level of the fourth clock signal is equal to the potential of the second power signal, and the potential of the third level of the fourth clock signal is equal to the potential of the third power signal.

12. The shift register according to any one of claims 4 to 8, characterized in that: The pulse width of the first level of the first clock signal is smaller than the pulse width of the second level; and / or the pulse width of the third level of the third clock signal is smaller than the pulse width of the fourth level.

13. The shift register according to any one of claims 1 to 3, characterized in that: The input subcircuit includes a first transistor, a second transistor and a third transistor; The first electrode of the first transistor is electrically connected to the signal input terminal, the second electrode is electrically connected to the first node, and the control electrode is electrically connected to the first clock signal line; A first electrode of the second transistor is electrically connected to the second clock signal line, a second electrode is electrically connected to the second node, and a control electrode is electrically connected to the first node; The first electrode of the third transistor is electrically connected to the first power signal line, the second electrode is electrically connected to the second node, and the control electrode is electrically connected to the second clock signal line.

14. The shift register according to any one of claims 1 to 8, characterized in that: The input subcircuit includes a first transistor, a second transistor and a third transistor; The first electrode of the first transistor is electrically connected to the signal input terminal, the second electrode is electrically connected to the first node, and the control electrode is electrically connected to the first clock signal line; A first electrode of the second transistor is electrically connected to the first clock signal line, a second electrode is electrically connected to the second node, and a control electrode is electrically connected to the first node; The first electrode of the third transistor is electrically connected to the first power signal line, the second electrode is electrically connected to the second node, and the control electrode is electrically connected to the second clock signal line.

15. The shift register according to any one of claims 1 to 8, characterized in that: The input subcircuit includes a first transistor, a second transistor and a third transistor; The first electrode of the first transistor is electrically connected to the signal input terminal, the second electrode is electrically connected to the first node, and the control electrode is electrically connected to the first clock signal line; A first electrode of the second transistor is electrically connected to the second clock signal line, a second electrode is electrically connected to the second node, and a control electrode is electrically connected to the first node; The first electrode of the third transistor is electrically connected to the first power signal line, the second electrode is electrically connected to the second node, and the control electrode is electrically connected to the first clock signal line.

16. The shift register according to any one of claims 1 to 8, characterized in that: The shift register further includes an isolation subcircuit; The isolation subcircuit is configured to isolate the first node from the first control subcircuit electrically connected to the first node; isolating the first node and the output subcircuit electrically connected to the first node; and, isolating the second node from the second control subcircuit electrically connected to the second node; The first control subcircuit is electrically connected to the fifth node; the output subcircuit is electrically connected to the fifth node; The second control subcircuit is electrically connected to a fourth node.

17. The shift register according to claim 16, characterized in that: The isolation subcircuit includes an eleventh transistor and a twelfth transistor; The eleventh transistor has a first electrode electrically connected to the second node, a second electrode electrically connected to the fourth node, and a control electrode electrically connected to the first power signal line; The first electrode of the twelfth transistor is electrically connected to the first node, the second electrode is electrically connected to the fifth node, and the control electrode is electrically connected to the second power signal line.

18. The shift register according to claim 16, characterized in that: The isolation subcircuit includes an eleventh transistor and a twelfth transistor; The eleventh transistor has a first electrode electrically connected to the second node, a second electrode electrically connected to the fourth node, and a control electrode electrically connected to the first power signal line; The first electrode of the twelfth transistor is electrically connected to the first node, the second electrode is electrically connected to the fifth node, and the control electrode is electrically connected to the first power signal line.

19. The shift register according to claim 16, characterized in that: The first control subcircuit includes a fourth transistor, a fifth transistor and a third capacitor; The first electrode of the fourth transistor is electrically connected to the third clock signal line, the second electrode is electrically connected to the second electrode of the fifth transistor, and the control electrode is electrically connected to the fifth node; The first electrode of the fifth transistor is electrically connected to the third power signal line, the second electrode is electrically connected to the first electrode plate of the third capacitor, and the control electrode is electrically connected to the second node; The second plate of the third capacitor is electrically connected to the fifth node.

20. The shift register according to claim 16, characterized in that: The second control subcircuit includes a sixth transistor, a seventh transistor, an eighth transistor and a first capacitor; The first electrode of the sixth transistor is electrically connected to the fourth clock signal line, the second electrode is electrically connected to the first electrode of the seventh transistor, and the control electrode is electrically connected to the fourth node and the first electrode plate of the first capacitor; The first electrode of the seventh transistor is electrically connected to the second electrode plate of the first capacitor, the second electrode is electrically connected to the third node, and the control electrode is electrically connected to the fourth clock signal line; The first electrode of the eighth transistor is electrically connected to the fourth power signal line, the second electrode is electrically connected to the third node, and the control electrode is electrically connected to the first node.

21. The shift register according to claim 16, characterized in that: The second control subcircuit includes a sixth transistor, a seventh transistor, an eighth transistor, a thirteenth transistor and a first capacitor; The first electrode of the sixth transistor is electrically connected to the fourth clock signal line, the second electrode is electrically connected to the first electrode of the seventh transistor, and the control electrode is electrically connected to the fourth node and the first electrode plate of the capacitor; The first electrode of the seventh transistor is electrically connected to the second electrode plate of the first capacitor, the second electrode is electrically connected to the third node, and the control electrode is electrically connected to the fourth clock signal line; The first electrode of the eighth transistor is electrically connected to the fourth power signal line, the second electrode is electrically connected to the third node, and the control electrode is electrically connected to the first node; The first electrode of the thirteenth transistor is electrically connected to the fourth power signal line, the second electrode is electrically connected to the first node, and the control electrode is electrically connected to a preset control terminal.

22. The shift register according to claim 16, characterized in that: The input subcircuit includes a first transistor, a second transistor, a third transistor and a fourteenth transistor; The first electrode of the first transistor is electrically connected to the signal input terminal, the second electrode is electrically connected to the first node, and the control electrode is electrically connected to the first clock signal line; A first electrode of the second transistor is electrically connected to the second clock signal line, a second electrode is electrically connected to the second node, and a control electrode is electrically connected to the first node; The first electrode of the third transistor is electrically connected to the first power signal line, the second electrode is electrically connected to the second node, and the control electrode is electrically connected to the second clock signal line; The first electrode of the fourteenth transistor is electrically connected to the signal input terminal, the second electrode is electrically connected to the eighth node, and the control electrode is electrically connected to the first clock signal line.

23. The shift register according to any one of claims 1 to 8, characterized in that: The shift register further includes an isolation subcircuit; The isolation subcircuit is configured to isolate the first node from the first control subcircuit electrically connected to the first node; isolating the first node and the output subcircuit electrically connected to the first node; isolating the first node from the second control subcircuit electrically connected to the first node; and isolating the second node from the second control subcircuit electrically connected to the second node; The first control subcircuit is electrically connected to the fifth node; the output subcircuit is electrically connected to the fifth node; The second control subcircuit is electrically connected to the fourth node and the fifth node.

24. The shift register according to claim 23, characterized in that: The input subcircuit includes a first transistor, a second transistor, a third transistor and a fourteenth transistor; The first electrode of the first transistor is electrically connected to the signal input terminal, the second electrode is electrically connected to the first node, and the control electrode is electrically connected to the first clock signal line; A first electrode of the second transistor is electrically connected to the first clock signal line, a second electrode is electrically connected to the second node, and a control electrode is electrically connected to the first node; The first electrode of the third transistor is electrically connected to the first power signal line, the second electrode is electrically connected to the second node, and the control electrode is electrically connected to the second clock signal line; The first electrode of the fourteenth transistor is electrically connected to the signal input terminal, the second electrode is electrically connected to the eighth node, and the control electrode is electrically connected to the second clock signal line.

25. The shift register according to claim 24, characterized in that: The first control subcircuit includes a fourth transistor, a fifth transistor, a fifteenth transistor, a sixteenth transistor and a third capacitor; The first electrode of the fourth transistor is electrically connected to the third clock signal line, the second electrode is electrically connected to the second electrode of the fifth transistor, and the control electrode is electrically connected to the second electrode plate of the third capacitor; The first electrode of the fifth transistor is electrically connected to the third power signal line, the second electrode is electrically connected to the first electrode plate of the third capacitor, and the control electrode is electrically connected to the second node; The first electrode of the fifteenth transistor is electrically connected to the eighth node, the second electrode is electrically connected to the first electrode of the sixteenth transistor and the control electrode of the sixteenth transistor, and the control electrode is electrically connected to the first power signal line; The second electrode of the sixteenth transistor is electrically connected to the fifth node, and the control electrode is electrically connected to the control electrode of the fourth transistor.

26. The shift register according to claim 25, characterized in that: The second control subcircuit includes a sixth transistor, a seventh transistor, an eighth transistor, a thirteenth transistor and a first capacitor; The first electrode of the sixth transistor is electrically connected to the fourth clock signal line, the second electrode is electrically connected to the first electrode of the seventh transistor, and the control electrode is electrically connected to the fourth node and the first electrode plate of the first capacitor; The first electrode of the seventh transistor is electrically connected to the second electrode plate of the first capacitor, the second electrode is electrically connected to the third node, and the control electrode is electrically connected to the fourth clock signal line; The first electrode of the eighth transistor is electrically connected to the fourth power signal line, the second electrode is electrically connected to the third node, and the control electrode is electrically connected to the fifth node; The first electrode of the thirteenth transistor is electrically connected to the fourth power signal line, the second electrode is electrically connected to the fifth node, and the control electrode is electrically connected to a preset control terminal.

27. The shift register according to claim 23, characterized in that: The output subcircuit includes a ninth transistor, a tenth transistor and a second capacitor; The first electrode of the ninth transistor is electrically connected to the third power signal line and the first electrode plate of the second capacitor, the second electrode is electrically connected to the signal output terminal, and the control electrode is electrically connected to the third node; The first electrode of the tenth transistor is electrically connected to the second power signal line, the second electrode is electrically connected to the signal output terminal, and the control electrode is electrically connected to the fifth node; The second plate of the second capacitor is electrically connected to the third node.

28. A gate drive circuit, characterized in that: It comprises N cascaded shift registers; except for the first stage shift register, the signal input end of the i+1th stage shift register is electrically connected to the signal output end of the ith stage shift register; N is a positive integer greater than 1, and i is a positive integer less than or equal to N.

29. The gate driving circuit according to claim 28, characterized in that: The first clock signal line in the shift register of the i-th level is multiplexed as the fourth clock signal line in the shift register of the i+1-th level, the second clock signal line in the shift register of the i-th level is multiplexed as the first clock signal line in the shift register of the i+1-th level, the third clock signal line in the shift register of the i-th level is multiplexed as the second clock signal line in the shift register of the i+1-th level, and the fourth clock signal line in the shift register of the i-th level is multiplexed as the third clock signal line in the shift register of the i+1-th level.

30. The gate driving circuit according to claim 28, characterized in that: The first clock signal line in the shift register at the i-th level is multiplexed as the third clock signal line in the shift register at the i+1-th level, the second clock signal line in the shift register at the i-th level is multiplexed as the fourth clock signal line in the shift register at the i+1-th level, the third clock signal line in the shift register at the i-th level is multiplexed as the first clock signal line in the shift register at the i+1-th level, and the fourth clock signal line in the shift register at the i-th level is multiplexed as the second clock signal line in the shift register at the i+1-th level.

31. A display device, characterized in that: It comprises a pixel driving circuit and a gate driving circuit as claimed in any one of claims 28 to 30, wherein the gate driving circuit is electrically connected to the pixel driving circuit to provide a gate control signal to the pixel driving circuit.

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