Display device

Abstract

One embodiment of the present invention provides a display device comprising: a substrate including a driver island part and a wiring island part spaced apart from each other along a first direction and a bridge part connecting the driver island part and wiring island part; a gate driver circuit disposed on the driver island part; an electrostatic discharge protection circuit disposed on the driver island part; and a plurality of first input lines disposed on the wiring island part and extending along a second direction intersecting the first direction, wherein the first input lines include initiation signal wires, and the initiation signal wires are electrically connected to the electrostatic discharge protection circuit.

Description

display device

[0001] Embodiments of the present invention relate to a display device, for example, a flexible display device.

[0002] As display devices that visually display electrical signals evolve, a variety of display devices with superior characteristics, such as thinness, lightness, and low power consumption, are being introduced. For example, flexible display devices that can be folded or rolled are being introduced. Recently, active research and development is underway on stretchable display devices capable of transforming into various forms.

[0003] Embodiments of the present invention aim to provide a display device capable of achieving high-quality images by efficiently utilizing non-display space while improving stretchability. However, these tasks are exemplary and do not limit the scope of the present invention.

[0004] One embodiment of the present invention provides a display device, comprising: a substrate including a driver island portion; a wiring island portion spaced apart from the driver island portion along a first direction; and a bridge portion extending toward the driver island portion and the wiring island portion; a gate driving circuit disposed in the driver island portion; an anti-static circuit disposed in the driver island portion; and a plurality of first input lines disposed in the wiring island portion and extending along a second direction intersecting the first direction; wherein the plurality of first input lines include a start signal wire, and the start signal wire is electrically connected to the anti-static circuit.

[0005] In one embodiment, the driver island portion and the wiring island portion may be arranged alternately along the first direction, and the driver island portion and the wiring island portion may be arranged continuously along the second direction, respectively.

[0006] In one embodiment, the driver island portion is provided in plurality, the plurality of driver island portions include a first driver island portion, and the anti-static circuit may be arranged in the first driver island portion that is arranged at the frontmost end with respect to the second direction among the driver island portions that are arranged continuously along the second direction.

[0007] In one embodiment, the gate driving circuit includes a plurality of stages, and a first stage may be arranged at the front end of the plurality of stages in the first driver island section.

[0008] In one embodiment, the initiation signal wiring may be electrically connected to the first stage.

[0009] In one embodiment, the gate driving circuit may include at least one of a light emission control driving circuit, a bypass driving circuit, an initialization driving circuit, and a data write driving circuit.

[0010] In one embodiment, the plurality of first input lines may further include a gate high voltage wiring and a gate low voltage wiring.

[0011] In one embodiment, the device further includes a high-voltage connection wiring disposed in the bridge portion and connected to the gate high-voltage wiring; and a low-voltage connection wiring disposed in the bridge portion and connected to the gate low-voltage wiring; wherein the high-voltage connection wiring is connected to the static electricity prevention circuit and the gate driving circuit, respectively, and the low-voltage connection wiring can be connected to the static electricity prevention circuit and the gate driving circuit, respectively.

[0012] In one embodiment, the driver island section further includes a plurality of second input lines, wherein the plurality of second input lines may include at least one of a clock wire, a carry wire, and a reset signal wire.

[0013] In one embodiment, the device may further include a first dummy island portion arranged at the front end of the driver island portion with respect to the second direction; and a second dummy island portion arranged at the front end of the wiring island portion.

[0014] In one embodiment, the gate high voltage wiring and the gate low voltage wiring can extend along the second direction on the wiring island portion and the second dummy island portion.

[0015] In one embodiment, the initiation signal wiring may extend from the wiring island portion through the second dummy island portion and the first dummy island portion to the driver island portion.

[0016] In one embodiment, the start signal wiring disposed on the second dummy island portion may be bent from a portion extending along the second direction and extended toward the first dummy island portion along the first direction, and the start signal wiring disposed on the first dummy island portion may be bent from a portion extending along the first direction and extended toward the driver island portion along the second direction.

[0017] In one embodiment, the device may further include a first dummy bridge portion connecting the first dummy island portion and the second dummy island portion; a second dummy bridge portion connecting the driver island portion and the first dummy island portion; and a third dummy bridge portion connecting the wiring island portion and the second dummy island portion.

[0018] In one embodiment, the bridge portion, the first dummy bridge portion, the second dummy bridge portion, and the third dummy bridge portion may have a serpentine shape.

[0019] In one embodiment, the initiation signal wiring may be arranged on the first dummy bridge portion, the second dummy bridge portion, and the third dummy bridge portion.

[0020] In one embodiment, the device further includes a first bridge electrode disposed on the second dummy island portion and having gate high voltage wiring connected to both ends; and a second bridge electrode disposed on the second dummy island portion and having gate low voltage wiring connected to both ends; wherein the first bridge electrode and the second bridge electrode intersect the start signal wiring, but may be disposed on a different layer from the start signal wiring.

[0021] In one embodiment, the invention further includes a start signal connection wiring that electrically connects the start signal wiring and the anti-static circuit, wherein the start signal connection wiring can extend through the bridge portion.

[0022] In one embodiment, the initiation signal connection wiring may include a first portion disposed on the wiring island portion and intersecting the gate high voltage wiring and the gate low voltage wiring; and a second portion disposed on the bridge portion.

[0023] In one embodiment, the initiation signal wiring and the first portion may be disposed on different layers, and the initiation signal wiring and the second portion may be disposed on substantially the same layer.

[0024] In one embodiment, the initiation signal wiring and the first portion may be electrically connected through a first contact hole, and the first portion and the second portion may be electrically connected through a second contact hole.

[0025] In one embodiment, the device further includes an output wiring connected to the gate driving circuit and disposed in the bridge portion, wherein the output wiring and the start signal connection wiring may be disposed on substantially the same layer on the bridge portion.

[0026] According to one embodiment of the present invention, a display device can be provided that prevents damage due to concentrated stress and can be stretched in various directions. Furthermore, the display device according to one embodiment of the present invention can efficiently utilize space in non-display areas and reduce the load on wires, thereby achieving superior image quality. The aforementioned effects are exemplary and should not be construed as limiting the scope of the present invention.

[0027] FIG. 1 is a perspective view schematically showing a display device according to one embodiment of the present invention.

[0028] FIG. 2a and FIG. 2b are perspective views showing the display device of FIG. 1 extended in the first direction.

[0029] Figure 2c is a perspective view showing the display device of Figure 1 extended in the second direction.

[0030] Figure 2d is a perspective view showing the display device of Figure 1 extended in the first direction and the second direction.

[0031] Figure 2e is a perspective view showing the display device of Figure 1 extended in the third direction.

[0032] Figure 3 is a schematic plan view of a display device according to one embodiment of the present invention.

[0033] FIG. 4 is an enlarged plan view of part A of FIG. 3 as part of a display device according to one embodiment of the present invention.

[0034] FIG. 5 is a cross-sectional view schematically showing a main island portion and a main bridge portion arranged in a display area of ​​a display device according to one embodiment of the present invention.

[0035] FIGS. 6A to 6C are equivalent circuit diagrams of subpixels of a display device according to one embodiment of the present invention, respectively.

[0036] FIG. 7a and FIG. 7b are cross-sectional views schematically showing the main island portion of a display device according to one embodiment of the present invention, respectively.

[0037] FIGS. 8A to 8G are perspective views schematically illustrating embodiments of an electronic device including a display device according to one embodiment of the present invention, respectively.

[0038] Figure 9 is a schematic diagram of a display device according to one embodiment of the present invention.

[0039] FIG. 10 is a schematic diagram illustrating a gate driving circuit of a display device according to one embodiment of the present invention.

[0040] FIG. 11a is a circuit diagram showing one embodiment of a first light emission control stage included in the gate driving circuit of FIG. 10.

[0041] FIG. 11b is a circuit diagram showing one embodiment of a first bypass stage included in the gate driving circuit of FIG. 10.

[0042] FIG. 11c is a circuit diagram showing one embodiment of a first initialization stage included in the gate driving circuit of FIG. 10.

[0043] FIG. 11d is a circuit diagram showing one embodiment of an anti-static circuit included in a display device according to one embodiment of the present invention.

[0044] FIG. 12 is a schematic plan view showing an enlarged portion of a display device according to one embodiment of the present invention, and is an enlarged view of part B of FIG. 3.

[0045] FIG. 13 is a schematic plan view showing an enlarged portion of a display device according to one embodiment of the present invention, and is an enlarged view of part C of FIG. 12.

[0046] FIG. 14 is a cross-sectional view showing a part of a display device according to one embodiment of the present invention, corresponding to a cross-section taken along lines Ⅰ-Ⅰ' and Ⅱ-Ⅱ' of FIG. 13.

[0047] FIG. 15 is a schematic enlarged plan view of a portion of a display device according to another embodiment of the present invention, and is an enlarged view of portion C of FIG. 12.

[0048] FIG. 16 is a cross-sectional view showing a part of a display device according to another embodiment of the present invention, corresponding to a cross-section taken along line Ⅲ-Ⅲ' of FIG. 15.

[0049] The present invention is capable of various modifications and embodiments. Specific embodiments are illustrated in the drawings and described in detail in the detailed description. The effects and features of the present invention, as well as the methods for achieving them, will become clearer with reference to the embodiments described in detail below, along with the drawings. However, the present invention is not limited to the embodiments disclosed below and can be implemented in various forms.

[0050] Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings. When describing with reference to the drawings, identical or corresponding components are given the same reference numerals and redundant descriptions thereof will be omitted.

[0051] In the examples below, the terms first, second, etc. are not used in a limiting sense, but are used for the purpose of distinguishing one component from another.

[0052] In the examples below, singular expressions include plural expressions unless the context clearly indicates otherwise.

[0053] In the examples below, terms such as “include” or “have” mean that a feature or component described in the specification is present, and do not preclude the possibility that one or more other features or components may be added.

[0054] In the following examples, when a part such as a film, region, component, etc. is said to be on or above another part, it includes not only a case where it is directly on top of the other part, but also a case where another film, region, component, etc. is interposed in between.

[0055] For convenience of explanation, the sizes of components in the drawings may be exaggerated or reduced. For example, the sizes and thicknesses of each component shown in the drawings are arbitrarily indicated for convenience of explanation, and thus the present invention is not necessarily limited to what is shown.

[0056] In some embodiments, where implementations are otherwise feasible, specific process sequences may be performed in a different order than described. For example, two processes described in succession may be performed substantially simultaneously, or in a reverse order from the described order.

[0057] In this specification, “A and / or B” refers to the case where it is A, or B, or both A and B. In addition, “at least one of A or B” refers to the case where it is A, or B, or both A and B.

[0058] In the following examples, when it is said that a film, region, component, etc. are connected, it includes cases where the films, regions, components, etc. are directly connected, and / or cases where other films, regions, components, etc. are interposed between the films, regions, components, etc. and are indirectly connected. For example, when it is said in this specification that a film, region, component, etc. are electrically connected, it refers to cases where the films, regions, components, etc. are directly electrically connected, and / or cases where other films, regions, components, etc. are interposed between them and are indirectly electrically connected.

[0059] The x-axis, y-axis, and z-axis are not limited to the three axes in the Cartesian coordinate system, but can be interpreted in a broader sense that includes them. For example, the x-axis, y-axis, and z-axis may be orthogonal to each other, but they can also refer to different directions that are not orthogonal to each other.

[0060] Fig. 1 is a perspective view schematically illustrating a display device (1) according to one embodiment of the present invention. Figs. 2a and 2b are perspective views illustrating the display device (1) of Fig. 1 in a state extended in a first direction. Fig. 2c is a perspective view illustrating the display device (1) of Fig. 1 in a state extended in a second direction. Fig. 2d is a perspective view illustrating the display device of Fig. 1 in a state extended in the first and second directions. Fig. 2e is a perspective view illustrating the display device (1) of Fig. 1 in a state extended in a third direction.

[0061] Referring to FIG. 1, a display device (1) may include a display area (DA) and a non-display area (NDA). The display area (DA) may include a plurality of pixels. The display device (1) may provide a predetermined image using light emitted from the plurality of pixels. The non-display area (NDA) may be arranged outside the display area (DA). The non-display area (NDA) may entirely surround the display area (DA).

[0062] The display device (1) can be extended or contracted in various directions. The display device (1) can be extended in a first direction (e.g., the x direction and / or the -x direction) by an external force applied by an external object or a user. In one embodiment, as illustrated in FIGS. 2A and 2B, the display area (DA) and / or the non-display area (NDA) of the display device (1) can be extended in the first direction (e.g., the x direction and / or the -x direction). For example, as illustrated in FIG. 2A, the display device (1) can be extended along the x direction and the -x direction, or as illustrated in FIG. 2B, one side of the display device (1) can be fixed and the display device (1) can be extended along the x direction.

[0063] The display device (1) can be stretched in a second direction (e.g., the y direction and / or the -y direction) by an external force applied by an external object or a user. In one embodiment, as illustrated in FIG. 2 c, the display area (DA) and / or the non-display area (NDA) of the display device (1) can be stretched in the y direction and the -y direction. In another embodiment, one side of the display device (1) can be fixed while being stretched in the y direction or the -y direction.

[0064] The display device (1) can be stretched in a plurality of directions, for example, a first direction (e.g., the x direction and / or the -x direction) and a second direction (e.g., the y direction and / or the -y direction) by an external force applied by an external object or a part of a human body. As illustrated in Fig. 2d, the display area (DA) and / or the non-display area (NDA) of the display device (1) can be stretched in the ±x direction and the ±y direction.

[0065] The display device (1) can be elongated in a third direction (e.g., the z direction or the -z direction) by an external force applied by an external object or a part of a human body. In one embodiment, FIG. 2e illustrates that a part of the display device (1), for example, a part of the display area (DA), protrudes in the z direction. In another embodiment, a part of the display device (1), for example, a part of the display area (DA), can protrude along the z direction (or be sunken along the -z direction).

[0066] Although FIGS. 2A to 2E illustrate the display device (1) extending in the first direction, the second direction, and / or the third direction, the present invention is not limited thereto. In other embodiments, the display device (1) may be variously deformed into an irregular shape, such as being bent or twisted along two or more axes.

[0067] Figure 3 is a plan view schematically showing a display device (1) according to one embodiment of the present invention.

[0068] A plurality of pixels may be arranged in a display area (DA) of a display device (1). Each pixel may include subpixels that emit light of different colors. A light-emitting element corresponding to each subpixel may be arranged in the display area (DA). A circuit for providing electrical signals to the light-emitting elements arranged in the display area (DA) and to transistors electrically connected to the light-emitting elements may be located in a non-display area (NDA) surrounding the display area (DA). A gate driving circuit (GDC) may be arranged in a first non-display area (NDA1) and a second non-display area (NDA2) respectively arranged on both sides of the display area (DA). The gate driving circuit (GDC) may include drivers for providing electrical signals to the gate electrodes of each of the transistors electrically connected to the light-emitting elements. FIG. 3 illustrates that the gate driving circuit (GDC) is arranged in each of the first non-display area (NDA1) and the second non-display area (NDA2), but the present invention is not limited thereto. In another embodiment, the gate drive circuit (GDC) may be placed in either the first non-display area (NDA1) or the second non-display area (NDA2).

[0069] The data driving circuit (DDC) may be disposed in a third non-display area (NDA3) and / or a fourth non-display area (NDA4) connecting the first non-display area (NDA1) and the second non-display area (NDA2). In one embodiment, FIG. 3 illustrates that the data driving circuit (DDC) is disposed in the fourth non-display area (NDA4). In another embodiment, the data driving circuit (DDC) may be disposed in each of the third non-display area (NDA3) and the fourth non-display area (NDA4).

[0070] Although Fig. 3 illustrates that the data drive circuit (DDC) is arranged in the fourth non-display area (NDA4) of the display device (1), the present invention is not limited thereto. In another embodiment, the display device (1) may further include a flexible circuit board (not shown) electrically connected through a terminal portion (not shown) arranged in the fourth non-display area (NDA4), and the data drive circuit (DDC) may be arranged on the aforementioned flexible circuit board.

[0071] In some embodiments, the elongation rate of the non-display area (NDA) may be equal to or less than the elongation rate of the display area (DA). In one embodiment, the elongation rates of the non-display areas (NDAs) may be different for each area. For example, the first non-display area (NDA1), the second non-display area (NDA2), and the third non-display area (NDA3) may have substantially the same elongation rates, but the elongation rate of the fourth non-display area (NDA4) may be less than the elongation rates of each of the first non-display area (NDA1), the second non-display area (NDA2), and the third non-display area (NDA3).

[0072] FIG. 4 is an enlarged plan view of part A of FIG. 3 as part of a display device (1) according to one embodiment of the present invention.

[0073] Referring to FIG. 4, the display device (1) may include main island portions (11) spaced apart from each other in a first direction (e.g., x direction or -x direction) and a second direction (e.g., y direction or -y direction) in the display area (DA) and main bridge portions (12) extending to adjacent main island portions (11).

[0074] The main bridge parts (12) may be arranged to be spaced apart from each other by a first opening (CS1) located between the main bridge parts (12). The main bridge parts (12) may have a winding shape. For example, as illustrated in FIG. 4, the main bridge parts (12) may have a shape roughly similar to the letter 'S'.

[0075] Each main island unit (11) may be connected to a plurality of main bridge units (12). For example, each main island unit (11) may be extended to four main bridge units (12). Two main bridge units (12) may be arranged on both sides of the main island unit (11) along a first direction (e.g., x direction or -x direction), and the remaining two main bridge units (12) may be arranged on both sides of the main island unit (11) along a second direction (e.g., y direction or -y direction). The four main bridge units (12) may be connected to four side edges of the main island unit (11), respectively. Each of the four main bridge units (12) may be adjacent to each corner of the main island unit (11).

[0076] The display device (1) may include peripheral island portions (21) spaced apart from each other in a first direction (e.g., x direction or -x direction) and a second direction (e.g., y direction or -y direction) in a non-display area, for example, a first non-display area (NDA1) illustrated in FIG. 4, and peripheral bridge portions (22) extending to adjacent peripheral island portions (21).

[0077] The peripheral bridge portions (22) may be spaced apart from each other by a second opening (CS2) located between the peripheral bridge portions (22). The peripheral bridge portions (22) may have a winding shape. For example, as illustrated in FIG. 4, the peripheral bridge portions (22) may have approximately the shape of the letter 'S'. The size and / or width of the peripheral bridge portions (22) may be different from the size and / or width of the main bridge portion (12). For example, the size and / or width of the peripheral bridge portions (22) may be larger than the size and / or width of the main bridge portion (12). The radius of curvature of the rounded portion of the peripheral bridge portions (22) may be different from the radius of curvature of the rounded portion of the main bridge portion (12). For example, the radius of curvature of the rounded portion of the peripheral bridge portion (22) may be larger than the radius of curvature of the rounded portion of the main bridge portion (12).

[0078] Each peripheral island portion (21) may be connected to a plurality of peripheral bridge portions (22). The size and / or width of each peripheral island portion (21) may be different from the size and / or width of the main island portion (11). For example, the planar area of ​​the peripheral island portion (21) may be larger than the planar area of ​​the main island portion (11). Each peripheral island portion (21) may extend to four peripheral bridge portions (22). Two peripheral bridge portions (22) may be arranged on both sides of the peripheral island portion (21) along a first direction (e.g., the x direction or the -x direction), and the remaining two peripheral bridge portions (22) may be arranged on both sides of the peripheral island portion (21) along a second direction (e.g., the y direction or the -y direction). In one embodiment, the four peripheral bridge portions (22) may extend to each of the four side edges of the peripheral island portion (21). Each peripheral bridge section (22) can extend to the central portion of each side of the peripheral island section (21).

[0079] The peripheral islands (21) of any one row arranged in the first non-display area (NDA1) may correspond to the main islands (11) of a plurality of rows arranged in the display area (DA). For example, the peripheral islands (21) of any one row arranged in the first non-display area (NDA1) may correspond to the main islands (11) arranged in the (i)-th row of the display area (DA) and the main islands (11) arranged in the (i+1)-th row (here, i is a positive integer greater than 0). In another embodiment, the peripheral islands (21) of any one row may correspond to n rows of the main islands (11) (here, n is a positive integer greater than 3).

[0080] A non-display area, for example, a first non-display area (NDA1), may include a first sub-non-display area (SNDA1) in which the aforementioned peripheral islands (21) and peripheral bridges (22) are arranged, and a second sub-non-display area (SNDA2) between the first sub-non-display area (SNDA1) and the display area (DA). In the second sub-non-display area (SNDA2), sub-bridges (23) extending from the display area (DA) to the first sub-non-display area (SNDA1) may be arranged. One end of the sub-bridges (23) may extend to the peripheral islands (21), and the other end of the sub-bridges (23) may extend to the main islands (11). For example, one end of the sub-bridge section (23) may extend to the central portion of one side of the peripheral island section (21), and the other end of the sub-bridge section (23) may extend to the central portion of one side of the main island section (11).

[0081] The sub-bridge portion (23) may have a serpentine shape. In one embodiment, the shape of the sub-bridge portion (23) may be different from the shapes of the main bridge portion (12) and the peripheral bridge portions (22). The width of the sub-bridge portion (23) may be different from the width of the main bridge portion (12) and the width of the peripheral bridge portions (22). The width of the sub-bridge portion (23) may be larger than the width of the main bridge portion (12) and smaller than the width of the peripheral bridge portions (22). Third openings (CS3) and fourth openings (CS4) of different shapes may be alternately arranged between the sub-bridge portions (23) in the second direction (e.g., the y direction or the -y direction).

[0082] FIG. 5 is a cross-sectional view schematically showing a main island portion (11) and a main bridge portion (12) arranged in a display area (DA) of a display device (1) according to one embodiment of the present invention.

[0083] Referring to Fig. 5, the main island portion (11) and the main bridge portion (12) arranged in the display area (DA) may be spaced apart from each other with a first opening (CS1) therebetween. The main island portion (11) includes light-emitting elements (LEDs) and a circuit for driving the light-emitting elements (LEDs) electrically connected thereto, for example, a pixel driving circuit portion (PC), and the main bridge portion (12) may include wiring (WL) electrically connected to pixel driving circuit portions (PC) arranged in each of the adjacent main island portions (11).

[0084] Looking at the main island unit (11), a buffer layer (111) including an inorganic insulator is disposed on a substrate (100), and a pixel driver circuit unit (PC) may be disposed on the buffer layer (111). An insulating layer (IL) including an inorganic insulator and / or an organic insulator may be disposed between the pixel driver circuit unit (PC) and the light emitting element (LED). The light emitting element (LED) is disposed on the insulating layer (IL) and may be electrically connected to a corresponding pixel driver circuit unit (PC). The light emitting elements (LEDs) may emit light of different colors or the same color. In one embodiment, the light emitting elements (LEDs) may emit red, green, and blue light, respectively. In some embodiments, the light emitting elements (LEDs) may emit white light. In another embodiment, the light emitting elements (LEDs) may emit red, green, blue, and white light, respectively.

[0085] The substrate (100) may include a polymer resin such as polyethersulfone, polyarylate, polyether imide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyimide, polycarbonate, cellulose triacetate, or cellulose acetate propionate. In one embodiment, the substrate (100) may be a single layer including the aforementioned polymer resin. In another embodiment, the substrate (100) may be a multilayer structure including a base layer including the aforementioned polymer resin and a barrier layer including an inorganic insulating material. The substrate (100) including the polymer resin may have flexible, rollable, and bendable properties.

[0086] In one embodiment, FIG. 5 illustrates three pixel driver circuits (PCs) arranged in each main island unit (11) and three light-emitting elements (LEDs) connected to each pixel driver circuit unit (PC), but the present invention is not limited thereto. In another embodiment, the number of pixel driver circuits (PCs) and light-emitting elements (LEDs) arranged in the main island unit (11) may be one, two, four or more.

[0087] The encapsulation layer (300) may be disposed on a light-emitting element (LED) and may protect the light-emitting element (LED) from external force and / or moisture permeation. The encapsulation layer (300) may include an inorganic encapsulation layer and / or an organic encapsulation layer. In some embodiments, the encapsulation layer (300) may include a structure in which an inorganic encapsulation layer including an inorganic insulating material, an organic encapsulation layer including an organic insulating material, and an inorganic encapsulation layer including an inorganic insulating material are laminated. In other embodiments, the encapsulation layer (300) may include an organic material such as a resin. In some embodiments, the encapsulation layer (300) may include urethane epoxy acrylate. The encapsulation layer (300) may include a photosensitive material, for example, a material such as a photoresist.

[0088] Looking at the main bridge portion (12), an insulating layer (IL) including an organic insulating material may be placed on the substrate (100). When the display device (1) is extended, the main bridge portion (12), which is relatively subject to a large amount of deformation, may not have a layer including an inorganic insulating material that is prone to cracking, unlike the main island portion (11).

[0089] In one embodiment, the substrate (100) corresponding to the main bridge portion (12) may have the same laminated structure as the substrate (100) corresponding to the main island portion (11). In one embodiment, the substrate (100) corresponding to the main bridge portion (12) and the substrate (100) corresponding to the main island portion (11) may be polymer resin layers formed together in the same process. In another embodiment, the substrate (100) corresponding to the main bridge portion (12) may have a different laminated structure from the substrate (100) corresponding to the main island portion (11). In some embodiments, the substrate (100) corresponding to the main island portion (11) may have a multilayer structure including a base layer including a polymer resin and a barrier layer including an inorganic insulating material, and the substrate (100) corresponding to the main bridge portion (12) may have a structure of a polymer resin layer without a layer including an inorganic insulating material.

[0090] The wirings (WL) of the main bridge section (12) may be signal lines (e.g., gate lines, data lines, etc.) for providing electrical signals to transistors included in the pixel driving circuit section (PC) of the main island section (11), as described above, or voltage lines (e.g., driving voltage lines, initialization voltage lines, etc.) for providing voltage. An encapsulation layer (300) may also be arranged in the main bridge section (12). In another embodiment, the encapsulation layer (300) may not exist in the main bridge section (12).

[0091] Referring to FIGS. 4A to 4C and FIG. 5, the substrate (100) corresponding to the main island portion (11) and the substrate (100) corresponding to the main bridge portion (12) may be connected to each other. In other words, the plan views illustrated in FIGS. 4A to 4C may be substantially the same as the plan view of the substrate (100) of FIG. 5. In other words, the substrate (100) may include an area corresponding to the main island portion (11), an area corresponding to the main bridge portion (12), and an opening (100OP1) having the same shape as a first opening (CS1) that may be defined in the substrate (100).

[0092] Similarly, the encapsulation layer (300) corresponding to the main island portion (11) and the encapsulation layer (300) corresponding to the main bridge portion (12) may be connected to each other. For example, the plan views illustrated in FIGS. 4A to 4C above may be substantially identical to the plan views of the encapsulation layer (300). In other words, the encapsulation layer (300) may include an area corresponding to the main island portion (11), an area corresponding to the main bridge portion (12), and an opening (300OP1) having the same shape as the first opening (CS1) that may be defined in the encapsulation layer (300).

[0093] The circuit-light-emitting element layer (200) between the substrate (100) and the encapsulation layer (300) may include a buffer layer (111), a pixel driving circuit (PC), a wiring (WL), an insulating layer (IL), and a light-emitting element (LED). Similar to the substrate (100), the plan views previously illustrated in FIGS. 4A to 4C may be substantially identical to the plan views of the circuit-light-emitting element layer (200). In other words, the circuit-light-emitting element layer (200) may include an opening (200OP1) having the same shape as the first opening (CS1).

[0094] Figures 6a to 6c are equivalent circuit diagrams of subpixels of a display device (1) according to one embodiment of the present invention, respectively.

[0095] Referring to FIG. 6a, a light emitting element (LED) corresponding to a subpixel is electrically connected to a pixel driver circuit (PC), and the pixel driver circuit (PC) may include a first transistor (T1), a second transistor (T2), and a storage capacitor (Cst). The pixel driver circuit (PC) may be electrically connected to a signal line and a voltage line. The signal line may include a gate line such as a scan signal line (GWL) and a data line (DL), and the voltage line may include a first voltage line (VDDL).

[0096] The second transistor (T2) can be electrically connected to a scan signal line (GWL) and a data line (DL). The scan signal line (GWL) can provide a scan signal (GW) to a gate electrode of the second transistor (T2). The second transistor (T2) can transmit a data signal (Dm) input from a data line (DL) to the first transistor (T1) according to a scan signal (GW) input from the scan signal line (GWL).

[0097] The storage capacitor (Cst) is electrically connected to the second transistor (T2) and the first voltage line (VDDL), and can store a voltage corresponding to the difference between the voltage received from the second transistor (T2) and the first power supply voltage (VDD) supplied by the first voltage line (VDDL).

[0098] A first transistor (T1) is a driving transistor and can control a driving current flowing through a light-emitting element (LED). The first transistor (T1) can be connected to a first voltage line (VDDL) and a storage capacitor (Cst). The first transistor (T1) can control a driving current flowing through the light-emitting element (LED) from the first voltage line (VDDL) in response to a voltage value stored in the storage capacitor (Cst). The light-emitting element (LED) can emit light having a predetermined brightness by the driving current. A first electrode of the light-emitting element (LED) can be electrically connected to the first transistor (T1), and a second electrode of the light-emitting element (LED) can be electrically connected to a second voltage line (VSSL) that supplies a second power voltage (VSS).

[0099] Although FIG. 6a illustrates that the pixel driver circuit (PC) includes two transistors and one storage capacitor, in other embodiments, the pixel driver circuit (PC) may include three or more transistors.

[0100] Referring to FIG. 6b, the pixel driving circuit (PC) may include a first transistor (T1), a second transistor (T2), a third transistor (T3), a fourth transistor (T4), a fifth transistor (T5), a sixth transistor (T6), a seventh transistor (T7), and a storage capacitor (Cst).

[0101] The pixel driver circuit (PC) is electrically connected to signal lines and voltage lines. The signal lines may include gate lines such as a scan signal line (GWL), a bypass control line (GBL), an initialization control line (GIL), and an emission control line (EML), and a data line (DL). The voltage lines may include first and second initialization voltage lines (VIL1, VIL2) and a first voltage line (VDDL).

[0102] The first voltage line (VDDL) can transmit the first power voltage (VDD) to the first transistor (T1). The first initialization voltage line (VIL1) can transmit the first initialization voltage (Vint) that initializes the first transistor (T1) to the pixel driver circuit (PC). The second initialization voltage line (VIL2) can transmit the second initialization voltage (Vaint) that initializes the first electrode of the light-emitting element (LED) to the pixel driver circuit (PC).

[0103] The first transistor (T1) may be electrically connected to the first voltage line (VDDL) via the fifth transistor (T5) and may be electrically connected to the light-emitting element (LED) via the sixth transistor (T6). The first transistor (T1) functions as a driving transistor, and receives a data signal (Dm) according to the switching operation of the second transistor (T2) to supply a driving current to the light-emitting element (LED).

[0104] The second transistor (T2) is a data write transistor and is electrically connected to the scan signal line (GWL) and the data line (DL). The second transistor (T2) is electrically connected to the first voltage line (VDDL) via the fifth transistor (T5). The second transistor (T2) is turned on in response to the scan signal (GW) received through the scan signal line (GWL) and performs a switching operation to transmit the data signal (Dm) transmitted to the data line (DL) to the first node (N1).

[0105] The third transistor (T3) is electrically connected to the scan signal line (GWL) and is electrically connected to the light-emitting element (LED) via the sixth transistor (T6). The third transistor (T3) can be turned on according to the scan signal (GW) received through the scan signal line (GWL) to diode-connect the first transistor (T1).

[0106] The fourth transistor (T4) is a first initialization transistor and is electrically connected to an initialization control line (GIL) and a first initialization voltage line (VIL1). The fourth transistor (T4) is turned on according to an initialization control signal (GI) received through the initialization control line (GIL) to transmit the first initialization voltage (Vint) from the first initialization voltage line (VIL1) to the gate electrode of the first transistor (T1) to initialize the voltage of the gate electrode of the first transistor (T1). The initialization control signal (GI) may correspond to a scan signal of another pixel driving circuit unit arranged in a previous row of the corresponding pixel driving circuit unit (PC).

[0107] The fifth transistor (T5) may be a motion control transistor, and the sixth transistor (T6) may be a light-emitting control transistor. The fifth transistor (T5) and the sixth transistor (T6) are electrically connected to the light-emitting control line (EML), and are simultaneously turned on in response to a light-emitting control signal (EM) transmitted through the light-emitting control line (EML), thereby forming a current path so that a driving current can flow from the first voltage line (VDDL) toward the light-emitting element (LED).

[0108] The seventh transistor (T7) is a second initialization transistor and can be electrically connected to a bypass control line (GBL), a second initialization voltage line (VIL2), and a sixth transistor (T6). The seventh transistor (T7) is turned on according to a bypass control signal (GB) received through the bypass control line (GBL), and can transmit a second initialization voltage (Vaint) from the second initialization voltage line (VIL2) to a first electrode of a light-emitting element (LED) to initialize the first electrode of the light-emitting element (LED).

[0109] A storage capacitor (Cst) includes a first electrode (CE1) and a second electrode (CE2). The first electrode (CE1) is electrically connected to the gate electrode of the first transistor (T1), and the second electrode (CE2) is electrically connected to the first voltage line (VDDL). The storage capacitor (Cst) can maintain a voltage applied to the gate electrode of the first transistor (T1) by storing and maintaining a voltage corresponding to a difference between the voltages across the first voltage line (VDDL) and the gate electrode of the first transistor (T1).

[0110] Referring to FIG. 6c, the pixel driving circuit (PC) may include a first transistor (T1), a second transistor (T2), a third transistor (T3), a fourth transistor (T4), a fifth transistor (T5), a sixth transistor (T6), a seventh transistor (T7), an eighth transistor (T8), a ninth transistor (T9), a storage capacitor (Cst), and an auxiliary capacitor (Ca).

[0111] The pixel driver circuit (PC) is electrically connected to signal lines and voltage lines. The signal lines may include gate lines such as a scan signal line (GWL), a bypass control line (GBL), an initialization control line (GIL), and an emission control line (EML), and a data line (DL). The voltage lines may include first and second initialization voltage lines (VIL1, VIL2), a sustain voltage line (VSL), and a first voltage line (VDDL).

[0112] A first voltage line (VDDL) can transmit a first power voltage (VDD) to a first transistor (T1). A first initialization voltage line (VIL1) can transmit a first initialization voltage (Vint) for initializing the first transistor (T1) to a pixel driver circuit (PC). A second initialization voltage line (VIL2) can transmit a second initialization voltage (Vaint) for initializing a first electrode of a light-emitting element (LED) to the pixel driver circuit (PC). A sustain voltage line (VSL) can provide a sustain voltage (VSUS) to a second node (N2), for example, a second electrode (CE2) of a storage capacitor (Cst), during an initialization period and a data write period.

[0113] The first transistor (T1) may be electrically connected to the first voltage line (VDDL) via the fifth transistor (T5) and the eighth transistor (T8), and may be electrically connected to the light-emitting element (LED) via the sixth transistor (T6). The first transistor (T1) functions as a driving transistor, and may receive a data signal (Dm) according to the switching operation of the second transistor (T2) to supply a driving current to the light-emitting element (LED).

[0114] The second transistor (T2) is electrically connected to the scan signal line (GWL) and the data line (DL), and is electrically connected to the first voltage line (VDDL) via the fifth transistor (T5) and the eighth transistor (T8). The second transistor (T2) is turned on in response to the scan signal (GW) received through the scan signal line (GWL) and performs a switching operation to transmit the data signal (Dm) transmitted to the data line (DL) to the first node (N1).

[0115] The third transistor (T3) is electrically connected to the scan signal line (GWL) and is electrically connected to the light-emitting element (LED) via the sixth transistor (T6). The third transistor (T3) is turned on in response to the scan signal (GW) received through the scan signal line (GWL) and diode-connects the first transistor (T1), thereby compensating for the threshold voltage of the first transistor (T1).

[0116] The fourth transistor (T4) is electrically connected to the initialization control line (GIL) and the first initialization voltage line (VIL1), and is turned on according to the initialization control signal (GI) transmitted through the initialization control line (GIL) to transmit the first initialization voltage (Vint) from the first initialization voltage line (VIL1) to the gate electrode of the first transistor (T1) to initialize the voltage of the gate electrode of the first transistor (T1). The initialization control signal (GI) may correspond to a scan signal of another pixel driving circuit unit arranged in a previous row of the corresponding pixel driving circuit unit (PC).

[0117] The fifth transistor (T5), the sixth transistor (T6), and the eighth transistor (T8) are electrically connected to the light emission control line (EML), and are simultaneously turned on in response to the light emission control signal (EM) transmitted through the light emission control line (EML), thereby forming a current path so that a driving current can flow from the first voltage line (VDDL) in the direction of the light emitting element (LED).

[0118] The seventh transistor (T7) is a second initialization transistor and can be electrically connected to a bypass control line (GBL), a second initialization voltage line (VIL2), and a sixth transistor (T6). The seventh transistor (T7) is turned on according to a bypass control signal (GB) received through the bypass control line (GBL) to transmit a second initialization voltage (Vaint) from the second initialization voltage line (VIL2) to the first electrode of the light emitting element (LED) to initialize the first electrode of the light emitting element (LED).

[0119] The ninth transistor (T9) can be electrically connected to a bypass control line (GBL), a second electrode (CE2) of a storage capacitor (Cst), and a holding voltage line (VSL). The ninth transistor (T9) is turned on according to a bypass control signal (GB) received through the bypass control line (GBL), and can transmit a holding voltage (VSUS) to a second node (N2), for example, the second electrode (CE2) of the storage capacitor (Cst), during an initialization section and a data writing section.

[0120] The eighth transistor (T8) and the ninth transistor (T9) may be electrically connected to a second node (N2), for example, a second electrode (CE2) of a storage capacitor (Cst), respectively. In some embodiments, the eighth transistor (T8) may be turned off and the ninth transistor (T9) may be turned on in the initialization period and the data writing period, and the eighth transistor (T8) may be turned on and the ninth transistor (T9) may be turned off in the light emitting period. Since the sustain voltage (VSUS) is transmitted to the second node (N2) in the initialization period and the data writing period, the uniformity of the luminance (e.g., LRU, Long Range Uniformity) of the display device according to the voltage drop of the first voltage line (VDDL) may be improved.

[0121] The storage capacitor (Cst) includes a first electrode (CE1) and a second electrode (CE2). The first electrode (CE1) is electrically connected to the gate electrode of the first transistor (T1), and the second electrode (CE2) is electrically connected to the eighth transistor (T8) and the ninth transistor (T9).

[0122] The auxiliary capacitor (Ca) can be electrically connected to the sixth transistor (T6), the sustain voltage line (VSL), and the first electrode of the light-emitting element (LED). The auxiliary capacitor (Ca) stores and maintains a voltage corresponding to the voltage difference between the first electrode of the light-emitting element (LED) and the sustain voltage line (VSL) while the seventh transistor (T7) and the ninth transistor (T9) are turned on, thereby preventing the problem of the black luminance increasing when the sixth transistor (T6) is turned off.

[0123] FIGS. 7A and 7B are cross-sectional views schematically showing the main island of a display device according to one embodiment of the present invention.

[0124] Referring to FIGS. 7A and 7B, the main island portion (11, FIG. 4) of the display device according to one embodiment of the present invention may include a pixel driver circuit unit (PC) and a light-emitting element (LED, FIG. 6A). The light-emitting element (LED, FIG. 6A) may include an organic light-emitting diode (220) as in FIG. 7A or an inorganic light-emitting diode (230) as in FIG. 7B. A pixel driver circuit unit (PC) may be arranged between the substrate (100) and the light-emitting element (LED, FIG. 6A). The pixel driver circuit unit (PC) may include a transistor and a storage capacitor as described above with reference to FIGS. 6A to 6C. In one embodiment, the pixel driver circuit unit (PC) is illustrated as having the same structure as the pixel driver circuit unit (PC) described with reference to FIG. 6A, and the specific structure is as described above.

[0125] First, referring to FIG. 7a, the substrate (100) corresponding to the main island portion (11, FIG. 4) may include a first sub-substrate (101), a first barrier layer (102), a second sub-substrate (103), and a second barrier layer (104). The first sub-substrate (101) and the second sub-substrate (103) may each include a polymer resin such as polyethersulfone, polyarylate, polyether imide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyimide, polycarbonate, cellulose triacetate, cellulose acetate propionate, etc. The first barrier layer (102) and the second barrier layer (104) may each include an inorganic insulating material such as silicon oxide, silicon nitride, or silicon oxynitride.

[0126] A buffer layer (111) is disposed on the substrate (100), and a pixel driving circuit (PC) may be disposed on the buffer layer (111). The buffer layer (111) may include an inorganic insulating material such as silicon oxide, silicon nitride, or silicon oxynitride.

[0127] The pixel driver circuit (PC) may include a transistor (TFT). The transistor (TFT) may include a semiconductor layer (Act), a gate electrode (GE), a source electrode (SE), and a drain electrode (DE). Fig. 7a illustrates a top gate type in which the gate electrode (GE) is disposed on the semiconductor layer (Act) with a gate insulating layer (113) therebetween, but according to another embodiment, the transistor (TFT) may be a bottom gate type.

[0128] The semiconductor layer (Act) may include polysilicon. Alternatively, the semiconductor layer (Act) may include amorphous silicon, an oxide semiconductor, an organic semiconductor, etc. The gate electrode (GE) may include a low-resistance metal material. The gate electrode (GE) may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may be formed as a multilayer or single layer including the above materials.

[0129] The gate insulating layer (113) between the semiconductor layer (Act) and the gate electrode (GE) may include an inorganic insulating material such as silicon oxide, nitrogen oxide, silicon oxynitride, aluminum oxide, or titanium oxide. The gate insulating layer (113) may be a single layer or a multilayer including the aforementioned material.

[0130] The source electrode (SE) and the drain electrode (DE) may be positioned on the same layer, for example, the second interlayer insulating layer (117), and may each include the same material. The source electrode (SE) and the drain electrode (DE) may include a material having relatively good conductivity. The source electrode (SE) and the drain electrode (DE) may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may be formed as a multilayer or a single layer including the above-mentioned materials. In one embodiment, the source electrode (SE) and the drain electrode (DE) may be formed as a multilayer structure of a titanium layer, an aluminum layer, and a titanium layer (Ti / Al / Ti). The second interlayer insulating layer (117) may include an inorganic insulating material such as silicon oxide, nitrogen oxide, silicon oxynitride, aluminum oxide, or titanium oxide, and may be a single layer or a multilayer including the above-mentioned materials.

[0131] The storage capacitor (Cst) may include a first electrode (CE1) and a second electrode (CE2) that overlap with a first interlayer insulating layer (115) therebetween. The storage capacitor (Cst) may overlap with the transistor (TFT). In this regard, FIG. 7A illustrates that the gate electrode (GE) of the transistor (TFT) is the first electrode (CE1) of the storage capacitor (Cst). In another embodiment, the storage capacitor (Cst) may not overlap with the transistor (TFT). The storage capacitor (Cst) may be covered with a second interlayer insulating layer (117). The second electrode (CE2) of the storage capacitor (Cst) may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), or the like, and may be formed as a multilayer or single layer including the above materials. The first interlayer insulating layer (115) may be disposed between the gate insulating layer (113) and the second interlayer insulating layer (117). The first interlayer insulating layer (115) may include an inorganic insulating material such as silicon oxide, nitrogen oxide, silicon oxynitride, aluminum oxide, or titanium oxide, and may be a single layer or multilayer including the aforementioned materials.

[0132] The size or area of ​​the inorganic insulating layer (IOL) corresponding to the main island portion (11, FIG. 4) may be smaller than the size or area of ​​the main island portion (11, FIG. 4). In other words, the size or area of ​​the inorganic insulating layer (IOL) disposed on the substrate (100) may be smaller than the size or area of ​​the first sub-substrate (101), the first barrier layer (102), and / or the second sub-substrate (103) of the substrate (100). The inorganic insulating layer (IOL) on the substrate (100) may include, for example, a buffer layer (111), a gate insulating layer (113), a first interlayer insulating layer (115), and a second interlayer insulating layer (117).

[0133] The first organic insulating layer (119) may be disposed on the second interlayer insulating layer (117), and the second organic insulating layer (121) may be disposed on the first organic insulating layer (119). The first organic insulating layer (119) and the second organic insulating layer (121) may each include an organic insulating material such as polyimide.

[0134] The first connecting piece (CM1) may be disposed on the first organic insulating layer (119), and the second connecting piece (CM2) may be disposed on the second organic insulating layer (121). The first connecting piece (CM1) and the second connecting piece (CM2) may electrically connect a transistor (TFT) and a light-emitting element (LED, FIG. 6a). Each of the first connecting piece (CM1) and the second connecting piece (CM2) may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), or the like, and may be formed as a multilayer or single layer including the above materials.

[0135] The second voltage line (VSSL, FIG. 6a) is disposed on the second organic insulating layer (121), and the third organic insulating layer (123) may be disposed on the second organic insulating layer (121). The third organic insulating layer (123) may include an organic insulating material such as polyimide. The second voltage line (VSSL) may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), or the like, and may be formed as a multilayer or single layer including the above materials.

[0136] In one embodiment, as shown in FIG. 7A, a light-emitting element (LED, FIG. 6A) according to one embodiment of the present invention may include an organic light-emitting diode (220) including an organic material. The organic light-emitting diode (220) may include a first electrode (221) disposed on an insulating layer, a second electrode (225) facing the first electrode (221), and a light-emitting layer (223) interposed between the first electrode (221) and the second electrode (225). A first functional layer (222) may be disposed between the first electrode (221) and the light-emitting layer (223), and a second functional layer (224) may be disposed between the light-emitting layer (223) and the second electrode (225).

[0137] The edge of the first electrode (221) may be covered with a bank layer (BKL) including an insulating material. The bank layer (BKL) may include an opening (B-OP) overlapping the central portion of the first electrode (221).

[0138] The first electrode (221) may include a conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), or aluminum zinc oxide (AZO). In another embodiment, the first electrode (221) may include a reflective layer including silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or a compound thereof. In another embodiment, the first electrode (221) may further include a layer formed of ITO, IZO, ZnO, AZO, or In2O3 on / under the aforementioned reflective layer.

[0139] The light-emitting layer (223) may include a polymer or low-molecular organic material that emits light of a predetermined color. The first functional layer (222) may include a hole transport layer (HTL) and / or a hole injection layer (HIL). The second functional layer (224) may include an electron transport layer (ETL) and / or an electron injection layer (EIL).

[0140] The second electrode (225) may be formed of a conductive material having a low work function. For example, the second electrode (225) may include a (semi-)transparent layer including silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), or an alloy thereof. Alternatively, the second electrode (225) may further include a layer such as ITO, IZO, ZnO, AZO, or In2O3 on the (semi-)transparent layer including the aforementioned material.

[0141] Next, referring to FIG. 7b, a light-emitting element (LED, FIG. 6) according to one embodiment of the present invention may include an inorganic light-emitting diode (230) including an inorganic material. The inorganic light-emitting diode (230) may include a first semiconductor layer (231), a second semiconductor layer (232), an intermediate layer (233) between the first semiconductor layer (231) and the second semiconductor layer (232), a first electrode (235) electrically connected to the first semiconductor layer (231), and a second electrode (238) electrically connected to the second semiconductor layer (232). The first electrode (235) and the second electrode (238) of the inorganic light-emitting diode (230) may be electrically connected to a first electrode pad (241) and a second electrode pad (242) respectively disposed on the same layer.

[0142] In some embodiments, the first semiconductor layer (231) may include a p-type semiconductor layer. The p-type semiconductor layer may be selected from semiconductor materials having a composition formula of InxAlyGa1-x-yN (0≤x≤1, 0≤y≤1, 0≤x+y≤1), such as GaN, AlN, AlGaN, InGaN, InN, InAlGaN, AlInN, etc., and may be doped with a p-type dopant such as Mg, Zn, Ca, Sr, or Ba.

[0143] The second semiconductor layer (232) may include, for example, an n-type semiconductor layer. The n-type semiconductor layer may be selected from semiconductor materials having a composition formula of InxAlyGa1-x-yN (0≤x≤1, 0≤y≤1, 0≤x+y≤1), such as GaN, AlN, AlGaN, InGaN, InN, InAlGaN, AlInN, etc., and may be doped with an n-type dopant such as Si, Ge, or Sn.

[0144] The intermediate layer (233) is a region where electrons and holes recombine, and as the electrons and holes recombine, they transition to a lower energy level and can generate light having a corresponding wavelength. The intermediate layer (233) can be formed by including, for example, a semiconductor material having a composition formula of InxAlyGa1-x-yN (0≤x≤1, 0≤y≤1, 0≤x+y≤1), and can be formed as a single quantum well structure or a multi-quantum well structure (MQW). In addition, it may include a quantum wire structure or a quantum dot structure.

[0145] Although Fig. 7b illustrates that the first semiconductor layer (231) includes a p-type semiconductor layer and the second semiconductor layer (232) includes an n-type semiconductor layer, the present invention is not limited thereto. In another embodiment, the first semiconductor layer (231) may include an n-type semiconductor layer and the second semiconductor layer (232) may include a p-type semiconductor layer.

[0146] The display device (1) according to the above-described embodiments can be used in various electronic devices capable of providing images. Here, the term "electronic device" refers to a device that uses electricity and can provide a predetermined image.

[0147] FIGS. 8A to 8G are perspective views schematically illustrating embodiments of an electronic device including a display device according to one embodiment of the present invention, respectively.

[0148] Referring to FIG. 8A, a display device according to an embodiment of the present invention may be utilized in a wearable electronic device (3100) that can be worn on a part of a user's body. The wearable electronic device (3100) may include a body portion (3110) and a display portion (3120) provided on the body portion (3110). The display device according to embodiments of the present invention may be utilized as the display portion (3120) of the wearable electronic device (3100). As illustrated in FIG. 8A, the wearable electronic device (3100) may be transformable. In one embodiment, it may be utilized as a smart watch or a smartphone, depending on the user's selection.

[0149] FIG. 8B illustrates a medical electronic device (3200). In one embodiment, the medical electronic device (3200) may include a body portion (3210) and a light-emitting portion (3220). A display device according to embodiments of the present invention may be used as the light-emitting portion (3220) of the medical electronic device (3200). The light-emitting portion (3220) may emit light of a certain wavelength band (e.g., infrared, visible light, etc.) to the patient's body. In one embodiment, the body portion (3210) may have a stretchable fiber material and may have a structure that allows the light-emitting portion to be worn on the body of a user.

[0150] FIG. 8C illustrates an educational electronic device (3300). In one embodiment, the educational electronic device may include a display unit (3320) provided within a frame (3310). The display unit (3320) may use a display device according to embodiments of the present invention. The display unit (3320) may provide an image such as a sea with waves, a snow-covered mountain, or a volcano with flowing lava, wherein the display unit (3320) may expand in the height direction (e.g., the z direction) to reflect the height of the wave, mountain, or volcano. In some embodiments, a portion of the display unit (3320) may sequentially vary in height along the direction of flowing lava to show the movement of lava in three dimensions. The educational electronic device (3300) may include a plurality of pins (or stroke units, 3330) arranged on the back surface of the display unit (3320) so that the display unit (3320) expands in the height direction. The pins (3330) can be implemented to move along a third direction (e.g., the z direction or the -z direction) so that the image displayed on the display unit (3320) has a three-dimensional height. Fig. 8c describes an educational electronic device (3300), but its use is not limited to providing certain image information.

[0151] While the electronic devices illustrated in FIGS. 8A to 8C are described as electronic devices whose shapes can be variable, the present invention is not limited thereto. As described in the embodiments below, display devices according to embodiments of the present invention can be used in electronic devices in which a portion capable of displaying an image (e.g., a screen) is fixed.

[0152] FIG. 8D illustrates a robot (3400) as another electronic device according to one embodiment of the present invention. The robot (3400) can recognize movement or objects using a camera unit (3440) and display a predetermined image to a user through a display unit (3420, 3430). In some embodiments, since the display devices according to one embodiment of the present invention can extend in various directions as described above, they can be assembled into a body frame having a hemispherical shape, and thus the robot (3400) can include a hemispherical display unit (3420, 3430).

[0153] FIG. 8E illustrates a vehicle display device (3500) as another electronic device according to one embodiment of the present invention. The vehicle display device (3500) may include a cluster (3510), a center information display (CID) (3520), and / or a passenger display. Since the display device according to the embodiment of the present invention can be extended in various directions, it may be used in the cluster (3510), the center information display (CID) (3520), and / or the passenger display (or co-driver display) (3530) regardless of the shape of the internal frame of the vehicle.

[0154] Although FIG. 8E illustrates that the cluster (3510), the Center Information Display (CID) (3520), and / or the co-driver display (3530) are each separate, the present invention is not limited thereto. In another embodiment, two or more selected from the cluster (3510), the Center Information Display (CID) (3520), and the co-driver display may be connected integrally.

[0155] In some embodiments, a vehicle display device (3500) may include a button (3540) capable of displaying a predetermined image. Referring to the enlarged view of FIG. 8E, the hemispherical button (3540) may include an object (3542) that provides a user experience of the button while moving in the z-direction or -z-direction, and a display device positioned on the object (3542). In some embodiments, when the object (3542) has a three-dimensionally rounded surface, the display device may also have a three-dimensionally rounded surface.

[0156] FIG. 8F illustrates an electronic device according to one embodiment of the present invention, which is an electronic device (3600) for advertising or display purposes. In some embodiments, the electronic device (3600) for advertising or display purposes may be installed on a fixed structure (3610), such as a wall or a pillar. If the structure (3610) includes a recessed surface as illustrated in FIG. 8F, the electronic device (3600) for advertising or display purposes may also be positioned along the recessed surface of the structure (3610). In some embodiments, the electronic device (3600) for advertising or display purposes may be installed on the structure (3610) using a heat shrink film or the like.

[0157] FIG. 8G illustrates an electronic device according to one embodiment of the present invention as a controller (3700). The controller (3700) may include an image-type button. For example, the controller (3700) may include first to third button areas (3720, 3730, 3740) in which a portion of the display unit (3710) protrudes in the z direction or protrudes in the -z direction (or is sunken in the z direction). In some embodiments, the first and third button areas (3720, 3740) may protrude in the z direction, and the second button area (3730) may protrude in the -z direction (or is sunken in the z direction).

[0158] Figure 9 is a schematic diagram of a display device according to one embodiment of the present invention.

[0159] Referring to FIG. 9, a display area (DA) may include a plurality of pixels (PX) and signal lines capable of applying electrical signals to the plurality of pixels (PX). The signal lines capable of applying electrical signals to each of the pixels (PX) may include a plurality of data lines (DL), a plurality of emission control lines (EML), a plurality of scan signal lines (GWL), a plurality of initialization control lines (GIL), and a plurality of bypass control lines (GBL).

[0160] A driving circuit (DC) of a display device (10) that supplies a signal for driving pixels (PX) on the outside of a display area (DA) may be positioned. The driving circuit (DC) may include a data driving circuit (DDC) and a gate driving circuit (GDC, FIG. 3), and the gate driving circuit (GDC, FIG. 3) may include an emission control driving circuit (EMDC), a bypass driving circuit (GBDC), an initialization driving circuit (GIDC), and a data write driving circuit (GWDC). The data driving circuit (DDC) may be positioned adjacent to a lower side of the display area (DA), connected to data lines (DL), and output a data signal (Dm) to the data lines (DL).

[0161] An emission control driving circuit (EMDC, or first gate driving circuit), a bypass driving circuit (GBDC, or second gate driving circuit), an initialization driving circuit (GIDC, or third gate driving circuit), and a data write driving circuit (GWDC, or fourth gate driving circuit) may be arranged adjacent to a left side or a right side of a display area (DA). The emission control driving circuit (EMDC) may be connected to emission control lines (EML) and may output an emission control signal (EM) to the emission control lines (EML). The bypass driving circuit (GBDC) may be connected to bypass control lines (GBL) and may output a bypass control signal (GB) to the bypass control lines (GBL). The initialization driving circuit (GIDC) may be connected to initialization control lines (GIL) and may output an initialization control signal (GI) to the initialization control lines (GIL). The data write drive circuit (GWDC) is connected to scan signal lines (GWL) and can output a scan signal (GW).

[0162] Fig. 10 is a schematic diagram of a gate driving circuit according to one embodiment of the present invention. Fig. 10 is a diagram schematically showing the configuration of an emission control driving circuit (EMDC), a bypass driving circuit (GBDC), an initialization driving circuit (GIDC), and a data write driving circuit (GWDC).

[0163] Referring to Fig. 10, the light emission control driving circuit (EMDC) can be implemented as a shift register including a plurality of light emission control stages (EMST1, EMST2, EMST3, ...). Each of the light emission control stages (EMST1, EMST2, EMST3, ...) can be a sub-driving circuit. Each of the light emission control stages (EMST1, EMST2, EMST3, ...) is connected to a corresponding light emission control line (EML) and can output a light emission control signal (EM) to the corresponding light emission control line (EML). The first light emission control stage (EMST1) outputs the light emission control signal (EM) in response to an external start signal (STV), and each of the remaining light emission control stages (EMST2, EMST3, ...) other than the first light emission control stage (EMST1) can receive a carry signal (CR) output from a previous stage as a start signal. Each of the light emission control stages (EMST1, EMST2, EMST3, ...) can be connected to a plurality of input lines (IL) arranged outside the light emission control stages (EMST1, EMST2, EMST3, ...).

[0164] A bypass driving circuit (GBDC) can be implemented as a shift register including a plurality of bypass stages (GBST1, GBST2, GBST3, 쪋). Each of the bypass stages (GBST1, GBST2, GBST3, 쪋) can be a sub-driving circuit. Each of the bypass stages (GBST1, GBST2, GBST3, 쪋) is connected to a corresponding bypass control line (GBL) and can output a bypass control signal (GB) to the corresponding bypass control line (GBL). The first bypass stage (GBST1) outputs the bypass control signal (GB) in response to an external start signal (STV), and each of the remaining bypass stages (GBST2, GBST3, 쪋) other than the first bypass stage (GBST1) can receive a carry signal (CR) output from a previous stage as a start signal. Each of the bypass stages (GBST1, GBST2, GBST3, 쪋) can be connected to a plurality of input lines (IL) arranged outside the bypass stages (GBST1, GBST2, GBST3, 쪋).

[0165] An initialization driving circuit (GIDC) can be implemented as a shift register including a plurality of initialization stages (GIST1, GIST2, GIST3, ...). Each of the initialization stages (GIST1, GIST2, GIST3, ...) can be a sub-driving circuit. Each of the initialization stages (GIST1, GIST2, GIST3, ...) is connected to an initialization control line (GIL) and can output an initialization control signal (GI) to a corresponding initialization control line (GIL). The first initialization stage (GIST1) outputs the initialization control signal (GI) in response to an external start signal (STV), and each of the remaining stages (GIST2, GIST3, ...) other than the first initialization stage (GIST1) can receive a carry signal (CR) output from a previous stage as a start signal. Each of the initialization stages (GIST1, GIST2, GIST3, ...) can be connected to a plurality of input lines (IL) arranged outside the initialization stages (GIST1, GIST2, GIST3, ...).

[0166] A data write drive circuit (GWDC) can be implemented as a shift register including a plurality of data write stages (GWST1, GWST2, GWST3, ...). Each of the data write stages (GWST1, GWST2, GWST3, ...) can be a sub-drive circuit. Each of the data write stages (GWST1, GWST2, GWST3, ...) is connected to a corresponding scan signal line (GWL) and can output a scan signal (GW) to the corresponding scan signal line (GWL). The first data write stage (GWST1) outputs the scan signal (GW) in response to an external start signal (STV), and each of the remaining data write stages (GWST2, GWST3, ...) other than the first data write stage (GWST1) can receive a carry signal (CR) output from a previous stage as a start signal. Each of the data writing stages (GWST1, GWST2, GWST3, ...) can be connected to a plurality of input lines (IL) arranged outside the data writing stages (GWST1, GWST2, GWST3, ...).

[0167] The plurality of input lines (IL) may be signal lines including a plurality of voltage lines and a plurality of clock lines. In Fig. 10, only one input line is illustrated for convenience of illustration. The plurality of input lines (IL) may include a gate high voltage line (VGH, Fig. 13), a gate low voltage line (VGL), a start signal line (FLM, Fig. 13), a first clock line (CLK1, Fig. 13), a second clock line (CLK2, Fig. 13), a carry line (CRL), and a reset signal line (ESR, Fig. 13).

[0168] FIG. 11a is a circuit diagram showing one embodiment of a first light emission control stage included in the gate driving circuit of FIG. 10, FIG. 11b is a circuit diagram showing one embodiment of a first bypass stage included in the gate driving circuit of FIG. 10, and FIG. 11c is a circuit diagram showing one embodiment of a first initialization stage included in the gate driving circuit of FIG. 10.

[0169] First, referring to FIG. 11A, the first light emission control stage (EMST1) may include an input terminal (IN0), a first power input terminal (IN1), a second power input terminal (IN2), a first clock input terminal (CIN1), a second clock input terminal (CIN2), a reset terminal (RST), and an output terminal (OUT). The internal circuit configuration of the first light emission control stage (EMST1) may be substantially the same as that of other light emission control stages.

[0170] A first power input terminal (IN1) may be connected to a gate high voltage line (VGH, FIG. 13), a second power input terminal (IN2) may be connected to a gate low voltage line (VGL, FIG. 13), and a reset terminal (RST) may be connected to a reset signal line (ESR, FIG. 13). In addition, a first clock input terminal (CIN1) may be connected to a first clock line (CLK1), and a second clock input terminal (CIN2) may be connected to a second clock line (CLK2). An input terminal (IN0) may be connected to a start signal line (FLM, FIG. 13), and other light emission control stages other than the first light emission control stage (EMST1) may be connected to a carry line (CRL, FIG. 13) connected to an output terminal (OUT) of a previous stage.

[0171] The first emission control stage (EMST1) may include a node control unit (SST1), an output unit (SST2, or buffer unit), and a node maintenance unit (SST3).

[0172] First, the output unit (SST2) is connected to the first power input terminal (IN1) and the second power input terminal (IN2), and the output unit (SST2) can output the gate power voltage as a first gate signal to the output terminal (OUT) based on the voltage of the second control node (Q_F) and the voltage of the first control node (QB).

[0173] The output section (SST2) may include a ninth transistor (T9) (or a pull-up transistor) and a tenth transistor (T10) (or a pull-down transistor). The ninth transistor (T9) may include a first electrode connected to a first power input terminal, a second electrode connected to an output terminal (OUT), and a gate electrode connected to a first control node (QB).

[0174] The tenth transistor (T10) may include a first electrode connected to an output terminal (OUT), a second electrode connected to a second power input terminal (IN2), and a gate electrode connected to a second control node (Q_F).

[0175] The node control unit (SST1) can be connected to an input terminal (IN0), a first power input terminal (IN1), a second power input terminal (IN2), a first clock input terminal (CIN1), and a second clock input terminal (CIN2). The node control unit (SST1) can control the voltage of the first control node (QB) and the voltage of the second control node (Q_F) using a start signal (or a previous gate signal) provided through the input terminal (IN0) and a gate high voltage received from a gate high voltage line (VGH).

[0176] The node control unit (SST1) may include first, second, third, fourth, fifth, sixth, seventh, eleventh, twelfth, and thirteenth transistors (T1, T2, T3, T4, T5, T6, T7, T11, T12, T13), a second capacitor (C2), and a third capacitor (C3).

[0177] The first transistor (T1) may include a first electrode connected to an input terminal (IN0), a second electrode connected to a third control node (Q) (or a first electrode of a twelfth transistor (T12)), and a gate electrode connected to a first clock input terminal (CIN1). The second transistor (T2) may include a first electrode connected to a first power input terminal (IN1), a second electrode connected to a first electrode of a third transistor (T3), and a gate electrode connected to a first electrode of an eleventh transistor (T11).

[0178] The third transistor (T3) may include a first electrode connected to the second electrode of the second transistor (T2), a second electrode connected to the second clock input terminal (CIN2), and a gate electrode connected to the second control node (Q_F). The third capacitor (C3) is formed between the second electrode of the second transistor (T2) and the second control node (Q_F), and may include a first electrode connected to the second electrode of the second transistor (T2) and a second electrode connected to the second control node (Q_F).

[0179] The fourth transistor (T4) may be provided with a pair of transistors, connected in series between the gate electrode of the second transistor (T2) and the first clock input terminal (CIN1), and may include a gate electrode connected to the third control node (Q). The fifth transistor (T5) may include a first electrode connected to the gate electrode of the second transistor (T2), a second electrode connected to the second power input terminal (IN2), and a gate electrode connected to the first clock input terminal (CIN1).

[0180] The sixth transistor (T6) may include a first electrode connected to the first control node (QB), a second electrode connected to the first electrode of the seventh transistor (T7), and a gate electrode connected to the second clock input terminal (CIN2). The seventh transistor (T7) may include a first electrode connected to the second electrode of the sixth transistor (T6), a second electrode connected to the second clock input terminal (CIN2), and a gate electrode connected to the second electrode of the eleventh transistor (T11).

[0181] The second capacitor (C2) is formed between the second electrode of the eleventh transistor (T11) and the second electrode of the sixth transistor (T6), and may include a first electrode connected to the second electrode of the eleventh transistor (T11) and a second electrode connected to the second electrode of the sixth transistor (T6). The eleventh transistor (T11) may include a first electrode connected to the gate electrode of the second transistor (T2), a second electrode connected to the first electrode of the second capacitor (C2), and a gate electrode connected to a second power input terminal (IN2).

[0182] The twelfth transistor (T12) may include a first electrode connected to a third control node (Q) (or a second electrode of the first transistor (T1)), a second electrode connected to a second control node (Q_F), and a gate electrode connected to a second power input terminal (IN2). The thirteenth transistor (T13) may include a first electrode connected to a first power input terminal (IN1), a second electrode connected to a third control node (Q) (or a second electrode of the first transistor (T1)), and a gate electrode connected to a reset terminal (RST). Here, the reset terminal (RST) may be connected to a reset signal wire (ESR, FIG. 13). When the display device is turned on or off, a reset signal having a relatively low level is applied to the reset terminal (RST), and the 13th transistor (T13) is turned on in response to the reset signal having a relatively logic low level, so that a reset operation can be performed so that the voltage at the second electrode (and the third control node (Q)) of the first transistor (T1) has a relatively high level.

[0183] The node holding unit (SST3) can maintain the voltage of the first control node (QB) constant in response to the voltage of the third control node (Q). The node holding unit (SST3) can include a first capacitor (C1) and an eighth transistor (T8).

[0184] A first capacitor (C1) is formed between a first power input terminal (IN1) and a first control node (QB), and may include a first electrode connected to the first power input terminal (IN1) and a second electrode connected to the first control node (QB). The first capacitor (C1) may maintain a constant voltage difference between the first power input terminal (IN1) and the first control node (QB).

[0185] The eighth transistor (T8) may include a first electrode connected to the first power input terminal (IN1), a second electrode connected to the first control node (QB), and a gate electrode connected to the third control node (Q). The eighth transistor (T8) may maintain the voltage of the first control node (QB) constant in response to the voltage of the third control node (Q). For example, when the voltage of the third control node (Q) has a relatively low level, the eighth transistor (T8) may maintain the voltage of the first control node (QB) at a relatively high level using a gate high voltage.

[0186] Each of the first to thirteenth transistors (T1 to T13) may be a P-type transistor. In FIG. 11A, the first to twelfth transistors (T1 to T12) are illustrated as single-gate transistors, but are not limited thereto. For example, to improve reliability, at least one of the first to twelfth transistors (T1 to T12) may be implemented as a dual-gate transistor.

[0187] The light emission control signal (EM, Fig. 10) output from the first light emission control stage (EMST1) having the above configuration can be transmitted to the corresponding light emission control line (EML, Fig. 10) through the corresponding light emission control output wiring. In addition, the signal output from the first light emission control stage (EMST1) can be transmitted to the second light emission control stage (EMST2, Fig. 10) located at the next stage of the first light emission control stage (EMST1) through the carry wiring (CRL, Fig. 13).

[0188] Next, referring to FIG. 11b, the first bypass stage (GBST1) may include an input terminal (IN0), a first power input terminal (IN1), a second power input terminal (IN2), a first clock input terminal (CIN1), a second clock input terminal (CIN2), a reset terminal (RST), and an output terminal (OUT). The internal circuit configuration of the first bypass stage (GBST1) may be substantially the same as the other bypass stages.

[0189] A first power input terminal (IN1) may be connected to a gate high voltage line (VGH, FIG. 13), a second power input terminal (IN2) may be connected to a gate low voltage line (VGL, FIG. 13), and a reset terminal (RST) may be connected to a reset signal line (ESR, FIG. 13). In addition, a first clock input terminal (CIN1) may be connected to a first clock line (CLK1), and a second clock input terminal (CIN2) may be connected to a second clock line (CLK2). An input terminal (IN0) may be connected to a start signal line (FLM, FIG. 13), and other bypass stages other than the first bypass stage (GBST1) may be connected to a carry line (CRL, FIG. 13) connected to an output terminal (OUT) of a previous stage.

[0190] The first bypass stage (GBST1) may include a node control unit (SST1'), an output unit (SST2', or buffer unit), and a node maintenance unit (SST3'). The first bypass stage (GBST1) may be substantially the same as or similar to the first emission control stage (EMST1), except for the fourteenth to sixteenth transistors (T14, T15, T16). Therefore, any overlapping description will not be repeated.

[0191] The first bypass stage (GBST1) may further include fourteenth to sixteenth transistors (T14, T15, T16).

[0192] The fourteenth transistor (T14) may include a first electrode connected to the gate electrode of the third transistor (T3), a second electrode connected to the second control node (Q_F), and a gate electrode connected to the gate electrode of the third transistor (T3). That is, the fourteenth transistor (T14) may be diode-connected between the gate electrode of the third transistor (T3) and the second control node (Q_F). The fourteenth transistor (T14) may maintain the voltage of the second control node (Q_F) constant, regardless of voltage fluctuations of the gate electrode of the third transistor (T3), after a specific point in time.

[0193] The fifteenth transistor (T15) may include a first electrode connected to an input terminal (IN0), a second electrode connected to the first electrode of the sixteenth transistor (T16), and a gate electrode connected to a first clock input terminal (CIN1). The fifteenth transistor (T15) may initialize the gate electrode of the third transistor (T3) using a start signal (or a previous compensation gate signal) provided to the input terminal (IN0) in response to a first clock signal provided through the first clock input terminal (CIN1).

[0194] The sixteenth transistor (T16) may include a first electrode connected to a second electrode of the fifteenth transistor (T15), a second electrode connected to a gate electrode of the third transistor (T3), and a gate electrode connected to a second power input terminal (IN2). The sixteenth transistor (T16) may reduce or distribute a bias voltage applied to the fifteenth transistor (T15) between the input terminal (IN0) and the gate electrode of the third transistor (T3).

[0195] A bypass control signal (GB, Fig. 10) output from a first bypass stage (GBST1) having the above configuration can be transmitted to a corresponding bypass control line (GBL, Fig. 10) via a corresponding bypass output wire. In addition, a signal output from the first bypass stage (GBST1) can be transmitted to a second bypass stage (GBST2, Fig. 10) located at the next stage of the first bypass stage (GBST1) via a carry wire (CRL, Fig. 15).

[0196] Next, referring to FIG. 11c, the first initialization stage (GIST1) may include an input terminal (IN0), a first power input terminal (IN1), a second power input terminal (IN2), a first clock input terminal (CIN1), a second clock input terminal (CIN2), and an output terminal (OUT). The internal circuit configuration of the first initialization stage (GIST1) may be the same as the internal circuit configuration of the first data write stage (GWST1). In addition, the internal circuit configuration of the first initialization stage (GIST1) may be substantially the same as the other initialization stages, and the internal circuit configuration of the first data write stage (GWST1) may be substantially the same as the other data write stages.

[0197] A first power input terminal (IN1) may be connected to a gate high voltage line (VGH, FIG. 13), and a second power input terminal (IN2) may be connected to a gate low voltage line (VGL, FIG. 13). In addition, a first clock input terminal (CIN1) may be connected to a first clock line (CLK1), and a second clock input terminal (CIN2) may be connected to a second clock line (CLK2). An input terminal (IN0) may be connected to a start signal line (FLM, FIG. 13), and initialization stages other than the first initialization stage (GIST1) may be connected to a carry line (CRL, FIG. 13) connected to an output terminal (OUT) of a previous stage.

[0198] The first initialization stage (GIST1) may include a first node control unit (SST1''), a second node control unit (SST2''), and an output unit (SST3'').

[0199] The output unit (SST3'') can control the voltage supplied to the output terminal (OUT) in response to the voltages of the first node (N1) and the second node (N2). To this end, the output unit (SST3'') can include a sixth transistor (T6) and a seventh transistor (T7). The output unit (SST3'') can be driven by a buffer. The sixth transistor (T6) and the seventh transistor (T7) included in the output unit (SST3'') can be connected in parallel with each other as illustrated.

[0200] The sixth transistor (T6) may be connected between a first power input terminal (IN1) and an output terminal (OUT), which are connected to a gate high voltage line (VGH). The sixth transistor (T6) may control the connection between the first power input terminal (IN1) and the output terminal (OUT) in response to a voltage applied to the first node (N1). The sixth transistor (T6) may include a first electrode connected to the first power input terminal (IN1), a second electrode connected to the output terminal (OUT), and a gate electrode connected to the first node (N1).

[0201] The seventh transistor (T7) may be connected between the output terminal (OUT) and the second clock input terminal (CIN2) connected to the second clock line (CLK2). The seventh transistor (T7) may control the connection between the output terminal (OUT) and the second clock input terminal (CIN2) in response to the voltage applied to the second node (N2). The seventh transistor (T7) may include a first electrode connected to the output terminal (OUT), a second electrode connected to the second clock input terminal (CIN2), and a gate electrode connected to the second node (N2).

[0202] The first node control unit (SST1'') can control the voltage of the third node (N3) in response to signals supplied to the input terminal (IN0), the first clock input terminal (CIN1), and the second clock input terminal (CIN2). To this end, the first node control unit (SST1'') can include a first transistor (T1), a second transistor (T2), and a third transistor (T3).

[0203] A first transistor (T1) may be connected between an input terminal (IN0) to which a start signal (or a previous gate signal) is applied and a third node (N3). The first transistor (T1) may control the connection between the input terminal (IN0) and the third node (N3) through a first clock signal supplied to the first clock input terminal (CIN1). The first transistor (T1) may be provided with a dual gate structure to prevent leakage current. The first transistor (T1) may be provided with a pair of transistors, may be connected in series between the input terminal (IN0) and the third node (N3), and may include a gate electrode connected to the first clock input terminal (CIN1).

[0204] A second transistor (T2) and a third transistor (T3) may be connected in series between a third node (N3) and a first power input terminal (IN1). The third transistor (T3) may be connected between the second transistor (T2) and a third node (N3). The third transistor (T3) may control the connection between the second transistor (T2) and the third node (N3) in response to a second clock signal supplied to the second clock input terminal (CIN2). The third transistor (T3) may include a first electrode connected to a second electrode of the second transistor (T2), a second electrode connected to the third node (N3), and a gate electrode connected to the second clock input terminal (CIN2).

[0205] The second transistor (T2) may be connected between the third transistor (T3) and the first power input terminal (IN1). The second transistor (T2) may control the connection between the third transistor (T3) and the first power input terminal (IN1) in response to the voltage of the first node (N1). The second transistor (T2) may include a first electrode connected to the first power input terminal (IN1), a second electrode connected to the first electrode of the third transistor (T3), and a gate electrode connected to the first node (N1).

[0206] The second node control unit (SST2'') can control the voltage of the first node (N1) in response to the voltage of the first clock input terminal (CIN1) and the third node (N3). To this end, the second node control unit (SST2'') can include an eighth transistor (T8), a fourth transistor (T4), a fifth transistor (T5), a first capacitor (C1), and a second capacitor (C2).

[0207] A first capacitor (C1) may be connected between a first node (N1) and a first power input terminal (IN1). The first capacitor (C1) may charge a voltage applied to the first node (N1). The first capacitor (C1) may include a first electrode connected to the first node (N1) and a second electrode connected to the first power input terminal (IN1). The first electrode of the first capacitor (C1) may be connected to a gate electrode of a second transistor (T2) and a gate electrode of a sixth transistor (T6).

[0208] A second capacitor (C2) may be connected between a second node (N2) and an output terminal (OUT). The second capacitor (C2) charges a voltage corresponding to the turn-on and turn-off of the seventh transistor (T7). The second capacitor (C2) may include a first electrode connected to the second node (N2) and a second electrode connected to the output terminal (OUT). The first electrode of the second capacitor (C2) may be electrically connected to the second electrode of the eighth transistor (T8).

[0209] A fourth transistor (T4) may be connected between a first node (N1) and a first clock input terminal (CIN1). The fourth transistor (T4) may control the connection between the first node (N1) and the first clock input terminal (CIN1) in response to the voltage of the third node (N3). The fourth transistor (T4) may include a first electrode connected to the first clock input terminal (CIN1), a second electrode connected to the first node (N1), and a gate electrode connected to the third node (N3).

[0210] The fifth transistor (T5) may be located between the first node (N1) and the second power input terminal (IN2) connected to the gate low voltage line (VGL). The fifth transistor (T5) may control the connection between the first node (N1) and the second power input terminal (IN2) in response to the first clock signal of the first clock input terminal (CIN1). The fifth transistor (T5) may include a first electrode connected to the first node (N1), a second electrode connected to the second power input terminal (IN2), and a gate electrode connected to the first clock input terminal (CIN1).

[0211] The eighth transistor (T8) may be positioned between the third node (N3) and the second node (N2). The eighth transistor (T8) may maintain an electrical connection between the third node (N3) and the second node (N2) while maintaining a turn-on state. In addition, the eighth transistor (T8) may limit a voltage drop range of the third node (N3) in response to the voltage of the second node (N2). The eighth transistor (T8) may include a first electrode connected to the third node (N3), a second electrode connected to the second node (N2), and a gate electrode connected to a second power input terminal (IN2).

[0212] An initialization control signal (GI, Fig. 10) output from a first initialization stage (GIST1) having the above configuration can be transmitted to a corresponding initialization control line (GIL, Fig. 10) via a corresponding initialization output wire. In addition, a signal output from the first initialization stage (GIST1) can be transmitted to a second initialization stage (GIST2, Fig. 10) located at the next stage of the first initialization stage (GIST1) via a carry wire (CRL, Fig. 16).

[0213] FIG. 11d is a circuit diagram showing one embodiment of an anti-static circuit included in a display device according to one embodiment of the present invention.

[0214] A display device according to one embodiment of the present invention may include an electrostatic discharge (ESD) circuit. The electrostatic discharge (ESD) circuit may be arranged in front of a gate driving circuit (GDC, FIG. 3) in a non-display area (NDA, FIG. 3). The electrostatic discharge (ESD) circuit may discharge static electricity flowing in from the outside and protect internal circuits from static electricity. For example, the electrostatic discharge (ESD) circuit may protect the gate driving circuit (GDC) and pixels (PX).

[0215] Referring to FIG. 11D, the electrostatic discharge prevention circuit (ESD) may include an input terminal (IN0), a first power input terminal (IN1), a second power input terminal (IN2), and an output terminal (OUT). The input terminal (IN0) may be connected to a start signal wire (FLM), the first power input terminal (IN1) may be connected to a gate high voltage wire (VGH), and the second power input terminal (IN2) may be connected to a gate low voltage wire (VGL). That is, the electrostatic discharge prevention circuit (ESD) is electrically connected to the start signal wire (FLM) and may discharge static electricity flowing into the start signal wire (FLM).

[0216] An electrostatic discharge (ESD) protection circuit may include a first protection transistor (TP1), a second protection transistor (TP2), a third protection transistor (TP3), and a fourth protection transistor (TP4). Each of the first protection transistor (TP1), the second protection transistor (TP2), the third protection transistor (TP3), and the fourth protection transistor (TP4) may include a gate electrode, a first electrode, and a second electrode. At this time, the gate electrode of each of the first to fourth protection transistors (TP1, TP2, TP3, TP4) may be connected to the first electrode. Accordingly, each of the first to fourth protection transistors (TP1, TP2, TP3, TP4) may be configured as a transistor that is diode-connected in the reverse direction.

[0217] A first electrode of a first protection transistor (TP1) may be connected to a gate high voltage line (VGH), and a second electrode of a second protection transistor (TP2) may be electrically connected to a start signal line (FLM). When a voltage higher than a first power voltage of the gate high voltage line (VGH) is applied to the start signal line (FLM) due to static electricity, the first protection transistor (TP1) and the second protection transistor (TP2) may be turned on. In this case, a current (e.g., a current due to static electricity) flows from the start signal line (FLM) to the gate high voltage line (VGH), and a voltage at the start signal line (FLM) may be lowered. That is, the first protection transistor (TP1) and the second protection transistor (TP2) may drop a voltage higher than the first power voltage.

[0218] A first electrode of a third protection transistor (TP3) may be connected to a start signal line (FLM), and a second electrode of a fourth protection transistor (TP4) may be electrically connected to a gate low voltage line (VGL). When a voltage lower than a second power supply voltage of the gate low voltage line (VGL) is applied to the start signal line (FLM) due to static electricity, the third protection transistor (TP3) and the fourth protection transistor (TP4) may be turned on. In this case, current flows from the gate low voltage line (VGL) to the start signal line (FLM), and the voltage at the start signal line (FLM) may increase. That is, the third protection transistor (TP3) and the fourth protection transistor (TP4) may increase a voltage lower than the second power supply voltage.

[0219] The voltage at the start signal wire (FLM) is maintained between the first power supply voltage and the second power supply voltage by the first to fourth protection transistors (TP1, TP2, TP3, TP4), and the internal circuit can be protected from static electricity.

[0220] Meanwhile, a first resistor (R1) may be electrically connected between the input terminal (IN0) and the protection transistor. The first resistor (R1) may have a resistance value greater than that of the initiation signal wire (FLM). For example, the first resistor (R1) may have a narrower width than the initiation signal wire (FLM), may have a zigzag shape, or may include a material with low electrical conductivity. At this time, when a surge voltage having a relatively high voltage level is applied to the initiation signal wire (FLM), the first resistor (R1) may consume the energy of the surge voltage in the form of heat, and may prevent the protection transistor from being damaged by the surge voltage.

[0221] FIG. 12 is a schematic plan view showing an enlarged portion of a display device according to one embodiment of the present invention, and is an enlarged view of part B of FIG. 3.

[0222] Referring to FIG. 12, a plurality of peripheral islands (21) and a plurality of peripheral bridges (22) may be arranged in a non-display area (NDA, FIG. 3). The plurality of peripheral islands (21) may be arranged spaced apart from each other, and the peripheral bridges (22) may connect adjacent peripheral islands (21) to each other. In the present specification, the meaning of adjacent peripheral islands (21) being connected to each other by the peripheral bridges (22) means that the peripheral bridges (22) extend between adjacent peripheral islands (21), and the peripheral islands (21) and the plurality of peripheral bridges (22) are provided as one body.

[0223] The peripheral island (21) may include a driver island (DIP) on which a driver stage may be arranged, and a wiring island (WIP) on which input lines may be arranged. Specifically, at least one driver stage may be arranged in the driver island (DIP), and some of the input lines for applying signals or voltages to the driver stages may be arranged in the wiring island (WIP). However, not all of the input lines for applying signals or voltages to the driver stages may be arranged in the wiring island (WIP), and some may be arranged in the wiring island (WIP), and some may be arranged in the driver island (DIP). Hereinafter, some of the plurality of input lines arranged in the wiring island (WIP) may be referred to as first input lines (IL1, FIG. 13), and some of the remaining plurality of input lines arranged in the driver island (DIP) may be referred to as second input lines (IL2, FIG. 13).

[0224] The driver island portion (DIP) and the wiring island portion (WIP) can be arranged alternately in a first row along a first direction (e.g., x direction), and the driver island portion (DIP) and the wiring island portion (WIP) can be arranged in a second row parallel to the first row in the same manner as in the first row. That is, the driver island portions (DIP) can be arranged continuously in a first column along a second direction (e.g., y direction), and the wiring island portions (WIP) can be arranged continuously in a second column parallel to the first column. As a plurality of wiring island portions (WIP) are arranged continuously along the second direction, a plurality of first input lines (IL1, FIG. 12) can extend along the second direction (e.g., y direction). Likewise, as multiple driver islands (DIPs) are sequentially arranged along the second direction, multiple second input lines (IL2, FIG. 12) can extend along the second direction (e.g., the y direction).

[0225] For example, the driver island section (DIP) may include a first-first driver island section (DIP11), a first-second driver island section (DIP12), a second-first driver island section (DIP21), a second-second driver island section (DIP22), a third-first driver island section (DIP31), a third-second driver island section (DIP32), a fourth-first driver island section (DIP41), and a fourth-second driver island section (DIP42). The wiring island section (WIP) may include a first-first wiring island section (WIP11), a first-second wiring island section (WIP12), a second-first wiring island section (WIP21), a second-second wiring island section (WIP22), a third-first wiring island section (WIP31), a third-second wiring island section (WIP32), a fourth-first wiring island section (WIP41), and a fourth-2 wiring island section (WIP42).

[0226] In addition, the peripheral island portion (21) may further include a dummy island portion (DMI) in addition to the driver island portion (DIP) and the wiring island portion (WIP). The dummy island portion (DMI) may be a peripheral island portion (21) that is arranged in a non-display area (NDA) but is not arranged in an area where the gate driving circuit (GDC, FIG. 3) and the data driving circuit (DDC, FIG. 3) are excluded. For example, the dummy island portion (DMI) may be arranged on the outer side of the driver island portion (DIP) and the wiring island portion (WIP).

[0227] In one embodiment, a dummy island (DMI) may be arranged before a driver island (DIP) and a wiring island (WIP). For example, a first dummy island (DMI1) may be arranged above a 1-1 driver island (DIP11) where an emission control stage (EMST) is arranged, and a second dummy island (DMI2) may be arranged above a 1-1 wiring island (WIP11) where input lines of the emission control stage (EMST) are arranged. Similarly, a third dummy island (DMI3) may be arranged above a 2-1 driver island (DIP21) where a bypass stage (GBST) is arranged, and a fourth dummy island (DMI4) may be arranged above a 2-1 wiring island (WIP21). A fifth dummy island (DMI5) may be placed on the upper side of the 3-1 driver island (DIP31) where the initialization stage (GIST) is placed, and a sixth dummy island (DMI6) may be placed on the upper side of the 3-1 wiring island (WIP31). A seventh dummy island (DMI7) may be placed on the upper side of the 4-1 driver island (DIP41) where the data write stage (GWST) is placed, and an eighth dummy island (DMI8) may be placed on the upper side of the 4-1 wiring island (WIP41).

[0228] The peripheral bridge section (22) is a section that connects adjacent peripheral island sections (21) to form an extension structure, and may have a winding shape. The peripheral bridge section (22) may be arranged with a plurality of output lines that transmit the output signal of the driver and a plurality of connection lines that are connected to input lines to transmit the input signal.

[0229] The peripheral bridge portion (22) may include a vertical bridge portion (VBP) and a horizontal bridge portion (HBP). Specifically, the vertical bridge portion (VBP) is a peripheral bridge portion (22) that connects a driver island portion (DIP) and a wiring island portion (WIP), and may have an 'S' shape with respect to a first direction (e.g., x direction). The horizontal bridge portion (HBP) is a peripheral bridge portion (22) that connects adjacent driver island portions (DIPs) or connects adjacent wiring island portions (WIPs), and may have an 'S' shape with respect to a second direction (e.g., y direction). That is, the horizontal bridge portion (HBP) may have a shape that is obtained by rotating the shape of the vertical bridge portion (VBP) by 90 degrees.

[0230] The vertical bridge unit (VBP) may include a first vertical bridge unit (VBP1) and a second vertical bridge unit (VBP2). The first vertical bridge unit (VBP1) may be a peripheral bridge unit (22) disposed between a specific driver island unit (DIP) and a wiring island unit (WIP) on which input lines for applying signals to the driver island unit (DIP) are disposed. The second vertical bridge unit (VBP2) may be disposed between a specific driver island unit (DIP) and a wiring island unit (WIP) on which input lines for applying signals to a driver island unit (DIP) other than the specific driver island unit (DIP) are disposed. In other words, the first vertical bridge portion (VBP1) may be a peripheral bridge portion (22) arranged between a specific driver island portion (DIP) and a wiring island portion (WIP) associated with the driver island portion (DIP), and the second vertical bridge portion (VBP2) may be a peripheral bridge portion (22) arranged between a specific driver island portion (DIP) and a wiring island portion (WIP) not associated with the driver island portion (DIP).

[0231] Accordingly, the first vertical bridge portion (VBP1) can have both the output wiring of the driver and the connection wiring of the input lines arranged thereon, whereas the second vertical bridge portion (VBP2) can have only the output wiring of the driver arranged thereon. The first vertical bridge portion (VBP1) and the second vertical bridge portion (VBP2) can be alternately arranged along the first direction. For example, the first vertical bridge portion (VBP1) can include a 1-1 bridge portion (BP11), a 1-3 bridge portion (BP13), a 1-5 bridge portion (BP15), and a 1-7 bridge portion (BP17). The second vertical bridge portion (VBP2) can include a 1-2 bridge portion (BP12), a 1-4 bridge portion (BP14), a 1-6 bridge portion (BP16), and a 1-8 bridge portion (BP18).

[0232] The horizontal bridge portion (HBP) may include a first horizontal bridge portion (HBP1) and a second horizontal bridge portion (HBP2). The first horizontal bridge portion (HBP1) may be a peripheral bridge portion (22) connecting driver island portions (DIPs) arranged adjacent to each other. The second horizontal bridge portion (HBP2) may be a peripheral bridge portion (22) connecting wiring island portions (WIPs) arranged adjacent to each other. Accordingly, the first horizontal bridge portion (HBP1) and the second horizontal bridge portion (HBP2) may be arranged alternately along a first direction (e.g., an x-direction).

[0233] For example, the first horizontal bridge portion (HBP1) may include a second-first bridge portion (BP21), a second-third bridge portion (BP23), a second-fifth bridge portion (BP25), and a second-seventh bridge portion (BP27). The second horizontal bridge portion (HBP2) may include a second-second bridge portion (BP22), a second-fourth bridge portion (BP24), a second-sixth bridge portion (BP26), and a second-eighth bridge portion (BP28).

[0234] In addition, the peripheral bridge portion (22) may further include a dummy bridge portion (DMB) in addition to the vertical bridge portion (VBP) and the horizontal bridge portion (HBP). The dummy bridge portion (DMB) may connect dummy island portions (DMI) arranged adjacent to each other, connect adjacent dummy island portions (DMI) and driver island portions (DIP), or connect adjacent dummy island portions (DMI) and wiring island portions (WIP).

[0235] Specifically, the dummy bridge unit (DMB) may include a first dummy bridge unit (DMB1) and a fourth dummy bridge unit (DMB4) that connect adjacent dummy island units (DMIs), a second dummy bridge unit (DMB2) that connects adjacent dummy island units (DMIs) and a driver island unit (DIP), and a third dummy bridge unit (DMB3) that connects adjacent dummy island units (DMIs) and a wiring island unit (WIP).

[0236] In one embodiment, the first dummy bridge portion (DMB1) may be arranged in front of the first vertical bridge portion (VBP1) and may have the same shape as the first vertical bridge portion (VBP1). For example, the first dummy bridge portion (DMB1) may include a 1-1 dummy bridge portion (DMB11) connecting the first dummy island portion (DMI1) and the second dummy island portion (DMI2), a 1-2 dummy bridge portion (DMB12) connecting the third dummy island portion (DMI3) and the fourth dummy island portion (DMI4), a 1-3 dummy bridge portion (DMB13) connecting the fifth dummy island portion (DMI5) and the sixth dummy island portion (DMI6), and a 1-4 dummy bridge portion (DMB14) connecting the seventh dummy island portion (DMI7) and the eighth dummy island portion (DMI8).

[0237] In one embodiment, the fourth dummy bridge portion (DMB4) may be arranged in front of the second vertical bridge portion (VBP2) and may have the same shape as the second vertical bridge portion (VBP2). For example, the fourth dummy bridge portion (DMB4) may include a 4-1 dummy bridge portion (DMB41) connecting the second dummy island portion (DMI2) and the third dummy island portion (DMI3), a 4-2 dummy bridge portion (DMB42) connecting the fourth dummy island portion (DMI4) and the fifth dummy island portion (DMI5), a 4-3 dummy bridge portion (DMB43) connecting the sixth dummy island portion (DMI6) and the seventh dummy island portion (DMI7), and a 4-4 dummy bridge portion (DMB44) connected to the eighth dummy island portion (DMI8).

[0238] In one embodiment, the second dummy bridge portion (DMB2) may be arranged in front of the first horizontal bridge portion (HBP1) and may have the same shape as the first horizontal bridge portion (HBP1). For example, the second dummy bridge portion (DMB2) may include a second-first dummy bridge portion (DMB21) connecting the first dummy island portion (DMI1) and the first-first driver island portion (DIP11), a second-second dummy bridge portion (DMB22) connecting the third dummy island portion (DMI3) and the second-first driver island portion (DIP21), a second-third dummy bridge portion (DMB23) connecting the fifth dummy island portion (DMI5) and the third-first driver island portion (DIP31), and a second-fourth dummy bridge portion (DMB24) connecting the seventh dummy island portion (DMI7) and the fourth-first driver island portion (DIP41).

[0239] In one embodiment, the third dummy bridge portion (DMB3) may be arranged in front of the second horizontal bridge portion (HBP2) and may have the same shape as the second horizontal bridge portion (HBP2). For example, the third dummy bridge portion (DMB3) may include a third-first dummy bridge portion (DMB31) connecting the second dummy island portion (DMI2) and the first-first wiring island portion (WIP11), a third-second dummy bridge portion (DMB32) connecting the fourth dummy island portion (DMI4) and the second-first wiring island portion (WIP21), a third-third dummy bridge portion (DMB33) connecting the sixth dummy island portion (DMI6) and the third-first wiring island portion (WIP31), and a third-fourth dummy bridge portion (DMB34) connecting the eighth dummy island portion (DMI8) and the fourth-first wiring island portion (WIP41).

[0240] Meanwhile, the gate driving circuit (GDC, Fig. 3) arranged in the driver island part (DIP) may be arranged in the following order from the outer edge toward the display area (DA, Fig. 3): an emission control driving circuit (EMDC, Fig. 10), a bypass driving circuit (GBDC, Fig. 10), an initialization driving circuit (GIDC, Fig. 10), and a data write driving circuit (GWDC, Fig. 10). In addition, when the size and / or width of the peripheral island part (21) is larger than the size and / or width of the main island part (21, Fig. 4), as shown in Fig. 12, two driver stages may be arranged in the driver island part (DIP).

[0241] For example, a second light emission control stage (EMST2) and a third light emission control stage (EMST3) may be arranged in the first-second driver island section (DIP12), a second bypass stage (GBST2) and a third bypass stage (GBST3) may be arranged in the second-second driver island section (DIP22), a second initialization stage (GIST2) and a third initialization stage (GIST3) may be arranged in the third-second driver island section (DIP32), and a second data writing stage (GWST2) and a third data writing stage (GWST3) may be arranged in the fourth-second driver island section (DIP42). Likewise, two driver stages can be arranged in the driver islands (DIPs) arranged at the rear end of each of the 1-2 driver islands (DIP12), the 2-2 driver islands (DIP22), the 3-2 driver islands (DIP32), and the 4-2 driver islands (DIP42).

[0242] However, one driver stage may be placed on the 1-1 driver island (DIP11), 2-1 driver island (DIP21), 3-1 driver island (DIP31), and 4-1 driver island (DIP41) located at the front end of the driver island (DIP). Instead, an electrostatic discharge (ESD) protection circuit may be additionally placed on the driver island (DIP) located at the front end.

[0243] For example, a first electrostatic discharge prevention circuit (ESD) and a first light emission control stage (EMST1) may be arranged in the 1-1 driver island section (DIP11), a second electrostatic discharge prevention circuit (ESD2) and a first bypass stage (GBST1) may be arranged in the 2-1 driver island section (DIP21), a third electrostatic discharge prevention circuit (ESD3) and a first initialization stage (GIST1) may be arranged in the 3-1 driver island section (DIP31), and a fourth electrostatic discharge prevention circuit (ESD4) and a first data writing stage (GWST1) may be arranged in the 4-1 driver island section (DIP41).

[0244] As described above, the input lines for applying signals or voltages to each driver stage may include first input lines (IL1, FIG. 12) arranged in the wiring island section (WIP) and second input lines (IL2, FIG. 12) arranged in the driver island section (DIP). The first input lines (IL1, FIG. 12) may be arranged in the wiring island section (WIP), but may be extended as they are also arranged in the second horizontal bridge section (HBP2). The second input lines (IL2, FIG. 12) may be arranged in the driver island section (DIP), but may be extended as they are also arranged in the first horizontal bridge section (HBP1).

[0245] For example, some of the input lines supplying signals or voltages to the emission control stage (EMST) may extend from the 1-1 wiring island section (WIP11) to the 1-2 wiring island section (WIP12) via the 2-2 bridge section (BP22), and some of the remaining lines may extend from the 1-1 driver island section (DIP11) to the 1-2 driver island section (DIP12) via the 2-1 bridge section (BP21). Similarly, some of the input lines supplying signals or voltages to the bypass stage (GBST) may extend from the 2-1 wiring island section (WIP21) to the 2-2 wiring island section (WIP22) via the 2-4 bridge section (BP24), and some of the remaining lines may extend from the 2-1 driver island section (DIP21) to the 1-2 driver island section (DIP12) via the 2-3 bridge section (BP23). Some of the input lines supplying signals or voltages to the initialization stage (GIST) may extend from the 3-1 wiring island (WIP31) to the 3-2 wiring island (WIP22) via the 2-6 bridge (BP26), and some of the remaining lines may extend from the 3-1 driver island (DIP31) to the 3-2 driver island (DIP32) via the 2-5 bridge (BP25). Some of the input lines supplying signals or voltages to the data write stage (GWST) may extend from the 4-1 wiring island (WIP41) to the 4-2 wiring island (WIP42) via the 2-8 bridge (BP28), and some of the remaining lines may extend from the 4-1 driver island (DIP41) to the 4-2 driver island (DIP42) via the 2-7 bridge (BP27).

[0246] At this time, some of the first input lines (IL1, FIG. 13) may be extended and arranged to the dummy island section (DMI). For example, some of the first input lines (IL1, FIG. 13) arranged to the 1-1 wiring island section (WIP11) may be extended and arranged to the second dummy island section (DMI2), and may even be extended and arranged to the first dummy island section (DMI1). This will be described in detail later with reference to FIGS. 13 and 15.

[0247] Meanwhile, the output wiring for transmitting the output signal of each driver stage may extend toward the display area (DA, Fig. 3) along the first direction (e.g., the x-direction). Accordingly, the output wiring may be arranged in the same row as the driver island portion (DIP) on which the connected driver stage is arranged, but may extend through a plurality of vertical bridge portions (VBP) that are closer to the display area (DA, Fig. 3) than the corresponding driver island portion (DIP).

[0248] For example, the light emission control output wiring of the first light emission control stage (EMST1) may be arranged in the same row as the 1-1 driver island section (DIP11), but may extend through the 1-1 bridge section (BP11), the 1-2 bridge section (BP12), the 1-3 bridge section (BP13), the 1-4 bridge section (BP14), the 1-5 bridge section (BP15), the 1-6 bridge section (BP16), the 1-7 bridge section (BP17), and the 1-8 bridge section (BP18) that are closer to the display area (DA, FIG. 3) than the 1-1 driver island section (DIP11). Likewise, the bypass output wiring of the first bypass stage (GBST1) may be arranged in the same row as the second-first island section (DIP21), but may extend through the first-third bridge section (BP13), the first-fourth bridge section (BP14), the first-fifth bridge section (BP15), the first-sixth bridge section (BP16), the first-seventh bridge section (BP17), and the first-eighth bridge section (BP18) which are closer to the display area (DA, Fig. 3) than the second-first driver island section (DIP21). The initialization output wiring of the first initialization stage (GIST1) may be arranged in the same row as the 3-1 driver island section (DIP31), but may be extended through the 1-5 bridge section (BP15), the 1-6 bridge section (BP16), the 1-7 bridge section (BP17), and the 1-8 bridge section (BP18) which are closer to the display area (DA, FIG. 3) than the 3-1 driver island section (DIP31). The data write output wiring of the first data write stage (GWST1) may be arranged in the same row as the 4-1 driver island section (DIP41), but may be connected through the 1-7 bridge section (BP17) and the 1-8 bridge section (BP18) which are closer to the display area (DA, FIG. 3) than the 4-1 driver island section (DIP41).

[0249] Fig. 13 is a schematic plan view showing an enlarged portion of a display device according to one embodiment of the present invention, and is an enlarged view of portion C of Fig. 12. Fig. 14 is a cross-sectional view showing a portion of a display device according to one embodiment of the present invention, and corresponds to the cross-sections taken along lines I-I' and II-II' of Fig. 13.

[0250] First, referring to FIG. 13, a first electrostatic discharge prevention circuit (ESD) and a first light emission control stage (EMST1) may be arranged in the first-first driver island section (DIP11). The first light emission control stage (EMST1) may include a first light emission node control section (EMNC1) and a first light emission buffer transistor (EMBF1), and other light emission control stages (EMST, FIG. 12) may have substantially the same configuration. The first light emission node control section (EMNC1) may include a plurality of transistors and capacitors, and may control the voltage of a node using a start signal, etc. provided through an input terminal. The first light emission buffer transistor (EMBF1) may be a transistor arranged to isolate a signal source from a circuit driven by a signal source. The first light emission control stage (EMST1) may have substantially the same circuit configuration as the first light emission control stage (EMST1, FIG. 11a) illustrated in FIG. 11a. Additionally, the first electrostatic discharge prevention circuit (ESD1) may have a circuit configuration substantially identical to the electrostatic discharge prevention circuit (ESD) illustrated in FIG. 11d.

[0251] The output signal of the first light emission control stage (EMST1) can apply a light emission control signal (EM, Fig. 10) to the display area (DA, Fig. 3) through the first light emission control output wiring (EMO1). Specifically, the light emission control signal (EM, Fig. 10) output from the first light emission control stage (EMST1) is first transmitted to the first light emission control output wiring (EMO1), and then can be supplied to the pixels of the display area (DA, Fig. 3) through the light emission control line (EML, Fig. 10) connected to the first light emission control output wiring (EMO1). One output wiring can be arranged per stage, and when two light emission control stages (EMST, Fig. 12) are arranged, such as in the 1-2 driver island section (DIP12, Fig. 12), two light emission control output wirings can be arranged.

[0252] The first light emission control output wiring (EMO1) can be extended through the first-first bridge section (BP11), the first-first wiring island section (WIP11), and the first-second bridge section (BP12). In addition, although not shown in Fig. 13, the light emission control output wiring (EMO) can be extended toward the display area through the bypass drive circuit (GBDC, Fig. 10), the initialization drive circuit (GIDC, Fig. 10), and the data write drive circuit (GWDC, Fig. 10).

[0253] The first light emission control output wiring (EMO1) may be arranged on substantially the same layer as the source electrode (SE, FIG. 7a) of the main island portion (11, FIG. 4). Similarly, a plurality of first input lines (IL1) to be described later may also be arranged on substantially the same layer as the source electrode (SE, FIG. 7a). Accordingly, in order to avoid overlap between the first light emission control output wiring (EMO1) and the plurality of first input lines (IL1), the first light emission control output wiring (EMO1) may be extended through a bridge electrode (BE) in an area overlapping with the plurality of first input lines (IL1) on the 1-1 wiring island portion (WIP11). Referring to Fig. 14, the bridge electrode (BE) is arranged lower than the first input lines (IL1) and the first light emission control output wiring (EMO1), and at least one insulating layer may be interposed between the first light emission control output wiring (EMO1) and the bridge electrode (BE). For example, the bridge electrode (BE) may be arranged on the same layer as the second electrode (CE2, Fig. 7a) or the gate electrode (GE, Fig. 7a) of the main island portion (11, Fig. 4). In this case, both ends of the bridge electrode (BE) may be connected to the first light emission control output wiring (EMO1) through a contact hole.

[0254] Referring back to FIG. 13, input lines for applying signals or voltages to the driver stage may be arranged in the non-display area (NDA, FIG. 3). The input lines may include first input lines (IL1) arranged in a wiring island (WIP, FIG. 12) and second input lines (IL2) arranged in a driver island (DIP, FIG. 12). Specifically, among the input lines required for the first light-emitting control stage (EMST1), the first input lines (IL1) may be arranged in the 1-1 wiring island (WIP11), and the second input lines (IL2) may be arranged in the 1-1 driver island (DIP11). The first input lines (IL1) and the second input lines (IL2) may each extend in a second direction (e.g., the y direction). Accordingly, the first input lines (IL1) can be extended toward the first-second wiring island (WIP12) disposed at the bottom through the second-second bridge section (BP22), and the second input lines (IL2) can be extended toward the first-second driver island (DIP12) disposed at the bottom through the second-first bridge section (BP21). At this time, the first input lines (IL1) of the first-first wiring island section (WIP11), which is the frontmost one among the wiring island sections (WIP, FIG. 12), can be extended in the second direction (e.g., the y direction) to the second dummy island section (DMI2) through the third-first dummy bridge section (BP31).

[0255] In one embodiment, the first input lines (IL1) may include a gate high voltage line (VGH), a gate low voltage line (VGL), and a start signal line (FLM). The gate high voltage line (VGH) and the gate low voltage line (VGL) are lines that apply a driving voltage to the light emission control stage (EMST), wherein the gate high voltage line (VGH) may apply a gate-off voltage, and the gate low voltage line (VGL) may apply a gate-on voltage. The start signal line (FLM) may be a line that applies a start signal to the first light emission control stage (EMST1).

[0256] In one embodiment, the second input lines (IL2) may include a first clock wire (CLK1), a second clock wire (CLK2), a carry wire (CRL), and a reset signal wire (ESR). The first clock wire (CLK1) and the second clock wire (CLK2) are wires that transmit a first clock signal and a second clock signal, respectively, and each of the first clock signal and the second clock signal may be a square wave signal that repeats a logic high level and a logic low level. The carry wire (CRL) is a wire that transmits a carry signal, and the carry signal may be a start signal of the next stage. For example, each of the remaining light emission control stages (EMST, FIG. 12) other than the first light emission control stage (EMST) may receive a carry signal output from the previous stage as a start signal. The reset signal wire (ESR) is a wire that transmits a reset signal, and the reset signal may be a signal that is activated to a low level when the display device is powered on or reset.

[0257] The second input lines (IL2) may be arranged adjacent to the light emission control stage (EMST) in the 1-1 driver island section (DIP11), so that signal transmission may be facilitated. In contrast, the first input lines (IL1) are arranged in the 1-1 wiring island section (WIP11) spaced apart from the 1-1 driver island section (DIP11), so that a connection wire (CW) may be additionally required. The connection wire (CW) may include a high voltage connection wire (VGHL) connected to the gate high voltage wire (VGH) among the first input lines (IL1), and a low voltage connection wire (VGLL) connected to the gate low voltage wire (VGL).

[0258] The high voltage connection wiring (VGHL) can be connected to the gate high voltage wiring (VGH) on the 1-1 wiring island section (WIP11), and the low voltage connection wiring (VGLL) can be connected to the gate low voltage wiring (VGL). Referring to FIG. 14, the high voltage connection wiring (VGHL) and the low voltage connection wiring (VGLL) can be arranged on substantially the same layer as the first connection piece (CM1, FIG. 7a) of the main island section (11, FIG. 4). The high voltage connection wiring (VGHL) and the low voltage connection wiring (VGLL) can be connected to the gate high voltage wiring (VGH) or the gate low voltage wiring (VGL) through contact holes, respectively. This may be to maximize the width of the wiring by arranging the first emission control output wiring (EMO1) and the connection wiring (CW) arranged on the 1-1 bridge section (BP11) on different layers.

[0259] A high voltage connection wire (VGHL) may extend along a first direction (e.g., x-direction) intersecting a gate high voltage wire (VGH) on a first-first wiring island portion (WIP11). The high voltage connection wire (VGHL) may extend from the first-first wiring island portion (WIP11) to the first-first bridge portion (BP11), and the high voltage connection wire (VGHL) arranged on the first-first bridge portion (BP11) may have a meandering shape or an 'S' shape. In addition, the high voltage connection wire (VGHL) may extend from the first-first bridge portion (BP11) to the first-first driver island portion (DIP11). The high voltage connection wiring (VGHL) arranged on the 1-1 driver island section (DIP11) can be branched and electrically connected to the first electrostatic discharge prevention circuit (ESD1) and the first light emission control stage (EMST1), respectively.

[0260] Similarly, the low voltage connecting wire (VGLL) has a structure similar to that of the high voltage connecting wire (VGHL) and can extend from the 1-1 wiring island section (WIP11) to the 1-1 driver island section (DIP11) via the 1-1 bridge section (BP11). The low voltage connecting wire (VGLL) arranged on the 1-1 bridge section (BP11) can overlap with the first light emission control output wire (EMO1).

[0261] Meanwhile, among the first input lines (IL1), the start signal wiring (FLM) does not need to transmit a signal to the nth light emission control stage arranged at the rear end, but needs to transmit a signal to the first light emission control stage (EMST1) arranged at the front end. However, since the start signal wiring (FLM) is also arranged in the 1-1 wiring island section (WIP11) like the gate high voltage wiring (VGH) and the gate low voltage wiring (VGL), the start signal wiring (FLM) also needs to be extended to the 1-1 driver island section (DIP11).

[0262] Accordingly, in one embodiment, the start signal wiring (FLM) may extend from the first-first wiring island portion (WIP11) to the first-first driver island portion (DIP11) via the second dummy island portion (DMI2) and the first dummy island portion (DMI1). Specifically, the start signal wiring (FLM) may include a first portion (FLM1), a second portion (FLM2), a third portion (FLM3), a fourth portion (FLM4), a fifth portion (FLM5), a sixth portion (FLM6), and a seventh portion (FLM7).

[0263] The first portion (FLM1) of the start signal wiring (FLM) may be an area disposed in the 1-1 wiring island portion (WIP11) among the start signal wiring (FLM). The first portion (FLM1) may extend in the second direction (e.g., the y direction) on the 1-1 wiring island portion (WIP11) similarly to the gate high voltage wiring (VGH) and the gate low voltage wiring (VGL). In addition, the first portion (FLM1) may be a portion extended from the wiring island portion (WIP, FIG. 12) disposed at the rear end of the 1-1 wiring island portion (WIP11) and the 2-2 bridge portion (BP22).

[0264] The second part (FLM2) of the start signal wiring (FLM) may be an area disposed in the 3-1 dummy bridge part (DMB31) among the start signal wirings (FLM). The second part (FLM2) may have a winding shape or an 'S' shape. However, since the second part (FLM2) is disposed in the 3-1 dummy bridge part (DMB31) having the same shape as the horizontal bridge part (HBP, FIG. 12), it may have an 'S' shape that is rotated 90 degrees and laid down. That is, the second part (FLM2) may have an 'S' shape based on the second direction (e.g., the y direction).

[0265] A third portion (FLM3) of the start signal wiring (FLM) may be an area disposed in a second dummy island portion (DMI2) among the start signal wirings (FLM). The gate high voltage wiring (VGH) and the gate low voltage wiring (VGL) may extend from a lower end of the second dummy island portion (DMI2) to an upper end of the second dummy island portion (DMI2) along a second direction (e.g., a y direction). In contrast, the third portion (FLM3) of the start signal wiring (FLM) may extend along the second direction (e.g., a y direction) together with the gate high voltage wiring (VGH) and the gate low voltage wiring (VGL), and may extend along a first direction (e.g., an x ​​direction) intersecting the gate high voltage wiring (VGH) and the gate low voltage wiring (VGL). In other words, the third portion (FLM3) may be bent from a portion extending along a second direction (e.g., y direction) on the second dummy island portion (DMI2) and may extend toward the first dummy island portion (DMI1) along a first direction (e.g., x direction). At this time, the bent portion of the third portion (FLM3) may be the central portion of the second dummy island portion (DMI2).

[0266] As described above, the gate high voltage wiring (VGH), the gate low voltage wiring (VGL), and the start signal wiring (FLM) may all be arranged on substantially the same layer as the source electrode (SE, FIG. 7a) of the main island portion (11, FIG. 4). At this time, when the third portion (FLM3) is bent and extended along the first direction (e.g., the x-direction), an area in which the third portion (FLM3) overlaps with the gate high voltage wiring (VGH) and the gate low voltage wiring (VGL) may occur. Accordingly, each of the gate high voltage wiring (VGH) and the gate low voltage wiring (VGL) may be extended using bridge electrodes (BE', BE'') in an area in which the third portion (FLM3) may overlap. Referring to FIG. 14, the bridge electrodes (BE', BE'') are arranged lower than the gate high voltage wiring (VGH), the gate low voltage wiring (VGL), and the start signal wiring (FLM), and at least one insulating layer may be interposed between the start signal wiring (FLM) and the bridge electrodes (BE, BE''). For example, the bridge electrodes (BE', BE'') may be arranged on the same layer as the second electrode (CE2, FIG. 7a) or the gate electrode (GE, FIG. 7a) of the main island portion (11, FIG. 4). In this case, both ends of the bridge electrodes (BE') may be connected to the gate high voltage wiring (VGH) through contact holes, and both ends of the bridge electrodes (BE'') may be connected to the gate low voltage wiring (VGL) through contact holes.

[0267] The fourth part (FLM4) of the start signal wiring (FLM) may be an area arranged on the 1-1 dummy bridge part (DMB11) among the start signal wirings (FLM). The fourth part (FLM4) may have a meandering shape or an 'S' shape. Since the 1-1 dummy bridge part (DMB11) has the same shape as the vertical bridge part (VBP, FIG. 12), the fourth part (FLM4) may have an 'S' shape with respect to the first direction (e.g., x-direction). Since only the start signal wiring (FLM) is arranged on substantially the same layer as the source electrode (SE, FIG. 7a) on the 1-1 dummy bridge part (DMB11), the fourth part (FLM4) may have the maximum width that can be secured on the 1-1 dummy bridge part (DMB11).

[0268] The fifth portion (FLM5) of the start signal wiring may be an area disposed on the first dummy island portion (DMI1) among the start signal wirings (FLM). The fifth portion (FLM5) may extend from the 1-1 dummy bridge portion (DMB11) in a first direction (e.g., x direction) and then extend in a second intersecting direction (e.g., y direction). In other words, the fifth portion (FLM5) may be bent from a portion extending along the first direction (e.g., x direction) on the first dummy island portion (DMI1) and may extend toward the 1-1 driver island portion (DIP11) in a second direction (e.g., y direction). At this time, the bent portion of the fifth portion (FLM5) may be the center portion of the first dummy island portion (DMI1).

[0269] The sixth part (FLM6) of the start signal wiring (FLM) may be an area disposed in the second-first dummy bridge portion (DMB21) among the start signal wirings (FLM). The sixth part (FLM6) may have a winding shape or an 'S' shape. However, since the sixth part (FLM6) is disposed in the second-first dummy bridge portion (DMB21) having the same shape as the horizontal bridge portion (HBP, FIG. 12), it may have an 'S' shape that is rotated 90 degrees and laid down. That is, the sixth part (FLM6) may have an 'S' shape with respect to the second direction (e.g., the y direction).

[0270] The seventh portion (FLM7) of the start signal wiring (FLM) may be an area disposed in the 1-1 driver island portion (DIP11) among the start signal wiring (FLM). The seventh portion (FLM7) may include a portion extending from the 2-1 dummy bridge portion (DMB21) and connected to the first electrostatic discharge prevention circuit (ESD1), and a portion extending from the first electrostatic discharge prevention circuit (ESD1) and connected to the first light emission control stage (EMST1). In other words, the seventh portion (FLM7) may be electrically connected to the first electrostatic discharge prevention circuit (ESD1) and the first light emission control stage (EMST1) disposed in the 1-1 driver island portion (DIP11).

[0271] The first part (FLM1), the second part (FLM2), the third part (FLM3), the fourth part (FLM4), the fifth part (FLM5), the sixth part (FLM6), and the seventh part (FLM7) may all be formed integrally. In addition, the first part (FLM1), the second part (FLM2), the third part (FLM3), the fourth part (FLM4), the fifth part (FLM5), the sixth part (FLM6), and the seventh part (FLM7) may be arranged on substantially the same layer as the source electrode (SE, FIG. 7a) of the main island portion (11, FIG. 4).

[0272] Through the above structure, the start signal wiring (FLM) can be electrically connected from the 1-1 wiring island section (WIP11) to the 2nd dummy island section (DMI2) and the 1st dummy island section (DMI1), and to the 1st electrostatic discharge prevention circuit (ESD1) and the 1st light emission control stage (EMST1) arranged in the 1-1 driver island section (DIP11) to transmit a signal.

[0273] In addition, the structure as described above is not limited to the start signal wiring (FLM), the first electrostatic discharge prevention circuit (ESD1), and the first light emission control stage (EMST1) arranged in the 1-1 driver island section (DIP11) and the 1-1 wiring island section (WIP11). Referring to Fig. 12, the structure of the start signal wiring (FLM) as described above can be equally applied to the start signal wiring connected to the second electrostatic discharge prevention circuit (ESD2) and the first bypass stage (GBST1), the start signal wiring connected to the third electrostatic discharge prevention circuit (ESD3) and the first initialization stage (GIST1), and the start signal wiring connected to the fourth electrostatic discharge prevention circuit (ESD4) and the first data writing stage (GWST1).

[0274] That is, the start signal wiring connected to the second electrostatic discharge prevention circuit (ESD2) and the first bypass stage (GBST1) can be extended from the second-first wiring island (WIP21) through the fourth dummy island (DMI4) and the third dummy island (DMI3) to the second-first driver island (DIP21). Similarly, the start signal wiring connected to the third electrostatic discharge prevention circuit (ESD3) and the first initialization stage (GIST1) can be extended from the third-first wiring island (WIP31) through the sixth dummy island (DMI6) and the fifth dummy island (DMI5) to the third-first driver island (DIP31). The start signal wiring connected to the 4th electrostatic discharge prevention circuit (ESD4) and the 1st data write stage (GWST1) can be extended from the 4-1 wiring island (WIP41) through the 8th dummy island (DMI8) and the 7th dummy island (DMI7) to the 4-1 driver island (DIP41).

[0275] A display device according to one embodiment of the present invention can secure flexibility through the structure of the start signal wiring (FLM) and the arrangement of the electrostatic discharge prevention circuit (ESD, FIG. 12) as described above, while efficiently utilizing the space of the non-display area (NDA, FIG. 3).

[0276] In particular, a start signal wiring (FLM) may be extended from a wiring island (WIP, Fig. 12) disposed on the right side of each of an emission control driving circuit (EMDC, Fig. 10), a bypass driving circuit (GBDC, Fig. 10), an initialization driving circuit (GIDC, Fig. 10), and a data write driving circuit (GWDC, Fig. 10) and electrically connected to an electrostatic discharge protection circuit (ESD, Fig. 12) and a front-end driver stage. This structure of the start signal wiring (FLM) can reduce the load of the start signal wiring (FLM) compared to a case where the start signal wiring (FLM) extends from the outermost part of the display device and branches off to each front-end driver.

[0277] In addition, when the start signal wire (FLM) extends through the dummy island part (DMI, FIG. 12), since the start signal wire (FLM) does not overlap with or is arranged adjacent to the high voltage connection wire (VGHL) and the low voltage connection wire (VGLL), noise or unnecessary signal overlap caused by the high voltage connection wire (VGHL) and the low voltage connection wire (VGLL) can be prevented. Accordingly, the display device according to an embodiment of the present invention can implement a better quality image.

[0278] Fig. 15 is a schematic enlarged plan view of a portion of a display device according to another embodiment of the present invention, and is an enlarged view of portion C of Fig. 12. Fig. 16 is a cross-sectional view showing a portion of a display device according to another embodiment of the present invention, and corresponds to a cross-section taken along line Ⅲ-Ⅲ' of Fig. 15. Referring to Figs. 15 and 16, except for the features of the start signal line (FLM) and the connection line (CW), other features are the same as those described in Figs. 13 and 14. The same reference numerals among the components of Figs. 15 and 16 replace those described in Figs. 13 and 14, and the following description focuses on the differences.

[0279] First, referring to FIG. 15, the first input lines (IL1) may include a gate high voltage line (VGH), a gate low voltage line (VGL), and a start signal line (FLM), and the second input lines (IL2) may include a first clock line (CLK1), a second clock line (CLK2), a carry line (CRL), and a reset signal line (ESR). The second input lines (IL2) may be arranged adjacent to the light emission control stage (EMST) in the 1-1 driver island section (DIP11), so that signals may be easily transmitted. In contrast, the first input lines (IL1) are arranged in the 1-1 wiring island section (WIP21) spaced apart from the 1-1 driver island section (DIP11), so that a connection line (CW) may be additionally required. The connection wiring (CW) may include a high voltage connection wiring (VGHL) connected to the gate high voltage wiring (VGH) among the first input lines (IL1), a low voltage connection wiring (VGLL) connected to the gate low voltage wiring (VGL), and a start signal connection wiring (FLML) connected to the start signal wiring (FLM).

[0280] The high voltage connection wiring (VGHL) can be connected to the gate high voltage wiring (VGH) on the first-first wiring island section (WIP11), and the low voltage connection wiring (VGLL) can be connected to the gate low voltage wiring (VGL). Referring to FIG. 16, the high voltage connection wiring (VGHL) and the low voltage connection wiring (VGLL) can be arranged on substantially the same layer as the first connection piece (CM1, FIG. 7a) of the main island section (11, FIG. 4). The high voltage connection wiring (VGHL) and the low voltage connection wiring (VGLL) can be connected to the gate high voltage wiring (VGH) or the gate low voltage wiring (VGL), respectively, through contact holes.

[0281] Each of the high voltage connection wiring (VGHL) and the low voltage connection wiring (VGLL) may have an 'S' shape as they extend from the 1-1 wiring island section (WIP11) and are arranged on the 1-1 bridge section (BP11). In addition, each of the high voltage connection wiring (VGHL) and the low voltage connection wiring (VGLL) may extend from the 1-1 bridge section (BP11) and be arranged on the 1-1 driver island section (DIP11). Each of the high voltage connection wiring (VGHL) and the low voltage connection wiring (VGLL) arranged on the 1-1 driver island section (DIP11) may branch and be electrically connected to the first electrostatic discharge prevention circuit (ESD1) and the first light emission control stage (EMST1), respectively.

[0282] Similar to the high voltage link wire (VGHL) and the low voltage link wire (VGLL), the start signal link wire (FLML) may extend from the 1-1 wiring island section (WIP11) to the 1-1 driver island section (DIP11) via the 1-1 bridge section (BP11). Specifically, the start signal link wire (FLML) may include a first section (FLML1) and a second section (FLML2).

[0283] The first part (FLML1) of the start signal connection wiring (FLML) may be an area disposed in the first-first wiring island portion (WIP11) of the start signal connection wiring (FLML). In particular, the first part (FLML1) may be a area directly connected to the start signal wiring (FLM) through a contact hole. The first part (FLML1) may be a area extending along a first direction (e.g., the x-direction) intersecting the start signal wiring (FLM). Accordingly, an area may be generated in the first part (FLML1) that overlaps the gate high voltage wiring (VGH) and the gate low voltage wiring (VGL). In order to prevent interference between the gate high voltage wiring (VGH) and the gate low voltage wiring (VGL) and the first part (FLML1), the first part (FLML1) may be disposed on a different layer from the plurality of first input lines (IL1).

[0284] Referring to FIG. 16, the start signal wiring (FLM), the gate high voltage wiring (VGH), and the gate low voltage wiring (VGL) may be arranged on substantially the same layer as the source electrode (SE, FIG. 7a) of the main island portion (11, FIG. 4). Meanwhile, the first portion (FLML1) may be arranged on substantially the same layer as the first connecting piece (CM1, FIG. 7a) of the main island portion (11, FIG. 4), and may be electrically connected to the start signal wiring (FLM) through a contact hole.

[0285] The second part (FLML2) of the start signal connection wiring (FLML) may be the remaining area excluding the first part (FLML1) of the start signal connection wiring (FLML). Accordingly, the second part (FLML2) may be disposed on the 1-1 wiring island part (WIP11), the 1-1 bridge part (BP11), and the 1-1 driver island part (DIP11). At this time, the second part (FLML2) may be disposed on a different layer from the first part (FLML1), and may be disposed on substantially the same layer as the start signal wiring (FLM). That is, referring to FIG. 16, the second part (FLML2) may be disposed on substantially the same layer as the source electrode (SE, FIG. 7a) of the main island part (11, FIG. 4), and may be electrically connected to the first part (FLML1) through a contact hole. The second part (FLML2) is connected to the first part (FLML1) through a contact hole on the first-first wiring island part (WIP11) and can extend toward the first-first bridge part (BP11) along the first direction (e.g., the x-direction).

[0286] The second part (FLML2) arranged on the 1-1 bridge portion (BP11) may have a winding shape or an 'S' shape. Since the second part (FLML2) is arranged on substantially the same layer as the source electrode (SE, FIG. 7a), it may be arranged on substantially the same layer as the first light emission control output wiring (EMO1) on the 1-1 bridge portion (BP11). Accordingly, since two wirings are arranged on substantially the same layer as the source electrode (SE, FIG. 7a) on the 1-1 bridge portion (BP11), the start signal connection wiring (FLML) and the first light emission control output wiring (EMO1) can divide the area and have the maximum width that can be secured respectively.

[0287] Meanwhile, a high-voltage connection wire (VGHL) and a low-voltage connection wire (VGLL) may be arranged on the 1-1 bridge section (BP11), but the high-voltage connection wire (VGHL) and the low-voltage connection wire (VGLL) may be arranged on different layers from the first light emission control output wire (EMO1) and the second part (FLML2). Accordingly, the second part (FLML2) may overlap the high-voltage connection wire (VGHL), and the first light emission control output wire (EMO1) may overlap the low-voltage connection wire (VGLL).

[0288] The second part (FLML2) may be extended from the 1-1 bridge part (BP11) and placed on the 1-1 driver island part (DIP11). The second part (FLML2) placed on the 1-1 driver island part (DIP11) may be branched and connected to the first electrostatic discharge prevention circuit (ESD1) and the first light emission control stage (EMST1), respectively.

[0289] Through the structure of the above-described start signal connection wiring (FLML), the signal of the start signal wiring (FLM) arranged in the 1-1 wiring island section (WIP11) can be transmitted to the first electrostatic discharge prevention circuit (ESD1) and the first light emission control stage (EMST1) arranged in the 1-1 driver island section (DIP11).

[0290] In addition, the structure of the above-described start signal connection wiring (FLML) is not limited to the start signal wiring (FLM), the first electrostatic discharge prevention circuit (ESD1), and the first light emission control stage (EMST1) arranged in the 1-1 driver island section (DIP11) and the 1-1 wiring island section (WIP11). That is, the wiring start signal wiring (FLM) arranged in the 2-1 wiring island section (WIP21, Fig. 12) can also transmit a signal to the second electrostatic discharge prevention circuit (ESD2, Fig. 12) and the first bypass stage (GBST1, Fig. 12) arranged in the 2-1 driver island section (DIP21, Fig. 12) through the start signal connection wiring (FLML). Likewise, the wiring start signal wiring (FLM) arranged in the 3-1 wiring island section (WIP31, FIG. 12) can also transmit a signal to the third electrostatic discharge prevention circuit (ESD3, FIG. 12) and the first initialization stage (GIST1, FIG. 12) arranged in the 3-1 driver island section (DIP31, FIG. 12) via the start signal connection wiring (FLML). The wiring start signal wiring (FLM) arranged in the 4-1 wiring island section (WIP41, FIG. 12) can also transmit a signal to the fourth electrostatic discharge prevention circuit (ESD4, FIG. 12) and the first data writing stage (GWST1, FIG. 12) arranged in the 4-1 driver island section (DIP41, FIG. 12) via the start signal connection wiring (FLML).

[0291] A display device according to another embodiment of the present invention can secure flexibility through the structure of the start signal connection wiring (FLML) and the arrangement of the electrostatic discharge prevention circuit (ESD, FIG. 12), while efficiently utilizing the space of the non-display area (NDA, FIG. 3).

[0292] In particular, a start signal wiring (FLM) may be extended from a wiring island (WIP, Fig. 12) disposed on the right side of each of an emission control driving circuit (EMDC, Fig. 10), a bypass driving circuit (GBDC, Fig. 10), an initialization driving circuit (GIDC, Fig. 10), and a data write driving circuit (GWDC, Fig. 10) and electrically connected to an electrostatic discharge protection circuit (ESD, Fig. 12) and a front-end driver stage. This structure of the start signal wiring (FLM) can reduce the load of the start signal wiring (FLM) compared to a case where the start signal wiring (FLM) extends from the outermost part of the display device and branches off to each front-end driver.

[0293] In addition, when using the start signal connection wiring (FLML), the wiring for transmitting the signal of the start signal wiring (FLM) can be directly connected from the 1-1 wiring island section (WIP11) to the 1-1 driver island section (DIP11) via the 1-1 bridge section (BP11). In other words, since the wiring for transmitting the signal of the start signal wiring (FLM) uses a minimum length, the load for transmitting the signal of the start signal wiring (FLM) can be further reduced. Accordingly, the display device according to another embodiment of the present invention can significantly reduce the load of the wiring, thereby implementing an image of better quality.

[0294] While the present invention has been described with reference to the embodiments illustrated in the drawings, these are merely exemplary, and those skilled in the art will appreciate that various modifications and variations of the embodiments are possible. Therefore, the true scope of technical protection of the present invention should be determined by the technical spirit of the appended claims.

Claims

1. A substrate including a driver island portion, a wiring island portion spaced apart from the driver island portion along a first direction, and a bridge portion extending toward the driver island portion and the wiring island portion; A gate driving circuit arranged in the above driver island section; An anti-static circuit arranged in the above driver island section; and A plurality of first input lines are arranged in the above wiring island section and extend along a second direction intersecting the first direction; The above plurality of first input lines include initiation signal wiring, A display device, wherein the above-mentioned start signal wiring is electrically connected to the above-mentioned static electricity prevention circuit.

2. In paragraph 1, The above driver island section and the above wiring island section are arranged alternately along the first direction, A display device, wherein the driver island section and the wiring island section are each arranged continuously along the second direction.

3. In paragraph 2, The above driver island section is provided in multiples, The plurality of driver islands includes a first driver island, The above anti-static circuit, A display device, arranged in a first driver island section that is arranged at the frontmost end with respect to the second direction among driver island sections that are arranged sequentially along the second direction.

4. In paragraph 3, The above gate driving circuit comprises a plurality of stages, A display device in which the first stage, which is positioned at the front end of the plurality of stages, is positioned in the first driver island section.

5. In paragraph 4, A display device, wherein the above-described initiation signal wiring is electrically connected to the first stage.

6. In paragraph 1, The above gate driving circuit, A display device comprising at least one of a light-emitting control driving circuit, a bypass driving circuit, an initialization driving circuit, and a data writing driving circuit.

7. In paragraph 1, The above plurality of first input lines are, A display device further comprising a gate high voltage wiring and a gate low voltage wiring.

8. In paragraph 7, A high voltage connection wiring arranged in the above bridge section and connected to the gate high voltage wiring; and It further includes a low voltage connection wiring arranged in the above bridge section and connected to the gate low voltage wiring; The above high voltage connection wiring is connected to the above static electricity prevention circuit and the above gate driving circuit, respectively. A display device in which the above low-voltage connection wiring is respectively connected to the above static electricity prevention circuit and the above gate driving circuit.

9. In paragraph 7, Further comprising a plurality of second input lines arranged in the driver island section; A display device, wherein the plurality of second input lines include at least one of a clock wiring, a carry wiring, and a reset signal wiring.

10. In paragraph 7, Based on the above second direction, A first dummy island section arranged at the front end of the above driver island section; and A display device further comprising a second dummy island section arranged at a front end of the above wiring island section.

11. In clause 10, A display device, wherein the gate high voltage wiring and the gate low voltage wiring extend along the second direction on the wiring island portion and the second dummy island portion.

12. In paragraph 10, A display device, wherein the above-described start signal wiring extends from the above-described wiring island section through the above-described second dummy island section and the above-described first dummy island section to the above-described driver island section.

13. In paragraph 12, The above initiation signal wiring arranged on the above second dummy island section is, From a portion extended along the second direction, it is bent and extended toward the first dummy island portion along the first direction, The above initiation signal wiring arranged on the above first dummy island section, A display device, which is bent from a portion extending along the first direction and extending toward the driver island portion along the second direction.

14. In paragraph 12, A first dummy bridge portion connecting the first dummy island portion and the second dummy island portion; A second dummy bridge section connecting the driver island section and the first dummy island section; and A display device further comprising a third dummy bridge portion connecting the wiring island portion and the second dummy island portion.

15. In paragraph 14, A display device, wherein the above bridge portion, the first dummy bridge portion, the second dummy bridge portion, and the third dummy bridge portion have a serpentine shape.

16. In paragraph 14, A display device, wherein the above-described initiation signal wiring is arranged on the first dummy bridge section, the second dummy bridge section, and the third dummy bridge section.

17. In paragraph 12, A first bridge electrode arranged on the second dummy island portion and having a gate high voltage wiring connected to both ends; and Further comprising a second bridge electrode arranged on the second dummy island portion and having gate low voltage wiring connected to both ends; A display device, wherein the first bridge electrode and the second bridge electrode intersect the initiation signal wiring, but are arranged on a different layer from the initiation signal wiring.

18. In paragraph 7, Further comprising: a start signal connection wiring electrically connecting the above start signal wiring and the above anti-static circuit; A display device in which the above-mentioned initiation signal connection wiring extends through the above-mentioned bridge section.

19. The above-mentioned start signal connection wiring is: A first portion arranged on the above wiring island portion and intersecting the gate high voltage wiring and the gate low voltage wiring; and A display device, comprising a second part disposed on the bridge portion.

20. In paragraph 19, The above-mentioned initiation signal wiring and the above-mentioned first part are arranged on different layers, A display device, wherein the above-mentioned start signal wiring and the second portion are arranged on substantially the same layer.

21. In paragraph 20, The above-mentioned initiation signal wiring and the above-mentioned first portion are electrically connected through the first contact hole, A display device, wherein the first part and the second part are electrically connected through a second contact hole.

22. In paragraph 18, It further includes an output wiring arranged in the above bridge section and connected to the gate driving circuit; A display device, wherein the above output wiring and the above start signal connection wiring are arranged on substantially the same layer on the bridge section.

Images