Display substrate, display panel, and display device

Abstract

Provided are a display substrate, a display panel, and a display device. The display substrate comprises a plurality of sub-pixels and a plurality of signal lines located on a substrate, wherein the plurality of sub-pixels are arranged in an array in a first direction and a second direction, and at least one sub-pixel comprises a light-emitting device and a pixel drive circuit; and the plurality of signal lines comprise a first power supply signal line. The display substrate further comprises: a light-shielding layer, a first semiconductor layer, and a first conductive layer which are away from the substrate in sequence. The pixel drive circuit comprises a third transistor comprising a third active layer located in the first semiconductor layer and a third gate located in the first conductive layer, wherein the third active layer comprises a third channel region, and the orthographic projections of the third gate and the third channel region on the substrate at least partially overlap with each other. The first power supply signal line comprises a first sub-power supply signal line located in the light-shielding layer, and the orthographic projection of the first sub-power supply signal line on the substrate covers the orthographic projection of the third channel region on the substrate.

Description

Display substrate, display panel and display device TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, and particularly relates to a display substrate, a display panel and a display device. BACKGROUND

[0002] With the development of display technology, display products show a development trend of high integration and low cost. At present, LTPO (Low Temperature Poly-Oxide) pixel driving circuit is commonly used in OLED display products, and the low leakage property of indium gallium zinc oxide IGZO (Indium Gallium Zinc Oxide) TFT in the LTPO pixel driving circuit can realize low-frequency display of the display product and reduce power consumption. However, compared with the traditional LTPS (Low Temperature Poly-Silicon) pixel driving circuit, the LTPO pixel driving circuit needs to increase a plurality of plating film layers, and the increase of the plating film layers needs to correspondingly increase a plurality of metal mask plates, which leads to the increase of the cost of the display product, and with the size reduction of the display product, the pixel driving circuit wiring space of the high-pixel display product becomes smaller, and the increase of the number of film layers in the preparation process of the pixel driving circuit will also lead to the reduction of the yield of the display product.

[0003] How to optimize the layout space of the pixel driving circuit of the display product to improve the yield of the display product and reduce unnecessary film layers to save the cost of the metal mask plate is one of the important research topics of the researchers.

[0004] The above information disclosed in this section is only for understanding the background of the inventive concept of the present disclosure, and therefore, the above information can contain information that does not constitute the prior art.

[0005] SUMMARY

[0006] In one aspect, a display substrate is provided, wherein the display substrate comprises: a substrate; a plurality of sub-pixels on the substrate, the plurality of sub-pixels are arranged in an array along a first direction and a second direction on the substrate, at least one sub-pixel comprises a light emitting device and a pixel driving circuit for driving the light emitting device to emit light, the first direction and the second direction are perpendicular to each other; a plurality of signal lines on the substrate, the plurality of signal lines comprises a first power signal line, the first power signal line is configured to provide a first power signal to the pixel driving circuit, wherein the display substrate further comprises: a light shielding layer on the substrate; a first semiconductor layer on a side of the light shielding layer away from the substrate; and a first conductive layer on a side of the first semiconductor layer away from the substrate; the pixel driving circuit comprises a third transistor, the third transistor comprises a third active layer and a third gate, the third active layer is in the first semiconductor layer, the third gate is in the first conductive layer, the third active layer comprises a third channel region, a projection of the third gate on the substrate at least partially overlaps a projection of the third channel region on the substrate; and the first power signal line comprises a first sub-power signal line in the light shielding layer, a projection of the first sub-power signal line on the substrate covers the projection of the third channel region on the substrate.

[0007] According to some exemplary embodiments, the first power signal line further comprises a second sub-power signal line in the light shielding layer, a main body portion of the first sub-power signal line extends along the first direction, and the second sub-power signal line extends along the second direction.

[0008] According to some exemplary embodiments, the display substrate comprises m first sub-power signal lines and n second sub-power signal lines in the light shielding layer, each of the m first sub-power signal lines intersects with each of the n second sub-power signal lines, so that a portion of the first power signal line in the light shielding layer has a grid-like structure.

[0009] According to some exemplary embodiments, the display substrate further comprises: a second conductive layer on a side of the first conductive layer away from the substrate; a planarization layer on a side of the second conductive layer away from the substrate; and a first electrode layer on a side of the planarization layer away from the substrate; the light emitting element further comprises a first electrode in the first electrode layer; the planarization layer comprises a first surface facing the second conductive layer and a second surface facing the first electrode layer, the first surface contacts at least a portion of the second conductive layer, and the second surface contacts at least a portion of the first electrode layer.

[0010] For example, the third transistor further includes a third source and a third drain, and the third source and the third drain are located in the second conductive layer.

[0011] According to some exemplary embodiments, the pixel driving circuit further includes a storage capacitor, the storage capacitor includes a first capacitor plate and a second capacitor plate; the part of the first capacitor plate overlapping with the third active layer is the third gate; and the part of the first power signal line located in the light shielding layer is electrically connected with the second capacitor plate. For example, the part of the first power signal line located in the light shielding layer is electrically connected with the second capacitor plate within the display area.

[0012] According to some exemplary embodiments, the display substrate further includes: a second conductive layer located on the side of the first conductive layer away from the substrate; the third transistor further includes a third source and a third drain, and the third source and the third drain are located in the second conductive layer; and the first power signal line further includes a third sub-power signal line located in the second conductive layer.

[0013] According to some exemplary embodiments, the orthographic projection of the third sub-power signal line on the substrate at least partially overlaps with the orthographic projection of the second sub-power signal line on the substrate.

[0014] According to some exemplary embodiments, the display substrate includes k third sub-power signal lines located in the second conductive layer; and the number n of the second sub-power signal lines is more than twice the number k of the third sub-power signal lines.

[0015] According to some exemplary embodiments, the third sub-power signal line is electrically connected with the second sub-power signal line through a first via.

[0016] According to some exemplary embodiments, the display substrate further includes: a second conductive layer located on the side of the first conductive layer away from the substrate; the third transistor further includes a third source and a third drain, and the third source and the third drain are located in the second conductive layer; and the first power signal line further includes a first conductive adapter located in the second conductive layer, and the first conductive adapter is electrically connected with the second sub-power signal line through a first via.

[0017] According to some exemplary embodiments, the orthographic projection of the first conductive adapter on the substrate at least partially overlaps with the orthographic projection of the second sub-power signal line on the substrate.

[0018] According to some exemplary embodiments, the display substrate further includes a second semiconductor layer located at a side of the first semiconductor layer distal to the base substrate; the pixel driving circuit further includes a second transistor, the second transistor including a second active layer, the second active layer being located in the second semiconductor layer; the first semiconductor layer includes a single-crystal silicon, amorphous silicon or polycrystalline silicon semiconductor material, and the second semiconductor layer includes an oxide semiconductor material.

[0019] According to some exemplary embodiments, the second transistor includes a second gate electrode, the second gate electrode including a first sub-gate electrode and a second sub-gate electrode, a layer where the first sub-gate electrode is located being at a side of the second semiconductor layer proximal to the base substrate, a layer where the second sub-gate electrode is located being at a side of the second semiconductor layer distal to the base substrate, a projection of the first sub-gate electrode on the base substrate at least partially overlapping a projection of the second active layer on the base substrate, and a projection of the second sub-gate electrode on the base substrate at least partially overlapping the projection of the second active layer on the base substrate.

[0020] According to some exemplary embodiments, the display substrate further includes a third conductive layer located between the first semiconductor layer and the second semiconductor layer, and a fourth conductive layer located at a side of the second semiconductor layer distal to the base substrate; the first sub-gate electrode is located in the third conductive layer, and the second sub-gate electrode is located in the fourth conductive layer.

[0021] According to some exemplary embodiments, the display substrate further includes a third conductive layer located at a side of the second semiconductor layer distal to the base substrate; the first sub-gate electrode is located in the first conductive layer, and the second sub-gate electrode is located in the third conductive layer.

[0022] According to some exemplary embodiments, the display substrate further includes a fourth conductive layer located at a side of the second semiconductor layer distal to the base substrate; the first sub-gate electrode is located in the first conductive layer, and the second sub-gate electrode is located in the fourth conductive layer.

[0023] According to some exemplary embodiments, at least a portion of the first capacitor plate is located in the first conductive layer, and at least a portion of the second capacitor plate is located in the third conductive layer.

[0024] According to some exemplary embodiments, at least a portion of the first capacitor plate is located in the first conductive layer, and at least a portion of the second capacitor plate is located in the fourth conductive layer.

[0025] According to some exemplary embodiments, a portion of the third sub power signal line is electrically connected with the second sub power signal line through a first via, and another portion of the third sub power signal line is electrically connected with at least a portion of the second capacitor plate through a second via.

[0026] According to some exemplary embodiments, a portion of the first conductive adapter is electrically connected with the second sub power signal line through a first via, and another portion of the first conductive adapter is electrically connected with at least a portion of the second capacitor plate through a second via.

[0027] According to some exemplary embodiments, the first conductive layer is located at a side of the second semiconductor layer away from the substrate; the second transistor and the third transistor both have a top gate structure; the second transistor includes a second gate, the second gate and the third gate are both located in the first conductive layer, a projection of the second gate on the substrate at least partially overlaps a projection of the second active layer on the substrate, and a projection of the third gate on the substrate at least partially overlaps a projection of the third active layer on the substrate.

[0028] According to some exemplary embodiments, the display substrate further includes: a second conductive layer located at a side of the first conductive layer away from the substrate; at least a portion of the first capacitor plate is located in the first conductive layer, and at least a portion of the second capacitor plate is located in the second conductive layer.

[0029] According to some exemplary embodiments, the third sub power signal line and at least a portion of the second capacitor plate, both of which are located in the second conductive layer, are connected, and the third sub power signal line is electrically connected with the second sub power signal line through a first via.

[0030] According to some exemplary embodiments, the second capacitor plate includes a first sub capacitor plate and a second sub capacitor plate, the first sub capacitor plate is located in the second conductive layer, and the second sub capacitor plate is located in the light shielding layer; a projection of each of the first sub capacitor plate and the second sub capacitor plate on the substrate at least partially overlaps a projection of the first capacitor plate on the substrate.

[0031] According to some exemplary embodiments, the material of the light shielding layer has a resistivity lower than that of the material of the second conductive layer.

[0032] According to some exemplary embodiments, the material of the light shielding layer includes copper or aluminum.

[0033] According to some exemplary embodiments, in the light shielding layer, a first portion of the first power signal line providing pixel driving circuits of jth column of sub-pixels and a second portion of the first power signal line providing pixel driving circuits of (j+1)th column of sub-pixels are symmetrical with respect to a first imaginary straight line, wherein the first imaginary straight line is a straight line extending along the second direction.

[0034] According to some exemplary embodiments, the plurality of signal lines further include a first initialization signal line, a second initialization signal line, a reset signal line, a first scan signal line, a second scan signal line, a third scan signal line, a light emitting control signal line and a data signal line, the first initialization signal line, the second initialization signal line, the reset signal line, the first scan signal line, the second scan signal line, the third scan signal line and the light emitting control signal line extend along the first direction, and the data signal line extends along the second direction.

[0035] According to some exemplary embodiments, the pixel driving circuit further includes a first transistor, a fourth transistor, a fifth transistor, a sixth transistor and a seventh transistor; the first transistor includes a first gate, a first source and a first drain, one of the first source and the first drain is electrically connected to the first initialization signal line, and the first gate is electrically connected to the reset signal line; the second gate is electrically connected to the third scan signal line; the fourth transistor includes a fourth gate, a fourth source and a fourth drain, one of the fourth source and the fourth drain is electrically connected to the data signal line, and the fourth gate is electrically connected to the first scan signal line; the fifth transistor includes a fifth gate, a fifth source and a fifth drain, one of the fifth source and the fifth drain is electrically connected to the first power signal line, and the fifth gate is electrically connected to the light emitting control signal line; the sixth transistor includes a sixth gate, a sixth source and a sixth drain, and the sixth gate is electrically connected to the light emitting control signal line; the seventh transistor includes a seventh gate, a seventh source and a seventh drain, the seventh gate is electrically connected to the second scan signal line, and one of the seventh source and the seventh drain is electrically connected to the second initialization signal line; and one of the second source and the second drain, the third gate and the first capacitor plate are electrically connected to each other, one of the third source and the third drain, the other of the fourth source and the fourth drain, and the other of the fifth source and the fifth drain are electrically connected to each other, the other of the first source and the first drain, the other of the second source and the second drain, the other of the third source and the third drain, and one of the sixth source and the sixth drain are electrically connected to each other, and the other of the sixth source and the sixth drain and the other of the seventh source and the seventh drain are electrically connected to each other.

[0036] According to some exemplary embodiments, the reset signal line, the first scan signal line, the second scan signal line, the light-emitting control signal line and the second initialization signal line are located in the first conductive layer; and the first initialization signal line is located in the third conductive layer.

[0037] According to some exemplary embodiments, the reset signal line, the first scan signal line, the second scan signal line, the light-emitting control signal line and the second initialization signal line are located in the first conductive layer; and the first initialization signal line is located in the fourth conductive layer.

[0038] According to some exemplary embodiments, the first initialization signal line, the reset signal line, the first scan signal line, the second scan signal line, the third scan signal line, the light-emitting control signal line and the second initialization signal line are all located in the first conductive layer.

[0039] In another aspect, a display substrate is provided, including: a substrate; a plurality of sub-pixels on the substrate, the plurality of sub-pixels being arranged in an array along a first direction and a second direction on the substrate, at least one sub-pixel including a light-emitting device and a pixel driving circuit for driving the light-emitting device to emit light, the first direction and the second direction being perpendicular to each other; a plurality of signal lines on the substrate, the plurality of signal lines including a first power signal line for providing a first power signal to the pixel driving circuit, wherein the display substrate further includes: a light-shielding layer on the substrate; a first semiconductor layer on a side of the light-shielding layer away from the substrate; and a first conductive layer on a side of the first semiconductor layer away from the substrate; the first power signal line further including a first sub-power signal line and a second sub-power signal line in the light-shielding layer, a main part of the first sub-power signal line extending along the first direction, the second sub-power signal line extending along the second direction, the first sub-power signal line and the second sub-power signal line being electrically connected to each other for transmitting the first power signal.

[0040] In yet another aspect, a display substrate is provided, wherein the display substrate comprises: a substrate; and a plurality of sub-pixels on the substrate, the plurality of sub-pixels are arranged in an array along a first direction and a second direction on the substrate, at least one sub-pixel comprises a light emitting device and a pixel driving circuit for driving the light emitting device to emit light, the first direction and the second direction are perpendicular to each other; wherein the display substrate further comprises: a first semiconductor layer on the substrate; a first conductive layer on a side of the first semiconductor layer away from the substrate; a second semiconductor layer on a side of the first conductive layer away from the substrate; and a third conductive layer on a side of the second semiconductor layer away from the substrate; the pixel driving circuit comprises a second transistor and a third transistor, the second transistor and the third transistor both have a top-gate structure; the third transistor comprises a third active layer and a third gate, the third active layer is in the first semiconductor layer, the third gate is in the first conductive layer, the third active layer comprises a third channel region, a projection of the third gate on the substrate at least partially overlaps with a projection of the third channel region on the substrate; and the second transistor comprises a second active layer and a second gate, the second active layer is in the second semiconductor layer, the second gate is in the third conductive layer, the second active layer comprises a second channel region, a projection of the second gate on the substrate at least partially overlaps with a projection of the second channel region on the substrate.

[0041] According to some exemplary embodiments, the display substrate further comprises a light shielding layer on a side of the first semiconductor layer close to the substrate; and the display substrate comprises a first light shielding portion and a second light shielding portion in the light shielding layer, a projection of the first light shielding portion on the substrate at least partially overlaps with a projection of the third channel region on the substrate, a projection of the second light shielding portion on the substrate at least partially overlaps with a projection of the second channel region on the substrate.

[0042] According to some exemplary embodiments, the first light shielding portion comprises a first light shielding sub-portion extending along the first direction and a second light shielding sub-portion extending along the second direction, the first light shielding sub-portion and the second light shielding sub-portion are connected such that the first light shielding portion forms an L-shaped structure; and / or, the second light shielding portion extends from a part of the first light shielding sub-portion along the second direction.

[0043] In yet another aspect, a display substrate is provided, wherein the display substrate comprises: a substrate; and a plurality of sub-pixels on the substrate, the plurality of sub-pixels are arranged in an array along a first direction and a second direction on the substrate, at least one sub-pixel comprises a light emitting device and a pixel driving circuit for driving the light emitting device to emit light, the first direction and the second direction are perpendicular to each other; wherein the display substrate further comprises: a first semiconductor layer on the substrate; a first conductive layer on a side of the first semiconductor layer away from the substrate; a second semiconductor layer on a side of the first conductive layer away from the substrate; a third conductive layer on a side of the second semiconductor layer away from the substrate; and a fourth conductive layer on a side of the third conductive layer away from the substrate; the pixel driving circuit comprises a second transistor and a third transistor, the second transistor has a double-gate structure, and the third transistor has a top-gate structure; the third transistor comprises a third active layer and a third gate, the third active layer is in the first semiconductor layer, the third gate is in the first conductive layer, the third active layer comprises a third channel region, and a projection of the third gate on the substrate at least partially overlaps a projection of the third channel region on the substrate; and the second transistor comprises a second active layer and a second gate, the second gate comprises a first sub-gate and a second sub-gate, the first sub-gate is in the first conductive layer, the second sub-gate is in the third conductive layer or the fourth conductive layer, a projection of the first sub-gate on the substrate at least partially overlaps a projection of the second active layer on the substrate, and a projection of the second sub-gate on the substrate at least partially overlaps the projection of the second active layer on the substrate.

[0044] In still another aspect, a display panel is provided, comprising the display substrate as in any one of the above.

[0045] In yet another aspect, a display device is provided, comprising the display substrate as in any one of the above or the display panel as described above. BRIEF DESCRIPTION OF DRAWINGS

[0046] The features and advantages of the present disclosure will become more apparent from the detailed description of example embodiments thereof in conjunction with the accompanying drawings.

[0047] FIG. 1 is a plan view of a display substrate according to some embodiments of the present disclosure;

[0048] FIG. 2 is a structural schematic view of a sub-pixel according to some embodiments of the present disclosure;

[0049] FIG. 3 is a structural block diagram of a pixel circuit according to some embodiments of the present disclosure;

[0050] FIG. 4 is an equivalent circuit diagram of a pixel circuit according to some embodiments of the present disclosure;

[0051] FIG. 5 is a plan view of a pixel driving circuit of a plurality of sub-pixels in a display substrate according to some embodiments of the present disclosure;

[0052] FIG. 6 is a plan view of a light shielding layer in the pixel driving circuit according to FIG. 5;

[0053] FIG. 7 is a plan view of a first semiconductor layer in the pixel driving circuit according to FIG. 5;

[0054] FIG. 8 is a plan view of a combined film layer of the light shielding layer and the first semiconductor layer in the pixel driving circuit according to FIG. 5;

[0055] FIG. 9 is a plan view of a first conductive layer in the pixel driving circuit according to FIG. 5;

[0056] FIG. 10 is a plan view of a combined film layer of the light shielding layer, the first semiconductor layer, and the first conductive layer in the pixel driving circuit according to FIG. 5;

[0057] FIG. 11 is a plan view of a third conductive layer in the pixel driving circuit according to FIG. 5;

[0058] FIG. 12 is a plan view of a combined film layer of the light shielding layer, the first semiconductor layer, the first conductive layer, and the third conductive layer in the pixel driving circuit according to FIG. 5;

[0059] FIG. 13 is a plan view of a combined film layer of the third conductive layer, a second semiconductor layer, and a fourth conductive layer in the pixel driving circuit according to FIG. 5;

[0060] FIG. 14 is a plan view of a second conductive layer in the pixel driving circuit according to FIG. 5;

[0061] FIG. 15 is a plan view of a combined film layer of the third conductive layer, the second semiconductor layer, the fourth conductive layer, and the second conductive layer in the pixel driving circuit according to FIG. 5;

[0062] FIG. 16 is a partial cross-sectional view of a display substrate taken along line AA’ in FIG. 5 according to some embodiments of the present disclosure;

[0063] FIG. 17 is a partial cross-sectional view of a display substrate taken along line BB’ in FIG. 5 according to some embodiments of the present disclosure.

[0064] FIG. 18 is a plan view of a pixel driving circuit of a plurality of sub-pixels in a display substrate according to some other embodiments of the present disclosure;

[0065] FIG. 19 is a plan view of a combined film layer of a first conductive layer, a second semiconductor layer, and a third conductive layer in the pixel driving circuit according to FIG. 18;

[0066] Fig. 20 is a plan view of a second conductive layer in the pixel driving circuit according to Fig. 18;

[0067] Fig. 21 is a partial cross-sectional view taken along line CC’ in Fig. 18;

[0068] Fig. 22 is a plan view of a pixel driving circuit of a plurality of sub-pixels in a display substrate according to further embodiments of the present disclosure;

[0069] Fig. 23 is a plan view of a combined film layer of a first conductive layer, a second semiconductor layer, and a fourth conductive layer in the pixel driving circuit according to Fig. 22;

[0070] Fig. 24 is a plan view of a second conductive layer in the pixel driving circuit according to Fig. 22;

[0071] Fig. 25 is a partial cross-sectional view taken along line DD’ in Fig. 22;

[0072] Fig. 26 is a plan view of a pixel driving circuit of a plurality of sub-pixels in a display substrate according to further embodiments of the present disclosure;

[0073] Fig. 27 is a plan view of a combined film layer of a light-shielding layer, a first semiconductor layer, and a first conductive layer in the pixel driving circuit according to Fig. 26;

[0074] Fig. 28 is a plan view of a combined film layer of a first conductive layer and a second semiconductor layer in the pixel driving circuit according to Fig. 26;

[0075] Fig. 29 is a plan view of a second conductive layer in the pixel driving circuit according to Fig. 26;

[0076] Fig. 30 is a partial cross-sectional view taken along line EE’ in Fig. 26;

[0077] Fig. 31A is a partial cross-sectional view taken along line FF’ in Fig. 26;

[0078] Fig. 31B is a partial cross-sectional view taken along line FF’ in a display substrate according to further embodiments of the present disclosure;

[0079] Fig. 32 is a plan view of a pixel driving circuit of a plurality of sub-pixels in a display substrate according to some embodiments of the present disclosure;

[0080] Fig. 33 is a plan view of a light-shielding layer in the pixel driving circuit according to Fig. 32;

[0081] Fig. 34 is a plan view of a combined film layer of a light-shielding layer and a first semiconductor layer in the pixel driving circuit according to Fig. 32;

[0082] FIG. 35 is a plan view of a combined film layer of a light-shielding layer, a first semiconductor layer, a first conductive layer, and a second semiconductor layer in the pixel driving circuit according to FIG. 32;

[0083] FIG. 36 is a plan view of a combined film layer of a light-shielding layer, a first semiconductor layer, a first conductive layer, a second semiconductor layer, and a third conductive layer in the pixel driving circuit according to FIG. 32;

[0084] FIG. 37 is a plan view of a second conductive layer in the pixel driving circuit according to FIG. 32;

[0085] FIG. 38 is a plan view of a combined film layer of a light-shielding layer, a first semiconductor layer, a first conductive layer, a second semiconductor layer, a third conductive layer, and a second conductive layer in the pixel driving circuit according to FIG. 32;

[0086] FIG. 39 is a partial cross-sectional view taken along line GG' in FIG. 32;

[0087] FIG. 40 is a partial cross-sectional view taken along line HH' in FIG. 32;

[0088] FIG. 41 is a plan view of a pixel driving circuit of a plurality of sub-pixels in a display substrate according to some embodiments of the present disclosure;

[0089] FIG. 42 is a partial cross-sectional view taken along line II' in FIG. 41;

[0090] FIG. 43 is a structural schematic view of a display panel according to some embodiments of the present disclosure;

[0091] FIG. 44 is a structural schematic view of a display device according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0092] In order to make the objects, technical solutions, and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings. Obviously, the described embodiments are some but not all of the embodiments of the present disclosure. Based on the described embodiments of the present disclosure, all other embodiments obtained by a person of ordinary skill in the art without creative effort belong to the protection scope of the present disclosure.

[0093] It should be noted that in the drawings, the size and relative size of the elements can be exaggerated for clarity and / or descriptive purposes. Thus, the size and relative size of the elements in the drawings should not be construed as being to scale. In the description and drawings, identical or similar reference numerals indicate identical or similar components.

[0094] When an element is described as being "on" another element, "connected to" another element, or "coupled to" another element, it can be directly on, directly connected to, or directly coupled to the other element, or intervening elements can be present. In contrast, when an element is described as being "directly on," "directly connected to," or "directly coupled to" another element, there are no intervening elements present. Other terms of description used herein, such as "between," "directly between," "adjacent to," "directly adjacent to," or "on" can be interpreted in a like fashion. In addition, the term "connected" can refer to physical or electrical connectivity, communicative connectivity, and / or fluidic connectivity. Furthermore, the X-axis, Y-axis, and Z-axis are not limited to the three axes of a Cartesian coordinate system and can be interpreted in a broader sense. For example, the X-axis, Y-axis, and Z-axis can be perpendicular to each other, or can represent different directions that are not perpendicular to each other. For the purposes of the present disclosure, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" can be interpreted to include only X, only Y, only Z, or any combination of two or more of X, Y, and Z such as XYZ, XYY, YZ, and ZZ. As used herein, the term "and / or" includes any and all combinations of one or more of the associated items.

[0095] It should be noted that, although the terms "first," "second," etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. Rather, these terms are used only to distinguish one element, component, region, layer and / or section from another element, component, region, layer and / or section. Thus, a first element, component, region, layer and / or section discussed below could be termed a second element, component, region, layer and / or section without departing from the teachings of the present disclosure.

[0096] Spatially relative terms, such as "on", "above", "left", "right", and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. For example, if a device described is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Similarly, if a device is turned over, elements described as "above" other elements or features would then be oriented "below" the other elements or features.

[0097] In this document, the terms“substantially,”“approximately,”“near,”“about,” and other similar terms are used as terms of approximation and not as terms of degree, and they are intended to account for the inherent deviations in measured or calculated values that would be recognized by those of ordinary skill in the art. Considering, for example, process variations, measurement difficulties, and errors associated with the measurement of a particular quantity (i.e., limitations of the measurement system),“about” or“approximately,” as used herein includes the stated value and means a range of values determined to be acceptable by one of ordinary skill in the art to a particular value. For example,“about” can mean within one or more standard deviations, or within ± 30%, ± 20%, ± 10%, ± 5% of the stated value.

[0098] It should be noted that, in this document, the expression“same layer” refers to a layer structure formed by using the same film forming process to form a film layer for forming a specific pattern, and then patterning the film layer by a one-time patterning process using the same mask plate. Depending on the specific pattern, the one-time patterning process can include multiple exposure, development or etching processes, and the specific pattern in the formed layer structure can be continuous or discontinuous. That is, the plurality of elements, components, structures and / or parts located in the“same layer” are composed of the same material and are formed by the same patterning process, and generally, the plurality of elements, components, structures and / or parts located in the“same layer” have substantially the same thickness.

[0099] It should be understood by those skilled in the art that, in this document, the expression“height” or“thickness” refers to the dimension along the surface of each film layer disposed perpendicular to the display substrate, i.e., the dimension along the light output direction of the display substrate, or the dimension along the normal direction of the display device, unless otherwise specified.

[0100] In this document, the expression“transistor” can be a triode, a thin film transistor or a field effect transistor or other devices with the same characteristics. In the embodiments of the present disclosure, in order to distinguish the two poles of the transistor other than the control pole, one of the poles is referred to as the first pole and the other is referred to as the second pole. In actual operation, when the transistor is a thin film transistor or a field effect transistor, the first pole can be a drain and the second pole can be a source, or the first pole can be a source and the second pole can be a drain.

[0101] Embodiments of the present disclosure at least provide a display substrate, wherein the display substrate comprises: a substrate substrate; a plurality of sub-pixels located on the substrate substrate, the plurality of sub-pixels are arranged in an array along a first direction and a second direction on the substrate substrate, at least one sub-pixel comprises a light emitting device and a pixel driving circuit for driving the light emitting device to emit light, the first direction and the second direction intersect; a plurality of signal lines provided on the substrate substrate, the plurality of signal lines comprise a first power supply signal line, the first power supply signal line is used to provide a first power supply signal to the pixel driving circuit, wherein the display substrate further comprises: a light shielding layer located on the substrate substrate; a first semiconductor layer located on a side of the light shielding layer away from the substrate substrate; and a first conductive layer located on a side of the first semiconductor layer away from the substrate substrate; the pixel driving circuit comprises a third transistor, the third transistor comprises a third active layer and a third gate, the third active layer is located in the first semiconductor layer, the third gate is located in the first conductive layer, the third active layer comprises a third channel region, and a projection of the third gate on the substrate substrate at least partially overlaps a projection of the third channel region on the substrate substrate; and the first power supply signal line comprises a first sub-power supply signal line located in the light shielding layer, and a projection of the first sub-power supply signal line on the substrate substrate covers a projection of the third channel region on the substrate substrate. By arranging the first sub-power supply signal line in the first power supply signal line in the light shielding layer, the first sub-power supply signal line can be used as a light shielding part and a power supply signal line to transmit a power supply signal at the same time, so that a conductive layer used as a power supply signal line and a planarization layer can be saved, thereby saving costs. At the same time, the light shielding part can be made of a low-resistance material, so as to ensure that the voltage drop of the power supply signal line in the light shielding part is small, which is beneficial to the transmission of the power supply signal.

[0102] FIG. 1 is a schematic plan view of a display substrate according to some embodiments of the present disclosure.

[0103] Referring to FIG. 1, a display substrate 400 according to an embodiment of the present disclosure can include a substrate substrate 10, a pixel unit PX disposed on the substrate substrate 10, a driving unit DRU disposed on the substrate substrate 10, and a wiring PL electrically connecting the pixel unit PX and the driving unit DRU, the driving unit DRU being configured to drive the pixel unit PX.

[0104] The display substrate can include a display area AA and a non-display area NA. The display area AA can be an area in which pixel units PX that display an image are disposed. The non-display area NA is an area in which the pixel units PX are not disposed, i.e., can be an area in which an image is not displayed. A driving unit DRU for driving the pixel units PX and some of the wiring lines PL connecting the pixel units PX and the driving unit DRU can be disposed in the non-display area NA. The non-display area NA corresponds to a bezel in a final display device, and a width of the bezel can be determined according to a width of the non-display area NA.

[0105] The display area AA can have various shapes. For example, the display area AA can be disposed in various shapes such as a polygon (e.g., a rectangle) including a straight side in a closed shape, a circle including a curved side, an ellipse, etc., and a semi-circle, a semi-ellipse, etc., including a straight side and a curved side. In an embodiment of the disclosure, the display area AA is disposed as one area having a quadrilateral shape including a straight side, and it should be understood that this is merely an exemplary embodiment of the disclosure, and is not a limitation of the disclosure.

[0106] The non-display area NA can be disposed at at least one side of the display area AA. In an embodiment of the disclosure, the non-display area NA can surround an outer periphery of the display area AA. In an embodiment of the disclosure, the non-display area NA can include a lateral portion extending in the first direction X and a longitudinal portion extending in the second direction Y.

[0107] The pixel units PX are disposed in the display area AA. The pixel units PX are the smallest units for displaying an image, and can be disposed in plural. For example, the pixel units PX can include light emitting devices that emit white light and / or colored light.

[0108] The pixel units PX can be disposed in plural to be arranged in a matrix form along rows extending in the first direction X and columns extending in the first direction Y. However, embodiments of the disclosure do not specifically limit the arrangement form of the pixel units PX, and the pixel units PX can be arranged in various forms. For example, the pixel units PX can be arranged such that a direction inclined with respect to the first direction X and the first direction Y becomes a column direction, and a direction crossing the column direction becomes a row direction.

[0109] A pixel unit PX can include a plurality of sub-pixels SP. For example, a pixel unit PX can include 3 sub-pixels, i.e., a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3. For another example, a pixel unit PX can include 4 sub-pixels, i.e., a first sub-pixel SP1, a second sub-pixel SP2, a third sub-pixel SP3, and a fourth sub-pixel. For example, the first sub-pixel SP1 can be a red sub-pixel, the second sub-pixel SP2 can be a green sub-pixel, the third sub-pixel SP3 can be a blue sub-pixel, and the fourth sub-pixel can be a white sub-pixel.

[0110] Each sub-pixel SP can include a light emitting element L and a pixel driving circuit 200 for driving the light emitting element. The light emitting element can include a current driving type element. Further, the light emitting element L can be a current type light emitting diode, for example, an Organic Light Emitting Diode (OLED). Illustratively, the first electrode and the second electrode of the light emitting element L are the anode and the cathode of the light emitting diode, respectively.

[0111] FIG. 2 is a structural schematic diagram of a sub-pixel according to some embodiments of the present disclosure.

[0112] As shown in FIG. 2, each sub-pixel SP includes a light emitting element L and a pixel circuit 200 coupled with the light emitting element L. The pixel circuit 200 is configured to provide a driving current to the light emitting element L to drive the light emitting element L to work (i.e., emit light).

[0113] Illustratively, continuing to refer to FIG. 2, the first electrode of the light emitting element L is coupled with the pixel circuit 200, and the second electrode of the light emitting element L is coupled with a second voltage terminal VSS. The second voltage terminal VSS is configured to transmit a second voltage. The second voltage can be a direct current reference voltage, for example, the second voltage Vss is -3V. Alternatively, the second voltage Vss is 0V, i.e., the second voltage terminal VSS is grounded. The second voltage terminal VSS only needs to provide 0V or a negative voltage to the second electrode of the light emitting element L.

[0114] FIG. 3 is a structural block diagram of a pixel circuit according to some embodiments of the present disclosure. FIG. 4 is an equivalent circuit diagram of a pixel circuit according to some embodiments of the present disclosure.

[0115] It should be noted that in the following description, a 7T1C pixel circuit is taken as an example to describe the structure of the pixel circuit in detail, but the embodiments of the present disclosure are not limited to the 7T1C pixel circuit, and other known pixel circuit structures can be applied to the embodiments of the present disclosure without conflict.

[0116] As shown in Figure 3, the pixel circuit includes: a first light emission control sub-circuit 201, a second light emission control sub-circuit 207, a first initialization sub-circuit 203, a second initialization sub-circuit 208, a data writing sub-circuit 202, a driving sub-circuit 204, a compensation sub-circuit 206, and a storage sub-circuit 205.

[0117] For example, referring to FIG3, a pixel circuit according to an embodiment of the present disclosure is used to drive a light-emitting element L. The pixel circuit includes a second initialization sub-circuit 208 for resetting the voltage of the first electrode of the light-emitting element L during a reset phase. The second initialization sub-circuit 208 is electrically connected to a second scan signal line GL2, a second initialization signal line Vinit2, and the first electrode of the light-emitting element L. Under the control of a second scan signal provided by the second scan signal line GL2, it controls the connection between the second initialization signal line Vinit2 and the first electrode of the light-emitting element L, thereby initializing the potential of the first electrode of the light-emitting element L, that is, pulling the potential of the first electrode of the light-emitting element L low.

[0118] During the reset phase, the voltage of the first electrode of the light-emitting element L is cleared by the second initialization sub-circuit 208, thereby initializing the potential of the first electrode of the light-emitting element L. This prevents the light-emitting element L from emitting light in the dark due to the leakage current of the second light-emitting control circuit 207, thus improving the display quality of the display device with this pixel circuit.

[0119] The pixel circuit further includes a first initialization sub-circuit 203 and a compensation sub-circuit 206, which can be used to reset the voltage of the third node N3 and the first node N1 during the reset phase. The compensation sub-circuit 206 is electrically connected to the third scan signal line GL3, the first node N1, and the third node N3, respectively, and is used to control the connection between the first node N1 and the third node N3 under the control of the third scan signal provided by the third scan signal line GL3. The first initialization sub-circuit 203 is electrically connected to the reset signal line R1, the first initialization signal line Vinit1, and the third node N3, respectively, and is used to control the connection between the first initialization signal line Vinit1 and the third node N3 under the control of the reset signal provided by the reset signal line R1, thereby resetting the voltage of the third node N3. Since the first node N1 and the third node N3 are connected at this time, the voltage of the first node N1 is also reset, that is, the potential of the first node is pulled low.

[0120] With continuous reference to FIG. 3, the pixel circuit further comprises a first light-emitting control sub-circuit 201 for performing voltage compensation on the first node N1 in a compensation stage. The first light-emitting control sub-circuit 201 is electrically connected with a first power signal line VDD, a light-emitting control signal line EM and a second node N2 respectively, for controlling the communication between the first power signal line VDD and the second node N2 under the control of a light-emitting control signal provided by the light-emitting control signal line EM, so as to write a first voltage Vdd provided by the first power signal line VDD into the second node N2, at which time V N2 = Vdd. In this stage, the compensation sub-circuit 206 controls the communication between the first node N1 and a third node N3 in response to a third scan signal received at a third scan signal line GL3, so as to transmit the voltage Vdd of the second node N2 and the threshold voltage Vth of the driving sub-circuit 204 to the first node N1, and thus the voltage V N1 of the first node N1 equals Vdd+Vth. Exemplarily, the first voltage Vdd from the first voltage terminal VDD is a direct current voltage, for example, a direct current high-level voltage, for example, the first voltage Vdd is 5V.

[0121] The pixel circuit can transmit the first voltage from the first power signal line VDD and the threshold voltage of the driving sub-circuit to the first node N1 in response to the light-emitting control signal and the third scan signal, so as to perform voltage compensation on the first node N1 and improve the driving effect of the pixel circuit on the light-emitting element L.

[0122] In FIG. 3, the node labeled N1 is a first node electrically connected with a control terminal of the driving sub-circuit 204, the node labeled N2 is a second node electrically connected with a first terminal of the driving sub-circuit 204, and the node labeled N3 is a third node electrically connected with a second terminal of the driving sub-circuit 204.

[0123] With continuous reference to FIG. 3, the pixel circuit further comprises a data writing sub-circuit 202 for writing a data signal provided by a data signal line Data into the second node N2 in a data writing stage. The data writing sub-circuit 202 is electrically connected with the data signal line Data, a first scan signal line GL1 and the second node N2 respectively, for controlling the communication between the data signal line Data and the second node N2 under the control of a first scan signal provided by the first scan signal line GL1 in the data writing stage, so as to write a data signal V data provided by the data signal line Data into the second node N2.

[0124] It should be understood that in the pixel circuit provided by the embodiments of the present disclosure, the nodes such as the first node N1, the second node N2, the third node N3, and the fourth node N4 do not necessarily represent actual components, and in some embodiments, these nodes represent the convergence points of the relevant couplings (i.e., electrical connections) in the equivalent circuit diagram of the pixel circuit, that is, these nodes are nodes equivalent to the convergence points of the relevant electrical connections in the circuit diagram.

[0125] Exemplarily, the light emitting element L is an OLED, and the threshold voltage of the light emitting element L is the threshold voltage V oled-th .

[0126] With reference to FIGS. 3 and 4, the pixel circuit further includes a storage sub-circuit 205 configured to maintain the potential of the first node N1. The storage sub-circuit 205 can include a storage capacitor C1, which can include a first capacitor plate C1a and a second capacitor plate C1b. The first capacitor plate C1a of the storage capacitor C1 is electrically connected to the first node N1, and the second capacitor plate C1b of the storage capacitor C1 is electrically connected to the first power supply signal line VDD.

[0127] When the voltage difference between the first power supply signal line VDD and the first node N1 is greater than the threshold voltage Vth of the driving sub-circuit 204, the driving sub-circuit 204 is turned on in response to the voltage V N1 of the first node N1 and generates a driving current I, which satisfies the following formula: I = 1 / 2·K·(Vgs-Vth) 2

[0128] wherein K is a fixed constant related to the process parameters and geometric dimensions of the driving sub-circuit 204. Vgs is the gate-source voltage difference of the driving transistor in the driving sub-circuit 204.

[0129] Continuing to refer to FIG. 3, the pixel circuit further includes a second light emitting control sub-circuit 208 for, in the light emitting stage of the image frame, outputting the driving current I transmitted to the third node N3 to the light emitting element L to drive the light emitting element L to emit light in response to the light emitting control signal received at the light emitting control signal EM.

[0130] Exemplarily, in some embodiments of the present disclosure, referring to FIG. 4, the first initialization sub-circuit 203 includes a seventh transistor T1, the second initialization sub-circuit 208 includes a first transistor T7, the first light-emitting control sub-circuit 201 includes a fifth transistor T5, the second light-emitting control sub-circuit 207 includes a sixth transistor T6, the driving sub-circuit 204 includes a third transistor T3, the compensation sub-circuit 206 includes a second transistor T2, the data writing sub-circuit 202 includes a fourth transistor T4, and the storage sub-circuit 205 can include a first capacitor C1. The light-emitting element L can be an organic light-emitting diode.

[0131] Wherein each transistor includes a control electrode of the transistor, i.e. a gate electrode; a first electrode of the transistor, i.e. one of a source electrode or a drain electrode; and a second electrode of the transistor, i.e. the other of the source electrode or the drain electrode. For example, the first transistor includes a first gate electrode, a first source electrode and a first drain electrode; the second transistor includes a second gate electrode, a second source electrode and a second drain electrode; the third transistor includes a third gate electrode, a third source electrode and a third drain electrode; the fourth transistor includes a fourth gate electrode, a fourth source electrode and a fourth drain electrode; the fifth transistor includes a fifth gate electrode, a fifth source electrode and a fifth drain electrode; the sixth transistor includes a sixth gate electrode, a sixth source electrode and a sixth drain electrode; and the seventh transistor includes a seventh gate electrode, a seventh source electrode and a seventh drain electrode.

[0132] The first capacitor C1 can include a first capacitor plate C1a and a second capacitor plate C1b. The first capacitor plate C1a of the first capacitor C1 is electrically connected to the first node N1, i.e. the first capacitor plate C1a of the first capacitor C1 is electrically connected to the third gate electrode of the third transistor and the first electrode of the second transistor. The second capacitor plate C1b of the first capacitor C1 is electrically connected to the first power signal line VDD and the first electrode of the fifth transistor.

[0133] The first gate electrode of the first transistor T1 is electrically connected to the reset signal line R1. The first electrode of the first transistor T1 is electrically connected to the third node N3. The second electrode of the first transistor T1 is electrically connected to the first initialization signal line Vinit1. For example, the first initialization signal line Vinit1 is used to provide a first initialization signal. The first electrode of the first transistor T1 is one of the first source electrode and the first drain electrode of the first transistor. The second electrode of the first transistor T1 is the other of the first source electrode and the first drain electrode of the first transistor.

[0134] The second gate of the second transistor T2 is electrically connected with the third scan signal line GL3, the first pole of the second transistor T2 is electrically connected with the first node N1, and the second pole of the second transistor T2 is electrically connected with the third node N3, that is, the first pole of the second transistor T2 is electrically connected with the gate of the third transistor T3 and the first capacitor plate C1a of the first capacitor C1, and the second pole of the second transistor T2 is electrically connected with the second pole of the third transistor T3, the first pole of the sixth transistor T6 and the first pole of the first transistor T1. For example, the first pole of the second transistor T2 is one of the second source and the second drain of the second transistor, and the second pole of the second transistor T2 is the other of the second source and the second drain of the second transistor.

[0135] The third gate of the third transistor T3 is electrically connected with the first node N1, the first pole of the third transistor T3 is electrically connected with the second node N2, and the second pole of the third transistor T3 is electrically connected with the node N3. For example, the first pole of the third transistor T3 is one of the third source and the third drain of the third transistor, and the second pole of the third transistor T3 is the other of the third source and the third drain of the third transistor.

[0136] The fourth gate of the fourth transistor T4 is electrically connected with the first scan signal line GL1, the second pole of the fourth transistor T4 is electrically connected with the data signal line Data, and the first pole of the fourth transistor T4 is electrically connected with the second node N2. For example, the first pole of the fourth transistor T4 is one of the fourth source and the fourth drain of the fourth transistor, and the second pole of the fourth transistor T4 is the other of the fourth source and the fourth drain of the fourth transistor.

[0137] The fifth gate of the fifth transistor T5 is electrically connected with the light-emitting control signal line EM, the first pole of the fifth transistor T5 is electrically connected with the first power signal line VDD, and the second pole of the fifth transistor T5 is electrically connected with the second node N2, that is, the second pole of the fifth transistor T5 is electrically connected with the first pole of the third transistor T3. The first power signal line VDD is used to provide a high voltage Vdd. For example, the first pole of the fifth transistor T5 is one of the fifth source and the fifth drain of the fifth transistor, and the second pole of the fifth transistor T5 is the other of the fifth source and the fifth drain of the fifth transistor.

[0138] The sixth gate of the sixth transistor T6 is electrically connected with the light-emitting control signal line EM; the first pole of the sixth transistor T6 is electrically connected with the node N3, that is, the first pole of the sixth transistor T6 is electrically connected with the second pole of the third transistor T3 and the second pole of the second transistor T2; the second pole of the sixth transistor T6 is electrically connected with the first electrode of the light-emitting element L, which can be an anode. For example, the first pole of the sixth transistor T6 is one of the sixth source and the sixth drain of the sixth transistor, and the second pole of the sixth transistor T6 is the other of the sixth source and the sixth drain of the sixth transistor.

[0139] The seventh gate of the seventh transistor T7 is electrically connected with the second scan signal line GL2, the second pole of the seventh transistor T7 is electrically connected with the second initialization signal terminal Vinit2, and the first pole of the seventh transistor T7 is electrically connected with the fourth node N4, that is, the first pole of the seventh transistor T7 is electrically connected with the second pole of the sixth transistor and the first electrode of the light-emitting element L; for example, the second initialization signal line Vinit2 is used to provide a second initialization signal. The first pole of the seventh transistor T7 is one of the seventh source and the seventh drain of the seventh transistor, and the second pole of the seventh transistor T7 is the other of the seventh source and the seventh drain of the seventh transistor.

[0140] That is, one of the second source and the second drain, the third gate and the first capacitor plate are electrically connected with the first node N1, one of the third source and the third drain, the other of the fourth source and the fourth drain, and the other of the fifth source and the fifth drain are electrically connected with the second node N2, the other of the first source and the first drain, the other of the second source and the second drain, the other of the third source and the third drain, and one of the sixth source and the sixth drain are electrically connected with the third node N3, the other of the sixth source and the sixth drain, and the other of the seventh source and the seventh drain are electrically connected with the fourth node N4.

[0141] The first electrode of the light-emitting element L is electrically connected with the second pole of the sixth transistor, and the second electrode of the light-emitting element L is electrically connected with the second voltage terminal VSS. The second voltage terminal VSS is used to provide a low voltage Vss.

[0142] In the embodiments of the present disclosure, Vinit1 and Vinit2 can be the same or different.

[0143] In the embodiments of the present disclosure, the fifth gate of the fifth transistor T5 and the sixth gate of the sixth transistor can be connected with the same light-emitting control signal line.

[0144] In embodiments of the present disclosure, the second transistor T2 can be an oxide thin film transistor, and other transistors (e.g., the first transistor T1, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7) can be low-temperature polysilicon thin film transistors. However, embodiments of the present disclosure are not limited thereto.

[0145] In at least one embodiment of the pixel circuit described in the present disclosure, the voltage value of Vinit1 can be greater than or equal to -6V and less than or equal to -2V, for example, the voltage value of Vinit1 can be -2V, -3V, -4V, -5V, or -6V, etc., but is not limited thereto.

[0146] The threshold voltage Vth of the transistor can be greater than or equal to -5V and less than or equal to -0.5V; for example, Vth can be -2.5V or -3V, etc.

[0147] The voltage value of the high voltage Vdd provided by the first power signal line VDD can be greater than or equal to 3V and less than or equal to 6V, for example, the voltage value of Vdd can be 4.6V; but is not limited thereto.

[0148] The absolute value of the voltage value of the high voltage Vdd can be greater than 1.5 times the absolute value of Vth, for example, the absolute value of the voltage value of Vdd can be 1.6 times, 1.8 times, 2 times, etc. the absolute value of Vth.

[0149] Optionally, the voltage value of the low voltage Vss provided by the second power signal line VSS can be greater than or equal to -6V and less than or equal to -3V; for example, the voltage value of Vss can be -5V, -4V, or -3V.

[0150] In at least one embodiment of the present disclosure, the voltage value of Vinit2 can be greater than or equal to -7V and less than or equal to 0V. For example, the voltage value of the second initialization voltage can be -6V, -5V, -4V, -3V, or -2V; but is not limited thereto.

[0151] Optionally, the voltage difference between the voltage value of Vinit2 and the voltage value of VSS needs to be less than the turn-on voltage of the light emitting element, so that when the first electrode of the light emitting element is connected to Vinit2, the light emitting element does not emit light.

[0152] In embodiments of the present disclosure, the second transistor T2 included in the compensation sub-circuit can be an oxide thin film transistor, which can reduce the leakage current of the control end of the driving circuit, ensure the stability of the voltage of the control end of the driving circuit, improve the display quality, improve the display uniformity, and reduce Flicker (flicker).

[0153] In embodiments of the present disclosure, the seventh transistor T7 can be controlled by a separate GOA which is electrically connected with the second scan signal line GL2, so that the light emitting element L can be reset at a specific frequency, for example, 240Hz.

[0154] In embodiments of the present disclosure, the second scan signal provided by the second scan signal line GL2 can be a high frequency signal. By increasing the frequency of the second scan signal provided by the second scan signal line GL2, the refresh frequency of the first electrode of the light emitting element L can be increased, so that the brightness setup time of the refresh stage and the holding stage of the light emitting element L remains consistent. In this way, the low component of the light emitting holding stage can be reduced, the brightness change visible to the naked eye can be reduced, the flicker level can be improved, and the power consumption can be reduced due to the reduced load.

[0155] It should be noted that in embodiments of the present disclosure, each of the thin film transistors T1, T2, T3, T4, T5, T6 and T7 can be a p-channel field effect transistor, but embodiments of the present disclosure are not limited thereto, and at least some of the thin film transistors T1, T2, T3, T4, T5, T6 and T7 can be n-channel field effect transistors.

[0156] FIG. 5 is a plan view of a pixel driving circuit of a plurality of sub-pixels in a display substrate according to some embodiments of the present disclosure; FIG. 6 is a plan view of a light shielding layer in the pixel driving circuit according to FIG. 5; FIG. 7 is a plan view of a first semiconductor layer in the pixel driving circuit according to FIG. 5; FIG. 8 is a plan view of a combined film layer of the light shielding layer and the first semiconductor layer in the pixel driving circuit according to FIG. 5; FIG. 9 is a plan view of a first conductive layer in the pixel driving circuit according to FIG. 5; FIG. 10 is a plan view of a combined film layer of the light shielding layer, the first semiconductor layer and the first conductive layer in the pixel driving circuit according to FIG. 5; FIG. 11 is a plan view of a third conductive layer in the pixel driving circuit according to FIG. 5; FIG. 12 is a plan view of a combined film layer of the light shielding layer, the first semiconductor layer, the first conductive layer and the third conductive layer in the pixel driving circuit according to FIG. 5; FIG. 13 is a plan view of a combined film layer of the third conductive layer, a second semiconductor layer and a fourth conductive layer in the pixel driving circuit according to FIG. 5; FIG. 14 is a plan view of a second conductive layer in the pixel driving circuit according to FIG. 5; FIG. 15 is a plan view of a combined film layer of the third conductive layer, the second semiconductor layer, the fourth conductive layer and the second conductive layer in the pixel driving circuit according to FIG. 5; FIG. 16 is a partial cross-sectional view of a display substrate taken along line AA' in FIG. 5 according to some embodiments of the present disclosure; and FIG. 17 is a partial cross-sectional view of a display substrate taken along line BB' in FIG. 5 according to some embodiments of the present disclosure.

[0157] Exemplarily, in the embodiments of the present disclosure, in combination with reference to FIGS. 5-17, the display substrate 400 comprises, in sequence from the substrate 10, the light shielding layer 1, the first semiconductor layer 2, the first conductive layer 3, the third conductive layer 4, the second semiconductor layer 5, the fourth conductive layer 6, the second conductive layer 7, the planarization layer PLN and the first electrode layer 100. The display substrate can further comprise a plurality of insulating layers and a plurality of passivation layers, for example, the insulating layer GI and the passivation layer PVX, wherein the insulating layer GI comprises the insulating layer GI-1 located between the first conductive layer 2 and the third conductive layer 4. In order to clearly describe the inventive points of the present disclosure, the schematic diagrams of the plurality of insulating layers and the plurality of passivation layers are omitted in the plurality of schematic diagrams of the present disclosure.

[0158] The pixel driving circuit comprises a plurality of signal lines arranged on the substrate, the plurality of signal lines comprising a first power signal line VDD for providing a first power signal to the pixel driving circuit. The plurality of signal lines further comprises a first initialization signal line Vinit1, a second initialization signal line Vinit2, a reset signal line R1, a first scan signal line GL1, a second scan signal line GL2, a third scan signal line GL3, an emission control signal line EM and a data signal line Data, the first initialization signal line Vinit1, the second initialization signal line Vinit2, the reset signal line R1, the first scan signal line GL1, the second scan signal line GL2, the third scan signal line GL3 and the emission control signal line EM extending along a first direction X, and the data signal line Data extending along a second direction Y. The reset signal line R1, the first scan signal line GL1, the second scan signal line GL2, the emission control signal line EM and the second initialization signal line Vinit2 are located in the first conductive layer 3; and the first initialization signal line Vinit1 is located in the third conductive layer 4. The pixel driving circuit further comprises a plurality of transistors and a storage capacitor, for example, a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7 and a storage capacitor C1.

[0159] Exemplarily, in some embodiments of the present disclosure, in combination with reference to FIG. 5, the pixel driving circuit includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a storage capacitor C1. The first transistor T1 includes a first gate G1 electrically connected to a reset signal line R1, a first source S1 and a first drain D1, one of which is electrically connected to a first initialization signal line Vinit1; the second transistor T2 includes a second gate G2 electrically connected to a third scan signal line GL3, a second source S2 and a second drain D2; the third transistor T3 includes a third gate G3, a third source S3 and a third drain D3; the fourth transistor T4 includes a fourth gate G4 electrically connected to a first scan signal line GL1, a fourth source S4 and a fourth drain D4, one of which is electrically connected to a data signal line Data; the fifth transistor T5 includes a fifth gate G5 electrically connected to an emission control signal line EM, a fifth source S5 and a fifth drain D5, one of which is electrically connected to the first power supply signal line; the sixth transistor T6 includes a sixth gate G6 electrically connected to the emission control signal line EM, a sixth source S6 and a sixth drain D6; the seventh transistor T7 includes a seventh gate G7 electrically connected to a second scan signal line GL2, a seventh source S7 and a seventh drain D7, one of which is electrically connected to the second initialization signal line Vinit2; and one of the second source S2 and the second drain D2, the third gate G3 and the first capacitor plate are electrically connected to a first node N1 respectively; one of the third source S3 and the third drain D3, the other of the fourth source S4 and the fourth drain D4, and the other of the fifth source S5 and the fifth drain D5 are electrically connected to a second node N2 respectively; the other of the first source S1 and the first drain D1, the other of the second source S2 and the second drain D2, the other of the third source S3 and the third drain D3, and one of the sixth source S6 and the sixth drain D6 are electrically connected to a third node N3 respectively; the other of the sixth source S6 and the sixth drain D6, and the other of the seventh source S7 and the seventh drain D7 are electrically connected to a fourth node N4 respectively.

[0160] Exemplarily, in some embodiments of the disclosure, the display substrate 400 further comprises a plurality of conductive transfer portions 70 in the second conductive layer 7, the plurality of conductive transfer portions 70 comprises a second conductive transfer portion 702 for electrically connecting one of the first source S1 and the first drain D1 of the first transistor T1 with the first initialization signal line Vinit1, the plurality of conductive transfer portions 70 further comprises a third conductive transfer portion 703 for electrically connecting one of the second source S2 and the second drain D2 of the second transistor T2 with the first node N1, the plurality of conductive transfer portions 70 further comprises a fourth conductive transfer portion 704 for respectively electrically connecting the other one of the second source S2 and the second drain D2 of the second transistor T2, one of the third source S3 and the third drain D3 of the third transistor T3, the other one of the first source S1 and the first drain D1 of the first transistor T1, and one of the sixth source S6 and the sixth drain D6 of the sixth transistor T6 with the third node N3, the plurality of conductive transfer portions 70 further comprises a fifth conductive transfer portion 705 for electrically connecting one of the fourth source S4 and the fourth drain D4 of the fourth transistor T4 with the data signal line Data, the plurality of conductive transfer portions 70 further comprises a sixth conductive transfer portion 706 for respectively electrically connecting the other one of the third source S3 and the third drain D3 of the third transistor T3, the other one of the fourth source S4 and the fourth drain D4 of the fourth transistor T4, and one of the fifth source S5 and the fifth drain D5 of the fifth transistor T5 with the second node N2, the plurality of conductive transfer portions 70 further comprises a seventh conductive transfer portion 707 for electrically connecting the other one of the fifth source S5 and the fifth drain D5 of the fifth transistor T5 with the first power signal line VDD, the plurality of conductive transfer portions 70 further comprises an eighth conductive transfer portion 708 for respectively electrically connecting the other one of the sixth source S6 and the sixth drain D6 of the sixth transistor T6 and one of the seventh source S7 and the seventh drain D7 of the seventh transistor T7 with the fourth node N4, the plurality of conductive transfer portions 70 further comprises a ninth conductive transfer portion 709 for electrically connecting the other one of the seventh source S7 and the seventh drain D7 of the seventh transistor T7 with the second initialization signal line Vinit2.

[0161] Exemplarily, in some embodiments of the present disclosure, in combination with reference to FIGS. 5-10 and 16, the display substrate 400 comprises: the light shielding layer 1 located on the substrate substrate 10; the first semiconductor layer 2 located on the side of the light shielding layer 1 away from the substrate substrate 10 and the first conductive layer 3 located on the side of the first semiconductor layer 2 away from the substrate substrate 10. The pixel driving circuit comprises a plurality of transistors, for example, the pixel driving circuit comprises a driving transistor for driving the light emitting device to emit light, and the driving transistor can be the third transistor T3. The third transistor T3 comprises a third active layer ACT3 and a third gate G3, the third active layer ACT3 is located in the first semiconductor layer 2, and the third gate G3 is located in the first conductive layer 3, the third active layer ACT3 comprises a third channel region CH3, and the orthographic projection of the third gate G3 on the substrate substrate at least partially overlaps the orthographic projection of the third channel region CH3 on the substrate substrate. The first power supply signal line VDD comprises a first sub-power supply signal line VDD1 located in the light shielding layer 1, and the orthographic projection of the first sub-power supply signal line on the substrate substrate covers the orthographic projection of the third channel region CH3 on the substrate substrate. The first semiconductor layer 2 can comprise a single crystal silicon, amorphous silicon or polycrystalline silicon semiconductor material, for example, the third transistor can be a low-temperature polycrystalline silicon thin film transistor.

[0162] Exemplarily, in some embodiments of the present disclosure, in combination with reference to FIGS. 5, 7 and 10, the pixel driving circuit further comprises a first transistor T1, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6 and a seventh transistor T7. The first transistor T1 comprises a first active layer ACT1 and a first gate G1, the first active layer ACT1 is located in the first semiconductor layer 2, and the first gate G1 is located in the first conductive layer 3; the fourth transistor T4 comprises a fourth active layer ACT4 and a fourth gate G4, the fourth active layer ACT4 is located in the first semiconductor layer 2, and the fourth gate G4 is located in the first conductive layer 3; the fifth transistor T5 comprises a fifth active layer ACT5 and a fifth gate G5, the fifth active layer ACT5 is located in the first semiconductor layer 2, and the fifth gate G5 is located in the first conductive layer 3; the sixth transistor T6 comprises a sixth active layer ACT6 and a first gate G6, the sixth active layer ACT6 is located in the first semiconductor layer 2, and the sixth gate G6 is located in the first conductive layer 3; and the seventh transistor T7 comprises a seventh active layer ACT7 and a seventh gate G7, the seventh active layer ACT7 is located in the first semiconductor layer 2, and the seventh gate G7 is located in the first conductive layer 3.

[0163] Exemplarily, in some embodiments of the present disclosure, in combination with reference to FIGS. 5 and 6, the first power supply signal line VDD further comprises a second sub-power supply signal line VDD2 located in the light shielding layer 1. The main body part VDD1-L of the first sub-power supply signal line extends along the first direction X, and the second sub-power supply signal line VDD2 extends along the second direction Y.

[0164] Exemplarily, continuing to refer to FIGS. 5 and 6, the display substrate includes m first sub-power signal lines VDD1 and n second sub-power signal lines VDD2 in the light shielding layer 1, each of the m first sub-power signal lines crosses the n second sub-power signal lines VDD2, so that the part of the first power signal line VDD in the light shielding layer 1 has a grid structure, m is greater than or equal to 1, and n is greater than or equal to 2.

[0165] By arranging the first sub-power signal lines and the second sub-power signal lines in the first power signal line in the light shielding layer, the light shielding part and the power signal line can be used to transmit the power signal at the same time, so that one conductive layer used as the power signal line and one planarization layer can be saved, thereby saving cost. The light shielding part can be made of a low-resistance material, so as to ensure that the voltage drop of the power signal line in the light shielding part is small, which is conducive to the transmission of the power signal. Meanwhile, the grid-shaped first power signal line design can facilitate the transmission of the first power signal in the first direction and the second direction, shorten the transmission distance, reduce the voltage drop, and improve the driving effect of the pixel driving circuit. By arranging the first sub-power signal lines and the second sub-power signal lines in the first power signal line in the light shielding layer, the light shielding part and the power signal line can be used to transmit the power signal at the same time, and the width of the signal line can be designed to be small, which is conducive to improving the flatness of the film layer and the aperture ratio of the display substrate, and improving the display effect of the display product.

[0166] Exemplarily, in some embodiments of the present disclosure, referring to FIG. 16, the display substrate further includes a second conductive layer 7 located on the side of the first conductive layer 3 away from the substrate substrate, a planarization layer PLN located on the side of the second conductive layer 7 away from the substrate substrate, and a first electrode layer 100 located on the side of the planarization layer PLN away from the substrate substrate. Referring to FIGS. 5 and 14, the pixel driving circuit includes a third transistor T3, for example, the third transistor T3 can be a driving transistor. The third transistor T3 includes a third source S3 and a third drain D3, and the third source S3 and the third drain D3 are located in the second conductive layer 7.

[0167] Exemplarily, referring to FIG. 16, the light emitting element L further includes a first electrode 110, an organic light emitting functional layer 111, and a second electrode 112, the first electrode 110 is located in the first electrode layer 100; the planarization layer PLN includes a first surface PLN1 facing the second conductive layer 7 and a second surface PLN2 facing the first electrode layer 100, the first surface PLN1 contacts at least part of the second conductive layer 7, and the second surface PLN2 contacts at least part of the first electrode layer 100.

[0168] Exemplarily, in some embodiments of the present disclosure, the pixel driving circuit further comprises a storage capacitor C1, which comprises a first capacitor plate C1a and a second capacitor plate C1b in combination with reference to FIGS. 5, 11 and 12; at least a portion of the first capacitor plate C1a is located in the first conductive layer 3; the portion of the first capacitor plate C1a overlapping with the third active layer ACT3 is the third gate of the third transistor. The display substrate further comprises a third conductive layer 4 located on the side of the first conductive layer 3 away from the substrate substrate, and the second capacitor plate C1b is located in the third conductive layer 4. The portion of the first power supply signal line VDD located in the light shielding layer 1 is electrically connected to the second capacitor plate C1b through the second via VH2 in the display area.

[0169] Exemplarily, in some embodiments of the present disclosure, in combination with reference to FIGS. 5, 14 and 16, the display substrate 400 further comprises: a second conductive layer 7 located on the side of the first conductive layer 3 away from the substrate substrate; the third transistor T3 comprises a third source S3 and a third drain D3, and the third source S3 and the third drain D3 are located in the second conductive layer 7; and the first power supply signal line VDD further comprises a third sub-power supply signal line VDD3 located in the second conductive layer 7. The orthographic projection of the third sub-power supply signal line VDD3 on the substrate substrate at least partially overlaps with the orthographic projection of the second sub-power supply signal line VDD2 on the substrate substrate. The voltage drop on the first power supply signal line can be reduced by the partial parallel connection of the first power supply signal line, and the stability of the driving circuit can be improved, thereby improving the display effect of the display substrate.

[0170] Exemplarily, in some embodiments of the present disclosure, in combination with reference to FIGS. 5, 6 and 14, the display substrate 400 comprises k third sub-power supply signal lines VDD3 located in the second conductive layer 7; and the number n of the second sub-power supply signal lines VDD2 is more than twice the number k of the third sub-power supply signal lines VDD3. k is greater than or equal to 1, and n is greater than or equal to 2. The voltage drop of the first power supply signal line can be reduced by densely arranging the first power supply signal lines in the second direction in the light shielding layer 1, and the stability of the driving circuit can be improved, thereby improving the display effect of the display substrate.

[0171] Exemplarily, in combination with reference to FIGS. 5, 6 and 14, the third sub-power supply signal line VDD3 is electrically connected to the second sub-power supply signal line VDD2 through the first via VH1.

[0172] Exemplarily, in some embodiments of the present disclosure, in combination with reference to FIG. 5, FIG. 13, FIG. 15 and FIG. 17, the display substrate 400 further comprises a second semiconductor layer 5 located on the side of the first semiconductor layer 2 away from the substrate 10. The pixel driving circuit further comprises a second transistor T2, the second transistor T2 comprises a second active layer ACT2, and the second active layer ACT2 is located in the second semiconductor layer 5. For example, the second semiconductor layer 5 can comprise an oxide semiconductor material, that is, the second transistor T2 can be an oxide thin film transistor.

[0173] Exemplarily, in some embodiments of the present disclosure, in combination with reference to FIG. 5, FIG. 13 and FIG. 17, the second transistor T2 comprises a second gate G2, the second gate G2 comprises a first sub-gate G21 and a second sub-gate G22, the layer where the first sub-gate G21 is located is on the side of the second semiconductor layer 5 close to the substrate 10, the layer where the second sub-gate G22 is located is on the side of the second semiconductor layer 5 away from the substrate 10, the orthographic projection of the first sub-gate G21 on the substrate 10 at least partially overlaps with the orthographic projection of the second active layer ACT2 on the substrate 10, and the orthographic projection of the second sub-gate G22 on the substrate 10 at least partially overlaps with the orthographic projection of the second active layer ACT2 on the substrate 10.

[0174] Exemplarily, in some embodiments of the present disclosure, in combination with reference to FIG. 13, FIG. 16 and FIG. 17, the display substrate further comprises a third conductive layer 4 located between the first semiconductor layer 2 and the second semiconductor layer 5, and a fourth conductive layer 6 located on the side of the second semiconductor layer 5 away from the substrate 10; the first sub-gate G21 of the second transistor T2 is located in the third conductive layer 4, and the second sub-gate G22 of the second transistor T2 is located in the fourth conductive layer 6. That is, the second transistor T2 has a double-gate structure located in different conductive layers.

[0175] Exemplarily, a gate insulating layer 50 can be provided between the first sub-gate G21 and the second active layer ACT2. A gate insulating layer 50 can be provided between the second sub-gate G22 and the second active layer ACT2. The display substrate can further comprise other insulating layers, such as an interlayer insulating layer 60.

[0176] Exemplarily, in some embodiments of the present disclosure, in combination with reference to FIG. 5, FIG. 9, FIG. 11 and FIG. 12, the pixel driving circuit further comprises a storage capacitor C1, the storage capacitor C1 comprises a first capacitor plate C1a and a second capacitor plate C1b; at least a part of the first capacitor plate C1a is located in the first conductive layer 3; and at least a part of the second capacitor plate C1b is located in the third conductive layer 4.

[0177] Exemplarily, in some embodiments of the present disclosure, in combination with reference to FIGS. 5, 6, 11 and 14, a part of the third sub-power signal line VDD3 is electrically connected with the second sub-power signal line VDD2 through the first via VH1, and another part of the third sub-power signal line VDD3 is electrically connected with at least a part of the second capacitor plate C1b in the display area through the second via VH2. For example, the second sub-power signal line VDD2, the third sub-power signal line VDD3 and the second capacitor plate C1b can be all electrically connected with each other through the second via VH2.

[0178] Exemplarily, in some embodiments of the present disclosure, the material of the light shielding layer 1 can include copper or aluminum. For example, the resistivity of the material of the light shielding layer 1 is lower than the resistivity of the material of the second conductive layer.

[0179] Exemplarily, in some embodiments of the present disclosure, the display substrate includes a plurality of sub-pixels and pixel driving circuits for driving the plurality of sub-pixels. For example, in combination with reference to FIGS. 5 and 6, the plurality of sub-pixels include sub-pixels in the jth column and sub-pixels in the j+1th column. In the light shielding layer 1, a first part P1 of the first power signal line for providing the pixel driving circuit of the jth column of sub-pixels and a second part P2 of the first power signal line for providing the pixel driving circuit of the j+1th column of sub-pixels are symmetrical with respect to a first imaginary straight line M1, wherein the first imaginary straight line M1 is a straight line extending along the second direction Y. That is, the first power signal line included in the pixel driving circuits of the two adjacent sub-pixels is symmetrical about the first imaginary straight line M1.

[0180] Exemplarily, in some embodiments of the present disclosure, the connection mode of the second gate G2 in the second transistor T2 can be changed in the pixel driving circuit of the display substrate, for example, the first sub-gate G21 of the second gate G2 is arranged in the first conductive layer 3, and the second sub-gate G22 of the second gate G2 is arranged in the third conductive layer 4 or the fourth conductive layer 6, so that one conductive layer can be omitted, for example, the fourth conductive layer or the third conductive layer, the manufacturing process is reduced, and the cost is saved. The display substrate can also arrange a part of the first power signal line in the light shielding layer, which can be used as a light shielding part and a power signal line to transmit a power signal at the same time, so that one conductive layer used as a power signal line and one planarization layer can be omitted, thereby saving cost. The light shielding part can adopt a low-resistance material, so as to ensure that the voltage drop of the power signal line in the light shielding part is small, which is conducive to the transmission of the power signal. At the same time, the grid-shaped design of the first power signal line can facilitate the transmission of the first power signal in the first direction and the second direction, shorten the transmission distance, reduce the voltage drop, and improve the driving effect of the pixel driving circuit.

[0181] Exemplarily, in some embodiments of the present disclosure, the pixel driving circuit can be a low-temperature polysilicon driving circuit, for example, the second transistor can be a LTPS (Low Temperature Poly-Silicon) thin film transistor. That is, the pixel driving circuit provided by the embodiments of the present disclosure can be compatible with a LTPS display substrate. In this case, the second semiconductor layer and the fourth conductive layer can be removed, realizing a high-PPI display substrate. By arranging the first sub-power signal line and the second sub-power signal line in the first power signal line in the light shielding layer, the first sub-power signal line and the second sub-power signal line can be used as a light shielding part and a power signal line to transmit a power signal at the same time, so that one conductive layer used as a power signal line and one planarization layer can be saved, thereby saving costs. The light shielding part can be made of a low-resistance material, thereby ensuring that the voltage drop of the power signal line in the light shielding part is small, which is conducive to the transmission of the power signal. Meanwhile, the grid-shaped design of the first power signal line can facilitate the transmission of the first power signal in the first direction and the second direction, shorten the transmission distance, reduce the voltage drop, and improve the driving effect of the pixel driving circuit. By arranging the first sub-power signal line and the second sub-power signal line in the first power signal line in the light shielding layer, the first sub-power signal line and the second sub-power signal line can be used as a light shielding part and a power signal line to transmit a power signal at the same time, and the width of the signal line trace can be designed to be small, which is conducive to improving the flatness of the film layer and the aperture ratio of the display substrate, and is conducive to improving the display effect of the display product.

[0182] FIG. 18 is a plan view of a pixel driving circuit of a plurality of sub-pixels in a display substrate according to some embodiments of the present disclosure; FIG. 19 is a plan view of a combined film layer of a first conductive layer, a second semiconductor layer, and a third conductive layer in the pixel driving circuit according to FIG. 18; FIG. 20 is a plan view of a second conductive layer in the pixel driving circuit according to FIG. 18; and FIG. 21 is a partial cross-sectional view taken along line CC’ in FIG. 18.

[0183] Exemplarily, in some embodiments of the present disclosure, in combination with reference to FIGS. 18 and 19, the display substrate 400 comprises a plurality of sub-pixels and a pixel driving circuit for driving the plurality of sub-pixels, the pixel driving circuit comprises a plurality of signal lines arranged on the substrate, the plurality of signal lines comprises a first power signal line VDD for providing a first power signal to the pixel driving circuit. The plurality of signal lines further comprises a first initialization signal line Vinit1, a second initialization signal line Vinit2, a reset signal line R1, a first scan signal line GL1, a second scan signal line GL2, a third scan signal line GL3, an emission control signal line EM, and a data signal line Data, the first initialization signal line Vinit1, the second initialization signal line Vinit2, the reset signal line R1, the first scan signal line GL1, the second scan signal line GL2, the third scan signal line GL3, and the emission control signal line EM extend along a first direction X, and the data signal line Data extends along a second direction Y. The reset signal line R1, the first scan signal line GL1, the second scan signal line GL2, the emission control signal line EM, and the second initialization signal line Vinit2 are located in the first conductive layer 3; the first initialization signal line Vinit1 is located in the third conductive layer 4. A part of the third scan signal line GL3 is located in the first conductive layer 3, and another part of the third scan signal line GL3 is located in the third conductive layer 4, that is, the third scan signal line is formed by a part located in the first conductive layer 3 and another part located in the third conductive layer 4 in parallel, for transmitting a third scan signal.

[0184] Exemplarily, in some embodiments of the present disclosure, in combination with reference to FIGS. 18, 20, and 21, the display substrate 400 further comprises: a second conductive layer 7 located on the side of the first conductive layer 3 away from the substrate; a third transistor T3 comprising a third source S3 and a third drain D3, the third source S3 and the third drain D3 are located in the second conductive layer 7, and the first power signal line VDD further comprises a first conductive adapter 701 located in the second conductive layer 7, the first conductive adapter is electrically connected with a second sub-power signal line VDD2 through a first via VH1.

[0185] Exemplarily, a gate insulating layer 50 can be arranged between the first sub-gate G21 and the second active layer ACT2. A gate insulating layer 50 can be arranged between the second sub-gate G22 and the second active layer ACT2. The display substrate can further comprise other insulating layers, such as an interlayer insulating layer 60.

[0186] Exemplarily, in some embodiments of the present disclosure, in combination with reference to FIGS. 18 and 20, the orthographic projection of the first conductive adapter 701 on the substrate 10 at least partially overlaps with the orthographic projection of the second sub-power signal line VDD2 on the substrate 10.

[0187] Exemplarily, in some embodiments of the present disclosure, in combination with reference to FIGS. 18 and 19, the display substrate further comprises a second transistor T2, the second transistor T2 comprises a second gate G2, the second gate G2 comprises a first sub-gate G21 and a second sub-gate G22. The display substrate further comprises a second semiconductor layer 5 and a third conductive layer 4 located on the side of the second semiconductor layer 5 away from the substrate 10; the first sub-gate G21 is located in the first conductive layer 3, and the second sub-gate G22 is located in the third conductive layer 4.

[0188] Exemplarily, in some embodiments of the present disclosure, in combination with reference to FIGS. 18 and 19, the display substrate further comprises a storage capacitor C1, the storage capacitor C1 comprises a first capacitor plate C1a and a second capacitor plate C1b, at least a part of the first capacitor plate C1a is located in the first conductive layer 3, and at least a part of the second capacitor plate C1b is located in the third conductive layer 4. A part of the first conductive adapter 701 is electrically connected with the second sub-power signal line VDD2 through a first via VH1, and another part of the first conductive adapter 701 is electrically connected with at least a part of the second capacitor plate C1b in the display area through a second via VH2.

[0189] By changing the connection mode of the gate of the second transistor T2, for example, the first sub-gate G21 of the second transistor is arranged in the first conductive layer 3, and the second sub-gate G22 is arranged in the third conductive layer 4, and the second capacitor plate C1b of the storage capacitor C1 can also be arranged in the third conductive layer 4 accordingly, so that one layer of conductive layer can be saved, and the corresponding metal mask plate can be reduced, thereby saving cost.

[0190] FIG. 22 is a plan view of a pixel driving circuit of a plurality of sub-pixels in a display substrate according to some other embodiments of the present disclosure; FIG. 23 is a plan view of a combined film layer of a first conductive layer, a second semiconductor layer and a fourth conductive layer in the pixel driving circuit according to FIG. 22; FIG. 24 is a plan view of a second conductive layer in the pixel driving circuit according to FIG. 22; and FIG. 25 is a partial cross-sectional view taken along the line DD’ in FIG. 22.

[0191] Exemplarily, in some embodiments of the present disclosure, in combination with reference to FIG. 22 and FIG. 23, the display substrate 400 comprises a plurality of sub-pixels and a pixel driving circuit for driving the plurality of sub-pixels, the pixel driving circuit comprises a plurality of signal lines arranged on the substrate, the plurality of signal lines comprises a first power signal line VDD for providing a first power signal to the pixel driving circuit. The plurality of signal lines further comprises a first initialization signal line Vinit1, a second initialization signal line Vinit2, a reset signal line R1, a first scan signal line GL1, a second scan signal line GL2, a third scan signal line GL3, an emission control signal line EM and a data signal line Data, the first initialization signal line Vinit1, the second initialization signal line Vinit2, the reset signal line R1, the first scan signal line GL1, the second scan signal line GL2, the third scan signal line GL3 and the emission control signal line EM extend along a first direction X, and the data signal line Data extends along a second direction Y. The reset signal line R1, the first scan signal line GL1, the second scan signal line GL2, the emission control signal line EM and the second initialization signal line Vinit2 are located in the first conductive layer 3; the first initialization signal line Vinit1 is located in the fourth conductive layer 6. A part of the third scan signal line GL3 is located in the first conductive layer 3, and another part of the third scan signal line GL3 is located in the fourth conductive layer 6, that is, the third scan signal line is formed by a part located in the first conductive layer 3 and another part located in the fourth conductive layer 6 in parallel, for transmitting a third scan signal.

[0192] Exemplarily, in some embodiments of the present disclosure, in combination with reference to FIG. 22, FIG. 24 and FIG. 25, the display substrate 400 further comprises: a second conductive layer 7 located on the side of the first conductive layer 3 away from the substrate; a third transistor T3 comprising a third source S3 and a third drain D3, the third source S3 and the third drain D3 are located in the second conductive layer 7, and the first power signal line VDD further comprises a first conductive adapter 701 located in the second conductive layer 7, the first conductive adapter is electrically connected with a second sub-power signal line VDD2 through a first via VH1.

[0193] Exemplarily, a gate insulating layer 50 can be arranged between the first sub-gate G21 and the second active layer ACT2. A gate insulating layer 50 can be arranged between the second sub-gate G22 and the second active layer ACT2. The display substrate can further comprise other insulating layers, such as an interlayer insulating layer 60.

[0194] Exemplarily, in some embodiments of the present disclosure, in combination with reference to FIG. 22 and FIG. 24, the first conductive adapter 701 has a projection on the substrate 10 that at least partially overlaps with a projection of the second sub-power signal line VDD2 on the substrate 10.

[0195] Exemplarily, in some embodiments of the present disclosure, in combination with reference to FIG. 22 and FIG. 23, the display substrate further comprises a second transistor T2, the second transistor T2 comprises a second gate G2, the second gate G2 comprises a first sub-gate G21 and a second sub-gate G22. The display substrate further comprises a second semiconductor layer 5 and a fourth conductive layer 6 located on a side of the second semiconductor layer 5 away from the substrate 10; the first sub-gate G21 is located in the first conductive layer 3, and the second sub-gate G22 is located in the fourth conductive layer 6.

[0196] The display substrate further comprises a storage capacitor C1, the storage capacitor C1 comprises a first capacitor plate C1a and a second capacitor plate C1b, at least a part of the first capacitor plate C1a is located in the first conductive layer 3, and at least a part of the second capacitor plate C1b is located in the fourth conductive layer 6. A part of the first conductive connection 701 is electrically connected with the second sub-power signal line VDD2 through a first via VH1, and another part of the first conductive connection 701 is electrically connected with at least a part of the second capacitor plate C1b in the display area through a second via VH2.

[0197] By changing the connection mode of the gate of the second transistor T2, for example, the first sub-gate G21 of the second transistor is arranged in the first conductive layer 3, and the second sub-gate G22 is arranged in the fourth conductive layer 6, and the second capacitor plate C1b of the storage capacitor C1 can also be arranged in the fourth conductive layer 6 accordingly, so that one layer of conductive layer can be saved, and the corresponding metal mask can be reduced, thereby saving cost.

[0198] Exemplarily, in some embodiments of the present disclosure, the pixel driving circuit of the display substrate comprises a second transistor, the second transistor can be a single-gate structure, for example, the gate of the second transistor can be arranged in the first conductive layer 3, that is, the gate of the second transistor in the pixel driving circuit and the gate of other transistors, for example, the gate of the third transistor, can be arranged in the same layer, so that the third conductive layer and the fourth conductive layer can be saved at the same time, and the corresponding metal mask can be reduced. The light shielding part can adopt a low-resistance material, so as to ensure that the voltage drop of the power signal line in the light shielding part is small, which is conducive to the transmission of the power signal. At the same time, the grid-shaped first power signal line design can facilitate the transmission of the first power signal in the first direction and the second direction, shorten the transmission distance, reduce the voltage drop, and improve the driving effect of the pixel driving circuit.

[0199] FIG. 26 is a plan view of a pixel driving circuit of a plurality of sub-pixels in a display substrate according to some embodiments of the present disclosure; FIG. 27 is a plan view of a combined film layer of a light shielding layer, a first semiconductor layer, and a first conductive layer in the pixel driving circuit according to FIG. 26; FIG. 28 is a plan view of a combined film layer of the first conductive layer and a second semiconductor layer in the pixel driving circuit according to FIG. 26; FIG. 29 is a plan view of a second conductive layer in the pixel driving circuit according to FIG. 26; FIG. 30 is a partial cross-sectional view taken along line EE’ in FIG. 26; FIG. 31A is a partial cross-sectional view taken along line FF’ in FIG. 26; FIG. 31B is a partial cross-sectional view taken along line FF’ in a display substrate according to some embodiments of the present disclosure.

[0200] For example, in some embodiments of the present disclosure, in combination with reference to FIGS. 26-28, the display substrate 400 includes a first initialization signal line Vinit1, a reset signal line R1, a first scan signal line GL1, a second scan signal line GL2, a third scan signal line GL3, a light-emitting control signal line EM, and a second initialization signal line Vinit2. The first initialization signal line Vinit1, the reset signal line R1, the first scan signal line GL1, the second scan signal line GL2, the third scan signal line GL3, the light-emitting control signal line EM, and the second initialization signal line Vinit2 are all located in the first conductive layer 3.

[0201] For example, in some embodiments of the present disclosure, in combination with reference to FIGS. 26-28 and 31A, the display substrate 400 can further include the first conductive layer 3 and the second semiconductor layer 5, the first conductive layer 3 being located on a side of the second semiconductor layer 5 away from the substrate. The display substrate 400 can further include a first insulating layer GI1 located between the first semiconductor layer 2 and the second semiconductor layer, and a second insulating layer GI2 located between the second semiconductor layer 5 and the first conductive layer 3. The display substrate further includes a second transistor T2 including a second gate G2 and a second active layer ACT2, and a third transistor T3 including a third gate G3 and a third active layer ACT3, the second gate G2 and the third gate G3 both being located in the first conductive layer 3, a projection of the second gate G2 on the substrate at least partially overlapping a projection of the second active layer ACT2 on the substrate, and a projection of the third gate G3 on the substrate at least partially overlapping a projection of the third active layer ACT3 on the substrate.

[0202] For example, a portion of the first insulating layer GI1 and the second insulating layer GI2 collectively constitute a gate insulating layer of the third transistor T3, and a portion of the second insulating layer GI2 constitutes a gate insulating layer of the second transistor T2.

[0203] For example, in some embodiments of the present disclosure, in combination with reference to FIGS. 28 and 31A, the second transistor T2 can be a single-gate structure, the thickness of the insulating layer between the first semiconductor layer 2 and the first conductive layer 3 is d1, the thickness of the insulating layer between the second semiconductor layer 5 and the first conductive layer is d2, the distance between the first semiconductor layer 2 and the second semiconductor layer 5 in the vertical substrate direction is d3, and the thickness of the second semiconductor layer 5 is d4. The sum of d2, d3, and d4 is substantially equal to the value of d1. Substantially equal means that the ratio of the absolute values of the two is between 0.8 and 1.2. By adjusting the distance between the first semiconductor layer 2, the second semiconductor layer 5, and the first conductive layer 3, it is ensured that the first conductive layer can be used as the top gate of the first semiconductor layer 2 and the second semiconductor layer 5 at the same time, which can reduce the manufacturing process and save costs.

[0204] For example, in some embodiments of the present disclosure, in combination with reference to FIGS. 26-28 and 31B, the display substrate 400 can further include a first conductive layer 3 located on the side of the first semiconductor layer 2 away from the substrate, and a second semiconductor layer 5 located on the side of the first conductive layer 3 away from the substrate. The display substrate 400 can further include a first insulating layer GI1 located between the first semiconductor layer 2 and the first conductive layer 3, and a second insulating layer GI2 located between the first conductive layer 3 and the second semiconductor layer 5. The display substrate further includes a second transistor T2 and a third transistor T3, the second transistor T2 includes a second gate G2 and a second active layer ACT2, and the third transistor T3 includes a third gate G3 and a third active layer ACT3, the second gate G2 and the third gate G3 are both located in the first conductive layer 3, the orthogonal projection of the second gate G2 on the substrate at least partially overlaps the orthogonal projection of the second active layer ACT2 on the substrate, and the orthogonal projection of the third gate G3 on the substrate at least partially overlaps the orthogonal projection of the third active layer ACT3 on the substrate.

[0205] For example, part of the first insulating layer GI1 collectively constitutes the gate insulating layer of the third transistor T3, and part of the second insulating layer GI2 constitutes the gate insulating layer of the second transistor T2.

[0206] For example, in some embodiments of the present disclosure, in combination with reference to FIGS. 28 and 31B, the second transistor T2 can be a single-gate structure, for example, the second transistor T2 can be a bottom-gate structure, wherein the gate G2 of the second transistor T2 and the gate G3 of the third transistor T3 can be located in the same conductive layer, for example, the first conductive layer 3. By designing the second transistor T2 as a bottom-gate structure and locating the gate G2 of the second transistor and the gate G3 of the third transistor in the same layer, the manufacturing process can be reduced and costs can be saved.

[0207] Exemplarily, in some embodiments of the present disclosure, in combination with reference to FIGS. 26, 29 and 30, the display substrate further comprises a second conductive layer 7 located on the side of the first conductive layer 3 away from the base substrate; at least a part of the first capacitor plate C1a of the storage capacitor C1 is located in the first conductive layer 3, and at least a part of the second capacitor plate C1b of the storage capacitor C1 is located in the second conductive layer 7.

[0208] Exemplarily, in some embodiments of the present disclosure, in combination with reference to FIGS. 26, 27 and 29, the display substrate 400 comprises a third sub-power signal line VDD3, the third sub-power signal line VDD3 and the second capacitor plate C1b are both located in the second conductive layer 7, and at least a part of the third sub-power signal line VDD3 and the second capacitor plate C1b are connected. The display substrate further comprises a second sub-power signal line VDD2 located in the light shielding layer 1, and the third sub-power signal line VDD3 is electrically connected with the second sub-power signal line VDD2 through the first via VH1.

[0209] Exemplarily, in some embodiments of the present disclosure, in combination with reference to FIGS. 26 and 30, the pixel driving circuit comprises a storage capacitor C1, the storage capacitor C1 comprises a first capacitor plate C1a and a second capacitor plate C1b; at least a part of the first capacitor plate C1a is located in the first conductive layer 3, the second capacitor plate C1b comprises a first sub-capacitor plate C1b1 and a second sub-capacitor plate C1b2, the first sub-capacitor plate C1b1 is located in the second conductive layer 7, and the second sub-capacitor plate C1b2 is located in the light shielding layer 1; the orthographic projection of each of the first sub-capacitor plate C1b1 and the second sub-capacitor plate C1b2 on the base substrate at least partially overlaps with the orthographic projection of the first capacitor plate C1a on the base substrate. By setting the storage capacitor in a sandwich structure, the capacity of the storage capacitor can be increased, the compensation capability for the driving transistor can be improved, which is conducive to improving the driving capability of the pixel driving circuit, and further improving the display effect of the display product.

[0210] Exemplarily, in some embodiments of the present disclosure, the second sub-capacitor plate C1b2 can adopt a widening design, further increasing the capacity of the storage capacitor, improving the compensation capability for the driving transistor, which is conducive to improving the driving capability of the pixel driving circuit, and further improving the display effect of the display product.

[0211] Exemplarily, at least some embodiments of the present disclosure also provide a display substrate, comprising: a substrate substrate; a plurality of sub-pixels on the substrate substrate, the plurality of sub-pixels are arranged in an array along a first direction and a second direction on the substrate substrate, at least one sub-pixel comprises a light emitting device and a pixel driving circuit for driving the light emitting device to emit light, the first direction and the second direction intersect; a plurality of signal lines on the substrate substrate, the plurality of signal lines comprise a first power supply signal line, the first power supply signal line is used to provide a first power supply signal to the pixel driving circuit, wherein the display substrate further comprises: a light shielding layer on the substrate substrate; a first semiconductor layer on a side of the light shielding layer away from the substrate substrate; and a first conductive layer on a side of the first semiconductor layer away from the substrate substrate; the first power supply signal line further comprises a first sub-power supply signal line and a second sub-power supply signal line in the light shielding layer, a main part of the first sub-power supply signal line extends along the first direction, the second sub-power supply signal line extends along the second direction, and the first sub-power supply signal line and the second sub-power supply signal line are electrically connected to each other and used to transmit the first power supply signal. By arranging the first sub-power supply signal line and the second sub-power supply signal line in the first power supply signal line in the light shielding layer, the first sub-power supply signal line and the second sub-power supply signal line can be used as a light shielding part and a power supply signal line to transmit the power supply signal at the same time, so that a conductive layer used as a power supply signal line and a planarization layer can be saved, thereby saving costs. The first sub-power supply signal line and the second sub-power supply signal line are arranged in a grid shape, which can shorten the transmission distance of the first power supply signal, thereby ensuring that the voltage drop of the power supply signal line in the light shielding part is small, which is beneficial to the transmission of the power supply signal.

[0212] Exemplarily, in some embodiments of the present disclosure, the light shielding part in the display substrate can not include the first power supply signal line, and is only used for shielding light to a local area in the pixel driving circuit of the display substrate. The first power supply signal line can be located in other film layers. For example, the display substrate can further comprise a fifth conductive layer, and a data signal line Data used for transmitting a data signal and a first power supply signal line VDD used for transmitting a first power supply signal can be arranged in the fifth conductive layer, that is, in some embodiments of the present disclosure, the pixel driving circuit can be compatible with the traditional light shielding layer design. By optimizing the connection mode of the gate of the second transistor in the pixel driving circuit, for example, the second transistor is designed as a single-gate structure, and the second gate of the second transistor is arranged in the third conductive layer, so that one conductive layer can be saved, and the corresponding metal mask can be reduced, thereby saving costs.

[0213] FIG. 32 is a plan view of a pixel driving circuit of a plurality of sub-pixels in a display substrate according to some embodiments of the present disclosure; FIG. 33 is a plan view of a light shielding layer in the pixel driving circuit according to FIG. 32; FIG. 34 is a plan view of a combined film layer of the light shielding layer and a first semiconductor layer in the pixel driving circuit according to FIG. 32; FIG. 35 is a plan view of a combined film layer of the light shielding layer, the first semiconductor layer, a first conductive layer, and a second semiconductor layer in the pixel driving circuit according to FIG. 32; FIG. 36 is a plan view of a combined film layer of the light shielding layer, the first semiconductor layer, the first conductive layer, the second semiconductor layer, and a third conductive layer in the pixel driving circuit according to FIG. 32; FIG. 37 is a plan view of the second conductive layer in the pixel driving circuit according to FIG. 32; FIG. 38 is a plan view of a combined film layer of the light shielding layer, the first semiconductor layer, the first conductive layer, the second semiconductor layer, the third conductive layer, and the second conductive layer in the pixel driving circuit according to FIG. 32; FIG. 39 is a partial cross-sectional view taken along line GG’ in FIG. 32; and FIG. 40 is a partial cross-sectional view taken along line HH’ in FIG. 32.

[0214] Exemplarily, at least some embodiments of the present disclosure also provide a display substrate, referring to FIG. 1, the display substrate comprises: a substrate 100; and a plurality of sub-pixels SP located on the substrate 100, the plurality of sub-pixels SP are arranged in an array along a first direction X and a second direction Y, at least one sub-pixel SP comprises a light emitting device L and a pixel driving circuit 200 for driving the light emitting device L to emit light, the first direction X and the second direction Y intersect.

[0215] Exemplarily, referring to FIG. 36, FIG. 39, and FIG. 40, the display substrate further comprises: a first semiconductor layer 2 located on the substrate 100; a first conductive layer 3 located on a side of the first semiconductor layer 2 away from the substrate 100; a second semiconductor layer 5 located on a side of the first conductive layer 3 away from the substrate 100; and a third conductive layer 4 located on a side of the second semiconductor layer 5 away from the substrate 100.

[0216] Exemplarily, referring to FIGS. 32-36, the pixel driving circuit of the substrate 400 includes a second transistor T2 and a third transistor T3, both of which can be in a top-gate structure, the second transistor T2 includes a second active layer ACT2 and a second gate G2, and the third transistor T3 includes a third active layer ACT3 and a third gate G3. The active layer ACT2 of the second transistor can include an oxide semiconductor material such as IGZO, and the active layer ACT3 of the third transistor can include a low-temperature polysilicon semiconductor material, i.e., the transistor types of the second transistor and the third transistor can be different, for example, the second transistor can be an oxide thin film transistor, and the third transistor can be a low-temperature polysilicon thin film transistor. The active layer of the second transistor and the active layer of the third transistor can be located in different layers, for example, the active layer ACT2 of the second transistor can be located in the second semiconductor layer 5, and the active layer ACT3 of the third transistor can be located in the first semiconductor layer 2. The second gate G2 of the second transistor and the third gate G3 of the third transistor can also be located in different layers, for example, the gate G2 of the second transistor can be located in the third conductive layer 4, and the gate G3 of the third transistor can be located in the first conductive layer 3.

[0217] Exemplarily, referring to FIGS. 34-36, the third active layer ACT3 in the third transistor includes a third channel region CH3, and a normal projection of the third gate G3 of the third transistor on the substrate substrate at least partially overlaps a normal projection of the third channel region CH3 on the substrate substrate. The second active layer ACT2 in the second transistor includes a second channel region CH2, and a normal projection of the second gate G2 of the second transistor on the substrate substrate at least partially overlaps a normal projection of the second channel region CH2 on the substrate substrate.

[0218] By designing the second transistor as a top-gate structure, at least one conductive layer can be reduced, for example, the fourth conductive layer is reduced, thereby saving costs, and at the same time, wiring space can be saved, which is beneficial to improve the aperture ratio and flatness of the display substrate.

[0219] Exemplarily, referring to FIG. 33, FIG. 35 and FIG. 40, the display substrate comprises the light shielding layer 1 located on the side of the first semiconductor layer 2 close to the substrate, the light shielding layer comprises a first light shielding part 101 and a second light shielding part 102, the first light shielding part 101 is configured to shield the third channel region CH3, and the second light shielding part 102 is configured to shield the second channel region CH2. That is, the light shielding layer 1 can be used to shield the second transistor and the third transistor at the same time, thereby improving the performance of the second transistor and the third transistor, and improving the display quality of the display substrate.

[0220] Exemplarily, referring to FIG. 33 and FIG. 38, the first light shielding part 101 comprises a first light shielding subpart 1011 extending along the first direction X and a second light shielding subpart 1012 extending along the second direction Y, the first light shielding subpart 1011 and the second light shielding subpart 1012 are connected so that the first light shielding part 101 forms an L-shaped structure; and / or, the second light shielding part 102 extends from a part of the first light shielding subpart 1011 along the second direction Y. That is, the light shielding part for shielding the second transistor and the third transistor can be continuous, which is conducive to improving the light shielding effect of the light shielding part on the second transistor and the third transistor.

[0221] Exemplarily, referring to FIG. 32 and FIG. 39, the display substrate further comprises a second conductive layer 7 located on the side of the third conductive layer 4 away from the substrate, and a fifth conductive layer 8 located on the side of the second conductive layer 7 away from the substrate. The data signal line Data for transmitting a data signal and the first power signal line VDD for transmitting a first power signal can be arranged in the fifth conductive layer 8. A plurality of data signal lines Data and a plurality of first power signal lines VDD are arranged in the first direction X, and each of the plurality of data signal lines Data and the plurality of first power signal lines VDD extends along the second direction Y. The light shielding part 1 in the display substrate can not include the first power signal line, and can only be used to shield a local area in the pixel driving circuit of the display substrate. That is, the design of the light shielding layer in at least some embodiments of the present disclosure can be compatible with the traditional light shielding layer design.

[0222] It should be noted that the display substrate 400 can further include an insulating layer between any two adjacent layers among the above-mentioned semiconductor layers and the above-mentioned conductive layers. As shown in FIG. 39, an insulating layer 50 can be arranged between the layer where the light shielding portion 1 is located and the second semiconductor layer 5, and an insulating layer 50 can be arranged between the second semiconductor layer 5 and the third conductive layer 4, for example, the insulating layer 50 can be a gate insulating layer. An insulating layer 61 can be arranged between the third conductive layer 4 and the second conductive layer 7, and an insulating layer 62 can be arranged between the second conductive layer 7 and the fifth conductive layer 8, for example, the insulating layers 61, 62 can be interlayer insulating layers. As shown in FIG. 40, an insulating layer IL1 can be arranged between the layer where the light shielding portion 1 is located and the first semiconductor layer 2, an insulating layer IL2 can be arranged between the first semiconductor layer 2 and the first conductive layer 3, an insulating layer IL3 can be arranged between the first conductive layer 3 and the third conductive layer 4, and an insulating layer IL4 can be arranged between the third conductive layer 4 and the fifth conductive layer 8. It should be noted that at least one of the above-mentioned insulating layers 50, 61, 62, IL1, IL2, IL3, IL4 can be a single-film layer structure, i.e., including only a single insulating film layer, or can be a multi-film layer structure, i.e., including 2 or more insulating film layers, and the structure of the insulating film layer is not particularly limited in the embodiments of the present disclosure.

[0223] Exemplarily, with reference to FIGS. 32 and 36, the pixel driving circuit of the display substrate 400 can further include a first transistor T1, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6 and a seventh transistor T7, and the active layer of each of the first transistor T1, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 can be located in the first semiconductor layer 2. The pixel circuit of the display substrate can further include a storage capacitor C1, and the storage capacitor C1 includes a first capacitor plate C1a and a second capacitor plate C1b, the first capacitor plate C1a can be located in the first conductive layer 3, and the second capacitor plate C1b can be located in the third conductive layer 4. The second capacitor plate C1b of the storage capacitor is electrically connected to one of the first power supply signal lines VDD through a third via hole VH3. One of the fifth gate and the fifth drain of the fifth transistor is electrically connected to the data signal line Data through a fourth via hole.

[0224] Exemplarily, the display substrate 400 comprises a first initialization signal line Vinit1, a reset signal line R1, a first scan signal line GL1, a second scan signal line GL2, a third scan signal line GL3, an emission control signal line EM and a second initialization signal line Vinit2. The reset signal line R1, the first scan signal line GL1, the second scan signal line GL2, the emission control signal line EM and the second initialization signal line Vinit2 are all located in the first conductive layer 3; the first initialization signal line Vinit1 and the third scan signal line GL3 are both located in the third conductive layer 4.

[0225] Exemplarily, with reference to FIGS. 32 and 37, the substrate 400 further includes a plurality of conductive transfer portions 70 in the second conductive layer 7, the plurality of conductive transfer portions 70 include a second conductive transfer portion 702 for electrically connecting one of the first source S1 and the first drain D1 of the first transistor T1 with the first initialization signal line Vinit1, the plurality of conductive transfer portions 70 further include a third conductive transfer portion 703 for electrically connecting one of the second source S2 and the second drain D2 of the second transistor T2 with the first node N1, the plurality of conductive transfer portions 70 further include a fourth conductive transfer portion 704 for respectively electrically connecting the other one of the second source S2 and the second drain D2 of the second transistor T2, one of the third source S3 and the third drain D3 of the third transistor T3, the other one of the first source S1 and the first drain D1 of the first transistor T1, and one of the sixth source S6 and the sixth drain D6 of the sixth transistor T6 with the third node N3, the plurality of conductive transfer portions 70 further include a fifth conductive transfer portion 705 for electrically connecting one of the fourth source S4 and the fourth drain D4 of the fourth transistor T4 with the data signal line Data, the plurality of conductive transfer portions 70 further include a sixth conductive transfer portion 706 for respectively electrically connecting the other one of the third source S3 and the third drain D3 of the third transistor T3, the other one of the fourth source S4 and the fourth drain D4 of the fourth transistor T4, and one of the fifth source S5 and the fifth drain D5 of the fifth transistor T5 with the second node N2, the plurality of conductive transfer portions 70 further include a seventh conductive transfer portion 707 for electrically connecting the other one of the fifth source S5 and the fifth drain D5 of the fifth transistor T5 with the first power signal line VDD, the plurality of conductive transfer portions 70 further include an eighth conductive transfer portion 708 for respectively electrically connecting the other one of the sixth source S6 and the sixth drain D6 of the sixth transistor T6 and one of the seventh source S7 and the seventh drain D7 of the seventh transistor T7 with the fourth node N4, and the plurality of conductive transfer portions 70 further include a ninth conductive transfer portion 709 for electrically connecting the other one of the seventh source S7 and the seventh drain D7 of the seventh transistor T7 with the second initialization signal line Vinit2.

[0226] Exemplarily, in some embodiments of the present disclosure, the light shielding part in the display substrate can not include the first power signal line, and is only used for shielding a local area in the pixel driving circuit, and the first power signal line can be located in other film layers. For example, the display substrate can include a fifth conductive layer, and a data signal line Data for transmitting a data signal and a first power signal line VDD for transmitting a first power signal can be both arranged in the fifth conductive layer, that is, in some embodiments of the present disclosure, a traditional light shielding layer design can be compatible. By optimizing the connection mode of the second gate of the second transistor in the pixel driving circuit, for example, adjusting the film layer where the double gate of the second transistor is located, setting the first sub-gate G21 of the second transistor in the first conductive layer 3, setting the second sub-gate G22 in the third conductive layer 4 or the fourth conductive layer 6, and the second capacitor plate C1b of the storage capacitor C1 can also be set in the third conductive layer 4 or the fourth conductive layer 6 accordingly, at least one conductive layer can be saved, the corresponding metal mask plate can be reduced, and the cost can be saved.

[0227] FIG. 41 is a plan view of a pixel driving circuit of a plurality of sub-pixels in a display substrate according to some other embodiments of the present disclosure; and FIG. 42 is a partial cross-sectional view taken along line II’ in FIG. 41.

[0228] Exemplarily, at least some embodiments of the present disclosure also provide a display substrate, referring to FIG. 1, wherein the display substrate includes: a substrate 100; and a plurality of sub-pixels SP arranged in an array along a first direction X and a second direction Y on the substrate 100, at least one sub-pixel SP including a light emitting device L and a pixel driving circuit 200 for driving the light emitting device L to emit light, the first direction X and the second direction Y intersecting.

[0229] Exemplarily, in some embodiments of the present disclosure, in combination with reference to FIGS. 41-42, the display substrate 400 further comprises: a first semiconductor layer 2 located on the base substrate; a first conductive layer 3 located on a side of the first semiconductor layer 2 away from the base substrate; a second semiconductor layer 5 located on a side of the first conductive layer 3 away from the base substrate; and a third conductive layer 4 located on a side of the second semiconductor layer 5 away from the base substrate. The pixel driving circuit comprises a second transistor T2 and a third transistor T3, the second transistor T2 has a double-gate structure, and the third transistor T3 has a top-gate structure; the third transistor T3 comprises a third active layer ACT3 and a third gate G3, the third active layer ACT3 is located in the first semiconductor layer 2, and the third gate G3 is located in the first conductive layer 3, the third active layer ACT3 comprises a third channel region CH3, and a projection of the third gate G3 on the base substrate at least partially overlaps a projection of the third channel region CH3 on the base substrate; and the second transistor T2 comprises a second active layer ACT2 and a second gate G2, the second gate G2 comprises a first sub-gate G21 and a second sub-gate G22, the first sub-gate G21 is located in the first conductive layer 3, and the second sub-gate G22 is located in the third conductive layer 4, a projection of the first sub-gate G21 on the base substrate at least partially overlaps a projection of the second active layer ACT2 on the base substrate, and a projection of the second sub-gate G22 on the base substrate at least partially overlaps a projection of the second active layer ACT2 on the base substrate.

[0230] It should be noted that, in some embodiments of the present disclosure, as shown in FIGS. 41 and 42, the display substrate 400 can not comprise a light-blocking portion, i.e., a separate light-blocking layer is not provided. In this case, a mask plate for forming the light-blocking layer is not needed, thereby reducing one mask process. In other embodiments of the present disclosure, the design shown in FIGS. 41 and 42 can also comprise a light-blocking portion, and can be compatible with the traditional light-blocking layer design.

[0231] Exemplarily, the display substrate 400 further comprises a second conductive layer 7 located on a side of the third conductive layer 4 away from the substrate substrate; and a fifth conductive layer 8 located on a side of the second conductive layer 7 away from the substrate substrate. Data signal lines Data for transmitting data signals and first power signal lines VDD for transmitting first power signals can be arranged in the fifth conductive layer 8. A plurality of the data signal lines Data and a plurality of the first power signal lines VDD are arranged at intervals in a first direction, and each of the plurality of the data signal lines Data and the plurality of the first power signal lines VDD extends along a second direction Y. The light shielding portion 1 in the display substrate can not include the first power signal lines, and is only used for light shielding of a local area in the pixel driving circuit of the display substrate. That is, the design of the light shielding layer in at least some embodiments of the present disclosure can be compatible with the traditional design of the light shielding layer.

[0232] Exemplarily, in some embodiments of the present disclosure, the second transistor can comprise a double-gate structure, and a second sub-gate G22 of the second transistor can also be arranged in the fourth conductive layer 6. For example, the display substrate further comprises: a first semiconductor layer 2 located on the substrate substrate; a first conductive layer 3 located on a side of the first semiconductor layer 2 away from the substrate substrate; a second semiconductor layer 5 located on a side of the first conductive layer 3 away from the substrate substrate; and a fourth conductive layer 6 located on a side of the second semiconductor layer 5 away from the substrate substrate. The pixel driving circuit comprises a second transistor T2 and a third transistor T3, the second transistor T2 has a double-gate structure, and the third transistor T3 has a top-gate structure; the third transistor T3 comprises a third active layer ACT3 and a third gate G3, the third active layer ACT3 is located in the first semiconductor layer 2, the third gate G3 is located in the first conductive layer 3, the third active layer ACT3 comprises a third channel region CH3, and a projection of the third gate G3 on the substrate substrate at least partially overlaps a projection of the third channel region CH3 on the substrate substrate; and the second transistor T2 comprises a second active layer ACT2 and a second gate G2, the second gate G2 comprises a first sub-gate G21 and a second sub-gate G22, the first sub-gate G21 is located in the first conductive layer 3, and the second sub-gate G22 is located in the fourth conductive layer 6, a projection of the first sub-gate G21 on the substrate substrate at least partially overlaps a projection of the second active layer ACT2 on the substrate substrate, and a projection of the second sub-gate G22 on the substrate substrate at least partially overlaps a projection of the second active layer ACT2 on the substrate substrate.

[0233] By setting the first sub-gate of the second transistor in the first conductive layer 3 and setting the second sub-gate of the second transistor in the third conductive layer or the fourth conductive layer, at least one conductive layer can be saved, the corresponding metal mask can be reduced, and cost can be saved. FIG. 43 is a structural schematic diagram of a display panel according to some embodiments of the present disclosure; and FIG. 44 is a structural schematic diagram of a display device according to some embodiments of the present disclosure.

[0234] Referring to FIG. 43, at least some embodiments of the present disclosure further provide a display panel 600. The display panel 600 can include the display substrate 400 as described above.

[0235] Referring to FIG. 44, at least some embodiments of the present disclosure further provide a display device 800. The display device 800 includes the display substrate 400 as described above or the display panel 600 as described above.

[0236] The display device can include any device or product having a display function. For example, the display device can be a smart phone, a mobile phone, an electronic book reader, a desktop PC, a laptop PC, a netbook PC, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital audio player, a mobile medical device, a camera, a wearable device (for example, a head-mounted device, electronic clothing, an electronic bracelet, an electronic necklace, electronic accessories, an electronic tattoo, or a smart watch), a television, or the like.

[0237] It should be understood that the display panel and the display device according to the embodiments of the present disclosure have all the features and advantages of the display substrate described above, and specific reference can be made to the description above, which will not be repeated here. Although some embodiments of the general inventive concept of the present disclosure have been shown and described, those of ordinary skill in the art will understand that changes can be made in these embodiments without departing from the principles and spirit of the general inventive concept, and the scope of the present disclosure is defined by the claims and their equivalents.

Claims

1. A display substrate, wherein, The display substrate comprises: a substrate substrate; a plurality of sub-pixels located on the substrate substrate, the plurality of sub-pixels being arranged in an array along a first direction and a second direction on the substrate substrate, at least one sub-pixel comprising a light-emitting device and a pixel driving circuit for driving the light-emitting device to emit light, the first direction and the second direction intersecting; a plurality of signal lines provided on the substrate substrate, the plurality of signal lines comprising a first power signal line for providing a first power signal to the pixel driving circuit, wherein the display substrate further comprises: a light-shielding layer located on the substrate substrate; a first semiconductor layer located on a side of the light-shielding layer away from the substrate substrate; and a first conductive layer located on a side of the first semiconductor layer away from the substrate substrate; the pixel driving circuit comprises a third transistor, the third transistor comprising a third active layer and a third gate electrode, the third active layer being located in the first semiconductor layer, the third gate electrode being located in the first conductive layer, the third active layer comprising a third channel region, and a projection of the third gate electrode on the substrate substrate at least partially overlaps with a projection of the third channel region on the substrate substrate; and the first power signal line comprises a first sub-power signal line located in the light-shielding layer, and a projection of the first sub-power signal line on the substrate substrate covers a projection of the third channel region on the substrate substrate. 2.The display substrate of claim 1, wherein, the first power signal line further comprises a second sub-power signal line located in the light-shielding layer, a main body portion of the first sub-power signal line extending along the first direction, and the second sub-power signal line extending along the second direction; and the display substrate comprises m first sub-power signal lines and n second sub-power signal lines located in the light-shielding layer, each of the m first sub-power signal lines intersecting with the n second sub-power signal lines, so that a portion of the first power signal line located in the light-shielding layer has a grid-like structure. 3.The display substrate of claim 1 or 2, wherein, the display substrate further comprises: a second conductive layer located on a side of the first conductive layer away from the substrate substrate; a planarization layer located on a side of the second conductive layer away from the substrate substrate; and a first electrode layer located on a side of the planarization layer away from the substrate substrate; the light-emitting element further comprises a first electrode located in the first electrode layer; and the planarization layer comprises a first surface facing the second conductive layer and a second surface facing the first electrode layer, the first surface contacting at least a portion of the second conductive layer, and the second surface contacting at least a portion of the first electrode layer. 4.The display substrate of claim 3, wherein, the pixel driving circuit further comprises a storage capacitor, the storage capacitor comprising a first capacitor plate and a second capacitor plate; a portion of the first capacitor plate overlapping with the third active layer is the third gate electrode; and a portion of the first power signal line located in the light-shielding layer is electrically connected to the second capacitor plate within a display area. 5.The display substrate of claim 3 or 4, wherein, the display substrate further comprises: a second conductive layer located on a side of the first conductive layer away from the substrate substrate; The third transistor further includes a third source and a third drain, and the third source and the third drain are located in the second conductive layer. The first power signal line further includes a third sub power signal line located in the second conductive layer. 6.The display substrate of claim 5, wherein, A projection of the third sub power signal line on the substrate substrate at least partially overlaps with a projection of the second sub power signal line on the substrate substrate. 7.The display substrate of claim 6, wherein, The display substrate includes k third sub power signal lines located in the second conductive layer; and The number n of the second sub power signal lines is more than twice the number k of the third sub power signal lines. 8.The display substrate of any one of claims 5-7, wherein, The third sub power signal line is electrically connected to the second sub power signal line through a first via. 9.The display substrate of claim 3 or 4, wherein, The display substrate further includes a second conductive layer located on a side of the first conductive layer away from the substrate substrate. The third transistor further includes a third source and a third drain, and the third source and the third drain are located in the second conductive layer. The first power signal line further includes a first conductive adapter located in the second conductive layer, and the first conductive adapter is electrically connected to the second sub power signal line through a first via. 10.The display substrate of claim 9, wherein, A projection of the first conductive adapter on the substrate substrate at least partially overlaps with a projection of the second sub power signal line on the substrate substrate. 11.The display substrate of any one of claims 1-10, wherein, The display substrate further includes a second semiconductor layer located on a side of the first semiconductor layer away from the substrate substrate. The pixel driving circuit further includes a second transistor, and the second transistor includes a second active layer located in the second semiconductor layer. The first semiconductor layer includes a single crystal silicon, amorphous silicon or polycrystalline silicon semiconductor material, and the second semiconductor layer includes an oxide semiconductor material. 12.The display substrate of claim 11, wherein, The second transistor includes a second gate, and the second gate includes a first sub gate and a second sub gate, a layer where the first sub gate is located is on a side of the second semiconductor layer close to the substrate substrate, a layer where the second sub gate is located is on a side of the second semiconductor layer away from the substrate substrate, a projection of the first sub gate on the substrate substrate at least partially overlaps with a projection of the second active layer on the substrate substrate, and a projection of the second sub gate on the substrate substrate at least partially overlaps with a projection of the second active layer on the substrate substrate. 13.The display substrate of claim 12, wherein, The display substrate further includes a third conductive layer located between the first semiconductor layer and the second semiconductor layer, a fourth conductive layer located on a side of the second semiconductor layer away from the substrate substrate, and The first sub gate is located in the third conductive layer, and the second sub gate is located in the fourth conductive layer. 14.The display substrate of claim 12, wherein, The display substrate further includes a third conductive layer located on a side of the second semiconductor layer away from the substrate substrate. The first sub gate is located in the first conductive layer, and the second sub gate is located in the third conductive layer. 15.The display substrate of claim 12, wherein, The display substrate further includes a fourth conductive layer located on a side of the second semiconductor layer away from the substrate substrate. The display substrate further includes a fourth conductive layer located on a side of the second semiconductor layer away from the substrate substrate. The first sub-gate is located in the first conductive layer, and the second sub-gate is located in the fourth conductive layer.

16. The display substrate of claim 13 or 14, wherein, At least part of the first capacitor plate is located in the first conductive layer, and at least part of the second capacitor plate is located in the third conductive layer.

17. The display substrate of claim 15, wherein, At least part of the first capacitor plate is located in the first conductive layer, and at least part of the second capacitor plate is located in the fourth conductive layer.

18. The display substrate of claim 16 or 17, wherein, Part of the third sub-power signal line is electrically connected with the second sub-power signal line through a first via, and another part of the third sub-power signal line is electrically connected with at least part of the second capacitor plate through a second via.

19. The display substrate of claim 16 or 17, wherein, Part of the first conductive adapter is electrically connected with the second sub-power signal line through a first via, and another part of the first conductive adapter is electrically connected with at least part of the second capacitor plate through a second via.

20. The display substrate of claim 11, wherein, The first conductive layer is located on the side of the second semiconductor layer away from the substrate. The second transistor and the third transistor both have a top gate structure; and The second transistor includes a second gate, the second gate and the third gate are both located in the first conductive layer, a projection of the second gate on the substrate at least partially overlaps a projection of the second active layer on the substrate, and a projection of the third gate on the substrate at least partially overlaps a projection of the third active layer on the substrate.

21. The display substrate of claim 20, wherein, The display substrate further includes a second conductive layer located on the side of the first conductive layer away from the substrate; and At least part of the first capacitor plate is located in the first conductive layer, and at least part of the second capacitor plate is located in the second conductive layer.

22. The display substrate of claim 21, wherein, The third sub-power signal line and at least part of the second capacitor plate both located in the second conductive layer are connected with each other, and the third sub-power signal line is electrically connected with the second sub-power signal line through a first via.

23. The display substrate of claim 21 or 22, wherein, The second capacitor plate includes a first sub-capacitor plate and a second sub-capacitor plate, the first sub-capacitor plate is located in the second conductive layer, and the second sub-capacitor plate is located in the light-shielding layer; and A projection of each of the first sub-capacitor plate and the second sub-capacitor plate on the substrate at least partially overlaps a projection of the first capacitor plate on the substrate.

24. The display substrate of any one of claims 1-23, wherein, The pixel driving circuit further includes a first transistor, a fourth transistor, a fifth transistor, a sixth transistor and a seventh transistor; the plurality of signal lines further include a first initialization signal line, a second initialization signal line, a reset signal line, a first scan signal line, a second scan signal line, a third scan signal line, a light-emitting control signal line and a data signal line, the first initialization signal line, the second initialization signal line, the reset signal line, the first scan signal line, the second scan signal line, the third scan signal line and the light-emitting control signal line extend along a first direction, and the data signal line extends along a second direction. The first transistor comprises a first gate, a first source and a first drain, the first gate is electrically connected with the reset signal line, one of the first source and the first drain is electrically connected with the first initialization signal line; The second gate is electrically connected with the third scan signal line; The fourth transistor comprises a fourth gate, a fourth source and a fourth drain, the fourth gate is electrically connected with the first scan signal line, one of the fourth source and the fourth drain is electrically connected with the data signal line; The fifth transistor comprises a fifth gate, a fifth source and a fifth drain, the fifth gate is electrically connected with the light-emitting control signal line, one of the fifth source and the fifth drain is electrically connected with the first power signal line; The sixth transistor comprises a sixth gate, a sixth source and a sixth drain, the sixth gate is electrically connected with the light-emitting control signal line; The seventh transistor comprises a seventh gate, a seventh source and a seventh drain, the seventh gate is electrically connected with the second scan signal line, one of the seventh source and the seventh drain is electrically connected with the second initialization signal line; And One of the second source and the second drain, the third gate and the first capacitor plate are electrically connected with each other, one of the third source and the third drain, the other of the fourth source and the fourth drain and the other of the fifth source and the fifth drain are electrically connected with each other, the other of the first source and the first drain, the other of the second source and the second drain, the other of the third source and the third drain and one of the sixth source and the sixth drain are electrically connected with each other, the other of the sixth source and the sixth drain and the other of the seventh source and the seventh drain are electrically connected with each other.

25. A display substrate, wherein, The display substrate comprises: a substrate substrate; a plurality of sub-pixels on the substrate substrate, the plurality of sub-pixels are arranged in an array along a first direction and a second direction on the substrate substrate, at least one sub-pixel comprises a light-emitting device and a pixel driving circuit for driving the light-emitting device to emit light, the first direction and the second direction intersect; and a plurality of signal lines provided on the substrate substrate, the plurality of signal lines comprise a first power signal line, the first power signal line is used to provide a first power signal to the pixel driving circuit, wherein the display substrate further comprises: a light shielding layer on the substrate substrate; a first semiconductor layer on a side of the light shielding layer away from the substrate substrate; and a first conductive layer on a side of the first semiconductor layer away from the substrate substrate; and the first power signal line further comprises a first sub-power signal line and a second sub-power signal line in the light shielding layer, a main part of the first sub-power signal line extends along the first direction, the second sub-power signal line extends along the second direction, the first sub-power signal line and the second sub-power signal line are electrically connected with each other, and are used to transmit the first power signal.

26. A display substrate, wherein, The display substrate comprises: a substrate substrate; and A plurality of sub-pixels are located on the substrate, the plurality of sub-pixels are arranged in an array along a first direction and a second direction on the substrate, at least one sub-pixel comprises a light emitting device and a pixel driving circuit for driving the light emitting device to emit light, the first direction and the second direction intersect; The display substrate further comprises: a first semiconductor layer located on the substrate; a first conductive layer located on a side of the first semiconductor layer away from the substrate; a second semiconductor layer located on a side of the first conductive layer away from the substrate; and a third conductive layer located on a side of the second semiconductor layer away from the substrate; The pixel driving circuit comprises a second transistor and a third transistor, and the second transistor and the third transistor both have a top gate structure; The third transistor comprises a third active layer and a third gate electrode, the third active layer is located in the first semiconductor layer, the third gate electrode is located in the first conductive layer, the third active layer comprises a third channel region, and a projection of the third gate electrode on the substrate at least partially overlaps a projection of the third channel region on the substrate; and The second transistor comprises a second active layer and a second gate electrode, the second active layer is located in the second semiconductor layer, the second gate electrode is located in the third conductive layer, the second active layer comprises a second channel region, and a projection of the second gate electrode on the substrate at least partially overlaps a projection of the second channel region on the substrate.

27. The display substrate of claim 26, wherein, The display substrate further comprises a light shielding layer located on a side of the first semiconductor layer close to the substrate; and The display substrate comprises a first light shielding part and a second light shielding part in the light shielding layer, a projection of the first light shielding part on the substrate at least partially overlaps a projection of the third channel region on the substrate, and a projection of the second light shielding part on the substrate at least partially overlaps a projection of the second channel region on the substrate. The first light shielding part comprises a first light shielding sub-part extending along the first direction and a second light shielding sub-part extending along the second direction, the first light shielding sub-part and the second light shielding sub-part are connected, so that the first light shielding part forms an L-shaped structure; and / or 28. The display substrate of claim 27, wherein, The second light shielding part extends from a part of the first light shielding sub-part along the second direction. The display substrate comprises:

29. A display substrate, wherein, a substrate; and a plurality of sub-pixels located on the substrate, the plurality of sub-pixels are arranged in an array along a first direction and a second direction on the substrate, at least one sub-pixel comprises a light emitting device and a pixel driving circuit for driving the light emitting device to emit light, the first direction and the second direction intersect; The display substrate further comprises: a first semiconductor layer located on the substrate; a first conductive layer located on a side of the first semiconductor layer away from the substrate; a second semiconductor layer located on a side of the first conductive layer away from the substrate; a third conductive layer located on a side of the second semiconductor layer away from the substrate; and a fourth conductive layer located on a side of the third conductive layer away from the substrate; ​ The pixel driving circuit comprises a second transistor and a third transistor, the second transistor has a double-gate structure, and the third transistor has a top-gate structure; The third transistor comprises a third active layer and a third gate electrode, the third active layer is located in the first semiconductor layer, the third gate electrode is located in the first conductive layer, the third active layer comprises a third channel region, and a projection of the third gate electrode on the substrate substrate at least partially overlaps a projection of the third channel region on the substrate substrate; and The second transistor comprises a second active layer and a second gate electrode, the second gate electrode comprises a first sub-gate electrode and a second sub-gate electrode, the first sub-gate electrode is located in the first conductive layer, the second sub-gate electrode is located in the third conductive layer or the fourth conductive layer, a projection of the first sub-gate electrode on the substrate substrate at least partially overlaps a projection of the second active layer on the substrate substrate, and a projection of the second sub-gate electrode on the substrate substrate at least partially overlaps a projection of the second active layer on the substrate substrate.

30. A display panel, comprising the display substrate according to any one of claims 1-29.

31. A display device, comprising the display substrate according to any one of claims 1-29 or the display panel according to claim 30.

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