Method and apparatus for precoded polar encoding and decoding related to procuct codes with dynamic frozen bits

Abstract

A method may include performing a first encoding by applying a precoding matrix P to information bits to obtain precoded bits. The method may also include performing a second encoding by applying a polar transform G (n) to the precoded bits to obtain a codeword. The method may further include performing a transmission through a wireless communication channel based at least in part on the first encoding and the second encoding. The precoding matrix P may indicate positions of one or more dynamic frozen bits within a sequence of bits input to the polar transform G (n) and one or more constraints for one or more respective dynamic frozen bits. The precoding matrix P is obtained by executing a Kronecker product of a first precoding matrix P 1 associated with a first component precoded polar code C1, and of a second precoding matrix P 2 associated with a second component precoded polar code C 2.

Description

TITLE:METHOD AND APPARATUS FOR PRECODED POLAR ENCODING AND DECODING RELATED TO PRODUCT CODES WITH DYNAMIC FROZEN BITSFIELD:

[0001] Some example embodiments may generally relate to mobile or wireless telecommunication systems, such as Long Term Evolution (LTE) or fifth generation (5G) new radio (NR) access technology, or 5G beyond, or sixth generation (6G) access technology, or other communications systems. For example, certain example embodiments may relate to apparatuses, systems, and / or methods for precoded polar encoding and decoding.BACKGROUND:

[0002] Examples of mobile or wireless telecommunication systems may include the Universal Mobile Telecommunications System (UMTS) Terrestrial Radio Access Network (UTRAN), Long Term Evolution (LTE) Evolved UTRAN (E-UTRAN), LTE-Advanced (LTE-A), MulteFire, LTE-A Pro, fifth generation (5G) radio access technology or new radio (NR) access technology and / or sixth generation (6G) radio access technology. 5G and 6G wireless systems refer to the next generation (NG) of radio systems and network architecture. 5G and 6G network technology is mostly based on NR technology, but the 5G / 6G (or NG) network can also build on E-UTRAN radio. It is estimated that NR may provide bitrates on the order of 10-20 Gbit / s or higher, and may support at least enhanced mobile broadband (eMBB) and ultra-reliable low-latency communication (URLLC) as well as massive machine-type communication (mMTC). NR is expected to deliver extreme broadband and ultra-robust, low-latency connectivity and massive networking to support the Internet of Things (loT).SUMMARY:

[0003] Some example embodiments may be directed to a method. The method may include performing a first encoding by applying a precoding matrix P to information bits to obtain precoded bits. The method may also include performing a second encoding by applying a polar transform ^^(^^)to the precoded bits to obtain a codeword. The method may further include performing a transmission through a wireless communication channel based at least in part on the first encoding and the second encoding. In certain example embodiments, the precoding matrix ^^ indicates positions of one or more dynamic frozen bits within a sequence of bits input to the polar transform ^^(^^), and one or more constraints for one or more respective dynamic frozen bits. In other example embodiments, the precoding matrix ^^ is obtained by executing a Kronecker product of a first precoding matrix ^^1associated with a first component precoded polar code ^^1, and of a second precoding matrix ^^2associated with a second component precoded polar code ^^2.

[0004] Other example embodiments may be directed to an apparatus. The apparatus may include at least one processor and at least one memory including computer program code. The at least one memory and the computer program code may be configured to, with the at least one processor, cause the apparatus at least to perform a first encoding by applying a precoding matrix ^^ to information bits to obtain precoded bits. The apparatus may also be caused to perform a second encoding by applying a polar transform ^^(^^)to the precoded bits to obtain a codeword. The apparatus may further be caused to perform a transmission through a wireless communication channel based at least in part on the first encoding and the second encoding. In certain exampleembodiments, the precoding matrix ^^ indicates positions of one or moredynamic frozen bits within a sequence of bits input to the polar transform ^^(^^), and one or more constraints for one or more respective dynamic frozen bits.In other example embodiments, the precoding matrix ^^ is obtained byexecuting a Kronecker product of a first precoding matrix ^^1associated with a first component precoded polar code ^^1, and of a second precoding matrix ^^2associated with a second component precoded polar code ^^2.

[0005] Other example embodiments may be directed to an apparatus. The apparatus may include means for performing a first encoding by applying a precoding matrix P to information bits to obtain precoded bits. The apparatus may also include means for performing a second encoding by applying a polar transform ^^(^^)to the precoded bits to obtain a codeword. The apparatus may further include means for performing a transmission through a wireless communication channel based at least in part on the first encoding and the second encoding. In certain example embodiments, the precoding matrix P indicates positions of one or more dynamic frozen bits within a sequence of bits input to the polar transform ^^(^^), and one or more constraints for one or more respective dynamic frozen bits. In other example embodiments, the precoding matrix P is obtained by executing a Kronecker product of a first precoding matrix ^^1associated with a first component precoded polar code ^^1, and of a second precoding matrix ^^2associated with a second component precoded polar code ^^2.

[0006] In accordance with other example embodiments, a non-transitory computer readable medium may be encoded with instructions that may, when executed in hardware, perform a method. The method may include performing a first encoding by applying a precoding matrix P to information bits to obtain precoded bits. The method may also include performing a second encoding by applying a polar transform ^^(^^)to the precoded bits to obtain a codeword. The method may further include performing a transmission through a wireless communication channel based at least in part on the first encoding and the second encoding. In certain example embodiments, the precoding matrix P indicates positions of one or more dynamic frozen bits within a sequence ofbits input to the polar transform ^^(^^), and one or more constraints for one or more respective dynamic frozen bits. In other example embodiments, the precoding matrix P is obtained by executing a Kronecker product of a first precoding matrix ^^1associated with a first component precoded polar code ^^1, and of a second precoding matrix ^^2associated with a second component precoded polar code ^^2.

[0007] Other example embodiments may be directed to a computer program product that performs a method. The method may include performing a first encoding by applying a precoding matrix P to information bits to obtain precoded bits. The method may also include performing a second encoding by applying a polar transform ^^(^^)to the precoded bits to obtain a codeword. The method may furtherperforming a transmission through a wireless communication channel based at least in part on the first encoding and the second encoding. In certain example embodiments, the precoding matrix P indicates positions of one or more dynamic frozen bits within a sequence of bits input to the polar transform ^^(^^), and one or more constraints for one or more respective dynamic frozen bits. In other example embodiments, the precoding matrix P is obtained by executing a Kronecker product of a first precoding matrix ^^1associated with a first component precoded polar code ^^1, and of a second precoding matrix ^^2associated with a second component precoded polar code ^^2.

[0008] Other example embodiments may be directed to an apparatus that may include circuitry configured to perform a first encoding by applying a precoding matrix P to information bits to obtain precoded bits. The apparatus may also include circuitry configured to perform a second encoding by applying a polar transform ^^(^^)to the precoded bits to obtain a codeword. The apparatus may further include circuitry configured to perform a transmission through a wireless communication channel based at least in parton the first encoding and the second encoding. In certain example embodiments, the precoding matrix P indicates positions of one or more dynamic frozen bits within a sequence of bits input to the polar transform ^^(^^), and one or more constraints for one or more respective dynamicIn other example embodiments, the precoding matrix P is obtained by executing a Kronecker product of a first precoding matrix ^^1associated with a first component precoded polar code ^^1, and of a second precoding matrix ^^2associated with a second component precoded polar code ^^2.

[0009] Some example embodiments may be directed to a method. The method may include iterating through performing a first decoding of received modulation symbols according to a first component precoded polar code ^^1and based on first constraints of the first component precoded polar code ^^1to obtain first decoded bit values. The method may also include iterating through performing a second decoding of the received modulation symbols according to a second component precoded polar code ^^2and based on second constraints of the second component precoded polar code ^^2to obtain second decoded bit values. In certain example embodiments, the iterating is performed until one of the following conditions is fulfilled: the first decoded bit values satisfy the first constraints or the second decoded bit values satisfy the second constraints, or a maximum number of iterations is reached. In other example embodiments, the first constraints may include one or more first constraints for one or more respective first dynamic frozen bits of the first component precoded polar code ^^1. In further example embodiments, the second constraints may include one or more second constraints for one or more respective second dynamic frozen bits of the second component precoded polar code ^^2.

[0010] Other example embodiments may be directed to an apparatus. The apparatus may include at least one processor and at least one memory including computer program code. The at least one memory and the computerprogram code may be configured to, with the at least one processor, cause the apparatus at least to iterate through performing a first decoding of received modulation symbols according to a first component precoded polar code ^^1and based on first constraints of the first component precoded polar code ^^1to obtain first decoded bit values. The apparatus may also be caused to iterate through performing a second decoding of the received modulation symbols according to a second component precoded polar code ^^2and based on second constraints of the second component precoded polar code ^^2to obtain second decoded bit values. In certain example embodiments, the iterating is performed until one of the following conditions is fulfilled: the first decoded bit values satisfy the first constraints or the second decoded bit values satisfy the second constraints, or a maximum number of iterations is reached. In other example embodiments, the first constraints may include one or more first constraints for one or more respective first dynamic frozen bits of the first component precoded polar code ^^1. In further example embodiments, the second constraints comprise one or more second constraints for one or more respective second dynamic frozen bits of the second component precoded polar code ^^2.

[0011] Other example embodiments may be directed to an apparatus. The apparatus may include means for iterating through performing a first decoding of received modulation symbols according to a first component precoded polar code ^^1and based on first constraints of the first component precoded polar code ^^1to obtain first decoded bit values. The apparatus may also include means for iterating through performing a second decoding of the received modulation symbols according to a second component precoded polar code ^^2and based on second constraints of the second component precoded polar code ^^2to obtain second decoded bit values. In certain example embodiments, the iterating is performed until one of the following conditions is fulfilled: the first decoded bit values satisfy the first constraints or thesecond decoded bit values satisfy the second constraints, or a maximum number of iterations is reached. In other example embodiments, the first constraints may include one or more first constraints for one or more respective first dynamic frozen bits of the first component precoded polar code ^^1. In further example embodiments, the second constraints may include one or more second constraints for one or more respective second dynamic frozen bits of the second component precoded polar code ^^2.

[0012] In accordance with other example embodiments, a non-transitory computer readable medium may be encoded with instructions that may, when executed in hardware, perform a method. The method may include iterating through performing a first decoding of received modulation symbols according to a first component precoded polar code ^^1and based on first constraints of the first component precoded polar code ^^1to obtain first decoded bit values. The method may also include iterating through performing a second decoding of the received modulation symbols according to a second component precoded polar code ^^2and based on second constraints of the second component precoded polar code ^^2to obtain second decoded bit values. In certain example embodiments, the iterating is performed until one of the following conditions is fulfilled: the first decoded bit values satisfy the first constraints or the second decoded bit values satisfy the second constraints, or a maximum number of iterations is reached. In other example the first constraints may include one or more first constraints for one or more respective first dynamic frozen bits of the first component precoded polar code ^^1. In further example embodiments, the second constraints may include one or more second constraints for one or more respective second dynamic frozen bits of the second component precoded polar code ^^2.

[0013] Other example embodiments may be directed to a computer program product that performs a method. The method may include iterating through performing a first decoding of received modulation symbols according to afirst component precoded polar code ^^1and based on first constraints of the first component precoded polar code ^^1to obtain first decoded bit values. The method may also include iterating through performing a second decoding of the received modulation symbols according to a second component precoded polar code ^^2and based on second constraints of the second component precoded polar code ^^2to obtain second decoded bit values. In certain example embodiments, the iterating is performed until one of the following conditions is fulfilled: the first decoded bit values satisfy the first constraints or the second decoded bit values satisfy the second constraints, or a maximum number of iterations is reached. In other example embodiments, the first constraints may include one or more first constraints for one or more respective first dynamic frozen bits of the first component precoded polar code ^^1. In further example embodiments, the second constraints may include one or more second constraints for one or more respective second dynamic frozen bits of the second component precoded polar code ^^2.

[0014] Other example embodiments may be directed to an apparatus that may include circuitry configured to iterate through performing a first decoding of received modulation symbols according to a first component precoded polar code ^^1and based on first constraints of the first component precoded polar code ^^1to obtain first decoded bit values. The apparatus may also include configured to iterate through performing a second decoding of the received modulation symbols according to a second component precoded polar code ^^2and based on second constraints of the second component precoded polar code ^^2to obtain second decoded bit values. In certain example embodiments, the iterating is performed until one of the following conditions is fulfilled: the first decoded bit values satisfy the first constraints or the second decoded bit values satisfy the second constraints, or a maximum number of iterations is reached. In other example embodiments, the first constraints may include one or more first constraints for one or morerespective first dynamic frozen bits of the first component precoded polar code ^^1. In further example embodiments, the second constraints may include one or more second constraints for one or more respective second dynamic frozen bits of the second component precoded polar code ^^2. BRIEF DESCRIPTION OF THE DRAWINGS:

[0015] For proper understanding of example embodiments, reference should be made to the accompanying drawings, wherein:

[0016] FIG.1 illustrates an example communication model.

[0017] FIG. 2 illustrates an example precoded polar encoder, according to certain example embodiments.

[0018] FIG. 3 illustrates an example flow diagram of a method, according to certain example embodiments.

[0019] FIG. 4 illustrates an example flow diagram of another method, according to certain example embodiments.

[0020] FIG. 5 illustrates an example two-dimensional array of modulation symbols, according to certain example embodiments.

[0021] FIG. 6 illustrates an example decoding iteration, according to certain example embodiments.

[0022] FIG.7 illustrates an example frame error rate (FER) vs. signal-to-noise ratio (SNR) graph under iterative decoding, according to certain example embodiments.

[0023] FIG. 8 illustrates an example of another FER vs. SNR graph under iterative decoding, according to certain example embodiments.

[0024] FIG. 9 illustrates an example of a further FER vs. SNR graph under iterative decoding, according to certain example embodiments.

[0025] FIG. 10 illustrates a table of an average number of iterations for convergence, according to certain example embodiments.

[0026] FIG. 11 illustrates a set of apparatuses, according to certain exampleembodiments. DETAILED DESCRIPTION:

[0027] It will be readily understood that the components of certain example embodiments, as generally described and illustrated in the figures herein, may be arranged and designed in a wide variety of different configurations. The following is a detailed description of some example embodiments of systems, methods, apparatuses, and computer program products for mapping of dynamic frozen bit constraints of product polar codes. In certain example embodiments, the mapping may be performed with pre-coded polar codes and their efficient decoding.

[0028] The features, structures, or characteristics of example embodiments described throughout this specification may be combined in any suitable manner in one or more example embodiments. For example, the usage of the phrases “certain embodiments,” “an example embodiment,” “some embodiments,” or other similar language, throughout this specification refers to the fact that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment. Thus, appearances of the phrases “in certain embodiments,” “an example embodiment,” “in some embodiments,” “in other embodiments,” or other similar language, throughout this specification do not necessarily refer to the same group of embodiments, and the described features, structures, or characteristics may be combined in any suitable manner in one or more example embodiments. Further, the terms “base station”, “cell”, “node”, “gNB”, “network” or other similar language throughout this specification may be used interchangeably.

[0029] As used herein, “at least one of the following: ” and “at least one of ” and similar wording, where the list of two or more elements are joined by “and” or “or,”mean at least any one of the elements, or at least any two or more of the elements, or at least all the elements.

[0030] Polar codes are linear error-correcting codes that rely on the polarization effect, which allows for sorting of bit positions of input ^^, called bit-channels, in order of reliability. They provide the first deterministic construction of capacity-achieving codes for binary memoryless symmetric (BMS) channels. As the codeword length goes towards infinity, the polarization phenomenon affects the reliability of bit-channels, which are either completely noisy or completely noiseless. Additionally, polar codes may be used for encoding control information.

[0031] Product codes and their modifications may be suitable for iterative decoding algorithms, which may serve as good solutions for low-latency applications. Product codes may usually be constructed with high-rate algebraic component codes, for which low-complexity soft-input soft-output (SISO) or algebraic decoders are available. For example, extended Hamming codes, which may be seen as Reed-Muller (RM) codes- may be selected as component codes in several wireless communication systems. Furthermore, product codes may be constructed as two- or three-dimensional arrays, where each dimension is encoded by a short algebraic code. Additionally, product codes with polar component codes may be provided to reduce the decoding latency compared to decoding an entire polar code of the same block length and rate. For high-rate examples, the bit error rate (BER) performance of the codes of certain example embodiments may be made comparable to product codes with Extended Bose-Chaudhuri-Hochquenghem (eBCH) component codes, which have very good minimum distance. However, the error- correcting performance of the schemes described herein may become non- competitive as the component code rates are slightly reduced due to the weak minimum distance of the polar component codes and the suboptimal computation of soft messages for iterative decoding.

[0032] Product codes based on RM component codes may be considered for cases where the component codes are extended Hamming and single parity- check (SPC) codes. Encoding of product codes may make use of the component codes’ systematic encoders, while decoding may be performed iteratively. An equivalent code may be obtained by using non-systematic encoders for the component codes. For example, an RM product code construction which directly maps the code structure onto the iterative Kronecker product of a 2x2 Hadamard kernel may be considered. A construction allowing interpretation of a polar code as a 2-dimensional product code may allow use of successive cancellation (SC) decoders row and column-wise to reduce the complexity / latency with respect to the case where SC decoding is performed over the larger polar code. Certain polar code decoding algorithms may be based on SC decoding algorithms, which may be inherently sequential. That is, the decoder may start with a decision for a bit and feed this decision back into the decoding process. SC may then proceed in this fashion until it decodes the last bit.

[0033] Existing product codes with polar components may exhibit weak performance even though they may significantly reduce latency. There may be several ingredients of this outcome. For example, one consideration may include the structural weakness of the product codes (e.g., small minimum distance). In this case, the performance may be weak especially at high signal- to-noise (SNR) values even under near maximum-likelihood (ML) decoding algorithms. Another consideration may be the sub-optimal decoding algorithm. Even when the structural weakness of a code is mitigated, such decoding method may limit the error-correcting performance of the resulting code. Thus, as described herein, certain example embodiments may address both aspects of the product codes with polar component codes.

[0034] FIG.1 illustrates an example communication model. As illustrated in FIG. 1, the transmitter may encompass blocks / source (S) of the informationpayload, which may be assumed to provide a message ^^ whose bits ^^^^can be modeled as independent and identically-distributed (IID) random variableswith Pr{^^^^ = 0} = Pr{^^^^ = 1} = 1 / 2. The encoder in FIG. 1 may map themessage ^^ onto a codeword ^^ through an invertible function ^^^^^^^^(∙) . Theencoded message is transmitted over the channel after suitable modulation.

[0035] As further illustrated in FIG.1, the channel is modeled as a probabilistic device which maps an input sequence x onto an output sequence y according to the conditional probability density function (pdf) ^^^^|^^(^^|^^). Further, thedecoder takes a decision as ^̂^ = ^^^^^^^^(y) based on the received message y,which allows obtaining ^̂^ by the function ^^^^−^^1^^(∙).

[0036] Certain example embodiments may relate to channel coding and may provide a new product code construction where component codes may be selected as polar codes with dynamic frozen bits. In particular, certain example embodiments may provide a new selection of the component codes including, for example, polar codes with dynamic frozen bits, where the minimum distance is significantly improved. According to certain example embodiments, component codes may be used with the best possible minimum distance for the provided parameters, which in turn may result in the best possible minimum distance for the resulting product code. In addition, the calculation of the soft message for the text iteration may be improved, which further improves the performance of the scheme. According to other example embodiments, the resulting code may be seen as a long polar code with dynamic frozen bits. This enables activation of a powerful non-iterative polar decoder (e.g., SCL decoding with large list size) for the resulting long polar code with dynamic frozen bits whenever the iterative decoder fails to converge to a valid codeword in row and column decoding after a pre-determined maximum number of iterations.

[0037] According to certain example embodiments, a 2-dimensional (N, K, D) product code C, where N, K, and D are the codeword length, the length of theinformation payload, and the minimum distance, respectively, may be obtained by iterating two binary linear block codes C1 and C2 in twodimensions with parameters (^^1, ^^1, ^^1) and (^^2, ^^2, ^^2) . Then, theparameters may have the following relationships: ^^ = ^^1^^2, ^^ = ^^1^^2 and^^ = ^^1^^2. In addition, the generator matrix ^^ = ^^1 ⊗ ^^2, where ^^^^ is thegenerator matrix of ^^^^and ⊗ is the Kronecker product.

[0038] In one example embodiment, let ^^2 ≜ [1 01 1]. With the value of K2known, consider the matrix ^^(^^) = ^^⊗2^^, where ^^⊗2^^is the ^^-fold Kronecker product of ^^⊗12with ^^2 = ^^2. In this example embodiment, ^^(^^)may be known as a polar transform matrix. First, all the codes may be obtained whose generator matrix is formed by choosing ^^ rows from ^^(^^). These selected row indices may be called the information indices and the set containing theindices may be denoted as ^^. For instance, an (^^, ^^) polar code may beobtained by storing the ^^ indices ^^ ∈ {1, 2, ... , ^^}, which provides the bestperformance under SC decoding (i.e., the most reliable ^^ bit channels arechosen). Another code generated from ^^(^^)is an ^^-th order RM code of length^^ = 2^^ and dimension ^^ ≜ ∑^^^^=0 (^^^^) with 0 ≤ ^^ ≤ ^^. In this case, the setay include the indices ^^ ∈ {1,2, … , ^^}, corresponding to the rows of ^^(^^)with the Hamming weight at least equal to 2^^−^^. In this example, ^^ may denote the ^^-bit message to be encoded. In both cases, encoding may be performed via applying polar transform after a suitable zero-padding to themessage, i.e., the codeword ^^ is obtained as ^^ = ^^^^(^^) where ^^ is a length-^^ binary vector with ^^ℱ = ^^ is the subvector of ^^ with the elements ofindices in set ℱ ≜ {1,2, … , ^^}\^^ and ^^^^ = ^^ . The set ^^ (hence ℱ ) isknown to the receiver.

[0039] As described herein, polar codes are introduced with dynamic frozen bits. According to certain example embodiments, a frozen bit ^^^^is dynamic ifits value is not always zero but depends on the preceding bits (^^1, ^^2, … , ^^^^−1).An alternative name for polar codes with dynamicpolar codes. In certain example embodiments, a ^^ × ^^ precoding matrix ^^ isdefined in addition to set ^^ , where ^^:,^^ = ^^^^ with ^^:,^^ being the matrixformed by the columns of ^^ with indices in ^^, and ^^^^ is the ^^ × ^^ identitymatrix. With these parameters, an example is defined by the following: 01 0 0 1 0 0 01 1 ö ÷

[0040] In thisencoded may be 6-bit long and denoted as ^^. The precoding may be performed as ^^ = ^^^^, whichis then followed by the polar transform as ^^ = ^^^^(^^). For instance, ^^ =(0, ^^1, ^^2, ^^3, ^^1 ⊕ ^^2, ^^4, ^^5, ^^6). This means ^^1 is a frozen bit whose valueis always set to ‘0’, and ^^5is a dynamic frozen bit, which is computed as a binary addition of ^^2 and ^^3 (i.e., dynamic frozen bit constraint is ^^5 = ^^2 ⊕^^3). Thus, a generator matrix for such codes is simply ^^ = ^^^^(^^). In certain example embodiments, the precoding matrix in the form of the above expression may be used at the receiver for SC-based decoding algorithms.

[0041] Certain example embodiments may use polar codes with dynamic frozen bits as the component codes for product code constructions instead of plain polar codes. For instance, in an example embodiment, component code parameters ^^1 = ^^2 = 32 and ^^1 = ^^2 = 21 , which results in an overallwith ^^ = 1024 and ^^ = 441. A plain (32,21) polar code mayhave a minimum distance of 4, which means the resulting product code has a minimum distance of 16. However, the minimum distance can be as large as 6for the given component code parameters, which would imply that theminimum distance of the resulting product code can be 36 instead of 16,which is the same as the minimum distance obtained by using eBCH component codes of the same parameters. In certain example embodiments, the (32,21) polar code with dynamic frozen bits may be used as thecomponent codes for a 2-dimensional product code, where the precoding matrices used for the precoded polar component codes are given by: ^^1 = ^^2to certain example embodiments. In particular, FIG. 2 illustrates the precoded polar encoder with K information bits v1… vkas input to the precoding matrix ^^ (e.g., ^^ = K x N matrix) for a polar code (K=4, N=8=23) to achieve a vector u of u1… uN, with frozen and dynamic frozen bits indicated by white circles. Apolar transform ^^(^^) = ^^⊗2^^is then applied to vector u after which vector y of y1… yNis transmitted to respective channels W.

[0043] The SCL soft-decision (SCL-SD) decoding algorithm may be an iterative decoding algorithm, where a posteriori probability (APP) Λ^^forcoded bit xi,where value ‘1’ or ‘0’ may be assigned to code bit xi, is approximated using Eq. (1) as follows after each row (column) decoding: Λ^^ = m(^^)in (^^^^) − m(^)in(^^^^) (1) ^^ =1 ^ ^^^^^^=0 In Eq. (1), ^^ℓdecoding for the codeword ^^(^^) ∈ ^^ after row (column) decoding, where ^^ denotes the final listof SCL

[0044] Following the decoding, extrinsic information may be extracted and provided to the column (row) decoding. One round of row and column decoding may correspond to a single decoding iteration (i.e., each row (column) decoding corresponds to a half decoding iteration), or each row (column) decoding corresponds to a single decoding iteration, and the decoding may be terminated after a maximum number of iterations is met or when the row (column) decoding provides the same hard decisions as the column (row) decoding if the hard decisions fully agree in row and column decoding of the same iteration. In the case where all codewords ^^(0), …, ^^(L - 1)have the same value for a given bit ^^^^, a large value may be

[0045] The iterative SCL soft-decision (SCL-SD) decoding algorithm may be implemented with a modification as shown in Eq. (2) below to further improve the error-correcting capability. For example, soft message Λ^^may be set as: ì+ mℓax(ℓ) ^^(ℓ)ℓ^^^^ ^^^^ = 0 ∀^^ ∈ ^^,message realization in the decoding process. As shown in Eq. (2), ^^ is the list ofcodewords x generated by SCL decoding of respective component precoded polar code, the max function is over all path metrics in the list ^^, ^^(^^)^^ ⊆ ^^includes the members ^^ of list ^^ such that their ^^-th element ^^^^is ^^, i.e., ^^^^= ^^, Λ^^represents the reliability of the estimation at the i-th position, ^^ℓis the metric for path ℓ, and ^^^^are the decoded bit values. Inall codewords have the same value for a given bit ^^^^, its magnitude or absolute value may be set to the largest path metric as per equation (2). All rows may be checked to determine whether all the rows are valid codewords by means of a parity check matrix of the component precoded polar code, or by checking the constraints imposed by precoding matrix P are satisfied. In some example embodiments, this type of checking may be performed via a parity check matrix.

[0046] A mapping between the dynamic frozen bit constraints of the component codes and the dynamic frozen bit constraints of the product code is proposed when the latter is represented as a single long polar code According to certain example embodiments, ^^1and ^^2may have generatormatrices ^^^^ = ^^1^^(^^^^) and ^^^^ = ^^2^^(^^^^), where ^^1and ^^2are chosen such that the set ofindices of the first 1s appearing in each row correspond to the information positions of ^^1and ^^2, respectively. Then, a generator matrix of the product code ^^ with the component codes ^^1and ^^2becomes^^ = (^^1 ⊗ ^^2)^^(^^^^+^^^^) . Then, ^^ = ^^1 ⊗ ^^2 defines the positions ofdynamic frozen bits and the constraints on them, which can be used in the end for using a decoding based on the entire product polar code whenever the iterative decoding for the component polar codes does not converge (i.e., does not yield a valid codeword). According to some example embodiments, all the column indices where they are all zeros correspond to frozen bits whose values are set to zero always. Additionally, the set of column indices of the first 1s appearing in each row correspond to the information positions. Further, these 1s are the only 1s in the respective columns. The indices of columns at which there are multiple 1s can be stored to provide the indices of dynamic frozenbits of the resulting product code when represented as a polar code (See Eq. (1) and the explanation for the corresponding mapping of the dynamic frozen bit constraints).

[0047] FIG. 3 illustrates an example flow diagram of a method, according to certain example embodiments. In an example embodiment, the method of FIG. 3 may be performed by a network entity, or a group of multiple network elements in a 3GPP system, such as 4G-LTE or 5G-NR or 6G. For instance, in an example embodiment, the method of FIG. 3 may be performed by an encoder of a user equipment (UE) or of a base station, similar to one of apparatuses 10 or 20 illustrated in FIG.12.

[0048] As illustrated in FIG. 3, the method may include, at 300, performing a first encoding by applying a precoding matrix ^^ to information bits to obtain precoded bits. The method may also include, at 305, performing a second encoding by applying a polar transform ^^(^^)to the precoded bits to obtain a codeword. The method may further include, at 310, performing a transmission through a wireless communication channel based at least in part on the first encoding and the second encoding. According to certain example embodiments, the precoding matrix P may indicate positions of one or more dynamic frozen bits within a sequence of bits input to the polar transform ^^(^^), and one or more constraints for one or more respective dynamic frozen bits. According to other example embodiments, the precoding matrix ^^ may be obtained by executing a Kronecker product of a first precoding matrix ^^1associated with a first component precoded polar code ^^1, and of a second precoding matrix ^^2associated with a second component precoded polar code ^^2. In certain example embodiments, the encoding may also be performed with row encoding (with ^^1and ^^(^^1)) followed by column encoding (with ^^2and ^^(^^2)), or vice-versa.

[0049] As an example of the method of FIG.2, ^^ may be defined as the vectorcomposed of the elements of information set ^^, where its elements are in ascending order (given A, ^^ is not needed). In this example, information bits may be represented as ^^ = [^^1, … , ^^^^] , and the precoded bits may berepresented as ^^ = [^^1, … , ^^^^] = ^^^^ , where ^^ is a precoding matrix ofdimensions ^^ × ^^ with the following properties: 1) ^^:,^^ = ^^^^ with ^^:,^^being the matrix formed by the columns of ^^ with indices in ^^ and ^^^^is the ^^ × ^^ identity matrix; and 2) Then, ^^^^,^^[^^] = 1 is the first non-zero element inrow ^^ for all ^^ = {1,2, … , ^^}. An example of P may be represented as:0 1 0 0 1 0 0 01 1 .Here, the firstencoding may berepresented as ^^ = ^^^^(^^) where ^^(^^) = ^^⊗^^2 , wherein ^^ = log2 ^^ and^^2 = [11

[0050] According to certain example embodiments, a constraint for a dynamic frozen bit may be defined as a constrained arithmetic relationship between the dynamic frozen bit and one or more information bits. For example, = [^^1, ^^2, … , ^^^^] = [0, ^^1, ^^2, ^^3, ^^1 ⊕ ^^2, ^^4, ^^5, ^^6] where the constraints ofor ^^2 ⊕ ^^3 ⊕ ^^5 =0. Additionally, the constraint for the dynamic frozen bit ^^5may be ^^5= ^^2 ⊕ ^^3 or ^^2 ⊕ ^^3 ⊕ ^^5 = 0.embodiments, the precoding matrix ^^ may further indicate positions of one or more frozen bits within the sequence of bits. For example, the frozen positions may be given by all the indices except for those of the indices in vector ^^ (i.e., ℱ ≜ {1,2, … , ^^}\^^ (or similarlyvector ^^ = [1,5] as before)). In another example, ℱ = {1,5}, where index 1corresponds to a (static) frozen bit, i.e. its value is always zero (^^1 = 0), andindex 5 corresponds to a dynamic frozen bit, i.e. its value depends onpreceding precoded bits ^^2 and ^^3 (^^5 = ^^2 ⊕ ^^3), or on the information bits^^1 and ^^2 (^^5 = ^^1 ⊕ ^^2).embodiments, the frozen bit constraints from ^^ may be obtained. For instance, if the column ^^[^^] is an all-zero column, then ^^^^[^^]is a frozen bit (i.e., ^^^^[^^] = 0). Otherwise, it is a dynamic frozen bit (i.e.,^^^^[^^] = ^^^^(^^1, ^^2, … , ^^^^−1)), where constraint ^^^^ may be found as follows: the^^ where ^^^^,^^[^^] = 1 is includedas sum in the constraint.

[0053] In some example embodiments, when ^^ = [1,5], the column ^^[1] =1 is all-zero, hence, ^^1 = 0. Additionally, the column ^^[2] = 5 may not bean all-zero column. There may be two rows with non-zero elements in column 5 of ^^, which are rows 1 and 2. The column index of first one appearing in row 1 is 2 (hence ^^2may be included in the constraint) and the column index of first one appearing in row 2 is 3 (hence ^^3is included in the constraint). Thus, it may be possible to obtain ^^^^[^^] = ^^^^(^^1, ^^2, … , ^^^^−1) as ^^5 = ^^2 ⊕^^3.

[0054] In certain example embodiments, a frozen bit may be a bit whose value is preliminarily known to a decoder. For example, ^^1=0.

[0055] FIG. 4 illustrates an example flow diagram of another method, according to certain example embodiments. In an example embodiment, the method of FIG.4 may be performed by a network entity, or a group of multiple network elements in a 3GPP system, such as 4G-LTE or 5G-NR or 6G. For instance, in an example embodiment, the method of FIG.4 may be performed by a decoder of a UE or of a base station, similar to one of apparatuses 10 or 20 illustrated in FIG.12.

[0056] As illustrated in FIG. 4, the method may include, at 400, iterating through performing a first decoding of received modulation symbols according to a first component precoded polar code ^^1and based on first constraints of the first component precoded polar code ^^1to obtain first decoded bit values. The method may also include, at 405, iterating through performing a second decoding of the received modulation symbols according to a second component precoded polar code ^^2and based on second constraints of the second component precoded polar code ^^2to obtain second decoded bit values. According to certain example embodiments, the iterating may be performed until one of the following conditions is fulfilled: the first decoded bit values satisfy the first constraints or the second decoded bit values satisfy the second constraints, or a maximum number of iterations is reached. According to other example embodiments, the first constraints may include one or more first constraints for one or more respective first dynamic frozen bits of the first component precoded polar code ^^1. According to further example embodiments, the second constraints may include one or more second constraints for one or more respective second dynamic frozen bits of the second component precoded polar code ^^2.

[0057] According to certain example embodiments, when the maximum number of iterations is reached, the method may further include decoding the received modulation symbols according to a product precoded polar code ^^ that is the product of the first component precoded polar code ^^1and of the second component precoded polar code ^^2and based on third constraints of the product precoded polar code C to obtain third decoded bit values. According to some example embodiments, the one or more first constraints for the one or more respective first dynamic frozen bits may be determined based on a first precoding matrix ^^1. According to other example embodiments, the one or more second constraints for the one or more respective second dynamic frozen bits may be determined based on a secondprecoding matrix ^^2. According to further example embodiments, the third constraints may include one or more third constraints for one or more respective third dynamic frozen bits of the product precoded polar code ^^, and the one or more third constraints for the one or more respective third dynamic frozen bits may be determined based on a precoding matrix P obtained by executing a Kronecker product of the first precoding matrices ^^1and of the second precoding matrix ^^2.

[0058] In certain example embodiments, the first precoded matrix ^^1may indicate positions of the one or more first dynamic frozen bits within a first sequence of bits input to a first polar transform ^^(^^1)of the first component precoded polar code ^^1, and the one or more first constraints for the one or more respective first dynamic frozen bits. In some example embodiments, the second precoded matrix ^^2may indicate positions of the one or more second dynamic frozen bits within a second sequence of bits input to a second polar transform ^^(^^2)of the second component precoded polar code ^^2, and the one or more second constraints for the one or more respective second dynamic frozen bits. In other example embodiments, the precoded matrix P may indicate positions of the one or more third dynamic frozen bits within a third sequence of bits input to a third polar transform ^^(^^^)of the product precoded polar code ^^, the one or more third constraints for the one or more respective third dynamic frozen bits.

[0059] According to certain example embodiments, a constraint for a dynamic frozen bit may be defined as a constrained arithmetic relationship between the dynamic frozen bit and one or more information bits. According to some example embodiments, the first precoded matrix ^^1may further indicate positions of one or more first frozen bits within the first sequence of bits, the second precoded matrix ^^2may further indicate positions of one or more second frozen bits within the second sequence of bits, the precoded matrix Pmay further indicate positions of one or more third frozen bits within the third sequence of bits. According to other example embodiments, a frozen bit may be a bit whose value is preliminary known to a decoder.

[0060] In certain example embodiments, the first and second decoded bit values may be estimated coded bit values. In some example embodiments, the method may further include determining the first decoded bit values based at least in part on first soft information generated after a first successive cancellation list decoding, and determining the second decoded bit values based at least in part on second soft information after a second successive cancellation list decoding.

[0061] According to certain example embodiments, the method may also include, in case that all codewords generated by the first successive cancellation list decoding have the same value for a given bit, setting the absolute value of first soft information of the given bit to a maximum path metric generated by the first successive cancellation list decoding, and sending first extrinsic information for the second decoding based on the first soft information. According to some example embodiments, the method may further include, in case that all codewords generated by the second successive cancellation list decoding have the same value for a given bit, setting the absolute value of the second soft information of the given bit to a maximum path metric generated by the second successive cancellation list decoding, and sending second extrinsic information for the first decoding based on the second soft information.

[0062] In certain example embodiments, the first soft information and the second soft information may be computed as:ì+ mℓax(ℓ) ^^ℓ^^^^ ^^^^ = 0 ∀^^(ℓ) ∈ ^^, wherein Λ^^of i-th element ^^^^ofx, ^^ℓ denotes a path metric for a decoding path ℓ yieldingcodeword ^^(ℓ),function is over all path metrics of paths in the list ^^, and ^^(^^)^^ ⊆ ^^ consists of the members ^^ of list ^^ such that their ^^-th element ^^^^ isto ^^.

[0063] For instance, in certain example embodiments, the received modulation symbols may include (^^1, ^^2, … , ^^^^1^^2). In this regard, FIG. 5 illustrates anexample two-arranging the received modulation symbols (^^1, ^^2, … , ^^^^1^^2), according to certain example embodiments. Asillustrated in FIG. 5, decoding may be performed at the receiver side. The received modulation symbols ( ^^1, ^^2, … , ^^^^1^^2) may be decoded usingdecoder 1. The row decoding may include decoding of the first row (^^1… ^^^^1), then decoding of the second row (^^^^1+1… ^^2^^1), etc, until the decoding of last row (^^^^1(^^2−1)+1… ^^^^1^^2).decoding mayan estimate of the transmitted codeword (^̂^1 … ^̂^^^1^^2). Then, if the estimated codeword (^̂^1 … ^̂^^^1^^2) (or correspondingbits ( ^̂^1 … ^̂^^^1^^2) = ( ^̂^1 … ^̂^^^1^^2)^^(^^)input to the polar transform ^^(^^1))terminates.decoding may be performed next using decoder 2. The column decoding may include decoding of the first column (^^1 … ^^^^1(^^2−1)+1), then decoding of thesecond column ( ^^2 … ^^^^1(^^2−1)+2 ), etc, until decoding of last column(^^^^1 … ^^^^1^^2). Additionally, similar to row decoding, column decoding maybe implemented in parallel. If the new estimated codeword (^̂^1 … ^̂^^^1^^2) afterthe column decoding (or corresponding bits (^̂^1 … ^̂^^^1^^2) = (^̂^1 … ^̂^^^1^^2)^^(^^)input to the polar transform ^^(^^2))the second constraint, then the decoding terminates. Else, ais started with a new row decoding.

[0064] FIG. 6 illustrates an example iteration, according to certain example embodiments. For instance, the iteration illustrated in FIG. 6 may take place at the receiver. At the receiver, each half iteration may include using SCL decoding for a component precoded polar code ^^^^, j=1,2, obtaining (^^) corresponding estimate of the coded bit values ^̂^^^for L different decoding hypothesis (the L-most probable codewords), and computing bit-wise soft- messages Λi. At each half iteration, various operations may be employed.

[0065] For example, as illustrated in FIG. 6, at 600, a vector of(^^1, ^^2, … , ^^^^1^^2 ) of received modulation symbols may be received by thedecoder of the receiver. At 605, the decoder takes the vectors of yi and then computes bit-wise channel LLRs ^^^^for the respective modulation symbol yito obtain (^^1, ^^2, … , ^^^^1^^2). Once the bit-wise channel LLRs are determined,it may be possible to move in one of two directions (e.g., left (row decoding) or right (column decoding)). For instance, moving toward the left side, a row decoder may be used, and the decoder may obtain the channel LLRs ^^^^as the input since the extrinsic message coming from column decoder is set to all- zeros initially. At 610, the receiver may implement SCL decoding for component pre-coded polar code ^^^^(e.g., row code), which generates a list ^^ with associated path metrics and respective codeword probabilities. At 615,the receiver may compute bit-wise soft values Λ^^ for each codeword bit ^̂^ iaccording to Eq. (2) where i = 1, 2, …, N1N2.instance, decoder ^^^^may take the LLRs ^^^^obtained from the channel, and outputs the soft values(Λ1, Λ2, … , Λ^^1^^2) according to Eq. (2).

[0066] After calculating the soft values, at 620, hard decisions may be madeas to the values of ^̂^^^ to obtain (^̂^1, ^̂^2, … , ^̂^^^1^^2) at 623, where the finalcodewords (^̂^1, ^̂^2, … , ^̂^^^1), (^̂^^^1+1, ^̂^^^1+2,… , ^̂^2^^1) … (^̂^^^1(^^2−1)+1, ^̂^^^1(^^2−1)+2, … ,be made as ^̂^^^based on Λ^^ , i.e., ^̂^^^ = 0 if Λ^^ ≥ 0 , else ^̂^^^ = 1 . At 625, the values ofto determine if they are valid codewords.blocks (^̂^1, ^̂^2, … , ^̂^^^1), (^̂^^^1+1, ^̂^^^1+2,… , ^̂^2^^1) … (^̂^^^1(^^2−1)+1, ^̂^^^1(^^2−1)+2, … ,be checked to bea valid codeword of the product code ^^ . If yes, at 627, the values of(^̂^1, ^̂^2, … , ^̂^^^1^^2) may be returned, and the decoding may be terminated.However, if it is determined that at least one of the so-obtained codewords is not valid, then the procedure may proceed to 630 where the receiver may check if a maximum number of iterations has been reached. If it is determined at 630 that the maximum number of iterations has been reached, the method may include decoding the received modulation symbols according to a product precoded polar code ^^ that is the product of the component precoded polar codes ^^^^and based on third constraints of the product precoded polar code ^^ to obtain third decoded bit values. On the other hand, if it is determined at 630 that the number of iterations has not been reached, the procedure may proceed to 617, where the bit-wise decoder inputs are subtracted from the soft values Λ^^determined at 615, leading to bit-wise extrinsic LLRs ^^^^^^. The resultant bit-wise extrinsic LLRs are then multiplied / weighted by α to obtain ^^(^^^^1 , ^^ ^^2 , … , ^^ ^^^^1^^2 ), where ^^ ∈ [0,1]. Then, the column decoder ^^^^′, j'≠j (e.g.,right side takes ^^(^^ + ^^^^ ^^ , ^^ ^^^^1 1 2 + ^^^^2 , … , ^^^^1^^2 + ^^^^^^1^^2) as the input. As illustrated inthe second half iterations performed on the right side of FIG. 6, similarly corresponding to operations 640 to 660. The description of operations 640 to660 are therefore similar to operations 610 to 630.

[0067] According to certain example embodiments, the one or more first constraints for the one or more respective first dynamic frozen bits may be determined based on a first precoding matrix ^^1. According to other example embodiments, the one or more second constraints for the one or more respective second dynamic frozen bits may be determined based on a second precoding matrix ^^2. According to further example embodiments, the third constraints may include one or more third constraints for one or more respective third dynamic frozen bits of the product precoded polar code ^^. In yet other example embodiments, the one or more third constraints for the one or more respective third dynamic frozen bits may be determined based on a precoding matrix ^^ obtained by executing a Kronecker product of the first precoding matrices ^^1and of the second precoding matrix ^^2.

[0068] In certain example embodiments, the first precoded matrix ^^1may indicate positions of the one or more first dynamic frozen bits within a first sequence of bits input to a first polar transform ^^(^^1)of the first component precoded polar code ^^1. In other examplethe first precoded matrix ^^1may indicate the one or more first constraints for the one or more respective first dynamic frozen bits. In further example embodiments, the second precoded matrix ^^2may indicate positions of the one or more second dynamic frozen bits within a second sequence of bits input to a second polar transform ^^(^^2)of the second component precoded polar code ^^2. In further examplethe second precoded matrix ^^2may indicate the one or more second constraints for the one or more respective second dynamic frozen bits. In additional example embodiments, the precoded matrix ^^ may indicate positions of the one or more third dynamic frozen bits within a third sequence of bits input to a third polar transform ^^(^^)of the product precoded polar code ^^. In additional example embodiments, the precoded matrix ^^may indicate the one or more third constraints for the one or more respective third dynamic frozen bits.

[0069] According to certain example embodiments, a constraint for a dynamic frozen bit is defined as a constrained arithmetic relationship between the dynamic frozen bit and one or more information bits.

[0070] In certain example embodiments, the first precoded matrix ^^1may further indicate positions of one or more first frozen bits within the first sequence of bits. Additionally, the second precoded matrix ^^2may indicate positions of one or more second frozen bits within the second sequence of bits. Further, the precoded matrix ^^ may include positions of one or more third frozen bits within the third sequence of bits. According to certain example embodiments, a frozen bit may be a bit whose value is preliminary known to a decoder.

[0071] According to other example embodiments, first soft information used by the first component precoded polar code ^^1and second soft information used by the second component precoded polar code ^^2are computed as per Eq. (2): +max(ℓ)= (ℓ)ì ℓ^^ℓ^^^^ ^^^^ 0 ∀^^ ∈ ^^generatedcode, max function is over all path metrics in the list ^^ and ^^(^^)^^ ⊆ ^^ consists of themembers ^^ of list ^^ such that its ^^-th element ^^ is^^^^ =

[0072] During the simulations, the list size may be set as ^^ = 16 for thecomponent code decoding and the scaling parameter may be set as ^^ = 0.5.FIG. 7 illustrates an example frame error rate (FER) vs. SNR graph underiterative decoding, according to certain example embodiments. In particular, FIG.7 illustrates FER vs. SNR for (1024,441) codes under iterative decoding where the component code uses SCL decoding with L = 16. As illustrated in FIG.7, the performance improves by 1.7 dB compared to the existing product code if the dynamic frozen bits are included in the component codes, where the gap tends to increase at lower FERs observing the slopes of the curves.

[0073] FIG. 8 illustrates an example of another FER vs. SNR graph under iterative decoding, according to certain example embodiments. In particular, FIG.8 illustrates FER vs. SNR for (1024,441) codes under iterative decoding where the soft message is computed as in Eq. (2). As a comparison, the row and column decoding are performed simultaneously. The soft messages are computed using Eq. (1) between iterations, and a large value (e.g., 20) is assigned as the amplitude in the case where all codewords ^^(0), …, ^^(L - 1)have the same value for a given bit ^^^^. Additionally, the iterative decoding is terminated either the row and column decoding provide the same decoded codewords at the end of the same iteration or the maximum number of iterations is reached. The maximum number of iterations are set to 10 and 20, respectively, as in the latter case, the row and column decoding can be parallelized, which amounts to the same worst-case latency. In both cases, thescaling factor is set as ^^ = 0.5. It can be observed that the iterative decodingimplemented via Eq. (2) outperforms the reference by 0.3 dB or more.

[0074] FIG. 9 illustrates an example of a further FER vs. SNR graph under iterative decoding, according to certain example embodiments. In particular, FIG.9 illustrates FER vs. SNR for (1024,441) codes under iterative decoding where SCL decoding with list size of 16 is used. As illustrated in FIG. 9, the results may be compared to the brief propagation (BP) decoding of 5G LDPC code. The maximum number of iterations may be set to 10 for the product code where the reference 5G LDPC code is decoded with maximum number of BP iterations of 10 and 20. It can be observed from FIG.9 that the proposedmethod outperforms 5G LDPC code by 1 dB if the maximum number of BP decoding iterations is set to 10 and by 0.25 dB if the maximum number of BP decoding iterations is set to 20.

[0075] FIG. 10 illustrates a table of an average number of iterations for convergence, according to certain example embodiments. In particular, FIG. 10 illustrates average number of iterations vs ^^^^ / ^^0(in dB) comparison for (1024,441) codes. As shown in FIG.10, the average number of iterations for the proposed product code of certain example embodiments is much smaller than that of the LDPC code, which means that there may be potential further decrease the latency compared to the 5G LDPC code. In addition, the proposed decoding implemented via Eq. (2) finishes decoding in lower number of average iterations as it does not perform row and column decoding simultaneously, which results in lower computations in addition to better performance.

[0076] FIG. 11 illustrates a set of apparatuses 10 and 20 according to certain example embodiments. In certain example embodiments, apparatuses 10 and 20 may be elements in a communications network or associated with such a network. For example, apparatus 10 may be a base station (gNB, eNB) or a user equipment or similar device comprising an encoder, and apparatus 20 may be a base station (gNB, eNB) or user equipment or similar device comprising a decoder.

[0077] In some example embodiments, apparatuses 10 and 20 may include one or more processors, one or more computer-readable storage medium (for example, memory, storage, or the like), one or more radio access components (for example, a modem, a transceiver, or the like), and / or a user interface. In some example embodiments, apparatuses 10 and 20 may be configured to operate using one or more radio access technologies, such as GSM, LTE, LTE- A, NR, 5G, 6G, WLAN, WiFi, NB-IoT, Bluetooth, NFC, MulteFire, and / or any other radio access technologies. It should be noted that one of ordinaryskill in the art would understand that apparatuses 10 and 20 may include components or features not shown in FIG.11.

[0078] As illustrated in the example of FIG. 11, apparatuses 10 and 20 may include or be coupled to a processors 12 and 22 for processing information and executing instructions or operations. Processors 12 and 22 may be any type of general or specific purpose processor. In fact, processors 12 and 22 may include one or more of general-purpose computers, special purpose computers, microprocessors, DSPs, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), and processors based on a multi-core processor architecture, as examples. While a single processors 12 and 22 is shown in FIG.11, multiple processors may be utilized according to other example embodiments. For example, it should be understood that, in certain example embodiments, apparatuses 10 and 20 may include two or more processors that may form a multiprocessor system (e.g., in this case processors 12 may represent a multiprocessor) that may support multiprocessing. According to certain example embodiments, the multiprocessor system may be tightly coupled or loosely coupled (e.g., to form a computer cluster).

[0079] Processors 12 and 22 may perform functions associated with the operation of apparatuses 10 and 20 including, as some examples, precoding of antenna gain / phase parameters, encoding and decoding of individual bits forming a communication message, formatting of information, and overall control of the apparatuses 10 and 20, including processes and examples illustrated in FIGs.1-10.

[0080] Apparatuses 10 and 20 may further include or be coupled to a memories 14 and 24 (internal or external), which may be respectively coupled to processors 12 and 24 for storing information and instructions that may be executed by processors 12 and 24. Memories 14 and 24 may be one or more memories and of any type suitable to the local application environment, andmay be implemented using any suitable volatile or nonvolatile data storage technology such as a semiconductor-based memory device, a magnetic memory device and system, an optical memory device and system, fixed memory, and / or removable memory. For example, memories 14 and 24 can be comprised of any combination of random access memory (RAM), read only memory (ROM), static storage such as a magnetic or optical disk, hard disk drive (HDD), or any other type of non-transitory machine or computer readable media. The instructions stored in memories 14 and 24 may include program instructions or computer program code that, when executed by processors 12 and 22, enable the apparatuses 10 and 20 to perform tasks as described herein.

[0081] In certain example embodiments, apparatuses 10 and 20 may further include or be coupled to (internal or external) a drive or port that is configured to accept and read an external computer readable storage medium, such as an optical disc, USB drive, flash drive, or any other storage medium. For example, the external computer readable storage medium may store a computer program or software for execution by processors 12 and 22 and / or apparatuses 10 and 20 to perform any of the methods and examples illustrated in FIGs.1-10.

[0082] In some example embodiments, apparatuses 10 and 20 may also include or be coupled to one or more antennas 15 and 25 for receiving a downlink signal and for transmitting via an UL from apparatuses 10 and 20. Apparatuses 10 and 20 may further include a transceivers 18 and 28 configured to transmit and receive information. The transceivers 18 and 28 may also include a radio interface (e.g., a modem) coupled to the antennas 15 and 25. The radio interface may correspond to a plurality of radio access technologies including one or more of GSM, LTE, LTE-A, 5G, NR, 6G, WLAN, NB-IoT, Bluetooth, BT-LE, NFC, RFID, UWB, and the like. The radio interface may include other components, such as filters, converters (forexample, digital-to-analog converters and the like), symbol demappers, signal shaping components, an Inverse Fast Fourier Transform (IFFT) module, and the like, to process symbols, such as OFDMA symbols, carried by a downlink or an UL.

[0083] For instance, transceivers 18 and 28 may be configured to modulate information on to a carrier waveform for transmission by the antennas 15 and 25 and demodulate information received via the antenna 15 and 25 for further processing by other elements of apparatuses 10 and 20. In other example embodiments, transceivers 18 and 28 may be capable of transmitting and receiving signals or data directly. Additionally or alternatively, in some example embodiments, apparatus 10 may include an input and / or output device (I / O device). In certain example embodiments, apparatuses 10 and 20 may further include a user interface, such as a graphical user interface or touchscreen.

[0084] In certain example embodiments, memories 14 and 34 store software modules that provide functionality when executed by processors 12 and 22. The modules may include, for example, an operating system that provides operating system functionality for apparatuses 10 and 20. The memory may also store one or more functional modules, such as an application or program, to provide additional functionality for apparatuses 10 and 20. The components of apparatuses 10 and 20 may be implemented in hardware, or as any suitable combination of hardware and software. According to certain example embodiments, apparatuses 10 and 20 may optionally be configured to communicate each other (in any combination) via a wireless or wired communication links 70 according to any radio access technology, such as NR.

[0085] According to certain example embodiments, processors 12 and 22 and memories 14 and 24 may be included in or may form a part of processing circuitry or control circuitry. In addition, in some example embodiments,transceivers 18 and 28 may be included in or may form a part of transceiving circuitry.

[0086] For instance, in certain example embodiments, apparatus 10 may be controlled by memory 14 and processor 12 to perform a first encoding by applying a precoding matrix P to information bits to obtain precoded bits. Apparatus 10 may also be controlled by memory 14 and processor 12 to perform a second encoding by applying a polar transform ^^(^^)to the precoded bits to obtain a codeword. Apparatus 10 may further be controlled by memory 14 and processor 12 to perform a transmission through a wireless communication channel based at least in part on the first encoding and the second encoding. In certain example embodiments, the precoding matrix P indicates positions of one or more dynamic frozen bits within a sequence of bits input to the polar transform ^^(^^), and one or more constraints for one or more respective dynamic frozen bits. In other example embodiments, the precoding matrix P may be obtained by executing a Kronecker product of a first precoding matrix ^^1associated with a first component precoded polar code ^^1, and of a second precoding matrix ^^2associated with a second component precoded polar code ^^2.

[0087] In other example embodiments, apparatus 20 may be controlled by memory 24 and processor 22 to iterate through performing a first decoding of received modulation symbols according to a first component precoded polar code ^^1and based on first constraints of the first component precoded polar code ^^1to obtain first decoded bit values. Apparatus 20 may also be controlled by memory 24 and processor 22 to iterate through performing a second decoding of the received modulation symbols according to a second component precoded polar code ^^2and based on second constraints of the second component precoded polar code ^^2to obtain second decoded bit values. In certain example embodiments the iterating may be performed untilone of the following conditions is fulfilled: the first decoded bit values satisfy the first constraints or the second decoded bit values satisfy the second constraints, or a maximum number of iterations is reached. In other example embodiments, the first constraints comprise one or more first constraints for one or more respective first dynamic frozen bits of the first component precoded polar code ^^1. In further example embodiments, the second constraints comprise one or more second constraints for one or more respective second dynamic frozen bits of the second component precoded polar code ^^2.

[0088] In some example embodiments, an apparatus (e.g., apparatus 10 and / or apparatus 20) may include means for performing a method, a process, or any of the variants discussed herein. Examples of the means may include one or more processors, memory, controllers, transmitters, receivers, and / or computer program code for causing the performance of the operations.

[0089] Certain example embodiments may be directed to an apparatus that includes means for performing any of the methods described herein including, for example, means for performing a first encoding by applying a precoding matrix P to information bits to obtain precoded bits. The apparatus may also include means for performing a second encoding by applying a polar transform ^^(^^)to the precoded bits to obtain a codeword. The apparatus maymeans for performing a transmission through a wireless communication channel based at least in part on the first encoding and the second encoding. In certain example embodiments, the precoding matrix P indicates positions of one or more dynamic frozen bits within a sequence of bits input to the polar transform ^^(^^), and one or more constraints for one or more respective dynamic frozen bits. In other example embodiments, the precoding matrix P is obtained by executing a Kronecker product of a first precoding matrix ^^1associated with a first component precoded polar code ^^1, and of a second precoding matrix ^^2associated with a second componentprecoded polar code ^^2.

[0090] Other example embodiments may be directed to an apparatus that includes means for performing any of the methods described herein including, for example, means for iterating through performing a first decoding of received modulation symbols according to a first component precoded polar code ^^1and based on first constraints of the first component precoded polar code ^^1to obtain first decoded bit values. The apparatus may also include means for iterating through performing a second decoding of the received modulation symbols according to a second component precoded polar code ^^2and based on second constraints of the second component precoded polar code ^^2to obtain second decoded bit values. In certain example embodiments, the iterating may be performed until one of the following conditions is fulfilled: the first decoded bit values satisfy the first constraints or the second decoded bit values satisfy the second constraints, or a maximum number of iterations is reached. In other example embodiments, the first constraints may include one or more first constraints for one or more respective first dynamic frozen bits of the first component precoded polar code ^^1. In further example embodiments, the second constraints may include one or more second constraints for one or more respective second dynamic frozen bits of the second component precoded polar code ^^2.

[0091] Certain example embodiments described herein provide several technical improvements, enhancements, and / or advantages in respect to mapping of dynamic frozen bit constraints of product codes with pre-coded polar codes and their efficient decoding. For instance, according to certain example embodiments, it may be possible to select polar codes with dynamic frozen bits where the minimum distance is significantly improved. For example, component codes with the best possible minimum distance for provided parameters may result in the best possible minimum distance for the resulting product code. Additionally, it may be possible to improve thecalculation of the soft message for the next iteration.

[0092] According to other example embodiments, it may be possible to maximize the minimum distance of the resulting product code while also having an efficient component code decoder, which uses, for instance, successive cancellation list (SCL) decoding. According to further example embodiments, it may also be possible to determine dynamic frozen bit positions and constraints from the dynamic frozen bit positions and the constraints of the component codes. Furthermore, it may be possible to modify the soft-message calculation for iterative decoding of the resulting product code.

[0093] According to other example embodiments, polar codes with dynamic frozen bits may improve performance vs. complexity trade-off due to better distance properties. As such, certain example embodiments may be relevant for high-throughput applications due to the use of such superior component codes in combination with the suitability of iterative decoding, which reduces the inherent latency of the polar code decoding. Furthermore, the mapping of certain example embodiments also enables polar code decoding of the code.

[0094] A computer program product may include one or more computer- executable components which, when the program is run, are configured to carry out some example embodiments. The one or more computer-executable components may be at least one software code or portions of it. Modifications and configurations required for implementing functionality of certain example embodiments may be performed as routine(s), which may be implemented as added or updated software routine(s). Software routine(s) may be downloaded into the apparatus.

[0095] As an example, software or a computer program code or portions of it may be in a source code form, object code form, or in some intermediate form, and it may be stored in some sort of carrier, distribution medium, or computer readable medium, which may be any entity or device capable of carrying theprogram. Such carriers may include a record medium, computer memory, read-only memory, photoelectrical and / or electrical carrier signal, telecommunications signal, and software distribution package, for example. Depending on the processing power needed, the computer program may be executed in a single electronic digital computer or it may be distributed amongst a number of computers. The computer readable medium or computer readable storage medium may be a non-transitory medium.

[0096] In other example embodiments, the functionality may be performed by hardware or circuitry included in an apparatus (e.g., apparatus 10 or apparatus 20), for example through the use of an application specific integrated circuit (ASIC), a programmable gate array (PGA), a field programmable gate array (FPGA), or any other combination of hardware and software. In yet another example embodiment, the functionality may be implemented as a signal, a non-tangible means that can be carried by an electromagnetic signal downloaded from the Internet or other network.

[0097] According to certain example embodiments, an apparatus, such as a node, device, or a corresponding component, may be configured as circuitry, a computer or a microprocessor, such as single-chip computer element, or as a chipset, including at least a memory for providing storage capacity used for arithmetic operation and an operation processor for executing the arithmetic operation.

[0098] One having ordinary skill in the art will readily understand that the disclosure as discussed above may be practiced with procedures in a different order, and / or with hardware elements in configurations which are different than those which are disclosed. Therefore, although the disclosure has been described based upon these example embodiments, it would be apparent to those of skill in the art that certain modifications, variations, and alternative constructions would be apparent, while remaining within the spirit and scope of example embodiments. Although the above embodiments refer to 5G NRand LTE technology, the above embodiments may also apply to any other present or future 3GPP technology, such as LTE-advanced, and / or fourth generation (4G) technology.

[0100] Partial Glossary:

[0101] 3GPP 3rd Generation Partnership Project

[0102] 5G 5th Generation

[0103] 5GCN 5G Core Network

[0104] 5GS 5G System

[0105] APP Aposteriori Probability

[0106] BS Base Station

[0107] DL Downlink

[0108] eNB Enhanced Node B

[0109] E-UTRAN Evolved UTRAN

[0110] FER Frame Error Rate

[0111] gNB 5G or Next Generation NodeB

[0112] LDPC Low-Density Parity-Check

[0113] LLR Log-Likelihood Ratio

[0114] LTE Long Term Evolution

[0115] ML Maximum Likelihood

[0116] NR New Radio

[0117] RM Reed-Muller

[0118] SC Successive Cancellation

[0119] SCL Successive Cancellation List

[0120] SISO Soft-Input Soft-Output

[0121] UE User Equipment

[0122] UL Uplink

Claims

WE CLAIM:

1. A method comprising: performing a first encoding by applying a precoding matrix P to information bits to obtain precoded bits; performing a second encoding by applying a polar transform ^^(^^)to the precoded bits to obtain a codeword; andperforming a transmission through a wireless communication channel based at least in part on the first encoding and the second encoding, wherein the precoding matrix P indicates: positions of one or more dynamic frozen bits within a sequence of bits input to the polar transform ^^(^^), and one or more constraints for one or more respective dynamic frozen bits, and wherein the precoding matrix P is obtained by executing a Kronecker product of a first precoding matrix ^^1associated with a first component precoded polar code ^^1, and of a second precoding matrix ^^2associated with a second component precoded polar code ^^2.

2. The method according to claim 1, wherein a constraint for a dynamic frozen bit is defined as a constrained arithmetic relationship between the dynamic frozen bit and one or more information bits.

3. The method according to claims 1 or 2, wherein the precoding matrix P further indicates positions of one or more frozen bits within the sequence of bits.

4. The method according to claim 3, wherein a frozen bit is a bit whose value is preliminarily known to a decoder.

5. A method, comprising: iterating through: performing a first decoding of received modulation symbols according to a first component precoded polar code ^^1and based on first constraints of the first component precoded polar code ^^1to obtain first decoded bit values; and next performing a second decoding of the received modulation symbols according to a second component precoded polar code ^^2and based on second constraints of the second component precoded polar code ^^2to obtain second decoded bit values, wherein the iterating is performed until one of the following conditions is fulfilled: the first decoded bit values satisfy the first constraints or the second decoded bit values satisfy the second constraints, or a maximum number of iterations is reached, wherein the first constraints comprise one or more first constraints for one or more respective first dynamic frozen bits of the first component precoded polar code ^^1, and wherein the second constraints comprise one or more second constraints for one or more respective second dynamic frozen bits of the second component precoded polar code ^^2.

6. The method according to claim 5, wherein, when the maximum number of iterations is reached, the method further comprises: decoding the received modulation symbols according to a product precoded polar code ^^ that is the product of the first component precoded polar code ^^1and of the second component precoded polar code ^^2and basedon third constraints of the product precoded polar code ^^ to obtain thirddecoded bit values.

7. The method according to claim 6, wherein the one or more first constraints for the one or more respective first dynamic frozen bits are determined based on a first precoding matrix ^^1, wherein the one or more second constraints for the one or more respective second dynamic frozen bits are determined based on a second precoding matrix ^^2, wherein the third constraints comprise one or more third constraints for one or more respective third dynamic frozen bits of the product precoded polar code ^^, and wherein the one or more third constraints for the one or more respective third dynamic frozen bits are determined based on a precoding matrix P obtained by executing a Kronecker product of the first precoding matrices ^^1and of the second precoding matrix ^^2.

8. The method according to claim 7, wherein the first precoded matrix ^^1indicates: positions of the one or more first dynamic frozen bits within a first sequence of bits input to a first polar transform ^^(^^^1)of the first component precoded polar code ^^1, and the one or more first constraints for the one or more respective first dynamic frozen bits, wherein the second precoded matrix ^^2indicates: positions of the one or more second dynamic frozen bits within a second sequence of bits input to a second polar transform ^^(^^2)of the second component precoded polar code ^^2, andthe one or more second constraints for the one or morerespective second dynamic frozen bits, and wherein the precoded matrix P indicates: positions of the one or more third dynamic frozen bits within a third sequence of bits input to a third polar transform ^^(^^)of the product precoded polar code ^^, and the one or more third constraints for the one or more respective third dynamic frozen bits.

9. The method according to any of claims 5-8, wherein a constraint for a dynamic frozen bit is defined as a constrained arithmetic relationship between the dynamic frozen bit and one or more information bits.

10. The method according to claim 8 or 9, wherein the first precoded matrix ^^1further indicates positions of one or more first frozen bits within the first sequence of bits, wherein the second precoded matrix ^^2further indicates positions of one or more second frozen bits within the second sequence of bits, and wherein the precoded matrix P further indicates positions of one or more third frozen bits within the third sequence of bits.

11. The method according to claim 10, wherein a frozen bit is a bit whose value is preliminary known to a decoder.

12. The method according to any of claims 5-11, wherein the first and second decoded bit values are estimated coded bit values, and wherein the method further comprises: determining the first decoded bit values based at least in part onfirst soft information generated after a first successive cancellation list decoding; and determining the second decoded bit values based at least in part on second soft information after a second successive cancellation list decoding.

13. The method according to claim 12, further comprising: in case that all codewords generated by the first successive cancellation list decoding have the same value for a given bit, setting the absolute value of the first soft information of the given bit to a maximum path metric generated by the first successive cancellation list decoding, and sending first extrinsic information for the second decoding based on the first soft information; and in case that all codewords generated by the second successive cancellation list decoding have the same value for a given bit, setting the absolute value of the second soft information of the given bit to a maximum path metric generated by the second successive cancellation list decoding, and sending second extrinsic information for the first decoding based on the second soft information.

14. The method according to claim 13, wherein the first soft information and the second soft information are computed as: (ℓ) ì+ mℓax^^ℓ^^^^ ^^^^ = 0 ∀^^(ℓ) ∈ ^^, wherein Λof i-th element^^Iofx, ^^ℓ denotes a path metric for a decoding path ℓ yieldingcodeword ^^(ℓ), max function is over all path metrics of paths in the list ^^, and ^^(^^)^^ ⊆ ^^ consists of the members ^^ of list ^^ such that their ^^-th element ^^^^ isto ^^.

15. An apparatus, comprising: at least one processor; and at least one memory comprising computer program code, wherein the at least one memory and the computer program code are configured to, with the at least one processor, cause the apparatus at least to perform a first encoding by applying a precoding matrix P to information bits to obtain precoded bits; perform a second encoding by applying a polar transform ^^(^^)to the precoded bits to obtain a codeword; and perform a transmission through a wireless communication channel based at least in part on the first encoding and the second encoding, wherein the precoding matrix P indicates: positions of one or more dynamic frozen bits within a sequence of bits input to the polar transform ^^(^^), and one or more constraints for one or more respective dynamic frozen bits, and wherein the precoding matrix P is obtained by executing a Kronecker product of a first precoding matrix ^^1associated with a first component precoded polar code ^^1, and of a second precoding matrix ^^2associated with a second component precoded polar code ^^2.

16. The apparatus according to claim 15, wherein a constraint for a dynamic frozen bit is defined as a constrained arithmetic relationship between the dynamic frozen bit and one or more information bits.

17. The apparatus according to claims 15 or 16, wherein the precoding matrix P further indicates positions of one or more frozen bits within the sequence of bits.

18. The apparatus according to claim 17, wherein a frozen bit is a bit whose value is preliminarily known to a decoder.

19. An apparatus, comprising: at least one processor; and at least one memory comprising computer program code, wherein the at least one memory and the computer program code are configured to, with the at least one processor, cause the apparatus at least to iterate through: performing a first decoding of received modulation symbols according to a first component precoded polar code ^^1and based on first constraints of the first component precoded polar code ^^1to obtain first decoded bit values; and nextperforming a second decoding of the received modulation symbols according to a second component precoded polar code ^^2and based on second constraints of the second component precoded polar code ^^2to obtain second decoded bit values wherein the iterating is performed until one of the following conditions is fulfilled: the first decoded bit values satisfy the first constraints or the second decoded bit values satisfy the second constraints, or a maximum number of iterations is reached, wherein the first constraints comprise one or more first constraints for one or more respective first dynamic frozen bits of the first componentprecoded polar code ^^1, and wherein the second constraints comprise one or more second constraints for one or more respective second dynamic frozen bits of the second component precoded polar code ^^2.

20. The apparatus according to claim 19, wherein, when the maximum number of iterations is reached, the at least one memory and the computer program code are configured to, with the at least one processor, further cause the apparatus at least to: decode the received modulation symbols according to a product precoded polar code ^^ that is the product of the first component precoded polar code ^^1and of the second component precoded polar code ^^2and basedon third constraints of the product precoded polar code ^^ to obtain thirddecoded bit values.

21. The apparatus according to claim 20, wherein the one or more first constraints for the one or more respective first dynamic frozen bits are determined based on a first precoding matrix ^^1, wherein the one or more second constraints for the one or more respective second dynamic frozen bits are determined based on a second precoding matrix ^^2, wherein the third constraints comprise one or more third constraints for one or more respective third dynamic frozen bits of the product precoded polar code ^^, and wherein the one or more third constraints for the one or more respective third dynamic frozen bits are determined based on a precoding matrix P obtained by executing a Kronecker product of the first precoding matrices ^^1and of the second precoding matrix ^^2.

22. The apparatus according to claim 21, wherein the first precoded matrix ^^1indicates, positions of the one or more first dynamic frozen bits within a first sequence of bits input to a first polar transform ^^(^^^1)of the first component precoded polar code ^^1, and the one or more first constraints for the one or more respective first dynamic frozen bits, wherein the second precoded matrix ^^2indicates, positions of the one or more second dynamic frozen bits within a second sequence of bits input to a second polar transform ^^(^^^2)of the second component precoded polar code ^^2, and the one or more second constraints for the one or more respective second dynamic frozen bits, and wherein the precoded matrix P indicates positions of the one or more third dynamic frozen bits within a third sequence of bits input to a third polar transform ^^(^^)of the product precoded polar code ^^, and the one or more third constraints for the one or more respective third dynamic frozen bits.

23. The apparatus according to any of claims 19-22, wherein a constraint for a dynamic frozen bit is defined as a constrained arithmetic relationship between the dynamic frozen bit and one or more information bits.

24. The apparatus according to claim 22 or 23, wherein the first precoded matrix ^^1further indicates positions of one or more first frozen bits within the first sequence of bits,wherein the second precoded matrix ^^2further indicates positions of one or more second frozen bits within the second sequence of bits, and wherein the precoded matrix P further indicates positions of one or more third frozen bits within the third sequence of bits.

25. The apparatus according to claim 22, wherein a frozen bit is a bit whose value is preliminary known to a decoder.

26. The apparatus according to any of claims 19-25, wherein the first and second decoded bit values are estimated coded bit values, and wherein the at least one memory and the computer program code are further configured to, with the at least one processor, cause the apparatus at least to: determine the first decoded bit values based at least in part on first soft information generated after a first successive cancellation list decoding; and determine the second decoded bit values based at least in part on second soft information after a second successive cancellation list decoding.

27. The apparatus according to claim 26, wherein the at least one memory and the computer program code are further configured to, with the at least one processor, cause the apparatus at least to: in case that all codewords generated by the first successive cancellation list decoding have the same value for a given bit, set the absolute value of the first soft information of the given bit to a maximum path metric generated by the first successive cancellation list decoding, and send first extrinsic information for the second decoding based on the first soft information; and in case that all codewords generated by the second successivecancellation list decoding have the same value for a given bit, set the absolute value of the second soft information of the given bit to a maximum path metric generated by the second successive cancellation list decoding, and send second extrinsic information for the first decoding based on the second soft information.

28. The apparatus according to claim 27, wherein the first soft information and the second soft information are computed as: (ℓ)(ℓì+ mℓax^^ℓ^^^^ ^^^^ = 0 ∀^^ ) ∈ ^^, wherein Λ^^of i-th element ^^^^ofx, ^^ℓ denotes a path metric for a decoding path ℓ yieldingcodeword ^^(ℓ), max function is over all path metrics of paths in the list ^^, and ^^(^^)^^ ⊆ ^^ consists of the members ^^ of list ^^ such that their ^^-th element ^^^^ isto ^^.

29. An apparatus, comprising: means for performing a first encoding by applying a precoding matrix P to information bits to obtain precoded bits; means for performing a second encoding by applying a polar transform ^^(^^)to the precoded bits to obtain a codeword; and means for performing a transmission through a wireless communication channel based at least in part on the first encoding and the second encoding, wherein the precoding matrix P indicates:positions of one or more dynamic frozen bits within a sequence of bits input to the polar transform ^^(^^), and one or more constraints for one or more respective dynamic frozen bits, and wherein the precoding matrix P is obtained by executing a Kronecker product of a first precoding matrix ^^1associated with a first component precoded polar code ^^1, and of a second precoding matrix ^^2associated with a second component precoded polar code ^^2.

30. The apparatus according to claim 29, wherein a constraint for a dynamic frozen bit is defined as a constrained arithmetic relationship between the dynamic frozen bit and one or more information bits.

31. The apparatus according to claims 29 or 30, wherein the precoding matrix P further indicates positions of one or more frozen bits within the sequence of bits.

32. The apparatus according to claim 31, wherein a frozen bit is a bit whose value is preliminarily known to a decoder.

33. An apparatus, comprising: means for iterating through: performing a first decoding of received modulation symbols according to a first component precoded polar code ^^1and based on first constraints of the first component precoded polar code ^^1to obtain first decoded bit values; and next performing a second decoding of the received modulation symbols according to a second component precoded polar code ^^2and based on second constraints of the second component precoded polar code ^^2toobtain second decoded bit values, wherein the iterating is performed until one of the following conditions is fulfilled: the first decoded bit values satisfy the first constraints or the second decoded bit values satisfy the second constraints, or a maximum number of iterations is reached, wherein the first constraints comprise one or more first constraints for one or more respective first dynamic frozen bits of the first component precoded polar code ^^1and wherein the second constraints comprise one or more second constraints for one or more respective second dynamic frozen bits of the second component precoded polar code ^^2.

34. The apparatus according to claim 33, wherein, when the maximum number of iterations is reached, the apparatus further comprises: means for decoding the received modulation symbols according to aproduct precoded polar code ^^ that is the product of the first componentprecoded polar code ^^1and of the second component precoded polar code ^^2and based on third constraints of the product precoded polar code ^^ to obtain third decoded bit values.

35. The apparatus according to claim 34, wherein the one or more first constraints for the one or more respective first dynamic frozen bits are determined based on a first precoding matrix ^^1, wherein the one or more second constraints for the one or more respective second dynamic frozen bits are determined based on a second precoding matrix ^^2, wherein the third constraints comprise one or more third constraints for one or more respective third dynamic frozen bits of the product precoded polarcode ^^, and wherein the one or more third constraints for the one or more respective third dynamic frozen bits are determined based on a precoding matrix P obtained by executing a Kronecker product of the first precoding matrices ^^1and of the second precoding matrix ^^2.

36. The apparatus according to claim 35, wherein the first precoded matrix ^^1indicates, positions of the one or more first dynamic frozen bits within a first sequence of bits input to a first polar transform ^^(^^^1)of the first component precoded polar code ^^1, and the one or more first constraints for the one or more respective first dynamic frozen bits, wherein the second precoded matrix ^^2indicates, positions of the one or more second dynamic frozen bits within a second sequence of bits input to a second polar transform ^^(^^^2)of the second component precoded polar code ^^2, and the one or more second constraints for the one or more respective second dynamic frozen bits, and wherein the precoded matrix P indicates positions of the one or more third dynamic frozen bits within a third sequence of bits input to a third polar transform ^^(^^)of the product precoded polar code ^^, and the one or more third constraints for the one or more respective third dynamic frozen bits.

37. The apparatus according to any of claims 33-36, wherein a constraint for a dynamic frozen bit is defined as a constrainedarithmetic relationship between the dynamic frozen bit and one or more information bits.

38. The apparatus according to claim 36 or 37, wherein the first precoded matrix ^^1further indicates positions of one or more first frozen bits within the first sequence of bits, wherein the second precoded matrix ^^2further indicates positions of one or more second frozen bits within the second sequence of bits, and wherein the precoded matrix P further indicates positions of one or more third frozen bits within the third sequence of bits.

39. The apparatus according to claim 38, wherein a frozen bit is a bit whose value is preliminary known to a decoder.

40. The apparatus according to any of claims 33-39, wherein the first and second decoded bit values are estimated coded bit values, and wherein the apparatus further comprises: means for determining the first decoded bit values based at least in part on first soft information generated after a first successive cancellation list decoding; and means for determining the second decoded bit values based at least in part on second soft information after a second successive cancellation list decoding.

41. The apparatus according to claim 40, further comprising: in case that all codewords generated by the first successive cancellation list decoding have the same value for a given bit, means for setting the absolute value of the first soft information of the given bit to a maximum path metricgenerated by the first successive cancellation list decoding, and means for sending first extrinsic information for the second decoding based on the first soft information; and in case that all codewords generated by the second successive cancellation list decoding have the same value for a given bit, means for setting the absolute value of the second soft information of the given bit to a maximum path metric generated by the second successive cancellation list decoding, and means for sending second extrinsic information for the first decoding based on the second soft information.

42. The apparatus according to claim 41, wherein the first soft information and the second soft information are computed as: +max(ℓ)= 0 ∀ (ℓ)ì ℓ^^ℓ^^^^ ^^^^ ^^ ∈ ^^, wherein Λof i-th element^^ofx, ^^ℓ denotes a path metric for a decoding path ℓ yieldingcodeword ^^(ℓ), max function is over all path metrics of paths in the list ^^, and ( ) ^^^^⊆ ^^of the members ^^ of list ^^ such that their ^^-th element ^^ isto ^^.

43. A non-transitory computer readable medium comprising program instructions stored thereon for performing the method according to any of claims 1-14.

44. An apparatus comprising circuitry configured to cause the apparatus toperform the process according to any of claims 1-14

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