Display substrate and display device

Abstract

The present disclosure provides a display substrate and a display device. The display substrate comprises a display area and a peripheral area located on the periphery of the display area, and further comprises a plurality of sub-pixels located in the display area, wherein each sub-pixel comprises a sub-pixel driving circuit, and the sub-pixel driving circuit comprises a transistor structure. The display substrate further comprises: a conductive layer and signal transmission lines, wherein the orthographic projection of the conductive layer on a base substrate at least partially overlaps the orthographic projection of the transistor structures on the base substrate, at least part of the conductive layer is located between the transistor structures and the base substrate of the display substrate, and the conductive layer is coupled to the signal transmission lines in the peripheral area.

Description

Display substrate and display device

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Chinese patent application No. 202311585356.1 filed in China on November 24, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to the field of display technology, and in particular to a display substrate and a display device. Background Art

[0004] With the continuous development of display technology, the application fields of display products are becoming more and more extensive, and people's requirements for the performance and application scenarios of display products are also becoming higher and higher. For example, for display products with touch functions, high-frequency touch use can be achieved; under the influence of external electric and magnetic fields, and in harsh environments such as high temperature and high humidity, the characteristics of transistors in display products remain stable; however, the above requirements cannot be achieved with existing technologies.

[0005] Summary of the Invention

[0006] An object of the present disclosure is to provide a display substrate and a display device.

[0007] In order to achieve the above objectives, the present disclosure provides the following technical solutions:

[0008] A first aspect of the present disclosure provides a display substrate, comprising a display area and a peripheral area located around the display area, and further comprising a plurality of sub-pixels located in the display area, wherein the sub-pixels include a sub-pixel driving circuit, and the sub-pixel driving circuit includes a transistor structure; the display substrate further comprises:

[0009] A conductive layer and a signal transmission line, wherein the orthographic projection of the conductive layer on the base substrate at least partially overlaps with the orthographic projection of the transistor structure on the base substrate, and at least a portion of the conductive layer is located between the transistor structure and the base substrate of the display substrate; the conductive layer and the signal transmission line are coupled in the peripheral area.

[0010] Optionally, the display substrate further includes a first initialization signal line, the signal transmission line includes a first reset signal line, the transistor structure includes a driving transistor and a first reset transistor, a gate of the first reset transistor is coupled to the corresponding first reset signal line, a first electrode of the first reset transistor is coupled to the corresponding first initialization signal line, and a second electrode of the first reset transistor is coupled to the gate of the driving transistor; the first reset transistor includes a first reset active layer;

[0011] The conductive layer includes a first conductive pattern, an orthographic projection of the first conductive pattern on the base substrate at least partially overlaps with an orthographic projection of the first reset active layer on the base substrate, and the first conductive pattern is coupled to the first reset signal line in the peripheral area.

[0012] Optionally, the display substrate further includes a second initialization signal line, the sub-pixel further includes a light-emitting element, and the transistor structure further includes a second reset transistor, wherein a gate of the second reset transistor is coupled to a first reset signal line coupled to a first reset transistor in an adjacent sub-pixel along a second direction, a first electrode of the second reset transistor is coupled to the corresponding second initialization signal line, and a second electrode of the second reset transistor is coupled to an anode of the light-emitting element; and the second reset transistor includes a second reset active layer;

[0013] An orthographic projection of the first conductive pattern on the base substrate at least partially overlaps with an orthographic projection of the second reset active layer on the base substrate.

[0014] Optionally, the plurality of sub-pixel driving circuits included in the plurality of sub-pixels are divided into a plurality of rows of sub-pixel driving circuits, each row of sub-pixel driving circuits includes a plurality of sub-pixel driving circuits arranged along a first direction; and the first conductive pattern includes at least a portion extending along the first direction;

[0015] The orthographic projection of the first conductive pattern on the base substrate at least partially overlaps with the orthographic projection of the first reset active layer included in each sub-pixel driving circuit in a corresponding row of sub-pixel driving circuits on the base substrate; and / or the orthographic projection of the first conductive pattern on the base substrate at least partially overlaps with the orthographic projection of the second reset active layer included in each sub-pixel driving circuit in an adjacent upper row of sub-pixel driving circuits on the base substrate.

[0016] Optionally, the peripheral area includes a left frame area and a right frame area arranged opposite to each other along the first direction, and the display area is located between the left frame area and the right frame area; the display substrate further includes a first conductive connection portion;

[0017] In the left frame area and / or the right frame area, the first conductive connection portion is coupled to the corresponding first reset signal line, and the first conductive connection portion is coupled to the corresponding first conductive pattern through a first via hole;

[0018] The first via includes a first sub-via and a second sub-via that are connected to each other. The first sub-via is located between the second sub-via and the base substrate. The orthographic projection of the hole wall of the first sub-via on the base substrate is surrounded by the orthographic projection of the second sub-via on the base substrate.

[0019] Optionally, the signal transmission line includes a scan line, the transistor structure includes a driving transistor and a compensation transistor, the gate of the compensation transistor is coupled to the corresponding scan line, the first electrode of the compensation transistor is coupled to the second electrode of the driving transistor, and the second electrode of the compensation transistor is coupled to the gate of the driving transistor; the compensation transistor includes a compensation active layer;

[0020] The conductive layer includes a second conductive pattern, an orthographic projection of the second conductive pattern on the base substrate at least partially overlaps with an orthographic projection of the compensation active layer on the base substrate, and the second conductive pattern is coupled to the scan line in the peripheral area.

[0021] Optionally, the compensation transistor includes a dual-gate transistor, the compensation active layer includes a first channel portion, a second channel portion and a conductor portion, the conductor portion is coupled to the first channel portion and the second channel portion respectively, the orthographic projection of the second conductive pattern on the substrate at least partially overlaps with the orthographic projection of the first channel portion on the substrate, and / or the orthographic projection of the second conductive pattern on the substrate at least partially overlaps with the orthographic projection of the second channel portion on the substrate.

[0022] Optionally, the display substrate further includes a data line, the transistor structure further includes a data write transistor, a gate of the data write transistor is coupled to the corresponding scan line, a first electrode of the data write transistor is coupled to the corresponding data line, and a second electrode of the data write transistor is coupled to the first electrode of the drive transistor; the data write transistor includes a data write active layer;

[0023] The orthographic projection of the second conductive pattern on the base substrate at least partially overlaps with the orthographic projection of the data writing active layer on the base substrate.

[0024] Optionally, the plurality of sub-pixel driving circuits included in the plurality of sub-pixels are divided into a plurality of rows of sub-pixel driving circuits, each row of sub-pixel driving circuits includes a plurality of sub-pixel driving circuits arranged along a first direction; and the second conductive pattern includes at least a portion extending along the first direction;

[0025] The orthographic projection of the second conductive pattern on the base substrate at least partially overlaps with the orthographic projection of the compensation active layer included in each sub-pixel driving circuit in a corresponding row of sub-pixel driving circuits on the base substrate; and / or the orthographic projection of the second conductive pattern on the base substrate at least partially overlaps with the orthographic projection of the data writing active layer included in each sub-pixel driving circuit in a corresponding row of sub-pixel driving circuits on the base substrate.

[0026] Optionally, the peripheral area includes a left frame area and a right frame area arranged opposite to each other along the first direction, and the display area is located between the left frame area and the right frame area; the display substrate further includes a second conductive connection portion;

[0027] In the left frame area and / or the right frame area, the second conductive connection portion is coupled to the corresponding scan line, and the second conductive connection portion is coupled to the corresponding second conductive pattern through a second via hole;

[0028] The second via includes a third sub-via and a fourth sub-via that are connected to each other. The third sub-via is located between the fourth sub-via and the base substrate. The orthographic projection of the hole wall of the third sub-via on the base substrate is surrounded by the orthographic projection of the fourth sub-via on the base substrate.

[0029] Optionally, the display substrate further includes a scan line, the signal transmission line includes a first initialization signal line, the transistor structure includes a driving transistor and a compensation transistor, the gate of the compensation transistor is coupled to the corresponding scan line, the first electrode of the compensation transistor is coupled to the second electrode of the driving transistor, and the second electrode of the compensation transistor is coupled to the gate of the driving transistor; the compensation transistor includes a compensation active layer;

[0030] The conductive layer includes a third conductive pattern, an orthographic projection of the third conductive pattern on the base substrate at least partially overlaps with an orthographic projection of the compensation active layer on the base substrate, and the third conductive pattern is coupled to the first initialization signal line in the peripheral area.

[0031] Optionally, the compensation active layer includes a first channel portion, a second channel portion and a conductor portion, and the conductor portion is coupled to the first channel portion and the second channel portion respectively;

[0032] The orthographic projection of the third conductive pattern on the substrate at least partially overlaps with the orthographic projection of the first channel portion on the substrate; and / or, the orthographic projection of the third conductive pattern on the substrate at least partially overlaps with the orthographic projection of the second channel portion on the substrate; and / or, the orthographic projection of the third conductive pattern on the substrate at least partially overlaps with the orthographic projection of the conductor portion on the substrate.

[0033] Optionally, the plurality of sub-pixel driving circuits included in the plurality of sub-pixels are divided into a plurality of rows of sub-pixel driving circuits, each row of sub-pixel driving circuits including a plurality of sub-pixel driving circuits arranged along a first direction; the third conductive pattern includes at least a portion extending along the first direction; the third conductive pattern includes a main portion and a plurality of protrusions respectively coupled to the main portion;

[0034] The main body portion includes at least a portion extending along a first direction, the main body portion is coupled to the first initialization signal line in the peripheral region, and an orthographic projection of the main body portion on the base substrate does not overlap with an orthographic projection of at least one of the first channel portion, the second channel portion, and the conductor portion on the base substrate;

[0035] The multiple protrusions correspond one-to-one to each compensation active layer in a corresponding row of sub-pixel driving circuits; the orthographic projection of the protrusion on the base substrate at least partially overlaps with the orthographic projection of the first channel portion included in the corresponding compensation active layer on the base substrate; and / or, the orthographic projection of the protrusion on the base substrate at least partially overlaps with the orthographic projection of the second channel portion included in the corresponding compensation active layer on the base substrate; and / or, the orthographic projection of the protrusion on the base substrate at least partially overlaps with the orthographic projection of the conductor portion included in the corresponding compensation active layer on the base substrate.

[0036] Optionally, the peripheral area includes a left border area and a right border area arranged opposite to each other along a first direction, and the display area is located between the left border area and the right border area; the display substrate also includes a first initialization bus located in the left border area and / or the right border area, the first initialization bus includes at least a portion extending along the second direction, and in the left border area and / or the right border area, the main body and the first initialization signal line are respectively coupled to the first initialization bus.

[0037] Optionally, the main body is coupled to the first initialization bus through a third via, the third via includes a fifth sub-via and a sixth sub-via that are connected, the fifth sub-via is located between the sixth sub-via and the base substrate, and the orthographic projection of the hole wall of the fifth sub-via on the base substrate is surrounded by the orthographic projection of the sixth sub-via on the base substrate.

[0038] Optionally, the conductive layer further includes a first connecting line, which is at least partially arranged around the display area, and the first connecting line is respectively coupled to two ends of each of the main parts in the display substrate.

[0039] Optionally, an orthographic projection of the first connecting line on the base substrate at least partially overlaps with an orthographic projection of the first initialization bus on the base substrate.

[0040] Optionally, the transmission signal line includes a power connection line located in the peripheral area, the transistor structure includes a driving transistor, and the driving transistor includes a driving active layer; the conductive layer includes a fourth conductive pattern, the orthographic projection of the fourth conductive pattern on the substrate at least partially overlaps with the orthographic projection of the driving active layer on the substrate, and the fourth conductive pattern is coupled to the power connection line.

[0041] Optionally, the peripheral area includes an upper frame area and a lower frame area that are arranged opposite to each other along the second direction, and the display area is located between the upper frame area and the lower frame area;

[0042] The power connection line is located in the upper frame area and / or the lower frame area; the conductive layer also includes a second connection line, at least part of the second connection line is arranged around the display area, the second connection line is coupled to the power connection line in the upper frame area and / or the lower frame area, and the second connection line is respectively coupled to the two ends of each of the fourth conductive patterns in the display substrate.

[0043] Optionally, the second connecting line is coupled to the power connecting line in the upper frame area and / or the lower frame area through a fourth via, and the fourth via includes a seventh sub-via and an eighth sub-via coupled, and the seventh sub-via is located between the eighth sub-via and the base substrate, and the orthographic projection of the hole wall of the seventh sub-via on the base substrate is surrounded by the orthographic projection of the hole wall of the eighth sub-via on the base substrate.

[0044] Optionally, the peripheral area further includes a first fan-out area and a second fan-out area, the first fan-out area being located between the display area and the second fan-out area; the display substrate further includes a plurality of data lines and a plurality of data fan-out lines, the data fan-out lines being coupled to corresponding data lines, at least portions of the data lines being located in the display area, and at least portions of the data fan-out lines being located in the first fan-out area and the second fan-out area, and a data fan-out line density in the first fan-out area being less than a fan-out line density in the second fan-out area;

[0045] The first connection line is located between the second fan-out area and the display area; or the second connection line is located between the second fan-out area and the display area.

[0046] Optionally, the plurality of sub-pixel driving circuits included in the plurality of sub-pixels are divided into a plurality of rows of sub-pixel driving circuits, each row of sub-pixel driving circuits includes a plurality of sub-pixel driving circuits arranged along a first direction; and the second conductive pattern includes at least a portion extending along the first direction;

[0047] The orthographic projection of the fourth conductive pattern on the base substrate at least partially overlaps with the orthographic projection of the driving active layer included in each sub-pixel driving circuit in a corresponding row of sub-pixel driving circuits on the base substrate.

[0048] Optionally, the display substrate further includes an interlayer insulating layer having a plurality of connection holes; the orthographic projection of the conductive layer on the base substrate does not overlap with the orthographic projection of the hole walls of the connection holes on the base substrate.

[0049] Optionally, the interlayer insulating layer further includes a plurality of virtual compensation holes, the virtual compensation holes being located in the display area and / or the peripheral area, and the orthographic projection of the conductive layer on the base substrate does not overlap with the orthographic projection of the hole wall of the virtual compensation hole on the base substrate.

[0050] Based on the technical solution of the above-mentioned display substrate, a second aspect of the present disclosure provides a display device including the above-mentioned display substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] The drawings described herein are used to provide a further understanding of the present disclosure and constitute a part of the present disclosure. The exemplary embodiments of the present disclosure and their descriptions are used to explain the present disclosure and do not constitute an improper limitation of the present disclosure. In the drawings:

[0052] FIG1 is a schematic diagram of a circuit principle of a sub-pixel driving circuit provided in an embodiment of the present disclosure;

[0053] FIG2 is a schematic cross-sectional view of a film layer of a display substrate provided by an embodiment of the present disclosure;

[0054] 3 is a schematic diagram of a first layout of a conductive layer, an active layer, and a first gate metal layer in a display substrate provided by an embodiment of the present disclosure;

[0055] 4 is a schematic diagram of the layout of the active layer, the first gate metal layer, the second gate metal layer, and the first source and drain metal layer in the display substrate provided by an embodiment of the present disclosure;

[0056] FIG5 is a schematic diagram of the layout of a first source / drain metal layer in a display substrate provided by an embodiment of the present disclosure;

[0057] FIG6 is a schematic diagram of a layout in which a second source / drain metal layer is added on the basis of FIG4 ;

[0058] FIG7 is a schematic diagram of the layout of the second source / drain metal layer in the display substrate provided by an embodiment of the present disclosure;

[0059] FIG8 is a schematic diagram showing a layout in which a second source / drain metal layer is added based on FIG6 ;

[0060] FIG9 is a schematic diagram showing connections between a third conductive pattern and a first connecting line according to an embodiment of the present disclosure;

[0061] FIG10 is a schematic diagram of a second layout of the conductive layer, the active layer, and the first gate metal layer in the display substrate provided by an embodiment of the present disclosure;

[0062] FIG11 is a schematic diagram of another layout from the conductive layer to the second source / drain metal layer in the display substrate provided by an embodiment of the present disclosure;

[0063] FIG12 is a schematic diagram of the connection between the third conductive pattern and the first connecting line in the left frame according to an embodiment of the present disclosure;

[0064] FIG13 is a schematic diagram showing the connection between a fourth conductive pattern and a second connecting line according to an embodiment of the present disclosure;

[0065] FIG14 is a schematic diagram of the connection between the second connection line of the lower frame and the power connection line provided by an embodiment of the present disclosure;

[0066] FIG15 is a schematic diagram of the connection between the second connection line of the upper frame and the power connection line provided by an embodiment of the present disclosure;

[0067] FIG16 is a schematic diagram showing the connection between the fourth conductive pattern and the second connecting line in the left frame according to an embodiment of the present disclosure;

[0068] FIG17 is a cross-sectional schematic diagram of a trepanation provided in an embodiment of the present disclosure;

[0069] FIG18 is a schematic diagram of the layout of the second connection line in the lower left corner and the fan-out area provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0070] In order to further illustrate the display substrate and the display device provided by the embodiments of the present disclosure, a detailed description is given below with reference to the accompanying drawings.

[0071] Referring to FIG. 1 to FIG. 3 , FIG. 10 , FIG. 12 , and FIG. 16 , an embodiment of the present disclosure provides a display substrate, including a display area 10 and a peripheral area 20 located around the display area 10 , and also including a plurality of sub-pixels located in the display area 10 , wherein the sub-pixels include a sub-pixel driving circuit, and the sub-pixel driving circuit includes a transistor structure; the display substrate further includes:

[0072] A conductive layer BSM and a signal transmission line 30, wherein the orthographic projection of the conductive layer BSM on the base substrate at least partially overlaps with the orthographic projection of the transistor structure (such as the first reset transistor T1, the second reset transistor T7, the compensation transistor T2, the data writing transistor T4 and the driving transistor T5, etc.) on the base substrate, and at least a portion of the conductive layer BSM is located between the transistor structure and the base substrate of the display substrate; the conductive layer BSM and the signal transmission line 30 are coupled in the peripheral area 20.

[0073] Exemplarily, the peripheral area 20 surrounds the display area 10 , but is not limited thereto.

[0074] Exemplarily, the display substrate includes a plurality of sub-pixels, and the plurality of sub-pixel driving circuits included in the plurality of sub-pixels are distributed in an array. The plurality of sub-pixel driving circuits are divided into a plurality of rows of sub-pixel driving circuits and a plurality of columns of sub-pixel driving circuits. The plurality of rows of sub-pixel driving circuits are arranged along a second direction, and each row of sub-pixel driving circuits includes a plurality of sub-pixel driving circuits arranged along a first direction. The plurality of columns of sub-pixel driving circuits are arranged along a first direction, and each column of sub-pixel driving circuits includes a plurality of sub-pixel driving circuits arranged along a second direction. Exemplarily, the first direction and the second direction intersect. For example, the first direction includes a transverse direction, and the second direction includes a longitudinal direction.

[0075] Exemplarily, the sub-pixel includes a sub-pixel driving circuit and a light-emitting element. The sub-pixel driving circuit is coupled to an anode of the light-emitting element and is configured to provide a driving signal to the light-emitting element to drive the light-emitting element to emit light.

[0076] Exemplarily, the specific structures of the sub-pixel driving circuit vary, for example, 6T1C (i.e., 6 transistors and 1 capacitor), 7T1C (i.e., 7 transistors and 1 capacitor), 8T1C (i.e., 8 transistors and 1 capacitor), 9T1C (i.e., 9 transistors and 1 capacitor), etc., but are not limited thereto. The transistor structure includes at least one transistor in a sub-pixel driving circuit of any of the above structures.

[0077] Exemplarily, at least a portion of the conductive layer BSM is located between the transistor structure and the base substrate of the display substrate. When the transistor structure includes a low-temperature polysilicon transistor, at least a portion of the conductive layer BSM is located between the active layer of the transistor structure and the base substrate.

[0078] Exemplarily, the conductive layer BSM is made of a conductive metal material, such as Mo (molybdenum), but is not limited thereto.

[0079] Exemplarily, the conductive layer BSM can extend from the display area 10 to the peripheral area 20 , but is not limited thereto.

[0080] Exemplarily, the signal transmission line 30 may include a portion located in the display area 10 and a portion located in the peripheral area 20; the signal transmission line 30 may also only include a portion located in the peripheral area 20; but is not limited to the above two methods.

[0081] Illustratively, the signal transmission line 30 is used to transmit a DC voltage signal having a stable potential; and / or the signal transmission line 30 is coupled to the gate of the transistor structure to provide a corresponding signal to the gate of the transistor structure to control the on and off state of the transistor structure. The conductive layer BSM is coupled to the signal transmission line 30 so that the conductive layer BSM and the signal transmission line 30 transmit the same signal.

[0082] Exemplarily, the peripheral area 20 includes a left border area and a right border area arranged relative to each other along a first direction, and an upper border area and a lower border area arranged relative to each other along a second direction, and the display area 10 is located between the upper border area and the lower border area, and between the left border area and the right border area; the conductive layer BSM is coupled to the signal transmission line 30 in at least one area among the upper border area, the lower border area, the left border area and the right border area.

[0083] Exemplarily, the transistor structure includes a corresponding transistor active layer, and the orthographic projection of the conductive layer BSM on the substrate at least partially overlaps with the orthographic projection of the transistor active layer on the substrate. Furthermore, the transistor active layer includes a channel portion, and the orthographic projection of the conductive layer BSM on the substrate can be arranged to at least partially overlap with the orthographic projection of the channel portion on the substrate. It is worth noting that the orthographic projection of the channel portion on the substrate is covered by the orthographic projection of the gate on the substrate.

[0084] According to the specific structure of the display substrate described above, in the display substrate provided by the embodiments of the present disclosure, the orthographic projection of the conductive layer BSM on the base substrate is arranged to at least partially overlap with the orthographic projection of the transistor structure on the base substrate. At least a portion of the conductive layer BSM is located between the transistor structure and the base substrate of the display substrate. The conductive layer BSM is coupled to the signal transmission line 30 in the peripheral region 20. When the signal transmission line 30 transmits a DC voltage signal with a stable potential, the conductive layer BSM also transmits a DC voltage signal with a stable potential. In this way, the conductive layer BSM can shield the transistor structure that overlaps with it, thereby shielding the transistor structure from the effects of the magnetic field and electric field generated by touch control when the display product is used at high frequencies. At the same time, it can shield the transistor structure from the effects of the magnetic field and electric field generated by the conductive structure within the display substrate. When the signal transmission line 30 is coupled to the gate of the transistor structure, the signal transmitted by the conductive layer BSM is the same as the signal transmitted by the signal transmission line 30 coupled to the gate of the overlapping transistor structure. In this way, the transistor structure and the conductive layer BSM can form a dual-gate structure, making the characteristics of the transistor structure more stable, thereby better meeting the reliability and yield requirements of display products in harsh environments such as high temperature and high humidity. Therefore, the display substrate provided by the embodiments of the present disclosure can achieve better display quality and avoid problems such as green display screen.

[0085] As shown in FIG3 to FIG8 , in some embodiments, the display substrate further includes a first initialization signal line Vinit1, the signal transmission line 30 includes a first reset signal line Rst, the transistor structure includes a driving transistor T3 and a first reset transistor T1, the gate of the first reset transistor T1 is coupled to the corresponding first reset signal line Rst, the first electrode of the first reset transistor T1 is coupled to the corresponding first initialization signal line Vinit1, and the second electrode of the first reset transistor T1 is coupled to the gate of the driving transistor T3; the first reset transistor T1 includes a first reset active layer 41;

[0086] The conductive layer BSM includes a first conductive pattern BSM1, the orthographic projection of the first conductive pattern BSM1 on the base substrate at least partially overlaps with the orthographic projection of the first reset active layer 41 on the base substrate, and the first conductive pattern BSM1 is coupled to the first reset signal line Rst in the peripheral area 20.

[0087] Exemplarily, the display substrate includes a plurality of first initialization signal lines Vinit1, the first initialization signal line Vinit1 includes at least a portion extending along the first direction, the first initialization signal line Vinit1 corresponds one-to-one to a plurality of rows of sub-pixel driving circuits, and the first initialization signal line Vinit1 is respectively coupled to the first electrode of the first reset transistor T1 included in each sub-pixel driving circuit in a corresponding row of sub-pixel driving circuits.

[0088] Exemplarily, the display substrate includes a plurality of first reset signal lines Rst, the first reset signal lines Rst include at least a portion extending along the first direction, the first reset signal lines Rst correspond one-to-one to a plurality of rows of sub-pixel driving circuits, and the first reset signal lines Rst are respectively coupled to the gates of the first reset transistors T1 included in each sub-pixel driving circuit in a corresponding row of sub-pixel driving circuits.

[0089] Exemplarily, the conductive layer BSM includes a plurality of first conductive patterns BSM1, the first conductive patterns BSM1 include at least a portion extending along the first direction, the first conductive patterns BSM1 correspond one-to-one to multiple rows of sub-pixel driving circuits, and the orthographic projection of the first conductive pattern BSM1 on the substrate at least partially overlaps with the orthographic projection of the first reset active layer 41 included in each sub-pixel driving circuit in a corresponding row of sub-pixel driving circuits on the substrate.

[0090] Exemplarily, the plurality of first conductive patterns BSM1 correspond one-to-one to the plurality of first reset signal lines Rst, and the first conductive patterns BSM1 are coupled to the corresponding first reset signal lines Rst in the peripheral region 20 .

[0091] In the display substrate provided in the above embodiment, the orthographic projection of the first conductive pattern BSM1 on the base substrate is arranged to at least partially overlap with the orthographic projection of the first reset active layer 41 on the base substrate. The first conductive pattern BSM1 is coupled to the first reset signal line Rst in the peripheral region 20. Thus, the signal transmitted by the first conductive pattern BSM1 is the same as the signal transmitted by the first reset signal line Rst, which is coupled to the gate of the first reset transistor T1 with which it overlaps. Thus, the first reset transistor T1 and the first conductive pattern BSM1 can together form a dual-gate structure, making the characteristics of the first reset transistor T1 more stable, thereby better meeting the reliability and yield requirements of display products in harsh environments such as high temperature and high humidity.

[0092] As shown in FIG3 to FIG8 , in some embodiments, the display substrate further includes a second initialization signal line Vinit2, the sub-pixel further includes a light-emitting element, and the transistor structure further includes a second reset transistor T7, wherein a gate of the second reset transistor T7 is coupled to the first reset signal line Rst coupled to the first reset transistor T1 in the adjacent sub-pixel along the second direction, a first electrode of the second reset transistor T7 is coupled to the corresponding second initialization signal line Vinit2, and a second electrode of the second reset transistor T7 is coupled to the anode of the light-emitting element; the second reset transistor T7 includes a second reset active layer 47;

[0093] An orthographic projection of the first conductive pattern BSM1 on the base substrate at least partially overlaps with an orthographic projection of the second reset active layer 47 on the base substrate.

[0094] Exemplarily, the display substrate includes a plurality of second initialization signal lines, the second initialization signal lines include at least a portion extending along the first direction, the second initialization signal lines correspond one-to-one to a plurality of rows of sub-pixel driving circuits, and the second initialization signal lines are respectively coupled to the first electrodes of the second reset transistors included in each sub-pixel driving circuit in a corresponding row of sub-pixel driving circuits.

[0095] Exemplarily, the first reset signal line Rst corresponds one-to-one to multiple rows of sub-pixel driving circuits, and the first reset signal line Rst is respectively coupled to the gate of the first reset transistor T1 included in each sub-pixel driving circuit in the corresponding row of sub-pixel driving circuits. The gate of the second reset transistor T7 in each row of sub-pixel driving circuits is coupled to the first reset signal line Rst corresponding to the sub-pixel driving circuit in the next adjacent row along the second direction.

[0096] Exemplarily, the second reset transistor T7 in each row of sub-pixel driving circuits includes an orthographic projection of the second reset active layer 47 on the substrate, which at least partially overlaps with the orthographic projection of the first conductive pattern BSM1 corresponding to the next row of sub-pixel driving circuits adjacent to the second direction on the substrate.

[0097] In the display substrate provided in the above embodiment, the orthographic projection of the first conductive pattern BSM1 on the base substrate is arranged to at least partially overlap with the orthographic projection of the second reset active layer on the base substrate, and the first conductive pattern BSM1 is coupled to the first reset signal line Rst in the peripheral region 20. In this way, the signal transmitted by the first conductive pattern BSM1 is the same as the signal transmitted by the first reset signal line Rst, which is coupled to the gate of the second reset transistor with which it overlaps. As a result, the second reset transistor and the first conductive pattern BSM1 can together form a dual-gate structure, making the characteristics of the second reset transistor more stable, thereby better meeting the reliability and yield requirements of display products in harsh environments such as high temperature and high humidity.

[0098] As shown in FIG3 to FIG8 , in some embodiments, the plurality of sub-pixel driving circuits included in the plurality of sub-pixels are divided into a plurality of rows of sub-pixel driving circuits, and each row of sub-pixel driving circuits includes a plurality of sub-pixel driving circuits arranged along a first direction; the first conductive pattern BSM1 includes at least a portion extending along the first direction;

[0099] The orthographic projection of the first conductive pattern BSM1 on the base substrate at least partially overlaps with the orthographic projection of the first reset active layer 41 included in each sub-pixel driving circuit in a corresponding row of sub-pixel driving circuits on the base substrate; and / or, the orthographic projection of the first conductive pattern BSM1 on the base substrate at least partially overlaps with the orthographic projection of the second reset active layer 47 included in each sub-pixel driving circuit in an adjacent upper row of sub-pixel driving circuits on the base substrate.

[0100] The above configuration improves the characteristics of the first reset transistor T1 and the second reset transistor T7 in the display substrate while simplifying the structure of the display substrate and reducing the difficulty of the layout of the display substrate.

[0101] As shown in FIG16 , in some embodiments, the peripheral region 20 includes a left frame region and a right frame region disposed opposite to each other along the first direction, and the display region 10 is located between the left frame region and the right frame region; the display substrate further includes a first conductive connection portion 51;

[0102] In the left frame area and / or the right frame area, the first conductive connection portion 51 is coupled to the corresponding first reset signal line Rst, and the first conductive connection portion 51 is coupled to the corresponding first conductive pattern BSM1 through the first via hole Via1;

[0103] As shown in Figure 17, the first via Via1 includes a first sub-via Via11 and a second sub-via Via12 that are connected to each other. The first sub-via Via11 is located between the second sub-via Via12 and the base substrate. The orthographic projection of the hole wall of the first sub-via Via11 on the base substrate is surrounded by the orthographic projection of the second sub-via Via12 on the base substrate.

[0104] It should be noted that the dotted boxes in FIG. 12 and FIG. 16 represent that a conductive connection portion made of a second source / drain metal layer will be provided here to electrically connect the corresponding structures.

[0105] As shown in FIG2 , the display substrate exemplarily includes a conductive layer BSM, a barrier layer Bar, a buffer layer BUF, an active layer poly, a first gate insulating layer GI1, a first gate metal layer gate1, a second gate insulating layer GI2, a second gate metal layer gate2, an interlayer insulating layer ILD, a first source / drain metal layer SD1, a first planarization layer PLN1, a second source / drain metal layer SD2, a second planarization layer PLN2, an anode layer ANO, a pixel defining layer PDL, a light emitting functional layer EL, a cathode layer cath, a first inorganic encapsulation layer CVD1, an organic encapsulation layer IJP, and a second inorganic encapsulation layer CVD2, which are sequentially stacked in a direction away from the base substrate 70. The display substrate may further include a passivation layer PVX, but is not limited thereto.

[0106] As shown in Figure 17, exemplarily, the first via Via1 is manufactured by the ILD&EBB via process, which includes two process flows; after the interlayer insulating layer ILD is manufactured, an ILD via process is performed to form the second sub-via Via12, and the second sub-via Via12 can at least penetrate the interlayer insulating layer ILD, and the second sub-via Via12 can further penetrate the second gate insulating layer GI2, at least one layer of the first gate insulating layer GI1 and the buffer layer BUF, and the second sub-via Via12 can also partially penetrate the barrier layer Bar; then an EBB via process is performed to completely penetrate the remaining film layer until the conductive layer BSM is exposed to form the first sub-via Via11.

[0107] Exemplarily, the first sub-via Via11 and the second sub-via Via12 are jointly formed into a stepped trestle design, and the aperture of the second sub-via Via12 is larger than the aperture of the first sub-via Via11. The specific aperture size is subject to process capabilities. For example: in a direction parallel to the base substrate, on at least one side of the first via Via1, the distance between the orthographic projection of the hole wall of the second sub-via Via12 on the base substrate and the orthographic projection of the hole wall of the first sub-via Via11 on the base substrate is greater than or equal to 1 micron, ensuring that the orthographic projection of the hole wall of the first sub-via Via11 on the base substrate is surrounded by the orthographic projection of the second sub-via Via12 on the base substrate.

[0108] The above-mentioned arrangement is in the left frame area and / or the right frame area, and the first conductive connection part 51 is coupled to the corresponding first reset signal line Rst, and the first conductive connection part 51 is coupled to the corresponding first conductive pattern BSM1 through the first via Via1; so that the first conductive pattern BSM1 can be coupled to the first reset signal line Rst on the left and right sides of the display area 10, and the first conductive pattern BSM1 can pass through the display area 10 along the first direction, thereby ensuring the signal transmission uniformity of the first conductive pattern BSM1 and the characteristic stability of its overlapping transistor structures.

[0109] The above-mentioned arrangement of the first via hole Via1 using a sleeve hole structure not only ensures the manufacturing yield of the first via hole Via1 , but also ensures the connection performance between the first conductive pattern BSM1 and the first conductive connecting portion 51 .

[0110] As shown in FIG3 to FIG8 , in some embodiments, the signal transmission line 30 includes a scan line GA, the transistor structure includes a driving transistor T3 and a compensation transistor T2, the gate of the compensation transistor T2 is coupled to the corresponding scan line GA, the first electrode of the compensation transistor T2 is coupled to the second electrode of the driving transistor T3, and the second electrode of the compensation transistor T2 is coupled to the gate of the driving transistor T3; the compensation transistor T2 includes a compensation active layer 42;

[0111] As shown in Figure 16, the conductive layer BSM includes a second conductive pattern BSM2, the orthographic projection of the second conductive pattern BSM2 on the base substrate at least partially overlaps with the orthographic projection of the compensation active layer 42 on the base substrate, and the second conductive pattern BSM2 is coupled to the scan line GA in the peripheral area 20.

[0112] Exemplarily, the display substrate includes a plurality of scan lines GA, the scan lines GA including at least a portion extending along the first direction, the scan lines GA corresponding one-to-one to a plurality of rows of sub-pixel driving circuits, and the scan lines GA are respectively coupled to the gates of the compensation transistors T2 included in each sub-pixel driving circuit in a corresponding row of sub-pixel driving circuits.

[0113] Exemplarily, the conductive layer BSM includes a plurality of second conductive patterns BSM2, the second conductive patterns BSM2 include at least a portion extending along the first direction, the second conductive patterns BSM2 correspond one-to-one to multiple rows of sub-pixel driving circuits, and the orthographic projection of the second conductive pattern BSM2 on the substrate at least partially overlaps with the orthographic projection of the compensation active layer 42 included in each sub-pixel driving circuit in a corresponding row of sub-pixel driving circuits on the substrate.

[0114] Exemplarily, the plurality of second conductive patterns BSM2 correspond one-to-one to the plurality of scan lines GA, and the second conductive patterns BSM2 are coupled to the corresponding scan lines GA in the peripheral region 20 .

[0115] For example, the first reset signal line Rst coupled to the current row of sub-pixel driving circuits is coupled to the scan line GA coupled to the adjacent previous row of sub-pixel driving circuits in the peripheral area 20. The coupling can be achieved through the first conductive connection portion 51, but is not limited thereto.

[0116] It is worth noting that if there is no corresponding signal line in the previous or next row to provide signals for the signal lines coupling the first row of sub-pixel driving circuits and the last row of sub-pixel driving circuits in the display substrate, corresponding shift register units can be directly added in the peripheral area 20 to provide corresponding signals for them.

[0117] In the display substrate provided in the above embodiment, the orthographic projection of the second conductive pattern BSM2 on the base substrate is configured to at least partially overlap with the orthographic projection of the compensation active layer 42 on the base substrate. The second conductive pattern BSM2 is coupled to the scan line GA in the peripheral region 20. Thus, the signal transmitted by the second conductive pattern BSM2 is the same as the signal transmitted by the scan line GA coupled to the gate of the compensation transistor T2 with which it overlaps. Consequently, the compensation transistor T2 and the second conductive pattern BSM2 can together form a dual-gate structure, making the characteristics of the compensation transistor T2 more stable, thereby better meeting the reliability and yield requirements of display products in harsh environments such as high temperature and high humidity.

[0118] As shown in Figures 3 to 8, in some embodiments, the compensation transistor T2 includes a dual-gate transistor, the compensation active layer 42 includes a first channel portion 421, a second channel portion 422 and a conductor portion 423, the conductor portion 423 is coupled to the first channel portion 421 and the second channel portion 422, respectively, the orthographic projection of the second conductive pattern BSM2 on the base substrate at least partially overlaps with the orthographic projection of the first channel portion 421 on the base substrate, and / or the orthographic projection of the second conductive pattern BSM2 on the base substrate at least partially overlaps with the orthographic projection of the second channel portion 422 on the base substrate.

[0119] Illustratively, an orthographic projection of the first channel portion 421 on the base substrate at least partially overlaps with an orthographic projection of the gate of the compensation transistor T2 on the base substrate. An orthographic projection of the second channel portion 422 on the base substrate at least partially overlaps with an orthographic projection of the gate of the compensation transistor T2 on the base substrate.

[0120] The above configuration enables the compensation transistor T2 and the second conductive pattern BSM2 to further form a dual-gate structure, making the characteristics of the compensation transistor T2 more stable, thereby better meeting the reliability and yield of display products in harsh environments such as high temperature and high humidity.

[0121] As shown in FIG3 to FIG8 , in some embodiments, the display substrate further includes a data line DA, and the transistor structure further includes a data writing transistor T4. The gate of the data writing transistor T4 is coupled to the corresponding scan line GA, the first electrode of the data writing transistor T4 is coupled to the corresponding data line DA, and the second electrode of the data writing transistor T4 is coupled to the first electrode of the driving transistor T3. The data writing transistor T4 includes a data writing active layer 44.

[0122] The orthographic projection of the second conductive pattern BSM2 on the base substrate at least partially overlaps with the orthographic projection of the data writing active layer 44 on the base substrate.

[0123] Exemplarily, the display substrate includes a plurality of data lines DA, the data lines DA including at least a portion extending along the second direction, the data lines DA corresponding one-to-one to a plurality of columns of sub-pixel driving circuits, and the data lines DA are respectively coupled to the first electrodes of the data writing transistors T4 included in each sub-pixel driving circuit in a corresponding column of sub-pixel driving circuits.

[0124] Exemplarily, the scan line GA corresponds one-to-one to multiple rows of sub-pixel driving circuits, and the scan line GA is respectively coupled to the gate of the compensation transistor T2 and the gate of the data writing transistor T4 included in each sub-pixel driving circuit in the corresponding row of sub-pixel driving circuits.

[0125] In the display substrate provided in the above embodiment, the orthographic projection of the second conductive pattern BSM2 on the base substrate is arranged to at least partially overlap with the orthographic projection of the data write active layer 44 on the base substrate. The second conductive pattern BSM2 is coupled to the scan line GA in the peripheral region 20. In this way, the signal transmitted by the second conductive pattern BSM2 is the same as the signal transmitted by the scan line GA coupled to the gate of the data write transistor T4 with which it overlaps. In this way, the data write transistor T4 and the second conductive pattern BSM2 can together form a dual-gate structure, making the characteristics of the data write transistor T4 more stable, thereby better meeting the reliability and yield requirements of display products in harsh environments such as high temperature and high humidity.

[0126] As shown in FIG3 to FIG8 , in some embodiments, the plurality of sub-pixel driving circuits included in the plurality of sub-pixels are divided into a plurality of rows of sub-pixel driving circuits, and each row of sub-pixel driving circuits includes a plurality of sub-pixel driving circuits arranged along a first direction; the second conductive pattern BSM2 includes at least a portion extending along the first direction;

[0127] The orthographic projection of the second conductive pattern BSM2 on the substrate at least partially overlaps with the orthographic projection of the compensation active layer 42 included in each sub-pixel driving circuit in a corresponding row of sub-pixel driving circuits on the substrate; and / or, the orthographic projection of the second conductive pattern BSM2 on the substrate at least partially overlaps with the orthographic projection of the data writing active layer 44 included in each sub-pixel driving circuit in a corresponding row of sub-pixel driving circuits on the substrate.

[0128] The above configuration improves the characteristics of the compensation transistor T2 and the data writing transistor T4 in the display substrate while simplifying the structure of the display substrate and reducing the difficulty of the layout of the display substrate.

[0129] As shown in FIG16 , in some embodiments, the peripheral region 20 includes a left frame region and a right frame region disposed opposite to each other along the first direction, and the display region 10 is located between the left frame region and the right frame region; the display substrate further includes a second conductive connection portion 52;

[0130] In the left frame area and / or the right frame area, the second conductive connection portion 52 is coupled to the corresponding scan line GA, and the second conductive connection portion 52 is coupled to the corresponding second conductive pattern BSM2 through a second via hole Via2;

[0131] The second via Via2 includes a third sub-via and a fourth sub-via that are connected to each other. The third sub-via is located between the fourth sub-via and the base substrate. The orthographic projection of the hole wall of the third sub-via on the base substrate is surrounded by the orthographic projection of the fourth sub-via on the base substrate.

[0132] Exemplarily, the second via Via2 is manufactured by an ILD&EBB via process, which includes two process flows; after the interlayer insulating layer ILD is manufactured, an ILD via process is performed to form the fourth sub-via, and the fourth sub-via can at least penetrate the interlayer insulating layer ILD, and the fourth sub-via can further penetrate the second gate insulating layer GI2, the first gate insulating layer GI1 and at least one layer of the buffer layer BUF, and the fourth sub-via can also partially penetrate the barrier layer Bar; then an EBB via process is performed to completely penetrate the remaining film layers until the conductive layer BSM is exposed to form the third sub-via.

[0133] Exemplarily, the third sub-via and the fourth sub-via are jointly formed into a stepped trepanning design, and the aperture of the fourth sub-via is larger than that of the third sub-via. The specific aperture size is subject to process capabilities. For example, in a direction parallel to the substrate, on at least one side of the second via Via2, the distance between the orthographic projection of the hole wall of the fourth sub-via on the substrate and the orthographic projection of the hole wall of the third sub-via on the substrate is greater than or equal to 1 micron, ensuring that the orthographic projection of the hole wall of the third sub-via on the substrate is surrounded by the orthographic projection of the fourth sub-via on the substrate.

[0134] The above-mentioned arrangement is in the left frame area and / or the right frame area, and the second conductive connection part 52 is coupled to the corresponding scan line GA, and the second conductive connection part 52 is coupled to the corresponding second conductive pattern BSM2 through the second via Via2; so that the second conductive pattern BSM2 can be coupled to the scan line GA on the left and right sides of the display area 10, and the second conductive pattern BSM2 can pass through the display area 10 along the first direction, thereby ensuring the signal transmission uniformity of the second conductive pattern BSM2 and the characteristic stability of each overlapping transistor structure.

[0135] The second via hole Via2 is configured to adopt a sleeve hole structure, which not only ensures the manufacturing yield of the second via hole Via2, but also ensures the connection performance between the second conductive pattern BSM2 and the second conductive connecting portion 52.

[0136] As shown in FIG10 to FIG12 , in some embodiments, the display substrate further includes a scan line GA, the signal transmission line 30 includes a first initialization signal line Vinit1, the transistor structure includes a driving transistor T3 and a compensation transistor T2, the gate of the compensation transistor T2 is coupled to the corresponding scan line GA, the first electrode of the compensation transistor T2 is coupled to the second electrode of the driving transistor T3, and the second electrode of the compensation transistor T2 is coupled to the gate of the driving transistor T3; the compensation transistor T2 includes a compensation active layer 42;

[0137] The conductive layer BSM includes a third conductive pattern BSM3, the orthographic projection of the third conductive pattern BSM3 on the base substrate at least partially overlaps with the orthographic projection of the compensation active layer 42 on the base substrate, and the third conductive pattern BSM3 is coupled to the first initialization signal line Vinit1 in the peripheral area 20.

[0138] Exemplarily, the compensation active layer 42 includes a first channel portion 421 , a second channel portion 422 and a conductor portion 423 , wherein the conductor portion 423 is coupled to the first channel portion 421 and the second channel portion 422 , respectively.

[0139] The orthographic projection of the third conductive pattern BSM3 on the substrate at least partially overlaps with the orthographic projection of the first channel portion 421 on the substrate; and / or, the orthographic projection of the third conductive pattern BSM3 on the substrate at least partially overlaps with the orthographic projection of the second channel portion 422 on the substrate; and / or, the orthographic projection of the third conductive pattern BSM3 on the substrate at least partially overlaps with the orthographic projection of the conductor portion 423 on the substrate.

[0140] The above-mentioned setting method enables the third conductive pattern BSM3 to also transmit the first initialization signal with a stable potential. In this way, the third conductive pattern BSM3 can shield the compensation transistor T2 overlapping with it, and can shield the influence of the magnetic field and electric field generated by the touch when the display product is used for high-frequency touch on the compensation transistor T2. At the same time, it can shield the influence of the magnetic field and electric field formed by the conductive structure inside the display substrate on the compensation transistor T2.

[0141] As shown in FIG10 to FIG12 , in some embodiments, the plurality of sub-pixel driving circuits included in the plurality of sub-pixels are divided into a plurality of rows of sub-pixel driving circuits, and each row of sub-pixel driving circuits includes a plurality of sub-pixel driving circuits arranged along a first direction; the third conductive pattern BSM3 includes at least a portion extending along the first direction; the third conductive pattern BSM3 includes a main portion BSM31 and a plurality of protrusions BSM32 respectively coupled to the main portion BSM31;

[0142] The main body portion BSM31 includes at least a portion extending along a first direction, the main body portion BSM31 is coupled to the first initialization signal line Vinit1 in the peripheral area 20, and an orthographic projection of the main body portion BSM31 on the base substrate does not overlap with an orthographic projection of at least one of the first channel portion 421, the second channel portion 422, and the conductor portion 423 on the base substrate;

[0143] The multiple protrusions BSM32 correspond one-to-one to each compensation active layer 42 in a corresponding row of sub-pixel driving circuits; the orthographic projection of the protrusion BSM32 on the base substrate at least partially overlaps with the orthographic projection of the first channel portion 421 included in the corresponding compensation active layer 42 on the base substrate; and / or, the orthographic projection of the protrusion BSM32 on the base substrate at least partially overlaps with the orthographic projection of the second channel portion 422 included in the corresponding compensation active layer 42 on the base substrate; and / or, the orthographic projection of the protrusion BSM32 on the base substrate at least partially overlaps with the orthographic projection of the conductor portion 423 included in the corresponding compensation active layer 42 on the base substrate.

[0144] Exemplarily, the main body BSM31 and the plurality of protrusions BSM32 respectively coupled to the main body BSM31 form an integral structure, but the present invention is not limited thereto.

[0145] The above configuration is conducive to reducing the layout difficulty of the third conductive pattern BSM3, reducing the overlapping area between the main body BSM31 and other conductive structures in the display area 10, and reducing the parasitic capacitance generated by the third conductive pattern BSM3.

[0146] As shown in Figure 12, in some embodiments, the peripheral area 20 includes a left border area and a right border area arranged opposite to each other along a first direction, and the display area 10 is located between the left border area and the right border area; the display substrate also includes a first initialization bus 61 located in the left border area and / or the right border area, and the first initialization bus 61 includes at least a portion extending along the second direction, and in the left border area and / or the right border area, the main body BSM31 and the first initialization signal line Vinit1 are respectively coupled to the first initialization bus 61.

[0147] It should be noted that FIG12 also illustrates a second initialization bus 62 , which is coupled to the second initialization signal line Vinit2 .

[0148] Exemplarily, the display substrate includes the first initialization bus 61 located in the left frame area, and further includes the first initialization bus 61 located in the right frame area.

[0149] Exemplarily, the main body BSM31 is coupled to the first initialization bus 61 via a third via Via3. The third via Via3 includes a fifth sub-via and a sixth sub-via that are connected. The fifth sub-via is located between the sixth sub-via and the base substrate. The orthographic projection of the hole wall of the fifth sub-via on the base substrate is surrounded by the orthographic projection of the sixth sub-via on the base substrate. It is worth noting that the specific manufacturing process of the third via Via3 is the same as that of the first via Via1 and the second via Via2 described above and will not be repeated here.

[0150] The above-mentioned arrangement is in the left frame area and / or the right frame area, and the main body BSM31 and the first initialization signal line Vinit1 are respectively coupled to the first initialization bus 61; so that the third conductive pattern BSM3 can be coupled to the first initialization bus 61 on the left and right sides of the display area 10, and the third conductive pattern BSM3 can penetrate the display area 10 along the first direction, thereby ensuring the signal transmission uniformity of the third conductive pattern BSM3 and the characteristic stability of each overlapping transistor structure.

[0151] The third via hole is configured to adopt a sleeve hole structure, which not only ensures the manufacturing yield of the third via hole, but also ensures the connection performance between the third conductive pattern BSM3 and the first initialization bus 61.

[0152] As shown in Figures 9 and 12, in some embodiments, the conductive layer BSM also includes a first connecting line BSM-L1, which is at least partially arranged around the display area 10, and the first connecting line BSM-L1 is respectively coupled to the two ends of each of the main parts BSM31 in the display substrate.

[0153] For example, the orthographic projection of the first connecting line BSM-L1 on the base substrate at least partially overlaps with the orthographic projection of the first initialization bus 61 on the base substrate. This arrangement is conducive to narrowing the frame of the display substrate.

[0154] Exemplarily, the first connecting line BSM-L1 surrounds the display area 10 , but is not limited thereto.

[0155] The above-mentioned arrangement of coupling the first connecting line BSM-L1 to both ends of each main body portion BSM31 in the display substrate is beneficial to further improve the uniformity of signal transmission of each third conductive pattern BSM3, thereby better improving the display quality of the display substrate.

[0156] It is worth noting that Figures 12 and 16 correspond to two different implementation schemes. To better achieve compatibility between the two implementation schemes, the adapter used in Figure 16 is retained in Figure 12, and the adapter used in Figure 12 is retained in Figure 16. The adapter is on the same layer as the first source / drain metal layer SD1 or the same layer as the conductive layer BSM, but is not limited thereto.

[0157] In some embodiments, the peripheral area 20 further includes a first fan-out area Fan1 and a second fan-out area Fan2, the first fan-out area Fan1 being located between the display area and the second fan-out area Fan2; the display substrate further includes a plurality of data lines DA and a plurality of data fan-out lines DAS, the data fan-out lines DAS being coupled to the corresponding data lines DA, at least a portion of the data lines DA being located in the display area 10, at least a portion of the data fan-out lines DAS being located in the first fan-out area Fan1 and the second fan-out area Fan2, a density of the data fan-out lines DAS in the first fan-out area Fan1 being less than a density of the fan-out lines in the second fan-out area Fan2, and a first connecting line BSM-L1 being located between the second fan-out area Fan2 and the display area 10.

[0158] The above configuration helps reduce the overlapping area between the first connecting line BSM-L1 and the fan-out line, reduces the parasitic capacitance generated between the first connecting line BSM-L1 and the fan-out line, and helps improve the uniformity of signal transmission of the third conductive pattern BSM3.

[0159] As shown in Figures 3 to 8 and Figures 13 to 16, in some embodiments, the transmission signal line includes a power connection line VDDL located in the peripheral area 20, the transistor structure includes a driving transistor T3, and the driving transistor T3 includes a driving active layer 43; the conductive layer BSM includes a fourth conductive pattern BSM4, the orthographic projection of the fourth conductive pattern BSM4 on the substrate at least partially overlaps with the orthographic projection of the driving active layer 43 on the substrate, and the fourth conductive pattern BSM4 is coupled to the power connection line VDDL.

[0160] Exemplarily, the driving active layer 43 includes a driving channel portion, and an orthographic projection of the fourth conductive pattern BSM4 on the base substrate at least partially overlaps with an orthographic projection of the driving channel portion on the base substrate.

[0161] The above-mentioned configuration enables the fourth conductive pattern BSM4 to also transmit a power signal with a stable potential. In this way, the fourth conductive pattern BSM4 can shield the driving transistor T3 overlapping with it, thereby shielding the driving transistor T3 from the influence of the magnetic field and electric field generated by the touch when the display product is used for high-frequency touch. At the same time, it can shield the driving transistor T3 from the influence of the magnetic field and electric field formed by the conductive structure inside the display substrate.

[0162] As shown in FIG. 13 to FIG. 16 , in some embodiments, the peripheral area 20 includes an upper frame area and a lower frame area disposed opposite to each other along the second direction, and the display area 10 is located between the upper frame area and the lower frame area;

[0163] The power connection line VDDL is located in the upper frame area and / or the lower frame area; the conductive layer BSM also includes a second connection line BSM-L2, at least part of the second connection line BSM-L2 is arranged around the display area 10, the second connection line BSM-L2 is coupled to the power connection line VDDL in the upper frame area and / or the lower frame area, and the second connection line BSM-L2 is respectively coupled to the two ends of each of the fourth conductive patterns BSM4 in the display substrate.

[0164] Exemplarily, as shown in FIG14 , the second connection line BSM-L2 is coupled to the power line VDD in the lower frame area.

[0165] Exemplarily, the second connecting line BSM-L2 surrounds the display area 10 , but is not limited thereto.

[0166] Exemplarily, the display substrate includes two power connection lines VDDL, one power connection line VDDL is located in the upper frame area, and the other power connection line VDDL is located in the lower frame area, and the two power connection lines VDDL are arranged opposite to each other along the second direction.

[0167] Exemplarily, the second connection line BSM-L2 is coupled to the power connection line VDDL in the upper frame area and / or the lower frame area through a fourth via Via4, and the fourth via Via4 includes a seventh sub-via and an eighth sub-via coupled, and the seventh sub-via is located between the eighth sub-via and the base substrate, and the orthographic projection of the hole wall of the seventh sub-via on the base substrate is surrounded by the orthographic projection of the hole wall of the eighth sub-via on the base substrate. It is worth noting that the specific manufacturing process of the fourth via Via4 is the same as that of the first via Via1 and the second via Via2 mentioned above, and will not be repeated here.

[0168] The above-mentioned second connection line BSM-L2 is at least partially arranged around the display area 10, and the second connection line BSM-L2 is coupled to the power connection line VDDL in the upper frame area and / or the lower frame area, and the second connection line BSM-L2 is respectively coupled to the two ends of each of the fourth conductive graphics BSM4 in the display substrate, so that the second connection line BSM-L2 can be connected to the power connection line VDDL in the upper frame area and / or the lower frame area, receive the power signal transmitted by the power connection line VDDL, and the second connection line BSM-L2 goes around to the left frame area and the right frame area to achieve coupling with each of the fourth conductive graphics BSM4, and transmits the power signal to the fourth conductive graphics BSM4, so as to better improve the uniformity of the signal transmitted by each of the fourth conductive graphics BSM4, thereby better improving the display quality of the display substrate.

[0169] The fourth via hole is configured to adopt a sleeve hole structure, which not only ensures the manufacturing yield of the fourth via hole, but also ensures the connection performance between the second connecting line BSM-L2 and the power connecting line VDDL.

[0170] As shown in Figure 18, in some embodiments, the peripheral area 20 also includes a first fan-out area Fan1 and a second fan-out area Fan2, and the first fan-out area Fan1 is located between the display area 10 and the second fan-out area Fan2; the display substrate also includes a plurality of data lines DA and a plurality of data fan-out lines DAS, the data fan-out lines DAS are coupled to the corresponding data lines DA, at least part of the data lines DA are located in the display area 10, and at least part of the data fan-out lines DAS are located in the first fan-out area Fan1 and the second fan-out area Fan2, and the data fan-out line DAS density of the first fan-out area Fan1 is less than the fan-out line density of the second fan-out area Fan2; the second connecting line BSM-L2 is located between the second fan-out area Fan2 and the display area 10.

[0171] The above configuration helps reduce the overlapping area between the second connecting line BSM-L2 and the data fan-out line DAS, reduces the parasitic capacitance generated between the second connecting line and the fan-out line, and helps improve the uniformity of signal transmission of the fourth conductive pattern.

[0172] As shown in FIG3 to FIG8 and FIG13 to FIG16, in some embodiments, the plurality of sub-pixel driving circuits included in the plurality of sub-pixels are divided into a plurality of rows of sub-pixel driving circuits, and each row of sub-pixel driving circuits includes a plurality of sub-pixel driving circuits arranged along a first direction; the second conductive pattern BSM2 includes at least a portion extending along the first direction;

[0173] The orthographic projection of the fourth conductive pattern BSM4 on the base substrate at least partially overlaps with the orthographic projection of the driving active layer 43 included in each sub-pixel driving circuit in a corresponding row of sub-pixel driving circuits on the base substrate.

[0174] Exemplarily, the fourth conductive pattern BSM4 penetrates the display area 10 along the first direction, but is not limited thereto.

[0175] The above configuration improves the stability of the driving transistor T3 in the display substrate while simplifying the structure of the display substrate and reducing the difficulty of the layout of the display substrate.

[0176] As shown in Figures 2, 3 and 10, in some embodiments, the display substrate further includes an interlayer insulating layer ILD, and the interlayer insulating layer ILD has a plurality of connection holes LVia; the orthographic projection of the conductive layer BSM on the base substrate does not overlap with the orthographic projection of the hole wall of the connection hole LVia on the base substrate.

[0177] Exemplarily, the multiple connection holes LVia include vias for connecting the active layer poly and the first source and drain metal layer SD1, vias for connecting the first gate insulating layer GI1 and the first source and drain metal layer SD1, and vias for connecting the second gate insulating layer GI2 and the first source and drain metal layer SD1.

[0178] Since the conductive layer BSM is produced first and the connecting hole LVia is produced later, during the process of forming the connecting hole LVia, the accumulated static electricity may be directed to the conductive layer BSM, causing damage to the conductive layer BSM. The above-mentioned setting makes the orthographic projection of the conductive layer BSM on the base substrate and the orthographic projection of the hole wall of the connecting hole LVia on the base substrate not overlap, so that the distance between the conductive layer BSM and the connecting hole LVia is relatively far, which can effectively avoid the above-mentioned problem.

[0179] As shown in Figure 18, in some embodiments, the interlayer insulating layer also includes a plurality of virtual compensation holes XVia, and the virtual compensation holes XVia are located in the display area 10 and / or the peripheral area 20, and the orthographic projection of the conductive layer BSM on the base substrate does not overlap with the orthographic projection of the hole wall of the virtual compensation hole XVia on the base substrate.

[0180] For example, the virtual compensation holes XVia are generally designed to ensure uniformity in the layout of the display substrate. The virtual compensation holes XVia may be arranged in various locations, for example, within the display area 10 at a corner of the display substrate and / or within the peripheral area 20 at the corner, but are not limited thereto. The corners include, but are not limited to, the upper left corner, the upper right corner, the lower left corner, and the lower right corner.

[0181] The above-mentioned setting makes the orthographic projection of the conductive layer BSM on the base substrate not overlap with the orthographic projection of the hole wall of the virtual compensation hole XVia on the base substrate, so that the distance between the conductive layer BSM and the virtual compensation hole XVia is relatively far. In this way, when making the virtual compensation hole XVia, it is possible to avoid the accumulated static electricity from being directed to the conductive layer BSM, thereby avoiding damaging the conductive layer BSM.

[0182] As shown in FIG1 , in some embodiments, the display substrate includes a power line VDD, a data line DA, a first initialization signal line Vinit1, a second initialization signal line Vinit2, a first reset signal line Rst, a scan line GA, and an emission control signal line EM. The sub-pixel driving circuit includes a driving transistor T3, a first reset transistor T1, a second reset transistor T7, a compensation transistor T2, a data writing transistor T4, a power control transistor T5, an emission control transistor T6, and a storage capacitor Cst.

[0183] The gate of the first reset transistor T1 is coupled to the corresponding first reset signal line Rst, the first electrode of the first reset transistor T1 is coupled to the corresponding first initialization signal line Vinit1, and the second electrode of the first reset transistor T1 is coupled to the gate T3-g of the driving transistor T3.

[0184] The gate of the compensation transistor T2 is coupled to the corresponding scan line GA, the first electrode of the compensation transistor T2 is coupled to the second electrode of the driving transistor T3, and the second electrode of the compensation transistor T2 is coupled to the gate T3-g of the driving transistor T3.

[0185] A gate of the data writing transistor T4 is coupled to the corresponding scan line GA1 , a first electrode of the data writing transistor T4 is coupled to the corresponding data line DA, and a second electrode of the data writing transistor T4 is coupled to the first electrode of the driving transistor T3 .

[0186] The gate of the power control transistor T5 is coupled to the corresponding light emitting control signal line EM, the first electrode of the power control transistor T5 is coupled to the corresponding power line VDD, and the second electrode of the power control transistor T5 is coupled to the first electrode of the driving transistor T3.

[0187] The gate of the light-emitting control transistor T6 is coupled to the corresponding light-emitting control signal line EM, the first electrode of the light-emitting control transistor T6 is coupled to the second electrode of the driving transistor T3, and the second electrode of the light-emitting control transistor T6 is coupled to the anode of the corresponding light-emitting element. The cathode of the light-emitting element transmits the VSS signal.

[0188] A gate of the second reset transistor T7 is coupled to a first reset signal line Rst′ connected to a sub-pixel driving circuit adjacent to the second direction.

[0189] The first plate Cst1 of the storage capacitor Cst is multiplexed as the gate of the driving transistor T3 , and the second plate Cst2 of the storage capacitor Cst is coupled to the power line VDD.

[0190] As shown in FIG3 and FIG10 , the power control active layer 45 included in the power control transistor T5 and the light emission control active layer 46 included in the light emission control transistor T6 are also shown.

[0191] As shown in Figure 4, the second initialization connection line Vinit2' and the first initialization connection line Vinit1' are illustrated. The second initialization connection line Vinit2' is coupled to each second initialization signal line Vinit2, forming a grid structure. The first initialization connection line Vinit1' is coupled to each first initialization signal line Vinit1, forming a grid structure.

[0192] As shown in Figure 5 , the figure shows a third conductive connection portion 53, a fourth conductive connection portion 54, a fifth conductive connection portion 55, a sixth conductive connection portion 56 and a seventh conductive connection portion 57. As shown in Figures 6 and 7 , the figure shows an eighth conductive connection portion 58.

[0193] As shown in Figures 4 to 7, the third conductive connection portion 53 is respectively coupled to the second electrode of the light-emitting control transistor T6 and the eighth conductive connection portion 58, and the eighth conductive connection portion 58 is coupled to the anode of the light-emitting element. The fourth conductive connection portion 54 is respectively coupled to the first electrode of the data write transistor T4 and the data line DA. The fifth conductive connection portion 55 is respectively coupled to the gate of the drive transistor T3, the second electrode of the first reset transistor T1, and the second electrode of the compensation transistor T2. The sixth conductive connection portion 56 is respectively coupled to the second initialization signal line Vinit2 and the first electrode of the second reset transistor T7. The seventh conductive connection portion 57 is respectively coupled to the first initialization signal line Vinit1 and the first electrode of the first reset transistor T1.

[0194] As shown in FIG6 and FIG7 , the figures illustrate the compensation power line VDD′, which is coupled to the corresponding power line VDD through a via hole (such as a larger square hole in the figure) penetrating the second planar layer.

[0195] An embodiment of the present disclosure further provides a display device, comprising the display substrate provided by the above embodiment.

[0196] It should be noted that the display device can be any product or component with a display function, such as a television, a monitor, a digital photo frame, a mobile phone, a tablet computer, etc., wherein the display device also includes a flexible circuit board, a printed circuit board and a backplane.

[0197] Exemplarily, the display device includes an active matrix organic light emitting diode display device, but is not limited thereto.

[0198] According to the specific structure of the display substrate described above, in the display substrate provided by the embodiments of the present disclosure, the orthographic projection of the conductive layer on the base substrate at least partially overlaps with the orthographic projection of the transistor structure on the base substrate, at least a portion of the conductive layer is located between the transistor structure and the base substrate of the display substrate, and the conductive layer is coupled to the signal transmission line in the peripheral region. When the signal transmission line transmits a DC voltage signal with a stable potential, the conductive layer also transmits a DC voltage signal with a stable potential. In this way, the conductive layer can shield the transistor structure with which it overlaps, shielding the transistor structure from the effects of magnetic and electric fields generated by touch control during high-frequency touch operation of the display product, and also shielding the transistor structure from the effects of magnetic and electric fields generated by the conductive structure within the display substrate. When the signal transmission line is coupled to the gate of the transistor structure, the signal transmitted by the conductive layer is the same as the signal transmitted by the signal transmission line coupled to the gate of the overlapping transistor structure. In this way, the transistor structure and the conductive layer can together form a dual-gate structure, making the characteristics of the transistor structure more stable, thereby better meeting the reliability and yield requirements of display products in harsh environments such as high temperature and high humidity. Therefore, the display substrate provided by the embodiment of the present disclosure can achieve better display quality and avoid problems such as green display screen.

[0199] It should be noted that the signal line extending along the X-direction means that the signal line includes a main portion and a secondary portion connected to the main portion, the main portion is a line, a line segment, or a strip-shaped body, the main portion extends along the X-direction, and the length of the main portion extending along the X-direction is greater than the length of the secondary portion extending along other directions.

[0200] It should be noted that the layout area occupied by each sub-pixel driving circuit may be an area that can accommodate the sub-pixel driving circuit. Exemplarily, the area may be a rectangular area, but is not limited thereto.

[0201] It should be noted that the "same layer" in the embodiment of the present disclosure may refer to a film layer on the same structural layer. Or, for example, a film layer in the same layer may be a film layer formed by using the same film forming process to form a specific pattern, and then patterning the film layer using the same mask through a single composition process to form a layer structure. Depending on the specific pattern, a single composition process may include multiple exposure, development or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous. These specific patterns may also be at different heights or have different thicknesses.

[0202] In the various method embodiments of the present disclosure, the serial numbers of the steps cannot be used to limit the order of the steps. For ordinary technicians in this field, without paying any creative work, changes to the order of the steps are also within the scope of protection of the present disclosure.

[0203] It should be noted that the various embodiments in this specification are described in a progressive manner. Similar parts between the various embodiments can be referred to in conjunction with each other. Each embodiment focuses on the differences from other embodiments. In particular, the method embodiments are described briefly because they are generally similar to the product embodiments. For relevant parts, refer to the description of the product embodiments.

[0204] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by persons of ordinary skill in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect", "couple" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0205] It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” or “under” another element, it can be “directly on” or “under” the other element or intervening elements may be present.

[0206] In the description of the above embodiments, specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.

[0207] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A display substrate, comprising a display area and a peripheral area located around the display area, and a plurality of sub-pixels located in the display area, wherein the sub-pixels include a sub-pixel driving circuit, and the sub-pixel driving circuit includes a transistor structure; the display substrate further comprises: A conductive layer and a signal transmission line, wherein the orthographic projection of the conductive layer on the base substrate at least partially overlaps with the orthographic projection of the transistor structure on the base substrate, and at least a portion of the conductive layer is located between the transistor structure and the base substrate of the display substrate; the conductive layer and the signal transmission line are coupled in the peripheral area.

2. The display substrate according to claim 1, wherein: The display substrate further includes a first initialization signal line, the signal transmission line includes a first reset signal line, the transistor structure includes a driving transistor and a first reset transistor, a gate of the first reset transistor is coupled to the corresponding first reset signal line, a first electrode of the first reset transistor is coupled to the corresponding first initialization signal line, and a second electrode of the first reset transistor is coupled to the gate of the driving transistor; the first reset transistor includes a first reset active layer; The conductive layer includes a first conductive pattern, an orthographic projection of the first conductive pattern on the base substrate at least partially overlaps with an orthographic projection of the first reset active layer on the base substrate, and the first conductive pattern is coupled to the first reset signal line in the peripheral area.

3. The display substrate according to claim 2, wherein: The display substrate further includes a second initialization signal line, the sub-pixel further includes a light-emitting element, the transistor structure further includes a second reset transistor, a gate of the second reset transistor is coupled to a first reset signal line coupled to a first reset transistor in a sub-pixel adjacent to the second direction, a first electrode of the second reset transistor is coupled to the corresponding second initialization signal line, and a second electrode of the second reset transistor is coupled to an anode of the light-emitting element; the second reset transistor includes a second reset active layer; An orthographic projection of the first conductive pattern on the base substrate at least partially overlaps with an orthographic projection of the second reset active layer on the base substrate.

4. The display substrate according to claim 3, wherein: The plurality of sub-pixel driving circuits included in the plurality of sub-pixels are divided into a plurality of rows of sub-pixel driving circuits, and each row of sub-pixel driving circuits includes a plurality of sub-pixel driving circuits arranged along a first direction; the first conductive pattern includes at least a portion extending along the first direction; The orthographic projection of the first conductive pattern on the substrate at least partially overlaps with the orthographic projection of the first reset active layer included in each sub-pixel driving circuit in a corresponding row of sub-pixel driving circuits on the substrate; and / or the orthographic projection of the first conductive pattern on the substrate at least partially overlaps with the orthographic projection of the second reset active layer included in each sub-pixel driving circuit in an adjacent upper row of sub-pixel driving circuits on the substrate.

5. The display substrate according to claim 4, wherein: The peripheral area includes a left frame area and a right frame area which are arranged opposite to each other along the first direction, and the display area is located between the left frame area and the right frame area; the display substrate also includes a first conductive connection portion; In the left frame area and / or the right frame area, the first conductive connection portion is coupled to the corresponding first reset signal line, and the first conductive connection portion is coupled to the corresponding first conductive pattern through a first via hole; The first via hole includes a first sub-via hole and a second sub-via hole that are connected to each other. The first sub-via hole is located between the second sub-via hole and the base substrate. The orthographic projection of the hole wall of the first sub-via hole on the base substrate is surrounded by the orthographic projection of the second sub-via hole on the base substrate.

6. The display substrate according to claim 1, wherein: The signal transmission line includes a scan line, the transistor structure includes a driving transistor and a compensation transistor, the gate of the compensation transistor is coupled to the corresponding scan line, the first electrode of the compensation transistor is coupled to the second electrode of the driving transistor, and the second electrode of the compensation transistor is coupled to the gate of the driving transistor; the compensation transistor includes a compensation active layer; The conductive layer includes a second conductive pattern, an orthographic projection of the second conductive pattern on the base substrate at least partially overlaps with an orthographic projection of the compensation active layer on the base substrate, and the second conductive pattern is coupled to the scan line in the peripheral area.

7. The display substrate according to claim 6, wherein: The compensation transistor comprises a dual-gate transistor, the compensation active layer comprises a first channel portion, a second channel portion and a conductor portion, the conductor portion is coupled to the first channel portion and the second channel portion respectively, the orthographic projection of the second conductive pattern on the substrate substrate at least partially overlaps with the orthographic projection of the first channel portion on the substrate substrate, and / or the orthographic projection of the second conductive pattern on the substrate substrate at least partially overlaps with the orthographic projection of the second channel portion on the substrate substrate.

8. The display substrate according to claim 6, wherein: The display substrate further includes a data line, the transistor structure further includes a data writing transistor, a gate of the data writing transistor is coupled to the corresponding scanning line, a first electrode of the data writing transistor is coupled to the corresponding data line, and a second electrode of the data writing transistor is coupled to the first electrode of the driving transistor; the data writing transistor includes a data writing active layer; The orthographic projection of the second conductive pattern on the base substrate at least partially overlaps with the orthographic projection of the data writing active layer on the base substrate.

9. The display substrate according to claim 8, wherein: The plurality of sub-pixel driving circuits included in the plurality of sub-pixels are divided into a plurality of rows of sub-pixel driving circuits, and each row of sub-pixel driving circuits includes a plurality of sub-pixel driving circuits arranged along a first direction; the second conductive pattern includes at least a portion extending along the first direction; The orthographic projection of the second conductive pattern on the substrate at least partially overlaps with the orthographic projection of the compensation active layer included in each sub-pixel driving circuit in a corresponding row of sub-pixel driving circuits on the substrate; and / or the orthographic projection of the second conductive pattern on the substrate at least partially overlaps with the orthographic projection of the data writing active layer included in each sub-pixel driving circuit in a corresponding row of sub-pixel driving circuits on the substrate.

10. The display substrate according to claim 9, wherein: The peripheral area includes a left frame area and a right frame area which are arranged opposite to each other along the first direction, and the display area is located between the left frame area and the right frame area; the display substrate also includes a second conductive connection portion; In the left frame area and / or the right frame area, the second conductive connection portion is coupled to the corresponding scan line, and the second conductive connection portion is coupled to the corresponding second conductive pattern through a second via hole; The second via hole includes a third sub-via hole and a fourth sub-via hole that are connected to each other. The third sub-via hole is located between the fourth sub-via hole and the base substrate. The orthographic projection of the hole wall of the third sub-via hole on the base substrate is surrounded by the orthographic projection of the fourth sub-via hole on the base substrate.

11. The display substrate according to claim 1, wherein: The display substrate further comprises a scan line, the signal transmission line comprises a first initialization signal line, the transistor structure comprises a driving transistor and a compensation transistor, the gate of the compensation transistor is coupled to the corresponding scan line, the first electrode of the compensation transistor is coupled to the second electrode of the driving transistor, and the second electrode of the compensation transistor is coupled to the gate of the driving transistor; the compensation transistor comprises a compensation active layer; The conductive layer includes a third conductive pattern, an orthographic projection of the third conductive pattern on the base substrate at least partially overlaps with an orthographic projection of the compensation active layer on the base substrate, and the third conductive pattern is coupled to the first initialization signal line in the peripheral area.

12. The display substrate according to claim 11, wherein: The compensation active layer includes a first channel portion, a second channel portion and a conductor portion, and the conductor portion is coupled to the first channel portion and the second channel portion respectively; The orthographic projection of the third conductive pattern on the substrate at least partially overlaps with the orthographic projection of the first channel portion on the substrate; And / or, an orthographic projection of the third conductive pattern on the substrate at least partially overlaps with an orthographic projection of the second channel portion on the substrate; And / or, an orthographic projection of the third conductive pattern on the base substrate at least partially overlaps with an orthographic projection of the conductor portion on the base substrate.

13. The display substrate according to claim 12, wherein: The plurality of sub-pixel driving circuits included in the plurality of sub-pixels are divided into a plurality of rows of sub-pixel driving circuits, and each row of sub-pixel driving circuits includes a plurality of sub-pixel driving circuits arranged along a first direction; the third conductive pattern includes at least a portion extending along the first direction; the third conductive pattern includes a main body portion, and a plurality of protrusions respectively coupled to the main body portion; The main body portion includes at least a portion extending along a first direction, the main body portion is coupled to the first initialization signal line in the peripheral region, and an orthographic projection of the main body portion on the base substrate does not overlap with an orthographic projection of at least one of the first channel portion, the second channel portion, and the conductor portion on the base substrate; The plurality of protrusions correspond one-to-one to each compensation active layer in a corresponding row of sub-pixel driving circuits; an orthographic projection of the protrusion on the substrate at least partially overlaps with an orthographic projection of the first channel portion included in the corresponding compensation active layer on the substrate; And / or, an orthographic projection of the protrusion on the substrate at least partially overlaps with an orthographic projection of the second channel portion included in the corresponding compensation active layer on the substrate; And / or, an orthographic projection of the protrusion on the substrate at least partially overlaps with an orthographic projection of the conductor portion included in the corresponding compensation active layer on the substrate.

14. The display substrate according to claim 13, wherein: The peripheral area includes a left frame area and a right frame area arranged relatively to each other along a first direction, and the display area is located between the left frame area and the right frame area; the display substrate also includes a first initialization bus located in the left frame area and / or the right frame area, the first initialization bus includes at least a portion extending along the second direction, and in the left frame area and / or the right frame area, the main body and the first initialization signal line are respectively coupled to the first initialization bus.

15. The display substrate according to claim 14, wherein: The main body is coupled to the first initialization bus through a third via, the third via includes a fifth sub-via and a sixth sub-via that are connected, the fifth sub-via is located between the sixth sub-via and the base substrate, and the orthographic projection of the hole wall of the fifth sub-via on the base substrate is surrounded by the orthographic projection of the sixth sub-via on the base substrate.

16. The display substrate according to claim 14, wherein: The conductive layer further includes a first connection line, which is at least partially arranged around the display area, and the first connection line is respectively coupled to two ends of each of the main body parts in the display substrate.

17. The display substrate according to claim 16, wherein: An orthographic projection of the first connection line on the substrate at least partially overlaps with an orthographic projection of the first initialization bus on the substrate.

18. The display substrate according to claim 1, wherein: The transmission signal line includes a power connection line located in the peripheral area, the transistor structure includes a driving transistor, and the driving transistor includes a driving active layer; the conductive layer includes a fourth conductive pattern, the orthographic projection of the fourth conductive pattern on the substrate at least partially overlaps with the orthographic projection of the driving active layer on the substrate, and the fourth conductive pattern is coupled to the power connection line.

19. The display substrate according to claim 18, wherein: The peripheral area includes an upper frame area and a lower frame area that are arranged opposite to each other along the second direction, and the display area is located between the upper frame area and the lower frame area; The power connection line is located in the upper frame area and / or the lower frame area; the conductive layer also includes a second connection line, at least part of the second connection line is arranged around the display area, the second connection line is coupled to the power connection line in the upper frame area and / or the lower frame area, and the second connection line is respectively coupled to both ends of each of the fourth conductive patterns in the display substrate.

20. The display substrate according to claim 19, wherein: The second connecting line is coupled to the power connecting line in the upper frame area and / or the lower frame area through a fourth via, the fourth via includes a seventh sub-via and an eighth sub-via coupled, the seventh sub-via is located between the eighth sub-via and the base substrate, and the orthographic projection of the hole wall of the seventh sub-via on the base substrate is surrounded by the orthographic projection of the hole wall of the eighth sub-via on the base substrate.

21. The display substrate according to claim 16 or 19, wherein: The peripheral area further includes a first fan-out area and a second fan-out area, the first fan-out area is located between the display area and the second fan-out area; the display substrate further includes a plurality of data lines and a plurality of data fan-out lines, the data fan-out lines are coupled to the corresponding data lines, at least a portion of the data lines is located in the display area, at least a portion of the data fan-out lines is located in the first fan-out area and the second fan-out area, and a data fan-out line density in the first fan-out area is less than a fan-out line density in the second fan-out area; The first connection line is located between the second fan-out area and the display area; or the second connection line is located between the second fan-out area and the display area.

22. The display substrate according to claim 18, wherein: The plurality of sub-pixel driving circuits included in the plurality of sub-pixels are divided into a plurality of rows of sub-pixel driving circuits, and each row of sub-pixel driving circuits includes a plurality of sub-pixel driving circuits arranged along a first direction; the second conductive pattern includes at least a portion extending along the first direction; The orthographic projection of the fourth conductive pattern on the base substrate at least partially overlaps with the orthographic projection of the driving active layer included in each sub-pixel driving circuit in a corresponding row of sub-pixel driving circuits on the base substrate.

23. The display substrate according to any one of claims 1 to 20, wherein: The display substrate further comprises an interlayer insulating layer having a plurality of connection holes; the orthographic projection of the conductive layer on the base substrate does not overlap with the orthographic projection of the hole wall of the connection hole on the base substrate.

24. The display substrate according to claim 23, wherein: The interlayer insulating layer also includes a plurality of virtual compensation holes, the virtual compensation holes are located in the display area and / or the peripheral area, and the orthographic projection of the conductive layer on the base substrate does not overlap with the orthographic projection of the hole wall of the virtual compensation hole on the base substrate.

25. A display device comprising the display substrate according to any one of claims 1 to 24.

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