Processed wafer and method for processing a plurality of optoelectronic devices

Abstract

The invention concerns a method for processing a plurality of optoelectronic device, in particular µLEDs, comprising the step of providing a growth substrate with a production region and a test structure regions. A plurality of devices having a functional layer with a first contact contacting the functional layer and facing away from the growth substrate are formed on the production region. Further, at least one test device is formed having the functional layer and a first and second contacts, each contacting the functional layer and facing away from the growth substrate. The at least one test device is a horizontal component. The wafer is rebonded to a carrier and processing is finalized to generate a plurality of vertical devices on the production region. The horizontal test device has the same functionality as the vertical devices and can easily be picked and placed for testing purposes.

Description

[0001] PROCESSED WAFER AND METHOD FOR PROCESSING A PLURALITY OF OPTOELECTRONIC DEVICES

[0002] The present invention concerns a processed wafer, in particular for vertical pLEDs and a method for processing a plurality of optoelectronic devices , in particular vertical pLEDs .

[0003] BACKGROUND

[0004] Modern lighting devices having dimensions of less than 50pm and even down to a few pm are referred to as pLEDs . Such pLEDs are mass produced on a growth substrate using epitaxial deposition techniques . While in some cases , one processes those pLEDs as monolithically integrated chip using a larger panel with a plurality of such integrated chip in subsequent steps , the pLEDs can also be separated and placed individually on a backplane for example . In such cases , it is not uncommon to rebond the pre-processed devices on wafer level to gain access to the growth substrate for further processing .

[0005] In addition to such manufacturing techniques , separate pLEDs can be associated in two classes referred to a vertical component and horizontal component . A vertical component is a component ( not necessarily a pLED, but any kind of semiconductor device ) that comprises its contacts on two opposing sides of the main semiconductor body . Hence , assembly of such devices require contacting the top surface as well , while the device is attached and connected with its bottom to a contact of a backplane for example . In case of vertical pLEDs , one of the contacts comprise a conductive transparent material as a portion of the contact area also forms an emission surface .

[0006] As an alternative , horizontal components comprise their respective contact areas on the same surface side . In case of horizontal optoelectronic components like horizontal pLEDs , the contacts are usually located opposite the main emission surface . It is an obj ect of the proposed principle to provide a method enabling vertical components to be tested without the increased effort as in conventional solutions .

[0007] SUMMARY OF THE INVENTION

[0008] This and other obj ects are addressed by the subj ect matter of the independent claims . Features and further aspects of the proposed principles are outlined in the dependent claims .

[0009] A common problem in vertical pLED manufacturing is that the produced pLEDs are not accessible for direct characterization measurements . Rather, they have to be picked and transferred to respective testing components to be placed there . This procedure may result in contamination of the surface , which can distort the measurement results .

[0010] On reason of the cumbersome procedure for testing lies in the fact , that the vertical pLEDs are typically arranged right after completion of the processing on some kind of release structure , being ready for transfer to their final application . Consequently, only one of the contacts pads are accessible for electrical measurements , which requires some picking and replacing on a new substrate and forming of a top contact and disregard the fact that characterization of individual pLED [e . g . absolute efficiency] on wafer level in this status is very difficult anyway .

[0011] One approach to overcome these problems is to transfer a few individual vertical pLEDs from various locations of the final production wafer to an intermediate substrate , on which the vertical pLEDs are electrically connected and subsequently electrically and optically characterized . Such electro optical characterization may comprise but is not limited to absolute brightness , far-field characteristics , forward voltage , color shifts .

[0012] The testing procedure requires an intermediate substrate and additional depositing and planarization steps , because only one of the contacts is connected to the intermediate test substrate . The top contact needs extra steps to be connected, including a planarization step in order to overcome the steep step on the edge of the vertical pLED, depositing a transparent ITO contact + an additional gold contact , and the like . After a correct contact , the pLED is characterized . The additional step requires time and more importantly, some characterization parameters may be influenced or under worst circumstances even corrupted due to the use of the transparent contact and the further process steps .

[0013] One could apply the same technology for the test chips as used for the other chip in their subsequent application, but this is even more cumbersome .

[0014] The inventors now propose a different approach . Instead of processing a wafer with vertical components and picking some of those , the test devices are implemented as horizontal components yet with the same functional layer as the vertical components . The vertical components can then be used for the product and the desired application, and the horizontal components are solely intended for the electro-optical characterization . It should be noted that both types of components are processed using mostly the same common techniques . The functional layer in the vertical and horizontal components is the same , hence both operate in the same manner and perform the same function . This enables transfer of the characterization and property results from the horizontal components to the vertical components , with or with only a very small adj ustment necessary .

[0015] However , the horizontal components may be easier to pick and place . They are significantly easier to contact as both contacts (p and n ) are facing to the new substrate . In case of optoelectronic devices and particularly pLEDs , the production of a pickable horizontal pLEDs as test devices in parallel to pickable vertical pLEDs are possible in one and the same process flow . The vertical pLEDs are here the product and the horizontal pLED is meant for EOC ( Electro optical characterization) . The proposed wafer as well as the method are not limited to optoelectronic devices and pLEDs but suitable for all kinds of semiconductor components that are implemented as vertical components irrespectively of size and function . In some aspects , the inventors propose a processed wafer with a plurality of semiconductor components , in particular pLEDs . The processed wafer comprises a carrier having defined one or more production regions and one or more test structure regions . Each of the one or more production regions comprise a plurality of pre-processed devices . The expression "pre-processed device" in this regard refers to a device that is either fully or at least partially be usable , at least to the extent that all semiconductor layers required for the desired functionality are present . Contacts to electrically contact the semiconductor layers required for the desired functionality are present . However , some process steps may still be missing, and the device has not been fully separated from the carrier .

[0016] Each of the pre-processed devices comprise a top surface and an opposing bottom surface , said bottom surface facing the carrier . Furthermore , each of the plurality of pre-processed devices comprises a functional layer stack, said functional layer stack in contact with a first contact on the bottom surface and a second contact on the top surface .

[0017] In accordance with the proposed principle , each of the one or more test structure regions also comprises at least one pre-processed test device . The pre-processed test device comprises a top surface and an opposing bottom surface , said bottom surface facing the carrier . The at least one pre-processed test device has been processed largely in the same manner as the plurality of pre-processed devices . Thus , the test device also comprises a functional layer stack, which comprises the same functionality in operation of the test device as the layer stack of the plurality of pre-processed devices . This will allow transferring the result of optical or electrical properties of the test device to the pre-processed devices .

[0018] The functional layer stack of the at least one test device is in contact with a first contact on the bottom surface of the at least one test device and a second contact on the bottom surface of the at least one test device laterally displaced to the first contact . Hence , in contrast to the pre-processed devices , the test device is implemented as a horizontal component . The proposed approach producing the pre-processed vertical components together with the horizontal test components on the same wafer or carrier utilizes the same chip processes and geometries . Geometry and structure of the vertical components and the horizontal components are similar ( i . e . the sizes may be a direct multiple of each other ) with the horizontal component using two electric contacts pointing in one and the same direction . This makes it easier to be bonded to a test substrate , in particularly like a "normal" Flip Chip ( horizontal LED emitting to the top and electrical contacts on the bottom) .

[0019] Therefore , this parallel produced horizontal component , i . e . in the form of pLED can be used very well for direct testing purposes as it can be transferred and bonded to a new substrate and directly measured without any additional and disturbing process steps and material like planarization and / or routing ITO .

[0020] If a manufacturer of components produces for sales or R&D purposes horizontal components in a separate chip flow ( flow H ) , in addition to the vertical components ( flow V) , the horizontal test components from flow V, as described within this application, may be mounted on the same intermediate substrate for testing as the horizontal components processed in flow H . This makes a comparison of the technologies from flow H and V considerably easier both in terms of effort / cost and obtained insight with regard to physical properties such as brightness , far-fields and degradation characteristics (use of same processes , substrates , ...) .

[0021] The size of the horizontal components in the vertical chip flow is adj ustable to cover an area corresponding to an area given by a multiple of any positive integer number with the pitch of a vertical component . Hence , only a very few adj ustments for mask layers and other mask templates are required .

[0022] In some aspects , the processed wafer comprises a plurality of devices which are at least partially separated by a mesa etched trench or recess . Hence , a partial mesa etch is conducted to partially separate the devices . Alternatively, each of the plurality of pre-processed device are separated from each other and the at least one pre-processed test device .

[0023] In some aspects , the bottom surface of the pre-processed devices and the at least one pre-processed test device are coupled to the carrier . However , this is not necessarily required . In some aspects , the first contacts of the pre-processed devices and at least one of the first and second contacts of the at least one pre-processed test device are connected to the carrier , in particular via a bond material . It is also possible to combine both approaches , that is , partially bond the bottom surface to the carrier and partially to one of the contacts .

[0024] In some aspects , the processed wafer comprises a plurality of anchor structures connecting the carrier with at least one of the bottom surface of each of the plurality of pre-processed devices , the first contacts of each of the plurality of pre-processed devices , the bottom surface of the at least one test device and / or at least one of the first contact and the second contact of the at least one test device . In other words , various coupling and anchoring points and structures are possible to connect the carrier to the pre-processed devices and the test devices . It may be suitable to use the same anchoring structure for the pre-processed devices and the test devices to avoid differences in the manufacturing method leading to differences in the electrical or optical properties .

[0025] In some aspects , the processed wafer further comprises a sacrificial material partially arranged between portions of the bottom and / or side surface of the pre-processed devices and the at least one test device and the carrier .

[0026] Some aspects concern the arrangement of the first and the second contact from each other . In order not to change the mas k layout and the mas k templates too much, it is proposed in some aspects that the second contact on the bottom surface of the at least one test device is laterally displaced to the first contact of the at least one test device by a distance that corresponds to a distance between two adj acent pre-processed devices . Hence , the distance between first and second contact may follow the pitch of the pre-processed devices . As an alternative , the distance between first and second contact may follow a multiple of the pitch of the pre-processed devices . In such embodiments , a distance between the first and second contact of the test device corresponds to a multiple of a distance between two adj acent pre-processed devices .

[0027] Another possible arrangement relates to the size and geometry of the test device . In some aspects , the at least one test device occupies an area on the carrier or wafer , which is substantially equal to a multiple of the area of one of the pre-processed test device , in particular 2 time or 3 times the area . In other words , the test device comprises a size substantially corresponding to 2 or 3 times the size of the pre- processed devices or the respective pitch thereof .

[0028] The functional layer of the original vertical device is usually configured to be contacted by contact on two opposing sides . However , as the at least one test device is a horizontal device , it is necessary to adj ust the contact structure in order to be able to contact the functional layer of the test device "from behind" . Therefore , it is proposed in some aspects to displace the first contact the first contact on the bottom surface not only laterally from the second contact on the bottom side but also vertically . The distance of the vertical displacement is such that one of the contacts is recessed with respect to the other by removing the functional layer including at least the p-doped side and the active layer above said contact .

[0029] This vertical displacement results in that the two contact are not arranged in the same horizontal plane , but substantially in two parallel planes . Consequently, when placing the test device with its contacts onto a flat surface plane , the test device will be slightly tilted . The tilt of the angle is still small and overall less than 5 ° and particularly less than 3 ° . By increasing the lateral distance between the first and second contact of the test device , one can further reduce the tilt angle . Some possible configurations of the test device and the respective tilt angel is illustrated herein . Reducing the tilt is beneficial , because testing optical parameters becomes more precise , as the pre-processed devices are usually not tilted .

[0030] Due to properties of the processing chamber ( s ) , the deposition of layers and thus the processing of devices may not occur fully homogenous , but gradients in dopants or other material can occur across the growth substrate . Also other variations of device parameters in up following chip flow are possible including for example CD variations , roughness , etching depths , metallization, thicknesses and dielectric material property variations to name a few . This issue is usually addressed by distribute several test regions with test devices across the growth substrate and wafer . Hence , in some cases , each of one or more production regions is associated with one or more test regions . By evaluating the properties of the test devices picked of those one or more test regions , one can deduce properties of the pre-processed devices on the production regions associated with the test regions .

[0031] In some aspects , the functional layer of the plurality of pre-processed devices and the at least one pre-processed test device is configured to emit light towards the top surface , thereby forming in particular a pLED . In such implementations , the functional layer may comprise a quantum well or a multi-quantum well , for example . The vertical and horizontal devices can comprise a quantum well intermixed sidewalls or regrown sidewalls to improve the IQE . Generally, apart from the different contact , all structural elements formed on the pre-processed devices should be conducted on the test device as well .

[0032] Some more aspects concern a method for processing a plurality of optoelectronic device , in particular pLEDs . The method comprises providing a growth substrate having defined one or more production regions and one or more test structure regions . The growth substrate can be one of the known substrates like sapphire , GaAs , GaN, GAP, Si and the like .

[0033] In the next step , one or more deposition steps are conducting to create a semiconductor layer stack . The layer sack is configured to perform a functionality when the devices are operated . For example , the layer stack may comprise a quantum well or a multi-quantum well structure to emit light of a certain wavelength . The layer stack may be the same within the one or more production regions and one or more test structure regions .

[0034] The one or more production regions are then structured to form a plurality of devices with the functional layer . A first contact contacts the functional layer and facing away from the growth substrate . In a similar fashion and usually parallel to the structuring of the one or more production regions , the one or more test structure regions are structured to form at least one test device having the functional layer and a first contact and a second contact . The first and second contact are contacting the functional layer and both contacts are facing away from the growth substrate .

[0035] The one or more production regions and one or more test structure regions are then rebonded onto a carrier and the growth substate removed . The removal provides access to the backside of the devices . Then second contacts are provided to each of the plurality of devices , the second contacts facing away from the carrier .

[0036] The proposed method provides a test device with two contact facing the carrier , which can be easily picked and placed on a test substrate for characterization, while offering the same structure shape and form for the vertical components in the production regions as in conventional processing solutions . However, the burden testing of vertical devices is omitted .

[0037] In some aspects , the step of structuring the one or more production regions may comprise conducting one or more etches to form a plurality of partially separate devices and the at least one test device ; and depositing a sacrificial layer material in particularly over the surface of the plurality of devices and the at least one test device . The steps of etching also referred to as mesa etching is also performed, often simultaneously with the step of structuring the one or more test structure regions . Simply speaking, in some aspects , the individual steps of etching layer structures , mas k layer deposition and structuring , photomas k deposition and structuring , depositing material and the like are conducted during the same processing steps and in parallel . The approach ensures that the test devices are processed together with the devices on the production regions , and hence similar parameters and also issues or properties of the epitaxial chamber and other process chambers are affecting the test device in the same manner as the other devices .

[0038] In some aspects , the proposed method further comprises the step of depositing a support layer over the one or more production regions and the one or more test structure regions in particular after the step of structuring the one or more production regions and / or the step of structuring the one or more test structure regions . The support layer can be planarized to provide a planar surface for the subsequent rebonding process to another carrier . The support layer also offers anchoring structures mechanically connecting the devices in the one or more production regions and the one or more test structure regions to the support layer and the carrier .

[0039] In this regard, the material of the support layer may in some aspects contact a portion of each of the plurality of devices , in particularly a portion of the first contact . Furthermore , the material of the support layer may contact a portion of the at least one test device , in particularly at least one of the first and second contacts of the at least one test device . In some aspects , the support layer provides stubs on which the respective devices are resting and can easily be picked by a transferring device .

[0040] Some aspects concern the step of structuring the one or more test structure regions . In some aspects , a structured mask layer is deposited on the layer stack, with portions of the layer stack within the test structure regions exposed . In this regard, it should be noted that the individual devices in the production region may be arranged in a grid of rows and columns on the wafer, with a dedicated pitch in between . The at least one device in the one or more test structure region may follow this grid, that is , correspond to an area similar to an area of one of the plurality of devices . It may also be positioned such that the portion of the exposed layer stack corresponds to a position of a device within the grid . This approach simplifies the overall processing, as no significant changes in the individual steps or changes in the mas k layers are required .

[0041] Rather, one can simply add a removal step in the general process . The removal step will remove material of the exposed portion of the layer stack within the one or more test structure region including the functional layer beneath the exposed portion .

[0042] As already stated previously, it is possible and suitable in many aspects to perform the steps of structuring the one or more production regions and the one or more test structure regions in parallel .

[0043] In some further aspects , the step of removing the growth substrate comprises removing portions of the layer stack to open recesses generated during the step of structuring the one or more production regions and / or the step of structuring the one or more test structure regions . These recesses provide access to an existing sacrificial layer . By removing the sacrificial layer through those recesses , i . e . by wet and / or vapour etching , one can generate a plurality of devices and test devices resting on anchoring structures connected to the carrier .

[0044] In some aspects , the first contact on the bottom surface of the at least one test device and the second contact on the bottom surface of the at least one test device are vertically displaced to each other . The displacement in vertical direction causes the at least one test device to tilt by an angle of less than 5 ° and particularly less than 3 ° when placed with the first and second contact on a flat plane .

[0045] SHORT DESCRIPTION OF THE DRAWINGS

[0046] Further aspects and embodiments in accordance with the proposed principle will become apparent in relation to the various embodiments and examples described in detail in connection with the accompanying drawings in which Figure 1 shows a pre-processed wafer in accordance with some aspects of the proposed principle ;

[0047] Figures 2A to 2C illustrate some initial steps for processing a plurality of devices including test devices on the same growth substrate in accordance with some aspects of the proposed principle ;

[0048] Figures 3A to 31 show some further processing steps for processing a plurality of devices including test devices on the growth substrate in accordance with some aspects of the proposed principle ;

[0049] Figures 4A to 4D illustrate some steps after the rebonding procedure for processing a pre-processed wafer in accordance with some aspects of the proposed principle ;

[0050] Figures 5A and 5B illustrate some aspect for using the test device of the pr-processed wafer;

[0051] Figure 6 and Figure 7 show two further embodiments of a pre-processed wafer in accordance with some aspects of the proposed principle ;

[0052] Figure 8 illustrates a table indicating some possible configurations for a horizontal test device , including the tilt angle ;

[0053] Figure 9 shows a further embodiment of a pre-processed wafer in accordance with some aspects of the proposed principle ;

[0054] Figure 10 illustrates an embodiment of an application of a pLED in accordance with the embodiment of Figure 9 .

[0055] DETAILED DESCRIPTION

[0056] The following embodiments and examples disclose various aspects and their combinations according to the proposed principle . The embodiments and examples are not always to scale . Likewise , different elements can be displayed enlarged or reduced in size to emphasize individual aspects . It goes without saying that the individual aspects of the embodiments and examples shown in the figures can be combined with each other without further ado , without this contradicting the principle according to the invention . Some aspects show a regular structure or form. It should be noted that in practice slight differences and deviations from the ideal form may occur without , however, contradicting the inventive idea .

[0057] In addition, the individual figures and aspects are not necessarily shown in the correct size , nor do the proportions between individual elements have to be essentially correct . Some aspects are highlighted by showing them enlarged . However , terms such as "above" , "over" , "below" , "under" "larger" , "smaller" and the like are correctly represented with regard to the elements in the figures . So it is possible to deduce such relations between the elements based on the figures .

[0058] Figure 1 illustrates a pre-processed wafer in accordance with some aspects of the proposed principle . The pre-processed wafer 1 comprises a carrier 100 and a support layer 200 , on which a plurality of pre- processed devices 3 , as well as one or more test devices 2 are arranged . The pre-processed devices 3 are located in a dedicated region, referred to as production region PR of the pre-processed wafer . Likewise , the one or more test devices 2 are located in a test structure region TR specifically dedicated for such test devices .

[0059] The pre-processed devices 3 as well as the test device 2 are processed in the same or similar manner using various deposition techniques including but not limited to epitaxial , lithographic, metal deposition ( evaporation, sputtering ) , dielectric material deposition techniques (CVD, sputter , ...) and so on known in the art . More particularly, the production region PR as well as in the test structure region TR each comprise a plurality of devices implemented as horizontal pLEDs , each of it having a layer stack 10 . While the present embodiment illustrates optoelectronic devices and pLEDs , the proposed principle is not limited thereto . Rather, the proposed principle is suitable to any kind of vertical devices , of which a horizontal component can be processed together on the same wafer and utilized for testing . In the embodiment of Figure 1 , the pre-processed devices 3 comprise a structured layer stack 10 having an active region 11 arranged between an n-doped side 14 and p-doped side 15 . The p-doped side 15 faces the support layer 200 and carrier 100 . A current distribution layer 150 that is in contact with a metal contact 120 is deposited on the surface of p-doped side 15 . Metal contact 12 faces the carrier 100 and rests on the stub element 201 of the supportive layer 200 .

[0060] The n-doped layer 14 is facing away from the support layer 200 and comprises a transparent contact 13 made of ITO on its surface . Alternatively, a similar transparent conductive oxide is arranged on the n-doped layer as electric contact for this layer . The surface of n-doped layer 14 and the mesa sidewalls corresponds to the main emission surface of the vertical pLEDs 3 . Each of the pre-processed devices 3 comprises etched sidewalls forming a Mesa structure . The sidewalls are covered by a first dielectric material 160 deposited upon by for example an ALD process . In an alternative embodiment ( e . g . for phosphide based systems ) , the layer 160 may act as a regrowth layer having a bandgap that is larger than the bandgap of the active layer 11 .

[0061] In the embodiment , layer 160 extends from the bottom surface of the pre-processed devices through the sidewall surface of the active layer 11 on to the n-doped layer 14 . Another dielectric layer 170 is deposited on top of layer 160 , extending from the bottom surface of the respective pre-processed devices towards the main emission surface thereof . Layer 160 and 170 protects the semiconductor material from external environmental hazards like oxidization of the semiconductor material . The two layers 160 and 170 comprise a recess on the bottom side , in which the material of electrical contact 12 is deposited . Furthermore , each of the pre-processed devices in the production region comprises an etched mesa structure separating the respective devices from each other , whereas the sidewalls of the mesa etched structure are covered by layer 170 . In this particular embodiment , the mesa etch results in slightly inclined sidewalls of the n-doped layer 14 . The angle can be adj usted by etching conditions . The test device 2 in the test structure region TR is structured and processed in a very similar fashion, and covers a size , often a multiple of the size of a pre-processed device . This size may be referred to as pitch in some aspects . The test device in the embodiment comprises a size appr . two times the size of the pre-processed devices , that is the size of the test device is the pitch of two pre-processed devices . Hence , the test device is in the 1x2 configuration . The test device comprises a first portion that mainly corresponds to one of the pre- processed devices 3 . In the embodiment of Figure 1 this is illustrated by the left portion of the test device 2 .

[0062] A second portion of the test device is mainly used for contacting the n-doped region of the first portion, and also includes the second contact . In the embodiment , the second portion is the right side of the test device , occupying the other pitch of a pre-processed device . The right portion is recessed with regard to the left portion and includes a second metal contact 12 for directly contacting the n-doped side of the test device being in contact with active layer 11 . The p- doped layer and the active layer 11 in said portion of the layer stack is completely removed and contact 12 directly deposited on the bottom surface facing the support substrate 200 . The contact 12 connects the n-doped layer 14 .

[0063] As illustrated herein, the processing of the test device is conducted in the same way as pre-processed devices by further attaching contacts 13 on the top emission surface . This ensures that the emission characteristics of the test device to corresponds substantially to the emission characteristics of the pre-processed devices with no deviation in between .

[0064] The pre-processed devices 3 as well as the test device 2 are resting on stubs 201 and 202 of the support layer 200 . More particularly, the steps 201 are directly contacted to the bottom contacts 12 of the pre- processed devices 3 and the test device 2 . Stub 202 is used to connect to the contact 12 being the second contact of the test device 2 . A small sacrificial layer between the support layer 200 and the respective devices has been removed, such that the pre-processed devices 3 as well as the test device 2 can be easily picked by a corresponding stamp for transfer purposes .

[0065] As shown in the embodiment of Figure 1 , the test device 2 and the pre- processed devices 3 are substantially processed and manufactured in parallel , such that the main characteristics of both devices remain the same . This enables to pick off the test device 2 from the carrier on wafer level and transfer the test device to a respective test substrate for testing purposes . Nevertheless , since both devices are processed in the same chamber ( s ) using the same processing steps or at least in a very similar manner , the electro-optical parameters of the test device 2 are similar to the pre-processed devices 3 . The transfer as well as the application of the test device 2 onto the test substrate is significantly simplified, because both metal contacts 12 are bottom faced and can be directly soldered or bonded to the test substrate .

[0066] The vertical distance between the two contacts 12 of the test device is compensated by either additional solder material or a slight difference in the heights of the contact areas on the test substrate . Alternatively, the small tilt caused by the different vertical level of the two contracts 12 is compensated during the measurements of the optical parameters by arranging the detector device accordingly . In some other alternatives illustrated further below, the tilt as such can be reduced by proper design choices .

[0067] Figures 2A to 31 illustrate the several steps of the wafer level processing, implementing the pre-processed devices 3 in the form of pLEDs and the test device 2 (being also a pLED ) on a common growth substrate . The structure will subsequently rebonded and further processed to finally form the pre-processed wafer .

[0068] In this regard, it should be noted that the proposed method for implementing test devices as horizontal pLEDs and pre-processed devices as vertical chips on the same growth substrate and carrier is not limited to a specific material system or a specific kind of device . In particular, different kinds of semiconductor material compositions can be used without deviating from the proposed concept . Although optoelectronic devices are illustrated herein for reference purposes , any kind of semiconductor devices can be manufactured on wafer level using this technology, in which the pre-processed devices comprise vertically arranged contacts , while the test device comprises corresponding horizontal contacts , rendering the installation on a test substrate significant easier for testing purposes .

[0069] Figure 2A illustrates the first step of manufacturing a processed wafer in accordance with the proposed principle .

[0070] In a first step , a growth substrate 101 is provided . A plurality of different buffer and other layers ( not illustrated in details ) are deposited on the growth substrate 101 . In this regard, the expression deposited may include several different techniques , including for example but not limited epaxial growth or another deposition process . Further n-doped layer 14 is deposited on said buffer layers , followed by an active layer 11 as well as another doped layer , namely p-doped layer 15 . The various doped layers 14 and 15 can include a plurality of sublayer, those sublayers having different doping level concentrations , changing dopant concentration in growth direction, being undoped, having slightly different material composition ( i . e . different Al portion ) and the like . The various sublayers provide different functionality like current spreading, current transport and current inj ection into the active layer . The layer structure , its dopant and material composition follow the desired needs , the application as well as material system.

[0071] Active layer 11 may include a quantum well layer or a multi-quantum well layer in accordance with the design choice . Furthermore , to prevent diffusion of dopant from the doped layers 14 and 15 into the active layer , the active layer may comprise two undoped cladding layers directly adj acent to the doped layers 14 and 15 . The active layer may be undoped, but can also include a small dopant concentration, different barrier material and other structural layers depending on the needs . The doped layers 14 , 15 , and the active layer 11 form the layer stack 10 being deposited on growth substrate 101 . This is done on wafer level , preferably with a homogeneous deposition of the various materials within the epitaxy chamber . The resulting surface of the layer stack 10 is then virtually divided into so-called production region PR as well as test structure region TR, in which in subsequent steps the pre-processed devices 3 and the test devices 2 are manufactured and processed . The location of the respective test structure regions TR across the wafer can vary and may depend on the design choice of the various pre-processed devices , the characteristics of the epitaxy chamber as well as the deposition parameters and materials . Generally, the test structure regions with several test devices in each region are distributed across the wafer to characterize all pre-processed devices in the production region PR . In this regard, one or more test regions TR can be associated with adj acent production regions PR to characterize the pre-processed devices . Such association allows considering spatial variation of deposited material during the manufacturing process .

[0072] In a subsequent step , illustrated in Figure 2B , a metallic contact or alternatively a TOO is deposited as a current distribution layer and subsequently structured to form a structured current distribution layer 150 on the p-doped layer 15 . The current distribution layer 150 allows for current distribution and charge carrier inj ection into the doped layer 15 . The position of the structured current distribution layer 150 corresponds to the areas of the pre-processed devices as well as the test device , respectively . A hard mas k layer 165 is then deposited on top of the structured current distribution layer 150 .

[0073] Continuing with Figure 2C, the hard mas k layer 165 is structured to form hard mask portions 165 ' on top of the current distribution layer 150 encapsulating the material of structured current distribution layer 150 . The hard mask material is used to protect the current distribution layer 1050 as well as the semiconductor material beneath against the subsequent mesa etching process to form recesses separating the active layers of the respective pre-processed and test devices from each other . As also illustrated in Figure 2B and 2C , a larger portion of the surface of the p-doped layer 15 is exposed in the testing structure region TR . The location of the exposed portion corresponds to the pitch of the pre-processed devices , such that the resulting test device 2 occupies a space substantially equal to two pre-processed devices within the test structure region TR .

[0074] Figures 3A to 3H illustrate the next steps of manufacturing a plurality of pre-processed devices as well as the test devices on wafer level in accordance with the proposed principle .

[0075] After applying a structured hard mas k layer 165 ' covering the current distribution layers 150 and extending slightly laterally over the edges of the current distribution layers 150 , an etching process is performed removing portions of the exposed material , thereby creating substantial vertical sidewalls of the p-doped region 15 , the active layer 11 , as well as parts of the n-doped layer 14 . The mesa etching process illustrated in Figure 3A may include several sub-steps as well as cleaning steps to ensure a substantially defect-reduced sidewall along the pre-processed and the test devices . As also shown in Figure 3A, the exposed portion in the test structure region corresponding to the location of a pre-processed device is removed completely, thereby exposing the lateral surface of the n-doped region 14 . A contact of the n-contact layer will be formed upon this portion in subsequent steps after removal of mask 165 .

[0076] Depending on the design choices as well as material systems , various measures can be taken to further reduce the defect density along the sidewalls . For example , an additional doping step can be used in phosphide material systems after depositing of the structured hard mask layer 165 ' as illustrated in Figure 2C on the exposed portions . The dopant will diffuse down into the active layer 11 and cause quantum well intermixed areas beneath the exposed portions . Alternatively, a regrowth process can be performed, covering the sidewalls of the layer stacks with a material having a larger bandgap than the active layer 11 . Quantum well intermixed areas or regrowth areas form a higher potential , repelling charge carrier from reaching the sidewall ' s surface . In nitride material systems other measures are necessary or can be omitted due to the lower diffusion length of charge carrier in the active layer .

[0077] Illustrated in Figure 3B, a first dielectric layer is then deposited on the exposed surface of the resulting structure , covering the current distribution layers 150 as well as the sidewalls and the top surface portion of n-doped layer 14 . Then, a mask layer 166 is deposited on the dielectric layer 116 and subsequently structured to expose surface portions of dielectric layer 160 between the pre-processed devices as well as the test device . The resulting structure is depicted in Figure 3C .

[0078] The exposed portions are then subsequently etched in a second mesa etching process illustrated in Figure 3D causing a plurality of inclined sidewalls of the n-doped semiconductor layer 14 . The depth of the second mesa etch is adj usted such that the resulting recess can subsequently be used to gain access to a sacrificial layer deposited in later processing steps and to control the final thickness of the device . Furthermore , the mesa etch ensures the separation of the pre- processed devices 3 and the test devices 2 from each other when the devices are bonded onto the carrier substrate . The structured mask layer 166' is removed, resulting in the structure illustrated in Figure 3D .

[0079] Figure 3E illustrate the next step , in which a second dielectric layer 170 is deposited on the exposed sidewalls of the deep mesa etch as well as the first dielectric layer 160 on the sidewalls of the pre-processed devices 3 as well as the test device 2 and on top of such devices . Area 14 ' of the n-doped material 14 within the test structure region is also covered by dielectric layer 160 and 170 , respectively .

[0080] In a subsequent step, a photo mas k layer is deposited and subsequently structured ( not shown ) . Another etching process is performed in Figure 3F to open recesses in layers 170 and 160 on the top surface of the pre-processed devices 3 above the current distribution layers 150 as well as in the test device 2 and particularly in the area 14 ' . Consequently, the exposed surface of area 14 ' can now form a contact directly electrically contacting the n-doped layer 14 of the test device 2 . The exposed portion of current distribution layers 150 are used to contact the p-doped layer 15 of the respective devices .

[0081] In a subsequent step , illustrated in Figure 3G, the recesses are filled with a metallic contact material to form contacts 12 . In the present embodiment , the recesses are slightly over filled with the contact material , such that portions of the contact material expand over the dielectric material 170 on the top surface of the respective devices . The test device 2 is now implemented as a horizontal device , while the pre-processed devices 3 in the respective production regions currently contain only one contact and will be implemented as vertical devices .

[0082] In a further subsequent step, another layer material 175 is deposited over the surface covering layer 170 as well as the contacts 12 , respectively . The resulting structure is illustrated in Figure 3H . Layer 175 acts as a sacrificial layer and is later removed, such that the devices only rest on the anchor structure 201 and 202 , respectively, prior to picking the processed devices . Consequently, illustrated in Figure 31 , a small portion above the contacts 12 of layer 175 is removed to gain access to the pre-processed devices in the production region and the test region . This recess acts as the anchor .

[0083] Figures 4A to 4D illustrate the next step of manufacturing a pre- processed wafer in accordance with some aspects of the proposed principle .

[0084] In a first step illustrated in Figure 4A, a support material 200 is now deposited on the top surface covering the sacrificial layer 175 completely as well as the metallic contacts 12 in each of the recesses in sacrificial layer 175 . The material of supporting layer 200 is planarized to enable bonding to the support carrier wafer 100 as illustrated in Figure 1 . The structure of the support material in layer 200 and the support carrier 100 enables rebonding the processed structure on growth substrate 101 . The resulting assembly is then turned to gain access to the growth substrate 101 . The growth substrate is removed ( e . g . by a lift-off process ) in a subsequent step . Furthermore , the semiconductor material , for example , the buffer layers as well as a portion of the n-doped layer 14 deposited on the growth substrate 101 is subsequently removed using mechanical chemical means ( i . e . grinding , polishing ) or a combination thereof ( e . g . CMP ) . The removal of the semiconductor material is continued until a portion of the deep Mesa etches between the pre-processed devices as well as the test devices is exposed . Simply speaking, one need access from this side to the material of the sacrificial layer 175 deposited in the deep mesa recesses .

[0085] The planarized surface of the pre-processed devices 3 may also act as the main emission surface for the devices in subsequent process steps and during operation of the devices according to their respective application . In this regard, the current distribution layer 150 and also portions of layer 160 may comprise a reflective material to ensure that light is substantially emitted through the emission surface illustrated in Figure 4B thereby providing a surface emitter . In alternative applications , the pre-processed devices may act as a volume emitter , emitting light but not only through the main emission surface but in all different direction .

[0086] In a subsequent step illustrated in Figure 4C , a photo mask layer is deposited on the exposed surface and structured with some portions of the surface exposed ( not shown ) , then a second contact material 13 is deposited on the exposed surfaces of the n-doped layer and the photo mas k removed . The second contact material 13 comprises a transparent conductive oxide like ITO and the like to ensure an electrical contact to the n-doped layer 14 of the pre-processed devices while maintaining light emission through the emission surface .

[0087] In summary, the pre-processed devices 3 in the production regions PR are now finalized as vertical components , while the test device 2 is usable as a vertical component but also as a horizontal component due to both contacts 12 facing the support carrier 100 . In a subsequent step, the material of sacrificial layer 175 and partially also the bond layer 200 is removed, such that the vertical devices 3 in the production region PR as well as the test device 2 in the test structure region TR is resting fully on stubs 201 and 202 made of the support material of layer 200 . The stubs 201 comprises a geometry, which simplifies the picking and placing process when assembling the pre-processed devices to the final substrate .

[0088] The pre-processed wafer 1 is now ready for characterization of the respective pre-processed devices 2 but can also be shipped to a potential customer as is . Testing can be done at the customers side , but also in-house .

[0089] Figure 5A and 5B illustrate the next steps , in which the test devices 2 from the pre-processed wafer illustrated in Figure 5A are picked by respective stamp and transferred to a test substrate TS . The test substrate TS comprises 2 contact areas 120 of a size larger than the respective area of contacts 12 of the test device 2 . The distance between the contact areas 12 corresponds to the pitch and distance of the pre-processed devices and follow the configuration of the test device 2 . When picking the test device , the test device 2 can be transferred directly with its two contacts 12 to the contact areas 120 and bonded or soldered thereto . No further contacting or other processing steps are required . Rather, after connecting the test device 2 to the contact area 120 , the test device 2 is optically and electrically characterized and its properties evaluated . For this purpose , the test substrate TS may comprise respective testing structures or connectors to a test and measurement system .

[0090] The vertical distance between the two contacts 12 of the test device 2 illustrated in Figure 5B may cause a small tilt when placing the test device 2 on the contact areas 120 .

[0091] Figure 8 illustrates the tilt given by such structure and illustrated for test devices of various configurations 1x2 , 1x3 , 1x4 and 2x3 . For example , with a dimension of 1x2 , a test device comprises substantially a length corresponding to two pre-processed devices and a width corresponding to one pre-processed device . A test device in the 1x4 configuration occupies a length substantially equal to 4 times the pitch of a single device on the pre-processed wafer . The maximum tilt angle is approximately 3 ° . This tilt angle is reduced when the test device becomes larger in length for instance with a configuration of 1x3 or 1 x 4 . The table in Figure 8 illustrates some exemplary device configurations as well as the corresponding tilt angle . One should note that the tilt and angles are depending on the mesa etch depth .

[0092] The device configuration, 1x3 , is also illustrated in Figure 6 as well as in Figure 7 . Figure 6 shows a test device 2 in the x3 configuration that corresponds substantially to a pitch of 3 pre-processed devices . The respective horizontal contact 12 in the test device 2 for contacting the n-doped layer 14 is laterally displaced by a distance , corresponding to a pitch of two pre-processed device ( so there is space of one pre-processed vertical device in between the left contact 2 and the right contact 12 in this view ) . On the surface opposing the carrier wafer 100 , the transparent contacts 13 are , however, processed in the same manner on the test device as for the pre-processed devices .

[0093] This embodiment not only indicates the respective pitch of the test device in comparison to the pre-processed devices , but also shows that several processing steps for processing the devices are implemented exactly in the same way as in conventional devices with no test device on the wafer . They are simply reused also for the test device , without any change in the masks . Consequently, only a very few processing steps have to be adapted to process one or more test devices 2 in accordance with the proposed principle on the wafer . The proposed method and the pre-processed test wafer does not only simplify the overall steps for incorporating a test device onto existing manufacturing procedures , but also reduces the overall costs as only a few steps (mainly litho steps ) have to be added or adj usted .

[0094] An alternative embodiment is illustrated in Figure 7 . Similar to the previous embodiment , a larger portion of the p-doped material as well as the active layer 11 is removed from the layer stack to implement the test device 2 in the 1x3 configuration- However, in contrast to the previous embodiment of Figure 6 another contact 12 is added providing an electric contact to the n-doped layer 14 at a position corresponding to a central pitch of a virtual vertical component . This structure may further simplify the processing and also homogenize the process ( there is less are dependencies ) due to the re-use of existing mas ks . Although the test device is in a 1x3 configuration, the additional second contact for the n-doped layer 14 may simplify later test procedures , depending on the test substrate used . For example , it is now possible to either contact the test device 2 with the right contact 12 in the 1x3 configuration reducing the tilt angle , or with the central contact effectively establishing a 1x2 configuration . In addition, one can establish a 3 point test geometry to overcome contact problems of the maybe non perfect n-contact .

[0095] Furthermore , the additional contact 12 may improve stability during handling of the device as it also rests on a stub 201 , thereby reducing the risk of breakage during the lifting and transfer process of test device 2 .

[0096] Figure 9 illustrates a further aspect , in which the test region TR include two test devices 2 and 2 ' implemented differently . Mor particular, test devices 2 ' is similar to two individual devices , that is vertical pLEDs in the production regions PR . However, the two pLEDs are not separated but connected together in the n-doped region 14 . During manufacture the deep mesa etching step usually used to separate the vertical devices from each other is omitted . The implementation results in a vertical device , in which two active layers can be operated separately .

[0097] However , the device can also be used for testing purposes . The benefit here is that the two bottom contacts are on the same level , hence no tilt occurs when placing the test device 2 ' onto the contact areas of a test substrate . These aspects are illustrated in Figure 10 . The test device 2 ' is arranged with its two bottom contacts in the contact areas of the test surface and soldered to the contact area thereof . In contrast to the previous test device , in which a portion of the doped layers and the active region has been removed, the test device 2 ' contains two active areas . Hence , for testing purposes one can either apply a needle to one of the top contacts 13 and then conduct the measurements necessary for the characteristics . The approach may be beneficial , as two devices ( the test devices 2 ' provides two vertical devices for testing purposes ) are present .

[0098] However , the needle used for contacting one of the two contacts may interfere with the measurements for characterizing the test device . Hence , a second solution lies in an artificial and deliberate destruction of one of the active layers to generate an ohmic contact . This situation is illustrated in Figure 10 . A current source is connected to the left contacts (bottom and top contact ) of the test device 2 ' using a needle and the contact area on which the test device 2 ' is soldered . Then, a high current pulse is given onto the contacts resulting in a current flow through the active layer . The current pulse is too high for the active layer to sustain the heat , such that the active layer in said area gets destroyed creating a short circuit ( close ) . As a result , the short acts as an ohmic contact enabling a current flow for said contact areas through the n-doped region into the unharmed active layer of the right portion of the test device . The test device on the test substrate can then be used for normal characterization and testing .

[0099] In another aspect , one can actually utilize the structure of the test device 2 ' as shown in Figure 9 for the purpose of mounting such devices on displays or display substrates as redundant devices . The approach is based on fact , that displays often contain redundant elements in case one of the element gets damage during processing and mounting . Hence , one may test all the optoelectronic elements and replace damaged ones by functional devices close by . It is proposed in some aspects to use the proposed method providing two vertical devices arranged together by a non-etched semiconductor layer, both of which are actual vertical elements . The devices 2 ' are placed on contact areas of the substrate and tested individually . If one of the devices is not working the other one is used . If both of the devices are working , one device is destroyed as indicated above .

[0100] Hence , for the above-mentioned testing method as well as for the creation of redundant devices , one of the two connected vertical optoelectronic components and pLEDs is purposely shorted by one or several forward and or reverse voltage / current pulses . Hereby the pn-j unction of this particular one pLED is selectively destroyed and a shortcut is formed . This can be done either by contacting with a needle on the upper n-pad of one of the LEDs ( electric circuit left using SI ) and using the left landing pad or by operating the device using the two landing pads ( electric circuit left using S2 ) in a p-n-p geometry* and a positive voltage on the right landing pad . In both cases , the active layer and / or the pn-j unction of the left device is shorted intentionally similar to an ESD impact .

[0101] The approach applied to production creates redundancy, but still allows to contact the device as a horizontal element and not a vertical element , thereby avoiding the additional processing steps . This approach may consume only a little more space and has the benefit that the subpixel arrangement in a pixel of the final application does not change . Moreover, the processing of such devices can be simplified as they are processed like normal vertical devices , but subsequently used as horizontal devices .

[0102] LIST OF REFERENCES

[0103] 1 processed wafer

[0104] 2 test device

[0105] 3 pre-processed device

[0106] 10 layer stack

[0107] 11 active layer

[0108] 12 , 13 contacts

[0109] 14 , 15 doped layers

[0110] 14 ' area

[0111] 100 carrier

[0112] 101 growth substrate

[0113] 120 contact areas

[0114] 150 current distribution layer

[0115] 160 dielectric layer

[0116] 165 mas k layer

[0117] 165 structured mask layer

[0118] 166 structured mask layer

[0119] 170 dielectric layer

[0120] 175 sacrificial layer

[0121] 200 support layer

[0122] 201 202 stubs

[0123] PR production region

[0124] TR test structure region

[0125] TS test substrate

Claims

CLAIMS1 . Processed wafer , in particular having a plurality of semiconductor components , in particular pLEDs : a carrier having defined one or more production regions and one or more test structure regions ; each of the one or more production regions comprising a plurality of pre-processed devices , each pre-processed device having a top surface and an opposing bottom surface , said bottom surface facing the carrier; wherein each of the plurality of pre-processed devices comprises a functional layer stack, said functional layer stack in contact with a first contact on the bottom surface and a second contact on the top surface ; each of the one or more test structure regions comprises at least one pre-processed test device , each pre-processed test device having a top surface and an opposing bottom surface , said bottom surface facing the carrier; wherein the at least one pre-processed test device comprises the functional layer stack, said functional layer stack in contact with a first contact on the bottom surface of the at least one test device and a second contact on the bottom surface of the at least one test device laterally displaced to the first contact .2 . Processed wafer according to claim 1 , wherein each of the plurality of pre-processed device are at least partially separated by a mesa etched recess ; or each of the plurality of pre-processed device are separated from each other and the at least one pre-processed test device .3 . Processed wafer according to any of the preceding claims , wherein- the bottom surface of the pre-processed devices and the at least one pre-processed test device are coupled to the carrier ; and / or- the first contacts of the pre-processed devices and at least one of the first and second contacts of the at least one pre-processed test device are connected to the carrier, in particular via a bond material .4 . Processed wafer according to any of the preceding claims , comprising a plurality of anchor structures connecting the carrier with at least one of : the bottom surface of each of the plurality of pre-processed devices ; or the first contacts of each of the plurality of pre-processed devices ; the bottom surface of the at least one test device ; at least one of the first contact and the second contact of the at least one test device .5 . Processed wafer according to any of the preceding claims , further comprising a sacrificial material partially arranged between portions of the bottom surface and the carrier .6 . Processed wafer according to any of the preceding claims , wherein the second contact on the bottom surface of the at least one test device is laterally displaced to the first contact of the at least one test device by a distance that corresponds to a distance between two adj acent pre-processed devices ; or a distance that corresponds to a multiple of a distance between two adj acent pre-processed devices .7 . Processed wafer according to any of the preceding claims , wherein the at least one test device occupies a lateral area substantially equal to a multiple of the area of one of the pre-processed test device , in particular 2 time or 3 times the area .8 . Processed wafer according to any of the preceding claims , wherein the first contact on the bottom surface and the second contact on the bottom surface of the at least one test device are vertically displaced to each other , in particular by a distance corresponding to a thickness of at least an active region of the functional layer .9 . Processed wafer according to any of the preceding claims , wherein the first contact on the bottom surface of the at least one testdevice and the second contact on the bottom surface of the at least one test device are vertically displaced to each other such that the at least one test device is tilted by an angle of less than 5 ° and particularly less than 3 ° when placed with the first and second contact on a flat plane .10 . Processed wafer according to any of the preceding claims , wherein each of one or more production regions is associated with one or more test regions .11 . Processed wafer according to any of the preceding claims , wherein the functional layer of the plurality of pre-processed devices and the at least one pre-processed test device is configured to emit light towards the top surface , thereby forming in particular a pLED .12 . Method for processing a plurality of optoelectronic device , in particular pLEDs , comprising :- providing a growth substrate having defined one or more production regions and one or more test structure regions ;- depositing a layer stack onto the growth substrate ;- structuring the one or more production regions to form a plurality of devices having a functional layer , with a first contact contacting the functional layer and facing away from the growth substrate ;- structuring the one or more test structure regions to form at least one test device having the functional layer and a first contact and a second contact , each contacting the functional layer and both contacts facing away from the growth substrate ;- rebonding the one or more production regions and one or more test structure regions onto a carrier;- removing the growth substrate ;- providing second contacts to each of the plurality of devices , the second contacts facing away from the carrier .13 . Method according to claim 12 , wherein the step of structuring the one or more production regions and / or the step of structuring the one or more test structure regions comprises the step of :conducting one or more etches to form a plurality of partially separate devices and the at least one test device ; depositing a sacrificial layer material in particularly over the surface of the plurality of devices and the at least one test device .14 . Method according to any of claims 12 to 13 , further comprising the step ofDepositing a support layer over the one or more production regions and the one or more test structure regions , in particular after the step of structuring the one or more production regions and / or the step of structuring the one or more test structure regions .15 . Method according to claim 14 , wherein the step of depositing is conducted such that material of the support layer contacts a portion of each of the plurality of devices , in particularly a portion of the first contact ; and material of the support layer contacts a portion of the at least one test device , in particularly at least one of the first and second contacts of the at least one test device .16 . Method according to any of claims 12 to 15 , wherein the step of structuring the one or more test structure regions comprises the step of : providing a structured mas k layer on the deposited layer stack with portions of the layer stack exposed; wherein optionally, a position of the exposed layer stack corresponds to an area similar to an area of one of the plurality of devices ; removing material of the exposed portion of the layer stack, including the functional layer beneath the exposed portion .17 . Method according to any of claims 12 to 16 , wherein the steps of structuring the one or more production regions and the one or more test structure regions are conducting in parallel .18 . Method according to any of claims 12 to 17 , wherein the step of removing the growth substrate comprises removing portions of the layer stack to open recesses generated during the step of structuring the one or more production regions and / or the step of structuring the one or more test structure regions .19 . Method according to any of claims 12 to 18 , wherein the first contact on the bottom surface of the at least one test device and the second contact on the bottom surface of the at least one test device are vertically displaced to each other such that the at least one test device is tilted by an angle of less than 5 ° and particularly less than 3 ° when placed with the first and second contact on a flat plane .

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