Pulse width determination in a single-wire bus apparatus

Abstract

Pulse width determination in a single-wire bus apparatus is described in the present disclosure. Herein, a pulse width determination circuit is configured to determine the width of a pulse based on a sampling clock. More specifically, the sampling clock can be a half-rate clock that reduces sampling power. Alternatively, the sampling clock can be a full-rate clock that increases sampling precision. Given that the pulse and the sampling clock can be asynchronous, the pulse width determination circuit is further configured to mitigate possible sampling errors associated with a rising edge and / or a falling edge of the pulse to thereby improve sampling accuracy. In an embodiment, the pulse width determination circuit can be provided in a slave circuit(s) in the single-wire bus apparatus to determine a synchronization pulse communicated by a master circuit via a single-wire bus to thereby establish a timing basis for subsequent communications with the master circuit.

Description

PULSE WIDTH DETERMINATION IN A SINGLE-WIRE BUS APPARATUSRelated Applications

[0001] This application claims the benefit of U.S. provisional patent application serial number 63 / 601 ,796, filed on November 22, 2023, and U.S. provisional patent application serial number 63 / 627,262, filed on January 31 , 2024, the disclosures of which are hereby incorporated herein by reference in their entireties.Field of the Disclosure

[0002] The technology of the disclosure relates generally to determining a pulse width by digitally sampling the pulse based on a sampling clock.Background

[0003] Mobile communication devices have become increasingly common in current society. The prevalence of these mobile communication devices is driven in part by the many functions that are now enabled on such devices. Increased processing capabilities in such devices means that mobile communication devices have evolved from being pure communication tools into sophisticated mobile multimedia centers that enable enhanced user experiences.

[0004] To provide the redefined user experience, a state-of-the-art wireless communication device (e.g., smartphone) is equipped with a variety of electrical circuits to support various applications and enable various user experiences. In addition, the wireless communication device also employs a variety of communication buses to enable inter-circuit and intra-circuit communications. As an example, a two-wire radio frequency front-end (RFFE) bus can enable a transceiver circuit(s) to communicate with a power amplifier circuit, a power management circuit, and / or an antenna circuit. A multi-wire, high-bandwidth memory bus can enable time-critical direct access to a memory circuit, and a multi-wire general purpose input / output (GPIO) bus can bridge communications to an external peripheral device.

[0005] However, not all communications require a multi-wire bus like the RFFE bus, the memory bus, and the GPIO bus. In some cases, a single-wire serial bus may be sufficient or even desired for carrying out low-speed and / or low-bandwidth communications between certain types of circuits (e.g., antennas tuners, sensors, and switches).

[0006] Aspects disclosed in the detailed description are related to pulse width determination in a single-wire bus apparatus. Herein, a pulse width determination circuit is configured to determine the width of a pulse based on a sampling clock. More specifically, the sampling clock can be a half-rate clock that reduces sampling power. Alternatively, the sampling clock can be a full-rate clock that increases sampling precision. Given that the pulse and the sampling clock can be asynchronous, the pulse width determination circuit is further configured to mitigate possible sampling errors associated with a rising edge and / or a falling edge of the pulse to thereby improve sampling accuracy. In an embodiment, the pulse width determination circuit can be provided in a slave circuit(s) in the single-wire bus apparatus to determine a synchronization pulse communicated by a master circuit via a single-wire bus to thereby establish a timing basis for subsequent communications with the master circuit.

[0007] In one aspect, a pulse width determination circuit is provided. The pulse width determination circuit is configured to receive a pulse defined by a pulse rising edge and a pulse falling edge. The pulse width determination circuit is also configured to enable a sampling clock having multiple clock cycles each comprising a high clock interval defined by a clock rising edge and a clock falling edge followed by a low clock interval in response to detecting the pulse rising edge. The pulse width determination circuit is also configured to increase a sampling counter for each of the multiple clock cycles of the sampling clock. The pulse width determination circuit is also configured to disable the sampling clock in response to detecting the clock rising edge and the clock falling edge that define the high clock interval immediately after the pulse falling edge. The pulsewidth determination circuit is also configured to determine a phase error indicator based on a relative position between the pulse falling edge and one of the multiple clock cycles in the sampling clock. The pulse width determination circuit is also configured to determine a digital sampling count based on the sampling counter and the phase error indicator.

[0008] In another aspect, a method for determining a pulse width of a pulse is provided. The method includes receiving the pulse defined by a pulse rising edge and a pulse falling edge. The method also includes enabling a sampling clock having multiple clock cycles each comprising a high clock interval defined by a clock rising edge and a clock falling edge followed by a low clock interval in response to detecting the pulse rising edge. The method also includes increasing a sampling counter for each of the multiple clock cycles of the sampling clock. The method also includes disabling the sampling clock in response to detecting the clock rising edge and the clock falling edge that define the high clock interval immediately after the pulse falling edge. The method also includes determining a phase error indicator based on a relative position between the pulse falling edge and one of the multiple clock cycles in the sampling clock. The method also includes determining a digital sampling count based on the sampling counter and the phase error indicator.

[0009] In another aspect, a wireless device is provided. The wireless device includes a single-wire bus apparatus. The single-wire bus apparatus includes a master circuit. The master circuit is coupled to a single-wire bus consisting of one wire. The master circuit is configured to communicate multiple bus telegrams each preceded by a start-of-sequence (SOS) sequence. The SOS sequence includes a synchronization pulse defined by a pulse rising edge and a pulse falling edge. The single-wire bus apparatus also includes multiple slave circuits. Each of the multiple slave circuits is coupled to the single-wire bus. Each of the multiple slave circuits includes a pulse width determination circuit. The pulse width determination circuit is configured to receive the synchronization pulse via the single-wire bus. The pulse width determination circuit is also configured to enable a sampling clock having multiple clock cycles eachcomprising a high clock interval defined by a clock rising edge and a clock falling edge followed by a low clock interval in response to detecting the pulse rising edge. The pulse width determination circuit is also configured to increase a sampling counter for each of the multiple clock cycles of the sampling clock. The pulse width determination circuit is also configured to disable the sampling clock in response to detecting the clock rising edge and the clock falling edge that define the high clock interval immediately after the pulse falling edge. The pulse width determination circuit is also configured to determine a phase error indicator based on a relative position between the pulse falling edge and one of the multiple clock cycles in the sampling clock. The pulse width determination circuit is also configured to determine a digital sampling count based on the sampling counter and the phase error indicator.

[0010] Those skilled in the art will appreciate the scope of the disclosure and realize additional aspects thereof after reading the following detailed description in association with the accompanying drawings.Brief Description of the Drawings

[0011] The accompanying drawings incorporated in and forming a part of this specification illustrate several aspects of the disclosure and, together with the description, serve to explain the principles of the disclosure.

[0012] Figure 1 A is a schematic diagram of an exemplary conventional singlewire bus apparatus in which a master circuit is configured to communicate with a slave circuit(s) over a single-wire bus;

[0013] Figure 1 B is a schematic diagram providing an exemplary illustration of one or more bus telegrams communicated from the master circuit to the slave circuit(s) over the single-wire bus of Figure 1 A;

[0014] Figure 1 C is a schematic diagram providing an exemplary illustration of one or more bus telegrams communicated from the slave circuit(s) to the master circuit over the single-wire bus of Figure 1 A;

[0015] Figure 1 D is a schematic diagram providing an exemplary illustration of a bus symbol modulated based on a voltage pulse-width modulation (PWM) to represent a voltage PWM value one (“1 ”);

[0016] Figure 1 E is a schematic diagram providing an exemplary illustration of the bus symbol modulated based on the voltage PWM to represent a voltage PWM value zero (“0”);

[0017] Figure 1 F is a schematic diagram providing an exemplary illustration of a start-of-sequence (SOS) sequence including a synchronization pulse and preceding each of the bus telegrams in Figures 1 B and 1 C;

[0018] Figure 2 is a schematic diagram of an exemplary single-wire bus apparatus wherein a slave circuit(s) can be configured to determine a pulse width of a pulse, such as the synchronization pulse in Figure 1 F, with a reasonable degree of precision and achieve a calculated trade-off between sampling precision and power consumption;

[0019] Figure 3 is a flowchart of an exemplary process whereby a pulse width determination circuit in the slave circuit(s) in Figure 2 can determine the pulse width of the pulse;

[0020] Figures 4A-4D are schematic diagrams providing exemplary illustrations of various operating scenarios of the pulse width determination circuit in Figure 2;

[0021] Figure 5 is a schematic diagram providing an exemplary illustration of the pulse width determination circuit in Figure 2 configured to handle the various operating scenarios in Figures 4A-4D;

[0022] Figure 6 is a schematic diagram providing an exemplary illustration as to how the pulse width determination circuit in Figure 5 can handle a metastability situation(s) in some of the operating scenarios illustrated in Figures 4A-4D; and

[0023] Figure 7 is a schematic diagram of an exemplary user element (e.g., a wireless device) wherein the single-wire bus apparatus of Figure 2 can be provided.Detailed Description

[0024] The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims.

[0025] It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0026] It will be understood that when an element such as a layer, region, or substrate is referred to as being "on" or extending "onto" another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or extending "directly onto" another element, there are no intervening elements present. Likewise, it will be understood that when an element such as a layer, region, or substrate is referred to as being "over" or extending "over" another element, it can be directly over or extend directly over the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly over" or extending "directly over" another element, there are no intervening elements present. It will also be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an elementis referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.

[0027] Relative terms such as "below" or "above" or "upper" or "lower" or "horizontal" or "vertical" may be used herein to describe a relationship of one element, layer, or region to another element, layer, or region as illustrated in the Figures. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures.

[0028] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises," "comprising," "includes," and / or "including" when used herein specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0029] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0030] Aspects disclosed in the detailed description are related to pulse width determination in a single-wire bus apparatus. Herein, a pulse width determination circuit is configured to determine the width of a pulse based on a sampling clock. More specifically, the sampling clock can be a half-rate clock that reduces sampling power. Alternatively, the sampling clock can be a full-rate clock that increases sampling precision. Given that the pulse and the sampling clock can be asynchronous, the pulse width determination circuit is furtherconfigured to mitigate possible sampling errors associated with a rising edge and / or a falling edge of the pulse to thereby improve sampling accuracy. In an embodiment, the pulse width determination circuit can be provided in a slave circuit(s) in the single-wire bus apparatus to determine a synchronization pulse communicated by a master circuit via a single-wire bus to thereby establish a timing basis for subsequent communications with the master circuit.

[0031] Before discussing a single-wire bus apparatus of the present disclosure, starting at Figure 2, a brief overview of a conventional single-wire bus apparatus is first provided with reference to Figures 1 A-1 F to help understand basic operations of a single-wire bus and the technical problems to be solve herein.

[0032] In this regard, Figure 1 A is a schematic diagram of an exemplary conventional single-wire bus apparatus 10 in which a master circuit 12 is configured to communicate with a number of slave circuits 14(1 )-14(M) over a single-wire bus 16 coupled to a master port 18. As such, the master circuit 12 and the slave circuits 14(1 )-14(M) may only communicate with each other in an alternate fashion (e.g., by time-division).

[0033] The master circuit 12 is configured to always initiate a bus telegram communication over the single-wire bus 16 by communicating a bus telegram(s) to one or more of the slave circuits 14(1 )-14(M). As such, the conventional single-wire bus apparatus 10 is also known as a “master-slave bus architecture.” The slave circuits 14(1 )-14(M) may provide a data payload(s) to the master circuit 12 over the single-wire bus 16 in response to receiving the bus telegram(s) from the master circuit 12. Hereinafter, the bus telegram(s) communicated from the master circuit 12 to the slave circuits 14(1)-14(M) is referred to as “a forward bus telegram(s)” and the data payload(s) communicated from the slave circuits 14(1 )-14(M) to the master circuit 12 is referred to as “a reverse bus telegram(s).”

[0034] Figure 1 B is a schematic diagram providing an exemplary illustration of one or more bus telegrams 20, 22 communicated from the master circuit 12 to any of the slave circuits 14(1 )-14(M) over the single-wire bus 16 of Figure 1 A. Each of the bus telegrams 20, 22 begins with an SOS sequence 24, followed bya bus command sequence 26. The bus command sequence 26 includes a write command frame 28 and a write data frame 30. The write command frame 28 includes a command field 32 (denoted as “CMD”), which is encoded with a binary value “100” to indicate a register-write operation. The write data frame 30 includes a write data period 34. The write data period 34 can include one or more write data symbols Ts modulated to carry data to the slave circuits 14(1 )- 14(M) during the register-write operation. In this regard, the bus telegrams 20, 22 may be an example of the forward bus telegram(s).

[0035] The SOS sequence 24 always precedes the bus command sequence 26 and is always communicated from the master circuit 12 to the slave circuits 14(1 )-14(M). The bus telegram 22, which succeeds the bus telegram 20, may be separated from the bus telegram 20 by a fast-charge period 36 that starts at time Ti and ends at time T2 (T2 > T1) and an idle period 38 that starts at time T2 and ends at time T3 (T3 > T2). Collectively, a duration between time T1 and T3 is also referred to as a suspension period (T3 - T1).

[0036] The fast-charge period 36 is configured to allow each of the slave circuits 14(1 )-14(M) to draw a higher charging current via the single-wire bus 16 and harvest power from the higher charging current. In this regard, the singlewire bus 16 is said to be in a fast-charge state during the fast-charge period 36. The idle period 38 may be a non-activity period in which the master circuit 12 and the slave circuits 14(1 )-14(M) may be inactive to help conserve power.Accordingly, the single-wire bus 16 is said to be in an idle state during the idle period 38.

[0037] The bus command sequence includes a slave address field 40 and is followed by a bus park period 42 and subsequently four acknowledgement (ACK) symbols 44. The slave address field 40 can be used to address the slave circuits 14(1 )-14(M). The bus park period 42 may be used to switch between the forward and the reverse communication modes. The ACK symbols 44 can be used by up to four of the slave circuits 14(1 )-14(M) to acknowledge a respective receipt of the data carried in the write data period 34. Given that the ACK symbols 44 are communicated immediately before the fast-charge period 36, each of the slavecircuits 14(1 )-14(M) can determine the time Ti to start the fast-charge period 36 by counting four ACKs communicated in the four ACK symbols 44 from the end of the bus park period 42.

[0038] Each of the slave circuits 14(1 )-14(M) is uniquely identified by a respective unique slave identification (IISID). As such, the bus command sequence 26 in the bus telegrams 20, 22 can be a unicast command sequence destined to any one of the slave circuits 14(1 )-14(M) when the slave address field 40 contains the USID of the any one of the slave circuits 14(1 )-14(M). The bus command sequence 26 in the bus telegrams 20, 22 can also be a multicast command sequence destined to a subset of the slave circuits 14(1 )-14(M) when the slave address field 40 contains a group slave identification (GSID) corresponding to the subset of the slave circuits 14(1 )-14(M). Furthermore, the bus command sequence 26 in the bus telegrams 20, 22 can be a broadcast command sequence destined to all of the slave circuits 14(1 )-14(M) when the slave address field 40 contains a broadcast slave identification (BSID).

[0039] Figure 1 C is a schematic diagram providing an exemplary illustration of one or more bus telegrams 46, 48 communicated from the slave circuits 14(1 )- 14(M) to the master circuit 12 over the single-wire bus 16 of Figure 1 A. Common elements between Figures 1 B and 1 C are shown therein with common element numbers and will not be re-described herein.

[0040] Each of the bus telegrams 46, 48 includes the bus command sequence 26. The bus command sequence 26 includes a read command frame 50 and a read data frame 52, separated by a bus park period 42. The read command frame 50 includes the command field 32 (denoted as “CMD”), which is encoded with a binary value “010” to indicate a register-read operation. The read data frame 52 includes a read data period 54, which includes one or more read data symbols Ts modulated to carry data payloads to the master circuit 12 during the register-read operation. The master circuit 12 first communicates the read command frame 50 to the slave circuits 14(1 )-14(M) identified by the slave address field 40 to initiate the register-read operation. The master circuit 12 then tri-states during the bus park period 42 to yield control of the single-wire bus 16to the slave circuits 14(1 )-14(M). Subsequently, the slave circuits 14(1 )-14(M) can begin sending the data payloads in the read data period 54. In this regard, the bus telegrams 46, 48 may be an example of both the forward and the reverse bus telegram(s).

[0041] With reference back to Figure 1A, the master circuit 12 is configured to suspend the bus telegram communication over the single-wire bus 16 during the suspension period (T3 - T1). Accordingly, the master circuit 12 and the slave circuits 14(1 )-14(M) are configured to refrain from communicating the bus telegram(s) and data payload(s) from time T1 to T3. In this regard, the single-wire bus 16 can be said to be in a suspension mode between time T1 and T3. During the suspension period (T3 - T1), the master circuit 12 maintains the single-wire bus 16 at a bus voltage VBUS at a high voltage level VHIGH (VHIGH > 0 V). As such, the slave circuits 14(1)-14(M) can each draw a charging current over the singlewire bus 16 to thereby harvest power from the master circuit 12.

[0042] Outside the suspension period (T3 - T1), the write data symbols Ts in the write data period 34 and the read data symbols Ts in the read data period 54 can be modulated by toggling the bus voltage VBUS between the high voltage level VHIGH and a low voltage level VLOW (VLOW < VHIGH), as illustrated in Figures 1 D and 1 E. Figure 1 D is a schematic diagram providing an exemplary illustration of a bus symbol Ts modulated based on a voltage PWM to represent a voltage PWM value one (“1 ”).

[0043] The bus symbol Ts, which can be any of the write data symbols Ts and the read data symbols Ts, is modulated based on a predefined low-voltage interval 56 and a predefined high-voltage interval 58 that are configured according to a predefined configuration ratio. To represent the voltage PWM value “1 ,” the predefined low-voltage interval 56 is shorter than the predefined high-voltage interval 58. For example, the bus symbol Ts can include sixteen (16) digitally controlled oscillators (DOOs) and the predefined configuration ratio between the predefined low-voltage interval 56 and the predefined high-voltage interval 58 is 25% to 75% (or 1 to 3). In a non-limiting example, the DCOs are derived from a clock running at the master circuit 12. Accordingly, the predefinedlow-voltage interval 56 lasts for four (4) DCOs and the predefined high-voltage interval 58 lasts for twelve (12) DCOs.

[0044] In this regard, to modulate the bus symbol Ts to represent the voltage PWM value “1 the bus voltage VBUS is first asserted at a low voltage level VLOW (VBUS = VLOW) for the predefined low-voltage interval 56 and then at the high voltage level VHIGH (VHIGH > VLOW) for the predefined high-voltage interval 58.

[0045] Figure 1 E is a schematic diagram providing an exemplary illustration of a voltage PWM symbol Ts modulated to represent a voltage PWM value zero (“0”). Common elements between Figures 1 D and 1 E are shown therein with common element numbers and will not be re-described herein.

[0046] To represent the voltage PWM value “0,” the predefined low-voltage interval 56 is longer than the predefined high-voltage interval 58. Based on the same example in Figure 1 D, the predefined low-voltage interval 56 lasts for 12 DCOs and the predefined high-voltage interval 58 lasts for 4 DCOs. Accordingly, to modulate the bus symbol Ts to represent the voltage PWM value “0,” the bus voltage VBUS is first asserted at the lower voltage level VLOW (VBUS = VLOW) for the predefined low-voltage interval 56 and then at the high voltage level VHIGH (VBUS = VHIGH) for the predefined high-voltage interval 58.

[0047] Figure 1 F is a schematic diagram providing an exemplary illustration of the SOS sequence 24 in Figures 1 B and 1 C. Common elements between Figures 1 B, 1 C, and 1 F are shown therein with common element numbers and will not be re-described herein.

[0048] The SOS sequence 24 is a unique sequence that can never occur with any bit combination in the bus command sequence 26. Each of the slave circuits 14(1 )-14(M) is configured to always watch for the SOS sequence 24, which signals a start of the bus telegrams 20, 22, 46, 48. The SOS sequence 24 includes a synchronization pulse 60, during which the bus voltage VBUS is maintained at the high voltage level VHIGH. The synchronization pulse 60 is defined by a pulse rising edge 62 and a pulse falling edge 64 and includes a number of DCO pulses 66 whereby each of the slave circuits 14(1 )-14(M) can establish a respective timing basis (e.g., for read, acknowledgement, and otherfunctions). Following the synchronization pulse 60, there is a pair of PWM symbols 68, 70. In a non-limiting example, the PWM symbol 68 is modulated according to Figure 1 E to represent binary “0” and the PWM symbol 70 is modulated according to Figure 1 D to represent binary “1

[0049] To accurately determine the respective timing basis for subsequent communications with the master circuit 12, each of the slave circuits 14(1 )-14(M) must determine a pulse width 72 of the synchronization pulse 60. Accordingly, each of the slave circuits 14(1)-14(M) can digitally sample the synchronization pulse 60 based on a sampling clock 74 that includes multiple repeating clock cycles 76. In a non-limiting example, the sampling clock 74 can be a square wave clock wherein each of the repeating clock cycles 76 includes a high clock interval 78 and a low clock interval 80 configured according to a fifty-fifty (50-50) ratio. Specifically, the high clock interval 78 is defined by a clock rising edge 82 and a clock falling edge 84.

[0050] Understandably, the faster the sampling clock 74, the more precise the sampling can be performed. However, increasing the speed of the sampling clock 74 not only requires a more expensive and / or sizable oscillator but also increases power consumption of the slave circuits 14(1 )-14(M). Moreover, since the sampling clock 74 is running on the slave circuits 14(1 )-14(M), the sampling clock 74 can be asynchronous from the pulse rising edge 62 and / or the pulse falling edge 64 of the synchronization pulse 60. As a result, the slave circuits 14(1 )-14(M) may not be able to accurately determine the pulse width 72 of the synchronization pulse 60.

[0051] Thus, the technical problem to be solved herein is to determine the pulse width 72 of the synchronization pulse 60, or any square wave pulse as a whole, with a reasonable degree of precision, such as within an error margin of ±0.5 least significant bit (LSB). In addition, it is also necessary to make a calculated trade-off between increasing sampling precision and reducing sampling power consumption.

[0052] Figure 2 is a schematic diagram of an exemplary single-wire bus apparatus 86 wherein at least one slave circuit 88 can be configured todetermine a pulse width PWIDTH of a pulse 90, such as the synchronization pulse 60 communicated in the bus telegrams 20, 22 in Figure 1 B and / or the bus telegrams 46, 48 in Figure 10, with a reasonable degree of precision (e.g., ±0.5 LSB) and achieve a calculated trade-off between sampling precision and power consumption. Herein, the pulse width PWIDTH of the pulse 90 is defined by a pulse rising edge 92 and a pulse falling edge 94 of the pulse 90. The single-wire bus apparatus 86 also includes a master circuit 96 that generates and communicates the pulse 90 to the slave circuit 88 via a single-wire bus 98.

[0053] The slave circuit 88 can be configured to include a slave control circuit 100, a switch 102, and a power harvesting circuit 104. The power harvesting circuit 104 may be implemented as a resistor-capacitor (RC) circuit that includes a resistor R (e.g., 200 Q) and a holding capacitor CHOLD (e.g., 1 nF). The slave control circuit 100 is configured to close the switch 102 during the suspension period (T3 - T1) to couple the power harvesting circuit 104 to the single-wire bus 98. As such, the slave circuit 88 can draw a bus current IBUS to charge the holding capacitor CHOLD to a local voltage CAP. Outside the suspension period (T3 - T1), the slave control circuit 100 opens the switch 102 to decouple the power harvesting circuit 104 from the single-wire bus 98. As a result, the holding capacitor CHOLD will be discharged to supply the local voltage VCAP to the slave control circuit 100.

[0054] The slave control circuit 100 can include a pulse width determination circuit 106 and a slave transceiver circuit 108. The pulse width determination circuit 106 is configured according to various embodiments described below to determine the pulse width PWIDTH of the pulse 90 and provide the determined pulse width PWIDTH to the slave transceiver circuit 108. The slave transceiver circuit 108, in turn, can determine the timing basis (e.g., timing synchronization) based on the determined pulse width PWIDTH to thereby perform subsequent communications with the master circuit 96 over the single-wire bus 98.

[0055] In an embodiment, the pulse width determination circuit 106 is configured to determine the pulse width PWIDTH of the pulse 90 by digitally sampling the pulse 90 based on a sampling clock 1 10. Like the sampling clock74 in Figure 1 F, the sampling clock 110 includes multiple clock cycles 112. In a non-limiting example, the sampling clock 1 10 can be a square wave clock wherein each of the repeating clock cycles 112 includes a high clock interval 114 and a low clock interval 116 configured according to a 50-50 ratio. Specifically, the high clock interval 114 is defined by a clock rising edge 1 18 and a clock falling edge 120.

[0056] Figure 3 is a flowchart of an exemplary process 122 whereby the pulse width determination circuit 106 in Figure 2 can determine the pulse width PWIDTH of the pulse 90. Common elements between Figures 2 and 3 are shown therein with common element numbers and will not be re-described herein.

[0057] The pulse width determination circuit 106 is first configured to detect the pulse rising edge 92 (step 124). In response to detecting the pulse rising edge 92, the pulse width determination circuit 106 enables (a.k.a. activates) the sampling clock 110. Notably, since the sampling clock 110 is enabled by the pulse rising edge 92, it is possible to eliminate measurement error associated with the pulse rising edge 92.

[0058] In an embodiment, the pulse width determination circuit 106 can either enable a full-rate clock or a half-rate clock as the sampling clock 1 10, depending on configuration requirements. In this regard, the pulse width determination circuit 106 first determines whether the configuration requirements are to increase sampling precision or reduce sampling power consumption (step 126). If the configuration requirements are about reducing sampling power consumption, the pulse width determination circuit 106 then enables the half-rate clock as the sampling clock 1 10 (step 128). If, however, the configuration requirements are about increasing sampling precision, the pulse width determination circuit 106 then enables the full-rate clock as the sampling clock 1 10 (step 130). In a non-limiting example, the full-rate clock has a clock frequency that is twice as fast as that of the half-rate clock.

[0059] The pulse width determination circuit 106 can be configured to include a sampling counter SMSB. While the sampling clock 110 is active, the sampling counter SMSB is increased for each clock cycle 1 12 of the sampling clock 1 10(step 132). In an embodiment, the pulse width determination circuit 106 increases the sampling counter SMSB by two (2) for each clock cycle 112 of the sampling clock 110.

[0060] The pulse width determination circuit 106 is configured to determine whether the sampling clock 1 10 should be disabled (a.k.a. deactivated) to stop the increment of the sampling counter SMSB (step 134). In an embodiment, the pulse width determination circuit 106 is configured to disable the sampling clock 1 10 in response to detecting the high clock interval 1 14 that is immediately after the pulse falling edge 94. In other words, the pulse width determination circuit 106 will disable the sampling clock 110 upon detecting the first high clock interval 1 14 after the pulse falling edge 94. To do so, the pulse width determination circuit 106 must detect both the clock rising edge 1 18 and the clock falling edge 120 that define the high clock interval 114 immediately after the pulse falling edge 94. If the pulse width determination circuit 106 determines that the condition for disabling the sampling clock 110 is not met, the process 122 returns to step 132. Otherwise, the pulse width determination circuit 106 will disable the sampling clock 110 to thereby stop the sampling counter SMSB from counting (step 136).

[0061] Given that the sampling clock 110 and the pulse 90 are asynchronized, when the sampling clock 110 is stopped, the pulse falling edge 94 may fall within either the high clock interval 114 or the low clock interval 116. Moreover, the pulse falling edge 94 may even coincide with either the clock rising edge 1 18 or the clock falling edge 120. Such alignment uncertainty, if not properly handled, can lead to an error in the final determination of the pulse width PWIDTH of the pulse 90. In this regard, the pulse width determination circuit 106 is further configured to determine a phase error indicator SLSB based on a relative position between the pulse falling edge 94 and the clock cycle 1 12 in the sampling clock 1 10 (step 138). According to an embodiment of the present disclosure, the phase error indicator SLSB is set to FALSE (logic “0”) when the pulse falling edge 94 falls within the high clock interval 1 14 or TRUE (logic “1 ”) when the pulse falling edge 94 falls within the low clock interval 1 16.

[0062] Accordingly, the pulse width determination circuit 106 can determine a digital sampling count SCOUNT based on the phase error indicator SLSB and the sampling counter SMSB (step 140). Specifically, the digital sampling count SCOUNT equals a value of the sampling counter PMSB subtracted by “1 ” (SCOUNT = SMSB - 1 ) when the phase error indicator SLSB is TRUE. In contrast, when the phase error indicator SLSB is FALSE, the digital sampling count SCOUNT equals the value of the sampling counter SMSB subtracted by “2” (SCOUNT = SMSB - 2). Finally, the pulse width determination circuit 106 can determine the pulse width PWIDTH of the pulse 90 based on the digital sampling count SCOUNT and the clock rate of the sampling clock 110 (step 142).

[0063] In an embodiment, the arithmetic determination of the digital sampling count SCOUNT can be optimized to help further reduce power consumption. As an example, the sampling counter SMSB can be configured to increment by one (1 ), instead of two (2), for each clock cycle 112 of the sampling clock 110. When the sampling clock 110 is stopped, the sampling counter SMSB is left shifted by one 1 ) to thereby multiply the sampling counter SMSB by two (2). Thereafter, the left- shifted sampling counter SMSB can be concatenated with the phase error indicator SLSB to thereby generate the digital sampling count SCOUNT.

[0064] Figures 4A-4D are schematic diagrams providing exemplary illustrations of various operating scenarios of the pulse width determination circuit 106 in Figure 2. Common elements between Figures 2, 3, and 4A-4D are shown therein with common element numbers and will not be re-described herein.Notably, the operating scenarios described in Figures 4A-4D are based on the sampling clock 110 being the half-rate clock. It should be appreciated that the operating scenarios discussed herein are applicable to the full-rate clock as well.

[0065] Figure 4A illustrates a scenario wherein the pulse falling edge 94 falls within the low clock interval 1 16 of the sampling clock 1 10. Herein, at time T 1 , the pulse width determination circuit 106 detects the pulse rising edge 92 of the pulse 90. In response, the pulse width determination circuit 106 enables the sampling clock 110 at time T2 (T2 T1). At time T3 (T3 > T2), the pulse width determination circuit 106 detects the clock falling edge 120. Accordingly, thesampling counter SMSB is increased by 2 (SMSB = 2). At time T4 (T4 > T3), the pulse width determination circuit 106 once again detects the clock falling edge 120. Accordingly, the sampling counter SMSB is increased by 2 again (SMSB = 4).

[0066] At time Ts (Ts > T4), the pulse width determination circuit 106 detects the pulse falling edge 94 of the pulse 90, which falls within the low clock interval 1 16 of the sampling clock 1 10. However, the pulse falling edge 94 falls within the low clock interval 1 16 of the sampling clock 110. In this regard, at time Ts, the pulse width determination circuit 106 has not yet detected another clock rising edge 118. Shortly after time Ts, the pulse width determination circuit 106 detects the clock rising edge 118. Subsequently, at time Te (Te > Ts), the pulse width determination circuit 106 detects both the clock rising edge 1 18 and the clock falling edge 120 that are immediately after the pulse falling edge 94.Accordingly, the sampling counter SMSB is increased by 2 again (SMSB = 6).

[0067] Given that the pulse 90 has turned LOW at time Ts and the pulse width determination circuit 106 detects both the clock rising edge 1 18 and the clock falling edge 120 at time Te, the condition for disabling the sampling clock 1 10 has been met. As such, the pulse width determination circuit 106 disables the sampling clock 110 at time T7 (T7 Te). Accordingly, the sampling counter SMSB stops incrementing. Since the pulse falling edge 94 has fallen within the low clock interval 116, the phase error indicator SLSB will be TRUE (logic “1 ”). As a result, the digital sampling count SCOUNT is equal to five (5) (SMSB - 1 ). In an embodiment, the phase error indicator SLSB may be inverted to mean “phase of clock in which pulse negative edge occurred on.” As a result, the phase error indicator SLSB will be turned to FALSE again.

[0068] Figure 4B illustrates a scenario wherein the pulse falling edge 94 falls within the high clock interval 114 of the sampling clock 110. Herein, at time T1 , the pulse width determination circuit 106 detects the pulse rising edge 92 of the pulse 90. In response, the pulse width determination circuit 106 enables the sampling clock 110 at time T2 (T2 > T1). At time T3 (T3 > T2), the pulse width determination circuit 106 detects the clock falling edge 120. Accordingly, the sampling counter SMSB is increased by 2 (SMSB = 2).

[0069] At time T4 (T4 > T3), the pulse width determination circuit 106 detects the pulse falling edge 94 of the pulse 90, which falls within the high clock interval 1 14 of the sampling clock 1 10. At time Ts (Ts > T4), the pulse width determination circuit 106 once again detects the clock falling edge 120. Accordingly, the sampling counter SMSB is increased by 2 again (SMSB = 4). At time Te (Te > Ts), the pulse width determination circuit 106 detects both the clock rising edge 118 and the clock falling edge 120 that are immediately after the pulse falling edge 94. Accordingly, the sampling counter SMSB is increased by 2 again (SMSB = 6).

[0070] Given that the pulse 90 has turned LOW at time T4 and the pulse width determination circuit 106 detects both the clock rising edge 1 18 and the clock falling edge 120 at time Te, the condition for disabling the sampling clock 1 10 has been met. As such, the pulse width determination circuit 106 disables the sampling clock 110 at time T7 (T7 Te). Accordingly, the sampling counter SMSB stops incrementing. Since the pulse falling edge 94 has fallen within the high clock interval 114, the phase error indicator SLSB will be FALSE (logic “0”). As a result, the digital sampling count SCOUNT is equal to four (4) (SMSB - 2).

[0071] Figures 4G and 4D illustrate two metastability scenarios. Specifically, Figure 4C illustrates a scenario wherein the pulse falling edge 94 coincides with the pulse rising edge 92 of the sampling clock 1 10.

[0072] Herein, at time T1 , the pulse width determination circuit 106 detects the pulse rising edge 92 of the pulse 90. In response, the pulse width determination circuit 106 enables the sampling clock 110 at time T2 (T2 s T1). At time T3 (T3 > T2), the pulse width determination circuit 106 detects the clock falling edge 120. Accordingly, the sampling counter SMSB is increased by 2 (SMSB = 2).

[0073] At time T4 (T4 > T3), the pulse width determination circuit 106 detects the pulse falling edge 94 of the pulse 90, which coincides with the clock rising edge 118 of the sampling clock 1 10. At time T5 (T5 > T4), the pulse width determination circuit 106 detects the clock falling edge 120 of the sampling clock 1 10. Accordingly, the sampling counter SMSB is increased by 2 again (SMSB = 4). At this point, the pulse width determination circuit 106 may produce the digitalsampling count SCOUNT with two different values, depending on whether the pulse width determination circuit 106 has sufficient setup and / or hold time to detect the clock rising edge 118 at time T4.

[0074] If the pulse width determination circuit 106 has sufficient setup / hold time to actually detect the clock rising edge 118 at time T4, the condition for disabling the sampling clock 110 will be met at time T5 and the pulse width determination circuit 106 may disable the sampling clock 110 at time Te (Te s T5). As such, the pulse falling edge 94 will be treated as falling within the low clock interval 1 16 and the sampling error indicator SLSB will be set to TRUE (as shown by the solid line). As a result, the digital sampling count SCOUNT is equal to three (3) (SMSB - 1 ).

[0075] If, however, the pulse width determination circuit 106 does not have sufficient setup / hold time to actually detect the clock rising edge 1 18 at time T4, the pulse width determination circuit 106 will detect both the clock rising edge 1 18 and the clock falling edge 120 at time T? (T? > Te). In this regard, the pulse width determination circuit 106 will process an additional clock cycle 112 (as shown by the dashed line). Accordingly, the sampling counter SMSB is increased by 2 again (SMSB = 6). Thereafter, the pulse width determination circuit 106 disables the sampling clock 1 10 at time Ts (Ts T7). As such, the pulse falling edge 94 will be treated as falling within the high clock interval 114 and the sampling error indicator SLSB will be set to FALSE (shown by the dashed line). As a result, the digital sampling count SCOUNT is equal to four (4) (SMSB - 2).

[0076] Figure 4D illustrates a scenario wherein the pulse falling edge 94 coincides with the clock falling edge 120 of the sampling clock 1 10. Herein, at time T1, the pulse width determination circuit 106 detects the pulse rising edge 92 of the pulse 90. In response, the pulse width determination circuit 106 enables the sampling clock 110 at time T2 (T2 > T1). At time T3 (T3 > T2), the pulse width determination circuit 106 detects the clock falling edge 120. Accordingly, the sampling counter SMSB is increased by 2 (SMSB = 2).

[0077] At time T4 (T4 > T3), the pulse width determination circuit 106 detects the pulse falling edge 94 of the pulse 90, which coincides with the clock fallingedge 120 of the sampling clock 1 10. Accordingly, the sampling counter SMSB is increased by 2 again (SMSB = 4). At time Ts (Ts > T4), the pulse width determination circuit 106 detects both the clock rising edge 1 18 and the clock falling edge 120 that are immediately after the pulse falling edge 94.Accordingly, the sampling counter SMSB is increased by 2 again (SMSB = 6).

[0078] Given that the pulse 90 has turned LOW at time T4 and the pulse width determination circuit 106 detects both the clock rising edge 1 18 and the clock falling edge 120 at time T5, the condition for disabling the sampling clock 1 10 has been met. As such, the pulse width determination circuit 106 disables the sampling clock 110 at time Te (Te Ts). Accordingly, the sampling counter SMSB stops incrementing.

[0079] At this point, the pulse width determination circuit 106 may face a dilemma as to whether the sampling error indicator SLSB should be TRUE or FALSE. If the pulse width determination circuit 106 determines the sampling error indicator SLSB as TRUE, the digital sampling count SCOUNT is equal to five (5) (SMSB - 1 ). Otherwise, the digital sampling count SCOUNT will be equal to four (4) (SMSB - 2).

[0080] Figure 5 is a schematic diagram providing an exemplary illustration of the pulse width determination circuit 106 in Figure 2 configured to handle the various operating scenarios in Figures 4A-4D. Common elements between Figures 2 and 5 are shown therein with common element numbers and will not be re-described herein.

[0081] In an embodiment, the pulse width determination circuit 106 includes a first flip-flop circuit 144, a second flip-flop circuit 146, a sampling counter circuit 148, and an oscillator 150. The oscillator 150, when enabled, is configured to generate the sampling clock 110 as either the half-rate clock or the full-rate clock.

[0082] The first flip-flop circuit 144 is configured to control the oscillator 150 to thereby enable and disable the sampling clock 110. Specifically, the first flip-flop circuit 144 is configured to carry out steps 124, 126, 128, 130, 134, and 136 in the process 122 of Figure 3.

[0083] The second flip-flop circuit 146 is configured to determine the phase error indicator SLSB. More specifically, the second flip-flop circuit 146 is configured to perform step 138 in the process 122.

[0084] The sampling counter circuit 148 is configured to increment the sampling count SMSB, determine the digital sampling count SCOUNT, and the pulse width PWIDTH of the pulse 90. In other words, the sampling counter circuit 148 is configured to carry out steps 132, 140, and 142 in the process 122.

[0085] According to an embodiment of the present disclosure, the first flip-flop circuit 144 includes a pair of first flip-flops 152, 154. The first flip-flops 152, 154 are locked on the clock rising edge 118 and the clock falling edge 120, respectively. As such, when the pulse 90 goes from HIGH to LOW, the first flipflops 152, 154 will be able to first detect the clock rising edge 1 18 after the pulse falling edge 94 and detect the clock falling edge 120 thereafter. Accordingly, the first flip-flop circuit 144 can control the oscillator 150 to disable the sampling clock 110 at or after detecting the clock falling edge 120.

[0086] The second flip-flop circuit 146 includes a pair of second flip-flops 156, 158. Herein, the second flip-flops 156, 158 are configured to track the relative position between the pulse falling edge 94 and a same one of the clock rising edge 118 and the clock falling edge 120 to thereby determine the phase error indicator SLSB. Because the second flip-flops 156, 158 in the second flip-flop circuit 146 are locked on the same edge of the sampling clock 110, the second flip-flop circuit 146 will yield a different phase error indicator SLSB for different values of the sampling counter SMSB.

[0087] The first flip-flop circuit 144 and the second flip-flop circuit 146 as configured herein are effective in handling the metastability scenarios illustrated in Figures 4G and 4D. Specifically, since the first flip-flop circuit 144 and the second flip-flop circuit 146 are clocked on opposite clock edges, the first flip-flop circuit 144 and the second flip-flop circuit 146 will correspond to an opposite polarity. In this regard, if one of the first flip-flop circuit 144 and the second flipflop circuit 146 experiences metastability, the other one of the first flip-flop circuit 144 and the second flip-flop circuit 146 will not. As an example, Figure 6 is aschematic diagram providing an exemplary illustration as to how the pulse width determination circuit 105 in Figure 5 can handle the metastability situation in Figure 40. Common elements between Figures 2 and 6 are shown therein with common element numbers and will not be re-described herein.

[0088] Herein, the pulse falling edge 94 coincides with the clock rising edge 1 18. In one possibility, the first flip-flop circuit 144 may treat the pulse falling edge 94 as in the low clock interval 116 to thereby cause the sampling counter SMSB to count three (3) times (SMSB = 6). In the meantime, the second flip-flop circuit 146 will set the phase error indicator SLSB to TRUE. As a result, the digital sampling count SCOUNT will be equal to five (5) (SMSB - 1 ).

[0089] In another possibility, the first flip-flop circuit 144 may treat the pulse falling edge 94 as in the high clock interval 114 to thereby cause the sampling counter SMSB to count four (4) times (SMSB = 8). In the meantime, the second flipflop circuit 146 will set the phase error indicator SLSB to FALSE. As a result, the digital sampling count SCOUNT will be equal to six (6) (SMSB - 2). Although the digital sampling count SCOU T under the two distinct situations can yield a one (1 ) LSB difference, the overall error margin is still within the reasonable error margin of ±0.5 LSB.

[0090] The single-wire bus apparatus 86 of Figure 2 can be provided in a user element (e.g., a wireless device) to support the embodiments described above.In this regard, Figure 7 is a schematic diagram of an exemplary user element 200 wherein the single-wire bus apparatus 86 of Figure 2 can be provided.

[0091] Herein, the user element 200 can be any type of user elements, such as mobile terminals, smart watches, tablets, computers, navigation devices, access points, and like wireless communication devices that support wireless communications, such as cellular, wireless local area network (WLAN), Bluetooth, and near field communications. The user element 200 will generally include a control system 202, a baseband processor 204, transmit circuitry 206, receive circuitry 208, antenna switching circuitry 210, multiple antennas 212, and user interface circuitry 214. In a non-limiting example, the control system 202 can be a field-programmable gate array (FPGA), as an example. In this regard,the control system 202 can include at least a microprocessor(s), an embedded memory circuit(s), and a communication bus interface(s). The receive circuitry 208 receives radio frequency signals via the antennas 212 and through the antenna switching circuitry 210 from one or more base stations. A low noise amplifier and a filter cooperate to amplify and remove broadband interference from the received signal for processing. Downconversion and digitization circuitry (not shown) will then downconvert the filtered, received signal to an intermediate or baseband frequency signal, which is then digitized into one or more digital streams using analog-to-digital converter(s) (ADC).

[0092] The baseband processor 204 processes the digitized received signal to extract the information or data bits conveyed in the received signal. This processing typically comprises demodulation, decoding, and error correction operations, as will be discussed in greater detail below. The baseband processor 204 is generally implemented in one or more digital signal processors (DSPs) and application specific integrated circuits (ASICs).

[0093] For transmission, the baseband processor 204 receives digitized data, which may represent voice, data, or control information, from the control system 202, which it encodes for transmission. The encoded data is output to the transmit circuitry 206, where a digital-to-analog converter(s) (DAC) converts the digitally encoded data into an analog signal and a modulator modulates the analog signal onto a carrier signal that is at a desired transmit frequency or frequencies. A power amplifier will amplify the modulated carrier signal to a level appropriate for transmission, and deliver the modulated carrier signal to the antennas 212 through the antenna switching circuitry 210. The multiple antennas 212 and the replicated transmit and receive circuitries 206, 208 may provide spatial diversity. Modulation and processing details will be understood by those skilled in the art.

[0094] In an embodiment, the single-wire bus apparatus 86 can be provided in the antenna switching circuitry 210 to enable communications between the antenna switching circuitry 210 and the antennas 212. In other embodiments, the single-wire bus apparatus 86 may also be utilized to enable communicationsbetween the antenna switching circuitry 210, the transmit circuitry 206, and / or the receive circuitry 208.

[0095] Those skilled in the art will recognize improvements and modifications to the embodiments of the present disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.

Claims

ClaimsWhat is claimed is:1 . A pulse width determination circuit configured to: receive a pulse defined by a pulse rising edge and a pulse falling edge; enable a sampling clock having a plurality of clock cycles each comprising a high clock interval defined by a clock rising edge and a clock falling edge followed by a low clock interval in response to detecting the pulse rising edge; increase a sampling counter for each of the plurality of clock cycles of the sampling clock; disable the sampling clock in response to detecting the clock rising edge and the clock falling edge that define the high clock interval immediately after the pulse falling edge; determine a phase error indicator based on a relative position between the pulse falling edge and one of the plurality of clock cycles in the sampling clock; and determine a digital sampling count based on the sampling counter and the phase error indicator.

2. The pulse width determination circuit of claim 1 , comprising: a first flip-flop circuit configured to: enable the sampling clock in response to detecting the pulse rising edge; and disable the sampling clock in response to detecting the clock rising edge and the clock falling edge that define the high clock interval immediately after the pulse falling edge; a second flip-flop circuit configured to determine the phase error indicator; and a sampling counter circuit configured to:increase the sampling counter for each of the plurality of clock cycles of the sampling clock; and determine the digital sampling count and a pulse width of the pulse based on the digital sampling count.

3. The pulse width determination circuit of claim 2, wherein: the first flip-flop circuit comprises a pair of first flip-flops configured to detect the clock rising edge and the clock falling edge, respectively, in each of the plurality of clock cycles; and the second flip-flop circuit comprises a pair of second flip-flops configured to track the relative position between the pulse falling edge and a same one of the clock rising edge and the clock falling edge in the one of the plurality of clock cycles to thereby determine the phase error indicator.

4. The pulse width determination circuit of claim 1 , further configured to determine a pulse width of the pulse based on the digital sampling count and a clock rate of the sampling clock.

5. The pulse width determination circuit of claim 1 , further configured to: enable a half-rate clock as the sampling clock to thereby save sampling power; and enable a full-rate clock twice as fast as that of the half-rate clock as the sampling clock to thereby increase sampling precision.

6. The pulse width determination circuit of claim 1 , further configured to increase the sampling counter by two, 2, for each of the plurality of clock cycles of the sampling clock.

7. The pulse width determination circuit of claim 6, further configured to increase the sampling counter in response to detecting the clock falling edge in each of the plurality of clock cycles.

8. The pulse width determination circuit of claim 1 , further configured to: determine the phase error indicator to be TRUE when the pulse falling edge is within the low clock interval; and determine the phase error indicator to be FALSE when the pulse falling edge is within the high clock interval.

9. The pulse width determination circuit of claim 8, further configured to: determine the digital sampling count to be equal to a value of the sampling counter subtracted by one, 1 , in response to the phase error indicator being TRUE; and determine the digital sampling count to be equal to the value of the sampling counter subtracted by two, 2, in response to the phase error indicator being FALSE.

10. A method for determining a pulse width of a pulse comprising: receiving the pulse defined by a pulse rising edge and a pulse falling edge; enabling a sampling clock having a plurality of clock cycles each comprising a high clock interval defined by a clock rising edge and a clock falling edge followed by a low clock interval in response to detecting the pulse rising edge; increasing a sampling counter for each of the plurality of clock cycles of the sampling clock; disabling the sampling clock in response to detecting the clock rising edge and the clock falling edge that define the high clock interval immediately after the pulse falling edge;determining a phase error indicator based on a relative position between the pulse falling edge and one of the plurality of clock cycles in the sampling clock; and determining a digital sampling count based on the sampling counter and the phase error indicator.1 1 . The method of claim 10, further comprising determining the pulse width of the pulse based on the digital sampling count and a clock rate of the sampling clock.

12. The method of claim 10, further comprising: enabling a half-rate clock as the sampling clock to thereby save sampling power; and enabling a full-rate clock twice as fast as that of the half-rate clock as the sampling clock to thereby increase sampling precision.

13. The method of claim 10, further comprising increasing the sampling counter by two, 2, for each of the plurality of clock cycles of the sampling clock.

14. The method of claim 13, further comprising increasing the sampling counter in response to detecting the clock falling edge in each of the plurality of clock cycles.

15. The method of claim 10, further comprising: determining the phase error indicator to be TRUE when the pulse falling edge is within the low clock interval; and determining the phase error indicator to be FALSE when the pulse falling edge is within the high clock interval.

16. The method of claim 15, further comprising:determining the digital sampling count to be equal to a value of the sampling counter subtracted by one, 1 , in response to the phase error indicator being TRUE; and determining the digital sampling count to be equal to the value of the sampling counter subtracted by two, 2, in response to the phase error indicator being FALSE.

17. A wireless device comprising a single-wire bus apparatus that comprises: a master circuit coupled to a single-wire bus consisting of one wire and configured to communicate a plurality of bus telegrams each preceded by a start-of-sequence, SOS, sequence, the SOS sequence comprises a synchronization pulse defined by a pulse rising edge and a pulse falling edge; and a plurality of slave circuits each coupled to the single-wire bus and comprising a pulse width determination circuit configured to: receive the synchronization pulse via the single-wire bus; enable a sampling clock having a plurality of clock cycles each comprising a high clock interval defined by a clock rising edge and a clock falling edge followed by a low clock interval in response to detecting the pulse rising edge; increase a sampling counter for each of the plurality of clock cycles of the sampling clock; disable the sampling clock in response to detecting the clock rising edge and the clock falling edge that define the high clock interval immediately after the pulse falling edge; determine a phase error indicator based on a relative position between the pulse falling edge and one of the plurality of clock cycles in the sampling clock; and determine a digital sampling count based on the sampling counter and the phase error indicator.

18. The wireless device of claim 17, wherein the pulse width determination circuit comprises: a first flip-flop circuit configured to: enable the sampling clock in response to detecting the pulse rising edge; and disable the sampling clock in response to detecting the clock rising edge and the clock falling edge that define the high clock interval immediately after the pulse falling edge; a second flip-flop circuit configured to determine the phase error indicator; and a sampling counter circuit configured to: increase the sampling counter for each of the plurality of clock cycles of the sampling clock; and determine the digital sampling count and a pulse width of the synchronization pulse based on the digital sampling count.

19. The wireless device of claim 18, wherein: the first flip-flop circuit comprises a pair of first flip-flops configured to detect the clock rising edge and the clock falling edge, respectively, in each of the plurality of clock cycles; and the second flip-flop circuit comprises a pair of second flip-flops configured to track the relative position between the pulse falling edge and a same one of the clock rising edge and the clock falling edge in the one of the plurality of clock cycles to thereby determine the phase error indicator.

20. The wireless device of claim 17, wherein the pulse width determination circuit is further configured to determine a pulse width of the synchronization pulse based on the digital sampling count and a clock rate of the sampling clock.

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