Display substrate and display device

Abstract

A display substrate, comprising a display area (AA) and a peripheral area (BB) surrounding the display area (AA). The display area (AA) comprises at least one arc-shaped display boundary. The display area (AA) comprises M rows of sub-pixels (PX) provided on a base, wherein a pixel circuit of at least one row of sub-pixels (PX) is connected to at least one constant-voltage signal line (INIT) extending in a first direction (X). N rows of sub-pixels close to the arc-shaped display boundary are arranged in a stepped shape. The peripheral area (BB) comprises a first bezel area (B1) located on one side of the display area (AA) in a second direction (Y). The first bezel area (B1) comprises at least one first area constant-voltage power supply line (INITa). The constant-voltage signal line (INIT) connected to the pixel circuit of at least one row of sub-pixels (PX) among the N rows of sub-pixels close to the arc-shaped display boundary is connected to the first area constant-voltage power supply line (INITa) of the first bezel area (B1) by means of a first adapter line (11, 12, 13).

Description

Display substrate and display device Technical Field

[0001] This article relates to but is not limited to display technology, and in particular to a display substrate and a display device. Background Art

[0002] Organic light-emitting diodes (OLEDs) and quantum-dot light-emitting diodes (QLEDs) are active light-emitting display devices with the advantages of self-luminescence, wide viewing angle, high contrast, low power consumption, extremely high response speed, light weight, flexibility and low cost.

[0003] Summary of the Invention

[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0005] Embodiments of the present disclosure provide a display substrate and a display device.

[0006] In one aspect, this embodiment provides a display substrate comprising: a display area and a peripheral area surrounding the display area, the display area including at least one arc-shaped display border. The display area includes M rows of sub-pixels disposed on a substrate, at least one row of the M rows of sub-pixels including a plurality of sub-pixels arranged sequentially along a first direction, at least one of the plurality of sub-pixels including a pixel circuit and a light-emitting element connected to the pixel circuit, and the pixel circuit of at least one row of the M rows of sub-pixels being electrically connected to at least one constant-voltage signal line extending along the first direction. N rows of sub-pixels adjacent to the arc-shaped display border are arranged in a staircase pattern, wherein N and M are both positive integers, and N is less than or equal to M. The peripheral area includes a first border area located on one side of the display area along a second direction intersecting the first direction. The first border area includes at least one first-region constant-voltage power supply line disposed on the substrate. The constant-voltage signal line connected to the pixel circuit of at least one row of the N rows of sub-pixels adjacent to the arc-shaped display border is connected to the first-region constant-voltage power supply line of the first border area via a first adapter line.

[0007] In some exemplary embodiments, the constant voltage signal line connected to the pixel circuit of a row of sub-pixels closest to the first border area among the N rows of sub-pixels close to the arc-shaped display boundary is connected to the first area constant voltage power supply line of the first border area through the first adapter line.

[0008] In some exemplary embodiments, the first adapter line includes a first sub-connection line and a second sub-connection line, wherein the first sub-connection line extends in a direction that intersects with the second sub-connection line, and the first sub-connection line and the second sub-connection line are connected. The constant voltage signal line connected to the pixel circuits of the row of sub-pixels closest to the first border region among the N rows of sub-pixels near the curved display boundary is connected to the first sub-connection line, and the second sub-connection line is connected to the first region constant voltage power supply line located in the first border region.

[0009] In some exemplary embodiments, the constant voltage signal lines transmitting the same signal connected to the pixel circuits of K rows of sub-pixels in the N rows of sub-pixels near the curved display boundary are connected together and connected to the first area constant voltage power supply line of the first border area through the first adapter line, where K is a positive integer less than or equal to N and greater than or equal to 2.

[0010] In some exemplary embodiments, K is smaller than N, and the K rows of sub-pixels are located on a side of the remaining rows of sub-pixels in the N rows of sub-pixels close to the first border area.

[0011] In some exemplary embodiments, the K rows of sub-pixels include seven rows of sub-pixels closest to the first border region among the N rows of sub-pixels.

[0012] In some exemplary embodiments, the first adapter line includes: a first sub-connection line and a second sub-connection line, wherein the first sub-connection line extends in a direction that intersects with the second sub-connection line, and the first sub-connection line and the second sub-connection line are connected. Constant-voltage signal lines transmitting the same signal connected to pixel circuits of adjacent rows of sub-pixels in the K rows of sub-pixels are electrically connected via a series connection line, the constant-voltage signal line connected to the pixel circuit of a row of sub-pixels in the K rows of sub-pixels closest to the first border region is connected to the first sub-connection line, and the second sub-connection line is connected to a first-region constant-voltage power supply line located in the first border region.

[0013] In some exemplary embodiments, the series connection line connected to the constant voltage signal line connected to the pixel circuits of adjacent rows of sub-pixels in the K rows of sub-pixels extends along a staircase formed by the adjacent rows of sub-pixels.

[0014] In some exemplary embodiments, the series connection line is located on a side of the constant voltage signal line to which it is connected that is away from the substrate.

[0015] In some exemplary embodiments, the first and second sub-connection lines are located on a side of the first-region constant-voltage power supply line to which they are connected that is away from the substrate. The second sub-connection line is located on a side of the first sub-connection line that is away from the substrate, or the second sub-connection line and the first sub-connection line are an integrally connected structure.

[0016] In some exemplary embodiments, the first border area further includes: a plurality of electrostatic release circuits, each electrostatic release circuit being connected to a signal line and configured to release static electricity in the connected signal line; and the second sub-connection line is located on a side of the plurality of electrostatic release circuits away from an edge of the display substrate in the first direction.

[0017] In some exemplary embodiments, the peripheral area further includes a second border area located on at least one side of the display area along the first direction. The second border area includes at least one second-area constant-voltage power supply line disposed on the substrate. The second-area constant-voltage power supply line is connected to the first-area constant-voltage power supply line. The constant-voltage signal line connected to the pixel circuit of at least one row of sub-pixels in the M rows of sub-pixels is electrically connected to the second-area constant-voltage power supply line via a second adapter line.

[0018] In some exemplary embodiments, the second border region further includes: at least one gate driving circuit disposed on the substrate; and the second region constant voltage power supply line is located on a side of the gate driving circuit close to the display region.

[0019] In some exemplary embodiments, an orthographic projection of the second-region constant-voltage power supply line on the substrate at least partially overlaps with an orthographic projection of the gate driving circuit on the substrate.

[0020] In some exemplary embodiments, the multiple constant voltage signal lines connected to the pixel circuits of each row of sub-pixel circuits include: a first initial signal line, a second initial signal line, and a third initial signal line. The pixel circuit includes at least: a drive transistor, a first reset transistor, a second reset transistor, and a third reset transistor; the drive transistor has a gate connected to the first node, a first electrode connected to the second node, and a second electrode connected to the third node; the first reset transistor is connected to the third node and the first initial signal line, and is configured to reset the third node using a first initial signal provided by the first initial signal line. The second reset transistor is connected to the second initial signal line and the anode of the light-emitting element, and is configured to reset the anode of the light-emitting element using a second initial signal provided by the second initial signal line. The third reset transistor is connected to the second node and the third initial signal line, and is configured to reset the second node using a third initial signal provided by the third initial signal line. The multiple first-region constant voltage power supply lines provided in the first border region include: a first initial power supply line, a second initial power supply line, and a third initial power supply line. The first initial signal line connected to the pixel circuits of at least one row of N rows of sub-pixels near the curved display boundary is connected to the first initial power supply line of the first frame area. The second initial signal line connected to the pixel circuits of at least one row of N rows of sub-pixels near the curved display boundary is connected to the second initial power supply line of the first frame area. The third initial signal line connected to the pixel circuits of at least one row of N rows of sub-pixels near the curved display boundary is connected to the third initial power supply line of the first frame area. The first initial power supply line, the second initial power supply line, and the third initial power supply line are arranged in sequence along a direction close to the display area.

[0021] In some exemplary embodiments, the peripheral area further includes: a second frame area located on one side of the display area along the first direction, the second frame area being connected to the first frame area. The second frame area includes: a plurality of second-area constant-voltage power supply lines, the plurality of second-area constant-voltage power supply lines including: a fourth initial power supply line, a fifth initial power supply line, and a sixth initial power supply line. The fourth initial power supply line is connected to the first initial power supply line, the fifth initial power supply line is connected to the second initial power supply line, and the sixth initial power supply line is connected to the third initial power supply line. The fourth initial power supply line, the fifth initial power supply line, and the sixth initial power supply line are arranged sequentially along a direction approaching the display area.

[0022] In some exemplary embodiments, the display substrate includes, in a direction perpendicular to the display substrate, a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer disposed on the substrate. The constant voltage signal line is located in the third conductive layer. The at least one first-region constant voltage power supply line is located in the first conductive layer, or in the second conductive layer, or is a dual-layer trace located in both the first and second conductive layers.

[0023] On the other hand, this embodiment provides a display device including the display substrate as described above.

[0024] On the other hand, this embodiment provides a display substrate comprising: a display area and a peripheral area surrounding the display area, wherein the display area includes at least one arc-shaped display border. The display area includes: M rows of sub-pixels disposed on a substrate, at least one row of the M rows of sub-pixels including a plurality of sub-pixels arranged sequentially along a first direction, at least one of the plurality of sub-pixels including a pixel circuit and a light-emitting element connected to the pixel circuit, and the pixel circuit of at least one row of the M rows of sub-pixels connected to at least one constant-voltage signal line extending along the first direction; N rows of sub-pixels adjacent to the arc-shaped display border are arranged in a stepped manner, wherein N and M are both positive integers, and N is less than or equal to M. The peripheral area includes: a first border area located on one side of the display area along a second direction, and a first corner area located outside the arc-shaped display border, the first border area being connected to the first corner area; the second direction intersects the first direction. The first border area includes: at least one first-area constant-voltage power supply line disposed on the substrate. The constant voltage signal line connected to the pixel circuit of at least one row of sub-pixels in the N rows of sub-pixels close to the arc-shaped display boundary is connected to the first area constant voltage power supply line of the first border area through a first adapter line; part of the first adapter line is located in the first corner area.

[0025] In some exemplary embodiments, the first transfer line includes: a first sub-connection line and a second sub-connection line, wherein the first sub-connection line extends in a direction intersecting the direction of extension of the second sub-connection line, and the first sub-connection line and the second sub-connection line are connected; the first sub-connection line is connected to a constant voltage signal line connected to the pixel circuit of at least one row of sub-pixels in the N rows of sub-pixels near the curved display boundary, and the second sub-connection line is connected to the first regional constant voltage power supply line. The connection position between the first sub-connection line and the second sub-connection line is located in the first corner region.

[0026] In some exemplary embodiments, the peripheral area further includes: at least one second-area constant-voltage power supply line, the second-area constant-voltage power supply line extending to the first corner area and connected to the first-area constant-voltage power supply line through the second sub-connection line.

[0027] In some exemplary embodiments, the second-region constant-voltage power supply line and the second sub-connection line connected thereto are an integrated structure connected to each other.

[0028] In some exemplary embodiments, the first corner region further includes: a plurality of cascaded driving units arranged on the substrate, the second-region constant-voltage power supply line is located on a side of the plurality of cascaded driving units close to the display region, and the second sub-connection line is located in the first direction on a side of the plurality of driving units close to the first-region constant-voltage power supply line.

[0029] In some exemplary embodiments, the driving unit is connected to the gate line connected to at least one row of sub-pixels via a driving connection line, and the driving connection line is located on a side of the first sub-connection line close to the display area in the second direction.

[0030] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description.

[0031] Summary of the Figures

[0032] The accompanying drawings are used to provide an understanding of the technical solution of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present application and do not constitute a limitation on the technical solution of the present application.

[0033] FIG1 is a schematic diagram of a display substrate according to at least one embodiment of the present disclosure;

[0034] FIG2 is an equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0035] FIG3 is a timing diagram of the operation of the pixel circuit provided in FIG2 ;

[0036] FIG4A is a schematic diagram of the local structure of area C1 in FIG1 ;

[0037] FIG4B is a schematic diagram of partial connection lines of area C3 in FIG4A ;

[0038] FIG4C is a schematic diagram of partial connection lines of area C4 in FIG4A ;

[0039] 5 is an equivalent circuit diagram of a driving unit of a first scan gate driving circuit according to at least one embodiment of the present disclosure;

[0040] FIG6 is an operation timing diagram of the driving unit of the first gate scan driving circuit shown in FIG5 ;

[0041] FIG7 is an equivalent circuit diagram of an electrostatic discharge circuit according to at least one embodiment of the present disclosure;

[0042] FIG8 is a schematic diagram of the local structure of area C2 in FIG4A ;

[0043] FIG9A is a schematic plan view of region C2 after the third wiring layer is formed in FIG8 ;

[0044] FIG9B is a schematic plan view of the region C2 after the second wiring layer is formed in FIG8 ;

[0045] FIG9C is a schematic plan view of region C2 after the first wiring layer is formed in FIG8 ;

[0046] FIG10A is a partial schematic diagram of a region C1 after forming a first semiconductor layer;

[0047] FIG10B is a partial schematic diagram of the display area after forming the first semiconductor layer;

[0048] FIG10C is a partial schematic diagram of the first corner region after forming the first semiconductor layer;

[0049] FIG11A is a partial schematic diagram of the first conductive layer in region C1;

[0050] FIG11B is a partial schematic diagram of the display area after forming the first conductive layer;

[0051] FIG11C is a partial schematic diagram of the first corner region after forming the first conductive layer;

[0052] FIG12A is a partial schematic diagram of the second conductive layer in region C1;

[0053] FIG12B is a partial schematic diagram of the display area after forming the second conductive layer;

[0054] FIG12C is a partial schematic diagram of the first corner region after forming the second conductive layer;

[0055] FIG13A is a partial schematic diagram of the second semiconductor layer in region C1;

[0056] FIG13B is a partial schematic diagram of the display area after forming the second semiconductor layer;

[0057] FIG14A is a partial schematic diagram of the third conductive layer in region C1;

[0058] FIG14B is a partial schematic diagram of the display area after forming the third conductive layer;

[0059] FIG14C is a partial schematic diagram of the first corner region after forming the third conductive layer;

[0060] FIG15A is a partial schematic diagram of the display area after forming a fifth insulating layer;

[0061] FIG15B is a partial schematic diagram of the first corner region after forming the fifth insulating layer;

[0062] FIG16A is a partial schematic diagram of the fourth conductive layer in region C1;

[0063] FIG16B is a partial schematic diagram of the display area after forming the fourth conductive layer;

[0064] FIG16C is a partial schematic diagram of the first corner region after forming the fourth conductive layer;

[0065] FIG17A is a partial schematic diagram of the display area after forming a seventh insulating layer;

[0066] FIG17B is a partial schematic diagram of the first corner region after forming the seventh insulating layer;

[0067] FIG18A is a partial schematic diagram of a region C1 after forming a fifth conductive layer;

[0068] FIG18B is a schematic diagram of the fifth conductive layer in FIG18A ;

[0069] FIG18C is a partial schematic diagram of the display area after the fifth conductive layer is formed;

[0070] FIG18D is a partial schematic diagram of the first corner region after forming the fifth conductive layer;

[0071] FIG19 is a partial schematic diagram of the display area after forming the eighth insulating layer;

[0072] FIG20A is a partial schematic diagram of the display area after forming the sixth conductive layer;

[0073] FIG20B is a schematic diagram of the sixth conductive layer in FIG20A ;

[0074] FIG21A is a schematic diagram of another partial structure of area C1 in FIG1 ;

[0075] FIG21B is a schematic diagram of partial connection lines of area C5 in FIG21A ;

[0076] FIG21C is a partial connection diagram of area C6 in FIG21A ;

[0077] FIG22 is a partial schematic diagram of a display area according to at least one embodiment of the present disclosure;

[0078] FIG23A is a schematic diagram of the display area after the third conductive layer is formed in FIG22;

[0079] FIG23B is a schematic diagram of the fourth conductive layer in FIG22;

[0080] FIG23C is a schematic diagram of the fifth conductive layer in FIG22;

[0081] FIG24 is another partial structural diagram of area C1 in FIG1 ;

[0082] FIG. 25 is a schematic diagram of a display device according to at least one embodiment of the present disclosure.

[0083] Details

[0084] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. The embodiments can be implemented in a variety of different forms. A person skilled in the art can easily understand that the method and content can be transformed into other forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments and features in the embodiments of the present disclosure can be combined with each other in any manner.

[0085] In the drawings, the size of one or more components, layer thicknesses, or regions may be exaggerated for clarity. Therefore, one embodiment of the present disclosure is not necessarily limited to these dimensions, and the shapes and sizes of one or more components in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate idealized examples, and one embodiment of the present disclosure is not limited to the shapes or values ​​shown in the drawings.

[0086] In this specification, ordinal numbers such as "first," "second," and "third" are provided to avoid confusion among constituent elements, and are not intended to limit the number. "Multiple" in this disclosure means two or more.

[0087] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and is not intended to indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the orientation of the constituent elements being described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced depending on the circumstances.

[0088] In this specification, unless otherwise expressly specified or limited, the terms "mounted," "connected," "connected," and "coupled" should be interpreted broadly. For example, they can refer to fixed connections, removable connections, or integral connections; they can refer to mechanical connections or connections; they can refer to direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the meanings of these terms in this disclosure based on the specific circumstances.

[0089] In this specification, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables transmission of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with multiple functions.

[0090] In this specification, a transistor refers to a device that includes at least three terminals: a gate, a drain, and a source. A transistor has a channel region between the drain (drain electrode terminal, drain region, or drain electrode) and the source (source electrode terminal, source region, or source electrode), and current can flow through the drain, channel region, and source. In this specification, the channel region refers to the region through which current primarily flows.

[0091] In this specification, the first electrode can be referred to as the drain and the second electrode as the source, or vice versa. The functions of "source" and "drain" are sometimes interchanged when using transistors with opposite polarity or when the direction of current changes during circuit operation. Therefore, in this specification, the terms "source" and "drain" can be interchanged. Furthermore, the gate electrode can also be referred to as the control electrode.

[0092] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state where the angle is greater than 85° and less than 95°.

[0093] In this specification, circles, ellipses, triangles, rectangles, trapezoids, pentagons or hexagons are not in the strict sense, but may be approximate circles, approximate ellipses, approximate triangles, approximate rectangles, approximate trapezoids, approximate pentagons or approximate hexagons, etc. There may be some small deformations caused by tolerances, such as chamfers, arc edges and deformations.

[0094] The term "light transmittance" in this disclosure refers to the ability of light to pass through a medium, and is the percentage of the luminous flux passing through a transparent or translucent body to the incident luminous flux.

[0095] In this disclosure, the terms "approximately" and "substantially" are used without strict boundaries, allowing for process and measurement errors. In this disclosure, "same" can include both identical and substantially the same. "Substantially the same" means that the values ​​differ by less than 10%.

[0096] In this disclosure, "A extends along direction B" means that A may include a main portion and a secondary portion connected to the main portion, the main portion being a line, line segment, or strip, extending along direction B, and the length of the main portion extending along direction B being greater than the length of the secondary portion extending along other directions. In this disclosure, "A extends along direction B" means "the main portion of A extends along direction B."

[0097] With the increasing attention paid to narrow-border design, display devices (such as mobile display devices such as mobile phones) have higher and higher requirements for screen border size. By reducing the proportion of the border, the black border of the display can be reduced. On the one hand, it can make the display device (such as a mobile phone) look more fashionable. On the other hand, it can effectively alleviate the problems such as the inconvenience of holding the large-screen display device, making it easier for users to operate. In order to meet the narrow-border design, the corner size of the display device is limited. When the corner space is less than 1.0 mm, the connection space within the corner will be greatly constrained, making it difficult to achieve the control range of the wiring space. For example, when the corner space is less than or equal to 0.95 mm, in order to ensure the line width of the low-potential (VSS) power supply line in the surrounding area, the cut-off area of ​​the gate drive circuit is usually higher than the last row of sub-pixels, so that the connection space of the last few rows of sub-pixels will be severely limited, and normal connection and signal transmission cannot be guaranteed.

[0098] This embodiment provides a display substrate and a display device, which can increase the wiring arrangement space in the peripheral area (such as the corner area), thereby achieving normal signal transmission and facilitating a narrow frame design.

[0099] This embodiment provides a display substrate comprising: a display area and a peripheral area surrounding the display area, wherein the display area includes at least one arc-shaped display border. The display area includes M rows of sub-pixels disposed on a substrate, wherein at least one row of the M rows of sub-pixels includes a plurality of sub-pixels arranged sequentially along a first direction, at least one sub-pixel including a pixel circuit and a light-emitting element connected to the pixel circuit, and the pixel circuit of at least one row of the M rows of sub-pixels is connected to at least one constant-voltage signal line extending along the first direction. N rows of sub-pixels near the arc-shaped display border are arranged in a staircase pattern, where N and M are both positive integers, and N is less than or equal to M. The peripheral area includes a first frame area located on one side of the display area along a second direction. The second direction intersects the first direction; for example, the first direction may be perpendicular to the second direction. The first frame area includes at least one first-region constant-voltage power supply line disposed on the substrate. The constant-voltage signal line connected to the pixel circuit of at least one row of the N rows of sub-pixels near the arc-shaped display border is connected to the first-region constant-voltage power supply line in the first frame area via a first adapter line.

[0100] The display substrate provided in this embodiment is provided with a constant voltage signal line connected to the pixel circuit of at least one row of sub-pixels in the N rows of sub-pixels near the curved display boundary, and is connected to the first area constant voltage power supply line of the first border area. This can reduce the number of wirings in the peripheral area of ​​the curved display boundary and ensure the normal connection of multiple rows of sub-pixels near the curved display boundary, which is conducive to narrow border design.

[0101] In some exemplary embodiments, at least one constant-voltage signal line connected to the pixel circuit of the row of sub-pixels closest to the first border region among the N rows of sub-pixels near the curved display border may be connected to at least one first-region constant-voltage power supply line in the first border region via a first adapter line. In this example, the constant-voltage signal line connected to the pixel circuit of the row of sub-pixels closest to the first border region among the N rows of sub-pixels near the curved display border is connected to the first-region constant-voltage power supply line in the first border region. This ensures normal signal transmission for multiple rows of sub-pixels near the curved display border while reducing the number of wiring in the peripheral area of ​​the curved display border, thereby facilitating a narrow-border design.

[0102] In some exemplary embodiments, the first transfer line may include: a first sub-connection line and a second sub-connection line, the extension direction of the first sub-connection line intersecting the extension direction of the second sub-connection line, and the first sub-connection line and the second sub-connection line being connected. The constant voltage signal line connected to the pixel circuit of the row of sub-pixels closest to the first border area among the N rows of sub-pixels near the arc-shaped display boundary is connected to the first sub-connection line, and the second sub-connection line is connected to the first region constant voltage power supply line located in the first border area. In this example, the connection between the constant voltage signal line and the first region constant voltage power supply line is achieved by sequentially transferring the first sub-connection line and the second sub-connection line, which helps save wiring space. In some examples, the first sub-connection line may be a line extending in a single direction, such as extending in the first direction; or the first sub-connection line may not be a line extending in a single direction, for example, the first sub-connection line may be formed by connecting line segments extending in multiple different directions, and the multiple different directions may include the first direction and other directions intersecting the first direction. In some examples, the second sub-connection line may be a line extending in a single direction, such as the second direction, the third direction, or the fourth direction. Alternatively, the second sub-connection line may not be a line extending in a single direction. For example, the second sub-connection line may be formed by connecting line segments extending in multiple different directions, where the multiple different directions may include the second direction and other directions intersecting the second direction, or the multiple different directions may include the third direction and other directions intersecting the third direction. This embodiment is not limited to this.

[0103] In some exemplary embodiments, the constant voltage signal lines transmitting the same signal connected to the pixel circuits of K rows of sub-pixels in N rows of sub-pixels near the curved display border are connected in series and connected to the first regional constant voltage power supply line of the first border area through a first adapter line, where K is a positive integer less than or equal to N and greater than or equal to 2. For example, K can be less than N, or K can be equal to N. In some examples, the first adapter line may include: a first sub-connection line extending at least along the first direction and a second sub-connection line extending at least along the second direction, the first sub-connection line and the second sub-connection line being connected. The constant voltage signal lines transmitting the same signal connected to the pixel circuits of adjacent rows of sub-pixels in the K rows of sub-pixels are electrically connected through a series connection line, and the constant voltage signal line connected to the pixel circuit of a row of sub-pixels closest to the first border area in the K rows of sub-pixels is connected to the first sub-connection line, and the second sub-connection line is connected to the first regional constant voltage power supply line located in the first border area. In this example, by connecting the constant voltage signal lines transmitting the same signal connected to adjacent sub-pixels in series, the number of wiring in the peripheral area of ​​the curved display border can be reduced, thereby facilitating a narrow border design.

[0104] In some exemplary embodiments, the peripheral area may further include: a second frame area located on at least one side of the display area along the first direction. The second frame area includes: at least one second-region constant voltage power supply line provided on the substrate. The second-region constant voltage power supply line is connected to the first-region constant voltage power supply line. The constant voltage signal line connected to the pixel circuit of at least one row of sub-pixels in the M rows of sub-pixels is electrically connected to the second-region constant voltage power supply line via a second adapter line. For example, the second adapter line can be formed by connecting a line segment extending along the first direction and a line segment extending along other directions intersecting the first direction.

[0105] In some exemplary embodiments, the multiple constant voltage signal lines connected to the pixel circuits of each row of sub-pixel circuits include: a first initial signal line, a second initial signal line, and a third initial signal line. The pixel circuit may include at least: a drive transistor, a first reset transistor, a second reset transistor, and a third reset transistor. The gate of the drive transistor is connected to the first node, the first electrode is connected to the second node, and the second electrode is connected to the third node. The first reset transistor is connected to the third node and the first initial signal line and is configured to reset the third node using a first initial signal provided by the first initial signal line. The second reset transistor is connected to the second initial signal line and the anode of the light-emitting element and is configured to reset the anode of the light-emitting element using a second initial signal provided by the second initial signal line. The third reset transistor is connected to the second node and the third initial signal line and is configured to reset the second node using a third initial signal provided by the third initial signal line. The multiple first-region constant voltage power supply lines provided in the first border region include: a first initial power supply line, a second initial power supply line, and a third initial power supply line. The first initial signal line connected to the pixel circuits of at least one row of sub-pixels in the N rows of sub-pixels near the curved display boundary is connected to the first initial power supply line of the first border region. The second initial signal line connected to the pixel circuit of at least one row of N rows of sub-pixels near the curved display boundary is connected to the second initial power supply line of the first frame area. The third initial signal line connected to the pixel circuit of at least one row of N rows of sub-pixels near the curved display boundary is connected to the third initial power supply line of the first frame area. The first initial power supply line, the second initial power supply line and the third initial power supply line can be arranged in sequence along the direction close to the display area. In this example, by setting the initial signal line connected to the pixel circuit to be connected to the corresponding initial power supply line in the first frame area, the number of wiring in the peripheral area of ​​the curved display boundary can be reduced on the basis of ensuring normal signal transmission, so as to facilitate narrow frame design.

[0106] The solution of this embodiment is illustrated below through some examples.

[0107] Figure 1 is a schematic diagram of a display substrate according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 1 , the display substrate may include: a display area AA and a peripheral area BB surrounding the display area AA. The display area AA may include at least one arc-shaped display boundary. In some examples, the display area AA may include multiple straight display boundaries and multiple arc-shaped display boundaries, and the arc-shaped display boundaries may be connected to the straight display boundaries. For example, as shown in Figure 1 , the display area AA may be roughly a rounded rectangle, and the display area AA may include: a first edge (lower edge) and a second edge (upper edge) disposed oppositely in the second direction Y, and a third edge (left edge) and a fourth edge (right edge) disposed oppositely in the first direction X. The first edge and the second edge may be parallel straight display boundaries, and the third edge and the fourth edge may be parallel straight display boundaries, and adjacent straight display boundaries may be connected by arc-shaped display boundaries. In other examples, the display area AA may include only multiple arc-shaped display boundaries. For example, the display area AA may be a circle or an ellipse formed by connecting multiple arc-shaped display boundaries in sequence. However, this embodiment is not limited to this.

[0108] In some examples, the display area AA may include: M rows of sub-pixels PX. At least one row of sub-pixels PX in the M rows of sub-pixels may include a plurality of sub-pixels arranged in sequence along the first direction X. For example, each row of sub-pixels PX may include a plurality of sub-pixels arranged in sequence along the first direction X. The N rows of sub-pixels close to the curved display boundary may be arranged in a stepped manner. For example, the number of sub-pixels in the N rows of sub-pixels adjacent to the lower frame area and close to the curved display boundary may increase in sequence along the second direction Y. Wherein, N and M may both be positive integers, and N may be less than or equal to M. In some examples, the stepped arrangement may be a 90-degree stepped arrangement, or may be a stepped arrangement at other angles, which may be determined according to the layout of the display substrate. In other examples, the edges of the N rows of sub-pixels close to the curved display boundary may be arranged in a wavy manner.

[0109] In some examples, at least one sub-pixel may include: a pixel circuit and a light-emitting element connected to the pixel circuit. The pixel circuit may be configured to drive the connected light-emitting element. For example, the pixel circuit may be configured to provide a driving current to drive the connected light-emitting element to emit light. The pixel circuit may include multiple transistors and at least one capacitor. For example, the pixel circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, 8T1C or 8T2C structure. In the above circuit structure, T refers to a thin film transistor, C refers to a capacitor, the number before T represents the number of thin film transistors in the circuit, and the number before C represents the number of capacitors in the circuit.

[0110] In some examples, the light-emitting element may be any one of a light-emitting diode (LED), an organic light-emitting diode (OLED), a quantum dot light-emitting diode (QLED), a micro-LED (including mini-LED or micro-LED), etc. For example, the light-emitting element may be an OLED, which may emit red light, green light, blue light, or white light, etc. when driven by its corresponding pixel circuit. The color of the light emitted by the light-emitting element may be determined as needed. In some examples, the light-emitting element may include: an anode, a cathode, and an organic light-emitting layer located between the anode and the cathode. The anode of the light-emitting element may be electrically connected to the corresponding pixel circuit. However, this embodiment is not limited to this.

[0111] In some examples, a pixel unit in display area AA may include three sub-pixels. For example, the three sub-pixels may be a red sub-pixel, a green sub-pixel, and a blue sub-pixel. However, this embodiment is not limited to this. In other examples, a pixel unit in display area AA may include four sub-pixels, and the four sub-pixels may include two green sub-pixels, one red sub-pixel, and one blue sub-pixel. In other examples, a pixel unit may include four sub-pixels, and the four sub-pixels may be a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel.

[0112] In some examples, the shape of the light-emitting element can be a rectangle, a rhombus, a pentagon, or a hexagon. When a pixel unit includes three sub-pixels, the light-emitting elements of the three sub-pixels can be arranged horizontally, vertically, or in a triangular pattern. When a pixel unit includes four sub-pixels, the light-emitting elements of the four sub-pixels can be arranged horizontally, vertically, or in a square pattern. However, this embodiment is not limited to this.

[0113] Figure 2 is an equivalent circuit diagram of a pixel circuit of at least one embodiment of the present disclosure. The pixel circuit of this example is illustrated using an 8T1C structure as an example. In some examples, as shown in Figure 2, the pixel circuit of this example may include eight transistors (i.e., a first pixel transistor PT1 to an eighth pixel transistor PT8) and a storage capacitor Cst. The first pixel transistor PT1 may also be referred to as a first reset transistor, the second pixel transistor PT2 may also be referred to as a threshold compensation transistor, the third pixel transistor PT3 may also be referred to as a drive transistor, the fourth pixel transistor PT4 may also be referred to as a data write transistor, the fifth pixel transistor PT5 may also be referred to as a first light-emitting control transistor, the sixth pixel transistor PT6 may also be referred to as a second light-emitting control transistor, the seventh pixel transistor PT7 may also be referred to as a second reset transistor, and the eighth pixel transistor PT8 may also be referred to as a third reset transistor. The light-emitting element EL may include an anode, a cathode, and an organic light-emitting layer disposed between the anode and the cathode.

[0114] In some examples, the first pixel transistor PT1, the third pixel transistor PT3, the eighth pixel transistor PT8 can be a first type transistor, for example, a P-type transistor, and the second pixel transistor PT2 can be a second type transistor, for example, an N-type transistor. However, this embodiment is not limited to this. For example, the multiple transistors in the pixel circuit can all be P-type transistors, or can all be N-type transistors. Using the same type of transistors in the pixel circuit can simplify the process flow, reduce the process difficulty of the display substrate, and improve the product yield.

[0115] In some examples, the first type of transistor of the pixel circuit (for example, including the first pixel transistor PT1, the third pixel transistor PT3 to the eighth pixel transistor PT8) can adopt a low-temperature polysilicon thin film transistor, and the second type of transistor of the pixel circuit (for example, including the second pixel transistor PT2) can adopt an oxide thin film transistor. The active layer of the low-temperature polysilicon thin film transistor adopts low-temperature polysilicon (LTPS), and the active layer of the oxide thin film transistor adopts an oxide semiconductor (Oxide). Low-temperature polysilicon thin film transistors have the advantages of high mobility and fast charging, and oxide thin film transistors have the advantages of low leakage current. Integrating low-temperature polysilicon thin film transistors and oxide thin film transistors on a display substrate to form a low-temperature polycrystalline oxide (LTPS+Oxide) display substrate can take advantage of the advantages of both, achieve low-frequency driving, reduce power consumption, and improve display quality.

[0116] In some examples, as shown in FIG2 , the pixel circuit can be electrically connected to a first scan line GL1, a second scan line GL2, a data line DL, a first power line VDD, a second power line VSS, an emission control line EML, a first initial signal line INIT1, a second initial signal line INIT2, a third initial signal line INIT3, a first reset control line RST1, and a second reset control line RST2. The first power line VDD can be configured to provide a constant first voltage signal Vdd to the pixel circuit, and the second power line VSS can be configured to provide a constant second voltage signal Vss to the pixel circuit, with the first voltage signal Vdd being greater than the second voltage signal Vss. The first scan line GL1 can be configured to provide a first scan signal SCAN1 to the pixel circuit. The second scan line GL2 can be configured to provide a second scan signal SCAN2 to the pixel circuit. The data line DL can be configured to provide a data signal to the pixel circuit. The emission control line EML can be configured to provide an emission control signal EM to the pixel circuit. The first reset control line RST1 can be configured to provide a first reset control signal RESET1 to the pixel circuit. The second reset control line may be configured to provide a second reset control signal RESET2 to the pixel circuit.

[0117] In some examples, as shown in FIG2 , the gate of the third pixel transistor PT3 is electrically connected to the first node PN1, the first electrode of the third pixel transistor PT3 is electrically connected to the second node PN2, and the second electrode of the third pixel transistor PT3 is electrically connected to the third node PN3. The gate of the fourth pixel transistor PT4 is electrically connected to the first scan line GL1, the first electrode of the fourth pixel transistor PT4 is electrically connected to the data line DL, and the second electrode of the fourth pixel transistor PT4 is electrically connected to the second node PN2. The gate of the second pixel transistor PT2 is electrically connected to the second scan line GL2, the second electrode of the second pixel transistor PT2 is electrically connected to the first node PN1, and the first electrode of the second pixel transistor PT2 is electrically connected to the third node PN3. The gate of the fifth pixel transistor PT5 is electrically connected to the emission control line EML, the first electrode of the fifth pixel transistor PT5 is electrically connected to the first power line VDD, and the second electrode of the fifth pixel transistor PT5 is electrically connected to the second node PN2. The gate of the sixth pixel transistor PT6 is electrically connected to the emission control line EML, the first electrode of the sixth pixel transistor PT6 is electrically connected to the third node PN3, and the second electrode of the sixth pixel transistor PT6 is electrically connected to the fourth node PN4. The gate of the first pixel transistor PT1 is electrically connected to the first reset control line RST1, the first electrode of the first pixel transistor PT1 is electrically connected to the first initial signal line INIT1, and the second electrode of the first pixel transistor PT1 is electrically connected to the third node PN3. The first pixel transistor PT1 can be configured to reset the third node PN3. The gate of the seventh pixel transistor PT7 is electrically connected to the second reset control line RST2, the first electrode of the seventh pixel transistor PT7 is electrically connected to the second initial signal line INIT2, and the second electrode of the seventh pixel transistor PT7 is electrically connected to the fourth node PN4. The seventh pixel transistor PT7 can be configured to reset the fourth node PN4. The gate of the eighth pixel transistor PT8 is electrically connected to the second reset control line RST2, the first electrode of the eighth pixel transistor PT8 is electrically connected to the third initial signal line INIT3, and the second electrode of the eighth pixel transistor PT8 is electrically connected to the second node PN2. The eighth pixel transistor PT8 can be configured to reset the second node PN2. The first electrode of the storage capacitor Cst is electrically connected to the first node PN1, and the second electrode of the storage capacitor Cst is electrically connected to the first power supply line VDD.

[0118] In this example, the first node PN1 is the connection point of the storage capacitor Cst, the second pixel transistor PT2 and the third pixel transistor PT3, the second node PN2 is the connection point of the fifth pixel transistor PT5, the fourth pixel transistor PT4, the eighth pixel transistor PT8 and the third pixel transistor PT3, the third node PN3 is the connection point of the first pixel transistor PT1, the third pixel transistor PT3, the second pixel transistor PT2 and the sixth pixel transistor PT6, and the fourth node PN4 is the connection point of the sixth pixel transistor PT6, the seventh pixel transistor PT7 and the light-emitting element EL.

[0119] FIG3 is an operating timing diagram of the pixel circuit shown in FIG2. The operation of the pixel circuit shown in FIG2 will be described below with reference to FIG3. Specifically, the first pixel transistor PT1, the third pixel transistor PT3, the eighth pixel transistor PT8, and the second pixel transistor PT2 are P-type transistors, respectively.

[0120] In some examples, as shown in FIG. 2 and FIG. 3 , during a frame display period, the operation process of the pixel circuit may include at least: a first stage S11 , a second stage S12 , a third stage S13 , and a fourth stage S14 .

[0121] The first phase S11 is called the first reset phase. The second reset control signal RESET2 provided by the second reset control line RST2 is a low-level signal, turning on the seventh pixel transistor PT7 and the eighth pixel transistor PT8. The second scan signal SCAN2 provided by the second scan line GL2 is a high-level signal, turning on the second pixel transistor PT2. The eighth pixel transistor PT8 is turned on, allowing the third initial signal provided by the third initial signal line INIT3 to be supplied to the second node PN2. The seventh pixel transistor PT7 is turned on, allowing the second initial signal provided by the second initial signal line INIT2 to be supplied to the fourth node PN4, initializing the fourth node PN4. The first scan signal SCAN1 provided by the first scan line GL1 is a high-level signal, the first reset control signal RESET1 provided by the first reset control line RST1 is a high-level signal, and the emission control signal EM provided by the emission control line EML is a high-level signal, turning off the fourth pixel transistor PT4, the first pixel transistor PT1, the fifth pixel transistor PT5, and the sixth pixel transistor PT6. During this phase, the light-emitting element EL does not emit light.

[0122] The second stage S12 is called the second reset stage. The first reset control signal RESET1 provided by the first reset control line RST1 is a low-level signal, turning on the first pixel transistor PT1; the second scan signal SCAN2 provided by the second scan line GL2 is a high-level signal, turning on the second pixel transistor PT2. The first pixel transistor PT1 and the second pixel transistor PT2 are turned on, so that the first initial signal line provided by the first initial signal line INIT1 is provided to the first node PN1, initializing the first node PN1. The second reset control signal RESET2 provided by the second reset control line RST2 is a high-level signal, the first scan signal SCAN1 provided by the first scan line GL1 is a high-level signal, and the emission control signal EM provided by the emission control line EML is a high-level signal, turning off the seventh pixel transistor PT7, the eighth pixel transistor PT8, the fourth pixel transistor PT4, the fifth pixel transistor PT5, and the sixth pixel transistor PT6. During this stage, the light-emitting element EL does not emit light.

[0123] The third stage S13 is called the data writing stage or the threshold compensation stage. The first scan signal SCAN1 provided by the first scan line GL1 is a low-level signal, and the fourth pixel transistor PT4 is turned on. The second scan signal SCAN2 provided by the second scan line GL2 is a high-level signal, and the second pixel transistor PT2 is turned on. During this stage, the first electrode of the storage capacitor Cst is at a low level, and the third pixel transistor PT3 is turned on. The second pixel transistor PT2, the fourth pixel transistor PT4, and the third pixel transistor PT3 are turned on, so that the data voltage Vdata output by the data line DL is provided to the first node PN1 through the second node PN2, the turned-on third pixel transistor PT3, the third node PN3, and the turned-on second pixel transistor PT2. The difference between the data voltage Vdata output by the data line DL and the threshold voltage of the third pixel transistor PT3 is charged into the storage capacitor Cst. The voltage at the first electrode of the storage capacitor Cst (i.e., the first node PN1) is Vdata-|Vth|, where Vdata is the data voltage output by the data line DL and Vth is the threshold voltage of the third pixel transistor PT3. The first reset control signal RESET1 provided by the first reset control line RST1 is a high-level signal, the second reset control signal RESET2 provided by the second reset control line RST2 is a high-level signal, and the light-emitting control signal EM provided by the light-emitting control line EML is a high-level signal, so that the first pixel transistor PT1, the seventh pixel transistor PT7, the eighth pixel transistor PT8, the fifth pixel transistor PT5 and the sixth pixel transistor PT6 are disconnected.

[0124] In the fourth stage S14, the light-emission control signal EM provided by the light-emission control line EML can be switched from a high-level signal to a low-level signal, turning on the fifth pixel transistor PT5 and the sixth pixel transistor PT6. The second scan signal SCAN2 provided by the second scan line GL2 is a low-level signal, turning off the second pixel transistor PT2. The first scan signal SCAN1 provided by the first scan line GL1, the first reset control signal RESET1 provided by the first reset control line RST1, and the second reset control signal RESET2 provided by the second reset control line RST2 are high-level signals, turning off the fourth pixel transistor PT4, the first pixel transistor PT1, the seventh pixel transistor PT7, and the eighth pixel transistor PT8. The first voltage signal Vdd output by the first power line VDD can provide a driving voltage to the anode of the light-emitting element EL through the turned-on fifth pixel transistor PT5, the third pixel transistor PT3, and the sixth pixel transistor PT6, thereby driving the light-emitting element EL to emit light.

[0125] During the driving process of the pixel circuit, the driving current flowing through the third pixel transistor PT3 is determined by the voltage difference between its gate and the first electrode. Since the voltage of the first node PN1 is Vdata-|Vth|, the driving current of the third pixel transistor PT3 is: I=K×(Vgs-Vth) 2 =K×[(Vdd-Vdata+|Vth|)-Vth] 2 =K×[Vdd-Vdata] 2 ;

[0126] Among them, I is the driving current flowing through the third pixel transistor PT3, that is, the driving current driving the light-emitting element, K is a constant, Vgs is the voltage difference between the gate and the first electrode of the third pixel transistor PT3, Vth is the threshold voltage of the third pixel transistor PT3, Vdata is the data voltage output by the data line DL, and Vdd is the first voltage signal output by the first power line VDD.

[0127] From the above equation, it can be seen that the current flowing through the light-emitting element is independent of the threshold voltage of the third pixel transistor PT3. Therefore, the pixel circuit of this embodiment can effectively compensate for the threshold voltage of the third pixel transistor PT3. Moreover, the pixel circuit provided by this embodiment can improve the display quality caused by low frequency and enhance the display effect of the light-emitting element.

[0128] In some examples, as shown in FIG1 , the peripheral area BB may include: a first border area (lower border) B1 and a third border area (upper border) B3 arranged opposite to each other in the second direction Y, and two second border areas (including a left border B2a and a right border B2b) arranged opposite to each other in the first direction X. The first border area B1 is adjacent to a first edge of the display area AA, the third border area B3 is adjacent to a second edge of the display area AA, the left border B2a is adjacent to a third edge of the display area AA, and the right border B2b is adjacent to a fourth edge of the display area AA.

[0129] In some examples, as shown in Figure 1, the peripheral area BB may further include: four corner areas (for example, including two first corner areas B4a and B4b, and two second corner areas B5a and B5b). The first border area B1 can be connected to the left border B2a through the first corner area B4a, and the first border area B1 can be connected to the right border B2b through the first corner area B4b; the third border area B3 can be connected to the left border B2a through the second corner area B5a, and can also be connected to the right border B2b through the second corner area B5b. The four corner areas can each correspond to an arc-shaped display boundary of the display area AA, and the corner areas can be located on the periphery of the corresponding arc-shaped display boundary. The edge of the corner area away from the side of the display area AA can be a curved edge.

[0130] In some examples, as shown in FIG1 , the peripheral area BB may include: multiple gate drive circuits (e.g., including at least one first gate drive circuit GA1 and at least one second gate drive circuit GA2). In some examples, the multiple first gate drive circuits GA1 may be disposed in the left frame B2a, the first corner area B4a, and the second corner area B5a, and the multiple second gate drive circuits GA2 may be disposed in the right frame B2b, the first corner area B4b, and the second corner area B5b.

[0131] In some examples, the number of first gate drive circuits GA1 can be three, for example, including a first scan gate drive circuit that provides a first scan signal, a second scan gate drive circuit that provides a second scan signal, and a first reset gate drive circuit that provides a first reset control signal. The number of second gate drive circuits GA2 can be two, for example, including a second reset gate drive circuit that provides a second reset control signal and a light-emitting control gate drive circuit that provides a light-emitting control signal. However, this embodiment is not limited to this. In other examples, the number of first gate drive circuits GA1 and second gate drive circuits GA2 can be the same.

[0132] In some examples, as shown in FIG1 , each gate driver circuit may include multiple cascaded driver units. Each driver unit may be configured to provide a driver signal to at least one row of sub-pixels within the display area AA. The multiple driver units of a single gate driver circuit may be arranged sequentially along an edge of the display area AA.

[0133] In some examples, as shown in FIG1 , the peripheral area BB may further include a second power supply line (also referred to as a low-potential power supply line) S_VSS. The second power supply line S_VSS may be located on a side of the plurality of gate drive circuits away from the display area AA and may be electrically connected to a second power line connected to the light-emitting elements within the display area AA. The second power supply line S_VSS may have a generally ring-shaped structure. However, this embodiment is not limited thereto.

[0134] In some examples, as shown in Figure 1, the peripheral area BB may further include: at least one constant voltage power supply line. Each constant voltage power supply line may include: a first area constant voltage power supply line INITa located in the first border area B1 and a second area constant voltage power supply line INITb located at least in the second border area (including the left border B2a and the right border B2b). The first area constant voltage power supply line INITa can be electrically connected to the second area constant voltage power supply line INITb that transmits the same signal. For example, the second area constant voltage power supply line INITb can extend from the left border B2a through the first corner area B4a to be electrically connected to the first area constant voltage power supply line INITa; the second area constant voltage power supply line INITb can also extend from the right border B2b through the first corner area B4b to be electrically connected to the first area constant voltage power supply line INITa.

[0135] In some examples, as shown in FIG1 , the pixel circuits of each row of sub-pixels in the display area can be connected to at least one constant-voltage signal line INIT extending along the first direction X. The constant-voltage signal line INIT connected to the pixel circuits of at least one row of sub-pixels near the curved display boundary can be connected to the first-region constant-voltage power supply line INITa of the first border area B1 , thereby reducing the number of wirings in the first corner areas B4a and B4b and facilitating a narrow-border design.

[0136] Figure 4A is a schematic diagram of the partial structure of region C1 in Figure 1. Figure 4B is a schematic diagram of the partial connection of region C3 in Figure 4A. Figure 4C is a schematic diagram of the partial connection of region C4 in Figure 4A. Figure 4A uses eight rows of sub-pixels (e.g., rows M-7 through M) near the curved display boundary of display area AA as an example, where the Mth row of sub-pixels may be closest to the first border region B1, and M may be a positive integer. The Mth row of sub-pixels may be the last row of sub-pixels on the display substrate.

[0137] In some examples, as shown in Figures 4A to 4C, the pixel circuit of each row of sub-pixels can be electrically connected to three constant voltage signal lines (for example, including a first initial signal line INIT1, a second initial signal line INIT2, and a third initial signal line INIT3). At least one constant voltage signal line connected to the pixel circuit of the M-th row of sub-pixels can be connected to the first regional constant voltage power supply line located in the first border area B1 through a first adapter line. The first regional constant voltage power supply line of the first border area B1 may include: a first initial power supply line INIT1a, a second initial power supply line INIT2a, and a third initial power supply line INIT3a. The second initial signal line INIT2(m) connected to the pixel circuit of the M-th row of sub-pixels can be electrically connected to the second initial power supply line INIT2a through the first adapter line 12, and the third initial signal line INIT3(m) connected to the pixel circuit of the M-th row of sub-pixels can be electrically connected to the third initial power supply line INIT3a through the first adapter line 13. The first initial signal line INIT1(m) located between the second initial signal line INIT2(m) and the third initial signal line INIT3(m) can be electrically connected to the first initial power supply line INIT1a through the first adapter line 11. In some examples, the pixel circuit of the Mth row of sub-pixels can be connected to the first initial signal line INIT1(m) closest to the first border area B1; or, the pixel circuit of the Mth row of sub-pixels can be connected to the first initial signal line INIT1(m-1) whose orthographic projection on the substrate overlaps with the pixel circuit of the M-1th row of sub-pixels, and the first initial signal line INIT1(m) closest to the first border area B1 can serve as an auxiliary initial signal line to ensure routing uniformity in the display area without the need for connection to the pixel circuit.

[0138] In some examples, as shown in Figures 4A to 4C, each first transfer line may include: a first sub-connection line and a second sub-connection line, and the first sub-connection line and the second sub-connection line are connected. The extension direction of the first sub-connection line may intersect with the extension direction of the second sub-connection line. For example, the first sub-connection line may be roughly in the shape of a broken line extending along the first direction X, and the second sub-connection line may be roughly in the shape of a broken line extending along the second direction Y. The first sub-connection line may include a line segment extending along the first direction X and a line segment extending along the remaining directions intersecting the first direction X. The second sub-connection line may include a line segment extending along the second direction Y and a line segment extending along the remaining directions intersecting the second direction Y. However, this embodiment is not limited to this. In other examples, the first sub-connection line may extend along the first direction X, and the second sub-connection line may extend along the second direction Y.

[0139] For example, the first patch line 11 may include a first sub-connection line 111 and a second sub-connection line 112; the first patch line 12 may include a first sub-connection line 121 and a second sub-connection line 122; and the first patch line 13 may include a first sub-connection line 131 and a second sub-connection line 132. For example, a portion of each first patch line may be located in the first corner area B4a.

[0140] In some examples, as shown in Figures 4A to 4C, at least one constant voltage signal line connected to the pixel circuits of the remaining rows of sub-pixels other than the Mth row of sub-pixels (for example, including the M-7th row to the M-1th row of sub-pixels in Figure 4A) can be connected to the second regional constant voltage power supply line located in the first corner area B4a through a second adapter line. The second regional constant voltage power supply line of this example may include: a fourth initial signal line INIT1b, a fifth initial power supply line INIT2b, and a sixth initial power supply line INIT3b. The fourth initial power supply line INIT1b can be connected to the first initial power supply line INIT1a and configured to transmit the first initial signal; the fifth initial power supply line INIT2b can be connected to the second initial power supply line INIT2a and configured to transmit the second initial signal; the sixth initial power supply line INIT3b can be connected to the third initial power supply line INIT3a and configured to transmit the third initial signal.

[0141] In some examples, as shown in FIG4C , the first initial signal line INIT1(m-1) overlapping with the orthographic projection of the pixel circuit of the M-1th row of sub-pixels on the substrate can be electrically connected to the fourth initial power supply line INIT1b via the second adapter line 141, the second initial signal line INIT2(m-1) connected to the pixel circuit of the M-1th row of sub-pixels can be electrically connected to the fifth initial power supply line INIT2b via the second adapter line 142, and the third initial signal line INIT3(m-1) connected to the pixel circuit of the M-1th row of sub-pixels can be electrically connected to the sixth initial power supply line INIT3b via the second adapter line 143. The second adapter lines 141, 142, and 143 can extend into the first corner area B4a and be connected to the corresponding initial power supply lines.

[0142] In some examples, as shown in FIG4A , three first gate drive circuits (e.g., including a first scan gate drive circuit GA1a, a second scan gate drive circuit GA1b, and a first reset gate drive circuit GA1c) may be provided in the left border B2a and the first corner area B4a. The first scan gate drive circuit GA1a, the second scan gate drive circuit GA1b, and the first reset gate drive circuit GA1c may be arranged sequentially in a direction away from the display area AA. Each first gate drive circuit may include multiple cascaded drive units. The first scan gate drive circuit GA1a may be configured to provide a first scan signal SCAN1 to the pixel circuits in the display area. For example, the output end of each stage of the drive unit in the first scan gate drive circuit GA1a may be electrically connected to a first scan line (e.g., first scan line GL1(m), GL1(m-1)) to which the pixel circuits of a row of sub-pixels are connected via a first drive connection line 151. The second scan gate drive circuit GA1b may be configured to provide a second scan signal SCAN2 to the pixel circuits in the display area. For example, the output end of each level of the driving unit in the second scan gate driving circuit can be connected to two adjacent second driving connection lines 152 so as to be electrically connected to the second scan line (e.g., the second scan line GL2(m-1), GL2(m)) connected to the pixel circuits of two adjacent rows of sub-pixels. The first reset gate driving circuit GA1c can be configured to provide a first reset control signal RESET1 to the pixel circuits of the display area. For example, the output end of each level of the driving unit in the first reset gate driving circuit can be connected to two third driving connection lines 153 so as to be electrically connected to the first reset control line (e.g., the first reset control line RST1(m-1), RST1(m)) connected to the pixel circuits of two adjacent rows of sub-pixels.

[0143] In some examples, two second gate driver circuits (e.g., including a second reset gate driver circuit and a light emission control gate driver circuit) may be provided in the right bezel B2b and the second corner region B4b. The second reset gate driver circuit may be configured to provide a second reset control signal RESET2 to the pixel circuits in the display area. The light emission control gate driver circuit may be configured to provide a light emission control signal EM to the pixel circuits in the display area.

[0144] In some examples, as shown in FIG4A , the first border region B1 may further include: a plurality of drive control lines. The plurality of drive control lines may extend from the first border region B1 to the first corner region B4a and be electrically connected to the first scan gate drive circuit GA1a, the second scan gate drive circuit GA1b, and the first reset gate drive circuit GA1c. The first initial power supply line INIT1a, the second initial power supply line INIT2a, and the third initial power supply line INIT3a may be located between the plurality of drive control lines.

[0145] In some examples, as shown in FIG4A , the first border area B1 may also be provided with a plurality of electrostatic release circuits 19. A plurality of drive control lines may be electrically connected to the plurality of electrostatic release circuits 19. For example, each drive control line may be connected to an electrostatic release circuit. The plurality of electrostatic release circuits 19 may be located between the second sub-connection line of the first adapter line and the three first gate drive circuits. The second sub-connection lines of the three first adapter lines may be located on a side of the plurality of electrostatic release circuits 19 away from the first gate drive circuit in the first direction X. The setting position of the first adapter line in this example is conducive to wiring arrangement.

[0146] In some examples, as shown in FIG4A , in order to ensure the line width L0 of the second power supply line S_VSS, the cutoff position GP of the gate drive circuit is generally higher than the last row of sub-pixels (i.e., the Mth row of sub-pixels in FIG4A ). The connection space (e.g., denoted as s) between the cutoff position of the gate drive circuit and the closest row of sub-pixels can be the product of the number of sub-pixel rows that have not yet been connected (e.g., denoted as n), the line width of the connection (e.g., denoted as p), and the number of connections (e.g., denoted as b), i.e., s=n*p*b. In this example, for the first corner area after size reduction, by transferring the constant voltage signal line connected to the first row of sub-pixels to the first area constant voltage power supply line of the first border area, the number of connections b can be reduced, thereby reducing the connection space s between the cutoff position GP of the gate drive circuit and the closest row of sub-pixels, thereby not only ensuring the normal connection and signal transmission between the gate drive circuit and the sub-pixels, but also facilitating the realization of a narrow border design.

[0147] In some examples, taking the example of seven rows of sub-pixels below the cutoff position GP of the gate drive circuit that need to be connected to the gate drive circuit, the required connection space s = 7*4.2*6 = 176.4 μm between the cutoff position GP of the gate drive circuit and the closest row of sub-pixels, plus the spacing between the two outermost traces and the adjacent traces on the same layer, that is, 6 μm on both sides, therefore, the required connection space s is at least 182.4 μm. However, in some examples, when the corner area space is less than 1.0 mm, the actual connection space s between the cutoff position GP and the closest row of sub-pixels is only 177 μm. This example reduces the wiring in the first corner area by providing signals from the first border area to the first initial signal line, the second initial signal line, and the third initial signal line closest to the first border area. In this example, the first initial signal line closest to the first border area serves only as an auxiliary initial signal line and is not connected to the pixel circuit of the Mth row of sub-pixels. It does not need to extend to the first corner area to be connected to the second-region constant voltage power supply line; the pixel circuit of the Mth row of sub-pixels is connected to the second initial signal line and the third initial signal line closest to the first border area. In this example, by setting the second initial signal line and the third initial signal line connected to the pixel circuit of the last row of sub-pixels (i.e., the Mth row of sub-pixels) to be connected to the first-region constant voltage power supply line of the first border area, the second adapter line required to connect the second initial signal line and the third initial signal line connected to the pixel circuit of the last row of sub-pixels to the second-region constant voltage power supply line can be saved, that is, two lines extending toward the gate drive circuit are reduced, and the required connection space can be reduced by 2 line widths, i.e., 4.2*2=8.4μm, so that the required connection space s=182.4-8.4=174μm<177μm. This example can meet the design requirements of a narrow border.

[0148] FIG5 is an equivalent circuit diagram of a driving unit of a first scan gate driving circuit according to at least one embodiment of the present disclosure. In some examples, as shown in FIG5 , the driving unit of the first scan gate driving circuit may include: eight transistors (i.e., a first shift transistor GT1, a second shift transistor GT2, a third shift transistor GT3, a fourth shift transistor GT4, a fifth shift transistor GT5, a sixth shift transistor GT6, a seventh shift transistor GT7, and an eighth shift transistor GT8) and two capacitors (a first capacitor GC1 and a second capacitor GC2). The fourth shift transistor GT4 and the fifth shift transistor GT5 are output transistors of the driving unit.

[0149] In some examples, as shown in FIG5 , the control electrode of the first shift transistor GT1 is electrically connected to the first clock signal line GCK, the first electrode of the first shift transistor GT1 is electrically connected to the shift input terminal GIN, and the second electrode of the first shift transistor GT1 is electrically connected to the first shift node GN1. The control electrode of the second shift transistor GT2 is electrically connected to the first shift node GN1, the first electrode of the second shift transistor GT2 is electrically connected to the first clock signal line GCK, and the second electrode of the second shift transistor GT2 is electrically connected to the second shift node GN2. The control electrode of the third shift transistor GT3 is electrically connected to the first clock signal line GCK, the first electrode of the third shift transistor GT3 is electrically connected to the fourth power line VGL, and the second electrode of the third shift transistor GT3 is electrically connected to the second shift node GN2. The control electrode of the fourth shift transistor GT4 is electrically connected to the second shift node GN2, the first electrode of the fourth shift transistor GT4 is electrically connected to the third power line VGH, and the second electrode of the fourth shift transistor GT4 is electrically connected to the shift output terminal GOUT. The control electrode of the fifth shift transistor GT5 is electrically connected to the third shift node GN3, the first electrode of the fifth shift transistor GT5 is electrically connected to the second clock signal line GCB, and the second electrode of the fifth shift transistor GT5 is electrically connected to the shift output terminal GOUT. The control electrode of the sixth shift transistor GT6 is electrically connected to the second shift node GN2, the first electrode of the sixth shift transistor GT6 is electrically connected to the third power supply line VGH, and the second electrode of the sixth shift transistor GT6 is electrically connected to the first electrode of the seventh shift transistor GT7. The control electrode of the seventh shift transistor GT7 is electrically connected to the second clock signal line GCB, and the second electrode of the seventh shift transistor GT7 is electrically connected to the first shift node GN1. The control electrode of the eighth shift transistor GT8 is electrically connected to the fourth power supply line VGL, the first electrode of the eighth shift transistor GT8 is electrically connected to the first shift node GN1, and the second electrode of the eighth shift transistor GT8 is electrically connected to the third shift node GN3. The second electrode of the first capacitor GC1 is electrically connected to the third power supply line VGH, and the first electrode of the first capacitor GC1 is electrically connected to the second shift node GN2. A second electrode of the second capacitor GC2 is electrically connected to the shift output terminal GOUT, and a first electrode of the second capacitor GC2 is electrically connected to the third shift node GN3.

[0150] In some examples, as shown in FIG5 , the first shift node GN1 is a connection point of the first shift transistor GT1, the second shift transistor GT2, the seventh shift transistor GT7, and the eighth shift transistor GT8. The second shift node GN2 is a connection point of the second shift transistor GT2, the third shift transistor GT3, the fourth shift transistor GT4, the sixth shift transistor GT6, and the first capacitor GC1. The third shift node GN3 is a connection point of the eighth shift transistor GT8, the fifth shift transistor GT5, and the second capacitor GC2.

[0151] In some examples, the first shift transistor GT1 to the eighth shift transistor GT8 of the first scan gate driving circuit shown in FIG5 may all be P-type transistors or N-type transistors. However, this embodiment is not limited thereto.

[0152] FIG6 is an operating timing diagram of the driving unit of the first gate scan driving circuit shown in FIG5 . In some examples, the first shift transistor GT1 to the eighth shift transistor GT8 of the driving unit shown in FIG5 are all P-type transistors. For example, the shift input terminal GIN of the first-stage driving circuit is electrically connected to the first start signal line GSTV. As shown in FIG5 and FIG6 , the driving unit of the first gate scan driving circuit of this exemplary embodiment may include eight transistor units (i.e., the first shift transistor GT1 to the eighth shift transistor GT8), two capacitor units (i.e., the first capacitor GC1 and the second capacitor GC2), three input terminals (i.e., the first clock signal line GCK, the second clock signal line GCB, and the shift input terminal GIN), one output terminal (i.e., the shift output terminal GOUT), and two power supply terminals (i.e., the third power supply line VGH and the fourth power supply line VGL). The third power supply line VGH can be configured to continuously provide a high-level signal, and the fourth power supply line VGL can be configured to continuously provide a low-level signal.

[0153] In some examples, as shown in FIG5 and FIG6 , the operation process of the driving unit of the first scan driving circuit of this example may include the following stages.

[0154] In the first phase S21, the first clock signal line GCK provides a low-level first clock signal, and the shift input terminal GIN receives a low-level trigger signal. Therefore, the first shift transistor GT1 and the third shift transistor GT3 are turned on. The turned-on first shift transistor GT1 transmits the low-level trigger signal to the first shift node GN1, thereby causing the level of the first shift node GN1 to become low. As a result, the second shift transistor GT2 and the fifth shift transistor GT5 are turned on. Because the eighth shift transistor GT8 is always turned on in response to the fourth voltage signal (continuously low) provided by the fourth power line VGL, the level of the third shift node GN3 can be the same as the level of the first shift node GN1, that is, at a low level. At the same time, this low level is stored in the second capacitor GC2. In addition, the turned-on third shift transistor GT3 transmits the low-level second voltage to the second shift node GN2, and the turned-on second shift transistor GT2 transmits the low-level first clock signal to the second shift node GN2, thereby changing the level of the second shift node GN2 to a low level and storing it in the first capacitor GC1. Therefore, the fourth shift transistor GT4 is turned on in response to the low level of the second shift node GN2, and outputs the high-level third voltage signal provided by the third power line VGH to the shift output terminal GOUT. At the same time, the fifth shift transistor GT5 is turned on in response to the low level of the third shift node GN3, and transmits the high-level second clock signal provided by the second clock signal line GCB to the shift output terminal GOUT. Therefore, at this stage, the driving unit outputs a high-level signal.

[0155] In the second phase S22, the second clock signal line GCB provides a low-level second clock signal, turning on the seventh shift transistor GT7. The first clock signal line GCK provides a high-level first clock signal, turning off the first shift transistor GT1 and the third shift transistor GT3. Due to the storage function of the second capacitor GC2, the first shift node GN1 can continue to maintain the low level from the previous phase, turning on the second shift transistor GT2 and the fifth shift transistor GT5. Since the second shift transistor GT2 is turned on, the high-level first clock signal from the first clock signal line GCK is transmitted to the second shift node GN2, causing the second shift node GN2 to reach a high level. Consequently, the sixth shift transistor GT6 and the fourth shift transistor GT4 are turned off, preventing the high-level signal from the third power supply line VGH from being output to the shift output terminal GOUT and the first shift node GN1. Simultaneously, since the fifth shift transistor GT5 is turned on, during this phase, the shift output terminal GOUT outputs the low-level signal transmitted by the second clock signal line GGB.

[0156] In the third phase S23, the first clock signal line GCK provides a low-level third clock signal, turning on the first and third shift transistors GT1 and GT3. At this time, the high-level signal provided by the scan initial signal line GSTV is transmitted from the shift input terminal GIN to the first and third shift nodes GN1 and GN3, turning off the fifth and second shift transistors GT5 and GT2. The second clock signal line GCB receives a high-level second clock signal, turning off the seventh shift transistor GT7. Since the third shift transistor GT3 is turned on, the low-level signal provided by the fourth power line VGL is transmitted to the second shift node GN2 and stored in the first capacitor GC1. Consequently, the fourth and sixth shift transistors GT4 and GT6 are turned on. During this phase, the shift output terminal GOUT outputs the high-level signal provided by the third power line VGH.

[0157] In the fourth phase S24, the first clock signal line GCK provides a high-level first clock signal, turning off the first shift transistor GT1 and the third shift transistor GT3. The second clock signal line GCB provides a low-level second clock signal, turning on the seventh shift transistor GT7. Due to the storage function of the second capacitor GC2, the voltage level at the first shift node GN1 remains high, as in the previous phase. This turns off the second shift transistor GT2 and the fifth shift transistor GT5. During this phase, the shift output terminal GOUT outputs the high-level signal provided by the third power supply line VGH. Due to the storage function of the first capacitor GC1, the second shift node GN2 continues to maintain the low-level voltage level from the previous phase, turning on the sixth shift transistor GT6. The high voltage level provided by the third power supply line VGH is transmitted to the first shift node GN1 and the third shift node GN3 via the turned-on sixth shift transistor GT6 and seventh shift transistor GT7. This keeps the first shift node GN1 and the third shift node GN3 high, effectively preventing the fifth shift transistor GT5 from turning on and thus avoiding erroneous output.

[0158] In some examples, the driving unit may subsequently repeatedly perform the third stage S23 and the fourth stage S24 until the shift input terminal GIN receives a low-level signal again.

[0159] Figure 7 is an equivalent circuit diagram of an electrostatic discharge circuit according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 7, at least one electrostatic discharge circuit is connected to a signal line SL and is configured to discharge static electricity from the connected signal line SL. The electrostatic discharge circuit can prevent static electricity accumulation in the signal line from causing damage due to discharge breakdown, thereby dissipating accumulated static electricity in the signal line and protecting the signal line.

[0160] In some examples, as shown in FIG7 , the electrostatic discharge circuit may include: first to fourth release transistors ST1 to ST4 . The control electrode and first electrode of the first release transistor ST1 are electrically connected to the third power line VGH, the second electrode of the first release transistor ST1 is electrically connected to the control electrode and first electrode of the second release transistor ST2, the second electrode of the second release transistor ST2 is electrically connected to the signal line SL corresponding to the electrostatic discharge circuit, the control electrode and first electrode of the third release transistor ST3 are electrically connected to the signal line SL corresponding to the electrostatic discharge circuit, the second electrode of the third release transistor ST3 is electrically connected to the control electrode and first electrode of the fourth release transistor ST4, and the second electrode of the fourth release transistor ST4 is electrically connected to the fourth power line VGL.

[0161] In another example, the electrostatic discharge circuit can include two discharge transistors, each with one electrode connected to its own gate, forming an equivalent diode connection. The signal line to be protected is connected between the two "diodes," and the other two ends of the two "diodes" are connected to the third power line VGH and the fourth power line VGL, respectively. Thus, when a transient high voltage (e.g., 100V) appears in the signal line due to accumulated positive charge, one of the "diodes" conducts, releasing the positive charge in the signal line. When a transient low voltage (e.g., -100V) appears in the signal line due to accumulated negative charge, the other "diode" conducts, releasing the negative charge in the signal line.

[0162] In some examples, in a direction perpendicular to the display substrate, the peripheral region may include at least: a first routing layer, a second routing layer, a third routing layer, and a fourth routing layer sequentially disposed on the substrate, with at least one insulating layer disposed between adjacent routing layers.

[0163] Figure 8 is a schematic diagram of the partial structure of region C2 in Figure 4A. Figure 8 is a schematic plan view of region C2 after the fourth routing layer is formed. Figure 9A is a schematic plan view of region C2 in Figure 8 after the third routing layer is formed. Figure 9B is a schematic plan view of region C2 in Figure 8 after the second routing layer is formed. Figure 9C is a schematic plan view of region C2 in Figure 8 after the first routing layer is formed.

[0164] In some examples, as shown in Figure 8, the first border area may include multiple drive control lines, and the multiple drive control lines may include: a first drive output line GOUT, a first control line NCX, a first start signal line GSTV, a first clock signal line GCK, a second clock signal line GCB, a second drive output line NOUT, a second start signal line NSTV, a third clock signal line NCK, a fourth clock signal line NCB, a third start signal line PSTV, a fifth clock signal line PCK, a sixth clock signal line PCB, a third drive output line POUT, a third power supply line S_VGH, a fourth power supply line S_VGL, a fifth power supply line S_VGH_N, and a sixth power supply line S_VHL_N.

[0165] In some examples, the first drive output line GOUT, the first control line NCX, the first start signal line GSTV, the first clock signal line GCK, the second clock signal line GCB, the third power supply line S_VGH, and the fourth power supply line S_VGL can be electrically connected to the first scan gate driver circuit. The second drive output line NOUT, the second start signal line NSTV, the third clock signal line NCK, the fourth clock signal line NCB, the fifth power supply line S_VGH_N, and the sixth power supply line S_VHL_N can be electrically connected to the second scan gate driver circuit. The third start signal line PSTV, the fifth clock signal line PCK, the sixth clock signal line PCB, the third drive output line POUT, the third power supply line S_VGH, and the fourth power supply line S_VGL can be electrically connected to the first reset gate driver circuit.

[0166] In some examples, the electrostatic discharge circuit to which the plurality of driving control lines are connected may be located between the third clock signal line NCK and the fourth clock signal line NCB in the second direction Y.

[0167] In some examples, the first driver output line GOUT, the second driver output line NOUT, and the third driver output line POUT can be single-layer routing lines, for example, located in the first routing layer. The first control line NCX, the first start signal line GSTV, the first clock signal line GCK, the second clock signal line GCB, the second start signal line NSTV, the third clock signal line NCK, the fourth clock signal line NCB, the third start signal line PSTV, the fifth clock signal line PCK, the sixth clock signal line PCB, the third power supply line S_VGH, the fourth power supply line S_VGL, the fifth power supply line S_VGH_N, and the sixth power supply line S_VHL_N can all be double-layer routing lines. Each double-layer routing line can include: a first sub-routing located in the first routing layer and a second sub-routing located in the second routing layer. The orthographic projection of the first sub-routing on the substrate can at least partially overlap with the orthographic projection of the second sub-routing on the substrate. For example, the orthographic projection of the first sub-routing on the substrate can cover the orthographic projection of the second sub-routing on the substrate.

[0168] In some examples, as shown in FIG8 , the first initial power supply line INIT1a, the second initial power supply line INIT2a, and the third initial power supply line INIT3a can be located between the fifth power supply line S_VGH_N and the fourth power supply line S_VGL. The first initial power supply line INIT1a, the second initial power supply line INIT2a, and the third initial power supply line INIT3a can be arranged sequentially in a direction approaching the display area. The first initial power supply line INIT1a, the second initial power supply line INIT2a, and the third initial power supply line INIT3a can all be double-layered. As shown in Figures 9B and 9C, the first initial power supply line INIT1a may include a first sub-route INIT1a-1 located in the first routing layer and a second sub-route INIT1a-2 located in the second routing layer; the second initial power supply line INIT2a may include a first sub-route INIT2a-1 located in the first routing layer and a second sub-route INIT2a-2 located in the second routing layer; the third initial power supply line INIT3a may include a first sub-route INIT3a-1 located in the first routing layer and a second sub-route INIT3a-2 located in the second routing layer.

[0169] In some examples, the fourth initial power supply line INIT1b, the fifth initial power supply line INIT2b, and the sixth initial power supply line INIT3b can be located on a side of the first drive output line GOUT close to the second direction Y, for example, on a side close to the display area. The fourth initial power supply line INIT1b, the fifth initial power supply line INIT2b, and the sixth initial power supply line INIT3b can be arranged sequentially along a direction close to the display area. The fourth initial power supply line INIT1b, the fifth initial power supply line INIT2b, and the sixth initial power supply line INIT3b can be arranged on the same layer, for example, all located on the fourth routing layer.

[0170] In some examples, as shown in FIG8 , the first adapter line 11 may include: a first sub-connection line 111 extending at least along the first direction X and a second sub-connection line 112 extending at least along the second direction Y, wherein the first sub-connection line 111 and the second sub-connection line 112 are connected. The first sub-connection line 111 may be in the shape of a zigzag extending along the first direction X, and the second sub-connection line 112 may be in the shape of a zigzag extending along the second direction Y. The first sub-connection line 111 may be located in a third routing layer, and the second sub-connection line 112 may be located in a fourth routing layer. One end of the second sub-connection line 112 may be connected to the first sub-connection line 111, and the other end may be connected to the first sub-routing INIT1a-1 and the second sub-routing INIT1a-2 of the first initial power supply line INIT1a via a first connection electrode 113 located in the third routing layer. The second sub-connection line 112 and the fourth initial power supply line INIT1b may be an integrated structure connected to each other.

[0171] In some examples, as shown in FIG8 , the second sub-connection line 112 may include a first line segment 1121 extending along a third direction F3, a second line segment 1122 extending along a second direction Y, a third line segment 1123 extending along a fourth direction F4, and a fourth line segment 1124 extending along the second direction Y. The third direction F3 may intersect both the first direction X and the second direction Y, and the fourth direction F4 may intersect both the first direction X and the second direction Y. The third direction F3 and the fourth direction F4 may intersect; for example, the third direction F3 may be perpendicular to the fourth direction F4. The first line segment 1121, the second line segment 1122, the third line segment 1123, and the fourth line segment 1124 may be connected in sequence. The first line segment 1121 and the fourth initial power supply line INIT1B may be an integrally connected structure. The end of the first line segment 1121 may be connected to the first sub-connection line 111. The end of the fourth line segment 1124 may be connected to the first initial power supply line INIT1a via the first connection electrode 113. In this example, the first line segment 1121 , the second line segment 1122 , the third line segment 1123 and the fourth line segment 1124 may be sequentially connected to form a second sub-connection line 112 that extends substantially along the second direction Y and is in a broken line shape.

[0172] In some examples, as shown in FIG8 , the first patch cable 12 may include: a first sub-connection cable 121 extending at least along a first direction X and a second sub-connection cable 122 extending at least along a second direction Y, wherein the first sub-connection cable 121 and the second sub-connection cable 122 are connected. The first sub-connection cable 121 may be in the shape of a zigzag extending along the first direction X and may be located on a side of the first sub-connection cable 111 opposite to the second direction Y. The second sub-connection cable 122 may be in the shape of a zigzag extending along the second direction Y and may be located on a side of the second sub-connection cable 112 in the first direction X. The first sub-connection cable 121 may be located on a fourth routing layer, and the second sub-connection cable 122 may be located on a fourth routing layer. One end of the second sub-connection line 122 can be connected to the first sub-connection line 121 located on the fourth routing layer via a fourth connection electrode 124 located on the third routing layer, and the other end can be connected to the first sub-routing INIT2a-1 located on the first routing layer and the second sub-routing INIT2a-2 located on the second routing layer of the second initial power supply line INIT2a via a second connection electrode 123 located on the third routing layer. The second sub-connection line 122 and the fifth initial power supply line INIT2b can be an integrated structure connected to each other. The shape of the second sub-connection line 122 can refer to the description of the second sub-connection line 112, so it will not be repeated here.

[0173] In some examples, as shown in FIG8 , the first patch cable 13 may include: a first sub-connection line 131 extending at least along the first direction X and a second sub-connection line 132 extending at least along the second direction Y, wherein the first sub-connection line 131 and the second sub-connection line 132 are connected. The first sub-connection line 131 may be in the shape of a zigzag extending along the first direction X and may be located on one side of the first sub-connection line 111 in the second direction Y. The second sub-connection line 132 may be in the shape of a zigzag extending along the second direction Y and may be located on one side of the second sub-connection line 122 in the first direction X. The first sub-connection line 131 may be located on a fourth routing layer, and the second sub-connection line 132 may be located on a fourth routing layer. The first sub-connection line 131 and the second sub-connection line 132 may be an integral structure connected to each other. The second sub-connection line 132 can be connected to the first sub-route INIT3a-1 located on the first routing layer and the second sub-route INIT3a-2 located on the second routing layer of the third initial power supply line INIT3a via a third connection electrode 133 located on the third routing layer. The second sub-connection line 132 and the sixth initial power supply line INIT3b can be an integrated structure connected to each other. The shape of the second sub-connection line 132 can be referred to the description of the second sub-connection line 112, and therefore will not be repeated here.

[0174] In some examples, as shown in FIG8 , the first drive connection line 151, the second drive connection line 152, and the third drive connection line 153 connected to the pixel circuits of the Mth row of sub-pixels can be located on the side of the first sub-connection line 131 of the first adapter line 13 that is closer to the display area. For example, the first drive connection line 151 can be located on the fourth routing layer, and the second drive connection line 152 and the third drive connection line 153 can be located on the third routing layer. In this example, multiple routing lines in the first corner area can be arranged on the third and fourth routing layers, and adjacent routing lines can be located on different film layers to increase routing space.

[0175] In some examples, in a direction perpendicular to the display substrate, the display substrate may include: a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer, a fourth conductive layer, a fifth conductive layer, and a sixth conductive layer disposed on a substrate. A first insulating layer may be disposed between the first semiconductor layer and the first conductive layer, a second insulating layer may be disposed between the first conductive layer and the second conductive layer, a third insulating layer may be disposed between the second conductive layer and the second semiconductor layer, a fourth insulating layer may be disposed between the second semiconductor layer and the third conductive layer, a fifth insulating layer may be disposed between the third conductive layer and the fourth conductive layer, a sixth insulating layer and a seventh insulating layer may be disposed between the fourth conductive layer and the fifth conductive layer, and an eighth insulating layer may be disposed between the fifth conductive layer and the sixth conductive layer. In some examples, the first to sixth insulating layers may be inorganic insulating layers, and the seventh and eighth insulating layers may be organic insulating layers. However, this embodiment is not limited to this.

[0176] In some examples, the first routing layer in the peripheral region may be located in the first conductive layer, the second routing layer may be located in the second conductive layer, the third routing layer may be located in the fourth conductive layer, and the fourth routing layer may be located in the fifth conductive layer.

[0177] The following is an example of the film structure of the display substrate of this example through the preparation process of the display substrate. The "patterning process" mentioned in this disclosure includes processes such as coating photoresist, mask exposure, development, etching, and stripping photoresist for metal materials, inorganic materials or transparent conductive materials, and includes processes such as coating organic materials, mask exposure and development for organic materials. Deposition can be carried out by any one or more of sputtering, evaporation, and chemical vapor deposition, coating can be carried out by any one or more of spraying, spin coating and inkjet printing, and etching can be carried out by any one or more of dry etching and wet etching, which are not limited in this disclosure. "Thin film" refers to a thin film made by deposition, coating or other processes on a substrate of a certain material. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern".

[0178] The terms "A and B are arranged in the same layer" and "A and B are in the same layer structure" mentioned in the present disclosure mean that A and B are formed simultaneously through the same patterning process, or the surfaces of A and B close to the substrate are at substantially the same distance from the substrate, or the surfaces of A and B close to the substrate are in direct contact with the same film layer. The "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of the present disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A includes the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B. The "shape of A" mentioned in the present disclosure refers to the shape of the orthographic projection of A on the substrate.

[0179] In some examples, the manufacturing process of the display substrate may include the following operations: In the following example, the film layers of the partial structure of four rows of pixel circuits in region C1 and four driving units of the first scanning gate driving circuit are used as an example.

[0180] (1) Provide a substrate. In some examples, the substrate can be a rigid substrate or a flexible substrate. For example, the rigid substrate can be, but is not limited to, one or more of glass and quartz, and the flexible substrate can be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fiber. In some examples, the flexible substrate can include a first flexible material layer, a first inorganic material layer, a second flexible material layer, and a second inorganic material layer stacked together. The materials of the first flexible material layer and the second flexible material layer can be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film. The materials of the first inorganic material layer and the second inorganic material layer can be silicon nitride (SiNy, y>0) or silicon oxide (SiOx, x>0), etc., to improve the substrate's resistance to water and oxygen.

[0181] (2) Forming a first semiconductor layer. In some examples, a first semiconductor thin film is deposited on a substrate, and the first semiconductor thin film is patterned by a patterning process to form a first semiconductor layer disposed on the substrate. In some examples, the first semiconductor layer can be made of amorphous silicon (a-Si), polycrystalline silicon (p-Si), sexithiophene, or polythiophene.

[0182] Figure 10A is a partial schematic diagram of region C1 after the first semiconductor layer is formed. Figure 10B is a partial schematic diagram of the display region after the first semiconductor layer is formed. Figure 10C is a partial schematic diagram of the first corner region after the first semiconductor layer is formed. Figure 10B illustrates the first semiconductor layers of three pixel circuits of a row of sub-pixels (the Mth row of sub-pixels in Figure 4A) closest to the first border region in region C1. Figure 10C illustrates the first semiconductor layers of four cascaded drive units (e.g., the M-3th to Mth stage drive units) of the first scan gate drive circuit located in the first corner region in region C1.

[0183] In some examples, as shown in Figures 10A and 10B, the first semiconductor layer of the display area AA may include at least: an active layer of multiple first-type transistors of the pixel circuit (for example, including an active layer PT10 of the first pixel transistor PT1, an active layer PT30 of the third pixel transistor PT3, an active layer PT40 of the fourth pixel transistor PT4, an active layer PT50 of the fifth pixel transistor PT5, an active layer PT60 of the sixth pixel transistor PT6, an active layer PT70 of the seventh pixel transistor PT7, and an active layer PT80 of the eighth pixel transistor PT8).

[0184] In some examples, the active layer of each transistor may include: a first region, a second region, and a channel region located between the first region and the second region. The material of the first semiconductor layer may include, for example, polysilicon. The channel region may not be doped with impurities and have semiconductor properties. The first region and the second region may be doped regions on both sides of the channel region, and are doped with impurities and therefore have conductivity. The impurities may vary depending on the type of transistor. In some examples, the doped region of the active layer may be interpreted as a source electrode or a drain electrode of the transistor. The portion of the active layer between the transistors may be interpreted as wiring doped with impurities, which can be used to electrically connect the transistors. This embodiment is not limited to this.

[0185] In some examples, as shown in FIG10B , the active layer PT10 of the first pixel transistor and the active layer PT40 of the fourth pixel transistor may be located on one side of the active layer PT30 of the third pixel transistor in the second direction Y, and the active layer PT50 of the fifth pixel transistor, the active layer PT60 of the sixth pixel transistor, the active layer PT70 of the seventh pixel transistor, and the active layer PT80 of the eighth pixel transistor may be located on a side of the active layer PT30 of the third pixel transistor in the opposite direction of the second direction Y. The active layer PT80 of the eighth pixel transistor may be located on a side of the active layer PT70 of the seventh pixel transistor in the opposite direction of the first direction X.

[0186] In some examples, the active layer PT30 of the third pixel transistor, the active layer PT40 of the fourth pixel transistor, the active layer PT50 of the fifth pixel transistor, the active layer PT60 of the sixth pixel transistor, and the active layer PT70 of the seventh pixel transistor of a single pixel circuit can be an interconnected integral structure. The first area of ​​the active layer PT30 of the third pixel transistor can simultaneously serve as the second area of ​​the active layer PT40 of the fourth pixel transistor and the second area of ​​the active layer PT50 of the fifth pixel transistor, and the second area of ​​the active layer PT30 of the third pixel transistor can simultaneously serve as the first area of ​​the active layer PT60 of the sixth pixel transistor. The second area of ​​the active layer PT60 of the sixth pixel transistor can simultaneously serve as the second area of ​​the active layer PT70 of the seventh pixel transistor. The first area of ​​the active layer PT40 of the fourth pixel transistor, the first area of ​​the active layer PT50 of the fifth pixel transistor, and the first area of ​​the seventh pixel transistor PT70 can be independently provided.

[0187] In some examples, the active layer PT30 of the third pixel transistor may be approximately U-shaped, the active layer PT40 of the fourth pixel transistor and the active layer PT50 of the fifth pixel transistor may be approximately I-shaped, and the active layer PT60 of the sixth pixel transistor, the active layer PT70 of the seventh pixel transistor, the active layer PT10 of the first pixel transistor, and the active layer PT80 of the eighth pixel transistor may be approximately L-shaped. This embodiment is not limited to this.

[0188] In some examples, a row of pixel circuits may include at least one pixel circuit group, each pixel circuit group may include two pixel circuits symmetrically arranged about a midline of the pixel circuit group in the first direction X. For example, the active layer PT30 of the third pixel transistor, the active layer PT40 of the fourth pixel transistor, the active layer PT50 of the fifth pixel transistor, the active layer PT60 of the sixth pixel transistor, and the active layer PT70 of the seventh pixel transistor of two pixel circuits in a pixel circuit group may be an interconnected integral structure.

[0189] In some examples, as shown in Figures 10A and 10C, the first semiconductor layer of the first corner area B4a may include at least: active layers of multiple transistors of the driving unit of the first scan gate driving circuit (for example, including the active layer GT10 of the first shift transistor, the active layer GT20 of the second shift transistor, the active layer GT30 of the third shift transistor, the active layer GT40 of the fourth shift transistor, the active layer GT50 of the fifth shift transistor, the active layer GT60 of the sixth shift transistor, the active layer GT70 of the seventh shift transistor, and the active layer GT80 of the eighth shift transistor).

[0190] In some examples, as shown in FIG10C , the active layer GT40 of the fourth shift transistor and the active layer GT50 of the fifth shift transistor of a single drive unit can be interconnected as an integrated structure. The second region of the active layer GT40 of the fourth shift transistor can also serve as the second region of the active layer GT50 of the fifth shift transistor. The active layers GT60 of the sixth shift transistor, GT70 of the seventh shift transistor, and GT80 of the eighth shift transistor of a single drive unit can be interconnected as an integrated structure, and the integrated structure can be located on one side of the active layer GT40 of the fourth shift transistor and the active layer GT50 of the fifth shift transistor in the opposite direction of the first direction X. The second region of the active layer GT60 of the sixth shift transistor can also serve as the first region of the active layer GT70 of the seventh shift transistor, and the second region of the active layer GT70 of the seventh shift transistor can also serve as the first region of the active layer GT80 of the eighth shift transistor.

[0191] In some examples, as shown in FIG10C , the active layer GT10 of the first shift transistor may be located on a side of the active layer GT60 of the sixth shift transistor in the opposite direction to the first direction X. The active layer GT10 of the first shift transistor may be substantially U-shaped. The active layer GT20 of the second shift transistor and the active layer GT30 of the third shift transistor may be located on a side of the active layer GT10 of the first shift transistor in the opposite direction to the first direction X.

[0192] In some examples, as shown in FIG10A , the first semiconductor layer of the first border region B1 may include at least active layers of multiple release transistors of multiple electrostatic discharge circuits. For example, the multiple electrostatic discharge circuits may be arranged in two rows. Each row may include multiple electrostatic discharge circuits, and the active layers of the multiple release transistors of the multiple electrostatic discharge circuits in a row may be interconnected and integrated.

[0193] (3) Forming a first conductive layer. In some examples, a first insulating film and a first conductive film are sequentially deposited on the substrate forming the aforementioned structure, and the first conductive film is patterned by a patterning process to form a first insulating layer and a first conductive layer disposed on the first insulating layer. In some examples, the first conductive layer may also be referred to as a first gate metal layer, and the first insulating layer may also be referred to as a first gate insulating layer.

[0194] Figure 11A is a partial schematic diagram of the first conductive layer in region C1. Figure 11B is a partial schematic diagram of the display region after the first conductive layer is formed. Figure 11C is a partial schematic diagram of the first corner region after the first conductive layer is formed. Figure 11B illustrates three pixel circuits in a row of sub-pixels closest to the first border region after the first conductive layer is formed. Figure 11C illustrates four cascaded drive units of the first scan gate drive circuit after the first conductive layer is formed.

[0195] In some examples, as shown in Figures 11A and 11B, the first conductive layer of the display area AA may include at least: a first electrode of the storage capacitor of the pixel circuit (for example, the first electrode Cst-1), multiple first scan lines (for example, including the first scan line GL1(m)), multiple first reset control lines (for example, including the first reset control line RST1(m)), multiple second reset control lines (for example, including the second reset control line RST2(m), RST2(m-1)), and multiple light-emitting control lines (for example, including the light-emitting control lines EML(m), EML(m-1)).

[0196] In some examples, as shown in FIG11B , the overlapping area between the first electrode Cst-1 of the storage capacitor and the active layer PT30 of the third pixel transistor PT3 can serve as the gate of the third pixel transistor PT3. The overlapping area between the first scan line GL1(m) and the active layer PT40 of the fourth pixel transistor PT4 of the pixel circuit can serve as the gate of the fourth pixel transistor PT4. The overlapping area between the first reset control line RST1(m) and the active layer PT10 of the first pixel transistor PT1 of the pixel circuit can serve as the gate of the first pixel transistor PT1. The overlapping area between the second reset control line RST2(m) and the active layer PT70 of the seventh pixel transistor PT7 of the pixel circuit can serve as the gate of the seventh pixel transistor PT7, and the overlapping area between the second reset control line RST2(m) and the active layer PT80 of the eighth pixel transistor PT8 can serve as the gate of the eighth pixel transistor PT8. The overlapping area of ​​the light-emitting control line EML(m) and the active layer PT50 of the fifth pixel transistor PT5 of the pixel circuit can serve as the gate of the fifth pixel transistor PT5, and the overlapping area with the active layer PT60 of the sixth pixel transistor PT6 can serve as the gate of the sixth pixel transistor PT6.

[0197] In some examples, as shown in Figures 11A and 11C, the first conductive layer of the first corner area B4a may include at least: the gates of multiple transistors of the driving unit of the first scan gate driving circuit, the first electrode GC1-1 of the first capacitor and the first electrode GC2-1 of the second capacitor, the first output connection electrode 401 and the second output connection electrode 402.

[0198] In some examples, as shown in FIG11C , the gate of the first shift transistor GT1 and the gate of the third shift transistor GT3 may be connected to each other as an integral structure. The gate of the sixth shift transistor GT6, the gate of the fourth shift transistor GT4, and the first electrode GC1-1 of the first capacitor may be connected to each other as an integral structure. The gate of the fifth shift transistor GT5 and the first electrode GC2-1 of the second capacitor may be connected to each other as an integral structure.

[0199] In some examples, as shown in FIG11C , the first output connection electrode 401 can be roughly T-shaped, and the second output connection electrode 402 can be roughly L-shaped. At least a portion of the first output connection electrode 401 and at least a portion of the second output connection electrode 402 can be located on one side of the gate of the fourth shift transistor GT4 and the fifth shift transistor GT5 in the first direction X. At least a portion of the first output connection electrode 401 and at least a portion of the second output connection electrode 402 can be arranged at intervals between the drive units. For example, the first output connection electrode 401 can be extended between the M-th and M-1-th drive units, the second output connection electrode 402 can be extended between the M-1-th and M-2-th drive units, and the first output connection electrode 401 can be extended between the M-2-th and M-3-th drive units.

[0200] In some examples, as shown in FIG11A , the first conductive layer of the first border area B1 may include at least: a first sub-route INIT1a-1 of a first initial power supply line, a first sub-route INIT2a-1 of a second initial power supply line, a first sub-route INIT3a-1 of a third initial power supply line, first sub-routes of a plurality of drive control lines, and gates of release transistors of a plurality of electrostatic discharge circuits. The first sub-route INIT1a-1 of the first initial power supply line, the first sub-route INIT2a-1 of the second initial power supply line, and the first sub-route INIT3a-1 of the third initial power supply line may be arranged adjacent to each other in a direction approaching the display area AA, and the first sub-route INIT1a-1 of the first initial power supply line, the first sub-route INIT2a-1 of the second initial power supply line, and the first sub-route INIT3a-1 of the third initial power supply line may be located between the first sub-routes of the plurality of drive control lines.

[0201] (4) Forming a second conductive layer. In some examples, a second insulating film and a second conductive film are sequentially deposited on the substrate forming the aforementioned structure. The second conductive film is patterned by a patterning process to form a second insulating layer and a second conductive layer disposed on the second insulating layer. In some examples, the second conductive layer may also be referred to as a second gate metal layer, and the second insulating layer may also be referred to as a second gate insulating layer.

[0202] Figure 12A is a partial schematic diagram of the second conductive layer in region C1. Figure 12B is a partial schematic diagram of the display region after the second conductive layer is formed. Figure 12C is a partial schematic diagram of the first corner region after the second conductive layer is formed. Figure 12B illustrates three pixel circuits in a row of sub-pixels closest to the first border region after the second conductive layer is formed. Figure 12C illustrates four cascaded drive units of the first scan gate drive circuit after the second conductive layer is formed.

[0203] In some examples, as shown in Figures 12A and 12B, the second conductive layer of the display area AA may include at least: a second electrode of the storage capacitor of the pixel circuit (e.g., a second electrode Cst-2), and a plurality of second auxiliary scan lines (e.g., including a second auxiliary scan line GL2a(m)). The second electrodes Cst-2 of adjacent pixel circuits within a row of pixel circuits may be interconnected as an integrated structure to achieve transmission of the first voltage signal along the first direction X. The orthographic projection of the second auxiliary scan line GL2a(m) on the substrate may be located between the orthographic projection of the first reset control line RST1(m) and the first scan line GL1(m) on the substrate.

[0204] In some examples, as shown in Figures 12A and 12C, the second conductive layer of the first corner region B4a may include at least: the second electrode GC1-2 of the first capacitor and the second electrode GC2-2 of the second capacitor of the driving unit of the first scan gate driving circuit, the third output connection electrode 403, and the first shift connection electrode 411. The third output connection electrode 403 may be aligned with the portion of the first output connection electrode 401 that is inserted between the two driving units.

[0205] In some examples, as shown in FIG12A , the second conductive layer of the first border area B1 may include at least: a second sub-route INIT1a-2 of the first initial power supply line, a second sub-route INIT2a-2 of the second initial power supply line, a third sub-route INIT3a-2 of the third initial power supply line, and second sub-routes of multiple drive control lines. The second sub-route INIT1a-2 of the first initial power supply line, the second sub-route INIT2a-2 of the second initial power supply line, and the third sub-route INIT3a-2 of the third initial power supply line may be arranged adjacent to each other in sequence along a direction approaching the display area AA, and the second sub-route INIT1a-2 of the first initial power supply line, the second sub-route INIT2a-2 of the second initial power supply line, and the third sub-route INIT3a-2 of the third initial power supply line may be located between the second sub-routes of the multiple drive control lines.

[0206] (5) Forming a second semiconductor layer. In some examples, a third insulating film and a second semiconductor film are sequentially deposited on the substrate having the aforementioned pattern formed thereon. The second semiconductor film is patterned by a patterning process to form a third insulating layer and a second semiconductor layer disposed on the third insulating layer. In some examples, the material of the second semiconductor layer may include indium gallium zinc oxide (IGZO). In some examples, the third insulating layer may also be referred to as a third gate insulating layer.

[0207] Figure 13A is a partial schematic diagram of the second semiconductor layer in region C1. Figure 13B is a partial schematic diagram of the display region after the second semiconductor layer is formed. Figure 13B illustrates three pixel circuits in a row of sub-pixels closest to the first border region after the second semiconductor layer is formed.

[0208] In some examples, as shown in Figures 13A and 13B, the second semiconductor layer of the display area AA may include at least: an active layer of the second type transistor of the pixel circuit (for example, including the active layer PT20 of the second pixel transistor). The orthographic projection of the active layer PT20 of the second pixel transistor on the substrate may be located on one side of the orthographic projection of the active layer PT30 of the third pixel transistor on the substrate in the second direction Y. The shape of the active layer PT20 of the second pixel transistor may be approximately L-shaped. The second semiconductor layer pattern of a pixel circuit group may be approximately symmetrical about the midline of the pixel circuit group in the first direction X.

[0209] (6) Forming a third conductive layer. In some examples, a fourth insulating film and a third conductive film are sequentially deposited on the substrate on which the aforementioned pattern is formed. The third conductive film is patterned by a patterning process to form a fourth insulating layer and a third conductive layer disposed on the fourth insulating layer. In some examples, the third conductive layer may also be referred to as a third gate metal layer, and the fourth insulating layer may also be referred to as a fourth gate insulating layer.

[0210] Figure 14A is a partial schematic diagram of the third conductive layer in region C1. Figure 14B is a partial schematic diagram of the display region after the third conductive layer is formed. Figure 14C is a partial schematic diagram of the first corner region after the third conductive layer is formed. Figure 14B illustrates three pixel circuits in a row of sub-pixels closest to the first border region after the first conductive layer is formed. Figure 14C illustrates four cascaded drive units of the first scan gate drive circuit after the first conductive layer is formed.

[0211] In some examples, as shown in Figures 14A and 14B, the third conductive layer of the display area AA may include at least: multiple second scan lines (for example, including the second scan line GL2(m)), multiple first initial signal lines (for example, including the first initial signal line INIT1(m), INIT1(m-1)), multiple second initial signal lines (for example, including the second initial signal line INIT2(m), INIT2(m-1)), and multiple third initial signal lines (for example, including the third initial signal line INIT3(m)).

[0212] In some examples, as shown in FIG14B , the overlapping region between the second scan line GL2(m) and the active layer PT20 of the second pixel transistor can serve as the gate of the second pixel transistor PT2. The overlapping region between the second auxiliary scan line GL2a(m) and the active layer PT20 of the second pixel transistor can serve as the bottom gate of the second pixel transistor PT2. The second scan line GL2(m) and the second auxiliary scan line GL2a(m) can transmit the same second scan signal.

[0213] In some examples, as shown in FIG14B , the first initial signal line INIT1(m), the second initial signal line INIT2(m), and the third initial signal line INIT3(m) may be located on a side of the storage capacitor of the pixel circuit in the Mth row opposite to the second direction Y. The first initial signal line INIT1(m) may be located between the second initial signal line INIT2(m) and the third initial signal line INIT3(m). The third initial signal line INIT3(m) may be located on a side of the first initial signal line INIT1(m) in the second direction Y, and the second initial signal line INIT2(m) may be located on a side of the first initial signal line INIT1(m) opposite to the second direction Y.

[0214] 14A and 14C , the third conductive layer of the first corner region B4a may include at least a fourth output connection electrode 404. The fourth output connection electrode 404 may be aligned with a portion of the second output connection electrode 402 inserted between the two driving units.

[0215] (7) Forming a fifth insulating layer. In some examples, a fifth insulating film is deposited on the substrate having the aforementioned pattern, and the fifth insulating film is patterned by a patterning process to form a fifth insulating layer. In some examples, the fifth insulating layer may also be referred to as an interlayer insulating layer. The fifth insulating layer may have a plurality of vias.

[0216] Figure 15A is a partial schematic diagram of the display area after the fifth insulating layer is formed. Figure 15B is a partial schematic diagram of the first corner area after the fifth insulating layer is formed.

[0217] In some examples, as shown in Figure 15A, the multiple vias opened in the fifth insulating layer of the display area may include: the first via V1 to the tenth via V10, the eleventh via V11 to the fifteenth via V15, the sixteenth via V16 to the seventeenth via V17, the twenty-first via V21 to the twenty-second via V22, and the twenty-third via V23 to the thirtieth via V30.

[0218] In some examples, the fifth insulating layer, the fourth insulating layer, the third insulating layer, the second insulating layer, and the first insulating layer in the first via hole V1 to the tenth via hole V10 can be removed to expose a portion of the surface of the first semiconductor layer. The fifth insulating layer, the fourth insulating layer, the third insulating layer, and the second insulating layer in the eleventh via hole V11 to the fifteenth via hole V15 can be removed to expose a portion of the surface of the first conductive layer. The fifth insulating layer, the fourth insulating layer, and the third insulating layer in the sixteenth via hole V16 to the seventeenth via hole V17 can be removed to expose a portion of the surface of the second conductive layer. The fifth insulating layer and the fourth insulating layer in the twenty-first via hole V21 and the twenty-second via hole V22 can be removed to expose a portion of the surface of the second semiconductor layer. The fifth insulating layer in the twenty-third via hole V23 to the thirtieth via hole V30 can be removed to expose a portion of the surface of the third conductive layer.

[0219] In some examples, as shown in Figure 15B, the multiple vias opened in the fifth insulation layer of the first corner area may include: the fifty-first via V51 to the sixty-second via V62, the sixty-third via V63 to the seventy-fifth via V75, the seventy-sixth via V76 to the eighty-first via V81, and the eighty-second via V82 to the eighty-third via V83.

[0220] In some examples, the fifth insulating layer, the fourth insulating layer, the third insulating layer, the second insulating layer, and the first insulating layer in the fifty-first via hole V51 to the sixty-second via hole V62 can be removed to expose a portion of the surface of the first semiconductor layer. The fifth insulating layer, the fourth insulating layer, the third insulating layer, and the second insulating layer in the sixty-third via hole V63 to the seventy-fifth via hole V75 can be removed to expose a portion of the surface of the first conductive layer. The fifth insulating layer, the fourth insulating layer, and the third insulating layer in the seventy-sixth via hole V76 to the eighty-first via hole V81 can be removed to expose a portion of the surface of the second conductive layer. The fifth insulating layer in the eighty-second via hole V82 to the eighty-third via hole V83 can be removed to expose a portion of the surface of the third conductive layer.

[0221] (8) Forming a fourth conductive layer. In some examples, a fourth conductive film is deposited on the substrate having the aforementioned pattern, and the fourth conductive film is patterned by a patterning process to form a fourth conductive layer on the fifth insulating layer. In some examples, the fourth conductive layer may also be referred to as a first source / drain metal layer.

[0222] Figure 16A is a partial schematic diagram of the fourth conductive layer in region C1. Figure 16B is a partial schematic diagram of the display region after the fourth conductive layer is formed. Figure 16C is a partial schematic diagram of the first corner region after the fourth conductive layer is formed.

[0223] In some examples, as shown in Figures 16A and 16B, the fourth conductive layer of the display area AA may include at least: a plurality of pixel connection electrodes (for example, including a first pixel connection electrode 301 to an eighth pixel connection electrode 308), a plurality of routing transfer electrodes (for example, including a first routing transfer electrode 311 to a sixth routing transfer electrode 316), a third initial auxiliary line 31, a first auxiliary connection line 321, and a second auxiliary connection line 322.

[0224] In some examples, the first pixel connection electrode 301 can be connected to the first area of ​​the active layer PT10 of the first pixel transistor PT1 through the first via hole V1, and can also be connected to the first initial signal line INIT1(m-1) through the twenty-third via hole V23. The second pixel connection electrode 302 can be connected to the second area of ​​the active layer PT10 of the first pixel transistor PT1 through the second via hole V2, and can also be connected to the first area of ​​the active layer PT20 of the second pixel transistor PT2 through the twenty-first via hole V21, and can also be connected to the first area of ​​the active layer PT60 of the sixth pixel transistor PT6 through the sixth via hole V6. The third pixel connection electrode 303 can be connected to the first area of ​​the active layer PT40 of the fourth pixel transistor PT4 through the third via hole V3. The fourth pixel connection electrode 304 can be connected to the first area of ​​the active layer PT50 of the fifth pixel transistor PT5 through the fifth via hole V4, and can also be connected to the second electrode Cst-2 of the storage capacitor through the sixteenth via hole V16. The fifth pixel connection electrode 305 can be connected to the first area of ​​the active layer PT50 of the fifth pixel transistor PT5 through the fourth via hole V4, and can also be connected to the second area of ​​the active layer PT80 of the eighth pixel transistor PT8 through the tenth via hole V10. The sixth pixel connection electrode 306 can be connected to the first area of ​​the active layer PT80 of the eighth pixel transistor PT8 through the ninth via hole V9, and can also be connected to the third initial signal line INIT3(m) through the twenty-fifth via hole V25. The seventh pixel connection electrode 307 can be connected to the first area of ​​the active layer PT70 of the seventh pixel transistor PT7 through the eighth via hole V8, and can also be connected to the second initial signal line INIT2(m) through the twenty-sixth via hole V26. The eighth pixel connection electrode 308 can be connected to the second area of ​​the active layer PT60 of the sixth pixel transistor PT6 through the seventh via hole V7.

[0225] In some examples, the third initial auxiliary line 31 may be a straight line extending along the second direction Y. The third initial auxiliary line 31 may be connected to the third initial signal line INIT3(m) through a twenty-fourth via V24. The third initial auxiliary line 31 may transmit the third initial signal along the second direction Y. The third initial auxiliary line 31 and the third initial signal line may form a mesh structure for transmitting the third initial signal in the display area, which facilitates uniform transmission of the third initial signal.

[0226] In some examples, the first auxiliary connection line 321 and the second auxiliary connection line 322 can be roughly stepped. The second auxiliary connection line 322 can be located on a side of the first auxiliary connection line 321 close to the pixel circuit. The first auxiliary connection line 321 can be configured to connect the second reset control line connected to two adjacent rows of pixel circuits. For example, one end of the first auxiliary connection line 321 can be connected to the second reset control line RST2(m) through the thirteenth via V13, and the other end can be connected to the second reset control line RST2(m-1). In this example, two adjacent rows of pixel circuits can be grouped together and receive the same second reset control signal.

[0227] In some examples, the second auxiliary connection line 322 can be configured to connect the emission control lines connected to two adjacent rows of pixel circuits. For example, one end of the second auxiliary connection line 322 can be connected to the emission control line EML(m) through the twelfth via V12, and the other end can be connected to the emission control line EML(m-1). In this example, the two adjacent rows of pixel circuits are grouped together and can receive the same emission control signal.

[0228] In some examples, the first routing electrode 311 can be connected to the end of the first initial signal line INIT1(m) through two twenty-ninth vias V29. The first routing electrode 311 and the first sub-connection line 111 of the first routing line 11 can be an integrated structure connected to each other. The first initial signal line INIT1(m) can be connected to multiple auxiliary blocks in the display area, and the first initial signal line INIT1(m) may not be connected to the pixel circuit.

[0229] In some examples, the second routing electrode 312 can be connected to the end of the second initial signal line INIT2(m) through two 30th vias V30. The second routing electrode 311 can be connected to the first sub-connection line 121 located on the fifth conductive layer of the first routing line 12 formed later.

[0230] In some examples, the third routing electrode 313 can be connected to the end of the third initial signal line INIT3(m) through two twenty-eighth vias V28. The third routing electrode 313 can be connected to the first sub-connection line 131 located on the fifth conductive layer of the first routing line 13 formed later.

[0231] In some examples, the fourth routing electrode 314 can be connected to the second scan auxiliary line GL2a(m) through two seventeenth vias V17 and can also be connected to the second scan line GL2(m) through two twenty-seventh vias V27. The fourth routing electrode 314 can be integrally connected to the second drive connection line 152.

[0232] In some examples, the fifth routing electrode 315 can be connected to the first scan line GL1 (m) through two fourteenth vias V14. The fifth routing electrode 315 can be connected to the first driving connection line 151 formed later on the fifth conductive layer as an integrated structure.

[0233] In some examples, the sixth routing electrode 316 can be connected to the first reset control line RST1(m) through two fifteenth via holes V15. The sixth routing electrode 316 and the third driving connection line 153 can be an integrated structure connected to each other.

[0234] In some examples, as shown in Figures 16A and 16C, the fourth conductive layer of the first corner area B4a may include at least: a plurality of shift connection electrodes (for example, including the second shift connection electrode 412 to the thirteenth shift connection electrode 423), a plurality of output connection electrodes (for example, the fifth output connection electrode 405 to the eighth output connection electrode 408, the ninth output connection electrodes 409a and 409b and the tenth output connection electrodes 410a and 410b), a plurality of routing transfer electrodes (for example, including the seventh routing transfer electrode 317 and the eighth routing transfer electrode 318), a second drive connection line 152, a third drive connection line 153, a first sub-connection line 111 of the first transfer line 11, and a second transfer line 141.

[0235] In some examples, the second shift connection electrode 412 can be connected to the first region of the active layer GT10 of the first shift transistor GT1 through the fifty-second via V52, and can also be connected to the output terminal of the previous-stage driver unit. The third shift connection electrode 413 can be connected to the first region of the active layer GT30 of the third shift transistor GT3 through the fifty-third via V52, and can also be connected to the gate of the eighth shift transistor of the previous-stage driver unit. The fourth shift connection electrode 414 can be connected to the integrated structure of the gates of the first shift transistor GT1 and the third shift transistor GT3 through the sixty-third via V63, and can also be connected to the first region of the active layer GT20 of the second shift transistor GT2 through the fifty-fifth via V55. The fifth shift connection electrode 415 can be connected to the second region of the active layer GT30 of the third shift transistor GT3 through the fifty-fourth via V54, can also be connected to the second region of the active layer GT20 of the second shift transistor GT2 through the fifty-sixth via V56, and can also be connected to the first shift connection electrode 411 through the eighty-first via V81. The sixth shift connection electrode 416 can be connected to the second region of the active layer GT10 of the first shift transistor GT1 through the fifty-first via V51, can be connected to the gate of the second shift transistor GT2 through the sixty-fourth via V64, and can be connected to the first region of the active layer GT80 of the eighth shift transistor GT8 through the fifty-eighth via V58. The seventh shift connection electrode 417 can be connected to the gate of the eighth shift transistor GT8 through the sixty-ninth via V69. The eighth shift connection electrode 418 can be connected to the gate of the seventh shift transistor GT7 through the sixty-seventh via V67. The ninth shift connection electrode 419 can be connected to the second region of the active layer GT80 of the eighth shift transistor GT8 through the fifty-ninth via V58, and can be connected to the gate of the fifth shift transistor GT5 through the sixty-eighth via V68. The tenth shift connection electrode 420 can be connected to the first shift connection electrode 411 through the eightieth via V80, and can be connected to the gate of the fourth shift transistor GT4 through the sixty-fifth via V65. The eleventh shift connection electrode 421 can be connected to the first region of the active layer GT60 of the sixth shift transistor GT6 through the fifty-seventh via hole V57, can also be connected to the first region of the active layer GT40 of the fourth shift transistor GT4 through multiple sixtieth via holes V60, and can also be connected to the second electrode GC1-2 of the first capacitor through two seventy-sixth via holes V76. The twelfth shift connection electrode 422 can be connected to the gate of the seventh shift transistor GT7 through the sixty-sixth via hole V66, and can also be connected to the first region of the active layer GT50 of the fifth shift transistor GT5 through multiple sixty-first via holes V6.The thirteenth shift connection electrode 423 can be connected to the second region of the active layer GT50 of the fifth shift transistor GT5 through a plurality of sixty-second via holes V62, and can also be connected to the second electrode GC2-2 of the second capacitor through a plurality of seventy-seven via holes V77. The thirteenth shift connection electrode 423 can serve as an output terminal of the current stage drive unit, and one end of the thirteenth shift connection electrode 423 can be located between a ninth output connection electrode and a tenth output connection electrode (for example, between the ninth output connection electrode 409a and the tenth output connection electrode 410a).

[0236] In some examples, the fifth output connection electrode 405 can be connected to the third output connection electrode 403 through the seventy-ninth via hole V79, and can also be connected to the first output connection electrode 401 through the seventy-first via hole V71. The sixth output connection electrode 406 can be connected to the fourth output connection electrode 404 through the eighty-third via hole V83, and can also be connected to the second output connection electrode 402 through the seventieth via hole V70. The seventh output connection electrode 407 can be connected to the third output connection electrode 403 through the seventy-eighth via hole V78. The eighth output connection electrode 408 can be connected to the fourth output connection electrode 404 through the eighty-second via hole V82. The ninth output connection electrode 409a can be connected to the first output connection electrode 401 through the seventy-fourth via hole V74, and the ninth output connection electrode 409b can be connected to the first output connection electrode 401 through the seventy-fifth via hole V73. The tenth output connection electrode 410 a may be connected to the second output connection electrode 402 through the seventy-second via hole V72 , and the tenth output connection electrode 410 b may be connected to the second output connection electrode 402 through the seventy-third via hole V73 .

[0237] In some examples, the seventh output connection electrode 407 can be connected to the output end of the driving unit of the second scan gate drive circuit. The seventh output connection electrode 407, the third output connection electrode 403, the fifth output connection electrode 405, the first output connection electrode 401 and the ninth output connection electrode 409a (or 409b) are connected in sequence to form a transmission path for the second scan signal. The ninth output connection electrode 409a can be connected to the second drive connection line 152, for example, configured to provide the second scan signal to the Mth row of pixel circuits, and the ninth output connection electrode 409b can be connected to another second drive connection line 152, for example, configured to provide the second scan signal to the M-1th row of pixel circuits. In this example, the second scan signal output by the first-level driving unit of the second scan gate drive circuit can be provided to two rows of pixel circuits.

[0238] In some examples, the eighth output connection electrode 408 can be connected to the output end of the driving unit of the first reset gate drive circuit. The eighth output connection electrode 408, the fourth output connection electrode 404, the sixth output connection electrode 406, the second output connection electrode 402 and the tenth output connection electrode 410a (or 410b) are connected in sequence to form a transmission path for the first reset control signal. The tenth output connection electrode 410a can be connected to the third drive connection line 153, for example, configured to provide the first reset control signal to the Mth row of pixel circuits, and the tenth output connection electrode 410b can be connected to another third drive connection line 153, for example, configured to provide the first reset control signal to the M-1th row of pixel circuits. In this example, the first reset control signal output by the first-level driving unit of the first reset gate drive circuit can be provided to two rows of pixel circuits.

[0239] In some examples, the seventh routing transfer electrode 317 and the eighth routing transfer electrode 318 may be adjacent. A seventh routing transfer electrode 317 and an eighth routing transfer electrode 318 may be grouped together and located between the adjacent tenth output connection electrode and the ninth output connection electrode (e.g., between the ninth output connection electrode 409b and the tenth output connection electrode 410a).

[0240] In some examples, the first initial signal line INIT1(m-1) can be connected to the second transfer line 141, and the second transfer line 141 can be an integrated structure connected to the seventh routing transfer electrode 317 to be electrically connected to the subsequently formed fourth initial power supply line INIT1a.

[0241] In some examples, one end of the first sub-connection line 111 of the first transfer line 11 may extend to connect to the first routing transfer electrode 311 . For example, the first sub-connection line 111 and the first routing transfer electrode 311 may be an integrated structure connected to each other.

[0242] In some examples, one end of the second drive connection line 152 can be connected to the fourth routing transfer electrode 314 to achieve electrical connection with the second scan line GL2(m) and the second scan auxiliary line GL2a(m). For example, the second drive connection line 152 and the fourth routing transfer electrode 314 can be an integrated structure connected to each other. The other end of the second drive connection line 152 can be connected to the ninth output connection electrode 409a to achieve connection with the second scan gate drive circuit. For example, the second drive connection line 152 and the ninth output connection electrode 409a can be an integrated structure connected to each other.

[0243] In some examples, one end of the third drive connection line 153 can be connected to the sixth routing transition electrode 316 to achieve connection with the first reset control line RST1(m). For example, the third drive connection line 153 and the sixth routing transition electrode 316 can be an integrated structure connected to each other. The other end of the third drive connection line 153 can be connected to the tenth output connection electrode 410a to achieve connection with the first reset gate drive circuit. For example, the third drive connection line 153 and the tenth output connection electrode 410a can be an integrated structure connected to each other.

[0244] In some examples, as shown in FIG16A , the fourth conductive layer of the first border area B1 may include at least a first connection electrode 113, a second connection electrode 123, and a third connection electrode 133, and a plurality of release connection electrodes. The release connection electrode can be configured to connect the drive control line with the corresponding electrostatic release circuit. The first connection electrode 113 can be configured to connect the second sub-connection line 112 and the first sub-track INIT1a-1 and the second sub-track INIT1a-2 of the first initial power supply line INIT1a, the second connection electrode 123 can be configured to connect the second sub-connection line 122 and the first sub-track INIT2a-1 and the second sub-track INIT2a-2 of the second initial power supply line INIT2a, and the third connection electrode 133 can be configured to connect the second sub-connection line 132 and the first sub-track INIT3a-1 and the second sub-track INIT3a-2 of the third initial power supply line INIT3a.

[0245] (9) Forming a sixth insulating layer and a seventh insulating layer. In some examples, a sixth insulating film is deposited on the substrate on which the aforementioned pattern is formed, and the sixth insulating film is patterned by a patterning process to form a sixth insulating layer; then, a seventh insulating film is applied, and the seventh insulating film is patterned by a patterning process to form a seventh insulating layer. In some examples, the sixth insulating layer may also be referred to as a passivation layer, and the seventh insulating layer may also be referred to as a first planarization layer.

[0246] Figure 17A is a partial schematic diagram of the display region after the seventh insulating layer is formed. Figure 17B is a partial schematic diagram of the first corner region after the seventh insulating layer is formed.

[0247] In some examples, as shown in FIG17A , the seventh insulating layer in the display area may be provided with a plurality of via holes, such as via holes 31 to 36 (V31 to V36). The seventh insulating layer and the sixth insulating layer within via holes 31 to 36 (V31 to V36) may be removed to expose a portion of the surface of the fourth conductive layer.

[0248] In some examples, as shown in FIG17B , the seventh insulating layer in the first corner region may be provided with a plurality of vias, such as the 81st through 87th vias V81 through V87. The seventh and sixth insulating layers within the 81st through 87th vias V81 through V87 may be removed to expose a portion of the surface of the fourth conductive layer.

[0249] (10) Forming a fifth conductive layer. In some examples, a fifth conductive film is deposited on the substrate having the aforementioned pattern, and the fifth conductive film is patterned by a patterning process to form a fifth conductive layer on the seventh insulating layer. In some examples, the fifth conductive layer may also be referred to as a second source / drain metal layer.

[0250] Figure 18A is a partial schematic diagram of region C1 after forming the fifth conductive layer. Figure 18B is a schematic diagram of the fifth conductive layer in Figure 18A. Figure 18C is a partial schematic diagram of the display region after forming the fifth conductive layer. Figure 18D is a partial schematic diagram of the first corner region after forming the fifth conductive layer.

[0251] In some examples, as shown in FIG. 18A , FIG. 18B , and FIG. 18C , the fifth conductive layer of the display area AA may include at least a data connection electrode 321 , a first power connection electrode 322 , a first anode connection electrode 323 , and a second power auxiliary line 32 .

[0252] In some examples, the data connection electrode 321 may be connected to the third pixel connection electrode 303 through the thirty-first via hole V31 to achieve connection with the first region of the active layer PT40 of the fourth pixel transistor PT4 of the pixel circuit.

[0253] In some examples, the first power connection electrode 322 can be connected to the fourth pixel connection electrode 304 through the thirty-second via hole V32, thereby connecting to the first region of the active layer PT50 of the fifth pixel transistor PT5 of the pixel circuit and the second electrode Cst-2 of the storage capacitor. The first power connection electrodes 322 connected to adjacent pixel circuits within adjacent pixel circuit groups can be interconnected and integrally structured, and can be substantially symmetrical about the midline of the two adjacent pixel circuit groups in the first direction X.

[0254] In some examples, the first anode connection electrode 323 may be connected to the second region of the active layer PT60 of the sixth pixel transistor PT6 through the thirty-third via hole V33 .

[0255] In some examples, the second auxiliary power supply line 32 may extend substantially along the first direction X. The orthographic projection of the second auxiliary power supply line 32 on the substrate may at least partially overlap with the orthographic projection of the first initial signal line on the substrate. The second auxiliary power supply line 32 may be electrically connected to a subsequently formed second power supply line.

[0256] In some examples, as shown in Figures 18A, 18B, and 18D, the fifth conductive layer of the first corner area B4a may include at least: a third power line VGH, a fourth power line VGL, a first clock signal line GCK, a second clock signal line GCB, a first start signal line GSTV, a fourth initial power line INIT1b, a fifth initial power line INIT2b, a sixth initial power line INIT3b, a first driving connection line 151, second transfer lines 142 and 143, a first sub-connection line 121 of the first transfer line 12, and a first sub-connection line 131 of the first transfer line 13. In some examples, the fifth conductive layer of the first border area B1 may include at least: a second sub-connection line 112 of the first transfer line 11, a second sub-connection line 122 of the first transfer line 12, and a second sub-connection line 132 of the first transfer line 13.

[0257] In some examples, the third power line VGH can be connected to the eleventh shift connection electrode 421 through the eighty-third via V83 to achieve electrical connection with the sixth shift transistor GT6, the fourth shift transistor GT4, and the first capacitor GC1. The third power line VGH can be electrically connected to the third power supply line S_VGH in the first border area.

[0258] In some examples, the fourth power line VGL can be connected to the seventh shift connection electrode 417 through the eighty-first via V81 to achieve electrical connection with the eighth shift transistor GT8. The fourth power line VGL can also be connected to the third shift connection electrode 413 to achieve electrical connection with the third shift transistor GT3 of the current stage and the eighth shift transistor of the previous stage driver unit. The fourth power line VGL can be electrically connected to the fourth power supply line S_VGL within the first border area.

[0259] In some examples, the first clock signal line GCK can be connected to the fourth shift connection electrode 414 through the 88th via V88 to achieve electrical connection with the first shift transistor GT1, the third shift transistor GT3, and the second shift transistor GT2 of the current stage driver unit, as well as the seventh shift transistor of the previous stage driver unit. The second clock signal line GCB can be connected to the eighth shift connection electrode 418 through the 82nd via V82 to achieve electrical connection with the seventh shift transistor of the current stage driver unit. In some examples, the first shift transistor, the second shift transistor, and the third shift transistor of the 2n-1 stage driver unit can be connected to the first clock signal line GCK, and the seventh shift transistor and the eighth shift transistor can be connected to the second clock signal line GCB; the first shift transistor, the second shift transistor, and the third shift transistor of the 2n stage driver unit can be connected to the second clock signal line GCB, and the seventh shift transistor and the eighth shift transistor can be connected to the first clock signal line GCK. n can be a positive integer. This embodiment is not limited to this.

[0260] In some examples, the fourth initial power supply line INIT1b, the fifth initial power supply line INIT2b, and the sixth initial power supply line INIT3b can be arranged sequentially in a direction close to the display area. The fourth initial power supply line INIT1b, the fifth initial power supply line INIT2b, and the sixth initial power supply line INIT3b can be located on a side of the fourth power line VGH close to the display area. The orthographic projections of the fourth initial power supply line INIT1b, the fifth initial power supply line INIT2b, and the sixth initial power supply line INIT3b on the substrate can at least partially overlap with the orthographic projection of the first scan gate drive circuit on the substrate. For example, the orthographic projections of the fourth initial power supply line INIT1b and the fifth initial power supply line INIT2b on the substrate can partially overlap with the orthographic projections of the first capacitor and the second capacitor of the drive unit of the first scan gate drive circuit on the substrate. The configuration of this example can reduce wiring layout space, which is conducive to narrow bezel design.

[0261] In some examples, the fourth initial power supply line INIT1b can be connected to the seventh routing electrode 317 through the 85th via V85. The seventh routing electrode 317 and the second routing line 141 on the fourth conductive layer can be connected to each other as an integrated structure. The fourth initial power supply line INIT1b and the second sub-connection line 112 can also be connected to each other as an integrated structure.

[0262] In some examples, the fifth initial power supply line INIT2b can be connected to the eighth routing electrode 318 located on the fourth conductive layer through the eighty-sixth via V86. The eighth routing electrode 318 can be connected to the second routing line 142 located on the fifth conductive layer through the eighty-seventh via V87. The second routing line 142 can be connected to the second initial signal line connected to the pixel circuit in the M-1th row to enable transmission of the second initial signal. The fifth initial power supply line INIT2b and the second sub-connection line 122 can be an integrated structure connected to each other.

[0263] In some examples, the sixth initial power supply line INIT3b and the third adapter line 143 can be connected to each other as an integral structure. The third adapter line 143 can be connected to the third initial signal line connected to the pixel circuit in the M-1th row to transmit the third initial signal. The sixth initial power supply line INIT3b and the second sub-connection line 132 can be connected to each other as an integral structure.

[0264] In some examples, one end of the first drive connection line 151 can be connected to the fifth routing electrode 315 through the thirty-sixth via V36 to achieve connection with the first scan line GL1(m). The first drive connection line 151 can be connected to the thirteenth shift connection electrode 423 of the M-th stage drive unit through the eighty-fourth via V84 to achieve transmission of the first scan signal.

[0265] In some examples, the first sub-connection line 121 of the first transfer line 12 can be connected to the first routing electrode 311 through the thirty-fourth via V34. The first sub-connection line 121 can be connected to the second sub-connection line 122 on the fifth conductive layer through the fourth connection electrode 124 on the fourth conductive layer.

[0266] In some examples, the first sub-connection line 131 of the first adapter line 13 can be connected to the third routing adapter electrode 313 through the thirty-fifth via V35. The first sub-connection line 131 and the second sub-connection line 132 of the first adapter line 13 can be an integrated structure connected to each other. In this example, the fourth initial power supply line INIT1b can be connected to the first initial power supply line INIT1a through the second sub-connection line 112 of the first adapter line 11, the fifth initial power supply line INIT2b can be connected to the second initial power supply line INIT2a through the second sub-connection line 122 of the first adapter line 12, and the sixth initial power supply line INIT3b can be connected to the third initial power supply line INIT3a through the second sub-connection line 132 of the first adapter line 13. However, this embodiment is not limited to this. In other examples, the fourth initial power supply line, the fifth initial power supply line and the sixth initial power supply line can be connected to the corresponding initial power supply lines in the first frame area through the remaining connection lines.

[0267] In this example, the first scan line connected to each row of pixel circuits can be connected to the output end of the driving unit of the first scan gate driving circuit via a first drive connection line 151 located on the fifth conductive layer; the second scan line and the second scan auxiliary line connected to each row of pixel circuits can be connected to the output end of the driving unit of the second scan gate driving circuit via a second drive connection line 152 located on the fourth conductive layer; and the first reset control line connected to each row of pixel circuits can be connected to the output end of the driving unit of the first reset gate driving circuit via a third drive connection line 153 located on the fourth conductive layer. The first drive connection line 151 connected to each row of pixel circuits can be located between the second drive connection line 152 and the third drive connection line 153. The orthographic projections of the first drive connection line 151, the second drive connection line 152, and the third drive connection line 153 on the substrate can have no overlap.

[0268] In this example, the second initial signal line connected to the last row of pixel circuits is connected to the first sub-connection line 121 located on the fifth conductive layer, and the third initial signal line is connected to the first sub-connection line 131 located on the fifth conductive layer. The first initial signal line closest to the first border area is connected to the first sub-connection line 111 located on the fourth conductive layer. The first sub-connection line 111 can be located between the first sub-connection line 121 and the first sub-connection line 131. The remaining first initial signal lines can be connected to the corresponding second transfer lines 141 located on the fourth conductive layer, the remaining second initial signal lines can be connected to the corresponding second transfer lines 142 located on the fifth conductive layer, and the remaining third initial signal lines can be connected to the corresponding second transfer lines 143 located on the fifth conductive layer. The second transfer line 141 can be located between the second transfer line 142 and the second transfer line 143. The orthographic projections of the first sub-connection lines 111, 121, and 131 and the second transfer lines 141, 142, and 143 on the substrate may not overlap.

[0269] In this example, multiple traces in the first corner area are arranged at intervals on the fifth conductive layer and the fourth conductive layer, which helps to reduce the intervals between adjacent traces and the space required for trace arrangement, thereby supporting a narrow frame design.

[0270] (10) Forming an eighth insulating layer. In some examples, an eighth insulating film is coated on the substrate having the aforementioned pattern, and the eighth insulating film is patterned by a patterning process to form the eighth insulating layer. In some examples, the eighth insulating layer may also be referred to as a second planar layer.

[0271] Figure 19 is a partial schematic diagram of the display area after the eighth insulating layer is formed. In some examples, as shown in Figure 19, the eighth insulating layer of the display area can be provided with multiple vias, such as vias 41 to 44 (V41 to V44). The eighth insulating layer within vias 41 to 44 (V41 to V44) can be removed, exposing a portion of the surface of the fifth conductive layer.

[0272] (11) Forming a sixth conductive layer. In some examples, a sixth conductive film is deposited on the substrate having the aforementioned pattern, and the sixth conductive film is patterned by a patterning process to form a sixth conductive layer on the eighth insulating layer. In some examples, the sixth conductive layer may also be referred to as a third source / drain metal layer.

[0273] Figure 20A is a partial schematic diagram of the display area after the sixth conductive layer is formed. Figure 20B is a schematic diagram of the sixth conductive layer in Figure 20A.

[0274] In some examples, as shown in FIG. 20A and FIG. 20B , the sixth conductive layer of the display area may include at least a data line DL, a first power line VDD, a second anode connection electrode 324 , and a second power line VSS.

[0275] In some examples, the data line DL may be substantially in the shape of a zigzag line extending along the second direction Y. The data line DL may be connected to the data connection electrode 321 through the forty-fourth via hole V44 to provide a data signal to the fourth pixel transistor PT4 of the pixel circuit.

[0276] In some examples, the second anode connection electrode 324 can be connected to the first anode connection electrode 323 through a forty-third via hole V43 to achieve connection with the second electrode of the sixth pixel transistor PT4 of the pixel circuit.

[0277] In some examples, the first power line VDD can be substantially in the shape of a non-uniform line extending along the second direction Y. The first power line VDD can be connected to the first power connection electrode 322 through the forty-second via V42 to achieve transmission of the first voltage signal along the second direction Y. The first power lines VDD connected to two adjacent pixel circuits can be an integrated structure connected to each other, and the integrated structure can be substantially symmetrical about the center line of the two pixel circuits along the first direction X. The first power line VDD can be connected to the integrated structure of the second electrodes of the plurality of storage capacitors located on the second conductive layer through the first power connection electrode 322, thereby achieving a mesh structure for transmitting the first voltage signal in the display area, which is beneficial to the uniformity of transmission of the first voltage signal.

[0278] In some examples, the second power line VSS can be connected to the second power auxiliary line 32 through the 44th via V44. The second power line VSS and the second power auxiliary line 32 can be connected in the display area to form a mesh structure for transmitting the second voltage signal, which is beneficial to the uniformity of the transmission of the second voltage signal.

[0279] In some examples, the sixth conductive layer in the peripheral area may include at least a second voltage transmission structure 33. The second voltage transmission structure 33 may be in a grid shape and may be an integrated structure interconnected with the second power line VSS in the display area.

[0280] In some examples, the second voltage supply line S_VSS in the peripheral region may have a three-layer routing structure, for example, including: a first sub-power line located on the fourth conductive layer, a second sub-power line located on the fifth conductive layer, and a third sub-power line located on the sixth conductive layer. The third sub-power line and the second voltage transmission structure 33 may be an integrated structure connected to each other.

[0281] In some examples, after forming the sixth conductive layer, a ninth insulating layer may be formed. Thus, the circuit structure layer of the display substrate may be completed. Subsequently, the light emitting structure and the encapsulation structure layer may be formed in sequence.

[0282] In some examples, the first conductive layer, the second conductive layer, the third conductive layer, the fourth conductive layer, the fifth conductive layer, and the sixth conductive layer can be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and can be a single layer structure or a multilayer composite structure, such as Mo / Cu / Mo. The first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer, the fifth insulating layer, and the sixth insulating layer can be made of any one or more of silicon oxide (SiOx, x>0), silicon nitride (SiNy, y>0), and silicon oxynitride (SiON), and can be a single layer, a multilayer, or a composite layer. The seventh to ninth insulating layers can be made of organic materials such as polyimide, acrylic, or polyethylene terephthalate. However, this embodiment is not limited to this.

[0283] The structure of the display substrate of this embodiment and its preparation process are merely exemplary. In some examples, the corresponding structure can be changed and the patterning process can be increased or decreased according to actual needs. In other examples, a bottom metal blocking layer (BSM) can be provided on the side of the first semiconductor layer close to the substrate, a first buffer layer can be provided between the bottom metal blocking layer and the substrate, a second buffer layer can be provided between the bottom metal blocking layer and the first semiconductor layer, and the positive projection of the bottom metal blocking layer on the substrate can cover the channel region of the active layer of multiple first-type transistors of the pixel circuit to improve the performance of the first-type transistors of the pixel circuit. However, this embodiment is not limited to this. In other examples, the sixth conductive layer can be omitted, and the data line and the first power line can be provided on the fifth conductive layer.

[0284] The preparation process of this exemplary embodiment can be realized by using currently mature preparation equipment and is well compatible with existing preparation processes. The process is simple to realize, easy to implement, has high production efficiency, low production cost, and high yield rate.

[0285] The display substrate provided in this example connects the second initial signal line and the third initial signal line connected to the M-th row of pixel circuits to the second initial power supply line and the third initial power supply line of the first border area through a first adapter line (including a first sub-connection line and a second sub-connection), and sets the first initial signal line closest to the first border area to be connected to the first initial power supply line of the first border area. This can reduce the number of traces extending to the first gate drive circuit in the first corner area, ensure the normal connection of multiple rows of pixel circuits close to the curved display area, and is conducive to narrow border design.

[0286] Figure 21A is another partial structural schematic diagram of region C1 in Figure 1. Figure 21B is a partial wiring schematic diagram of region C5 in Figure 21A. Figure 21C is a partial wiring schematic diagram of region C6 in Figure 21A. Figure 21A uses eight rows of sub-pixels (e.g., rows M-7 through M) near the curved display boundary of display area AA as an example. The Mth row of sub-pixels may be closest to the first border region B1, and M may be a positive integer. The Mth row of sub-pixels may be the last row of sub-pixels on the display substrate.

[0287] In some examples, as shown in Figures 21A to 21C, the pixel circuit of each row of sub-pixels can be electrically connected to three constant-voltage signal lines (for example, including a first initial signal line INIT1, a second initial signal line INIT2, and a third initial signal line INIT3). At least one constant-voltage signal line connected to the pixel circuits of K rows of sub-pixels (for example, K is 7, including sub-pixels in rows M to M-6) near the first border area B1 can be connected to the first-region constant-voltage power supply line located in the first border area B1 via a first adapter line.

[0288] In some examples, as shown in Figures 21A to 21C, the constant voltage signal lines transmitting the same signal connected to the pixel circuits of the seven rows of sub-pixels closest to the first border area B1 can be connected through a series connection line and connected to the first area constant voltage power supply line of the first border area B1 through a first transfer line. For example, the first initial signal line connected to the adjacent rows of pixel circuits in the Mth row to the M-6th row can be connected through a first series connection line 61a and connected to the first transfer line 11 through the first initial signal line closest to the first border area B1, and the first transfer line 11 is connected to the first initial power supply line INIT1a of the first border area B1. The second initial signal line connected to the adjacent rows of pixel circuits in the Mth row to the M-6th row can be connected through a second series connection line 61b and connected to the first transfer line 12 through the second initial signal line closest to the first border area B1, and the first transfer line 12 is connected to the second initial power supply line INIT2a of the first border area B1. The third initial signal lines connected to the pixel circuits in adjacent rows in the Mth row to the M-6th row can be connected through the third serial connection line 61c, and connected to the first transfer line 13 through the third initial signal line closest to the first frame area B1, and the first transfer line 13 is connected to the third initial power supply line INIT3a of the first frame area B1. For example, the first initial signal lines INIT1(m-3) and INIT1(m-2) can be connected to the first initial signal line INIT1(m) through the first serial connection line 61a, and the first initial signal line INIT1(m) can be connected to the first sub-connection line 111 of the first transfer line 11. The second initial signal lines INIT2(m-3) and INIT2(m-2) can be connected to the second initial signal line INIT2(m) through the second serial connection line 61b, and the second initial signal line INIT2(m) can be connected to the first sub-connection line 121 of the first transfer line 12. The third initial signal lines INIT3(m-3) and INIT3(m-2) may be connected to the third initial signal line INIT3(m) through the third series connection line 61c, and the third initial signal line INIT3(m) may be connected to the first sub-connection line 131 of the first patch line 13.

[0289] In some examples, the first series connection line 61a, the second series connection line 61b, and the third series connection line 61c can extend in a stepped manner along adjacent rows of pixel circuits. The second series connection line 61b, the first series connection line 61a, and the third series connection line 61c can be arranged in sequence in a direction close to the pixel circuits.

[0290] In some examples, the first initial signal line, the second initial signal line, and the third initial signal line connected to the seven rows of pixel circuits closest to the first border area B1 are respectively connected to the first initial power supply line, the second initial power supply line, and the third initial power supply line of the first border area through the first adapter line, so that the number of wiring in the first corner area can be reduced. In this example, each row of pixel circuits has three signal lines (for example, including: a first drive connection line 151 connected to the first scan line, a second drive connection line 152 connected to the second scan line, and a third drive connection line 153 connected to the first reset control line) connected to the gate drive circuit. Compared with each row of pixel circuits having six signal lines (for example, including: a first drive connection line 151 connected to the first scan line, a second drive connection line 152 connected to the second scan line, a third drive connection line 153 connected to the first reset control line, and three second adapter lines) extending to the gate drive circuit, this example can reduce the number of wiring from the area where the gate drive circuit is located in the first corner area to the display area; for example, the saved wiring space can be 7*4.2*3=88.2μm, and the space utilization can be increased by 50%. By reducing the number of connections, this example can further move the cutoff position of the gate drive circuit upward, which is beneficial to widening the line width of the second power supply line S_VSS, preventing excessive resistance and current density, and reducing power consumption. In addition, the dummy pixels in the display area can be retained to ensure the etching uniformity and stable transistor characteristics of the display area. This example is conducive to achieving a narrow bezel design and can be beneficial for designing display products with a larger screen-to-body ratio.

[0291] Figure 22 is a partial schematic diagram of the display area of ​​at least one embodiment of the present disclosure. Figure 22 illustrates the wiring connection structure between two adjacent rows of pixel circuits (for example, the i-th row of pixel circuits and the i-1-th row of pixel circuits) closest to the first border area, where i can be a positive integer less than M. Figure 22 illustrates a partial schematic diagram of the display substrate after the fifth conductive layer is formed. Figure 23A is a schematic diagram of the display area after the third conductive layer is formed in Figure 22. Figure 23B is a schematic diagram of the fourth conductive layer in Figure 22. Figure 23C is a schematic diagram of the fifth conductive layer in Figure 22.

[0292] In some examples, as shown in Figures 22 to 23C, the first initial signal lines INIT1(i) and INIT1(i-1), the second initial signal lines INIT2(i) and INIT2(i-1), and the third initial signal lines INIT3(i) and INIT3(i-1) can be located in the third conductive layer. The first initial signal lines INIT1(i) and INIT1(i-1) can be connected by a first series connection line 61a, the second initial signal lines INIT2(i) and INIT2(i-1) can be connected by a second series connection line 61b, and the third initial signal lines INIT3(i) and INIT3(i-1) can be connected by a third series connection line 61c. The first series connection line 61a, the second series connection line 61b, and the third series connection line 61c can be located in the fourth conductive layer. The second series connection line 61b, the first series connection line 61a, and the third series connection line 61c can be arranged in sequence along a direction close to the pixel circuit. The first series connection line 61 a , the second series connection line 61 b ​​, and the third series connection line 61 c may extend along a staircase shape formed between the pixel circuits in the i-th row and the pixel circuits in the (i−1)th row.

[0293] In some examples, the fourth conductive layer may further include: a first auxiliary connection line 321 and a second auxiliary connection line 322. The first auxiliary connection line 321 may connect the second reset control lines RST2(i) and RST2(i-1) located in the first conductive layer. The second auxiliary connection line 322 may connect the light emission control lines EML(i) and EML(i-1) located in the first conductive layer. The first auxiliary connection line 321 and the second auxiliary connection line 322 may be located on a side of the three series connection lines close to the pixel circuit. The extension direction of the first auxiliary connection line 321 and the second auxiliary connection line 322 may be substantially the same as the extension direction of the three series connection lines.

[0294] In some examples, the first drive connection line 151, the second drive connection line 152, and the third drive connection line 153 may be located in the fifth conductive layer. The first drive connection line 151 may be connected to the first scan line GL1(i) located in the first conductive layer via the fifth routing transfer electrode 315 located in the fourth conductive layer. The second drive connection line 152 may be connected to the second scan auxiliary line GL2a(i) located in the second conductive layer and the second scan line GL2(i) located in the third conductive layer via the fourth routing transfer electrode 314 located in the fourth conductive layer. The third drive connection line 153 may be connected to the first reset control line RST1(i) located in the first conductive layer via the sixth routing transfer electrode 316 located in the fourth conductive layer. However, this embodiment is not limited to this. In other examples, the fourth routing transfer electrode, the fifth routing transfer electrode, and the sixth routing transfer electrode may be located in the fifth conductive layer, and the first drive connection line, the second drive connection line, and the third drive connection line may be located in the fourth conductive layer.

[0295] In this example, by connecting the initial signal lines connected to the seven rows of pixel circuits near the first border area, and then leading them to the first border area to connect to the initial power supply lines located in the first border area, the number of traces in the first corner area can be reduced, thereby facilitating a narrow border design. The remaining description of this example can be referred to the description of the previous embodiment, so it will not be repeated here.

[0296] Figure 24 is another partial structural diagram of area C1 in Figure 1. In some examples, as shown in Figure 24, the curved display boundary corresponding to the first corner area can be adjacent to N rows of sub-pixels in the display area, that is, N rows of sub-pixels are close to the curved display boundary, where N can be a positive integer. The constant voltage signal lines transmitting the same signal connected to the pixel circuits of the N rows of sub-pixels can be connected together and connected to the first area constant voltage power supply line of the first border area via a first adapter line. For example, the first initial signal lines corresponding to adjacent rows of pixel circuits in N rows of pixel circuits can be connected through the first series connection line 61a, and the first initial signal line closest to the first border area can be connected to the first initial power supply line INIT1a through the first adapter line 11; the second initial signal lines corresponding to adjacent rows of pixel circuits in N rows of pixel circuits can be connected through the second series connection line 61b, and the second initial signal line closest to the first border area can be connected to the second initial power supply line INIT2a through the first adapter line 12; the third initial signal lines corresponding to adjacent rows of pixel circuits in N rows of pixel circuits can be connected through the third series connection line 61c, and the third initial signal line closest to the first border area can be connected to the third initial power supply line INIT3a through the first adapter line 13.

[0297] In some examples, assuming that the first corner area corresponds to 150 rows of sub-pixels, by saving three second transfer lines of the initial signal lines for each row of pixel circuits, that is, corresponding to each row of pixel circuits, 4.2*3=12.6μm of routing space can be saved in the first corner area. In this way, the cutoff position of the gate drive circuit can be moved upward, for example, the cutoff position of the gate drive circuit can be moved up by one-quarter of the total length of the first corner area; or the line width of the second power supply line S_VSS can be widened, for example, the line width of the second power supply line S_VSS can be doubled. The rest of the description of this example can refer to the description of the aforementioned embodiment, so it will not be repeated here.

[0298] This embodiment also provides a display substrate, comprising: a display area and a peripheral area surrounding the display area, wherein the display area includes at least one arc-shaped display border. The display area includes M rows of sub-pixels disposed on a substrate, wherein at least one row of the M rows of sub-pixels includes a plurality of sub-pixels arranged sequentially along a first direction, at least one sub-pixel including a pixel circuit and a light-emitting element connected to the pixel circuit, and the pixel circuit of at least one row of the M rows of sub-pixels is connected to at least one constant-voltage signal line extending along the first direction. N rows of sub-pixels adjacent to the arc-shaped display border are arranged in a stepped manner, wherein N and M are both positive integers, and N is less than or equal to M. The peripheral area includes a first frame area located on one side of the display area along a second direction, and a first corner area located outside the arc-shaped display border, the first frame area being connected to the first corner area. The second direction intersects the first direction. The first frame area includes at least one first-region constant-voltage power supply line disposed on the substrate. The constant-voltage signal line connected to the pixel circuit of at least one row of the N rows of sub-pixels adjacent to the arc-shaped display border is connected to the first-region constant-voltage power supply line in the first frame area via a first adapter line. A portion of the first patch cord is located in the first corner area.

[0299] The display substrate provided in this embodiment is provided with a constant voltage signal line connected to the pixel circuit of at least one row of sub-pixels in the N rows of sub-pixels close to the curved display boundary, and is connected to the first area constant voltage power supply line of the first border area. This can reduce the number of wiring in the first corner area and ensure the normal connection of multiple rows of sub-pixels close to the curved display boundary, which is conducive to narrow border design.

[0300] In some exemplary embodiments, the first adapter line may include: a first sub-connection line and a second sub-connection line, wherein the extension direction of the first sub-connection line intersects the extension direction of the second sub-connection line, and the first sub-connection line and the second sub-connection line are connected; the first sub-connection line is connected to a constant voltage signal line connected to the pixel circuit of at least one row of sub-pixels in the N rows of sub-pixels near the curved display boundary, and the second sub-connection line is connected to the constant voltage power supply line of the first region. The connection point between the first sub-connection line and the second sub-connection line may be located in the first corner region. This example can help reduce the number of traces extending into the region where the gate drive circuit is located, thereby facilitating a narrow bezel design.

[0301] In some exemplary embodiments, the peripheral area may further include at least one second-area constant-voltage power supply line, which extends to the first corner area and is connected to the first-area constant-voltage power supply line via a second sub-connection line. In some examples, the second-area constant-voltage power supply line and the connected second sub-connection line may be an integrated structure that is interconnected. This example may facilitate the connection between the first-area constant-voltage power supply line and the second-area constant-voltage power supply line, reducing the required wiring.

[0302] In some exemplary embodiments, the first corner region may further include: a plurality of cascaded drive units disposed on the substrate, the second region constant voltage power supply line being located on a side of the plurality of cascaded drive units closer to the display region, and the second sub-connection line being located in the first direction on a side of the plurality of drive units closer to the first region constant voltage power supply line. In some examples, the drive units may be connected to gate lines connected to at least one row of sub-pixels via a drive connection line, and the drive connection line may be located in the second direction on a side of the first sub-connection line closer to the display region. This exemplary arrangement can help reduce the number of wiring in the first corner region, thereby facilitating a narrow bezel design.

[0303] The description of the display substrate of this embodiment can refer to the description of the aforementioned embodiment, and thus will not be repeated here.

[0304] FIG25 is a schematic diagram of a display device according to at least one embodiment of the present disclosure. In some examples, as shown in FIG25 , the present embodiment provides a display device including a display substrate according to the aforementioned embodiment.

[0305] In some examples, the display substrate 91 may be a flexible OLED display substrate, a QLED display substrate, a Micro-LED display substrate, or a Mini-LED display substrate. The display device may be a product having an image (including a static image or a dynamic image, wherein the dynamic image may be a video) display function. For example, the display device may be: a display, a television, a billboard, a digital photo frame, a laser printer with a display function, a telephone, a mobile phone, a painting screen, a personal digital assistant (PDA), a digital camera, a portable camcorder, a viewfinder, a navigator, a vehicle, a large-area wall, an information query device (such as business query equipment for e-government, banks, hospitals, power departments, etc.), a monitor, and the like. For another example, the display device may also be a microdisplay, a VR device or an AR device containing a microdisplay, and the like.

[0306] The drawings in this disclosure only relate to the structures involved in this disclosure, and other structures can refer to the general design. In the absence of conflict, the embodiments of the present disclosure, that is, the features in the embodiments, can be combined with each other to obtain new embodiments. It should be noted that the above-mentioned embodiments or implementation methods are merely exemplary and not restrictive. Therefore, the present disclosure is not limited to the contents shown and described in detail herein. Various modifications, replacements or omissions can be made to the form and details of the implementation without departing from the scope of this disclosure.

Claims

1. A display substrate, comprising: a display area and a peripheral area surrounding the display area, the display area including at least one arc-shaped display boundary; the display area includes: M rows of sub-pixels disposed on a substrate, at least one row of the M rows of sub-pixels including a plurality of sub-pixels arranged in sequence along a first direction, at least one of the plurality of sub-pixels including a pixel circuit and a light-emitting element connected to the pixel circuit, the pixel circuit of at least one row of the M rows of sub-pixels being connected to at least one constant voltage signal line extending along the first direction; N rows of sub-pixels adjacent to the arc-shaped display boundary are arranged in a stepped manner, where N and M are both positive integers, and N is less than or equal to M; the peripheral area includes: a first border area located on one side of the display area along a second direction, the second direction intersecting the first direction; the first border area includes: at least one first area constant voltage power supply line disposed on the substrate; the constant voltage signal line connected to the pixel circuit of at least one row of the N rows of sub-pixels adjacent to the arc-shaped display boundary is connected to the first area constant voltage power supply line of the first border area through a first jumper wire.

2. The display substrate according to claim 1, wherein, the constant voltage signal line connected to the pixel circuit of the row of sub-pixels closest to the first border area among the N rows of sub-pixels adjacent to the arc-shaped display boundary is connected to the first area constant voltage power supply line of the first border area through the first jumper wire.

3. The display substrate according to claim 2, wherein, the first jumper wire includes: a first sub-connection wire and a second sub-connection wire, the extending direction of the first sub-connection wire intersecting the extending direction of the second sub-connection wire, and the first sub-connection wire and the second sub-connection wire being connected; the constant voltage signal line connected to the pixel circuit of the row of sub-pixels closest to the first border area among the N rows of sub-pixels adjacent to the arc-shaped display boundary is connected to the first sub-connection wire, and the second sub-connection wire is connected to the first area constant voltage power supply line located in the first border area.

4. The display substrate according to claim 1, wherein, the constant voltage signal lines connected to the pixel circuits of K rows of sub-pixels among the N rows of sub-pixels adjacent to the arc-shaped display boundary and transmitting the same signal are connected together and connected to the first area constant voltage power supply line of the first border area through the first jumper wire, where K is a positive integer less than or equal to N and greater than or equal to 2.

5. The display substrate according to claim 4, wherein, K is less than N, and the K rows of sub-pixels are located on the side of the remaining rows of sub-pixels among the N rows of sub-pixels closer to the first border area.

6. The display substrate according to claim 5, wherein, the K rows of sub-pixels include the seven rows of sub-pixels closest to the first border area among the N rows of sub-pixels.

7. The display substrate according to claim 4, wherein, The first adapter cable includes: a first sub - connection cable and a second sub - connection cable. The extending direction of the first sub - connection cable intersects with the extending direction of the second sub - connection cable, and the first sub - connection cable is connected to the second sub - connection cable. The constant - voltage signal lines that transmit the same signal and are connected to the pixel circuits of adjacent rows of sub - pixels among the K rows of sub - pixels are electrically connected through a series connection cable. The constant - voltage signal line connected to the pixel circuit of the row of sub - pixels closest to the first border region among the K rows of sub - pixels is connected to the first sub - connection cable, and the second sub - connection cable is connected to the first - region constant - voltage power supply line located in the first border region.

8. The display substrate according to claim 7, wherein, The series connection cable connected to the constant - voltage signal lines connected to the pixel circuits of adjacent rows of sub - pixels among the K rows of sub - pixels extends along the stepped shape formed by the adjacent rows of sub - pixels.

9. The display substrate according to claim 7, wherein, The series connection cable is located on the side of the connected constant - voltage signal line away from the substrate.

10. The display substrate according to claim 3 or 7, wherein, The first sub - connection cable and the second sub - connection cable are located on the side of the connected first - region constant - voltage power supply line away from the substrate; The second sub - connection cable is located on the side of the first sub - connection cable away from the substrate, or the second sub - connection cable and the first sub - connection cable are an integrally connected structure.

11. The display substrate according to claim 3 or 7, wherein, The first border region further includes: a plurality of electrostatic discharge circuits. Each electrostatic discharge circuit is connected to a signal line and is configured to discharge the static electricity in the connected signal line; the second sub - connection cable is located on the side away from the edge of the display substrate of the plurality of electrostatic discharge circuits in the first direction.

12. The display substrate according to any one of claims 1 to 11, wherein, The peripheral region further includes: a second border region located on at least one side of the display region along the first direction; The second border region includes: at least one second - region constant - voltage power supply line provided on the substrate; The second - region constant - voltage power supply line is connected to the first - region constant - voltage power supply line; The constant - voltage signal line connected to the pixel circuit of at least one row of sub - pixels among the M rows of sub - pixels is electrically connected to the second - region constant - voltage power supply line through a second adapter cable.

13. The display substrate according to claim 12, wherein, The second border region further includes: at least one gate driving circuit provided on the substrate; the second - region constant - voltage power supply line is located on the side of the gate driving circuit close to the display region.

14. The display substrate according to claim 13, wherein, The orthographic projection of the second - region constant - voltage power supply line on the substrate overlaps at least partially with the orthographic projection of the gate driving circuit on the substrate.

15. The display substrate according to claim 1, wherein, The multiple constant - voltage signal lines connected to the pixel circuits of each row of sub - pixels include: a first initial signal line, a second initial signal line, and a third initial signal line; The pixel circuit at least includes: a driving transistor, a first reset transistor, a second reset transistor, and a third reset transistor; a gate of the driving transistor is connected to a first node, a first pole is connected to a second node, and a second pole is connected to a third node; the first reset transistor is connected to the third node and a first initial signal line, and is configured to reset the third node by using a first initial signal provided by the first initial signal line; The second reset transistor is connected to a second initial signal line and an anode of a light-emitting element, and is configured to reset the anode of the light-emitting element by using a second initial signal provided by the second initial signal line; The third reset transistor is connected to the second node and a third initial signal line, and is configured to reset the second node by using a third initial signal provided by the third initial signal line; The plurality of first-region constant-voltage supply lines provided in the first border region include: a first initial supply line, a second initial supply line, and a third initial supply line; A first initial signal line connected to a pixel circuit of at least one row of sub-pixels among N rows of sub-pixels close to the arc-shaped display boundary is connected to the first initial supply line in the first border region; A second initial signal line connected to a pixel circuit of at least one row of sub-pixels among N rows of sub-pixels close to the arc-shaped display boundary is connected to the second initial supply line in the first border region; A third initial signal line connected to a pixel circuit of at least one row of sub-pixels among N rows of sub-pixels close to the arc-shaped display boundary is connected to the third initial supply line in the first border region; The first initial supply line, the second initial supply line, and the third initial supply line are sequentially arranged along a direction close to the display region.

16. The display substrate according to claim 15, wherein, The peripheral region further includes: a second border region located on one side of the display region along the first direction, and the second border region is communicated with the first border region; The second border region includes: a plurality of second-region constant-voltage supply lines, and the plurality of second-region constant-voltage supply lines include: a fourth initial supply line, a fifth initial supply line, and a sixth initial supply line; The fourth initial supply line is connected to the first initial supply line, the fifth initial supply line is connected to the second initial supply line, and the sixth initial supply line is connected to the third initial supply line; The fourth initial supply line, the fifth initial supply line, and the sixth initial supply line are sequentially arranged along a direction close to the display region.

17. The display substrate according to claim 1, wherein, In a direction perpendicular to the display substrate, the display substrate includes: a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer provided on the substrate; The constant-voltage signal line is located in the third conductive layer; The at least one first-region constant-voltage supply line is located in the first conductive layer, or is located in the second conductive layer, or is a double-layer trace located in the first conductive layer and the second conductive layer.

18. A display device, comprising a display substrate according to any one of claims 1 to 17.

19. A display substrate, comprising: a display area and a peripheral area surrounding the display area, the display area including at least one arc-shaped display boundary; the display area includes: M rows of sub-pixels disposed on a substrate, at least one row of the M rows of sub-pixels includes a plurality of sub-pixels arranged in sequence in a first direction, at least one of the plurality of sub-pixels includes a pixel circuit and a light-emitting element connected to the pixel circuit, and the pixel circuits of at least one row of the M rows of sub-pixels are connected to at least one constant-voltage signal line extending in the first direction; N rows of sub-pixels adjacent to the arc-shaped display boundary are arranged in a stepped manner, where N and M are both positive integers, and N is less than or equal to M; the peripheral area includes: a first border area located on one side of the display area in a second direction and a first corner area located outside the arc-shaped display boundary, the first border area communicating with the first corner area; the second direction intersects the first direction; the first border area includes: at least one first area constant-voltage power supply line disposed on the substrate; the constant-voltage signal line connected to the pixel circuit of at least one row of the N rows of sub-pixels adjacent to the arc-shaped display boundary is connected to the first area constant-voltage power supply line of the first border area through a first jumper wire; a part of the first jumper wire is located in the first corner area.

20. The display substrate according to claim 19, wherein, the first jumper wire includes: a first sub-connection wire and a second sub-connection wire, the first sub-connection wire and the second sub-connection wire are connected, and the extending direction of the first sub-connection wire intersects the extending direction of the second sub-connection wire; the first sub-connection wire is connected to the constant-voltage signal line connected to the pixel circuit of at least one row of the N rows of sub-pixels adjacent to the arc-shaped display boundary, and the second sub-connection wire is connected to the first area constant-voltage power supply line; the connection position of the first sub-connection wire and the second sub-connection wire is located in the first corner area.

21. The display substrate according to claim 20, wherein, the peripheral area further includes: at least one second area constant-voltage power supply line, the second area constant-voltage power supply line extends to the first corner area and is connected to the first area constant-voltage power supply line through the second sub-connection wire.

22. The display substrate according to claim 21, wherein, the second area constant-voltage power supply line and the connected second sub-connection wire are an integrally connected structure.

23. The display substrate according to claim 21, wherein, the first corner area further includes: a plurality of cascaded driving units disposed on the substrate, the second area constant-voltage power supply line is located on a side of the plurality of cascaded driving units close to the display area, and the second sub-connection wire is located on a side of the plurality of driving units close to the first area constant-voltage power supply line in the first direction.

24. The display substrate according to claim 23, wherein, The driving unit is connected to the gate lines connected to at least one row of sub-pixels through driving connection lines, and the driving connection lines are located on a side closer to the display area of the first sub-connection line in the second direction.

Images