Display panel, display device, and driving method

Abstract

The present disclosure provides a display panel, a display device, and a driving method. The display panel comprises a substrate and a plurality of pixel opening areas provided on the substrate; the display panel further comprises at least one planarization layer, and at least two conductive layers stacked on the substrate; one planarization layer is arranged between adjacent conductive layers; the planarization layer is provided with a first-type via hole and a second-type via hole; the orthographic projection of the first-type via hole on the substrate does not overlap the orthographic projections of the pixel opening areas on the substrate; and the orthographic projection of the second-type via hole on the substrate does not overlap the orthographic projections of the pixel opening areas on the substrate. The present disclosure meets the requirements of a printing process for the flatness of a substrate of a light emitting element.

Description

Display panel, display device, and driving method Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display panel, a display device, and a driving method. Background Art

[0002] In related technologies, a printing process can be used to manufacture light-emitting devices. This printing process requires a highly flat substrate. If the substrate is uneven or not flat enough, it will affect the light color and electrical characteristics of the light-emitting device. The end result is that the light color of the light-emitting device deviates, and the efficiency, lifespan and other characteristics of the light-emitting device will also be greatly deteriorated.

[0003] Summary of the Invention

[0004] In one aspect, an embodiment of the present disclosure provides a display panel, comprising a substrate and a plurality of pixel opening areas disposed on the substrate, further comprising at least one planar layer and at least two conductive layers stacked on the substrate, wherein the planar layer is disposed between adjacent conductive layers, and the planar layer has first-type via holes and second-type via holes;

[0005] The display panel includes a signal line for transmitting a reference voltage signal and a signal line for transmitting a power supply voltage signal;

[0006] The signal line for transmitting the reference voltage signal includes a first signal line and a second signal line; the first signal line is electrically connected to the second signal line through the first type of via;

[0007] The signal line for transmitting the power supply voltage signal includes a third signal line and a fourth signal line, and the third signal line is electrically connected to the fourth signal line through the second type of via;

[0008] The orthographic projection of the first type of via on the substrate does not overlap with the orthographic projection of the pixel opening area on the substrate;

[0009] The orthographic projection of the second-type via hole on the substrate does not overlap with the orthographic projection of the pixel opening area on the substrate.

[0010] Optionally, the display panel includes a first conductive layer, a second conductive layer, and a first planar layer; the first conductive layer, the first planar layer, and the second conductive layer are arranged in sequence in a direction away from the substrate; the first signal line is a first reference signal line, and the second signal line is a first reference connecting line; the first type of via includes a first via;

[0011] The first conductive layer includes the first reference signal line, and the second conductive layer includes the first reference connection line;

[0012] The first planar layer has the first via hole; the first reference signal line is electrically connected to the first reference connection line through the first via hole.

[0013] Optionally, the display panel further includes a third conductive layer; the first conductive layer includes a second reference signal line; the third conductive layer includes a second reference connecting line; the second reference signal line is electrically connected to the second reference connecting line;

[0014] The third conductive layer is disposed between the substrate and the first conductive layer;

[0015] The first reference connection line and the second reference connection line both extend along a first direction;

[0016] The orthographic projections of the two second reference connection lines on the substrate are arranged on two opposite sides of the orthographic projection of the first reference connection line on the substrate.

[0017] Optionally, the display panel includes a first conductive layer, a second conductive layer, and a first planar layer; the first conductive layer, the first planar layer, and the second conductive layer are arranged in sequence in a direction away from the substrate; the third signal line is a first voltage line, and the fourth signal line is a first voltage connection line; the second-type via includes a second via;

[0018] The first conductive layer includes the first voltage line, and the second conductive layer includes the first voltage connection line;

[0019] The first planar layer has the second via hole; the first voltage line is electrically connected to the first voltage connection line through the second via hole.

[0020] Optionally, the planar layer has a third type of via hole;

[0021] The display panel includes a plurality of sub-pixels arranged on the substrate; the sub-pixels include a light-emitting element, a storage capacitor and a plurality of transistors;

[0022] The sub-pixel includes a plurality of conductive parts, and the plurality of conductive parts include an anode of a light-emitting element, a plate of a storage capacitor, and an electrode of the transistor;

[0023] Some of the plurality of conductive parts are electrically connected through the third type of vias;

[0024] The orthographic projection of the third type of via hole on the substrate does not overlap with the orthographic projection of the pixel opening area on the substrate.

[0025] Optionally, the planar layer has a fourth type of via hole;

[0026] The display panel includes a plurality of data lines and a plurality of sub-pixels arranged on the substrate;

[0027] Part of the electrodes of part of the transistors in the sub-pixel are electrically connected to the data line through the fourth type of via hole;

[0028] The orthographic projection of the fourth type of via hole on the substrate does not overlap with the orthographic projection of the pixel opening area on the substrate.

[0029] Optionally, the transistor in the sub-pixel includes a first reset transistor; the third type of via hole includes a third via hole and a fourth via hole;

[0030] The display panel further includes a semiconductor layer, a first conductive layer, a first planar layer, a second conductive layer, a second planar layer, and a fourth conductive layer sequentially arranged in a direction away from the substrate; the semiconductor layer includes a first electrode of the first reset transistor, and the fourth conductive layer includes an anode of the light-emitting element; the first planar layer has the third via hole, and the second planar layer has the fourth via hole;

[0031] The first electrode of the first reset transistor is electrically connected to the anode of the light emitting element through the third via hole and the fourth via hole.

[0032] Optionally, the third type of via hole includes a fifth via hole and a sixth via hole; the display panel further includes a fifth conductive layer, a first insulating layer, a first conductive layer, a first flat layer, a second conductive layer, a second flat layer, and a fourth conductive layer arranged in sequence along a direction away from the substrate;

[0033] The fourth conductive layer includes the anode of the light-emitting element; the fifth conductive layer includes the first plate of the storage capacitor;

[0034] The first flat layer has the fifth via hole, and the second flat layer has the sixth via hole;

[0035] The anode of the light emitting element is electrically connected to the first plate of the storage capacitor through the sixth via hole, the fifth via hole, and a via hole penetrating the first insulating layer.

[0036] Optionally, the transistor in the sub-pixel includes a data writing transistor; the fourth type of via hole includes a seventh via hole;

[0037] The display panel further includes a semiconductor layer, a first conductive layer, a first planar layer, and a second conductive layer sequentially arranged in a direction away from the substrate;

[0038] The semiconductor layer includes a first electrode of the data writing transistor, and the second conductive layer includes the data line;

[0039] The first planar layer has the seventh via hole, and the first electrode of the data writing transistor is electrically connected to the data line through the seventh via hole.

[0040] Optionally, the transistor in the sub-pixel includes a first reset transistor; the third type of via hole includes a third via hole, a fourth via hole and an eighth via hole;

[0041] The display panel further includes a semiconductor layer, a first conductive layer, a first planar layer, a second conductive layer, a second planar layer, a fourth conductive layer, a third planar layer, and a sixth conductive layer, which are sequentially arranged in a direction away from the substrate;

[0042] The semiconductor layer includes the first electrode of the first reset transistor, and the sixth conductive layer includes the anode of the light-emitting element; the first flat layer has the third via hole, the second flat layer has the fourth via hole, and the third flat layer has the eighth via hole;

[0043] The first electrode of the first reset transistor is electrically connected to the anode of the light emitting element through the third via hole, the fourth via hole, and the eighth via hole.

[0044] Optionally, the third type of vias includes a fifth via, a sixth via, and a ninth via;

[0045] The display panel further includes a fifth conductive layer, a first insulating layer, a first conductive layer, a first flat layer, a second conductive layer, a second flat layer, a fourth conductive layer, a third flat layer, and a sixth conductive layer, which are sequentially arranged in a direction away from the substrate;

[0046] The sixth conductive layer includes the anode of the light-emitting element, and the fifth conductive layer includes the first plate of the storage capacitor;

[0047] The first flat layer has the fifth via hole, the second flat layer has the sixth via hole, and the third flat layer has the ninth via hole;

[0048] The anode of the light-emitting element is electrically connected to the first plate of the storage capacitor through the ninth via hole, the sixth via hole, the fifth via hole, and a via hole penetrating the first insulating layer.

[0049] Optionally, the plurality of sub-pixels are divided into a plurality of pixel units arranged in an array; the pixel unit includes a plurality of sub-pixels arranged along a second direction; the first direction intersects the second direction;

[0050] N columns of the pixel units are arranged between two adjacent columns of the first reference connection lines; N is an integer greater than 1.

[0051] Optionally, the display panel further comprises a lens group of multiple rows and columns arranged on a side of the pixel unit away from the substrate; the lens group comprises an odd number of lenses;

[0052] The N pixel units located in the same row and arranged between two adjacent columns of first reference connection lines correspond to the same lens group.

[0053] Optionally, pixel units arranged between two different adjacent columns of first reference connection lines correspond to different lens groups.

[0054] Optionally, the second reference connection line is adjacent to the first reference connection line in the second direction.

[0055] Optionally, the display panel includes a plurality of sub-pixels disposed on the substrate; the sub-pixels include light-emitting elements;

[0056] The display panel includes a second conductive layer, an anode planarization layer, and a fourth conductive layer stacked in a direction away from the substrate; the fourth conductive layer includes an anode of the light-emitting element;

[0057] The thickness of the anode planarization layer is greater than that of the planarization layer.

[0058] Optionally, the sub-pixel further includes a plurality of transistors and storage capacitors;

[0059] The anode of the light-emitting element is electrically connected to a portion of electrodes of a portion of the transistors and / or a portion of the plate of the storage capacitor through a fifth type via hole of the anode planarization layer;

[0060] The orthographic projection of the fifth type of via hole on the substrate does not overlap with the orthographic projection of the pixel opening area on the substrate.

[0061] Optionally, the display panel includes a plurality of sub-pixels disposed on the substrate; the sub-pixels include light-emitting elements; the light-emitting elements include a light-emitting layer;

[0062] The light-emitting layers of the light-emitting elements in the sub-pixels located in the same column are continuous with each other and have the same color.

[0063] Optionally, the thickness of the planar layer is greater than a first thickness threshold, and the first thickness threshold is greater than or equal to 2.8 μm and less than or equal to 3.2 μm.

[0064] Optionally, the display panel includes a plurality of sub-pixels disposed on the substrate; the sub-pixels include a light-emitting element, a storage capacitor, a first reset transistor, a data writing transistor, and a second reset transistor;

[0065] The active pattern of the second reset transistor is electrically connected to the active pattern of the data writing transistor through a first connection line; the active pattern of the data writing transistor is electrically connected to the second plate of the storage capacitor through a second connection line;

[0066] The anode of the light emitting element is electrically connected to the active pattern of the first reset transistor via a third connecting line;

[0067] The first connection line, the second connection line and the third connection line are arranged on the same layer as the active pattern.

[0068] Optionally, the display panel includes a first pixel defining layer and a second pixel defining layer;

[0069] The second pixel defining layer forms a plurality of openings arranged along the second direction, and the openings extend along the first direction;

[0070] The first pixel defining layer includes a plurality of pixel defining parts arranged along a first direction, the pixel defining parts filling a portion of the openings, and the plurality of pixel defining parts defining a plurality of pixel opening areas in the plurality of openings.

[0071] Optionally, the pixel defining portion includes an integral structure extending along the second direction; or,

[0072] The pixel defining portion includes a plurality of pixel defining patterns arranged along the second direction, and at least a portion of the pixel defining patterns is filled in the corresponding openings.

[0073] Optionally, a maximum distance between the first pixel defining layer and the substrate is different from a maximum distance between the second pixel defining layer and the substrate.

[0074] In a second aspect, an embodiment of the present disclosure provides a display device comprising the above-mentioned display panel.

[0075] Optionally, the display panel includes sub-pixels;

[0076] The sub-pixel includes a light-emitting element, an energy storage circuit, a driving circuit, a data writing circuit and a light-emitting control circuit;

[0077] The first end of the energy storage circuit is electrically connected to the anode of the light-emitting element; the control end of the drive circuit is electrically connected to the second end of the energy storage circuit, the first end of the drive circuit is electrically connected to the anode of the light-emitting element, and the cathode of the light-emitting element is electrically connected to the second voltage line;

[0078] The data writing circuit is electrically connected to the first scan line, the data line and the second end of the energy storage circuit respectively, and is used to write the data voltage provided by the data line into the second end of the energy storage circuit under the control of the first scan signal provided by the first scan line;

[0079] The light-emitting control circuit is electrically connected to the light-emitting control line, the second end of the driving circuit and the first voltage line respectively, and is used to control the connection between the first voltage line and the second end of the driving circuit under the control of the light-emitting control signal provided by the light-emitting control line.

[0080] Optionally, the sub-pixel further includes a first reset circuit and a second reset circuit;

[0081] The second reset circuit is electrically connected to the second scan line, the reference voltage line and the second end of the energy storage circuit respectively, and is used to write the reference voltage provided by the reference voltage line into the second end of the energy storage circuit under the control of the second scan signal provided by the second scan line;

[0082] The first reset circuit is electrically connected to the third scan line, the initial voltage line and the anode of the light-emitting element respectively, and is used to write the initial voltage provided by the initial voltage line into the anode of the light-emitting element under the control of the third scan signal provided by the third scan line.

[0083] In a third aspect, an embodiment of the present disclosure provides a driving method, which is applied to the above-mentioned display device, wherein the display cycle includes N display stages; the nth display stage includes an nth data writing stage arranged successively; N is an integer greater than 1, and n is a positive integer less than or equal to N; the driving method includes: in at least a part of the time period included in the nth data writing stage, the data writing circuit included in the 2n-1th row of sub-pixels writes the data voltage to the second end of the energy storage circuit included in the 2n-1th row of sub-pixels under the control of the first scanning signal provided by the first scanning line of the 2n-1th row, and the data writing circuit included in the 2nth row of sub-pixels writes the data voltage to the second end of the energy storage circuit included in the 2nth row of sub-pixels under the control of the first scanning signal provided by the first scanning line of the 2nth row.

[0084] Optionally, the nth data writing phase includes an nth first writing time period and an nth second writing time period;

[0085] The driving method includes:

[0086] In the nth first writing time period, the data writing circuit included in the sub-pixel in the 2n-1th row writes the data voltage into the second end of the energy storage circuit included in the sub-pixel in the 2n-1th row under the control of the first scanning signal provided by the first scanning line in the 2n-1th row;

[0087] In the nth second writing time period, the data writing circuit included in the sub-pixels in the 2nth row writes the data voltage into the second end of the energy storage circuit included in the sub-pixels in the 2nth row under the control of the first scanning signal provided by the first scanning line in the 2nth row;

[0088] The nth first writing time period and the nth second writing time period at least partially overlap. BRIEF DESCRIPTION OF THE DRAWINGS

[0089] FIG1 is a circuit diagram of a display panel including a row and six columns of sub-pixels according to at least one embodiment of the present disclosure;

[0090] FIG2 is a first layout diagram of at least one embodiment of the display panel shown in FIG1 ;

[0091] 3A and 3B are layout diagrams of the semiconductor layer in FIG. 2 ;

[0092] FIG4 is a layout diagram of the first gate metal layer in FIG2 ;

[0093] FIG5 is a layout diagram of the second gate metal layer in FIG2 ;

[0094] FIG6 is a layout diagram of the first source / drain metal layer in FIG2 ;

[0095] FIG7 is a layout diagram of the second source / drain metal layer in FIG2 ;

[0096] FIG8 is a layout diagram of the first ITO layer in FIG2 ;

[0097] FIG9 is a layout diagram in FIG2 without the first ITO layer;

[0098] 10 is a schematic diagram of superimposed vias in the semiconductor layer, the first gate metal layer, the second gate metal layer, the first source / drain metal layer, and the first planar layer in FIG. 2 ;

[0099] 11 is a schematic diagram of the superposition of the semiconductor layer, the first gate metal layer, the second gate metal layer, the first source-drain metal layer, the via holes in the first planar layer, the second source-drain metal layer, and the via holes in the second planar layer in FIG. 2 .

[0100] FIG12 is a schematic diagram of the superposition of the semiconductor layer, the first gate metal layer, the second gate metal layer, and the via hole of the first insulating layer in FIG2 ;

[0101] FIG13 is a second layout diagram of at least one embodiment of the display panel shown in FIG1 ;

[0102] FIG14 is a schematic structural diagram of the first ITO layer in FIG13;

[0103] FIG15 is a layout diagram of the film layers except the second ITO layer in FIG13;

[0104] FIG16 is an enlarged schematic diagram of the first area AA1 in FIG15 ;

[0105] FIG17 is a circuit diagram of a display panel including a row and six columns of sub-pixels according to at least one embodiment of the present disclosure;

[0106] FIG18 is a schematic diagram showing a first pixel defining layer disposed on the layout diagram of the display panel shown in FIG2 ;

[0107] FIG19A is a schematic diagram showing a second pixel defining layer added to FIG18;

[0108] FIG19B is a structural diagram of a display panel according to at least one embodiment of the present disclosure;

[0109] FIG19C is a structural diagram of a display panel according to at least one embodiment of the present disclosure;

[0110] FIG19D is a structural diagram of a display panel according to at least one embodiment of the present disclosure;

[0111] FIG19E is a structural diagram of a display panel according to at least one embodiment of the present disclosure;

[0112] FIG20 is a layout diagram of the first pixel definition layer in FIG19A;

[0113] FIG21 is a schematic diagram of openings of the second pixel defining layer in FIG19A;

[0114] FIG22 is a schematic diagram of the superposition of openings in the first pixel defining layer and the second pixel defining layer according to at least one embodiment;

[0115] FIG23 is a layout diagram of the first pixel definition layer in FIG22;

[0116] FIG24 is a schematic diagram showing a first pixel defining layer disposed on the layout diagram of the display panel shown in FIG2 ;

[0117] FIG25 is a schematic diagram showing a second pixel defining layer added to FIG24;

[0118] FIG26 is a layout diagram of the first pixel definition layer in FIG25;

[0119] FIG27 is a schematic diagram of openings of the second pixel defining layer in FIG25;

[0120] FIG28 is a schematic diagram of at least one embodiment of overlapping openings of the first pixel defining layer and the second pixel defining layer in FIG25 ;

[0121] FIG29A is a cross-sectional view taken along line AA' after the light-emitting layer and the cathode layer are fabricated on the basis of FIG19A;

[0122] FIG29B is a cross-sectional view of a display panel according to at least one embodiment of the present disclosure;

[0123] FIG30 is a structural diagram of at least one embodiment of a sub-pixel in a display panel according to the present disclosure;

[0124] FIG31 is a structural diagram of at least one embodiment of a sub-pixel in a display panel according to the present disclosure;

[0125] FIG32 is a circuit diagram of at least one embodiment of a sub-pixel in a display panel according to the present disclosure;

[0126] FIG33 is an operation timing diagram of at least one embodiment of the sub-pixel shown in FIG32 ;

[0127] FIG. 34 is an operation timing diagram of at least one embodiment of the sub-pixel shown in FIG. 32 . DETAILED DESCRIPTION

[0128] The following will be combined with the accompanying drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the embodiments described are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of the present disclosure.

[0129] The transistors used in all embodiments of the present disclosure may be thin film transistors, field effect transistors, or other devices with the same characteristics. In the embodiments of the present disclosure, to distinguish the two electrodes of the transistor other than the gate, one electrode is referred to as the first electrode and the other electrode is referred to as the second electrode.

[0130] In actual operation, when the transistor is a thin film transistor or a field effect transistor, the first electrode may be a drain, and the second electrode may be a source; or, the first electrode may be a source, and the second electrode may be a drain.

[0131] The display panel according to the embodiment of the present disclosure includes a substrate and a plurality of pixel opening areas provided on the substrate, and further includes at least one planar layer and at least two conductive layers stacked on the substrate, wherein the planar layer is provided between adjacent conductive layers, and the planar layer has first-type via holes and second-type via holes;

[0132] The display panel includes a signal line for transmitting a reference voltage signal and a signal line for transmitting a power supply voltage signal;

[0133] The signal line for transmitting the reference voltage signal includes a first signal line and a second signal line; the first signal line is electrically connected to the second signal line through the first type of via;

[0134] The signal line for transmitting the power supply voltage signal includes a third signal line and a fourth signal line, and the third signal line is electrically connected to the fourth signal line through the second type of via;

[0135] The orthographic projection of the first type of via on the substrate does not overlap with the orthographic projection of the pixel opening area on the substrate;

[0136] The orthographic projection of the second-type via hole on the substrate does not overlap with the orthographic projection of the pixel opening area on the substrate.

[0137] In the display panel described in the embodiment of the present disclosure, the orthographic projections of the first type of vias possessed by the flat layer and the second type of vias possessed by the flat layer on the substrate and the orthographic projections of the pixel opening area on the substrate enable the light-emitting material layer to be arranged on a flat surface, thereby meeting the requirements of the printing process for the flatness of the substrate of the light-emitting element, increasing the stability of the light-emitting element, and avoiding the generation of Mura (uneven display).

[0138] Optionally, the reference voltage signal is a reference voltage signal and / or an initial voltage signal, and the power supply voltage signal may be a first voltage signal, but is not limited thereto.

[0139] In at least one embodiment of the present disclosure, the first voltage signal may be a high voltage signal.

[0140] In a specific implementation, when the display panel is working, current flows through the signal lines for transmitting the reference voltage signal and the signal lines for transmitting the power supply voltage signal. Therefore, the above-mentioned signal lines can adopt a mesh structure to reduce the impact of uneven voltage drop on the display; the signal lines for transmitting the reference voltage signal include a first signal line and a second signal line located in different conductive layers; the signal lines for transmitting the power supply voltage signal include a third signal line and a fourth signal line located in different conductive layers; the first signal line and the second signal line are electrically connected to each other through the first type of vias provided in the flat layer, and the third signal line and the fourth signal line are electrically connected to each other through the second type of vias provided in the flat layer. The first type of vias and the second type of vias avoid the pixel opening area, so that the light-emitting material layer is arranged on a flat surface, meeting the printing process requirements for the flatness of the substrate of the light-emitting element, increasing the stability of the light-emitting element, and avoiding the generation of Mura (uneven display).

[0141] In related technologies, a printing process can be used to manufacture light-emitting devices. This printing process requires a highly flat substrate. If the substrate is uneven or not flat enough, it will affect the light color and electrical characteristics of the light-emitting device. The end result is that the light color of the light-emitting device deviates, and the efficiency, lifespan and other characteristics of the light-emitting device will also be greatly deteriorated.

[0142] Optionally, the thickness of the planar layer may be greater than a first thickness threshold, and the first thickness threshold may be greater than or equal to 2.8 μm and less than or equal to 3.2 μm; for example, the first thickness threshold may be 3 μm.

[0143] In a specific implementation, since the thickness of the flat layer is relatively large, the vias passing through the flat layer will affect the flatness of the substrate, while the thickness of other insulating layers (such as the gate insulating layer, interlayer dielectric layer, etc.) is relatively small. Therefore, the vias passing through the other insulating layers have lower requirements for the flatness of the substrate.

[0144] In at least one embodiment of the present disclosure, when the display panel includes a first source-drain metal layer, a second source-drain metal layer, and a first ITO (indium tin oxide) layer stacked in sequence in a direction away from the substrate, a first planarization layer may be provided between the first source-drain metal layer and the second source-drain metal layer, and a second planarization layer may be provided between the second source-drain metal layer and the first ITO layer.

[0145] When the display panel further includes a second ITO layer disposed on a side of the first ITO layer away from the substrate, a third planar layer may be further disposed between the first ITO layer and the second ITO layer.

[0146] In at least one embodiment of the present disclosure, the display panel includes a first conductive layer, a second conductive layer, and a first planar layer; the first conductive layer, the first planar layer, and the second conductive layer are arranged in sequence in a direction away from the substrate; the first signal line is a first reference signal line, and the second signal line is a first reference connecting line; the first-type via includes a first via;

[0147] The first conductive layer includes the first reference signal line, the second conductive layer includes the first reference connection line; the first type of via includes a first via;

[0148] The first planar layer has the first via hole; the first reference signal line is electrically connected to the first reference connection line through the first via hole.

[0149] In a specific implementation, the first reference signal line can be a reference voltage line or an initial voltage line, the first reference connection line can be a reference voltage connection line or an initial voltage connection line, the reference voltage line is used to provide a reference voltage for the sub-pixel, the initial voltage line is used to provide an initial voltage for the sub-pixel, the reference voltage connection line and the reference voltage line are located in different layers, and the reference voltage line is electrically connected to the reference voltage line; the initial voltage connection line and the initial voltage line are located in different layers, and the initial voltage connection line is electrically connected to the initial voltage line.

[0150] In at least one embodiment of the present disclosure, when the display panel is in operation, current flows through the signal line for providing the reference voltage and the signal line for providing the initial voltage. Therefore, a mesh structure is adopted to reduce the impact of uneven voltage drop on the display; and the first conductive layer includes the first reference signal line, the second conductive layer includes the first reference connecting line, and a first flat layer is provided between the first conductive layer and the second conductive layer. The first flat layer has a first via, and the first reference signal line and the first reference connecting line are electrically connected through the first via. Since the first reference signal line and the first reference connecting line need to be electrically connected through the first via of the first flat layer, for the printing process, the position of the first via needs to be isolated from the pixel opening area to avoid affecting the display. Based on this, the first reference connecting line can be set at the center of the pixel, and the first via can be set to avoid the pixel opening area to reduce the impact of the via of the flat layer on the display.

[0151] Optionally, the first conductive layer may be a first source-drain metal layer, and the second conductive layer may be a second source-drain metal layer; the first reference connection line may extend along a first direction, and the first reference signal line may extend along a second direction; the first direction may be a vertical direction, and the second direction may be a horizontal direction.

[0152] In a specific implementation, a first flat layer and a first passivation layer may be provided between the first source-drain metal layer and the second source-drain metal layer. The first flat layer serves to increase the thickness between the first source-drain metal layer and the second source-drain metal layer, thereby reducing the parasitic capacitance of the wiring and meeting the driving requirements of large-size loads.

[0153] In at least one embodiment of the present disclosure, the display panel further includes a third conductive layer; the first conductive layer includes a second reference signal line; the third conductive layer includes a second reference connecting line; and the second reference signal line is electrically connected to the second reference connecting line.

[0154] The third conductive layer is disposed between the substrate and the first conductive layer;

[0155] The first reference connection line and the second reference connection line both extend along a first direction;

[0156] The orthographic projections of the two second reference connection lines on the substrate are arranged on two opposite sides of the orthographic projection of the first reference connection line on the substrate.

[0157] In a specific implementation, when the first reference signal line is a reference voltage line and the first reference connection line is a reference voltage connection line, the second reference signal line may be an initial voltage line and the second reference connection line may be an initial voltage connection line;

[0158] When the first reference signal line is an initial voltage line and the first reference connection line is an initial voltage connection line, the second reference signal line may be a reference voltage line and the second reference connection line may be a reference voltage connection line.

[0159] In at least one embodiment of the present disclosure, the orthographic projection of the second reference connection line on the substrate may be adjacent to the orthographic projection of the first reference connection line on the substrate.

[0160] Optionally, the third conductive layer can be a first gate metal layer; the first conductive layer can be a first source and drain metal layer; the third conductive layer includes a second reference connection line, and the first conductive layer includes a second reference signal line; the second reference signal line and the second reference connection line are located in different layers, and the second reference signal line and the second reference connection line are electrically connected through a via.

[0161] In at least one embodiment of the present disclosure, since the second reference connection line is located in the first gate metal layer and the block resistance Rs of the first gate metal layer is relatively large, it is necessary to use a second reference connection line arranged on two opposite sides of the first reference connection line (the first reference connection line and the second reference connection line are located in different layers), and the first reference connection line is arranged in the center of the pixel. This type of wiring can solve the problem of the via in the flat layer affecting the pixel opening area, while also avoiding the risk of short circuit between the first reference connection line and the second reference connection line.

[0162] In specific implementation, since in the Ltps-ntype (low-temperature polycrystalline silicon-n-type) process, the gate metal layer can only adopt the Mo (molybdenum)-Al (aluminum)-Mo structure, the square resistance Rs of the gate metal layer is large and cannot meet the requirements of large-size driving loads. At least one embodiment of the present disclosure adopts a source-drain metal layer (the source-drain metal layer can, for example, adopt a Ti (titanium)-Al-Ti structure) to make a scanning line, a light-emitting control line and a voltage signal line. The scanning line and the light-emitting control line are electrically connected to the gate of the transistor in the sub-pixel through a via.

[0163] In at least one embodiment of the present disclosure, the display panel includes a first conductive layer, a second conductive layer, and a first planar layer; the first conductive layer, the first planar layer, and the second conductive layer are arranged in sequence in a direction away from the substrate; the third signal line is a first voltage line, and the fourth signal line is a first voltage connection line; the second-type via includes a second via;

[0164] The first conductive layer includes the first voltage line, and the second conductive layer includes the first voltage connection line;

[0165] The first planar layer has the second via hole; the first voltage line is electrically connected to the first voltage connection line through the second via hole.

[0166] In a specific implementation, the first conductive layer can be a first source-drain metal layer, the second conductive layer can be a second source-drain metal layer, the first conductive layer can include a first voltage line extending along the second direction, the second conductive layer can include a first voltage connection line extending along the first direction, the first voltage line is electrically connected to the first voltage connection line through a second via hole provided in the first flat layer, and the second via hole avoids the pixel opening area, thereby reducing the impact of the via hole provided in the flat layer on the display.

[0167] Optionally, the first voltage line may be a high voltage line, which may be used to directly provide a high voltage signal to the sub-pixel, and the first voltage connection line is electrically connected to the first voltage line.

[0168] In embodiments of the present disclosure, signal lines for providing a reference voltage, signal lines for providing an initial voltage, and voltage lines for providing a high-voltage signal require current to flow during the compensation, reset, and light-emitting phases. To maintain signal integrity, these lines must be routed using a conductive layer with a low Rs. In at least one embodiment of the present disclosure, the first and second source / drain metal layers have a low Rs.

[0169] Optionally, the light-emitting element in the sub-pixel may be an organic light-emitting diode, but is not limited thereto. In actual operation, the light-emitting element may also be other types of light-emitting diodes. In at least one embodiment of the present disclosure, the display panel includes a plurality of sub-pixels disposed on the substrate; the sub-pixels include light-emitting elements;

[0170] The display panel includes a second conductive layer, an anode planarization layer, and a fourth conductive layer stacked in a direction away from the substrate; the fourth conductive layer includes an anode of the light-emitting element;

[0171] The thickness of the anode planarization layer is greater than that of the planarization layer.

[0172] Optionally, the fourth conductive layer may be a first ITO (indium tin oxide) layer, the second conductive layer may be a second source / drain metal layer, and a thicker anode planarization layer may be provided between the second conductive layer and the fourth conductive layer to improve the flatness of the substrate of the light-emitting element;

[0173] The thickness of the anode planarization layer is greater than that of the planarization layer.

[0174] For example, the thickness of the anode planarization layer may be greater than a second thickness threshold;

[0175] The second thickness threshold may be greater than or equal to 3.5 μm and less than or equal to 4 μm, but is not limited thereto.

[0176] FIG. 1 is a circuit diagram of a display panel including one row and six columns of sub-pixels according to at least one embodiment of the present disclosure.

[0177] As shown in FIG1 , the first sub-pixel P1 located in the first column includes an organic light emitting diode O1 , a storage capacitor C1 , a first reset transistor T3 , a data writing transistor T2 , a second reset transistor T1 , a driving transistor T0 , and a light emitting control transistor T4 ;

[0178] The gate of the first reset transistor T3 is electrically connected to the third scan line G3, the first electrode of the first reset transistor T3 is electrically connected to the anode of the organic light emitting diode O1, and the second electrode of the first reset transistor T3 is electrically connected to the initial voltage line I1;

[0179] The anode of the organic light emitting diode O1 is electrically connected to the first electrode of the storage capacitor C1; the second electrode of the storage capacitor C1 is electrically connected to the second electrode of the data writing transistor T2;

[0180] The gate of the data writing transistor T2 is electrically connected to the first scan line G1, and the first electrode of the data writing transistor T2 is electrically connected to the first column data line DA1;

[0181] The gate of the second reset transistor T1 is electrically connected to the second scan line G2, the first electrode of the second reset transistor T1 is electrically connected to the reference voltage line REF, and the second electrode of the second reset transistor T1 is electrically connected to the second electrode of the data writing transistor T2;

[0182] The gate of the driving transistor T0 is electrically connected to the second plate of the storage capacitor, the first electrode of the driving transistor T0 is electrically connected to the anode of the organic light emitting diode O1, and the second electrode of the driving transistor T0 is electrically connected to the first electrode of the light emitting control transistor T4;

[0183] A gate of the light emission control transistor T4 is electrically connected to the light emission control line EM, and a second voltage of the light emission control transistor T4 is electrically connected to the high voltage line VDD.

[0184] In at least one embodiment shown in FIG. 1 , the light-emitting element is an organic light-emitting diode.

[0185] In at least one embodiment shown in FIG1 , the transistors in the sub-pixel are n-type LTPS (low temperature polysilicon) transistors. Since n-type LTPS transistors have a large leakage current, T1 , T2 , and T3 can all adopt a dual-channel series architecture.

[0186] In FIG1 and FIG2, the data line labeled DA2 is the second column, the data line labeled DA3 is the third column, the data line labeled DA4 is the fourth column, the data line labeled DA5 is the fifth column, and the data line labeled DA6 is the sixth column;

[0187] The line labeled VDL1 is a first high voltage connection line, the line labeled VDL2 is a second high voltage connection line, the line labeled IL1 is a first initial voltage connection line, the line labeled IL2 is a second initial voltage connection line, and the line labeled RL1 is a first reference voltage connection line.

[0188] As shown in FIG1 , the first pixel unit includes a first sub-pixel P1, a second sub-pixel P2, and a third sub-pixel P3 arranged sequentially from left to right, and the second pixel unit includes a fourth sub-pixel P4, a fifth sub-pixel P5, and a sixth sub-pixel P6 arranged sequentially from left to right;

[0189] The first pixel unit and the second pixel unit form a pixel module;

[0190] The first reference voltage connection line RL1, the first initial voltage connection line IL1 and the second initial voltage connection line IL2 are all disposed between the first pixel unit and the second pixel unit;

[0191] The first reference voltage connection line RL1 is disposed in the middle of the pixel module, IL1 is disposed on the left side of RL1, and IL2 is disposed on the right side of RL1; IL1 is adjacent to RL1, and IL2 is adjacent to RL1.

[0192] In at least one embodiment shown in FIG. 1 , P1 and P4 may be red sub-pixels, P2 and P5 may be green sub-pixels, and P3 and P6 may be blue sub-pixels.

[0193] In at least one embodiment of the present disclosure, P2 and P5 may also be replaced by blue sub-pixels, and P3 and P6 may also be replaced by green sub-pixels.

[0194] In at least one embodiment shown in FIG. 1 , IL1 and IL2 may be located in the first gate metal layer, RL1 may be located in the second source / drain metal layer, and REF, G2, G1, EM, VDD, G3, and I1 may be located in the first source / drain metal layer.

[0195] REF, G2, G1, EM, VDD, G3, and I1 can extend in the horizontal direction;

[0196] VDL1, DA1, DA2, DA3, IL1, RL1, IL2, DA4, DA5, DA6 and VDL2 all extend in the vertical direction.

[0197] In FIG1 , the first sub-pixel is labeled P1, the second sub-pixel is labeled P2, the third sub-pixel is labeled P3, the fourth sub-pixel is labeled P4, the fifth sub-pixel is labeled P5, and the sixth sub-pixel is labeled P6.

[0198] FIG. 2 is a first layout diagram of at least one embodiment of the display panel shown in FIG. 1 .

[0199] Figures 3A and 3B are layout diagrams of the semiconductor layer in Figure 2, Figure 4 is a layout diagram of the first gate metal layer in Figure 2, Figure 5 is a layout diagram of the second gate metal layer in Figure 2, Figure 6 is a layout diagram of the first source and drain metal layer in Figure 2, Figure 7 is a layout diagram of the second source and drain metal layer in Figure 2, and Figure 8 is a layout diagram of the first ITO layer in Figure 2.

[0200] In Figure 2, the anode of the organic light-emitting diode in the first sub-pixel is labeled AD1, the anode of the organic light-emitting diode in the second sub-pixel is labeled AD2, the anode of the organic light-emitting diode in the third sub-pixel is labeled AD3, the anode of the organic light-emitting diode in the fourth sub-pixel is labeled AD4, the anode of the organic light-emitting diode in the fifth sub-pixel is labeled AD5, and the anode of the organic light-emitting diode in the sixth sub-pixel is labeled AD6.

[0201] FIG. 9 is a layout diagram in which the first ITO layer is not provided in FIG. 2 .

[0202] In FIG. 3A , the active pattern labeled A3 is the first reset transistor T3 , the active pattern labeled A2 is the data writing transistor T2 , and the active pattern labeled A1 is the second reset transistor T1 .

[0203] In FIG. 3B , S2 is the first electrode of the data writing transistor T2 , and S3 is the first electrode of the first reset transistor T3 .

[0204] In Figure 4, the first plate portion of the second plate of the storage capacitor C1 is labeled C1b1, and in Figure 6, the second plate portion of the second plate of the storage capacitor C1 is labeled C1b2. The second plate of the storage capacitor C1 includes a first plate portion C1b1 and a second plate portion C1b2 electrically connected to each other through a via.

[0205] In FIG. 5 , the first plate of the storage capacitor C1 is labeled C1a.

[0206] As shown in FIG. 2 to FIG. 12 , the first reference voltage connection line RL1 is electrically connected to the reference voltage line REF through a first via H1 ;

[0207] The first reference voltage connection line RL1 is located in the second source-drain metal layer, the reference voltage line REF is located in the first source-drain metal layer, the first via hole H1 is a via hole in the first planar layer, and the first via hole H1 avoids the pixel opening area.

[0208] As shown in FIG2 to FIG12 , the first high voltage connection line VDL1 is electrically connected to the high voltage line VDD through the first second via H12 ;

[0209] The second high voltage connection line VDL2 is electrically connected to the high voltage line VDD through the second second via hole H22;

[0210] VDL1 and VDL2 are located in the second source-drain metal layer, and VDD is located in the first source-drain metal layer; H12 and H22 are via holes in the first planar layer, and H12 and H22 avoid the pixel opening area.

[0211] In at least one embodiment of the present disclosure, the planar layer may have a third type of via hole;

[0212] The display panel includes a plurality of sub-pixels arranged on the substrate; the sub-pixels include a light-emitting element, a storage capacitor and a plurality of transistors;

[0213] The sub-pixel includes a plurality of conductive parts, and the plurality of conductive parts include an anode of a light-emitting element, a plate of a storage capacitor, and an electrode of the transistor;

[0214] Some of the plurality of conductive parts are electrically connected through the third type of vias;

[0215] The orthographic projection of the third type of via hole on the substrate does not overlap with the orthographic projection of the pixel opening area on the substrate.

[0216] In a specific implementation, the anode of the light-emitting element and part of the electrodes of some transistors in the sub-pixel can be electrically connected through the third type of via provided by the planar layer, and the anode of the light-emitting element and one plate of the storage capacitor can be electrically connected through the third type of via provided by the planar layer. The third type of via avoids the pixel opening area, so that the light-emitting material layer is arranged on a flat surface, meeting the requirements of the printing process for the flatness of the substrate of the light-emitting element, increasing the stability of the light-emitting element, and avoiding the generation of Mura (uneven display).

[0217] In at least one embodiment of the present disclosure, the planar layer has a fourth type of via hole;

[0218] The display panel includes a plurality of data lines and a plurality of sub-pixels arranged on the substrate;

[0219] Part of the electrodes of part of the transistors in the sub-pixel are electrically connected to the data line through the fourth type of via hole;

[0220] The orthographic projection of the fourth type of via hole on the substrate does not overlap with the orthographic projection of the pixel opening area on the substrate.

[0221] In a specific implementation, part of the electrodes of some transistors in the sub-pixels are electrically connected to the data lines through the fourth type of vias provided in the flat layer. The fourth type of vias avoid the pixel opening area, so that the light-emitting material layer is arranged on a flat surface, meeting the requirements of the printing process for the flatness of the substrate of the light-emitting element, increasing the stability of the light-emitting element, and avoiding the generation of Mura (uneven display).

[0222] In at least one embodiment of the present disclosure, the via holes of each planar layer may avoid the pixel opening area to improve the flatness of the substrate of the light-emitting element, but the present invention is not limited thereto. In actual operation, at least some of the via holes of each planar layer avoid the pixel opening area.

[0223] Optionally, the display panel includes a plurality of sub-pixels disposed on the substrate; the sub-pixels include a first reset transistor; and the third type of via hole includes a third via hole and a fourth via hole;

[0224] The display panel further includes a semiconductor layer, a first conductive layer, a first planar layer, a second conductive layer, a second planar layer, and a fourth conductive layer sequentially arranged in a direction away from the substrate; the semiconductor layer includes a first electrode of the first reset transistor, and the fourth conductive layer includes an anode of the light-emitting element; the first planar layer has the third via hole, and the second planar layer has the fourth via hole;

[0225] The first electrode of the first reset transistor is electrically connected to the anode of the light emitting element through the third via hole and the fourth via hole.

[0226] In a specific implementation, the first conductive layer may be a first source-drain metal layer, the second conductive layer may be a second source-drain metal layer, and the fourth conductive layer may be a first ITO (indium tin oxide) layer. A first planar layer is provided between the first source-drain metal layer and the second source-drain metal layer, and a second planar layer is provided between the second source-drain metal layer and the first ITO layer. The first electrode of the first reset transistor is located in the semiconductor layer, and the anode of the light-emitting element may be located in the first ITO layer. The first electrode of the first reset transistor is electrically connected to the anode of the light-emitting element through a third via hole in the first planar layer, and a fourth via hole in the second planar layer. The third and fourth via holes avoid the pixel opening area, thereby reducing the impact of the via holes in the planar layer on the display.

[0227] In at least one embodiment of the present disclosure, a second passivation layer and a second flattening layer may be provided between the second source / drain metal layer and the first ITO layer. The second flattening layer serves to increase the thickness between the second source / drain metal layer and the first ITO layer and reduce the parasitic capacitance of the wiring, thereby meeting the driving requirements of large-size loads.

[0228] 10 is a schematic diagram of superimposed vias in the semiconductor layer, the first gate metal layer, the second gate metal layer, the first source / drain metal layer, and the first planar layer in FIG. 2 ;

[0229] 11 is a schematic diagram of the superposition of the semiconductor layer, the first gate metal layer, the second gate metal layer, the first source-drain metal layer, the via holes in the first planar layer, the second source-drain metal layer, and the via holes in the second planar layer in FIG. 2 .

[0230] FIG12 is a schematic diagram of superposition of the semiconductor layer, the first gate metal layer, the second gate metal layer, and the via holes in the first insulating layer (the first insulating layer may be an interlayer dielectric layer) in FIG2 .

[0231] In FIG10 , the via hole labeled H3 is the third via hole, and in FIG11 , the via hole labeled H4 is the fourth via hole;

[0232] As shown in FIG. 1 to FIG. 11 , the first electrode S3 of the first reset transistor is electrically connected to the anode AD1 of the organic light emitting diode in the first sub-pixel through the third via hole H3 and the fourth via hole H4 .

[0233] In at least one embodiment of the present disclosure, the third type of vias includes a fifth via and a sixth via;

[0234] The display panel further includes a fifth conductive layer, a first insulating layer, a first conductive layer, a first flat layer, a second conductive layer, a second flat layer, and a fourth conductive layer, which are sequentially arranged in a direction away from the substrate;

[0235] The fourth conductive layer includes the anode of the light-emitting element; the fifth conductive layer includes the first plate of the storage capacitor;

[0236] The first flat layer has the fifth via hole, and the second flat layer has the sixth via hole;

[0237] The anode of the light emitting element is electrically connected to the first plate of the storage capacitor through the sixth via hole, the fifth via hole, and a via hole penetrating the first insulating layer.

[0238] In a specific implementation, the fifth conductive layer may be a second gate metal layer, the first insulating layer may be a first insulating layer (the first insulating layer may be an interlayer dielectric layer), the first conductive layer may be a first source-drain metal layer, the second conductive layer may be a second source-drain metal layer, the fourth conductive layer may be a first ITO layer, an interlayer dielectric layer may be provided between the second gate metal layer and the first source-drain metal layer, a first flat layer may be provided between the first source-drain metal layer and the second source-drain metal layer, and a second flat layer may be provided between the second source-drain metal layer and the first ITO layer. The anode of the light-emitting element may be located in the first ITO layer, and the first plate of the storage capacitor may be located in the second gate metal layer. The anode of the light-emitting element may be electrically connected to the first plate of the storage capacitor through the sixth via provided in the second flat layer, the fifth via provided in the first flat layer, and the first connection via that passes through the first insulating layer. The fifth via and the sixth via avoid the pixel opening area to reduce the influence of the vias provided in the flat layer on the display.

[0239] In FIG. 10 , the via hole labeled H5 is the fifth via hole, in FIG. 11 , the via hole labeled H6 is the sixth via hole, and in FIG. 12 , the via hole labeled HL1 is the first connection via hole.

[0240] As shown in FIG. 1 to FIG. 12 , the anode AD1 of the organic light emitting diode in the first sub-pixel is electrically connected to the first plate C1 a of the storage capacitor through the sixth via H6 , the fifth via H5 , and the first connection via HL1 .

[0241] In at least one embodiment of the present disclosure, the sub-pixel includes a data writing transistor; the fourth type of via hole includes a seventh via hole;

[0242] The display panel further includes a semiconductor layer, a first conductive layer, a first planar layer, and a second conductive layer sequentially arranged in a direction away from the substrate;

[0243] The semiconductor layer includes a first electrode of the data writing transistor, and the second conductive layer includes the data line;

[0244] The first planar layer has the seventh via hole, and the first electrode of the data writing transistor is electrically connected to the data line through the seventh via hole.

[0245] In a specific implementation, the first conductive layer may be a first source-drain metal layer, the second conductive layer may be a second source-drain metal layer, a first planar layer is provided between the first source-drain metal layer and the second source-drain metal layer, the first electrode of the data write transistor is located in the semiconductor layer, the data line is located in the second source-drain metal layer, and the first electrode of the data write transistor is electrically connected to the data line via a seventh via hole in the first planar layer. The seventh via hole avoids the pixel opening area to reduce the impact of the via hole in the planar layer on the display

[0246] In FIG. 10 , the via hole labeled H7 is the seventh via hole.

[0247] As shown in FIG. 1 to FIG. 10 , the first electrode S1 of the data writing transistor is electrically connected to the first data line DA1 through the seventh via hole H7 .

[0248] Optionally, the sub-pixel includes a first reset transistor; the third type of via hole includes a third via hole, a fourth via hole and an eighth via hole;

[0249] The display panel further includes a semiconductor layer, a first conductive layer, a first planar layer, a second conductive layer, a second planar layer, a fourth conductive layer, a third planar layer, and a sixth conductive layer, which are sequentially arranged in a direction away from the substrate;

[0250] The semiconductor layer includes the first electrode of the first reset transistor, and the sixth conductive layer includes the anode of the light-emitting element; the first flat layer has the third via hole, the second flat layer has the fourth via hole, and the third flat layer has the eighth via hole;

[0251] The first electrode of the first reset transistor is electrically connected to the anode of the light emitting element through the third via hole, the fourth via hole, and the eighth via hole.

[0252] In a specific implementation, the first conductive layer may be a first source-drain metal layer, the second conductive layer may be a second source-drain metal layer, the fourth conductive layer may be a first ITO layer, the sixth conductive layer may be a second ITO layer, a first flat layer may be provided between the first source-drain metal layer and the second source-drain metal layer, a second flat layer may be provided between the second source-drain metal layer and the first ITO layer, a third flat layer may be provided between the first ITO layer and the second ITO layer, the first electrode of the first reset transistor may be located in the semiconductor layer, the anode of the light-emitting element may be located in the second ITO layer, the first electrode of the first reset transistor may be electrically connected to the anode of the light-emitting element through a third via hole in the first flat layer, a fourth via hole in the second flat layer, and an eighth via hole in the third flat layer, the third via hole, the fourth via hole and the eighth via hole avoid the pixel opening area, so as to reduce the influence of the via holes in the flat layer on the display.

[0253] FIG. 13 is a second layout diagram of at least one embodiment of the display panel shown in FIG. 1 .

[0254] In at least one embodiment of the display panel shown in FIG13 , a semiconductor layer, a first gate metal layer, a second gate metal layer, a first source / drain metal layer, a second source / drain metal layer, a first ITO layer, and a second ITO layer are sequentially stacked along a side away from the substrate.

[0255] A first insulating layer is arranged between the second gate metal layer and the first source / drain metal layer, a first flattening layer is arranged between the first source / drain metal layer and the second source / drain metal layer, a second flattening layer is arranged between the second source / drain metal layer and the first ITO layer, and a third flattening layer is arranged between the first ITO layer and the second ITO layer.

[0256] The structure of the semiconductor layer in Figure 13 is shown in Figure 3A, the structure of the first gate metal layer in Figure 13 is shown in Figure 4, the structure of the second gate metal layer in Figure 13 is shown in Figure 5, the structure of the first source and drain metal layer in Figure 13 is shown in Figure 6, the structure of the second source and drain metal layer in Figure 13 is shown in Figure 7, the structure of the first ITO layer in Figure 13 is shown in Figure 14, and the structure of the second ITO layer in Figure 13 is shown in Figure 8.

[0257] FIG. 15 is a layout diagram of the film layers excluding the second ITO layer in FIG. 13 .

[0258] The second layout diagram shown in FIG13 differs from the second layout diagram shown in FIG2 in that: it has two ITO layers: a first ITO layer and a second ITO layer;

[0259] The second ITO layer comprises an anode of the light emitting element;

[0260] The first ITO layer includes a first conductive pattern DX1.

[0261] As shown in Figures 13, 10, 11 and 15, as well as Figures 3A to 7, the first electrode S3 of the first reset transistor can be electrically connected to the anode AD1 of the organic light emitting diode in the first sub-pixel through the third via hole H3 of the first flat layer, the fourth via hole H4 of the second flat layer, and the eighth via hole H8 of the third flat layer.

[0262] In specific implementation, in order to improve the impact of the printing flatness effect of the pixel opening area on the printing device, at least one embodiment of the present disclosure adds a third flat layer and a second ITO layer (due to the addition of a flat layer, the printing flatness effect of the pixel opening area is better), and the anode of the light-emitting element is set to be located in the second ITO layer. The first ITO layer includes a first conductive pattern DX1. The anode of the light-emitting element is electrically connected to the first electrode of the first reset transistor through the first conductive pattern DX1. The anode of the light-emitting element is a reflective anode. Since there is a film layer wiring of the second source and drain metal layer at the opening, the third flat layer is used for flattening, which improves the problem of uneven printing caused by the film layer wiring of the second source and drain metal layer; the eighth via of the third flat layer avoids the pixel opening area, while improving the printing flattening, it has no effect on the size of the pixel opening area.

[0263] FIG. 16 is an enlarged schematic diagram of the first area AA1 in FIG. 15 .

[0264] In FIG. 16 , the eighth via hole is labeled H8 , the ninth via hole is labeled H9 , and the first conductive pattern is labeled DX1 .

[0265] In at least one embodiment of the present disclosure, the third type of vias includes a fifth via, a sixth via, and a ninth via;

[0266] The display panel further includes a fifth conductive layer, a first insulating layer, a first conductive layer, a first flat layer, a second conductive layer, a second flat layer, a fourth conductive layer, a third flat layer, and a sixth conductive layer, which are sequentially arranged in a direction away from the substrate;

[0267] The sixth conductive layer includes the anode of the light-emitting element, and the fifth conductive layer includes the first plate of the storage capacitor;

[0268] The first flat layer has the fifth via hole, the second flat layer has the sixth via hole, and the third flat layer has the ninth via hole;

[0269] The anode of the light-emitting element is electrically connected to the first plate of the storage capacitor through the ninth via hole, the sixth via hole, the fifth via hole, and a via hole penetrating the first insulating layer.

[0270] In a specific implementation, the fifth conductive layer can be a second gate metal layer, the first conductive layer can be a first source-drain metal layer, the second conductive layer can be a second source-drain metal layer, the fourth conductive layer can be a first ITO layer, the sixth conductive layer can be a second ITO layer, the anode of the light-emitting element can be located in the second ITO layer, the second plate of the storage capacitor can be located in the second gate metal layer, the anode of the light-emitting element can be electrically connected to the first plate of the storage capacitor through the ninth via hole of the third flat layer, the sixth via hole of the second flat layer, the fifth via hole of the first flat layer, and the first connecting via hole passing through the first insulating layer, the ninth via hole, the sixth via hole and the fifth via hole avoid the pixel opening area, thereby reducing the influence of the via holes of the flat layer on the display.

[0271] As shown in Figures 13, 10, 11, 12 and 15, as well as Figures 3A to 7, the anode AD1 of the organic light emitting diode in the first sub-pixel is electrically connected to the first plate C1a of the storage capacitor through the ninth via hole H9, the sixth via hole H6, the fifth via hole H5, and the first connection via hole HL1 that passes through the first insulating layer.

[0272] In at least one embodiment of the present disclosure, the plurality of sub-pixels are divided into a plurality of pixel units arranged in an array; the pixel unit includes a plurality of sub-pixels arranged along a second direction; the first direction intersects the second direction;

[0273] N columns of the pixel units are arranged between two adjacent columns of the first reference connection lines; N is an integer greater than 1.

[0274] Optionally, the first direction may be a vertical direction, and the second direction may be a horizontal direction.

[0275] In a specific implementation, the pixel unit may include a plurality of sub-pixels arranged in a horizontal direction. For example, the pixel unit may include red sub-pixels, green sub-pixels and blue sub-pixels arranged in sequence along the horizontal direction. Every two columns of pixel units constitute a pixel unit column, and the first reference connection line is located between a first column of pixel units included in the pixel unit column and a second column of pixel units included in the pixel unit column; that is, the first column of pixel units and the second column of pixel units constitute a first pixel unit column, and the third column of pixel units and the fourth column of pixel units constitute a second pixel unit column. A first column of first reference connection lines is arranged between the first column of pixel units and the second column of pixel units, a second column of first reference connection lines is arranged between the third column of pixel units and the fourth column of pixel units, and no first reference connection line is arranged between the second column of pixel units and the third column of pixel units.

[0276] In at least one embodiment of the present disclosure, the display panel further comprises a lens group of multiple rows and columns arranged on a side of the pixel unit away from the substrate; the lens group comprises an odd number of lenses;

[0277] The N pixel units located in the same row and arranged between two adjacent columns of first reference connection lines correspond to the same lens group.

[0278] In a specific implementation, the display panel also includes a multi-row and multi-column lens group arranged on a side of the pixel unit away from the substrate, and the N pixel units located in the same row between two adjacent columns of first reference connection lines correspond to the same lens group, and the lens group may include an odd number of lenses.

[0279] In at least one embodiment of the present disclosure, pixel units disposed between two different adjacent columns of first reference connection lines correspond to different lens groups.

[0280] In a specific implementation, the pixel units between two different adjacent columns of first reference connection lines correspond to different lens groups.

[0281] Optionally, the lens may be a 3D lens.

[0282] For example, when a first column of pixel units and a second column of pixel units are arranged between the first column of first reference connecting lines and the second column of first reference connecting lines, and a third column of pixel units and a fourth column of pixel units are arranged between the second column of first reference connecting lines and the third column of first reference connecting lines, the first column of first reference connecting lines and the second column of first reference connecting lines are two adjacent columns of first reference connecting lines of the first group, the second column of first reference connecting lines and the third column of first reference connecting lines are two adjacent columns of first reference connecting lines of the second group, the adjacent two columns of first reference connecting lines of the first group and the adjacent two columns of first reference connecting lines of the second group are different adjacent two columns of first reference connecting lines, the first pixel unit column includes the first column of pixel units and the second column of pixel units, the second pixel unit column includes the third column of pixel units and the fourth column of pixel units, and the pixel units located in the same row in the first column of pixel units and the second pixel unit column correspond to different lens groups.

[0283] In at least one embodiment of the present disclosure, the display panel includes a plurality of sub-pixels disposed on the substrate; the sub-pixels include light-emitting elements; the light-emitting elements include a light-emitting layer;

[0284] The light-emitting layers of the light-emitting elements in the sub-pixels located in the same column are continuous with each other and have the same color.

[0285] In a specific implementation, the light-emitting layers of the light-emitting elements in the sub-pixels in the same column are continuous in color.

[0286] Optionally, the sub-pixel includes a light-emitting element, a storage capacitor, a first reset transistor, a data writing transistor, and a second reset transistor;

[0287] The active pattern of the second reset transistor is electrically connected to the active pattern of the data writing transistor through a first connection line; the active pattern of the data writing transistor is electrically connected to the second plate of the storage capacitor through a second connection line;

[0288] The anode of the light emitting element is electrically connected to the active pattern of the first reset transistor via a third connecting line;

[0289] The first connection line, the second connection line and the third connection line are arranged on the same layer as the active pattern.

[0290] As shown in FIG3A , and FIG2 , FIG4 - FIG12 , the active pattern A1 of the second reset transistor is connected to the active pattern S2 of the data writing transistor through the first connection line L1 ;

[0291] The active pattern S2 of the data writing transistor is electrically connected to the second plate of the storage capacitor via the second connection line L2;

[0292] The anode AD1 of the organic light emitting diode in the first sub-pixel is electrically connected to the active pattern A3 of the first reset transistor through the third connection line L3.

[0293] As shown in FIG3A , the first connection line L1 , the second connection line L2 and the third connection line L3 are all located in the semiconductor layer, and the semiconductor layer is used as a long conductive line to enter the sub-pixel.

[0294] In practice, n-type LTPS (low-temperature polysilicon) transistors have relatively high leakage currents, which can easily cause screen flickering when the sub-pixels in the display panel emit light for extended periods of time. Since the semiconductor layer has relatively high resistance, positioning the first, second, and third connecting lines within the semiconductor layer can reduce leakage currents and improve display quality.

[0295] In at least one embodiment of the present disclosure, the position of the reference voltage connection line and the position of the initial voltage connection line may be interchanged.

[0296] As shown in FIG17 , the first reference voltage connection line RL1 and the second reference voltage connection line RL2 extend in a vertical direction, and the initial voltage connection line IL extends in a vertical direction;

[0297] The initial voltage connection line IL is electrically connected to the initial voltage line I1, RL1 is electrically connected to the reference voltage line REF, and RL2 is electrically connected to the reference voltage line REF;

[0298] The initial voltage connection line IL is set between two columns of pixel units and does not affect the display of the pixel opening area;

[0299] RL1 is set on the left side of IL, and RL2 is set on the right side of IL. RL1 is adjacent to IL, and RL2 is adjacent to IL. The reference voltage connection line uses two wirings of the first gate metal layer to reduce resistance.

[0300] In at least one embodiment shown in Figure 17, the first reference voltage connection line RL1 and the second reference voltage connection line RL2 can be located in the first gate metal layer, the initial voltage connection line IL can be located in the second source and drain metal layer, and the reference voltage line REF and the initial voltage line I1 can be located in the first source and drain metal layer.

[0301] Through the layout design in at least one embodiment of the present disclosure, the signal line RC (resistance-capacitance) loading wiring is optimized while being compatible with the flatness requirements of the printing process, making it compatible with large-size loads, printing processes and variable frequency refresh requirements, and providing technical support for large-size high PPI (pixel density) internal compensation display products.

[0302] In at least one embodiment of the present disclosure, the display panel includes a first pixel defining layer and a second pixel defining layer;

[0303] The second pixel defining layer forms a plurality of openings arranged along the second direction, and the openings extend along the first direction;

[0304] The first pixel defining layer includes a plurality of pixel defining parts arranged along a first direction, the pixel defining parts filling a portion of the openings, and the plurality of pixel defining parts defining a plurality of pixel opening areas in the plurality of openings.

[0305] Optionally, the pixel defining portion includes an integral structure extending along the second direction; or,

[0306] The pixel defining portion includes a plurality of pixel defining patterns arranged along the second direction, and at least a portion of the pixel defining patterns is filled in the corresponding openings.

[0307] FIG. 18 is a schematic diagram showing a first pixel defining layer disposed on the layout diagram of the display panel shown in FIG. 2 .

[0308] In Figure 18, the first pixel-defining graphic is labeled PL11, the second pixel-defining graphic is labeled PL12, the third pixel-defining graphic is labeled PL13, the fourth pixel-defining graphic is labeled PL14, the fifth pixel-defining graphic is labeled PL15, and the sixth pixel-defining graphic is labeled PL16.

[0309] A pixel defining material is disposed within each pixel defining pattern.

[0310] As shown in FIG19A , after the first pixel defining layer is formed, the second pixel defining layer may be formed;

[0311] In FIG19A , K1 is the first opening, K2 is the second opening, K3 is the third opening, K4 is the fourth opening, K5 is the fifth opening, and K6 is the sixth opening;

[0312] forming a pixel defining material at locations other than the openings;

[0313] K1, K2, K3, K4, K5 and K6 are arranged in the horizontal direction.

[0314] K1 , K2 , K3 , K4 , K5 , and K6 extend in the vertical direction.

[0315] As shown in FIG19A , the second pixel defining layer forms a first opening K1 , a second opening K2 , a third opening K3 , a fourth opening K4 , a fifth opening K5 and a sixth opening K6 arranged in a horizontal direction;

[0316] The first opening K1, the second opening K2, the third opening K3, the fourth opening K4, the fifth opening K5 and the sixth opening K6 extend in the vertical direction;

[0317] The first pixel defining layer includes a first pixel defining pattern PL1, a second pixel defining pattern PL2, a third pixel defining pattern PL3, a fourth pixel defining pattern PL4, a fifth pixel defining pattern PL5 and a sixth pixel defining pattern PL6;

[0318] PL1 fills part of K1, PL2 fills part of K2, PL3 fills part of K3, PL4 fills part of K4, PL5 fills part of K5, and PL6 fills part of K6. Each pixel defining portion defines a pixel opening area in each opening.

[0319] FIG20 is a layout diagram of the first pixel defining layer in FIG19A , and FIG21 is a schematic diagram of openings of the second pixel defining layer in FIG19A .

[0320] As shown in FIG. 20 , PL1 , PL2 , PL3 , PL4 , PL5 , and PL6 may be included in the first pixel defining portion PB1 .

[0321] As shown in FIG19B , in at least one embodiment of the present disclosure, the display panel includes a first pixel opening area PK1, a second pixel opening area PK2, a third pixel opening area PK3, a fourth pixel opening area PK4, a fifth pixel opening area PK5, a sixth pixel opening area PK6, a seventh pixel opening area PK7, an eighth pixel opening area PK8, a ninth pixel opening area PK9, a tenth pixel opening area PK10, an eleventh pixel opening area PK11, and a twelfth pixel opening area PK12, which are disposed on a substrate;

[0322] PK1, PK2, PK3, PK4, PK5, and PK6 are arranged in the horizontal direction;

[0323] PK7, PK8, PK9, PK10, PK11, and PK12 are arranged in the horizontal direction;

[0324] PK1 and PK7 are arranged in a vertical direction, PK2 and PK8 are arranged in a vertical direction, PK3 and PK9 are arranged in a vertical direction, PK4 and PK10 are arranged in a vertical direction, PK5 and PK11 are arranged in a vertical direction, and PK6 and PK12 are arranged in a vertical direction.

[0325] In at least one embodiment corresponding to FIG. 19B , each pixel opening region is defined by the first pixel defining layer and the second pixel defining layer in FIG. 19A .

[0326] As shown in FIG19C , in at least one embodiment of the present disclosure, the display panel includes a first pixel opening area PK1, a second pixel opening area PK2, a third pixel opening area PK3, a fourth pixel opening area PK4, a fifth pixel opening area PK5, a sixth pixel opening area PK6, a seventh pixel opening area PK7, an eighth pixel opening area PK8, a ninth pixel opening area PK9, a tenth pixel opening area PK10, an eleventh pixel opening area PK11, and a twelfth pixel opening area PK12, which are disposed on a substrate.

[0327] PK1, PK2, PK3, PK4, PK5, and PK6 are arranged in the horizontal direction;

[0328] PK7, PK8, PK9, PK10, PK11, and PK12 are arranged in the horizontal direction;

[0329] PK1 and PK7 are arranged in a vertical direction, PK2 and PK8 are arranged in a vertical direction, PK3 and PK9 are arranged in a vertical direction, PK4 and PK10 are arranged in a vertical direction, PK5 and PK11 are arranged in a vertical direction, and PK6 and PK12 are arranged in a vertical direction;

[0330] Compared with at least one embodiment corresponding to FIG. 19B , in at least one embodiment corresponding to FIG. 19C , the vertical lengths of PK7, PK8, PK9, PK10, PK11, and PK12 are reduced to avoid third-type and fourth-type via holes between two vertically adjacent pixel opening areas.

[0331] Narrowing the width of PK7 in the horizontal direction, that is, moving the left boundary line of PK7 to the right to avoid the first second via hole H12;

[0332] Narrowing the width of PK12 in the horizontal direction, that is, moving the right boundary line of PK12 to the left to avoid the second via hole H22;

[0333] Narrowing the width of PK3 in the horizontal direction, that is, moving the right boundary line of PK3 to the left to avoid the first via hole H1;

[0334] The width of PK4 in the horizontal direction is narrowed, that is, the left boundary line of PK4 is moved to the right to avoid the first via hole H1.

[0335] Compared with at least one embodiment corresponding to FIG. 19C , in at least one embodiment corresponding to FIG. 19E , the width of PK8 along the horizontal direction is narrowed, and the width of PK11 along the horizontal direction is narrowed to avoid the fourth via hole;

[0336] The width of PK2 is narrowed in the horizontal direction, and the width of PK5 is narrowed in the horizontal direction.

[0337] As shown in FIG19E , the display panel further includes a lens group disposed on a side of each sub-pixel away from the substrate; the lens group may include seven lenses: a first lens TJ1, a second lens TJ2, a third lens TJ3, a fourth lens TJ4, a fifth lens TJ5, a sixth lens TJ6, and a seventh lens TJ7.

[0338] FIG. 22 is a schematic diagram of overlapping openings of the first pixel defining layer and the second pixel defining layer according to at least one embodiment.

[0339] In Figure 22, the first opening of the second pixel defining layer is labeled K1, the second opening of the second pixel defining layer is labeled K2, the third opening of the second pixel defining layer is labeled K3, the fourth opening of the second pixel defining layer is labeled K4, the fifth opening of the second pixel defining layer is labeled K5, the sixth opening of the second pixel defining layer is labeled K6, the seventh opening of the second pixel defining layer is labeled K7, the eighth opening of the second pixel defining layer is labeled K8, the ninth opening of the second pixel defining layer is labeled K9, the tenth opening of the second pixel defining layer is labeled K10, and the eleventh opening of the second pixel defining layer is labeled K11.

[0340] FIG. 23 is a layout diagram of the first pixel defining layer in FIG. 22 .

[0341] In FIG23 , the portion labeled PB1 is a first pixel defining portion, the portion labeled PB2 is a second pixel defining portion, and the portion labeled PB3 is a third pixel defining portion;

[0342] The first pixel defining portion PB1 , the second pixel defining portion PB2 , and the third pixel defining portion PB3 are arranged along a vertical direction.

[0343] FIG. 24 is a schematic diagram showing a first pixel defining layer disposed on the layout diagram of the display panel shown in FIG. 2 .

[0344] In FIG24 , the first pixel defining portion is labeled PB1;

[0345] The first pixel defining portion PB1 is an integrated structure extending along the horizontal direction.

[0346] As shown in FIG25 , after the first pixel defining layer is formed, the second pixel defining layer may be formed;

[0347] In FIG25 , the first opening is labeled K1, the second opening is labeled K2, the third opening is labeled K3, the fourth opening is labeled K4, the fifth opening is labeled K5, and the sixth opening is labeled K6;

[0348] forming a pixel defining material at locations other than the openings;

[0349] K1, K2, K3, K4, K5 and K6 are arranged in the horizontal direction.

[0350] K1 , K2 , K3 , K4 , K5 , and K6 extend in the vertical direction.

[0351] As shown in FIG25 , the second pixel defining layer forms a first opening K1 , a second opening K2 , a third opening K3 , a fourth opening K4 , a fifth opening K5 and a sixth opening K6 arranged in a horizontal direction;

[0352] The first opening K1, the second opening K2, the third opening K3, the fourth opening K4, the fifth opening K5 and the sixth opening K6 extend in the vertical direction;

[0353] PB1 fills part of K1 , PB1 fills part of K2 , PB1 fills part of K3 , PB1 fills part of K4 , PB1 fills part of K5 , and PB1 fills part of K6 . Each pixel defining portion defines a pixel opening area in each opening.

[0354] FIG26 is a layout diagram of the first pixel defining layer in FIG25 , and FIG26 is a schematic diagram of the openings of the second pixel defining layer in FIG24 .

[0355] FIG. 28 is a schematic diagram showing at least one embodiment of overlapping openings of the first pixel defining layer and the second pixel defining layer in FIG. 25 .

[0356] In at least one embodiment of the present disclosure, the maximum distance between the first pixel defining layer and the substrate is different from the maximum distance between the second pixel defining layer and the substrate, so that the light-emitting layers of the light-emitting elements in the sub-pixels located in the same column are continuous with each other and have the same color.

[0357] Figure 29A is a cross-sectional view after a semiconductor layer, a first gate metal layer, a second gate metal layer, a first source-drain metal layer, a second source-drain metal layer, a first ITO layer, a first pixel defining layer, a second pixel defining layer, a light-emitting layer and a cathode layer are arranged on a substrate. In this cross-sectional view, a connection via is shown between the plate of the storage capacitor located in the second gate metal layer and the anode of the light-emitting element located in the first ITO layer.

[0358] In Figure 29A, the number 10 is the substrate, the number 11 is the second insulating layer, the number 12 is the semiconductor layer, the number 13 is the first gate insulating layer, the number 14 is the first gate metal layer, the number 15 is the second gate insulating layer, the number 16 is the second gate metal layer, the number 17 is the interlayer dielectric layer, the number 18 is the first source and drain metal layer, the number 19 is the first planarizing layer, the number 110 is the first passivation layer, the number 111 is the second source and drain metal layer, the number 112 is the second passivation layer, the number 113 is the second planarizing layer, the number 114 is the first ITO layer, the number 115 is the first pixel defining layer, the number 116 is the second pixel defining layer, the number 117 is the light-emitting layer, and the number 118 is the cathode layer.

[0359] As shown in FIG. 29A , the via holes of the first planar layer 19 and the via holes of the second planar layer 113 avoid the pixel opening area.

[0360] The difference between FIG. 29B and FIG. 29A is that an anode planarization layer 290 is provided between the second source / drain metal layer 111 and the first ITO layer 114 ;

[0361] The thickness of the anode planarization layer 290 is greater than the thickness of the second planarization layer;

[0362] The via holes of the anode planarization layer 290 can avoid the pixel opening area.

[0363] The display device described in the embodiment of the present disclosure includes the above-mentioned display panel.

[0364] Optionally, the display panel includes sub-pixels;

[0365] As shown in FIG30 , the sub-pixel includes a light-emitting element E1, a storage circuit 31, a driving circuit 30, a data writing circuit 32, and a light-emitting control circuit 33;

[0366] The first end of the energy storage circuit 31 is electrically connected to the anode of the light emitting element E1; the control end of the drive circuit 30 is electrically connected to the second end of the energy storage circuit 31, the first end of the drive circuit 30 is electrically connected to the anode of the light emitting element E1, and the cathode of the light emitting element E1 is electrically connected to the second voltage line V2;

[0367] The data writing circuit 32 is electrically connected to the first scan line G1, the data line DA, and the second end of the energy storage circuit 31, respectively, and is used to write the data voltage provided by the data line DA into the second end of the energy storage circuit 31 under the control of the first scan signal provided by the first scan line G1;

[0368] The light-emitting control circuit 33 is electrically connected to the light-emitting control line EM, the second end of the driving circuit 30 and the first voltage line V1 respectively, and is used to control the connection between the first voltage line V1 and the second end of the driving circuit 30 under the control of the light-emitting control signal provided by the light-emitting control line EM.

[0369] Optionally, the first voltage line may be a high voltage line, and the second voltage line may be a low voltage line.

[0370] In at least one embodiment of the present disclosure, the light emitting element E1 may be an organic light emitting diode, but is not limited thereto. In actual operation, the light emitting element E1 may also be other types of light emitting diodes.

[0371] Optionally, the sub-pixel further includes a first reset circuit and a second reset circuit;

[0372] The second reset circuit is electrically connected to the second scan line, the reference voltage line and the second end of the energy storage circuit respectively, and is used to write the reference voltage provided by the reference voltage line into the second end of the energy storage circuit under the control of the second scan signal provided by the second scan line;

[0373] The first reset circuit is electrically connected to the third scan line, the initial voltage line and the anode of the light-emitting element respectively, and is used to write the initial voltage provided by the initial voltage line into the anode of the light-emitting element under the control of the third scan signal provided by the third scan line.

[0374] In a specific implementation, the sub-pixel may further include a first reset circuit and a second reset circuit, wherein the first reset circuit is used to reset the potential of the second end of the energy storage circuit and the second reset circuit is used to reset the potential of the anode of the light-emitting element.

[0375] As shown in FIG31 , based on at least one embodiment of the sub-pixel shown in FIG30 , the sub-pixel may further include a first reset circuit 34 and a second reset circuit 35 ;

[0376] The second reset circuit 35 is electrically connected to the second scan line G2, the reference voltage line REF, and the second end of the energy storage circuit 31, respectively, and is used to write the reference voltage Vfef provided by the reference voltage line REF into the second end of the energy storage circuit 31 under the control of the second scan signal provided by the second scan line G2;

[0377] The first reset circuit 34 is electrically connected to the third scan line G3, the initial voltage line I1 and the anode of the light-emitting element E1, respectively, and is used to write the initial voltage Vi provided by the initial voltage line I1 into the anode of the light-emitting element E1 under the control of the third scan signal provided by the third scan line G3.

[0378] As shown in FIG32 , based on at least one embodiment of the sub-pixel shown in FIG31 , the light-emitting element may be an organic light-emitting diode O1, the energy storage circuit includes a storage capacitor C1, the first reset circuit includes a first reset transistor T3, the data write circuit may include a data write transistor T2, the second reset circuit may include a second reset transistor T1, the drive circuit may include a drive transistor T0, and the light-emission control circuit may include a light-emission control transistor T4;

[0379] The gate of the first reset transistor T3 is electrically connected to the third scan line G3, the first electrode of the first reset transistor T3 is electrically connected to the anode of the organic light emitting diode O1, the second electrode of the first reset transistor T3 is electrically connected to the initial voltage line I1; the cathode of O1 is electrically connected to the low voltage line VSS;

[0380] The anode of the organic light emitting diode O1 is electrically connected to the first electrode of the storage capacitor C1; the second electrode of the storage capacitor C1 is electrically connected to the second electrode of the data writing transistor T2;

[0381] The gate of the data writing transistor T2 is electrically connected to the first scan line G1, and the first electrode of the data writing transistor T2 is electrically connected to the first column data line DA1;

[0382] The gate of the second reset transistor T1 is electrically connected to the second scan line G2, the first electrode of the second reset transistor T1 is electrically connected to the reference voltage line REF, and the second electrode of the second reset transistor T1 is electrically connected to the second electrode of the data writing transistor T2;

[0383] The gate of the driving transistor T0 is electrically connected to the second plate of the storage capacitor, the first electrode of the driving transistor T0 is electrically connected to the anode of the organic light emitting diode O1, and the second electrode of the driving transistor T0 is electrically connected to the first electrode of the light emitting control transistor T4;

[0384] A gate of the light emission control transistor T4 is electrically connected to the light emission control line EM, and a second voltage of the light emission control transistor T4 is electrically connected to the high voltage line VDD.

[0385] In at least one embodiment of the sub-pixel shown in FIG. 32 , all transistors are n-type transistors.

[0386] In at least one embodiment of the present disclosure, the display panel may include multiple rows and columns of at least one embodiment of the sub-pixels shown in FIG32 ;

[0387] When the display panel is in operation, two rows of sub-pixels can be reset and compensated simultaneously, and then data voltages are written to the two rows one by one to emit light.

[0388] As shown in FIG33 , when at least one embodiment of the display panel is in operation, a display cycle may include a reset phase S1 , a compensation phase S2 , a data writing phase S3 , and a light emitting phase S4 , which are arranged in sequence;

[0389] In the reset phase S1, G3 provides a high voltage signal and T3 is turned on to write Vi into the anode of O1 and clear the residual charge on the anode of O1; G2 provides a high voltage signal and T1 is turned on to write Vref into the second electrode of the data writing transistor T2;

[0390] In the compensation phase S2, G2 provides a high voltage signal, EM provides a high voltage signal, T1 is turned on, and T4 is turned on;

[0391] In the data writing phase S3, G1(1) and G2(2) successively output high voltage signals, T2 in the first row of sub-pixels and T2 in the second row of sub-pixels are successively turned on, and the corresponding data voltages are successively written to the corresponding sub-pixels; wherein, G1

[0392] (1) is the first scan line of the first row electrically connected to the first row of sub-pixels, and G1(2) is the first scan line of the second row electrically connected to the second row of sub-pixels;

[0393] As shown in FIG33 , in the data writing phase S23 , the time period when G1 (1) outputs a high voltage signal partially overlaps with the time period when G1 (2) outputs a high voltage signal, making it easier to be compatible with large-size loads.

[0394] In the light-emitting stage S4, EM provides a high voltage signal and T0 drives O1 to emit light.

[0395] In FIG33 , the period labeled S31 is the first writing period, and the period labeled S32 is the second writing period.

[0396] FIG34 is a timing diagram of pixel binning with doubled refresh rate. In FIG34 , the reset and compensation timing diagrams are the same as those in FIG33 .

[0397] As shown in FIG34 , the first writing time period S31 and the second writing time period are the same time period. In the first writing time period S31 , the same data is written into the first row of sub-pixels and the second sub-pixels, thereby realizing a display with reduced resolution and doubled refresh rate.

[0398] The driving method described in the embodiment of the present disclosure is applied to the above-mentioned display device, and the display cycle includes N display stages; the nth display stage includes an nth data writing stage set in sequence; N is an integer greater than 1, and n is a positive integer less than or equal to N; the driving method includes: in at least a part of the time period included in the nth data writing stage, the data writing circuit included in the 2n-1th row of sub-pixels writes the data voltage into the second end of the energy storage circuit included in the 2n-1th row of sub-pixels under the control of the first scanning signal provided by the first scanning line of the 2n-1th row, and the data writing circuit included in the 2nth row of sub-pixels writes the data voltage into the second end of the energy storage circuit included in the 2nth row of sub-pixels under the control of the first scanning signal provided by the first scanning line of the 2nth row.

[0399] In at least one embodiment of the present disclosure, the nth data writing phase includes an nth first writing time period and an nth second writing time period;

[0400] The driving method includes:

[0401] In the nth first writing time period, the data writing circuit included in the sub-pixel in the 2n-1th row writes the data voltage into the second end of the energy storage circuit included in the sub-pixel in the 2n-1th row under the control of the first scanning signal provided by the first scanning line in the 2n-1th row;

[0402] In the nth second writing time period, the data writing circuit included in the sub-pixels in the 2nth row writes the data voltage into the second end of the energy storage circuit included in the sub-pixels in the 2nth row under the control of the first scanning signal provided by the first scanning line in the 2nth row;

[0403] The nth first writing time period and the nth second writing time period at least partially overlap.

[0404] The above is a preferred embodiment of the present disclosure. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles described in the present disclosure. These improvements and modifications should also be regarded as the scope of protection of the present disclosure.

Claims

1. A display panel, comprising a substrate and a plurality of pixel openings disposed on the substrate, further comprising at least one flat layer and at least two conductive layers stacked on the substrate, with one flat layer disposed between adjacent conductive layers, and the flat layer having a first type of via and a second type of via; The display panel includes signal lines for transmitting a reference voltage signal and signal lines for transmitting a power supply voltage signal; The signal lines for transmitting the reference voltage signal include a first signal line and a second signal line; the first signal line is electrically connected to the second signal line through the first type of via; The signal lines for transmitting the power supply voltage signal include a third signal line and a fourth signal line, and the third signal line is electrically connected to the fourth signal line through the second type of via; The orthographic projection of the first type of via on the substrate does not overlap with the orthographic projection of the pixel opening on the substrate; The orthographic projection of the second type of via on the substrate does not overlap with the orthographic projection of the pixel opening on the substrate.

2. The display panel according to claim 1, wherein, The display panel includes a first conductive layer, a second conductive layer, and a first flat layer; the first conductive layer, the first flat layer, and the second conductive layer are arranged in sequence along a direction away from the substrate; the first signal line is a first reference signal line, and the second signal line is a first reference connection line; The first type of via includes a first via; The first conductive layer includes the first reference signal line, and the second conductive layer includes the first reference connection line; The first flat layer has the first via; the first reference signal line is electrically connected to the first reference connection line through the first via.

3. The display panel according to claim 2, wherein, The display panel further includes a third conductive layer; the first conductive layer includes a second reference signal line; the third conductive layer includes a second reference connection line; the second reference signal line is electrically connected to the second reference connection line; The third conductive layer is disposed between the substrate and the first conductive layer; The first reference connection line and the second reference connection line both extend in a first direction; The orthographic projections of the two second reference connection lines on the substrate are disposed on opposite sides of the orthographic projection of the first reference connection line on the substrate.

4. The display panel according to claim 1, wherein, The display panel includes a first conductive layer, a second conductive layer, and a first flat layer; the first conductive layer, the first flat layer, and the second conductive layer are arranged in sequence along a direction away from the substrate; the third signal line is a first voltage line, and the fourth signal line is a first voltage connection line; the second type of via includes a second via; The first conductive layer includes the first voltage line, and the second conductive layer includes the first voltage connection line; The first flat layer has the second via; the first voltage line is electrically connected to the first voltage connection line through the second via.

5. The display panel according to claim 1, wherein, The flat layer has a third type of via; The display panel includes a plurality of sub-pixels disposed on the substrate; the sub-pixels include light-emitting elements, storage capacitors, and a plurality of transistors; The sub-pixels include a plurality of conductive portions, and the plurality of conductive portions include anodes of the light-emitting elements, plates of the storage capacitors, and electrodes of the transistors; Some of the conductive portions among the plurality of conductive portions are electrically connected through the third type of vias; The orthographic projection of the third type of vias on the substrate does not overlap with the orthographic projection of the pixel opening region on the substrate.

6. The display panel according to claim 1, wherein, The planarization layer has fourth type of vias; The display panel includes a plurality of data lines and a plurality of sub-pixels disposed on the substrate; Partial electrodes of some of the transistors in the sub-pixels are electrically connected to the data lines through the fourth type of vias; The orthographic projection of the fourth type of vias on the substrate does not overlap with the orthographic projection of the pixel opening region on the substrate.

7. The display panel according to claim 5, wherein, The transistors in the sub-pixels include first reset transistors; the third type of vias include third vias and fourth vias; The display panel further includes a semiconductor layer, a first conductive layer, a first planarization layer, a second conductive layer, a second planarization layer, and a fourth conductive layer arranged in sequence along a direction away from the substrate; the semiconductor layer includes a first electrode of the first reset transistor, and the fourth conductive layer includes an anode of the light-emitting element; the first planarization layer has the third vias, and the second planarization layer has the fourth vias; The first electrode of the first reset transistor is electrically connected to the anode of the light-emitting element through the third vias and the fourth vias.

8. The display panel according to claim 5, wherein, The third type of vias include fifth vias and sixth vias; the display panel further includes a fifth conductive layer, a first insulating layer, a first conductive layer, a first planarization layer, a second conductive layer, a second planarization layer, and a fourth conductive layer arranged in sequence along a direction away from the substrate; The fourth conductive layer includes an anode of the light-emitting element; the fifth conductive layer includes a first plate of the storage capacitor; The first planarization layer has the fifth vias, and the second planarization layer has the sixth vias; The anode of the light-emitting element is electrically connected to the first plate of the storage capacitor through the sixth vias, the fifth vias, and a via penetrating the first insulating layer.

9. The display panel according to claim 6, wherein, The transistors in the sub-pixels include data writing transistors; the fourth type of vias include seventh vias; The display panel further includes a semiconductor layer, a first conductive layer, a first planarization layer, and a second conductive layer arranged in sequence along a direction away from the substrate; The semiconductor layer includes a first electrode of the data writing transistor, and the second conductive layer includes the data lines; The first planarization layer has the seventh vias, and the first electrode of the data writing transistor is electrically connected to the data lines through the seventh vias.

10. The display panel according to claim 5, wherein, The transistor in the sub-pixel includes a first reset transistor; the third type of vias includes a third via, a fourth via, and an eighth via; The display panel further includes a semiconductor layer, a first conductive layer, a first planarization layer, a second conductive layer, a second planarization layer, a fourth conductive layer, a third planarization layer, and a sixth conductive layer arranged in sequence along a direction away from the substrate; The semiconductor layer includes a first electrode of the first reset transistor, and the sixth conductive layer includes an anode of the light-emitting element; the first planarization layer has the third via, the second planarization layer has the fourth via, and the third planarization layer has the eighth via; The first electrode of the first reset transistor is electrically connected to the anode of the light-emitting element through the third via, the fourth via, and the eighth via.

11. The display panel according to claim 5, wherein, The third type of vias includes a fifth via, a sixth via, and a ninth via; The display panel further includes a fifth conductive layer, a first insulating layer, a first conductive layer, a first planarization layer, a second conductive layer, a second planarization layer, a fourth conductive layer, a third planarization layer, and a sixth conductive layer arranged in sequence along a direction away from the substrate; The sixth conductive layer includes an anode of the light-emitting element, and the fifth conductive layer includes a first electrode plate of the storage capacitor; The first planarization layer has the fifth via, the second planarization layer has the sixth via, and the third planarization layer has the ninth via; The anode of the light-emitting element is electrically connected to the first electrode plate of the storage capacitor through the ninth via, the sixth via, the fifth via, and a via penetrating the first insulating layer.

12. The display panel according to claim 3, wherein, The multiple sub-pixels are divided into multiple pixel units arranged in an array; each pixel unit includes multiple sub-pixels arranged in a second direction; the first direction intersects with the second direction; There are N columns of the pixel units arranged between two adjacent first reference connection lines; N is an integer greater than 1.

13. The display panel according to claim 12, wherein, The display panel further includes a multi-row and multi-column lens group arranged on a side of the pixel unit away from the substrate; the lens group includes an odd number of lenses; The N pixel units in the same row arranged between two adjacent first reference connection lines correspond to the same lens group.

14. The display panel according to claim 13, wherein, The pixel units arranged between different adjacent two first reference connection lines correspond to different lens groups.

15. The display panel according to claim 12, wherein, The second reference connection line is adjacent to the first reference connection line in the second direction.

16. The display panel according to any one of claims 1 to 4, wherein, The display panel includes multiple sub-pixels arranged on the substrate; the sub-pixels include light-emitting elements; The display panel includes a second conductive layer, an anode planarization layer, and a fourth conductive layer stacked along a direction away from the substrate; the fourth conductive layer includes an anode of the light-emitting element; The thickness of the anode planarization layer is greater than the thickness of the planarization layer.

17. The display panel according to claim 16, wherein, the sub-pixel further includes a plurality of transistors and a storage capacitor; the anode of the light-emitting element is electrically connected to partial electrodes of some of the plurality of transistors and / or partial plates of the storage capacitor through a fifth type of via hole in the anode planarization layer; a positive projection of the fifth type of via hole on the substrate does not overlap with a positive projection of the pixel opening region on the substrate.

18. The display panel according to any one of claims 1 to 15, wherein, the display panel includes a plurality of sub-pixels disposed on the substrate; the sub-pixels include light-emitting elements; the light-emitting elements include light-emitting layers; the light-emitting layers of the light-emitting elements in the sub-pixels located in the same column are continuous with each other and have the same color.

19. The display panel according to any one of claims 1 to 15, wherein, the thickness of the planarization layer is greater than a first thickness threshold, and the first thickness threshold is greater than or equal to 2.8 μm and less than or equal to 3.2 μm.

20. The display panel according to any one of claims 1 to 15, wherein, the display panel includes a plurality of sub-pixels disposed on the substrate; the sub-pixels include light-emitting elements, storage capacitors, first reset transistors, data writing transistors, and second reset transistors; the active pattern of the second reset transistor is electrically connected to the active pattern of the data writing transistor through a first connection line; the active pattern of the data writing transistor is electrically connected to a second plate of the storage capacitor through a second connection line; the anode of the light-emitting element is electrically connected to the active pattern of the first reset transistor through a third connection line; the first connection line, the second connection line, and the third connection line are disposed on the same layer as the active pattern.

21. The display panel according to any one of claims 1 to 15, wherein, the display panel includes a first pixel defining layer and a second pixel defining layer; the second pixel defining layer forms a plurality of openings arranged along a second direction, and the openings extend along a first direction; the first pixel defining layer includes a plurality of pixel defining portions arranged along the first direction, the pixel defining portions fill a part of the openings, and the plurality of pixel defining portions define a plurality of pixel opening regions in the plurality of openings.

22. The display panel according to claim 19, wherein, the pixel defining portion includes an integral structure extending along the second direction; or, the pixel defining portion includes a plurality of pixel defining patterns arranged along the second direction, and at least part of the pixel defining patterns is filled in the corresponding openings.

23. The display panel according to claim 19, wherein, a maximum distance between the first pixel defining layer and the substrate is different from a maximum distance between the second pixel defining layer and the substrate.

24. A display device, including the display panel according to any one of claims 1 to 23.

25. The display device according to claim 24, wherein, the display panel includes sub-pixels; The sub-pixel includes a light-emitting element, an energy storage circuit, a driving circuit, a data writing circuit, and a light-emitting control circuit; A first end of the energy storage circuit is electrically connected to an anode of the light-emitting element; a control end of the driving circuit is electrically connected to a second end of the energy storage circuit, a first end of the driving circuit is electrically connected to the anode of the light-emitting element, and a cathode of the light-emitting element is electrically connected to a second voltage line; The data writing circuit is electrically connected to a first scan line, a data line, and the second end of the energy storage circuit respectively, and is configured to write a data voltage provided by the data line into the second end of the energy storage circuit under the control of a first scan signal provided by the first scan line; The light-emitting control circuit is electrically connected to a light-emitting control line, a second end of the driving circuit, and a first voltage line respectively, and is configured to control communication between the first voltage line and the second end of the driving circuit under the control of a light-emitting control signal provided by the light-emitting control line.

26. The display device according to claim 24, wherein, the sub-pixel further includes a first reset circuit and a second reset circuit; The second reset circuit is electrically connected to a second scan line, a reference voltage line, and the second end of the energy storage circuit respectively, and is configured to write a reference voltage provided by the reference voltage line into the second end of the energy storage circuit under the control of a second scan signal provided by the second scan line; The first reset circuit is electrically connected to a third scan line, an initial voltage line, and the anode of the light-emitting element respectively, and is configured to write an initial voltage provided by the initial voltage line into the anode of the light-emitting element under the control of a third scan signal provided by the third scan line.

27. A driving method is applied to the display device according to claim 25 or 26. A display period includes N display phases; the nth display phase includes a first n data writing phase arranged successively; N is an integer greater than 1, and n is a positive integer less than or equal to N; the driving method includes: In at least a partial time period included in the nth data writing phase, the data writing circuit included in the sub-pixels of the (2n - 1)th row writes a data voltage into the second end of the energy storage circuit included in the sub-pixels of the (2n - 1)th row under the control of a first scan signal provided by the first scan line of the (2n - 1)th row, and the data writing circuit included in the sub-pixels of the 2nth row writes a data voltage into the second end of the energy storage circuit included in the sub-pixels of the 2nth row under the control of a first scan signal provided by the first scan line of the 2nth row.

28. The driving method according to claim 27, wherein, the nth data writing phase includes an nth first writing time period and an nth second writing time period; The driving method includes: In the nth first writing time period, the data writing circuit included in the sub-pixels of the (2n - 1)th row writes a data voltage into the second end of the energy storage circuit included in the sub-pixels of the (2n - 1)th row under the control of a first scan signal provided by the first scan line of the (2n - 1)th row; During the n-th second writing period, the data writing circuit included in the sub-pixels of the 2n-th row writes a data voltage to the second end of the energy storage circuit included in the sub-pixels of the 2n-th row under the control of the first scanning signal provided by the first scanning line of the 2n-th row; The n-th first writing period and the n-th second writing period at least partially overlap.

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