Shift register unit, display substrate, and display apparatus

Abstract

Provided in the present disclosure are a shift register unit, a display substrate, and a display apparatus. The shift register unit comprises a first output transistor, a gate driving signal output end, a first output control node, a control signal input end and a first signal input end, wherein the first output transistor comprises a double-gate structure, a first gate electrode of the first output transistor is coupled to the first output control node, and a second gate electrode of the first output transistor is coupled to the control signal input end, a first electrode of the first output transistor is coupled to the first signal input end, and a second electrode of the first output transistor is coupled to the gate driving signal output end.

Description

Shift register unit, display substrate, and display device

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Chinese patent application No. 202311621298.3 filed in China on November 30, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to the field of display technology, and in particular to a shift register unit, a display substrate, and a display device. Background Art

[0004] With the continuous development of display technology, the application fields of display products are becoming increasingly broad, and people's requirements for display quality of display products are also becoming higher and higher. In order to further narrow the width of the display device border and improve the driving performance of the display product, GOA (Gate On Array) technology is generally adopted. This GOA technology integrates the gate drive circuit in the peripheral area of ​​the array substrate of the display product. In this way, based on the external circuit providing only a few control signals, the gate drive circuit is manufactured using the same process as thin-film transistors, which can achieve the row-by-row scanning drive function.

[0005] A gate drive circuit generally includes multiple cascaded shift register units, each of which includes multiple thin-film transistors. In related art, the characteristics of thin-film transistors have a certain impact on the stability of the gate drive signal output by the shift register unit, thereby affecting the display quality of the display product.

[0006] Summary of the Invention

[0007] The present disclosure aims to provide a shift register unit, a display substrate and a display device.

[0008] In order to achieve the above objectives, the present disclosure provides the following technical solutions:

[0009] A first aspect of the present disclosure provides a shift register unit comprising a first output transistor, a gate drive signal output terminal, a first output control node, a control signal input terminal and a first signal input terminal;

[0010] The first output transistor includes a dual-gate structure, the first gate of the first output transistor is coupled to the first output control node, the second gate of the first output transistor is coupled to the control signal input terminal, the first electrode of the first output transistor is coupled to the first signal input terminal, and the second electrode of the first output transistor is coupled to the gate drive signal output terminal.

[0011] Optionally, the shift register unit further includes a second output transistor, a second output control node and a first level signal input terminal, a gate of the second output transistor is coupled to the second output control node, a first electrode of the second output transistor is coupled to the first level signal input terminal, and a second electrode of the second output transistor is coupled to the gate drive signal output terminal;

[0012] The first signal input terminal includes a first clock signal input terminal; the shift register unit further includes a second level signal input terminal, a third level signal input terminal and a control signal debugging unit, and the control signal debugging unit includes a first debugging sub-unit and a second debugging sub-unit;

[0013] The first debugging sub-unit is coupled to the first clock signal input terminal, the second output control node, the second level signal input terminal and the control signal input terminal respectively, and is used to control the electrical connection between the second level signal input terminal and the control signal input terminal to be turned on or off under the control of the first clock signal input terminal and the second output control node;

[0014] The second debugging sub-unit is coupled to the first output control node, the third level signal input terminal and the control signal input terminal respectively, and is used to control the conduction or disconnection of the electrical connection between the third level signal input terminal and the control signal input terminal under the control of the first output control node.

[0015] Optionally, the first debugging sub-unit includes a first debugging transistor and a second debugging transistor; the second debugging sub-unit includes a third debugging transistor;

[0016] The gate of the first debug transistor is coupled to the first clock signal input terminal, the first electrode of the first debug transistor is coupled to the second electrode of the second debug transistor, and the second electrode of the first debug transistor is coupled to the control signal input terminal;

[0017] The gate of the second debug transistor is coupled to the second output control node, and the first electrode of the second debug transistor is coupled to the second level signal input terminal;

[0018] A gate of the third debug transistor is coupled to the first output control node, a first electrode of the third debug transistor is coupled to the third level signal input terminal, and a second electrode of the third debug transistor is coupled to the control signal input terminal.

[0019] Optionally, the shift register unit further includes: a first node control unit, a second node control unit, a second clock signal input terminal and a start signal input terminal;

[0020] The first node control unit is coupled to the second clock signal input terminal, the first output control node and the start signal input terminal respectively; and is used to control the electrical connection between the initial signal input terminal and the first output control node to be turned on or off under the control of the second clock signal input terminal;

[0021] The second node control unit is coupled to the first clock signal input terminal, the second clock signal input terminal, the first level signal input terminal, the third level signal input terminal and the second output control node respectively, and is used to control the electrical connection between the first level signal input terminal and the second output control node under the control of the first clock signal input terminal, and is used to control the electrical connection between the third level signal input terminal and the second output control node under the control of the second clock signal input terminal; or, the second node control unit is coupled to the second clock signal input terminal, the first output control node, the second output control node and the third level signal input terminal respectively, and is used to control the electrical connection between the third level signal input terminal and the second output control node under the control of the second clock signal input terminal; and is used to control the electrical connection between the second clock signal input terminal and the second output control node under the control of the first output control node.

[0022] Optionally, the first node control unit is also coupled to the first clock signal input terminal, the second output control node, and the first level signal input terminal, respectively; and is used to control the conduction or disconnection of the electrical connection between the first level signal input terminal and the first output control node under the control of the first clock signal input terminal and the second output control node.

[0023] Optionally, the first signal input terminal includes a first level signal input terminal, and the control signal input terminal includes a second level signal input terminal, and the second level signal input terminal is used to input a second level DC signal;

[0024] The shift register unit also includes: a second output transistor, a second output control node and a third level signal input terminal, the gate of the second output transistor is coupled to the second output control node, the first electrode of the second output transistor is coupled to the third level signal input terminal, and the second electrode of the second output transistor is coupled to the gate drive signal output terminal.

[0025] Optionally, the shift register unit also includes a first node control unit, which is coupled to the second output control node, the first level signal input terminal and the first output control node respectively, and is used to control the conduction or disconnection of the electrical connection between the first level signal input terminal and the first output control node under the control of the second output control node.

[0026] Optionally, the first node control unit is also coupled to the second level signal input terminal; the first node control unit includes: a first control transistor, the first control transistor includes a dual-gate structure, the first gate of the first control transistor is coupled to the second output control node, the second gate of the first control transistor is coupled to the second level signal input terminal, the first electrode of the first control transistor is coupled to the first level signal input terminal, and the second electrode of the first control transistor is coupled to the first output control node.

[0027] Optionally, the shift register unit also includes a second node control unit, a third clock signal input terminal and a start signal input terminal; the second node control unit is coupled to the third clock signal input terminal, the start signal input terminal and the second output control node respectively, and is used to control the conduction or disconnection of the electrical connection between the start signal input terminal and the second output control node under the control of the third clock signal input terminal.

[0028] Optionally, the second node control unit is further coupled to the third level signal input terminal; the second node control unit includes: a second control transistor, a third control transistor and a fourth control transistor;

[0029] The gate of the second control transistor is coupled to the third clock signal input terminal, the first electrode of the second control transistor is coupled to the start signal input terminal, and the second electrode of the second control transistor is coupled to the first electrode of the third control transistor;

[0030] A gate of the third control transistor is coupled to the third clock signal input terminal, and a second electrode of the third control transistor is coupled to the second output control node.

[0031] The gate of the fourth control transistor is coupled to the second output control node, the first electrode of the fourth control transistor is coupled to the third level signal input terminal, and the second electrode of the fourth control transistor is coupled to the first electrode of the third control transistor.

[0032] Optionally, the first node control unit is also coupled to the first level signal input terminal, the third level signal input terminal and the start signal input terminal respectively; and is used to control the conduction or disconnection of the electrical connection between the third level signal input terminal and the first output control node under the control of the first level signal input terminal and the start signal input terminal.

[0033] Based on the technical solution of the above-mentioned shift register unit, the second aspect of the present disclosure provides a display substrate, including the above-mentioned shift register unit, the display substrate including a display area and a peripheral area located around the display area, and the shift register unit is located in the display area and / or the peripheral area.

[0034] Optionally, the shift register unit includes a control signal debugging unit, the control signal debugging unit includes a first debugging sub-unit and a second debugging sub-unit, the first debugging sub-unit includes a first debugging transistor and a second debugging transistor; the second debugging sub-unit includes a third debugging transistor; the shift register unit further includes a first output transistor and a second output transistor;

[0035] The first output transistor and the second output transistor are arranged along a first direction; at least part of the third debug transistor, the first debug transistor and the second debug transistor are arranged along the first direction; the first output transistor is located between the display area and the first debug transistor.

[0036] Optionally, the second debug transistor and the second output transistor both include a dual-gate structure, the first gate of the second debug transistor and the first gate of the second output transistor form an integrated structure, and the second gate of the second debug transistor and the second gate of the second output transistor form an integrated structure.

[0037] Optionally, the gate of the third debug transistor and the first gate of the first output transistor form an integrated structure.

[0038] Optionally, the display substrate further includes a second level signal line, and the second level signal line is coupled to the second debug transistor as a second level signal input terminal;

[0039] The first debug transistor includes a first debug active layer, the second debug transistor includes a second debug active layer, and the third debug transistor includes a third debug active layer;

[0040] The orthographic projection of the second-level signal line on the base substrate of the display substrate at least partially overlaps with the orthographic projection of the first debugging active layer on the base substrate of the display substrate; and / or, the orthographic projection of the second-level signal line on the base substrate of the display substrate at least partially overlaps with the orthographic projection of the second debugging active layer on the base substrate of the display substrate; and / or, the orthographic projection of the second-level signal line on the base substrate of the display substrate at least partially overlaps with the orthographic projection of the third debugging active layer on the base substrate of the display substrate.

[0041] Optionally, the display substrate further includes a first level signal line and a third level signal line; the first level signal line is coupled to the second output transistor as a first level signal input terminal; the third level signal line is coupled to the third debug transistor as a third level signal input terminal;

[0042] Along a direction close to the display area, an orthographic projection of the third-level signal line on the base substrate, an orthographic projection of the first-level signal line on the base substrate, and an orthographic projection of the second-level signal line on the base substrate are arranged in sequence.

[0043] Optionally, the display substrate further includes a first clock signal line, a second clock signal line, and a start signal line, wherein the first clock signal line is coupled to the first debug transistor as a first clock signal input terminal; the shift register unit further includes a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor;

[0044] The gate of the fifth transistor is coupled to the second clock signal line, the first electrode of the fifth transistor is coupled to the third level signal line, and the second electrode of the fifth transistor is coupled to the gate of the second output transistor;

[0045] The gate of the sixth transistor is coupled to the first clock signal line, the first electrode of the sixth transistor is coupled to the first level signal line, and the second electrode of the sixth transistor is coupled to the gate of the second output transistor;

[0046] a gate of the seventh transistor coupled to the second clock signal line, a first electrode of the seventh transistor coupled to the start signal line, a second electrode of the seventh transistor coupled to the first electrode of the eighth transistor, a second electrode of the eighth transistor coupled to the gate of the first output transistor, and a gate of the eighth transistor coupled to the third level signal line;

[0047] The seventh transistor, the eighth transistor, the sixth transistor and the fifth transistor are arranged in sequence along the first direction; the orthographic projection of the seventh transistor on the substrate, the orthographic projection of the eighth transistor on the substrate, the orthographic projection of the sixth transistor on the substrate, and the orthographic projection of the fifth transistor on the substrate are all located between the orthographic projection of the third-level signal line on the substrate and the orthographic projection of the first-level signal line on the substrate.

[0048] Optionally, along a direction close to the display area, the start signal line, the second clock signal line, the first clock signal line and the third level signal line are arranged in sequence.

[0049] Based on the technical solution of the above-mentioned display substrate, a third aspect of the present disclosure provides a display device including the above-mentioned display substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] The drawings described herein are used to provide a further understanding of the present disclosure and constitute a part of the present disclosure. The exemplary embodiments of the present disclosure and their descriptions are used to explain the present disclosure and do not constitute an improper limitation of the present disclosure. In the drawings:

[0051] FIG1 is a schematic diagram of a circuit structure of a shift register unit provided by an embodiment of the present disclosure;

[0052] FIG2 is a timing diagram corresponding to the circuit structure of FIG1 ;

[0053] FIG3 is a waveform diagram of a gate drive signal corresponding to different threshold voltage offset voltage values ​​of the circuit structure of FIG1 ;

[0054] FIG4 is a schematic structural diagram of a dual-gate transistor provided by an embodiment of the present disclosure;

[0055] FIG5 is a schematic diagram of characteristic curves corresponding to different bottom gate voltages provided by an embodiment of the present disclosure;

[0056] FIG6 is a schematic structural diagram of a dual-gate transistor provided by an embodiment of the present disclosure;

[0057] FIG7 is a schematic diagram of waveforms corresponding to the top gate and the bottom gate provided in an embodiment of the present disclosure;

[0058] FIG8 is a schematic diagram of voltage changes at the control signal input terminal corresponding to changes in the voltage value of the second level signal provided by an embodiment of the present disclosure;

[0059] FIG9 is a schematic diagram of a circuit structure of a shift register unit provided in an embodiment of the present disclosure;

[0060] FIG10 is a timing diagram corresponding to FIG9 ;

[0061] FIG11 is a waveform diagram of a gate drive signal corresponding to different threshold voltage offset voltage values ​​of the circuit structure of FIG9 ;

[0062] FIG12 is a schematic diagram of a circuit structure of a shift register unit provided in an embodiment of the present disclosure;

[0063] FIG13 is a schematic diagram of a circuit structure of a shift register unit provided in an embodiment of the present disclosure;

[0064] FIG14 is a schematic diagram of a circuit structure of a shift register unit provided in an embodiment of the present disclosure;

[0065] FIG15 is a waveform diagram of a gate drive signal corresponding to different threshold voltage offset voltage values ​​of the circuit structure of FIG14 ;

[0066] FIG16 is a schematic diagram of a circuit structure of a shift register unit provided in an embodiment of the present disclosure;

[0067] FIG17 is a waveform diagram of a gate drive signal corresponding to different threshold voltage offset voltage values ​​of the circuit structure of FIG16 ;

[0068] FIG18 is a schematic diagram of the layout of the first gate metal layer of the shift register unit provided by an embodiment of the present disclosure;

[0069] FIG19 is a schematic diagram of a layout in which a second gate metal layer is added on the basis of FIG18;

[0070] FIG20 is a schematic diagram of the layout of the second gate metal layer added in FIG19;

[0071] FIG21 is a schematic diagram of a layout in which an oxide active layer is added based on FIG19;

[0072] FIG22 is a schematic diagram of the layout of the oxide active layer added in FIG21;

[0073] FIG23 is a schematic diagram of a layout in which a third gate metal layer is added on the basis of FIG21;

[0074] FIG24 is a schematic diagram of the layout of the third gate metal layer added in FIG23;

[0075] FIG25 is a schematic diagram of a layout in which a first source / drain metal layer is added on the basis of FIG23;

[0076] FIG26 is a schematic diagram of the layout of the first source / drain metal layer added in FIG25 ;

[0077] FIG27 is a schematic diagram of the layout of FIG25 with a second source / drain metal layer added. DETAILED DESCRIPTION

[0078] In order to further illustrate the shift register unit, display substrate and display device provided by the embodiments of the present disclosure, they are described in detail below with reference to the accompanying drawings.

[0079] 9 to 14 , an embodiment of the present disclosure provides a shift register unit including a first output transistor Ts1 , a gate drive signal output terminal OUT, a first output control node N1 , a control signal input terminal K0 and a first signal input terminal X0 ;

[0080] The first output transistor Ts1 includes a dual-gate structure, the first gate of the first output transistor Ts1 is coupled to the first output control node N1, the second gate of the first output transistor Ts1 is coupled to the control signal input terminal K0, the first electrode of the first output transistor Ts1 is coupled to the first signal input terminal X0, and the second electrode of the first output transistor Ts1 is coupled to the gate drive signal output terminal OUT.

[0081] Exemplarily, the shift register unit is applied to a gate drive circuit, and the gate drive circuit includes a plurality of cascaded shift register units, such as a gate control shift register unit (Gate GOA) and an emission control shift register unit (EM GOA), but is not limited thereto.

[0082] Exemplarily, the display device includes a display area and a peripheral area located around the display area, the display area includes a plurality of sub-pixels distributed in an array, and the plurality of sub-pixels include a plurality of sub-pixel driving circuits divided into a plurality of rows of sub-pixel driving circuits.

[0083] Exemplarily, the display device further includes a plurality of gate lines, and the gate lines are respectively coupled to each sub-pixel driving circuit in a corresponding row of sub-pixel driving circuits, and are used to provide gate signals for each sub-pixel driving circuit. Taking the sub-pixel driving circuit adopting a 7T1C (i.e., including 7 transistors and 1 capacitor) circuit structure as an example, the compensation transistor and / or data writing transistor included in the sub-pixel driving circuit can be coupled to the gate line, but is not limited to this. Exemplarily, in the peripheral area, the gate driving circuit includes a gate control gate driving circuit, and the gate control gate driving circuit includes a plurality of cascaded Gate GOAs, and the gate drive signal output terminal OUT of each Gate GOA is coupled to the corresponding gate line.

[0084] Exemplarily, the display device further includes a plurality of light-emission control signal lines, each coupled to each sub-pixel driver circuit in a corresponding row of sub-pixel driver circuits, for providing a light-emission control signal to each sub-pixel driver circuit. Taking a sub-pixel driver circuit employing a 7T1C circuit structure as an example, the power control transistor and light-emission control transistor included in the sub-pixel driver circuit can be coupled to the light-emission control signal lines, but the present invention is not limited thereto. Exemplarily, in the peripheral region, the gate driver circuit includes a light-emission control gate driver circuit, which includes a plurality of cascaded EM GOAs, with the gate drive signal output terminal OUT of each EM GOA coupled to a corresponding light-emission control signal line.

[0085] Exemplarily, the shift register unit includes a plurality of transistors, and the transistors include oxide transistors, but are not limited thereto.

[0086] Exemplarily, the first electrode includes a source electrode, and the second electrode includes a drain electrode; or, the first electrode includes a drain electrode, and the second electrode includes a source electrode.

[0087] Exemplarily, the first gate of the first output transistor Ts1 is coupled to the first output control node N1, and the second gate of the first output transistor Ts1 is coupled to the control signal input terminal K0. The first output transistor Ts1 is used to realize the electrical connection between the first signal input terminal X0 and the gate drive signal output terminal OUT under the joint control of the first output control node N1 and the control signal input terminal K0.

[0088] In more detail, as shown in Figures 1 and 2, it is a schematic diagram of the abnormal output waveforms of each node and the gate drive signal output terminal OUT after the threshold voltage shift (VTH Shift) occurs in the first output transistor Ts1 in the shift register unit, such as after negative bias. The main reason for this abnormality is that the negative bias leakage causes the first output transistor Ts1 to turn on, and the increase in parasitic capacitance causes the first clock signal input terminal GCB to couple and leak with the gate drive signal output terminal OUT, resulting in burrs on the signal waveform, which in turn causes screen Mura to appear after VTH Shift negative bias. Through simulation, it is found that the main transistor negative bias point is the first output transistor Ts1. Therefore, improving the structure of the first output transistor Ts1 and its control signal can improve the negative bias of the first output transistor Ts1 structure, thereby improving the output gate drive signal. It should be noted that N3 in Figure 2 represents the node between the seventh transistor T7 and the eighth transistor T8 in Figure 1.

[0089] As shown in FIG4 , when the first output transistor Ts1 is set to adopt a dual-gate structure, the first gate of the first output transistor Ts1 is defined as a top gate TG, and the second gate of the first output transistor Ts1 is defined as a bottom gate BG. By regulating the voltage of the bottom gate BG, the threshold voltage of the first output transistor Ts1 can be regulated.

[0090] As shown in Figure 5, the effect of the bottom gate BG potential on the transistor characteristics is shown. The horizontal axis in the figure represents V GS1 , which is the voltage difference between the top gate TG and the source of the transistor. The vertical axis in the figure represents Ids, which is the current between the source and drain of the transistor. The figure shows the effect on the characteristic curve when the voltage of the bottom gate BG is set to 0V, 2V, 4V, 6V, -2V, -4V, and -6V respectively. Therefore, by adjusting the voltage of the bottom gate BG, the characteristic curve of the transistor can be regulated, so that even if the transistor is negatively biased, it can be adjusted back through the control of the bottom gate BG.

[0091] As shown in FIG6 , a connection method of the first output transistor Ts1 is shown. The first electrode of the first output transistor Ts1 is coupled to the first clock signal input terminal GCB, and the second electrode of the first output transistor Ts1 is coupled to the gate drive signal output terminal OUT. As shown in FIG7 , the V GS1 is the voltage difference between the top gate TG and the source of the first output transistor Ts1. GS2 is the voltage difference between the bottom gate BG and the source of the first output transistor Ts1. The signal waveform of the bottom gate BG will change with the signal waveform of the top gate TG, and can also be controlled by the control signal input terminal K0. The first dark area in Figure 7 shows V GS2 >0, the second dark area indicates V GS2 = 0, the third dark area indicates V GS2 <0. Set the V GS2 It is possible to adjust the characteristics of the first output transistor Ts1 to be forward biased.

[0092] As shown in Figure 3, before the first output transistor Ts1 is improved, the waveform of the gate drive signal output when the VTH Shift of the first output transistor Ts1 is biased from -5V to +5V is shown. It can be seen that when the bias voltage is between -5V and -2V, the output gate drive signal fluctuates. As shown in Figure 11, after the first output transistor Ts1 is improved, the waveform of the gate drive signal output when the VTH Shift of the first output transistor Ts1 is biased from -5V to +5V is shown. It can be seen that when the bias voltage is between -5V and +5V, the output gate drive signal does not fluctuate.

[0093] According to the specific structure of the above-mentioned shift register unit, in the shift register unit provided by the embodiment of the present disclosure, the first output transistor Ts1 is provided with a dual-gate structure, the first gate of the first output transistor Ts1 is coupled to the first output control node N1, the second gate of the first output transistor Ts1 is coupled to the control signal input terminal K0, the first electrode of the first output transistor Ts1 is coupled to the first signal input terminal X0, and the second electrode of the first output transistor Ts1 is coupled to the gate drive signal output terminal OUT. The first gate and the second gate can be used to control the conduction or cutoff of the first output transistor Ts1 to ensure the normal operation of the shift register unit. By adjusting the voltage of the second gate, the characteristic curve of the first output transistor Ts1 can be adjusted, thereby effectively improving the negative bias of the first output transistor Ts1 and improving the fluctuation of the output gate drive signal.

[0094] It should be noted that in the production process of oxide display products, oxide transistors are prone to negative bias, which in turn causes the shift register unit to fail. In order to take into account the process margin, it is necessary to improve the process margin of the oxide transistor. In the shift register unit provided in the embodiment of the present disclosure, by setting the first output transistor Ts1 to include a dual-gate structure, and by adjusting the voltage of the second gate of the first output transistor Ts1, it is possible to control the characteristic curve of the first output transistor Ts1, so that even if the first output transistor Ts1 has a negative bias, it can be adjusted back through the control of the bottom gate BG. Therefore, in the shift register unit provided in the embodiment of the present disclosure, the process margin of the first output transistor Ts1 is improved, so that the first output transistor Ts1 has the ability to be compatible with a wider range of negative bias, thereby ensuring the stability of the output gate drive signal.

[0095] As shown in Figures 9 to 13, in some embodiments, the shift register unit further includes a second output transistor Ts2, a second output control node N2 and a first level signal input terminal VGL, a gate of the second output transistor Ts2 is coupled to the second output control node N2, a first electrode of the second output transistor Ts2 is coupled to the first level signal input terminal VGL, and a second electrode of the second output transistor Ts2 is coupled to the gate drive signal output terminal OUT;

[0096] The first signal input terminal X0 includes a first clock signal input terminal GCB; the shift register unit further includes a second level signal input terminal VGL2, a third level signal input terminal VGH and a control signal debugging unit, and the control signal debugging unit includes a first debugging sub-unit 11 and a second debugging sub-unit 12;

[0097] The first debugging sub-unit 11 is coupled to the first clock signal input terminal GCB, the second output control node N2, the second level signal input terminal VGL2 and the control signal input terminal K0, respectively, and is configured to control the electrical connection between the second level signal input terminal VGL2 and the control signal input terminal K0 to be turned on or off under the control of the first clock signal input terminal GCB and the second output control node N2;

[0098] The second debugging sub-unit 12 is coupled to the first output control node N1, the third level signal input terminal VGH and the control signal input terminal K0 respectively, and is used to control the conduction or disconnection of the electrical connection between the third level signal input terminal VGH and the control signal input terminal K0 under the control of the first output control node N1.

[0099] Exemplarily, the first debugging sub-unit 11 includes a first debugging transistor T01 and a second debugging transistor T02; the second debugging sub-unit 12 includes a third debugging transistor T03; a gate of the first debugging transistor T01 is coupled to the first clock signal input terminal GCB, a first electrode of the first debugging transistor T01 is coupled to the second electrode of the second debugging transistor T02, and the second electrode of the first debugging transistor T01 is coupled to the control signal input terminal K0; a gate of the second debugging transistor T02 is coupled to the second output control node N2, a first electrode of the second debugging transistor T02 is coupled to the second level signal input terminal VGL2; a gate of the third debugging transistor T03 is coupled to the first output control node N1, a first electrode of the third debugging transistor T03 is coupled to the third level signal input terminal VGH, and a second electrode of the third debugging transistor T03 is coupled to the control signal input terminal K0.

[0100] Exemplarily, when the signal transmitted by the first output control node N1 is at an inactive level, the second debugging sub-unit 12, under the control of the first output control node N1, disconnects the electrical connection between the third-level signal input terminal VGH and the control signal input terminal K0, thereby turning off the third debug transistor T03. When the signal transmitted by the first clock signal input terminal GCB and the signal transmitted by the second output control node N2 are at active levels, the first debugging sub-unit 11, under the control of the first clock signal input terminal GCB and the second output control node N2, disconnects the electrical connection between the second-level signal input terminal VGL2 and the control signal input terminal K0, thereby turning on both the first debug transistor T01 and the second debug transistor T02, so that the potential of the control signal input terminal K0 is controlled by the second-level signal input terminal VGL2. As shown in FIG8 , as the voltage of the second-level signal input terminal VGL2 changes from -6V to -14V, the voltage of the control signal input terminal K0 correspondingly changes from -6V to -12V.

[0101] Exemplarily, when the signal transmitted by the first clock signal input terminal GCB and the signal transmitted by the second output control node N2 are at an inactive level, the first debugging sub-unit 11, under the control of the first clock signal input terminal GCB and the second output control node N2, controls the disconnection between the second level signal input terminal VGL2 and the control signal input terminal K0, i.e., the first debug transistor T01 and the second debug transistor T02 are both turned off. When the signal transmitted by the first output control node N1 is at an active level, the second debugging sub-unit 12, under the control of the first output control node N1, controls the disconnection between the third level signal input terminal VGH and the control signal input terminal K0, i.e., the third debug transistor T03 is turned on, so that the potential of the control signal input terminal K0 is controlled by the third level signal input terminal VGH.

[0102] In the shift register unit provided in the above embodiment, the control signal debugging unit can adaptively adjust the potential of the control signal input terminal K0 according to different working stages, that is, the different working states of the first output transistor Ts1, so that the potential of the second gate of the first output transistor Ts1 can be adaptively adjusted in different working stages. Therefore, the shift register unit provided in the above embodiment can adaptively adjust its characteristic curve according to the different working states of the first output transistor Ts1, while effectively improving the negative bias problem of the first output transistor Ts1, and can further improve the output stability of the gate drive signal and reduce the power consumption of the transistor.

[0103] As shown in FIG9 , FIG12 and FIG13 , in some embodiments, the shift register unit further includes: a first node control unit 21 , a second node control unit 22 , a second clock signal input terminal GCK and a start signal input terminal STV;

[0104] The first node control unit 21 is coupled to the second clock signal input terminal GCK, the first output control node N1 and the start signal input terminal STV respectively; and is used to control the electrical connection between the initial signal input terminal and the first output control node N1 to be turned on or off under the control of the second clock signal input terminal GCK;

[0105] As shown in FIG9 , the second node control unit 22 is coupled to the first clock signal input terminal GCB, the second clock signal input terminal GCK, the first level signal input terminal VGL, the third level signal input terminal VGH and the second output control node N2, respectively, and is used to control the electrical connection between the first level signal input terminal VGL and the second output control node N2 under the control of the first clock signal input terminal GCB, and to control the electrical connection between the third level signal input terminal VGH and the second output control node N2 under the control of the second clock signal input terminal GCK; or, as shown in FIG12 and FIG13 , the second node control unit 22 is coupled to the second clock signal input terminal GCK, the first output control node N1, the second output control node N2 and the third level signal input terminal VGH, respectively, and is used to control the electrical connection between the third level signal input terminal VGH and the second output control node N2 under the control of the second clock signal input terminal GCK; and to control the electrical connection between the second clock signal input terminal GCK and the second output control node N2 under the control of the first output control node N1.

[0106] Exemplarily, the first node control unit 21 includes a seventh transistor T7, a gate of the seventh transistor T7 is coupled to the second clock signal input terminal GCK, a first electrode of the seventh transistor T7 is coupled to the start signal input terminal STV, and a second electrode of the seventh transistor T7 is coupled to the first output control node N1.

[0107] Exemplarily, as shown in FIG9 , the second node control unit 22 includes a fifth transistor T5 and a sixth transistor T6. The gate of the fifth transistor T5 is coupled to the second clock signal input terminal GCK, the first electrode of the fifth transistor T5 is coupled to the third level signal input terminal VGH, and the second electrode of the fifth transistor T5 is coupled to the second output control node N2. The gate of the sixth transistor T6 is coupled to the first clock signal input terminal GCB, the first electrode of the sixth transistor T6 is coupled to the first level signal input terminal VGL, and the second electrode of the sixth transistor T6 is coupled to the second output control node N2.

[0108] As shown in Figure 10, in the P1 stage, N2 = high level, N3 = high level, N1 = high level, OUT = low level; in the P2 stage, N2 = low level, N3 = high level, N1 = high level, OUT = high level; in the P3 stage, N2 = high level, N3 = low level, N1 = low level, OUT = low level; in the P4 stage, N2 = high level, N3 = low level, N1 = low level, OUT = low level. Based on the potential conditions of the above nodes, it is possible to calculate the V of each transistor when it is working. GS Voltage.

[0109] Exemplarily, as shown in Figures 12 and 13, the second node control unit 22 includes the fifth transistor T5 and the ninth transistor T9, the gate of the ninth transistor T9 is coupled to the first output control node N1, the first electrode of the ninth transistor T9 is coupled to the second clock signal input terminal GCK, and the second electrode of the ninth transistor T9 is coupled to the second output control node N2.

[0110] Exemplarily, the shift register unit further includes an eighth transistor T8, a gate of the eighth transistor T8 coupled to the third level signal input terminal VGH, a first electrode of the eighth transistor T8 coupled to the second electrode of the seventh transistor T7, and a second electrode of the eighth transistor T8 coupled to the first output control node N1. The shift register unit further includes a fourth capacitor C4, a first plate of the fourth capacitor C4 coupled to the first output control node N1, and a second plate of the fourth capacitor C4 coupled to the gate drive signal output terminal OUT.

[0111] It should be noted that, as shown in Figure 13, when the shift register unit further includes an eighth transistor T8, the second electrode of the seventh transistor T7, the gate of the ninth transistor T9, and the second electrode of the eleventh transistor T11 are all coupled to the first output control node N1 through the eighth transistor T8.

[0112] As shown in Figure 13, in some embodiments, the first node control unit 21 is also coupled to the first clock signal input terminal GCB, the second output control node N2, and the first level signal input terminal VGL, respectively; and is used to control the conduction or disconnection of the electrical connection between the first level signal input terminal VGL and the first output control node N1 under the control of the first clock signal input terminal GCB and the second output control node N2.

[0113] Exemplarily, the first node control unit 21 further includes a tenth transistor T10 and an eleventh transistor T11. A gate of the tenth transistor T10 is coupled to the second output control node N2, a first electrode of the tenth transistor T10 is coupled to the first level signal input terminal VGL, a second electrode of the tenth transistor T10 is coupled to the first electrode of the eleventh transistor T11, a second electrode of the eleventh transistor T11 is coupled to the first output control node N1, and a gate of the eleventh transistor T11 is coupled to the first clock signal input terminal GCB.

[0114] As shown in FIG. 14 to FIG. 17 , in some embodiments, the first signal input terminal X0 includes a first level signal input terminal VGL, and the control signal input terminal K0 includes a second level signal input terminal VGL2 , wherein the second level signal input terminal VGL2 is used to input a DC second level signal;

[0115] The shift register unit also includes: a second output transistor Ts2, a second output control node N2 and a third level signal input terminal VGH, the gate of the second output transistor Ts2 is coupled to the second output control node N2, the first electrode of the second output transistor Ts2 is coupled to the third level signal input terminal VGH, and the second electrode of the second output transistor Ts2 is coupled to the gate drive signal output terminal OUT.

[0116] It should be noted that the above solution is limited to the first output transistor Ts1 having a fixed source potential, and the source voltage cannot be changed arbitrarily, otherwise V GS2 The above-mentioned configuration of the first signal input terminal X0 including the first level signal input terminal VGL enables the source of the first output transistor Ts1 to have the same fixed potential as the first level signal. By configuring the control signal input terminal K0 to include the second level signal input terminal VGL2, the voltage of the second gate can be used to adjust the characteristic curve of the first output transistor Ts1, thereby effectively improving the negative bias of the first output transistor Ts1 and reducing the fluctuation of the output gate drive signal.

[0117] In some embodiments, the shift register unit also includes a first node control unit 21, which is respectively coupled to the second output control node N2, the first level signal input terminal VGL and the first output control node N1, and is used to control the conduction or disconnection of the electrical connection between the first level signal input terminal VGL and the first output control node N1 under the control of the second output control node N2.

[0118] As shown in Figures 16 and 17, in some embodiments, the first node control unit 21 is also coupled to the second level signal input terminal VGL2; the first node control unit 21 includes: a first control transistor Tk1, the first control transistor Tk1 includes a dual-gate structure, the first gate of the first control transistor Tk1 is coupled to the second output control node N2, the second gate of the first control transistor Tk1 is coupled to the second level signal input terminal VGL2, the first electrode of the first control transistor Tk1 is coupled to the first level signal input terminal VGL, and the second electrode of the first control transistor Tk1 is coupled to the first output control node N1.

[0119] The above-mentioned setting of the first control transistor Tk1 includes a dual-gate structure, so that the characteristic curve of the first control transistor Tk1 can be adjusted by the voltage of the second gate of the first control transistor Tk1, thereby effectively improving the negative bias of the first control transistor Tk1 and improving the fluctuation of the output gate drive signal.

[0120] More specifically, Figure 17 illustrates the waveform of the gate drive signal output when the VTH of the first control transistor Tk1 is shifted from -5V to +5V after the first control transistor Tk1 is improved. It can be seen that the output gate drive signal does not fluctuate when the bias voltage is between -3V and +3V.

[0121] As shown in Figure 16, in some embodiments, the shift register unit also includes a second node control unit 22, a third clock signal input terminal CK and a start signal input terminal STV; the second node control unit 22 is coupled to the third clock signal input terminal CK, the start signal input terminal STV and the second output control node N2, respectively, and is used to control the conduction or disconnection of the electrical connection between the start signal input terminal STV and the second output control node N2 under the control of the third clock signal input terminal CK.

[0122] Exemplarily, the second node control unit 22 includes a fourteenth transistor T14, a gate of the fourteenth transistor T14 is coupled to the third clock signal input terminal CK, a first electrode of the fourteenth transistor T14 is coupled to the start signal input terminal STV, and a second electrode of the fourteenth transistor T14 is coupled to the second output control node N2.

[0123] As shown in FIG14 and FIG15 , in some embodiments, the second node control unit 22 is further coupled to the third level signal input terminal VGH; the second node control unit 22 includes: a second control transistor Tk2, a third control transistor Tk3 and a fourth control transistor Tk4;

[0124] The gate of the second control transistor Tk2 is coupled to the third clock signal input terminal CK, the first electrode of the second control transistor Tk2 is coupled to the start signal input terminal STV, and the second electrode of the second control transistor Tk2 is coupled to the first electrode of the third control transistor Tk3;

[0125] A gate of the third control transistor Tk3 is coupled to the third clock signal input terminal CK, and a second electrode of the third control transistor Tk3 is coupled to the second output control node N2.

[0126] A gate of the fourth control transistor Tk4 is coupled to the second output control node N2 , a first electrode of the fourth control transistor Tk4 is coupled to the third level signal input terminal VGH, and a second electrode of the fourth control transistor Tk4 is coupled to a first electrode of the third control transistor Tk3 .

[0127] Exemplarily, the channel width-to-length ratio of the fourth control transistor Tk4 is greater than the channel width-to-length ratio of the second control transistor Tk2; and / or the channel width-to-length ratio of the fourth control transistor Tk4 is greater than the channel width-to-length ratio of the third control transistor Tk3.

[0128] In more detail, the larger the channel width-to-length ratio of the fourth control transistor Tk4 is, the smaller the channel resistance is, which is more conducive to the leakage current being transmitted to the fourth control transistor Tk4, thereby absorbing the leakage current.

[0129] FIG15 illustrates the waveform of the gate drive signal output when the VTH Shift of the second and third control transistors Tk2 and Tk3 is shifted from -5V to +5V, when the second node control unit 22 includes a second control transistor Tk2, a third control transistor Tk3, and a fourth control transistor Tk4. It can be seen that when the bias voltage is between -4V and 2V, the fourth control transistor Tk4 can effectively absorb leakage current and output a stable gate drive signal.

[0130] In the shift register unit provided in the above embodiment, by providing the second node control unit 22 including: a second control transistor Tk2, a third control transistor Tk3, and a fourth control transistor Tk4, not only can the signal be transmitted through the second control transistor Tk2 and the third control transistor Tk3, but the leakage current signal generated by the transistor characteristic deviation can also be absorbed by the fourth control transistor Tk4 with a larger channel width-to-length ratio. In this way, even in the case of characteristic deviation of the second control transistor Tk2 and the third control transistor Tk3, the shift register unit can still output the gate drive signal normally. Therefore, in the shift register unit provided in the above embodiment, the problem of unstable output gate drive signal caused by transistor characteristic deviation and increased leakage current is effectively improved, and the normal driving of the display area is ensured, thereby ensuring the display quality of the display product.

[0131] The above-mentioned simultaneous setting of the first output transistor Ts1 and the first control transistor Tk1 to adopt a dual-gate structure allows the characteristics of the transistor to be regulated by adjusting the second level signal received by the second gate of the transistor. Even if the transistor is negatively biased, the VTH Margin can be optimized by changing the potential of the second gate, thereby ensuring the output of a stable gate drive signal.

[0132] As shown in Figures 14 and 16, in some embodiments, the first node control unit 21 is also coupled to the first level signal input terminal VGL, the third level signal input terminal VGH and the start signal input terminal STV, respectively; and is used to control the conduction or disconnection of the electrical connection between the third level signal input terminal VGH and the first output control node N1 under the control of the first level signal input terminal VGL and the start signal input terminal STV.

[0133] Exemplarily, the first node control unit 21 includes a first transistor T1, a second transistor T2, and a first capacitor C1. The gate of the first transistor T1 is coupled to the second electrode of the second transistor T2, the first electrode of the first transistor T1 is coupled to the third level signal input terminal VGH, and the second electrode of the first transistor T1 is coupled to the first output control node N1. The gate of the second transistor T2 is coupled to the start signal input terminal STV, and the first electrode of the second transistor T2 is coupled to the first level signal input terminal VGL. The first plate of the first capacitor C1 is coupled to the third clock signal input terminal CK, and the second plate of the first capacitor C1 is coupled to the gate of the first transistor T1.

[0134] Exemplarily, the shift register unit further includes a fourth transistor T4, a gate of the fourth transistor T4 coupled to the third level signal input terminal VGH, a first electrode of the fourth transistor T4 coupled to the second electrode of the first transistor T1, and a second electrode of the fourth transistor T4 coupled to the first output control node N1. The shift register unit further includes a second capacitor C2 and a third capacitor C3, a first plate of the second capacitor C2 coupled to the first output control node N1, and a second plate of the second capacitor C2 coupled to the gate drive signal output terminal OUT. A first plate of the third capacitor C3 coupled to the gate drive signal output terminal OUT, and a second plate of the third capacitor C3 coupled to the gate of the second output transistor Ts2.

[0135] As shown in Figures 18 to 27, an embodiment of the present disclosure also provides a display substrate, including the shift register unit provided in the above embodiment, the display substrate includes a display area and a peripheral area located around the display area, and the shift register unit is located in the display area and / or the peripheral area.

[0136] Exemplarily, the peripheral area surrounds the display area, but is not limited thereto.

[0137] Exemplarily, the peripheral area includes a left border area and a right border area, and the display area is located between the left border area and the right border area. The shift register unit can be arranged in the left border area and / or the right border area. The shift register unit can also be arranged in the display area.

[0138] In the shift register unit provided in the above embodiment, the first gate and the second gate can control the conduction or cutoff of the first output transistor Ts1, thereby ensuring the normal operation of the shift register unit. By adjusting the voltage of the second gate, the characteristic curve of the first output transistor Ts1 can be adjusted, thereby effectively improving the negative bias of the first output transistor Ts1 and improving the fluctuation of the output gate drive signal. In the shift register unit provided in the above embodiment, by setting the first output transistor Ts1 to include a dual-gate structure, by adjusting the voltage of the second gate Ts1-g2 of the first output transistor Ts1, the characteristic curve of the first output transistor Ts1 is regulated, so that even if the first output transistor Ts1 has a negative bias, it can be adjusted back through the control of the bottom gate BG. In the shift register unit provided in the above embodiment, the process margin of the first output transistor Ts1 is improved, so that the first output transistor Ts1 has the ability to accommodate a wider range of negative biases, thereby ensuring the stability of the output gate drive signal.

[0139] The display substrate provided by the embodiment of the present disclosure also has the above-mentioned beneficial effects when including the shift register unit provided by the above-mentioned embodiment. The display substrate can achieve higher display quality when driven by a stable gate driving signal.

[0140] As shown in FIG18 to FIG27 , in some embodiments, the shift register unit includes a control signal debugging unit, the control signal debugging unit includes a first debugging sub-unit 11 and a second debugging sub-unit 12, the first debugging sub-unit 11 includes a first debugging transistor T01 and a second debugging transistor T02; the second debugging sub-unit 12 includes a third debugging transistor T03; the shift register unit also includes a first output transistor Ts1 and a second output transistor Ts2;

[0141] The first output transistor Ts1 and the second output transistor Ts2 are arranged along a first direction; at least a portion of the third debug transistor T03, the first debug transistor T01 and the second debug transistor T02 are arranged along the first direction; the first output transistor Ts1 is located between the display area and the first debug transistor T01.

[0142] Exemplarily, the third debug transistor T03 and the first output transistor Ts1 are arranged along the second direction, the first debug transistor T01 and the first output transistor Ts1 are arranged along the second direction, and the second debug transistor T02 and the first output transistor Ts1 are arranged along the second direction.

[0143] Exemplarily, the first direction intersects the second direction. For example, the first direction includes the longitudinal direction, and the second direction includes the transverse direction.

[0144] In the above arrangement, the first output transistor Ts1 and the second output transistor Ts2 are arranged along the first direction, and at least part of the third debug transistor T03, the first debug transistor T01, and the second debug transistor T02 are arranged along the first direction. This reduces the width of the layout space occupied by the first output transistor Ts1, the second output transistor Ts2, the first debug transistor T01, the second debug transistor T02, and the third debug transistor T03 in the second direction, thereby effectively reducing the border width of the display substrate.

[0145] The above arrangement of locating the first output transistor Ts1 between the display area and the first debugging transistor T01 better plans the limited layout space and reduces the layout difficulty of the shift register unit in the limited layout space.

[0146] As shown in Figures 20 and 24, in some embodiments, the second debug transistor T02 and the second output transistor Ts2 both include a dual-gate structure, the first gate T02-g1 of the second debug transistor T02 and the first gate Ts2-g1 of the second output transistor Ts2 form an integral structure, and the second gate T02-g2 of the second debug transistor T02 and the second gate of the second output transistor Ts2 form an integral structure.

[0147] The above configuration of the second debug transistor T02 and the second output transistor Ts2 both comprising a dual-gate structure further improves the performance of the second debug transistor T02 and the second output transistor Ts2. Furthermore, forming the above structure as an integrated structure not only ensures coupling performance between the structures, but also simplifies the manufacturing process and reduces manufacturing costs.

[0148] As shown in FIG. 24 , in some embodiments, the gate T03 - g of the third debug transistor T03 and the first gate Ts1 - g1 of the first output transistor Ts1 are formed into an integrated structure.

[0149] Forming the above structure in an integrated manner not only ensures the coupling performance between the structures, but also helps to simplify the manufacturing process and reduce the manufacturing cost.

[0150] As shown in FIG. 22 and FIG. 27 , in some embodiments, the display substrate further includes a second level signal line VGL2 ′, and the second level signal line VGL2 ′ serves as a second level signal input terminal VGL2 coupled to the second debug transistor T02 ;

[0151] The first debug transistor T01 includes a first debug active layer 501 , the second debug transistor T02 includes a second debug active layer 502 , and the third debug transistor T03 includes a third debug active layer 503 ;

[0152] The orthographic projection of the second-level signal line VGL2' on the base substrate of the display substrate at least partially overlaps with the orthographic projection of the first debugging active layer 501 on the base substrate of the display substrate; and / or, the orthographic projection of the second-level signal line VGL2' on the base substrate of the display substrate at least partially overlaps with the orthographic projection of the second debugging active layer 502 on the base substrate of the display substrate; and / or, the orthographic projection of the second-level signal line VGL2' on the base substrate of the display substrate at least partially overlaps with the orthographic projection of the third debugging active layer 503 on the base substrate of the display substrate.

[0153] Exemplarily, the first debugging active layer 501 , the second debugging active layer 502 and the third debugging active layer 503 all include oxide active layers, such as IGZO active layers, but not limited thereto.

[0154] Exemplarily, the second level signal line VGL2' includes at least a portion extending along the first direction. The first debugging active layer 501 and the second debugging active layer 502 both extend along the first direction, and the third debugging active layer 503 includes a portion extending along the first direction and a portion extending along the second direction.

[0155] Illustratively, the orthographic projection of the first debugging active layer 501 on the base substrate is located inside the orthographic projection of the second-level signal line VGL2' on the base substrate. The orthographic projection of the second debugging active layer 502 on the base substrate is located inside the orthographic projection of the second-level signal line VGL2' on the base substrate. The orthographic projection of the third debugging active layer 503 on the base substrate of the display substrate partially overlaps with the orthographic projection of the second-level signal line VGL2' on the base substrate of the display substrate.

[0156] Exemplarily, the second debugging active layer 502 and the first debugging active layer 501 form an integrated structure.

[0157] The above configuration is beneficial to reducing the layout space independently occupied by the second-level signal line VGL2 ′, and is beneficial to narrowing the frame of the display substrate.

[0158] As shown in FIG18 to FIG27 , in some embodiments, the display substrate further includes a first-level signal line VGL′ and a third-level signal line VGH′; the first-level signal line VGL′ serves as a first-level signal input terminal VGL coupled to the second output transistor Ts2; the third-level signal line VGH′ serves as a third-level signal input terminal VGH coupled to the third debug transistor T03;

[0159] Along the direction close to the display area, the orthographic projection of the third level signal line VGH' on the base substrate, the orthographic projection of the first level signal line VGL' on the base substrate, and the orthographic projection of the second level signal line VGL2' on the base substrate are arranged in sequence.

[0160] Exemplarily, the first level signal line VGL' includes at least a portion extending along the first direction. The third level signal line VGH' includes at least a portion extending along the first direction.

[0161] As shown in FIG18 to FIG27 , in some embodiments, the display substrate further includes a first clock signal line GCB′, a second clock signal line GCK′, and a start signal line STV′. The first clock signal line GCB′ serves as a first clock signal input terminal GCB coupled to the first debug transistor T01. The shift register unit further includes a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and an eighth transistor T8.

[0162] The gate of the fifth transistor T5 is coupled to the second clock signal line GCK', the first electrode of the fifth transistor T5 is coupled to the third level signal line VGH', and the second electrode of the fifth transistor T5 is coupled to the gate of the second output transistor Ts2;

[0163] The gate of the sixth transistor T6 is coupled to the first clock signal line GCB', the first electrode of the sixth transistor T6 is coupled to the first level signal line VGL', and the second electrode of the sixth transistor T6 is coupled to the gate of the second output transistor Ts2;

[0164] The gate of the seventh transistor T7 is coupled to the second clock signal line GCK', the first electrode of the seventh transistor T7 is coupled to the start signal line STV', the second electrode of the seventh transistor T7 is coupled to the first electrode of the eighth transistor T8, the second electrode of the eighth transistor T8 is coupled to the gate of the first output transistor Ts1, and the gate of the eighth transistor T8 is coupled to the third level signal line VGH'; it should be noted that, in the case where the display substrate includes a plurality of cascaded shift register units, the first electrode of the seventh transistor T7 in the first-stage shift register unit is directly coupled to the start signal line STV', and the first electrodes of the seventh transistors T7 in the remaining stages of the shift register unit are all coupled to the gate drive signal output terminal OUT of the adjacent previous stage shift register unit.

[0165] The seventh transistor T7, the eighth transistor T8, the sixth transistor T6 and the fifth transistor T5 are arranged sequentially along the first direction; the orthographic projection of the seventh transistor T7 on the base substrate, the orthographic projection of the eighth transistor T8 on the base substrate, the orthographic projection of the sixth transistor T6 on the base substrate, and the orthographic projection of the fifth transistor T5 on the base substrate are all located between the orthographic projection of the third level signal line VGH' on the base substrate and the orthographic projection of the first level signal line VGL' on the base substrate.

[0166] Exemplarily, along a direction close to the display area, the start signal line STV', the second clock signal line GCK', the first clock signal line GCB' and the third level signal line VGH' are arranged in sequence.

[0167] The above-mentioned arrangement of the seventh transistor T7, the eighth transistor T8, the sixth transistor T6 and the fifth transistor T5 in sequence along the first direction reduces the width of the layout space occupied by the seventh transistor T7, the eighth transistor T8, the sixth transistor T6 and the fifth transistor T5 in the second direction, thereby effectively reducing the border width of the display substrate.

[0168] Moreover, the orthographic projection of the eighth transistor T8 on the substrate, the orthographic projection of the sixth transistor T6 on the substrate, and the orthographic projection of the fifth transistor T5 on the substrate are all located between the orthographic projection of the third level signal line VGH' on the substrate and the orthographic projection of the first level signal line VGL' on the substrate, thereby better planning the limited layout space, simplifying the layout complexity, and reducing the difficulty of layouting the shift register unit within the limited layout space while ensuring the coupling performance between the transistors and the signal lines.

[0169] In addition, in the display substrate provided by the above embodiment, the stacking design of each transistor in the shift register unit is optimized, thereby achieving efficient driving of the shift register unit.

[0170] More specifically, FIG18 illustrates the second plate C42 of the fourth capacitor C4 and the second plate C52 of the fifth capacitor C5. FIG19 illustrates the fourth capacitor C4 and the fifth capacitor C5. FIG20 illustrates the first plate C41 of the fourth capacitor C4 and the first plate C51 of the fifth capacitor C5.

[0171] As shown in Figures 21 and 22, there are illustrated a first output active layer 5s1 included in the first output transistor Ts1, a second output active layer 5s2 included in the second output transistor Ts2, a first debugging active layer 501 included in the first debugging transistor T01, a second debugging active layer 502 included in the second debugging transistor T02, a third debugging active layer 503 included in the third debugging transistor T03, a fifth active layer 55 included in the fifth transistor T5, a sixth active layer 56 included in the sixth transistor T6, a seventh active layer 57 included in the seventh transistor T7, and an eighth active layer 58 included in the eighth transistor T8.

[0172] As shown in FIG24 , the gate T01 - g of the first debugging transistor T01 , the gate T5 - g of the fifth transistor T5 , the gate T6 - g of the sixth transistor T6 , the gate T7 - ​​g of the seventh transistor T7 , and the gate T8 - g of the eighth transistor T8 are illustrated.

[0173] It should be noted that the black dots in Figure 25 represent connection holes between the first source / drain metal layer and the film layer thereunder. The black square holes in Figure 27 are used to connect the second level signal line VGL2 ′ and the seventh conductive connection portion 67 .

[0174] As shown in Figures 18 to 27, the first conductive connection portion 61 is coupled to the first electrode of the seventh transistor T7. The second conductive connection portion 62 is respectively coupled to one electrode of the third debugging transistor T03 and the gate of the eighth transistor T8. The gate of the eighth transistor T8 is coupled to the third level signal line VGH'.

[0175] The third conductive connection portion 63 is respectively coupled to the other electrode of the third debugging transistor T03 , the second gate Ts1 - g2 of the first output transistor Ts1 , and one electrode of the first debugging transistor T01 .

[0176] The fourth conductive connection portion 64 is respectively coupled to one electrode of the eighth transistor T8 and the first gate Ts1 - g1 of the first output transistor Ts1 .

[0177] The fifth conductive connection portion 65 is respectively coupled to one electrode of the sixth transistor T6 , the first plate C51 of the fifth capacitor C5 , and one electrode of the fifth transistor T5 .

[0178] The sixth conductive connection portion 66 is coupled to the first plate C51 of the fifth capacitor C5 and the first gate Ts2 - g1 of the second output transistor Ts2 .

[0179] The seventh conductive connection portion 67 is coupled to one electrode of the second debugging transistor T02 and the second level signal line VGL2 ′ respectively.

[0180] A portion of the eighth conductive connection portion 68 and the ninth conductive connection portion 69 may serve as an electrode of the first output transistor Ts1 , and another portion of the ninth conductive connection portion 69 may serve as an electrode of the second output transistor Ts2 .

[0181] It should be noted that the display substrate provided in the above embodiment includes the shift register unit structure shown in FIG9 , but is not limited thereto.

[0182] An embodiment of the present disclosure further provides a display device, comprising the display substrate provided by the above embodiment.

[0183] It should be noted that the display device can be any product or component with display function, such as a television, monitor, digital photo frame, mobile phone, tablet computer, etc., wherein the display device also includes a flexible unit board, a printed unit board and a backplane.

[0184] The display substrate provided in the above embodiment can achieve good display effects when including the above shift register unit. The display device provided in the embodiment of the present disclosure also has the above beneficial effects when including the above display substrate, which will not be described in detail here.

[0185] It should be noted that the signal line extending along the X-direction means that the signal line includes a main portion and a secondary portion connected to the main portion, the main portion is a line, a line segment, or a strip-shaped body, the main portion extends along the X-direction, and the length of the main portion extending along the X-direction is greater than the length of the secondary portion extending along other directions.

[0186] It should be noted that the "same layer" in the embodiment of the present disclosure may refer to a film layer on the same structural layer. Or, for example, a film layer in the same layer may be a film layer formed by using the same film forming process to form a specific pattern, and then patterning the film layer using the same mask through a single composition process to form a layer structure. Depending on the specific pattern, a single composition process may include multiple exposure, development or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous. These specific patterns may also be at different heights or have different thicknesses.

[0187] In the various method embodiments of the present disclosure, the serial numbers of the steps cannot be used to limit the order of the steps. For ordinary technicians in this field, without paying any creative work, changes to the order of the steps are also within the scope of protection of the present disclosure.

[0188] It should be noted that the various embodiments in this specification are described in a progressive manner. Similar parts between the various embodiments can be referred to in conjunction with each other. Each embodiment focuses on the differences from other embodiments. In particular, the method embodiments are described briefly because they are generally similar to the product embodiments. For relevant parts, refer to the description of the product embodiments.

[0189] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by persons of ordinary skill in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect", "couple" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0190] It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” or “under” another element, it can be “directly on” or “under” the other element or intervening elements may be present.

[0191] In the description of the above embodiments, specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.

[0192] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A shift register unit, comprising a first output transistor, a gate drive signal output terminal, a first output control node, a control signal input terminal and a first signal input terminal; The first output transistor includes a dual-gate structure, a first gate of the first output transistor is coupled to the first output control node, a second gate of the first output transistor is coupled to the control signal input terminal, a first electrode of the first output transistor is coupled to the first signal input terminal, and a second electrode of the first output transistor is coupled to the gate drive signal output terminal.

2. The shift register unit according to claim 1, wherein: The shift register unit further includes a second output transistor, a second output control node and a first level signal input terminal, a gate of the second output transistor is coupled to the second output control node, a first electrode of the second output transistor is coupled to the first level signal input terminal, and a second electrode of the second output transistor is coupled to the gate drive signal output terminal; The first signal input terminal includes a first clock signal input terminal; the shift register unit also includes a second level signal input terminal, a third level signal input terminal and a control signal debugging unit, and the control signal debugging unit includes a first debugging sub-unit and a second debugging sub-unit; The first debugging sub-unit is coupled to the first clock signal input terminal, the second output control node, the second level signal input terminal and the control signal input terminal respectively, and is used to control the conduction or disconnection of the electrical connection between the second level signal input terminal and the control signal input terminal under the control of the first clock signal input terminal and the second output control node; The second debugging subunit is coupled to the first output control node, the third level signal input terminal and the control signal input terminal respectively, and is used to control the conduction or disconnection of the electrical connection between the third level signal input terminal and the control signal input terminal under the control of the first output control node.

3. The shift register unit according to claim 2, wherein: The first debugging sub-unit includes a first debugging transistor and a second debugging transistor; the second debugging sub-unit includes a third debugging transistor; The gate of the first debugging transistor is coupled to the first clock signal input terminal, the first electrode of the first debugging transistor is coupled to the second electrode of the second debugging transistor, and the first debugging transistor The second electrode of the body tube is coupled to the control signal input terminal; The gate of the second debugging transistor is coupled to the second output control node, and the first electrode of the second debugging transistor is coupled to the second level signal input terminal; A gate of the third debugging transistor is coupled to the first output control node, a first electrode of the third debugging transistor is coupled to the third level signal input terminal, and a second electrode of the third debugging transistor is coupled to the control signal input terminal.

4. The shift register unit according to claim 2 or 3, wherein: The shift register unit further includes: a first node control unit, a second node control unit, a second clock signal input terminal and a start signal input terminal; The first node control unit is coupled to the second clock signal input terminal, the first output control node and the start signal input terminal respectively; and is used to control the conduction or disconnection of the electrical connection between the initial signal input terminal and the first output control node under the control of the second clock signal input terminal; The second node control unit is coupled to the first clock signal input terminal, the second clock signal input terminal, the first level signal input terminal, the third level signal input terminal and the second output control node respectively, and is used to control the electrical connection between the first level signal input terminal and the second output control node under the control of the first clock signal input terminal, and is used to control the electrical connection between the third level signal input terminal and the second output control node under the control of the second clock signal input terminal; or, the second node control unit is coupled to the second clock signal input terminal, the first output control node, the second output control node and the third level signal input terminal respectively, and is used to control the electrical connection between the third level signal input terminal and the second output control node under the control of the second clock signal input terminal; and is used to control the electrical connection between the second clock signal input terminal and the second output control node under the control of the first output control node.

5. The shift register unit according to claim 4, wherein: The first node control unit is also coupled to the first clock signal input terminal, the second output control node, and the first level signal input terminal respectively; and is used to control the conduction or disconnection of the electrical connection between the first level signal input terminal and the first output control node under the control of the first clock signal input terminal and the second output control node.

6. The shift register unit according to claim 1, wherein: The first signal input terminal includes a first level signal input terminal, the control signal input terminal includes a second level signal input terminal, and the second level signal input terminal is used to input a DC second level signal; The shift register unit also includes: a second output transistor, a second output control node and a third level signal input terminal, the gate of the second output transistor is coupled to the second output control node, the first electrode of the second output transistor is coupled to the third level signal input terminal, and the second electrode of the second output transistor is coupled to the gate drive signal output terminal.

7. The shift register unit according to claim 6, wherein: The shift register unit also includes a first node control unit, which is respectively coupled to the second output control node, the first level signal input terminal and the first output control node, and is used to control the conduction or disconnection of the electrical connection between the first level signal input terminal and the first output control node under the control of the second output control node.

8. The shift register unit according to claim 7, wherein: The first node control unit is also coupled to the second level signal input terminal; The first node control unit includes: a first control transistor, the first control transistor includes a dual-gate structure, the first gate of the first control transistor is coupled to the second output control node, the second gate of the first control transistor is coupled to the second level signal input terminal, the first electrode of the first control transistor is coupled to the first level signal input terminal, and the second electrode of the first control transistor is coupled to the first output control node.

9. The shift register unit according to claim 6, wherein: The shift register unit also includes a second node control unit, a third clock signal input terminal and a start signal input terminal; the second node control unit is coupled to the third clock signal input terminal, the start signal input terminal and the second output control node respectively, and is used to control the conduction or disconnection of the electrical connection between the start signal input terminal and the second output control node under the control of the third clock signal input terminal.

10. The shift register unit according to claim 9, wherein: The second node control unit is also coupled to the third level signal input terminal; The second node control unit includes: a second control transistor, a third control transistor and a fourth control transistor; The gate of the second control transistor is coupled to the third clock signal input terminal, the first electrode of the second control transistor is coupled to the start signal input terminal, and the second electrode of the second control transistor is coupled to the first electrode of the third control transistor; A gate of the third control transistor is coupled to the third clock signal input terminal, and a second electrode of the third control transistor is coupled to the second output control node. The gate of the fourth control transistor is coupled to the second output control node, the first electrode of the fourth control transistor is coupled to the third level signal input terminal, and the second electrode of the fourth control transistor is coupled to the first electrode of the third control transistor.

11. The shift register unit according to any one of claims 7 to 10, wherein: The first node control unit is also coupled to the first level signal input terminal, the third level signal input terminal and the start signal input terminal respectively; and is used to control the conduction or disconnection of the electrical connection between the third level signal input terminal and the first output control node under the control of the first level signal input terminal and the start signal input terminal.

12. A display substrate, comprising the shift register unit according to any one of claims 1 to 11, the display substrate comprising a display area and a peripheral area located around the display area, and the shift register unit is located in the display area and / or the peripheral area.

13. The display substrate according to claim 12, wherein: The shift register unit includes a control signal debugging unit, the control signal debugging unit includes a first debugging sub-unit and a second debugging sub-unit, the first debugging sub-unit includes a first debugging transistor and a second debugging transistor; the second debugging sub-unit includes a third debugging transistor; the shift register unit also includes a first output transistor and a second output transistor; The first output transistor and the second output transistor are arranged along a first direction; at least a portion of the third debug transistor, the first debug transistor and the second debug transistor are arranged along the first direction; the first output transistor is located between the display area and the first debug transistor.

14. The display substrate according to claim 13, wherein: The second debug transistor and the second output transistor both include a dual-gate structure, a first gate of the second debug transistor and a first gate of the second output transistor form an integral structure, and a second gate of the second debug transistor and a second gate of the second output transistor form an integral structure.

15. The display substrate according to claim 13, wherein: The gate of the third debugging transistor and the first gate of the first output transistor form an integrated structure.

16. The display substrate according to any one of claims 12 to 15, wherein: The display substrate further comprises a second level signal line, and the second level signal line is coupled to the second debugging transistor as a second level signal input terminal; The first debug transistor includes a first debug active layer, the second debug transistor includes a second debug active layer, and the third debug transistor includes a third debug active layer; The orthographic projection of the second level signal line on the base substrate of the display substrate at least partially overlaps with the orthographic projection of the first debugging active layer on the base substrate of the display substrate; And / or, the orthographic projection of the second level signal line on the base substrate of the display substrate at least partially overlaps with the orthographic projection of the second debugging active layer on the base substrate of the display substrate; And / or, the orthographic projection of the second level signal line on the base substrate of the display substrate at least partially overlaps with the orthographic projection of the third debugging active layer on the base substrate of the display substrate.

17. The display substrate according to claim 16, wherein: The display substrate further comprises a first level signal line and a third level signal line; the first level signal line is coupled to the second output transistor as a first level signal input terminal; The third level signal line is coupled to the third debugging transistor as a third level signal input terminal; Along a direction approaching the display area, an orthographic projection of the third level signal line on the base substrate, an orthographic projection of the first level signal line on the base substrate, and an orthographic projection of the second level signal line on the base substrate are arranged in sequence.

18. The display substrate according to claim 17, wherein: The display substrate further includes a first clock signal line, a second clock signal line and a start signal line, wherein the first clock signal line is coupled to the first debug transistor as a first clock signal input terminal; the shift register unit further includes a fifth transistor, a sixth transistor, a seventh transistor and an eighth transistor; The gate of the fifth transistor is coupled to the second clock signal line, the first electrode of the fifth transistor is coupled to the third level signal line, and the second electrode of the fifth transistor is coupled to the gate of the second output transistor; The gate of the sixth transistor is coupled to the first clock signal line, the first electrode of the sixth transistor is coupled to the first level signal line, and the second electrode of the sixth transistor is coupled to the gate of the second output transistor; The gate of the seventh transistor is coupled to the second clock signal line, the first electrode of the seventh transistor is coupled to the start signal line, and the second electrode of the seventh transistor is coupled to the first electrode of the eighth transistor. coupling, the second electrode of the eighth transistor is coupled to the gate of the first output transistor, and the gate of the eighth transistor is coupled to the third level signal line; The seventh transistor, the eighth transistor, the sixth transistor and the fifth transistor are arranged in sequence along the first direction; the orthographic projection of the seventh transistor on the substrate, the orthographic projection of the eighth transistor on the substrate, the orthographic projection of the sixth transistor on the substrate, and the orthographic projection of the fifth transistor on the substrate are all located between the orthographic projection of the third-level signal line on the substrate and the orthographic projection of the first-level signal line on the substrate.

19. The display substrate according to claim 18, wherein: Along a direction approaching the display area, the start signal line, the second clock signal line, the first clock signal line and the third level signal line are arranged in sequence.

20. A display device comprising the display substrate according to any one of claims 13 to 19.

Images