Gate driving circuit, display panel and display apparatus

Abstract

A gate driving circuit, a display panel and a display apparatus. The gate driving circuit comprises: a shift register unit (20) and a level control unit (10). The shift register unit (20) comprises a scan shift register and a dummy shift register; and the level control unit (10) is separately and electrically connected to a first scan input signal line (CN) and a second scan input signal line (CNB) of the scan shift register and the dummy shift register, and is configured to be driven by different control signals to input different signals to the first scan input signal line (CN) and the second scan input signal line (CNB). In this way, after transistors used for frame resetting in the scan shift register and the dummy shift register are removed, frame resetting processing of the scan shift register and the dummy shift register is performed on the basis of different conduction conditions of the level control unit, thereby reducing the number of transistors in the gate driving circuit, saving costs, and improving the panel yield.

Description

Gate drive circuit, display panel and display device

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office of China on November 29, 2023, with application number 202311615862.0 and application name “A gate drive circuit, display panel and display device”, the entire contents of which are incorporated by reference into this application. Technical Field

[0003] The present application relates to the field of display technology and provides a gate drive circuit, a display panel and a display device. Background Art

[0004] In the field of display technology, gate driver circuits are often used to replace gate management ICs to provide scan signals for display panels, thereby reducing circuit costs. Furthermore, to address the display flipping problem of the display panel during display, the gate driver circuit often employs a bidirectional scanning method. The gate driver circuit typically includes three shift registers: a dummy gate driver on array (dummy GOA1), a scanning shift register (normal gate driver on array, normal GOA), and a dummy gate driver on array (dummy GOA2). For specific circuits, see Figures 1, 2, and 3. This results in a complex shift register structure in the gate driver circuit, leading to higher display panel costs and lower panel yields.

[0005] Summary of the Invention

[0006] The embodiments of the present application provide a gate drive circuit, a display panel, and a display device for performing frame reset processing on a scanning shift register and a virtual shift register in combination with different conduction conditions of a level control unit, thereby reducing the number of tubes in the gate drive circuit, saving costs, and improving the panel yield.

[0007] The specific technical solutions provided in this application are as follows:

[0008] In a first aspect, an embodiment of the present application provides a gate driving circuit, comprising: a shift register unit and a level control unit;

[0009] The shift register unit includes a scan shift register and a dummy shift register, the scan shift register is electrically connected to the gate line and is configured to input a scan drive signal to the gate line according to the signal of the first scan input signal line and the second scan input signal line, and the dummy shift register is electrically connected to the scan shift register and is configured to input a cascade drive signal to the scan shift register according to the signal of the first scan input signal line and the second scan input signal line;

[0010] A level control unit is electrically connected to the first scan input signal line and the second scan input signal line of the scan shift register and the virtual shift register, respectively, and is configured to write the first scan control signal into the first scan input signal line of the scan shift register and the virtual shift register in response to a first control signal, write the second scan control signal into the second scan input signal line of the scan shift register and the virtual shift register, write the second scan control signal into the first scan input signal line and the second scan input signal line of the scan shift register and the virtual shift register in response to a second control signal, and write the first scan control signal into the first scan input signal line and the second scan input signal line of the scan shift register and the virtual shift register in response to a third control signal.

[0011] Optionally, the level control unit includes: a first control subunit, a second control subunit and a third control subunit;

[0012] The control end of the first control subunit is electrically connected to the first control signal line, the first end of the first control subunit is electrically connected to the first transmission line, and the second end of the first control subunit is electrically connected to the second transmission line;

[0013] a first control subunit configured to connect the first transmission line and the second transmission line in response to an active level signal of the first control signal line;

[0014] The control end of the second control subunit is electrically connected to the second control signal line, the first end of the second control subunit is electrically connected to the first transmission line, and the second end of the first control subunit is electrically connected to the first scan control signal line;

[0015] a second control subunit configured to write the first scan control into the first transmission line in response to an active level signal of the second control signal line;

[0016] The control end of the third control subunit is electrically connected to the third control signal line, the first end of the third control subunit is electrically connected to the second transmission line, and the second end of the third control subunit is electrically connected to the second scan control signal line;

[0017] The third control subunit is configured to write the second scan control into the second transmission line in response to the active level signal of the third control signal line.

[0018] Optionally, the first scan input signal line of the scan shift register and the dummy shift register is electrically connected to the first transmission line, and the second scan input signal line of the scan shift register and the dummy shift register is electrically connected to the second transmission line;

[0019] The first control signal causes the first control signal line to provide an invalid level signal, the second control signal line to provide an effective level signal, and the third control signal line to provide an effective level signal;

[0020] The second control signal causes the first control signal line to provide a valid level signal, the second control signal line to provide an invalid level signal, and the third control signal line to provide a valid level signal;

[0021] The third control signal causes the first control signal line to provide a valid level signal, the second control signal line to provide a valid level signal, and the third control signal line to provide an invalid level signal.

[0022] Optionally, the first control subunit includes: a first transistor, a control end of the first transistor is electrically connected to the first control signal line, a first end of the first transistor is electrically connected to the first transmission line, and a second end of the first transistor is electrically connected to the second transmission line.

[0023] Optionally, the second control subunit includes: a second transistor, a control end of the second transistor is electrically connected to the second control signal line, a first end of the second transistor is electrically connected to the first scan control signal, and a second end of the second transistor is electrically connected to the first transmission line.

[0024] Optionally, the third control subunit includes: a third transistor, a control end of the third transistor is electrically connected to the third control signal line, a first end of the third transistor is electrically connected to the second transmission line, and a second end of the third transistor is electrically connected to the second scan control signal.

[0025] Optionally, the shift register unit includes a plurality of scanning shift registers, and the plurality of scanning shift registers are cascaded;

[0026] The virtual shift register includes a first virtual shift register, a first input signal line of the first virtual shift register is electrically connected to a frame start signal line, a second input signal line of the first virtual shift register is electrically connected to a cascade signal output end of a first scanning shift register among a plurality of scanning shift registers, and a cascade output signal line of the first virtual shift register is electrically connected to the first input signal line of the first scanning shift register.

[0027] Optionally, the shift register unit includes a plurality of scanning shift registers, and the plurality of scanning shift registers are cascaded;

[0028] The virtual shift register includes a second virtual shift register, a first input signal line of the second virtual shift register is electrically connected to the cascade signal output end of the last scanning shift register among multiple scanning shift registers, a second input signal line of the second virtual shift register is electrically connected to the frame start signal line, and a cascade output signal line of the second virtual shift register is electrically connected to the second input signal line of the last scanning shift register.

[0029] Optionally, the scanning shift register includes:

[0030] a first input module configured to provide a signal of the first scan input signal line to the pull-up node in response to a signal of the first input signal line;

[0031] a second input module configured to provide a signal of the second scan input signal line to the pull-up node in response to a signal of the second input signal line;

[0032] A first node control module is configured to control signals of a pull-up node and a pull-down node;

[0033] A first cascade output module is configured to provide a signal of the cascade clock signal line to the cascade signal output terminal in response to a signal of the pull-up node; or to provide a signal of the first reference signal line to the cascade signal output terminal in response to a signal of the pull-down node;

[0034] The first driver output module is configured to provide the signal of the clock signal line to the driver output terminal in response to the signal of the pull-up node; or to provide the signal of the second reference signal line to the driver output terminal in response to the signal of the pull-down node.

[0035] Optionally, the first input module includes: a fourth transistor;

[0036] A control terminal of the fourth transistor is electrically connected to the first input signal line, a first terminal of the fourth transistor is electrically connected to the first scan input signal line, and a second terminal of the fourth transistor is electrically connected to the pull-up node.

[0037] Optionally, the second input module includes: a fifth transistor;

[0038] The control end of the fifth transistor is electrically connected to the second input signal line, the first end of the fifth transistor is electrically connected to the pull-up node, and the second end of the fifth transistor is electrically connected to the second scan input signal line.

[0039] Optionally, the device further comprises: a frame reset module, the frame reset module being electrically connected to the pull-up node;

[0040] The frame reset module is configured to provide a signal of the first reference signal line to the pull-up node in response to a signal of the frame start signal line.

[0041] Optionally, the frame reset module includes: a sixth transistor;

[0042] The control end of the sixth transistor is electrically connected to the frame start signal line, the first end of the sixth transistor is electrically connected to the pull-up node, and the second end of the sixth transistor is electrically connected to the first reference signal line.

[0043] Optionally, the virtual shift register includes:

[0044] a third input module configured to provide a signal of the first scan input signal line to the pull-up node in response to a signal of the first input signal line;

[0045] a fourth input module configured to provide a signal of the second scan input signal line to the pull-up node in response to a signal of the second input signal line;

[0046] A second node control module is configured to control signals of the pull-up node and the pull-down node;

[0047] A second cascade output module is configured to provide a signal of the cascade clock signal line to the cascade output signal line in response to a signal of the pull-up node; or to provide a signal of the first reference signal line to the cascade output signal line in response to a signal of the pull-down node;

[0048] The second driver output module is configured to provide the signal of the clock signal line to the driver output terminal in response to the signal of the pull-up node; or to provide the signal of the second reference signal line to the driver output terminal in response to the signal of the pull-down node.

[0049] Optionally, the third input module includes: a seventh transistor;

[0050] A control terminal of the seventh transistor is electrically connected to the first input signal line, a first terminal of the seventh transistor is electrically connected to the first scan input signal line, and a second terminal of the seventh transistor is electrically connected to the pull-up node.

[0051] Optionally, the fourth input module includes: an eighth transistor;

[0052] The control end of the eighth transistor is electrically connected to the second input signal line, the first end of the eighth transistor is electrically connected to the pull-up node, and the second end of the eighth transistor is electrically connected to the second scan input signal line.

[0053] Optionally, a compensation module is further included, and the compensation module is electrically connected to the pull-up node;

[0054] The compensation module is configured to provide a high-level compensation signal to the pull-up node in response to a signal of the compensation signal line.

[0055] Optionally, the compensation module includes a twenty-seventh transistor, a twenty-eighth transistor, a twenty-ninth transistor and a fourth capacitor;

[0056] The control terminal of the twenty-seventh transistor is electrically connected to the compensation signal line, the first terminal of the twenty-seventh transistor is electrically connected to the cascade signal output terminal, and the second terminal of the twenty-seventh transistor is electrically connected to the control terminal of the twenty-eighth transistor;

[0057] A first terminal of the twenty-eighth transistor is electrically connected to the compensation clock signal line, and a second terminal of the twenty-eighth transistor is electrically connected to the first terminal of the twenty-ninth transistor;

[0058] The control terminal of the twenty-ninth transistor is electrically connected to the compensation clock signal line, and the second terminal of the twenty-ninth transistor is electrically connected to the pull-up node;

[0059] A first end of the fourth capacitor is electrically connected to the control end of the twenty-eighth transistor, and a second end of the fourth capacitor is electrically connected to the first reference signal line.

[0060] Optionally, an auxiliary compensation module is further included, the auxiliary compensation module including a 30th transistor and a 31st transistor;

[0061] a control terminal of the 30th transistor electrically connected to the compensation clock signal line, a first terminal of the 30th transistor electrically connected to the pull-down node, and a second terminal of the 30th transistor electrically connected to the first terminal of the 31st transistor;

[0062] The control terminal of the thirty-first transistor is electrically connected to the control terminal of the twenty-eighth transistor, and the second terminal of the thirty-first transistor is electrically connected to the first reference signal line.

[0063] In a second aspect, an embodiment of the present application further provides a display panel, comprising: a plurality of gate lines and the above-mentioned gate driving circuit;

[0064] A driving output terminal of a scan shift register in the gate driving circuit is electrically connected to one gate line among the plurality of gate lines.

[0065] In a third aspect, an embodiment of the present application further provides a display device comprising the above-mentioned display panel.

[0066] In a fourth aspect, an embodiment of the present application further provides a driving method of the above-mentioned gate driving circuit, comprising:

[0067] Scanning stage: In response to a first control signal, the level control unit connects the first scan input signal line to the first scan control signal and connects the second scan input signal line to the second scan control signal; the scan shift register inputs a scan drive signal to the gate line in response to signals from the first scan input signal line and the second scan input signal line; and the dummy shift register inputs a cascade drive signal to the scan shift register in response to signals from the first scan input signal line and the second scan input signal line.

[0068] Frame reset stage: the scan shift register resets its pull-up node in response to the frame start signal line, and the virtual shift register resets its pull-up node through the signal of the first scan input signal line and / or the second scan input signal line in response to the signal of the frame start signal line; wherein the level control unit writes the second scan control signal into the first scan input signal line and the second scan input signal line of the scan shift register and the virtual shift register in response to the second control signal, or, writes the first scan control signal into the first scan input signal line and the second scan input signal line of the scan shift register and the virtual shift register in response to the third control signal.

[0069] The beneficial effects of this application are as follows:

[0070] In summary, an embodiment of the present application provides a gate drive circuit, a display panel, and a display device, wherein the gate drive circuit includes: a shift register unit and a level control unit, the shift register unit including a scan shift register and a virtual shift register, the scan shift register being electrically connected to the gate line and configured to input a scan drive signal to the gate line according to a signal of a first scan input signal line and a second scan input signal line, the virtual shift register being electrically connected to the scan shift register and configured to input a cascade drive signal to the scan shift register according to a signal of the first scan input signal line and the second scan input signal line, the level control unit being electrically connected to the first scan input signal line and the second scan input signal line of the scan shift register and the virtual shift register, respectively, and being configured to write a signal provided by the first scan control signal line into the scan shift register and the virtual shift register in response to a first control signal. The first scan input signal line of the shift register writes the signal provided by the second scan control signal line into the second scan input signal line of the scan shift register and the virtual shift register, responds to the second control signal, writes the signal provided by the second scan control signal line into the first scan input signal line and the second scan input signal line of the scan shift register and the virtual shift register, and responds to the third control signal, writes the signal provided by the first scan control signal line into the first scan input signal line and the second scan input signal line of the scan shift register and the virtual shift register. After removing the transistors for frame reset in the scan shift register and the virtual shift register, the scan shift register and the virtual shift register are frame reset in combination with the different conduction conditions of the level control unit, thereby reducing the number of tubes in the gate drive circuit, saving costs, and improving the panel yield.

[0071] Other features and advantages of the present application will be described in the following description, and in part will become apparent from the description, or will be understood by practicing the present application. The purposes and other advantages of the present application can be realized and obtained by the structures particularly pointed out in the written description, claims, and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0072] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0073] FIG1 is a schematic diagram of a dummy GOA1 in the related art;

[0074] FIG2 is a schematic diagram of a Normal GOA in the related art;

[0075] FIG3 is a schematic diagram of a dummy GOA2 in the related art;

[0076] FIG4 is a schematic diagram of electrical connections of a gate drive circuit according to an embodiment of the present application;

[0077] FIG5 is a schematic diagram of electrical connections of a gate drive circuit according to an embodiment of the present application;

[0078] FIG6 is a schematic diagram of electrical connections of a scan shift register in an embodiment of the present application;

[0079] FIG7 is a schematic diagram of the electrical connection of the circuit of the scan shift register according to an embodiment of the present application;

[0080] FIG8 is a schematic diagram of electrical connections of a virtual shift register in an embodiment of the present application;

[0081] FIG9 is a schematic diagram of the electrical connection of the circuit of the first virtual shift register in an embodiment of the present application;

[0082] FIG10 is a schematic diagram of the electrical connection of the circuit of the second virtual shift register in an embodiment of the present application;

[0083] FIG11 is a simulation waveform diagram of a gate drive circuit according to an embodiment of the present application;

[0084] FIG12 is a schematic diagram of the electrical connection of another scanning shift register unit according to an embodiment of the present application;

[0085] FIG13 is a schematic diagram of electrical connections of another first virtual shift register in the related art;

[0086] FIG14 is a schematic diagram of electrical connections of another circuit of a second virtual shift register according to an embodiment of the present application;

[0087] FIG15 is a flow chart of a driving method of a gate driving circuit in an embodiment of the present application. DETAILED DESCRIPTION

[0088] To make the purpose, technical solutions, and advantages of the embodiments of this application more clear, the technical solutions of this application will be clearly and completely described below in conjunction with the drawings in the embodiments of this application. Obviously, the described embodiments are part of the embodiments of the technical solutions of this application, but not all of them. Based on the embodiments described in this application document, all other embodiments obtained by ordinary technicians in this field without making creative efforts shall fall within the scope of protection of the technical solutions of this application.

[0089] The terms "first," "second," and the like in the description and claims of the present invention and the accompanying drawings are used to distinguish similar objects and are not necessarily used to describe a particular order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate, such that the embodiments of the present invention described herein can be practiced using orders other than those illustrated or described herein.

[0090] The preferred embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0091] 4 , a gate driving circuit proposed in an embodiment of the present application includes a level control unit 10 and a shift register unit 20 .

[0092] 5 , the level control unit 10 is electrically connected to the first scan input signal line CN and the second scan input signal line CNB of the scan shift register and the dummy shift register, respectively, and is configured to write the first scan control signal CN1 into the first scan input signal line CN of the scan shift register and the dummy shift register, and write the second scan control signal CNB1 into the second scan input signal line CNB of the scan shift register and the dummy shift register in response to a first control signal; write the second scan control signal CNB1 into the first scan input signal line CN and the second scan input signal line CNB of the scan shift register and the dummy shift register in response to a second control signal; and write the first scan control signal CN1 into the first scan input signal line CN and the second scan input signal line CNB of the scan shift register and the dummy shift register in response to a third control signal.

[0093] It should be noted that, during the forward scanning process, the first scanning control signal CN1 is high and the second scanning control signal CNB1 is low; during the reverse scanning process, the first scanning control signal CN1 is low and the second scanning control signal CNB1 is high.

[0094] When the gate drive circuit is in forward scanning, during the process of scanning the current frame, the level control unit 10, in response to the first control signal, connects the first scan input signal line CN of the scan shift register and the dummy shift register to the first scan control signal CN1, and connects the second scan input signal line CNB of the scan shift register and the dummy shift register to the second scan control signal CNB1. That is, the level control unit 10 provides a high-level signal for the first scan control signal CN1 and a low-level signal for the second scan control signal CNB1. It should be noted that the first control signal causes the first control signal line A1 to provide an inactive level signal, that is, the first transistor T1 is turned off, the second control signal line A2 to provide an active level signal, that is, the second transistor T2 is turned on, and the third control signal line A3 to provide an active level signal, that is, the third transistor T3 is turned on.

[0095] After scanning the current frame and before scanning the next frame, the level control unit 10, in response to the second control signal, connects the first scan input signal line CN and the second scan input signal line CNB of the scan shift register and the dummy shift register to the second scan control signal CNB1. That is, during the frame reset process, the second scan control signal CNB1 provides a low-level signal for the first scan control signal CN1 and the second scan control signal CNB1. It should be noted that the second control signal causes the first control signal line A1 to provide an active-level signal, which turns on the first transistor T1; the second control signal line A2 to provide an inactive-level signal, which turns off the second transistor T2; and the third control signal line A3 to provide an active-level signal, which turns on the third transistor T3.

[0096] When the gate drive circuit is in reverse scanning, during the process of scanning the current frame image, the level control unit 10 responds to the first control signal to connect the first scanning input signal line CN of the scanning shift register and the virtual shift register with the first scanning control signal CN1, and connects the second scanning input signal line CNB of the scanning shift register and the virtual shift register with the second scanning control signal CNB1, that is, the level control unit 10 provides a low-level signal to the first scanning control signal line CN1 and provides a high-level signal to the second scanning control signal line CNB1.

[0097] After scanning the current frame and before scanning the next frame, the level control unit 10, in response to the third control signal, connects the first scan input signal line CN and the second scan input signal line CNB of the scan shift register and the dummy shift register to the first scan control signal CN1. That is, during the frame reset process, the first scan control signal CN1 provides a low-level signal for the first scan control signal CN1 and the second scan control signal CNB1. It should be noted that the third control signal causes the first control signal line A1 to provide an active-level signal, which turns on the first transistor T1; the second control signal line A2 to provide an active-level signal, which turns on the second transistor T2; and the third control signal line A3 to provide an inactive-level signal, which turns off the third transistor T3.

[0098] The level control unit 10 is described in detail below. The level control unit 10 includes a first control subunit 110 , a second control subunit 120 and a third control subunit 130 .

[0099] The control end of the first control subunit 110 is electrically connected to the first control signal line A1 , the first end of the first control subunit 110 is electrically connected to the first transmission line, and the second end of the first control subunit 110 is electrically connected to the second transmission line.

[0100] The first control sub-unit 110 is configured to connect the first transmission line and the second transmission line in response to an active level signal of the first control signal line A1.

[0101] In the embodiment of the present application, the first control subunit 110 mainly acts as a switch. When the first control signal line A1 provides a valid level signal, the first control subunit 110 connects the first transmission line and the second transmission line. Obviously, in this case, the signals in the first transmission line and the second transmission line are the same signal.

[0102] It should be supplemented that the first scan input signal line CN of the scan shift register and the dummy shift register is electrically connected to the first transmission line, and the second scan input signal line CNB of the scan shift register and the dummy shift register is electrically connected to the second transmission line.

[0103] In the embodiment of the present application, the signal of the first scan input signal line CN of the scan shift register and the virtual shift register is provided by the first transmission line, and the signal of the second scan input signal line CNB of the scan shift register and the virtual shift register is provided by the second transmission line.

[0104] Exemplarily, referring to FIG5 , the first control subunit 110 includes: a first transistor T1, a control end of the first transistor T1 electrically connected to the first control signal line A1, a first end of the first transistor T1 electrically connected to the first transmission line, and a second end of the first transistor T1 electrically connected to the second transmission line.

[0105] During implementation, when the first control signal line A1 provides an effective level signal, the first transistor T1 is turned on, and the first transmission line is connected to the second transmission line, that is, the first transmission line and the second transmission line transmit the same signal.

[0106] The control end of the second control subunit 120 is electrically connected to the second control signal line A2 , the first end of the second control subunit 120 is electrically connected to the first transmission line, and the second end of the first control subunit 110 is electrically connected to the first scan control signal CN1 .

[0107] The second control sub-unit 120 is configured to write the first scan control signal CN1 into the first transmission line in response to the active level signal of the second control signal line A2.

[0108] In the embodiment of the present application, the second control subunit 120 mainly transmits the first scan control signal CN1 to the first transmission line. When the second control signal line A2 provides a valid level signal, the first scan control signal CN1 is transmitted to the first transmission line via the second control subunit 120.

[0109] Exemplarily, referring to Figure 5, the second control subunit 120 includes: a second transistor T2, the control end of the second transistor T2 is electrically connected to the second control signal line A2, the first end of the second transistor T2 is electrically connected to the first scan control signal CN1, and the second end of the second transistor T2 is electrically connected to the first transmission line.

[0110] During implementation, when the second control signal line A2 provides an effective level signal, the second transistor T2 is turned on, and the first scan control signal CN1 is transmitted to the first transmission line via the turned-on second transistor T2.

[0111] The control end of the third control subunit 130 is electrically connected to the third control signal line A3 , the first end of the third control subunit 130 is electrically connected to the second transmission line, and the second end of the third control subunit 130 is electrically connected to the second scan control signal CNB1 .

[0112] The third control sub-unit 130 is configured to write the second scan control signal CNB1 into the second transmission line in response to the active level signal of the third control signal line A3.

[0113] In the embodiment of the present application, the third control subunit 130 mainly transmits the signal provided by the second scanning control signal line CNB1 to the second transmission line. When the third control signal line A3 provides a valid level signal, the signal provided by the second scanning control signal line CNB1 is transmitted to the second transmission line via the third control subunit 130.

[0114] Exemplarily, referring to Figure 5, the third control subunit 130 includes: a third transistor T3, the control end of the third transistor T3 is electrically connected to the third control signal line A3, the first end of the third transistor T3 is electrically connected to the second transmission line, and the second end of the third transistor T3 is electrically connected to the second scan control signal CNB1.

[0115] During implementation, when the third control signal line A3 provides an effective level signal, the third transistor T3 is turned on, and the second scan control signal CNB1 is transmitted to the second transmission line via the turned-on third transistor T3.

[0116] In addition, it should be noted that the first control signal causes the first control signal line A1 to provide an invalid level signal, the second control signal line A2 to provide an effective level signal, and the third control signal line A3 to provide an effective level signal.

[0117] That is, during the forward scanning process, when the gate drive circuit inputs the scanning drive signal to the gate line, the second control signal line A2 provides a valid level signal, the second transistor T2 is turned on, and the first scanning control signal CN1 provides a high level signal for the first scanning input signal line CN of the scanning shift register and the virtual shift register; the third control signal line A3 provides a valid level signal, the third transistor T3 is turned on, and the second scanning control signal CNB1 provides a low level signal for the second scanning input signal line CNB of the scanning shift register and the virtual shift register.

[0118] During the reverse scanning process, when the gate drive circuit inputs a scan drive signal to the gate line, the second control signal line A2 provides a valid level signal, the second transistor T2 is turned on, and the first scan control signal CN1 provides a low level signal for the first scan input signal line CN of the scan shift register and the virtual shift register; the third control signal line A3 provides a valid level signal, the third transistor T3 is turned on, and the second scan control signal CNB1 provides a high level signal for the second scan input signal line CNB of the scan shift register and the virtual shift register.

[0119] The second control signal causes the first control signal line A1 to provide a valid level signal, the second control signal line A2 to provide an invalid level signal, and the third control signal line A3 to provide a valid level signal.

[0120] That is, during forward scanning, after scanning the current frame and during the frame reset process before scanning the next frame, the third control signal line A3 provides a valid level signal, the third transistor T3 is turned on, and the second scan control signal CNB1 provides a low level signal for the second scan input signal line CNB of the scan shift register and the virtual shift register. The first control signal line A1 provides a valid level signal, the first transistor T1 is turned on, the above-mentioned first transmission line and the second transmission line are turned on, and the low level signal is provided to the first transmission line via the second transmission line, and then provided to the first scan input signal line CN of the scan shift register and the virtual shift register, that is, the signal accessed by the first scan input signal line CN is a low level signal.

[0121] The third control signal causes the first control signal line A1 to provide an active level signal, the second control signal line A2 to provide an active level signal, and the third control signal line A3 to provide an inactive level signal.

[0122] That is, during reverse scanning, after scanning the current frame and during the frame reset process before scanning the next frame, the second control signal line A2 provides a valid level signal, the second transistor T2 is turned on, and the first scan control signal CN1 provides a low level signal for the first scan input signal line CN of the scan shift register and the virtual shift register. The first control signal line A1 provides a valid level signal, the first transistor T1 is turned on, the above-mentioned first transmission line and the second transmission line are turned on, and the low level signal is provided to the second transmission line via the first transmission line, and then provided to the second scan input signal line CNB of the scan shift register and the virtual shift register, that is, the signal in the second scan input signal line CNB is a low level signal.

[0123] In an embodiment of the present application, the shift register unit 20 includes a scanning shift register and a virtual shift register. The scanning shift register is electrically connected to the gate line and is configured to input a scanning drive signal to the gate line according to the signal of the first scanning input signal line CN and the second scanning input signal line CNB. The virtual shift register is electrically connected to the scanning shift register and is configured to input a cascade drive signal to the scanning shift register according to the signal of the first scanning input signal line CN and the second scanning input signal line CNB.

[0124] During implementation, the scan shift register is electrically connected to a corresponding gate line. During forward scanning and reverse scanning of the display panel, the scan shift register can input a scan drive signal to the gate line according to the signal provided by the first scan input signal line CN and the second scan input signal line CNB.

[0125] In order to ensure the normal operation of the above-mentioned scanning shift register, a virtual shift register is also provided in the embodiment of the present application. During implementation, the virtual shift register inputs a cascade drive signal to the scanning shift register based on the signals provided by the first scanning input signal line CN and the second scanning input signal line CNB.

[0126] Typically, there are at least two virtual shift registers, one of which is arranged in a row before the first row of scanning shift registers, and the virtual shift register inputs a cascade drive signal to the scanning shift register of the first row, and the above-mentioned cascade drive signal serves as the input signal of the scanning shift register of the first row, so that the scanning shift register of the first row can start working as soon as possible; the other virtual shift register is arranged in a row after the last row of scanning shift registers, and the virtual shift register inputs a cascade drive signal to the scanning shift register of the last row, and the above-mentioned cascade drive signal serves as the reset signal of the scanning shift register of the last row, so that the scanning shift register of the last row clears the data after the data of this row is displayed.

[0127] In the embodiment of the present application, the transistors originally provided in the scanning shift register and the virtual shift register for frame reset are omitted, thereby saving costs and improving the panel yield. However, in order to enable the scanning shift register and the virtual shift register to clear the data after the display of the current frame data is completed, a level control unit 10 is provided, that is, the level control unit 10 cooperates with the scanning shift register and the virtual shift register after the transistors for frame reset are removed to complete the work of inputting the scanning drive signal to the gate line, which includes resetting the gate drive circuit before the scanning of the next frame of the picture begins.

[0128] The shift register unit 20 is introduced below:

[0129] (1) The shift register unit 20 in the embodiment of the present application includes a plurality of scanning shift registers, and the plurality of scanning shift registers are cascaded.

[0130] The above-mentioned multiple cascaded scanning shift registers are driven row by row, providing scanning driving signals to the gate lines corresponding to each row of pixel units respectively. The scanning shift register of the previous row also outputs cascade signals to the scanning shift register of the next row. The working process of the multiple scanning shift registers is not repeated here.

[0131] The virtual shift register in the embodiment of the present application includes a first virtual shift register, the first input signal line of the first virtual shift register is electrically connected to the frame start signal line STU, the second input signal line of the first virtual shift register is electrically connected to the cascade signal output end of the first scanning shift register among multiple scanning shift registers, and the cascade output signal line of the first virtual shift register is electrically connected to the first input signal line of the first scanning shift register.

[0132] That is, the first case: when at least one virtual shift register (that is, the first virtual shift register) is arranged before the scanning shift register of the first row, the signal of the frame start signal line STU is provided to the first input signal line of the first virtual shift register to prompt the cascade output signal line of the first virtual shift register to output the signal.

[0133] The cascade output signal line of the first virtual shift register is electrically connected to the first input signal line of the first scanning shift register. That is, the signal of the cascade output signal line of the first virtual shift register serves as the signal of the first input signal line of the first scanning shift register, so that the first scanning shift register starts the scanning process.

[0134] The reset signal line of the first virtual shift register, i.e., the second input signal line, is electrically connected to the cascade signal output end of the first scanning shift register among the multiple scanning shift registers, and the signal of the cascade signal output end of the first scanning shift register provides the first virtual shift register with a signal for resetting the row.

[0135] (2) The shift register unit 20 includes a plurality of scanning shift registers, which are cascaded.

[0136] The above-mentioned multiple cascaded scanning shift registers are driven row by row, providing scanning driving signals to the gate lines corresponding to each row of pixel units respectively. The scanning shift register of the previous row also outputs cascade signals to the scanning shift register of the next row. The working process of the multiple scanning shift registers is not repeated here.

[0137] The virtual shift register includes a second virtual shift register, the first input signal line of the second virtual shift register is electrically connected to the cascade signal output end of the last scanning shift register among multiple scanning shift registers, the second input signal line of the second virtual shift register is electrically connected to the frame start signal line STU, and the cascade output signal line of the second virtual shift register is electrically connected to the second input signal line of the last scanning shift register.

[0138] That is the second situation: when at least one virtual shift register (i.e., the second virtual shift register) is provided after the scanning shift register in the last row, the cascade signal output end of the last scanning shift register among the multiple scanning shift registers provides the signal of the first input signal line to the second virtual shift register, so that the second virtual shift register starts working.

[0139] The signal of the cascade output signal line of the second virtual shift register is used to provide a signal for the second input signal line of the last scanning shift register, so that the last scanning shift register is used for resetting the row.

[0140] The reset signal line of the second virtual shift register, ie, the second input signal line, is electrically connected to the frame start signal line STU, and the signal of the frame start signal line STU provides the second virtual shift register with a signal for frame reset.

[0141] Next, the structure of a single scanning shift register is introduced. For the sake of simplicity, the working process of the scanning shift register is described in detail using forward scanning as an example. As shown in FIG6 , the scanning shift register includes:

[0142] The first input module 101 is configured to respond to the first input signal line CR <n-1>The signal of the first scan input signal line CN is provided to the pull-up node Q1.

[0143] Exemplarily, referring to FIG. 7 , the first input module 101 includes: a fourth transistor T4 .

[0144] The control terminal of the fourth transistor T4 is connected to the first input signal line CR <n-1>A first end of the fourth transistor T4 is electrically connected to the first scan input signal line CN, and a second end of the fourth transistor T4 is electrically connected to the pull-up node Q1.

[0145] During the implementation, when the first input signal line CR <n-1>When the signal of the first scan input signal line CN is at a high level, the fourth transistor T4 is turned on, and the signal of the first scan input signal line CN is provided to the pull-up node Q1, that is, the high level signal is written into the pull-up node Q1.

[0146] The second input module 102 is configured to respond to the second input signal line CR<N+1> The signal of the second scan input signal line CNB is provided to the pull-up node Q1.

[0147] Exemplarily, referring to FIG. 7 , the second input module 102 includes a fifth transistor T5 .

[0148] The control terminal of the fifth transistor T5 is connected to the second input signal line CR<N+1> A first end of the fifth transistor T5 is electrically connected to the pull-up node Q1 , and a second end of the fifth transistor T5 is electrically connected to the second scan input signal line CNB.

[0149] During the implementation, when the second input signal line CR<N+1> When a high-level signal is provided, the fifth transistor T5 is turned on, and the signal in the second scan input signal line CNB is provided to the pull-up node Q1 , and a low-level signal is written into the pull-up node Q1 .

[0150] The first node control module 103 is configured to control signals of the pull-up node Q1 and the pull-down node QB1 .

[0151] Exemplarily, referring to FIG. 7 , the first node control module 103 includes: a ninth transistor T9 , a tenth transistor T10 , an eleventh transistor T11 , a twelfth transistor T12 , and a thirteenth transistor T13 .

[0152] A control terminal of the ninth transistor T9 is electrically connected to the pull-up node Q1 , a first terminal of the ninth transistor T9 is electrically connected to the pull-down node QB1 , and a second terminal of the ninth transistor T9 is electrically connected to the first reference signal line VGL1 .

[0153] During implementation, when the pull-up node Q1 is at a high level, the ninth transistor T9 is turned on, and the low level provided by the first reference signal line VGL1 is provided to the pull-down node QB1 via the turned-on ninth transistor T9, and a low level signal is written into the pull-down node QB1.

[0154] A control terminal of the tenth transistor T10 is electrically connected to the pull-down node, a first terminal of the tenth transistor T10 is electrically connected to the pull-up node Q1 , and a second terminal of the tenth transistor T10 is electrically connected to the first reference signal line VGL1 .

[0155] During implementation, when the pull-down node QB1 is at a high level, the tenth transistor T10 is turned on, and the low level provided by the first reference signal line VGL1 is provided to the pull-up node Q1 via the turned-on tenth transistor T10, so that a low level signal is written into the pull-up node Q1, thereby achieving reset after the row scan is completed.

[0156] A control terminal of the eleventh transistor T11 is electrically connected to the power signal line VDD, a first terminal of the eleventh transistor T11 is electrically connected to the power signal line VDD, and a second terminal of the eleventh transistor T11 is electrically connected to the pull-down node.

[0157] During the implementation process, except for the stage where the pull-up node Q1 is at a high level and the pull-down node QB1 is at a low level, the above-mentioned power signal line VDD is at a high level, thereby turning on the eleventh transistor T11, and the high level provided by the power signal line VDD is provided to the pull-down node QB1, that is, the pull-down node QB1 is written with a high level.

[0158] The control terminal of the twelfth transistor T12 is connected to the first input signal line CR of the scan shift register. <n-1>A first end of the twelfth transistor T12 is electrically connected to the pull-down node QB1 , and a second end of the twelfth transistor T12 is electrically connected to the second scan input signal line CNB.

[0159] During the implementation process, the first input signal line CR of the scanning shift register is <n-1>When a high level signal is provided, the twelfth transistor T12 is turned on, and the low level signal provided by the second scan input signal line CNB is provided to the pull-down node QB1 through the turned-on twelfth transistor T12, so that the low level signal is written into the pull-down node QB1.

[0160] The control terminal of the thirteenth transistor T13 is connected to the second input signal line CR of the scan shift register.<N+1> A first end of the thirteenth transistor T13 is electrically connected to the pull-down node QB1 , and a second end of the thirteenth transistor T13 is electrically connected to the first scan input signal line CN.

[0161] During the implementation, when the second input signal line CR of the scanning shift register is<N+1> When the voltage is high, the thirteenth transistor T13 is turned on, and the high-level signal provided by the first scan input signal line CN is provided to the pull-down node QB1 via the turned-on thirteenth transistor T13, so that the high-level signal is written into the pull-down node QB1.

[0162] The first cascade output module 104 is configured to provide the signal of the cascade clock signal line CLKD_1 to the cascade signal output terminal cr in response to the signal of the pull-up node Q1. <n>Or, in response to the signal of the pull-down node QB1, the signal of the first reference signal line VGL1 is provided to the cascade signal output terminal cr <n>.

[0163] Exemplarily, referring to FIG. 7 , the first cascade output module 104 includes a fourteenth transistor T14 and a fifteenth transistor T15 .

[0164] The control end of the fourteenth transistor T14 is electrically connected to the pull-up node Q1, the first end of the fourteenth transistor T14 is electrically connected to the cascade clock signal line CLKD_1, and the second end of the fourteenth transistor T14 is electrically connected to the cascade signal output end cr <n>Electrical connection.

[0165] During the implementation process, when the pull-up node Q1 is a high level signal, the fourteenth transistor T14 is turned on, and the high level signal provided by the cascade clock signal line CLKD_1 is written into the cascade signal output terminal cr through the turned-on fourteenth transistor T14. <n>.

[0166] The control terminal of the fifteenth transistor T15 is electrically connected to the pull-down node QB1, and the first terminal of the fifteenth transistor T15 is electrically connected to the cascade signal output terminal cr <n>A second end of the fifteenth transistor T15 is electrically connected to the first reference signal line VGL1 .

[0167] During the implementation process, when the pull-down node QB1 is a high level signal, the fifteenth transistor T15 is turned on, and the low level signal provided by the first reference signal line VGL1 is written into the cascade signal output terminal cr through the turned-on fifteenth transistor T15. <n>, to cascade signal output terminal cr <n>Perform a reset.

[0168] The first driver output module 105 is configured to provide the signal provided by the clock signal line CLKE_1 to the driver output terminal OUT1 in response to the signal of the pull-up node Q1. <n>Or, in response to the signal of the pull-down node QB1, the signal of the second reference signal line VGL2 is provided to the driving output terminal OUT1 <n>.

[0169] Exemplarily, referring to FIG. 7 , the first driving output module 105 includes a sixteenth transistor T16 , a seventeenth transistor T17 and a first capacitor c1 .

[0170] The control end of the sixteenth transistor T16 is electrically connected to the pull-up node Q1, the first end of the sixteenth transistor T16 is electrically connected to the clock signal line CLKE_1, and the second end of the sixteenth transistor T16 is electrically connected to the driving output end OUT1. <n>Electrical connection.

[0171] During the implementation process, when the pull-up node Q1 is a high-level signal, the sixteenth transistor T16 is turned on, and the high-level signal provided by the clock signal line CLKE_1 is written into the driving output terminal OUT1 through the turned-on sixteenth transistor T16. <n>.

[0172] The control terminal of the seventeenth transistor T17 is electrically connected to the pull-down node QB1, and the first terminal of the seventeenth transistor T17 is electrically connected to the driving output terminal OUT1. <n>The second end of the seventeenth transistor T17 is electrically connected to the second reference signal line VGL2.

[0173] During the implementation process, when the signal of the pull-down node QB1 is at a high level, the seventeenth transistor T17 is turned on, and the low level signal provided by the second reference signal line VGL2 is written into the driving output terminal OUT1 through the turned-on seventeenth transistor T17. <n>, driving output terminal OUT1 <n>A low level signal may be provided to the gate line.

[0174] In the embodiment of the present application, the first end of the first capacitor c1 is electrically connected to the pull-up node Q1, and the second end of the first capacitor c1 is electrically connected to the driving output terminal OUT1. <n>When the fourth transistor T4 is turned on, a high level can be transmitted to the pull-up node Q1, thereby increasing the voltage of the pull-up node Q1 and charging the first capacitor C1. When the fourth transistor T4 is turned off, the first capacitor C1 can be discharged, so that the pull-up node Q1 maintains a high level, thereby keeping the sixteenth transistor T16 in the on state.

[0175] In addition, when the sixteenth transistor T16 is turned on and the signal provided by the clock signal line CLKE_1 changes from a high level to a low level, the output terminal OUT1 is driven. <n>The output is low level. At the same time, due to the bootstrap effect of the first capacitor c1, the voltage of the pull-up node Q1 will also drop.

[0176] It should be noted that after scanning a frame of picture, the gate drive circuit needs to be reset to avoid affecting the display of the next frame of picture. For this purpose, the above-mentioned scanning shift register also includes: a frame reset module, which is electrically connected to the pull-up node.

[0177] The frame reset module is configured to provide a signal of the first reference signal line VGL1 to the pull-up node Q1 in response to a signal of the frame start signal line STU.

[0178] Exemplarily, referring to FIG. 7 , the frame resetting module includes: a sixth transistor T6 .

[0179] A control end of the sixth transistor T6 is electrically connected to the frame start signal line STU, a first end of the sixth transistor T6 is electrically connected to the pull-up node Q1 , and a second end of the sixth transistor T6 is electrically connected to the first reference signal line VGL1 .

[0180] During implementation, after a frame of picture is scanned, the frame start signal line STU provides a high-level signal, so that the sixth transistor T6 is turned on, and the low-level signal provided by the first reference signal line VGL1 is written into the pull-up node Q1, thereby resetting the pull-up node Q1 after a frame of picture is scanned.

[0181] Since the shift register unit 20 provided in the embodiment of the present invention can realize bidirectional scanning, during reverse scanning, the functions of the first input module 101 and the second input module 102 of the scanning shift register are interchanged, that is, during forward scanning, the first input module 101 serves as an input module, and the first input signal line serves as an input signal line. The gate drive circuit, when realizing reverse scanning of the gate line, interchanges the functions of the first input module 101 and the second input module 102 of each scanning shift register, during reverse scanning, the second input module 102 of each scanning shift register serves as an input module, and the second input signal line serves as an input signal line, and the first input module 101 of each scanning shift register serves as a reset module, and the first input signal line serves as a reset signal line. At this time, the electrical connection relationship of the circuit does not change, but the circuit function changes.

[0182] Next, the composition of a single virtual shift register is introduced. For the sake of simplicity, the working process of the following virtual shift register is described in detail using forward scanning as an example. As shown in FIG8 , the virtual shift register includes:

[0183] The third input module 201 is configured to provide the signal of the first scan input signal line CN to the pull-up node Q2 of the first dummy shift register or the pull-up node Q3 of the second dummy shift register in response to the signal of the first input signal line STU.

[0184] Exemplarily, referring to FIG. 9 , the third input module 201 includes: a seventh transistor T7 .

[0185] A control end of the seventh transistor T7 is electrically connected to the first input signal line STU, a first end of the seventh transistor T7 is electrically connected to the first scan input signal line CN, and a second end of the seventh transistor T7 is electrically connected to the pull-up node Q2.

[0186] During implementation, when the signal provided by the first input signal line is at a high level, the seventh transistor T7 is turned on, and the high level signal provided by the first scan input signal line CN is written into the pull-up node Q2 via the turned-on seventh transistor T7, causing the pull-up node Q2 to be at a high level. It should be noted that when the virtual shift register is the first virtual shift register, the first input signal line is electrically connected to the frame start signal line STU; when the virtual shift register is the second virtual shift register, the first input signal line is electrically connected to the cascade signal output terminal CR of the last scan shift register. <n-1>For electrical connections, see Figure 10.

[0187] The fourth input module 202 is configured to respond to the second input signal line CR<N+1> The signal of the second scan input signal line CNB is provided to the pull-up node Q2.

[0188] Exemplarily, referring to FIG. 9 , the fourth input module 202 includes an eighth transistor T8 .

[0189] The control terminal of the eighth transistor T8 is connected to the second input signal line CR<N+1> The first end of the eighth transistor T8 is electrically connected to the pull-up node Q2, and the second end of the eighth transistor T8 is electrically connected to the second scan input signal line CNB.

[0190] During the implementation process, the second input signal line CR<N+1> When the signal of is high, the eighth transistor T8 is turned on, and the low level provided by the second scan input signal line CNB causes the pull-up node Q2 to be written to a low level, thereby resetting the pull-up node Q2. It should be noted that when the virtual shift register is the first virtual shift register, the second input signal line and the cascade signal output terminal CR of the first scan shift register are connected.<N+1> when the virtual shift register is a second virtual shift register, the second input signal line is electrically connected to the frame start signal line STU.

[0191] The second node control module 203 is configured to control the signals of the pull-up node and the pull-down node.

[0192] Exemplarily, referring to FIG. 9 , the second node control module 203 includes an eighteenth transistor T18 , a nineteenth transistor T19 , a twentieth transistor T20 , a twenty-first transistor T21 , and a twenty-second transistor T22 .

[0193] The electrical connection relationship and conduction status of each of the above transistors will be described in detail below with reference to FIG. 9 .

[0194] A control end of the eighteenth transistor T18 is electrically connected to the pull-up node of the virtual shift register, a first end of the eighteenth transistor T18 is electrically connected to the pull-down node of the virtual shift register, and a second end of the eighteenth transistor T18 is electrically connected to the first reference signal line VGL1 of the virtual shift register.

[0195] During implementation, when the pull-up node Q2 of the virtual shift register is at a high level, the eighteenth transistor T18 is turned on, and the low level provided by the first reference signal line VGL1 is written into the pull-up node Q2 via the turned-on eighteenth transistor T18, making the pull-down node QB2 of the virtual shift register at a low level.

[0196] The control end of the nineteenth transistor T19 is electrically connected to the pull-down node QB2 of the virtual shift register, the first end of the nineteenth transistor T19 is electrically connected to the pull-up node Q2 of the virtual shift register, and the second end of the nineteenth transistor T19 is electrically connected to the first reference signal line VGL1 of the virtual shift register.

[0197] During the implementation process, when the pull-down node QB2 of the virtual shift register is at a high level, the nineteenth transistor T19 is turned on, and the low level of the first reference signal line VGL1 of the virtual shift register is provided to the pull-up node Q2 through the turned-on nineteenth transistor T19, so that the pull-up node Q2 of the virtual shift register is at a low level, thereby achieving reset after the current row scan is completed.

[0198] The control terminal of the twentieth transistor T20 is electrically connected to the power signal line VDD of the dummy shift register, the first terminal of the twentieth transistor T20 is electrically connected to the power signal line VDD of the dummy shift register, and the second terminal of the twentieth transistor T20 is electrically connected to the pull-down node QB2 of the dummy shift register.

[0199] During the implementation process, except for the stage where the pull-up node Q2 of the virtual shift register is at a high level and the pull-down node QB2 is at a low level, the above-mentioned power signal line VDD is at a high level, thereby turning on the twentieth transistor T20, and the high level of the power signal line VDD causes the pull-down node QB2 of the virtual shift register to be at a high level.

[0200] 9 , the control end of the twenty-first transistor T21 is electrically connected to the frame start signal line STU of the first virtual shift register, the first end of the twenty-first transistor T21 is electrically connected to the pull-down node QB2 of the virtual shift register, and the second end of the twenty-first transistor T21 is electrically connected to the second scan input signal line CNB.

[0201] During implementation, when the first input signal line STU of the first virtual shift register is at a high level, the twenty-first transistor T21 is turned on, and the low level signal of the second scan input signal line CNB is provided to the pull-down node QB2 through the turned-on twenty-first transistor T21, making the pull-down node QB2 at a low level.

[0202] 10, the control terminal of the twenty-first transistor T21' is connected to the first input signal line CR of the second virtual shift register. <n-1>The first end of the twenty-first transistor T21 ′ is electrically connected to the pull-down node QB3 of the dummy shift register, and the second end of the twenty-first transistor T21 ′ is electrically connected to the second scan input signal line terminal CNB.

[0203] During the implementation process, the first input signal line CR of the second virtual shift register <n-1>When the voltage is high, the twenty-first transistor T21 ′ is turned on, and the low-level signal of the second scan input signal line CNB is provided to the pull-down node QB3 via the turned-on twenty-first transistor T21 ′, so that the pull-down node QB3 is at a low level.

[0204] 9, the control terminal of the twenty-second transistor T22 is connected to the second input signal line CR of the first virtual shift register.<N+1> The first end of the twenty-second transistor T22 is electrically connected to the pull-down node QB2 of the first dummy shift register, and the second end of the twenty-second transistor T22 is electrically connected to the first scan input signal line CN.

[0205] 10 , the control end of the twenty-second transistor T22′ is electrically connected to the frame start signal line STU of the second shift register, the first end of the twenty-second transistor T22′ is electrically connected to the pull-down node QB3 of the second dummy shift register, and the second end of the twenty-second transistor T22′ is electrically connected to the first scan input signal line CN.

[0206] During the implementation, when the second input signal line CR of the first virtual shift register<N+1> When the level is high, the 22nd transistor T22 is turned on, and the high level signal provided by the first scan input signal line CN is written into the pull-down node QB2 via the turned-on 22nd transistor T22, so that the pull-down node QB2 is at a high level.

[0207] During implementation, when the frame start signal line STU of the second shift register is at a high level, the 22nd transistor T22' is turned on, and the high level signal provided by the first scan input signal line CN is written into the pull-down node QB3 through the turned-on 22nd transistor T22', making the pull-down node QB3 at a high level.

[0208] The second cascade output module 204 is configured to provide the signal of the cascade clock signal line to the cascade output signal line CR in response to the signal of the pull-up node Q3. <n>Or, in response to the signal of the pull-down node QB2 of the first dummy shift register or the pull-down node QB3 of the second dummy shift register, the signal of the first reference signal line VGL1 is provided to the cascade output signal line CR <n>.

[0209] Exemplarily, referring to FIG. 9 , the second cascade output module 204 includes a twenty-third transistor T23 and a twenty-fourth transistor T24 .

[0210] 9, the control end of the twenty-third transistor T23 is electrically connected to the pull-up node Q2 of the first virtual shift register, the first end of the twenty-third transistor T23 is electrically connected to the cascade clock signal line CLKD_2 of the virtual shift register, and the second end of the twenty-third transistor T23 is electrically connected to the cascade output signal line CR of the virtual shift register. <n>Electrical connection.

[0211] During the implementation process, when the pull-up node Q2 of the first virtual shift register is a high-level signal, the twenty-third transistor T23 is turned on, and the high-level signal of the cascade clock signal line CLKD_2 is written into the cascade output signal line CR through the turned-on twenty-third transistor T23. <n>.

[0212] The control end of the twenty-fourth transistor T24 is electrically connected to the pull-down node QB2 of the first virtual shift register, and the first end of the twenty-fourth transistor T24 is electrically connected to the cascade output signal line CR of the first virtual shift register. <n>The second end of the twenty-fourth transistor T24 is electrically connected to the first reference signal line VGL1 of the virtual shift register.

[0213] During the implementation, when the pull-down node QB2 of the first virtual shift register is a high level signal, the twenty-fourth transistor T24 is turned on, and the low level signal of the first reference signal line VGL1 is written into the cascade output signal line CR through the turned-on twenty-fourth transistor T24. <n>, to cascade output signal line CR <n>Perform a reset.

[0214] The second driver output module 205 is configured to provide the signal of the clock signal line CLKE_2 to the driver output terminal OUT2 in response to the signal of the pull-up node Q2. <n>Or, in response to the signal of the pull-down node QB2, the signal of the second reference signal line VGL2 is provided to the driving output terminal OUT2 <n>.

[0215] Exemplarily, referring to FIG. 9 , the second driving output module 205 includes a twenty-fifth transistor T25 , a twenty-sixth transistor T26 , and a second capacitor c2 .

[0216] 9, the control end of the twenty-fifth transistor T25 is electrically connected to the pull-up node Q2 of the first virtual shift register, the first end of the twenty-fifth transistor T25 is electrically connected to the clock signal line CLKE_2 of the first virtual shift register, and the second end of the twenty-fifth transistor T25 is electrically connected to the driving output terminal OUT2 of the first virtual shift register. <n>Electrical connection.

[0217] During the implementation process, when the pull-up node Q2 of the first virtual shift register is a high-level signal, the twenty-fifth transistor T25 is turned on, and the high-level signal of the clock signal line CLKE_2 of the first virtual shift register is provided to the driving output terminal OUT2 through the turned-on twenty-fifth transistor T25. <n>.

[0218] The control terminal of the twenty-sixth transistor T26 is electrically connected to the pull-down node QB2 of the first virtual shift register, and the first terminal of the twenty-sixth transistor T26 is electrically connected to the driving output terminal OUT2 of the first virtual shift register. <n>The second end of the twenty-sixth transistor T26 is electrically connected to the second reference signal line VGL2.

[0219] During the implementation process, when the signal of the pull-down node QB2 of the first virtual shift register is at a high level, the twenty-sixth transistor T26 is turned on, and the low level signal of the second reference signal line VGL2 is written into the driving output terminal OUT2 through the turned-on twenty-sixth transistor T26. <n>.

[0220] In the embodiment of the present application, the first end of the second capacitor C2 is electrically connected to the pull-up node Q2, and the second end of the second capacitor C2 is electrically connected to the driving output terminal OUT2. <n>When the seventh transistor T7 is turned on, a high level can be transmitted to the pull-up node Q2, thereby increasing the voltage of the pull-up node Q2 and charging the first capacitor C1. When the seventh transistor T7 is turned off, the second capacitor C2 can be discharged, so that the pull-up node Q2 maintains a high level, thereby keeping the twenty-fifth transistor T25 in the on state.

[0221] In addition, when the twenty-fifth transistor T25 is turned on, the clock signal line CLKE_2 changes from a high level to a low level, and the output terminal OUT2 is driven. <n>The output is low level. At the same time, due to the bootstrap effect of the first capacitor c1, the voltage of the pull-up node Q2 will also drop.

[0222] Similarly, the shift register unit 20 provided in the embodiment of the present invention can realize bidirectional scanning. During reverse scanning, the functions of the third input module 201 and the fourth input module 202 of the virtual shift register are interchanged, that is, during forward scanning, the third input module 201 serves as an input module, and the third input signal line serves as an input signal line. The gate drive circuit, when realizing reverse scanning of the gate line, interchanges the functions of the third input module 201 and the fourth input module 202 of each virtual shift register, that is, relative to the forward scanning, during reverse scanning, the fourth input module 202 of each virtual shift register serves as an input module, and the second input signal line serves as an input signal line, and the third input module 201 of each virtual register serves as a reset module, and the first input signal line serves as a reset signal line. At this time, the electrical connection relationship of the circuit does not change, but the circuit function changes.

[0223] Referring to Figure 11, the main working process of the gate drive circuit during the forward scanning process is described below in combination with the timing diagram. It is assumed that the above-mentioned gate drive circuit includes three shift registers: a first virtual shift register, a scanning virtual shift register and a second virtual shift register. The driving output end of the scanning virtual shift register provides a scanning signal for the corresponding gate line.

[0224] During timing t1, the inactive level signal on the first control signal line A1 in the level control unit 10, i.e., the first transistor T1, is turned off. The active level signal on the second control signal line A2, i.e., the second transistor T2, is turned on. The active level signal on the third control signal line A3, i.e., the third transistor T3, is turned on. In the shift register unit 20, the cascaded clock signal line CLKD_1 is low, the clock signal line CLKE_1 is low, the first reference signal line VGL1 is low, the second reference signal line VGL2 is low, and the frame start signal line STU is high.

[0225] When the second transistor T2 is turned on, the high-level signal in the first scan control signal CN1 is provided via the first transmission line to the first scan input signal line CN of the first dummy shift register, the scan dummy shift register, and the second dummy shift register, causing the signal on the first scan input signal line CN to be high. When the third transistor T3 is turned on, the low-level signal in the second scan control signal CNB1 is provided via the second transmission line to the second scan input signal line CNB of the first dummy shift register, the scan dummy shift register, and the second dummy shift register, causing the signal on the second scan input signal line CNB to be low.

[0226] When the frame start signal line STU is at a high level, the seventh transistor T7 is turned on, and the signal of the first scan input signal line CN is at a high level. Thus, a high level signal is written into the pull-up node Q2 of the first virtual shift register.

[0227] In the first virtual shift register, since the pull-up node Q2 of the first virtual shift register is a high-level signal, the twenty-third transistor T23 and the twenty-fifth transistor T25 are both turned on. Since the frame start signal line STU provides a high-level signal, the twenty-first transistor T21 is turned on at this time, and the low-level signal provided by the second scan input signal line CNB is written to the pull-down node QB2. At this time, the twenty-fourth transistor T24 and the twenty-sixth transistor T26 are both turned off. Among them, the low-level signal of the cascade clock signal line CLKD_2 of the first virtual shift register is written to the cascade output signal line CR via the turned-on twenty-third transistor T23. <n>, cascade output signal line CR <n>Output low level signal; the low level signal of the clock signal line CLKE_2 of the first virtual shift register is written into the driving output terminal OUT2 via the turned-on twenty-fifth transistor T25 <n>, the driving output terminal OUT2 of the first virtual shift register <n>Outputs a low-level signal.

[0228] In the scan shift register, since the cascade output signal line of the first virtual shift register provides a low-level signal, the fourth transistor T4 and the twelfth transistor T12 are turned off. The frame start signal line STU is a high-level signal, so the sixth transistor T6 is turned on, and the low-level signal of the first reference signal line VGL1 is written into the pull-up node Q1 of the scan shift register via the turned-on sixth transistor T6. Therefore, the fourteenth transistor T14 and the sixteenth transistor T16 are turned off. At this time, the VDD signal in the power supply signal line is written into the pull-down node QB1 via the turned-on eleventh transistor T11, that is, the pull-down node DB1 is written into a high-level signal. At this time, the fifteenth transistor T15 and the seventeenth transistor T17 are turned on. Among them, the low-level signal of the first reference signal line VGL1 is written into the cascade signal output terminal cr via the fifteenth transistor T15. <n>, cascade signal output terminal cr <n>Output low level signal; the low level signal of the second reference signal line VGL2 is written into the driving output terminal OUT1 through the seventeenth transistor T17 <n>, scan the drive output terminal OUT1 of the shift register <n>Outputs a low-level signal.

[0229] In the second virtual shift register, since the cascade signal output terminal cr of the scan shift register <n>A low-level signal is provided, and the seventh transistor T7' and the twenty-first transistor T21' are turned off. Since the frame start signal line STU is at a high level, the eighth transistor T8' and the twenty-second transistor T22' are turned on. At this time, the low-level signal of the second scan input signal line CNB is written to the pull-up node Q3 via the eighth transistor T8', and the high-level signal of the first scan input signal line CN is written to the pull-down node QB3 via the twenty-second transistor T22'. At this time, the twenty-third transistor T23' and the twenty-fifth transistor T25' are turned off, the twenty-fourth transistor T24' and the twenty-sixth transistor T26' are turned on, and the cascade output signal line CR of the second virtual shift register is turned on. <n>and drive output OUT3 <n>Both output low-level signals.

[0230] During timing t2, the inactive level signal on the first control signal line A1 in the level control unit 10, i.e., the first transistor T1, is turned off. The active level signal on the second control signal line A2, i.e., the second transistor T2, is turned on. The active level signal on the third control signal line A3, i.e., the third transistor T3, is turned on. In the first virtual shift register, the cascaded clock signal line CLKD_2 is high, the clock signal line CLKE_2 is high, the first reference signal line VGL1 is low, the second reference signal line VGL2 is low, and the start-of-frame signal line STU is low.

[0231] When the second transistor T2 is turned on, the high-level signal in the first scan control signal CN1 is provided via the first transmission line to the first scan input signal line CN of the first dummy shift register, the scan dummy shift register, and the second dummy shift register, causing the signal on the first scan input signal line CN to be high. When the third transistor T3 is turned on, the low-level signal in the second scan control signal CNB1 is provided via the second transmission line to the second scan input signal line CNB of the first dummy shift register, the scan dummy shift register, and the second dummy shift register, causing the signal on the second scan input signal line CNB to be low.

[0232] After the signals in the cascaded clock signal line CLKD_2 and the clock signal line CLKE_2 jump from a low level to a high level, the voltage of the pull-up node Q2 of the first virtual shift register is further raised due to the bootstrap effect of the second capacitor C2. The twenty-third transistor T23 and the twenty-fifth transistor T25 are fully turned on. The high level of the pull-up node Q2 of the first virtual shift register controls the eighteenth transistor T18 to turn on. The low level of the first reference signal line VGL1 is written to the pull-down node QB2 of the first virtual shift register via the turned-on eighteenth transistor T18. The high level of the clock signal line CLKE_2 is written to the driver output terminal OUT2 via the twenty-fifth transistor T25. <n>, that is, driving output terminal OUT2 <n>Output high level signal, the high level of the cascade clock signal line CLKD_2 is written into the cascade output signal line CR through the twenty-third transistor T23 <n>, that is, the cascade output signal line CR <n>Outputs a high-level signal.

[0233] At the same time, due to the cascade output signal line CR of the first virtual shift register <n>Output high level signal, the cascade output signal line CR <n>The high level signal in the scan shift register is provided to the first input signal line CR <n-1>, thereby turning on the fourth transistor T4 in the scan shift register, and the high level signal of the first scan input signal line CN is written into the pull-up node Q1 in the scan shift register through the turned-on fourth transistor T4, and the fourteenth transistor T14 and the sixteenth transistor T16 are turned on. At the same time, due to the cascade output signal line CR of the first virtual shift register <n>The high level signal in turns on the twelfth transistor T12 in the scan shift register, and the low level signal of the second scan input signal line CNB turns on the pull-down node QB1 of the scan shift register, so that the tenth transistor T10, the fifteenth transistor T15 and the seventeenth transistor T17 are all turned off.

[0234] At the same time, due to the cascade output signal line CR of the first virtual shift register <n>A high-level signal is output, the twelfth transistor T12 is turned on, and the low-level signal in the second scan input signal line CNB is written into the pull-down node QB1 in the scan shift register through the turned-on twelfth transistor T12.

[0235] At this time, in the second virtual shift register, due to the cascade signal output terminal cr of the scan shift register <n>A low level signal is output. At this time, the seventh transistor T7 ′ and the twenty-first transistor T21 ′ in the second virtual shift register are both turned off.

[0236] During timing t3, the inactive level signal on the first control signal line A1 in the level control unit 10, i.e., the first transistor T1, is turned off. The active level signal on the second control signal line A2, i.e., the second transistor T2, is turned on. The active level signal on the third control signal line A3, i.e., the third transistor T3, is turned on. The cascaded clock signal line CLKD_1 and the clock signal line CLKE_1 in the scan shift register are both high. The first reference signal line VGL1 and the second reference signal line VGL2 are both low. The frame start signal line STU is also low.

[0237] When the second transistor T2 is turned on, the high-level signal in the first scan control signal CN1 is provided via the first transmission line to the first scan input signal line CN of the first dummy shift register, the scan dummy shift register, and the second dummy shift register, causing the signal on the first scan input signal line CN to be high. When the third transistor T3 is turned on, the low-level signal in the second scan control signal CNB1 is provided via the second transmission line to the second scan input signal line CNB of the first dummy shift register, the scan dummy shift register, and the second dummy shift register, causing the signal on the second scan input signal line CNB to be low.

[0238] At this time, in the first virtual shift register: since the cascade clock signal line CLKD_1 and the clock signal line CLKE_1 in the first virtual shift register jump from high level to low level, the cascade output terminal CR in the first virtual shift register <n>and drive output OUT2 <n>In the scanning shift register, the fourth transistor T4 and the twelfth transistor T12 are connected to the cascade output terminal CR in the first virtual shift register. <n>It is shut down under the control of a low level signal.

[0239] After the cascaded clock signal lines CLKD_2 and CLKE_2 in the scan shift register jump from a low level to a high level, the voltage of the pull-up node Q1 of the scan shift register is further raised due to the bootstrap effect of the first capacitor C1. The fourteenth transistor T14 and the sixteenth transistor T16 are fully turned on. The high level of the pull-up node Q1 of the scan shift register controls the ninth transistor T9 to turn on. The low level of the first reference signal line VGL1 is written to the pull-down node QB1 of the scan shift register. The high level of the clock signal line CLKE_1 is output through the sixteenth transistor T16, that is, it drives the output terminal OUT1. <n>Output high level signal, that is, scan the drive output terminal OUT1 of the shift register <n>Provides a high level signal for the gate line, and the high level of the cascade clock signal line CLKD_1 is output through the fourteenth transistor T14, that is, the cascade output signal line CR <n>Outputs a high-level signal.

[0240] At the same time, since the signal in the cascade output signal line of the scan shift register is high level, the cascade output signal line CR <n>The high-level signal in the first scan input signal line CN is provided to the first input signal line of the second virtual shift register, thereby turning on the seventh transistor T7' in the second virtual shift register, and the high-level signal in the first scan input signal line CN is written into the pull-up node Q3 in the second virtual shift register through the turned-on seventh transistor T7', and the twenty-third transistor T23' and the twenty-fifth transistor T25' are turned on.

[0241] At this time, the cascade output signal line CR of the second virtual shift register <n>and drive output OUT3 <n>Correspondingly, the fifth transistor T5 and the thirteenth transistor T13 in the scan shift register are turned off.

[0242] At the same time, since the signal in the cascade output signal line of the scan shift register is high level, the cascade output signal line CR <n>The high level signal in the scan input signal is provided to the second input signal line of the first virtual shift register, thereby turning on the eighth transistor T8 of the first virtual shift register, and the low level signal of the second scan input signal is written to the pull-up node of the first virtual shift register. Since the signal in the cascade output signal line of the scan shift register is high level, the cascade output signal line CR <n>The high-level signal in the first virtual shift register is provided to the twenty-second transistor T22 of the first virtual shift register, turning on the twenty-second transistor T22. The high-level signal of the first scan input signal is provided to the pull-down node of the first virtual shift register via the turned-on twenty-second transistor T22, thereby turning on the twenty-fourth transistor T24. The low-level signal of the first reference signal line VGL1 is written to the cascade signal output terminal of the first virtual shift register via the turned-on twenty-fourth transistor T24, thereby resetting the cascade signal output terminal. The high-level signal of the pull-down node is also provided to the twenty-sixth transistor T26, turning on the twenty-sixth transistor T26. The low-level signal of the second reference signal line VGL2 is written to the driving output terminal of the first virtual shift register via the turned-on twenty-sixth transistor T26, causing the driving output terminal to output a low-level signal. The high-level signal of the pull-down node is also provided to the nineteenth transistor T19, turning on the nineteenth transistor T19. The low-level signal of the first reference signal line VGL1 is written to the pull-up node of the first virtual shift register via the turned-on nineteenth transistor T19, thereby resetting the pull-up node.

[0243] At the same time, since the signal in the cascade output signal line of the scan shift register is high level, the cascade output signal line CR <n>The high level signal in is provided to the twenty-first transistor T21' of the second virtual shift register, the twenty-first transistor T21' is turned on, and the low level signal of the second scan input signal is written into the pull-down node of the second virtual shift register through the turned-on twenty-first transistor T21'.

[0244] During timing t4, the inactive level signal on the first control signal line A1 in the level control unit 10, i.e., the first transistor T1, is turned off. The active level signal on the second control signal line A2, i.e., the second transistor T2, is turned on. The active level signal on the third control signal line A3, i.e., the third transistor T3, is turned on. In the shift register unit 20, the cascaded clock signal line CLKD_3 and the clock signal line CLKE_3 are both high. The first reference signal line VGL1 and the second reference signal line VGL2 are both low. The frame start signal line STU is also low.

[0245] When the second transistor T2 is turned on, the high-level signal in the first scan control signal CN1 is provided via the first transmission line to the first scan input signal line CN of the first dummy shift register, the scan dummy shift register, and the second dummy shift register, causing the signal on the first scan input signal line CN to be high. When the third transistor T3 is turned on, the low-level signal in the second scan control signal CNB1 is provided via the second transmission line to the second scan input signal line CNB of the first dummy shift register, the scan dummy shift register, and the second dummy shift register, causing the signal on the second scan input signal line CNB to be low.

[0246] In the scan shift register, since the cascade clock signal line CLKD_1 and the clock signal line CLKE_1 jump from high level to low level, the cascade output terminal CR in the scan shift register is <n>and drive output OUT1 <n>Both output low-level signals.

[0247] In the first virtual shift register, the eighth transistor T8 and the twenty-second transistor T22 are connected to the cascade output terminal CR in the scan shift register. <n>It is shut down under the control of a low level signal.

[0248] In the second virtual shift register, the seventh transistor T7' and the twenty-first transistor T21' are connected to the cascade output terminal CR in the scan shift register. <n>It is shut down under the control of a low level signal.

[0249] After the cascaded clock signal line CLKD_3 and the clock signal line CLKE_3 of the second virtual shift register jump from a low level to a high level, the voltage of the pull-up node Q3 of the second virtual shift register is further raised due to the bootstrap effect of the third capacitor C3. The twenty-third transistor T23' and the twenty-fifth transistor T25' are fully turned on. The high level of the pull-up node Q3 of the second virtual shift register controls the eighteenth transistor T18' of the second virtual shift register to turn on. The low level of the first reference signal line VGL1 is written to the pull-down node Q3 of the second virtual shift register. The high level of the clock signal line CLKE_3 is written to the driver output terminal OUT3 through the twenty-fifth transistor T25'. <n>, that is, driving the output terminal OUT3 <n>Output high level signal, the high level of the cascade clock signal line CLKD_3 is written into the cascade output signal line CR through the twenty-third transistor T23 ' <n>, that is, the cascade signal output terminal CR <n>Outputs a high-level signal.

[0250] At the same time, due to the cascade output signal line CR of the second virtual shift register <n>The signal in is high level, the cascade output signal line CR <n>The high level signal in the second input signal line of the scan shift register is provided to the second input signal line of the scan shift register, thereby turning on the fifth transistor T5 of the scan shift register, and the low level signal of the second scan input signal line CNB in ​​the scan shift register is written to the pull-up node Q1 of the scan shift register. <n>The signal in is high level, the cascade output signal line CR <n>The high-level signal of the first scan input signal line CN is provided to the thirteenth transistor T13 of the scan shift register, so that the thirteenth transistor T13 is turned on. The high-level signal of the first scan input signal line CN is provided to the pull-down node QB1 of the scan shift register through the turned-on thirteenth transistor T13, thereby turning on the fifteenth transistor T15 of the scan shift register. The low-level signal of the first reference signal line VGL1 is written into the cascade signal output terminal cr of the scan shift register through the turned-on fifteenth transistor T15. <n>, to achieve the reset of the cascade signal output end.

[0251] At the same time, the high-level signal of the pull-down node QB1 of the scan shift register is also provided to the tenth transistor T10 of the scan shift register. The tenth transistor T10 is turned on, and the low-level signal of the first reference signal line VGL1 is written into the pull-up node Q1 of the scan shift register through the turned-on tenth transistor T10.

[0252] Timing stage t5: The first control signal line A1 in the level control unit 10 is at an active level, i.e., the first transistor T1 is turned on; the second control signal line A2 is at an inactive level, i.e., the second transistor T2 is turned off; the third control signal line A3 is at an active level, i.e., the third transistor T3 is turned on. The cascaded clock signal line CLKD_2 in the shift register unit 20 is at a low level, the clock signal line CLKE_2 is at a low level, the first reference signal line VGL1 is at a low level, the second reference signal line VGL2 is at a low level, the frame start signal line STU is at a high level, and the cascaded output signal line CR of the first virtual shift register is at a low level. <n>is low level, and the cascade signal output terminal OUT1 of the scan shift register is low level.

[0253] First, it should be supplemented that after the display panel finishes displaying a frame of picture, the signal in the frame start signal line STU is set to a high level again.

[0254] When the third transistor T3 is turned on, the low-level signal in the second scan control signal CNB1 is provided via the second transmission line to the second scan input signal line CNB of the first dummy shift register, the scan dummy shift register, and the second dummy shift register, causing the signal on the second scan input signal line CNB to be low. When the first transistor T1 is turned on, the first transmission line and the second transmission line are connected, and the low-level signal in the second scan control signal CNB1 is transmitted via the second transmission line to the first transmission line. Then, the first transmission line provides the low-level signal via the second transmission line to the first scan input signal line CN of the first dummy shift register, the scan dummy shift register, and the second dummy shift register, causing the signal on the first scan input signal line CN to also be low.

[0255] When the frame start signal line STU is high, the second input signal line of the second virtual shift register is high, and the eighth transistor T8' is turned on. The low-level signal of the second scan input signal line CNB is written to the pull-up node of the second virtual shift register via the turned-on eighth transistor T8'. Simultaneously, when the frame start signal line STU is high, the twenty-second transistor T22' of the second virtual shift register is turned on, and the low-level signal of the first scan input signal line CN is written to the pull-down node Q3 of the second virtual shift register via the turned-on twenty-second transistor T22'. However, the high-level signal of the power signal line VDD turns on the twenty-fourth transistor T24' and the twenty-sixth transistor T26', and the low-level signal of the first reference signal line VGL1 is written into the cascade signal output terminal of the second virtual shift register through the turned-on twenty-fourth transistor T24', thereby resetting the cascade signal output terminal of the second virtual shift register. The low-level signal of the second reference signal line VGL2 is provided to the driving output terminal OUT3 of the second virtual shift register through the turned-on twenty-sixth transistor T26'. <n>, thereby realizing the driving output terminal OUT3 of the second virtual shift register <n>Reset.

[0256] In addition, after scanning a frame of picture using the first virtual shift register, the scanning virtual shift register and the second virtual shift register, and before scanning the next frame of picture, the gate driving circuit needs to be reset.

[0257] During the frame reset process, in the first virtual shift register, the high-level signal of the frame start signal line STU turns on the seventh transistor T7 of the third input module 201 of the first virtual shift register, and the low-level signal of the first scan input signal line CN is provided to the pull-up node Q2 of the first virtual shift register through the turned-on seventh transistor T7, thereby performing frame reset.

[0258] During the frame reset process, in the scan shift register, the high-level signal of the frame start signal line STU turns on the sixth transistor T6 of the frame reset module of the scan shift register, and the low-level signal of the first reference signal line VGL1 is provided to the pull-up node Q1 of the scan shift register through the turned-on sixth transistor T6, thereby performing frame reset.

[0259] During the frame reset process, in the second virtual shift register, the high-level signal of the frame start signal line STU turns on the eighth transistor T8' of the fourth input module 202 of the second virtual shift register, and the low-level signal of the second scan input signal line CNB is provided to the pull-up node Q3 of the second virtual shift register through the turned-on eighth transistor T8', thereby performing frame reset.

[0260] In addition, it should be noted that the above-mentioned process of using the frame start signal line STU to perform frame reset can also be applied to the circuits shown in Figures 12, 13 and 14. The frame reset process here is similar to that of Figures 7, 9 and 10 above, and will not be repeated here.

[0261] In addition, referring to FIG12 , the pull-up node Q4 may leak due to the influence of the negative bias voltage. For this reason, the scan shift register in the embodiment of the present application also includes a compensation module, which is configured to respond to the signal of the compensation signal line OE and provide a high-level compensation signal to the pull-up node Q4.

[0262] The compensation module includes a twenty-seventh transistor T27, a twenty-eighth transistor T28, a twenty-ninth transistor T29 and a fourth capacitor C4. The control end of the twenty-seventh transistor T27 is electrically connected to the compensation signal line OE, and the first end of the twenty-seventh transistor T27 is electrically connected to the cascade signal output end cr. <n>A second end of the twenty-seventh transistor T27 is electrically connected to the control end of the twenty-eighth transistor T28, a first end of the twenty-eighth transistor T28 is electrically connected to the compensation clock signal line CLKA, a second end of the twenty-eighth transistor T28 is electrically connected to the first end of the twenty-ninth transistor T29, the control end of the twenty-ninth transistor T29 is electrically connected to the compensation clock signal line CLKA, and a second end of the twenty-ninth transistor T29 is electrically connected to the pull-up node Q4. A first end of the fourth capacitor C4 is electrically connected to the control end of the twenty-eighth transistor T28, and a second end of the fourth capacitor C4 is electrically connected to the first reference signal line VGL1.

[0263] During the implementation process, the waveform of the compensation signal line OE is consistent with the cascade signal output terminal cr <n>The waveform is consistent with that of the cascade signal output terminal cr <n>When a high level signal is output, the compensation signal line OE is also a high level signal, the twenty-seventh transistor T27 is turned on, and the cascade signal output terminal cr <n>The high-level signal of the compensation clock signal line CLKA is provided to the control terminal of the twenty-eighth transistor T28 via the conductive twenty-seventh transistor T27. The twenty-eighth transistor T28 is then conductive, and the high-level signal of the compensation clock signal line CLKA is provided to the control terminal of the twenty-ninth transistor T29. The twenty-ninth transistor T29 is then conductive, and the high-level signal of the compensation clock signal line CLKA is provided to the pull-up node Q4 via the conductive twenty-eighth and second transistors T28 and T29, thereby compensating the voltage level of the pull-up node Q4. The fourth capacitor C4 is used to maintain the potential of the control terminal of the twenty-eighth transistor T28. During the display phase of a frame, a high potential is written to the control terminal of the twenty-eighth transistor T28 via the twenty-seventh transistor T27. This high potential is maintained until the end of the frame display, i.e., in the blank region. During the blank region, a high potential is written to the pull-up node Q4 via the twenty-eighth and second transistors T28 and T29.

[0264] In addition, the scan shift register further includes an auxiliary compensation module, which can pull down the pull-down node QB4 when a high potential is written to the pull-up node Q4. The auxiliary compensation module includes a 30th transistor T30 and a 31st transistor T31.

[0265] The control end of the 30th transistor T30 is electrically connected to the compensation clock signal line CLKA, the first end of the 30th transistor T30 is electrically connected to the pull-down node QB4, the second end of the 30th transistor T30 is electrically connected to the first end of the 31st transistor T31, the control end of the 31st transistor T31 is electrically connected to the control end of the 28th transistor T28, and the second end of the 31st transistor T31 is electrically connected to the first reference signal line VGL1.

[0266] During implementation, when the compensation clock signal line CLKA is at a high potential, the 30th transistor T30 is turned on, and when the control terminal of the 28th transistor T28 is at a high potential, the 30th transistor T31 is turned on, and the low potential of the first reference signal line VGL1 is written into the pull-down node QB4 via the turned-on 30th transistor T30 and the 30th transistor T31, so that the pull-down node QB4 is at a low potential.

[0267] Based on the same inventive concept, an embodiment of the present application provides a display panel, comprising: a plurality of gate lines and the above-mentioned gate driving circuit;

[0268] A driving output terminal of a scan shift register in the gate driving circuit is electrically connected to one gate line among the plurality of gate lines.

[0269] Based on the same inventive concept, an embodiment of the present application provides a display device, including the above-mentioned display panel.

[0270] The display device provided in the embodiments of the present application can be any product or component with a display function, such as a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigation system, etc. Other essential components of the display device are well understood by those skilled in the art and are not described here in detail, nor should they be construed as limitations of the present application.

[0271] Based on the same inventive concept, an embodiment of the present application provides a driving method for the above-mentioned gate driving circuit, as shown in FIG15 , including:

[0272] Step 201: Scanning phase: The level control unit 10 responds to the first control signal, writes the first scan control signal CN1 into the first scan input signal line CN, and writes the second scan control signal CNB1 into the second scan input signal line CNB, the scan shift register responds to the signals of the first scan input signal line CN and the second scan input signal line CNB to input the scan drive signal to the gate line, and the virtual shift register responds to the signals of the first scan input signal line CN and the second scan input signal line CNB to input the cascade drive signal to the scan shift register.

[0273] During the implementation process, the level control unit 10 and the shift register unit 20 are used in conjunction with each other. The level control unit 10 mainly provides the shift register unit 20 with a first scanning control signal and a second scanning control signal of different levels during the forward scanning, reverse scanning and frame reset processes, so that the shift register unit 20 can work according to the first scanning input signal and the second scanning input signal during the forward scanning, reverse scanning and frame reset processes after removing the original tube used for frame reset.

[0274] During the forward scan process, the level control unit 10, under the action of the first control signal, writes the first scan control signal CN1 into the first scan input signal line CN, and writes the second scan control signal CNB1 into the second scan input signal line CNB. Thereafter, the level control unit 10 provides a high-level signal to the first scan input signal line CN of the scan shift register and the dummy shift register in the shift register unit 20, and provides a low-level signal to the second scan input signal line CNB of the scan shift register and the dummy shift register in the shift register unit 20. Under the control of the first and second scan input signals, the dummy shift register inputs a cascade drive signal to the scan shift register. Under the control of the first and second scan input signals, the scan shift register inputs a scan drive signal to the gate line.

[0275] During the reverse scan process, the level control unit 10, under the action of the first control signal, writes the first scan control signal CN1 into the first scan input signal line CN and the second scan control signal CNB1 into the second scan input signal line CNB, providing a low-level signal to the first scan input signal line CN of the scan shift register and the dummy shift register in the shift register unit 20, and providing a high-level signal to the second scan input signal line CNB of the scan shift register and the dummy shift register in the shift register unit 20. Under the control of the first scan input signal and the second scan input signal, the dummy shift register inputs a cascade drive signal to the scan shift register. Under the control of the first scan input signal, the second scan input signal, and the cascade drive signal, the scan shift register inputs a scan drive signal to the gate line.

[0276] Step 202: Frame reset phase: the scan shift register resets its pull-up node in response to the frame start signal line STU, and the virtual shift register resets its pull-up node in response to the signal of the frame start signal line STU through the signal of the first scan input signal line CN and / or the second scan input signal line CNB; wherein, the level control unit 10 writes the second scan control signal CNB1 into the first scan input signal line CN and the second scan input signal line CNB of the scan shift register and the virtual shift register in response to the second control signal, or, writes the first scan control signal CN1 into the first scan input signal line CN and the second scan input signal line CNB of the scan shift register and the virtual shift register in response to the third control signal.

[0277] In the embodiment of the present application, since the transistor originally used for frame reset is removed, the level control unit 10 and the shift register unit 20 need to cooperate to complete the frame reset before the next frame starts after one frame is displayed.

[0278] In a specific implementation, after the forward scan is completed, the level control unit 10 responds to the second control signal and writes the second scan control signal CNB1 into the first scan input signal line CN and the second scan input signal line CNB of the scan shift register and the dummy shift register. That is, after the forward scan is completed, low-level signals are input into the first scan input signal line CN and the second scan input signal line CNB of the scan shift register and the dummy shift register. The scan shift register responds to the frame start signal line STU by using the sixth transistor T6 to reset its pull-up node. The dummy shift register responds to the signal of the frame start signal line STU by using the signal of the first scan input signal line CN and / or the second scan input signal line CNB to reset its pull-up node. That is, the first dummy shift register responds to the signal of the frame start signal line STU by using the seventh transistor T7 to reset its pull-up node via the signal of the first scan input signal line CN. The second dummy shift register responds to the signal of the frame start signal line STU by using the eighth transistor T8 to reset its pull-up node via the signal of the second scan input signal line CNB.

[0279] In a specific implementation, after the reverse scan is completed, the level control unit 10 responds to the third control signal and writes the first scan control signal CN1 into the first scan input signal line CN and the second scan input signal line CNB of the scan shift register and the dummy shift register. That is, after the forward scan is completed, low-level signals are input into the first scan input signal line CN and the second scan input signal line CNB of the scan shift register and the dummy shift register. The scan shift register responds to the frame start signal line STU using the sixth transistor T6 to reset its pull-up node. The dummy shift register responds to the signal of the frame start signal line STU using the signal of the first scan input signal line CN and / or the signal of the second scan input signal line CNB. That is, the first dummy shift register responds to the signal of the frame start signal line STU using the seventh transistor T7 to reset its pull-up node via the signal of the second scan input signal line CNB. The second dummy shift register responds to the signal of the frame start signal line STU using the eighth transistor T8 to reset its pull-up node via the signal of the first scan input signal line CN.

[0280] In summary, a gate drive circuit, a display panel, and a display device are provided in the embodiments of the present application. The gate drive circuit includes: a shift register unit and a level control unit. The shift register unit includes a scan shift register and a virtual shift register. The scan shift register is electrically connected to the gate line and is configured to input a scan drive signal to the gate line according to the signal of the first scan input signal line and the second scan input signal line. The virtual shift register is electrically connected to the scan shift register and is configured to input a cascade drive signal to the scan shift register according to the signal of the first scan input signal line and the second scan input signal line. The level control unit is electrically connected to the first scan input signal line and the second scan input signal line of the scan shift register and the virtual shift register, respectively, and is configured to write the first scan control signal into the scan shift register in response to the first control signal. The first scan input signal line of the scan shift register and the virtual shift register is connected to the first scan input signal line of the scan shift register and the virtual shift register, the second scan control signal is written into the second scan input signal line of the scan shift register and the virtual shift register in response to the second control signal, and, in response to the third control signal, the first scan control signal is written into the first scan input signal line and the second scan input signal line of the scan shift register and the virtual shift register. After removing the transistors for frame reset in the scan shift register and the virtual shift register, the scan shift register and the virtual shift register are frame reset in combination with the different conduction conditions of the level control unit, thereby reducing the number of tubes in the gate drive circuit, saving costs and improving the panel yield.

[0281] Those skilled in the art will appreciate that the embodiments of the present application can be provided as methods, systems, or computer program product systems. Therefore, the present application can adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application can adopt the form of a computer program product system implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage, CD-ROM, optical storage, etc.) that contain computer-usable program code.

[0282] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program product systems according to the present application. It should be understood that each flow and / or box in the flow chart and / or block diagram, as well as the combination of the flow chart and / or box in the flow chart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device produce a device for implementing the functions specified in one or more flow charts and / or one or more boxes in the block diagram.

[0283] These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce a product including an instruction device that implements the functions specified in one or more processes in the flowchart and / or one or more boxes in the block diagram.

[0284] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, so that the instructions executed on the computer or other programmable device provide steps for implementing the functions specified in one or more processes in the flowchart and / or one or more boxes in the block diagram.

[0285] Obviously, those skilled in the art may make various changes and modifications to this application without departing from the spirit and scope of this application. Thus, if these modifications and variations of this application fall within the scope of the claims of this application and their equivalents, this application is intended to include these modifications and variations.< / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n>

Claims

1. A gate drive circuit, characterized in that: include: A shift register unit and a level control unit; The shift register unit includes a scan shift register and a dummy shift register, wherein the scan shift register is electrically connected to the gate line and configured to input a scan drive signal to the gate line according to signals of a first scan input signal line and a second scan input signal line, and the dummy shift register is electrically connected to the scan shift register and configured to input a cascade drive signal to the scan shift register according to signals of the first scan input signal line and the second scan input signal line; The level control unit is electrically connected to the first scan input signal line and the second scan input signal line of the scan shift register and the virtual shift register, respectively, and is configured to write a first scan control signal into the first scan input signal line of the scan shift register and the virtual shift register in response to a first control signal, write a second scan control signal into the second scan input signal line of the scan shift register and the virtual shift register, write the second scan control signal into the first scan input signal line and the second scan input signal line of the scan shift register and the virtual shift register in response to a second control signal, and write the first scan control signal into the first scan input signal line and the second scan input signal line of the scan shift register and the virtual shift register in response to a third control signal.

2. The circuit according to claim 1, characterized in that The level control unit comprises: a first control subunit, a second control subunit and a third control subunit; The control end of the first control subunit is electrically connected to the first control signal line, the first end of the first control subunit is electrically connected to the first transmission line, and the second end of the first control subunit is electrically connected to the second transmission line; The first control subunit is configured to connect the first transmission line and the second transmission line in response to an effective level signal of a first control signal line; The control end of the second control subunit is electrically connected to the second control signal line, the first end of the second control subunit is electrically connected to the first transmission line, and the second end of the first control subunit is electrically connected to the first scanning control signal line; The second control subunit is configured to write the first scanning control signal into the first transmission line in response to an effective level signal of a second control signal line; The control end of the third control subunit is electrically connected to the third control signal line, the first end of the third control subunit is electrically connected to the second transmission line, and the second end of the third control subunit is electrically connected to the second scan control signal line; The third control subunit is configured to write the second scanning control signal into the second transmission line in response to an effective level signal of a third control signal line.

3. The circuit according to claim 2, characterized in that The first scan input signal line of the scan shift register and the dummy shift register is electrically connected to the first transmission line, and the second scan input signal line of the scan shift register and the dummy shift register is electrically connected to the second transmission line; The first control signal causes the first control signal line to provide an invalid level signal, and the second control signal The signal line provides a valid level signal, and the third control signal line provides a valid level signal; The second control signal causes the first control signal line to provide a valid level signal, the second control signal line to provide an invalid level signal, and the third control signal line to provide a valid level signal; The third control signal causes the first control signal line to provide a valid level signal, the second control signal line to provide a valid level signal, and the third control signal line to provide an invalid level signal.

4. The circuit according to claim 2, characterized in that The first control subunit includes: a first transistor, a control end of the first transistor is electrically connected to a first control signal line, a first end of the first transistor is electrically connected to the first transmission line, and a second end of the first transistor is electrically connected to the second transmission line.

5. The circuit according to claim 2, characterized in that The second control subunit includes: a second transistor, a control end of the second transistor is electrically connected to a second control signal line, a first end of the second transistor is electrically connected to the first scan control signal line, and a second end of the second transistor is electrically connected to the first transmission line.

6. The circuit according to claim 2, characterized in that The third control subunit includes: a third transistor, a control end of the third transistor is electrically connected to a third control signal line, a first end of the third transistor is electrically connected to the second transmission line, and a second end of the third transistor is electrically connected to the second scan control signal line.

7. The circuit according to claim 1, characterized in that The shift register unit comprises a plurality of scanning shift registers, and the plurality of scanning shift registers are cascaded; The virtual shift register includes a first virtual shift register, a first input signal line of the first virtual shift register is electrically connected to a frame start signal line, a second input signal line of the first virtual shift register is electrically connected to a cascade signal output end of a first scanning shift register among the multiple scanning shift registers, and a cascade output signal line of the first virtual shift register is electrically connected to a first input signal line of the first scanning shift register.

8. The circuit according to claim 1, characterized in that The shift register unit comprises a plurality of scanning shift registers, and the plurality of scanning shift registers are cascaded; The virtual shift register includes a second virtual shift register, a first input signal line of the second virtual shift register is electrically connected to the cascade signal output end of the last scan shift register among the multiple scan shift registers, a second input signal line of the second virtual shift register is electrically connected to the frame start signal line, and a cascade output signal line of the second virtual shift register is electrically connected to the second input signal line of the last scan shift register.

9. The circuit according to claim 7 or 8, characterized in that The scanning shift register comprises: A first input module configured to provide a signal of a first scan input signal line to a pull-up node in response to a signal of a first input signal line; a second input module configured to provide a signal of a second scan input signal line to the pull-up node in response to a signal of a second input signal line; A first node control module, configured to control signals of a pull-up node and a pull-down node; The first cascade output module is configured to provide the signal of the cascade clock signal line to the cascade signal output terminal in response to the signal of the pull-up node; or, in response to the signal of the pull-down node, The signal of the first reference signal line is provided to the cascade signal output terminal; The first driver output module is configured to provide a signal of the clock signal line to the driver output terminal in response to the signal of the pull-up node; or to provide a signal of the second reference signal line to the driver output terminal in response to the signal of the pull-down node.

10. The circuit according to claim 9, characterized in that The first input module includes: a fourth transistor; The control end of the fourth transistor is electrically connected to the first input signal line, the first end of the fourth transistor is electrically connected to the first scan input signal line, and the second end of the fourth transistor is electrically connected to the pull-up node.

11. The circuit according to claim 9, characterized in that The second input module includes: a fifth transistor; The control end of the fifth transistor is electrically connected to the second input signal line, the first end of the fifth transistor is electrically connected to the pull-up node, and the second end of the fifth transistor is electrically connected to the second scan input signal line.

12. The circuit according to claim 9, characterized in that Also includes: A frame reset module, the frame reset module is electrically connected to the pull-up node; The frame reset module is configured to provide a signal of the first reference signal line to the pull-up node in response to a signal of the frame start signal line.

13. The circuit according to claim 12, characterized in that The frame resetting module comprises: a sixth transistor; The control end of the sixth transistor is electrically connected to the frame start signal line, the first end of the sixth transistor is electrically connected to the pull-up node, and the second end of the sixth transistor is electrically connected to the first reference signal line.

14. The circuit according to claim 7 or 8, characterized in that The virtual shift register comprises: a third input module configured to provide a signal of the first scan input signal line to the pull-up node in response to a signal of the first input signal line; a fourth input module configured to provide a signal of the second scan input signal line to the pull-up node in response to a signal of the second input signal line; A second node control module is configured to control signals of a pull-up node and a pull-down node; A second cascade output module is configured to provide a signal of the cascade clock signal line to the cascade output signal line in response to a signal of the pull-up node; or, in response to a signal of the pull-down node, provide a signal of the first reference signal line to the cascade output signal line; The second driver output module is configured to provide the signal of the clock signal line to the driver output terminal in response to the signal of the pull-up node; or to provide the signal of the second reference signal line to the driver output terminal in response to the signal of the pull-down node.

15. The circuit according to claim 14, characterized in that The third input module comprises: a seventh transistor; The control end of the seventh transistor is electrically connected to the first input signal line, the first end of the seventh transistor is electrically connected to the first scan input signal line, and the second end of the seventh transistor is electrically connected to the The pull-up nodes are electrically connected.

16. The circuit according to claim 15, characterized in that The fourth input module comprises: an eighth transistor; The control end of the eighth transistor is electrically connected to the second input signal line, the first end of the eighth transistor is electrically connected to the pull-up node, and the second end of the eighth transistor is electrically connected to the second scan input signal line.

17. The circuit according to claim 13, characterized in that Also included is a compensation module, the compensation module being electrically connected to the pull-up node; The compensation module is configured to provide a high-level compensation signal to the pull-up node in response to a signal of a compensation signal line.

18. The circuit according to claim 17, characterized in that The compensation module includes a twenty-seventh transistor, a twenty-eighth transistor, a twenty-ninth transistor and a fourth capacitor; The control terminal of the twenty-seventh transistor is electrically connected to the compensation signal line, the first terminal of the twenty-seventh transistor is electrically connected to the cascade signal output terminal, and the second terminal of the twenty-seventh transistor is electrically connected to the control terminal of the twenty-eighth transistor; A first terminal of the twenty-eighth transistor is electrically connected to the compensation clock signal line, and a second terminal of the twenty-eighth transistor is electrically connected to a first terminal of the twenty-ninth transistor; The control terminal of the twenty-ninth transistor is electrically connected to the compensation clock signal line, and the second terminal of the twenty-ninth transistor is electrically connected to the pull-up node; A first end of the fourth capacitor is electrically connected to the control end of the 28th transistor, and a second end of the fourth capacitor is electrically connected to the first reference signal line.

19. The circuit according to claim 18, characterized in that Also included is an auxiliary compensation module, the auxiliary compensation module including a thirtieth transistor and a thirty-first transistor; The control terminal of the 30th transistor is electrically connected to the compensation clock signal line, the first terminal of the 30th transistor is electrically connected to the pull-down node, and the second terminal of the 30th transistor is electrically connected to the first terminal of the 31st transistor; The control end of the thirty-first transistor is electrically connected to the control end of the twenty-eighth transistor, and the second end of the thirty-first transistor is electrically connected to the first reference signal line.

20. A display panel, characterized in that: include: A plurality of gate lines and a gate driving circuit as claimed in any one of claims 1 to 19; A driving output terminal of a scan shift register in the gate driving circuit is electrically connected to a gate line among the plurality of gate lines.

21. A display device, characterized in that: include: The display panel as claimed in claim 20.

22. A driving method of a gate driving circuit according to any one of claims 1 to 19, characterized in that: include: Scanning stage: the level control unit writes the first scanning control signal into the first scanning input signal line and the second scanning control signal into the second scanning input signal line in response to the first control signal, the scanning shift register inputs the scanning driving signal into the gate line in response to the signals of the first scanning input signal line and the second scanning input signal line, and the dummy shift register inputs the cascade driving signal into the scanning shift register in response to the signals of the first scanning input signal line and the second scanning input signal line; Frame reset stage: the scan shift register resets its pull-up node in response to the frame start signal line, and the virtual shift register resets its pull-up node in response to the signal of the frame start signal line through the signal of the first scan input signal line and / or the second scan input signal line; wherein the level control unit writes the second scan control signal into the first scan input signal line and the second scan input signal line of the scan shift register and the virtual shift register in response to the second control signal, or writes the first scan control signal into the first scan input signal line and the second scan input signal line of the scan shift register and the virtual shift register in response to the third control signal.

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