Source driver chip, and display panel and driving method therefor

Abstract

Provided are a source driver chip, and a display panel and a driving method therefor. The driving method comprises: in a first mode, generating first data (used for generating a first latch signal) on the basis of a first signal to be counted; and in a second mode, generating second data (used for generating a second latch signal) on the basis of a second signal to be counted, wherein the ending time of delay sub-signals in the two latch signals is used for controlling an initial latch data signal, and the ending time of a delay sub-signal in the second latch signal is earlier.

Description

Source driver chip, display panel and driving method thereof

[0001] This application claims priority to Chinese patent application No. 202311641869.X filed on November 30, 2023, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of display technology, and in particular to a source driver chip, a display panel, and a driving method thereof. Background Art

[0003] Liquid crystal displays are currently the most widely used displays. Considering the cost of data driver chips, they have introduced the DLS architecture (adjacent sub-pixels on the left and right share a data line) and the Tri-gate architecture (the gate lines are increased by 3 times to reduce the number of data lines to 1 / 3).

[0004] While the above architecture reduces the number of source driver chips by half or more compared to the 1G1D architecture, the differences in distance between the motherboard and different source driver chips, as well as the differences in distance between each source driver chip and data lines at different locations, require differentiated parameter settings within the source driver chips at different locations to mitigate the differences in charging time required for the corresponding data signals to act on the corresponding sub-pixels caused by these "distance differences." However, the current minimum setting for the parameters within the source driver chips is relatively large, at 9 UI (UI being the minimum unit of delay). For two source driver chips with a smaller "distance difference," such as those corresponding to two adjacent display areas, the two source driver chips cannot be configured with a smaller output "time difference." Consequently, the time difference between the data signals output by the two source driver chips and transmitted to the corresponding display areas is too large, resulting in a split-screen phenomenon and reduced display quality. SUMMARY OF THE INVENTION

[0005] The purpose of the present application is to provide a source driver chip, a display panel and a driving method thereof, so as to improve the split screen phenomenon caused by a large minimum gear of the parameters in the source driver chip in the existing display panel.

[0006] In a first aspect, the present application provides a source driver chip, wherein the source driver chip has a first mode and a second mode, and the source driver chip includes:

[0007] a counting module, configured to generate first data according to a first signal to be counted in the first mode, and to generate second data according to a second signal to be counted in the second mode;

[0008] a latch signal generating module, electrically connected to the counting module, for generating a first latch signal according to the first data in the first mode, and generating a second latch signal according to the second data in the second mode;

[0009] In which, the first latch signal includes a first delayed sub-signal, the second latch signal includes a second delayed sub-signal, the end time of the first delayed sub-signal in the first latch signal is used to control the latching of the initial data signal, the end time of the second delayed sub-signal in the second latch signal is used to control the latching of the initial data signal, and the end time of the second delayed sub-signal is earlier than the end time of the first delayed sub-signal.

[0010] In a second aspect, the present application further provides a display panel, comprising a panel body and a driver chip electrically connected to the panel body, wherein the driver chip comprises:

[0011] At least two source driver chips as described above, each of the source driver chips is used to generate a target data signal according to the initial data signal and transmit the target data signal to the panel body;

[0012] A timing control chip is electrically connected to the source driver chip, and is used to control the source driver chip to generate the first latch signal in the first mode, and to control the source driver chip to generate the second latch signal in the second mode.

[0013] In a third aspect, the present application further provides a method for driving a display panel, for driving the display panel as described above, comprising:

[0014] generating the first latch signal in the first mode, the first latch signal including a first delayed sub-signal, an end time of the first delayed sub-signal in the first latch signal being used to control latching of an initial data signal, and latching the initial data signal according to the first latch signal;

[0015] generating a second latch signal in the second mode, the second latch signal including a second delayed sub-signal, an end time of the second delayed sub-signal in the second latch signal being used to control latching of the initial data signal, and latching the initial data signal according to the second latch signal;

[0016] The step of generating the first latch signal in the first mode includes:

[0017] generating first data according to a first signal to be counted in the first mode;

[0018] generating the first latch signal according to the first data;

[0019] Wherein, the step of generating second data according to the second signal to be counted in the second mode includes:

[0020] generating second data according to a second signal to be counted in the second mode;

[0021] The second latch signal is generated according to the second data. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] FIG1 , FIG3 , FIG7 and FIG8 are respectively multiple structural block diagrams of the source driver chip provided in the embodiments of the present application.

[0023] FIG2 , FIG4 , FIG5 and FIG6 are waveform diagrams of some signals in the display panel provided in the embodiments of the present application respectively.

[0024] FIG9 and FIG10 are two flow charts of the display panel driving method provided in the embodiments of the present application.

[0025] FIG11 is a circuit diagram of a first delay subunit provided in an embodiment of the present application.

[0026] FIG12 is a circuit diagram of a first XOR subunit provided in an embodiment of the present application. Modes for Carrying Out the Invention

[0027] The following will be combined with the accompanying drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the embodiments described are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative efforts are within the scope of protection of this application.

[0028] In the description of this application, the terms "first", "second", etc. are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" or "second" may explicitly or implicitly include one or more of the said features. In addition, it should be noted that the drawings only provide structures that are closely related to the present invention, and some details that are not closely related to the invention are omitted. The purpose is to simplify the drawings and make the invention clear at a glance, rather than to indicate that the actual device is exactly the same as the drawings, and it is not intended to limit the actual device.

[0029] References to "embodiments" herein mean that a particular feature, structure, or characteristic described in connection with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase at various times in the specification does not necessarily refer to the same embodiment, nor does it constitute an independent or alternative embodiment that is mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0030] Beneficial effects: The present application provides a source driver chip, a display panel, and a driving method thereof, wherein the source driver chip has a first mode and a second mode, and is used to generate first data according to a first signal to be counted in the first mode and generate a first latch signal according to the first data, and to generate second data according to a second signal to be counted in the second mode and generate a second latch signal according to the second data; wherein the first latch signal includes a first delayed sub-signal, and the second latch signal includes a second delayed sub-signal, the end time of the first delayed sub-signal in the first latch signal is used to control the latching of an initial data signal, and the end time of the second delayed sub-signal in the second latch signal is used to control the latching of the initial data signal; wherein, by setting the end time of the second delayed sub-signal to be earlier than the end time of the first delayed sub-signal, the "minimum gear" in the two modes is different, then for two source driver chips with a smaller "distance difference", they can be set to operate in the second mode, so that the difference between the end times of the delayed sub-signals in the two latch signals is smaller, so that the difference in the time when the corresponding two target data signals are output to the corresponding multiple sub-pixels is smaller, thereby reducing the risk of split screen phenomenon.

[0031] The present application provides a source driver chip, which may include but is not limited to the following embodiments and combinations of the following embodiments.

[0032] In one embodiment, as shown in Figures 1 and 2, the source driver chip 10 has a first mode M1 and a second mode M2. The source driver chip 10 includes: a counting module 101, configured to generate first data according to a first signal to be counted CT in the first mode M1, and to generate second data according to a second signal to be counted CK3 in the second mode M2; a latch signal generating module 102, electrically connected to the counting module 101, configured to generate a first latch signal TP1 according to the first data in the first mode M1, and to generate a second latch signal TP2 according to the second data in the second mode M2; wherein, as shown in Figure 2, the first latch signal TP1 includes a first delayed sub-signal (duration period is "TP delay1"), and the second latch signal TP2 includes a second delayed sub-signal (duration period is "TP delay2"), the end time of the first delayed sub-signal in the first latch signal TP1 is used to control the latching of the initial data signal data0, the end time of the second delayed sub-signal in the second latch signal TP2 is used to control the latching of the initial data signal data0, and the end time of the second delayed sub-signal is earlier than the end time of the first delayed sub-signal.

[0033] Specifically, as shown in FIG3 , the source driver chip 10 may further include a shift register 103 loaded with a source sampling clock signal SCLK, a latch 104 (including a first latch 1041 or a second latch 1042 ) loaded with a corresponding image signal RGB Data and a corresponding latch signal TP (a first latch signal TP1 or a second latch signal TP2 ), a digital-to-analog converter 105, and a buffer 106. The shift register 103 can generate a sampling signal based on the source sampling clock signal SCLK to be input to the first latch 1041. The first latch 1041 can sample the corresponding image signal RGB Data according to the sampling signal to obtain multiple initial data voltages corresponding to multiple sub-pixels located in the same row (contained in a corresponding initial data signal data0). The first latch 1041 transmits the initial data voltages to the digital-to-analog converter 105 after being latched by itself and another sub-latch. The digital-to-analog converter 105 can convert the multiple data voltages (essentially digital voltages) in the initial data signal data0 into analog data voltages based on the gamma reference voltage. Furthermore, the buffer can amplify the analog data voltages to obtain multiple target data voltages (constituting the target data signal data1) loaded onto the corresponding multiple sub-pixels.

[0034] It should be noted that the initial data signals corresponding to the multiple sub-pixels of each level are sequentially transmitted through the first latch 1041 and the second latch 1042 and then transmitted to the digital-to-analog converter 105. For example, the source driver chip 10 is processing the initial data signal data0(i) corresponding to the multiple sub-pixels of the i-th level as an example. The first latch 1041 can be used to latch the initial data signal data0(i+1) including the multiple initial data voltages corresponding to the multiple sub-pixels of the (i+1)-th level, and the second latch 1042 can be used to latch the initial data signal data0(i) including the multiple data voltages corresponding to the multiple sub-pixels of the i-th level located before the (i+1)-th level. Furthermore, the multiple initial data voltages in the initial data signal data0(i) output by the second latch 1042 are sequentially transmitted through the corresponding digital-to-analog converter 105 and the buffer 106 to generate a plurality of target data voltages to be loaded onto the corresponding multiple sub-pixels.

[0035] Among them, the second latch 1042 can control the time when the initial data signal data0 enters the second latch 1042 and the time when it leaves the second latch 1042 under the control of the latch signal. Specifically, as shown in Figure 2, the source driver chip 10 can also receive a P2P signal to generate a corresponding latch signal according to the P2P signal. For example, the P2P signal can include a row end sub-signal CE, a signal to be counted (a first signal to be counted CT or a second signal to be counted CK3), and a row start sub-signal CS arranged in sequence. It can be considered that the source driver chip 10 can start generating the latch signal after recognizing the signal to be counted after the row end sub-signal CE. That is, the starting time of the latch signal is the same as the starting time of the signal to be counted. The specific waveform of the latch signal can be determined by at least the specific waveform of the signal to be counted. Each latch signal (first latch signal TP1 or second latch signal TP2) may include a sequentially arranged delayed sub-signal (a first delayed sub-signal included in first latch signal TP1, a second delayed sub-signal included in second latch signal TP2) and a latch sub-signal (a first latch sub-signal subsequent to the first delayed sub-signal, a second latch sub-signal subsequent to the second delayed sub-signal). The end time of the delayed sub-signal may be equal to the start time of the corresponding latch sub-signal. Taking the i-th level initial data signal data0(i) as an example, it can be assumed that at the start time of the latch sub-signal (e.g., the end time of the corresponding first delayed sub-signal or second delayed sub-signal, i.e., the end time of "TP delay1" or "TP delay2"), the initial data signal data0 is input into the second latch 1042, and at the end time of the latch sub-signal, the second latch 1042 outputs the initial data signal data0.

[0036] In this application, the amplitude of the delayed sub-signal in each latch signal is smaller than the amplitude of the corresponding latch sub-signal as an example, that is, it can be considered that at the end time of the delayed sub-signal (that is, the starting time of the latch sub-signal), the latch signal is on the rising edge.

[0037] That is, for source driver chips 10 located at different locations, while the start time of the delayed sub-signal and the duration of the latched sub-signal remain constant, the end time of the delayed sub-signal, or the duration of the delayed sub-signal's duration, is set differently. This allows the corresponding initial data signal data0 to be output at different times, thereby compensating for the difference in charging duration caused by the distance differences between different source driver chips 10 and the multiple sub-pixels, and ensuring that the corresponding target data signal data1 is output to the corresponding multiple sub-pixels at the same time. The duration of the delayed sub-signal in each source driver chip 10 increases incrementally based on the "minimum gear" as a base value, i.e., the end time of the delayed sub-signal is delayed based on the "minimum gear" as a base value. Furthermore, the difference in the duration of the two delayed sub-signals in the two latched signals corresponding to any two source driver chips 10 can be equal to an integer multiple of the "minimum gear".

[0038] It should be noted that, for the two source driver chips 10 corresponding to the smaller "distance difference" mentioned above, the current minimum gear is relatively large, which is 9UI (UI is the minimum unit of delay). For the two source driver chips 10 corresponding to the smaller "distance difference" mentioned above, for example, corresponding to two adjacent display areas, since the two source driver chips 10 cannot set a smaller output "moment difference" (at least the difference is 9UI), the time difference between the data signals output by the two and transmitted to the corresponding two display areas is too large, resulting in a split screen phenomenon.

[0039] The first mode M1 and the second mode M2 ​​described above are merely used to represent the two modes in which the source driver chip 10 generates the first latch signal and the second latch signal, respectively, and are provided for conceptual illustration only. Of course, when the source driver chip 10 generates the first latch signal and when it generates the second latch signal can be determined based on other signals, that is, when the driver chip is in the first mode M1 and when it is in the second mode M2, as will be discussed later.

[0040] It can be understood that the source driver chip 10 in this embodiment can have at least two working modes, the first mode M1 and the second mode M2, and the moments for controlling the latching of the corresponding initial data signals (the end moments of the delayed sub-signals in the two latch signals) generated in the two modes are different, that is, the above-mentioned "minimum gears" are different. In the case of two source driver chips 10 corresponding to a smaller "distance difference", they can be set to work in the second mode M2, so that the difference between the end moments of the delayed sub-signals in the two latch signals is smaller, so that the difference in the moments when the corresponding two target data signals data1 are output to the corresponding multiple sub-pixels is smaller, thereby reducing the risk of the split screen phenomenon; of course, in the case of two source driver chips 10 corresponding to a larger "distance difference", they can be set to work in the first mode M1 to compensate for the larger difference in charging time of the respective sub-pixels caused by the larger "distance difference".

[0041] In one embodiment, as shown in FIG. 4 and FIG. 5 , the first to-be-counted signal CT and the second to-be-counted signal CK3 are both periodic signals, and the period of the second to-be-counted signal CK3 is smaller than the period of the first to-be-counted signal CT.

[0042] Specifically, in combination with Figures 2, 4 and 5, as discussed above, the starting time of the delayed sub-signal in the latch signal is equal to the starting time of the signal to be counted, and the duration of the duration period of the delayed sub-signal in the latch signal can at least be determined based on the signal to be counted. Here, the signal to be counted (the first signal to be counted CT and the second signal to be counted CK3) is a periodic signal and a square wave signal as an example. The counting module 101 can count once for each rising edge of the signal to be counted, and at any moment, the number of times currently counted can be set to the data at the current moment (the first data or the second data), that is, the data is related to the duration of the count and the period of the signal to be counted. At any moment, the value of the corresponding latch signal at this time can be determined based on the size relationship between the specific value of the current data and the preset value.

[0043] As shown in FIG2 and FIG4 , for example, the first signal to be counted CT is a square wave signal with a period equal to 9 UI (1 UI can be understood as a unit time length), and the counting module 101 can count each rising edge of the first signal to be counted CT once, with the first rising edge as the starting point of counting. Then, at the moment "18 UI", the first data is equal to 2 (the value of "first data" in FIG4 is equal to the number of arrows generated at the current moment and before, and each rising edge of the first signal to be counted CT generates an arrow). Similarly, at the moment "n×UI", the first data is equal to n / 9. If the first preset value is equal to x1, since the first data increases from 0, it can be considered that when the first data is less than or equal to x1, the value corresponding to the first latch signal TP1 is controlled to be the first value (corresponding to the first delay sub-signal), and when the first data is greater than x1, the value corresponding to the first latch signal TP1 is controlled to be the second value (corresponding to the first latch sub-signal). For example, when the second value is greater than the first value, it is considered that the first latch signal TP1 jumps upward when the first data changes from less than or equal to x1 to greater than x1.

[0044] As shown in Figure 2 and Figure 5, the difference is that the period of the second signal to be counted CK3 is equal to UI, so at the moment "n×UI", the first data is equal to n. If the second preset value is equal to x2, it can be considered that when the second data is less than or equal to x2, the value corresponding to the second latch signal TP2 is controlled to be the first value (corresponding to the second delay sub-signal), and when the second data is greater than x2, the value corresponding to the second latch signal TP2 is controlled to be the second value (corresponding to the second latch sub-signal). For example, when the second value is greater than the first value, it is considered that when the second data changes from less than or equal to x1 to greater than x1, the second latch signal TP2 jumps upward.

[0045] It can be understood that in this embodiment, the period of the second signal to be counted CK3 is set to be smaller than the period of the first signal to be counted CT, that is, the minimum value of the duration of the second delayed sub-signal in the second mode (i.e., the "minimum gear") can be smaller than the minimum value of the duration of the first delayed sub-signal in the first mode (i.e., the "minimum gear"), thereby realizing the above-mentioned two different "minimum gears".

[0046] In one embodiment, as shown in Figure 1, the source driver chip 10 further includes: a to-be-counted signal generating module 107, electrically connected to the counting module 101, for generating the second to-be-counted signal CK3; wherein, as shown in Figure 6, the to-be-counted signal generating module 107 is used to generate the second to-be-counted signal CK3 according to the initial to-be-counted signal CK1 or the first to-be-counted signal CT, the initial to-be-counted signal CK1, the first to-be-counted signal CT and the second to-be-counted signal CK3 are all periodic signals, and the period of the initial to-be-counted signal CK1 is less than the period of the first to-be-counted signal CT.

[0047] Specifically, it can be considered that the first signal to be counted CT can be obtained by the source driver chip 10 from the outside world (including but not limited to the timing control chip) for counting by the counting module 101, and the newly added second signal to be counted CK3 with a smaller period can be generated by the newly added signal to be counted generation module 107 for counting by the counting module 101.

[0048] Specifically, here we take the example of the period of the first signal to be counted CT being equal to 9UI. If the period of the initial signal to be counted CK1 is greater than 9UI, there is no need to set the initial signal to be counted CK1, and the first signal to be counted CT is directly up-converted in sequence to obtain the second signal to be counted CK3 with a smaller period. If the period of the initial signal to be counted CK1 is less than 9UI, for example, as shown in FIG6 , it is equal to 4UI, then the initial signal to be counted CK1 is up-converted in sequence to obtain the second signal to be counted CK3 with a smaller period. For example, the initial signal to be counted CK1 is first up-converted to obtain the second transition signal CK11 with a period equal to 2UI, and then the second transition signal CK11 is up-converted to obtain CK3 with a period equal to UI.

[0049] Of course, since the period of the initial signal to be counted CK1 is also smaller than the period of the first signal to be counted CT, the initial signal to be counted CK1 can also be directly set as the second signal to be counted CK3 for the counting module 101 to perform counting processing. As discussed above, at this time, under the condition that other conditions are the same, the end time of the second delayed sub-signal can also be achieved earlier than the end time of the first delayed sub-signal, so as to achieve a smaller "minimum gear" in the second mode M2, thereby being suitable for two source driver chips 10 corresponding to a smaller "distance difference".

[0050] In one embodiment, as shown in FIG7 , the signal-to-be-counted generating module 107 includes a first switch unit 1071, an electrically connected first switch unit 1071, and a frequency increasing unit 1072, wherein the frequency increasing unit 1072 is electrically connected to the counting module 101. The first switch unit 1071 is configured to control, in the second mode M2, the transmission of the initial signal to be counted CK1 or the first signal to be counted CT to the frequency increasing unit 1072 according to the first switch signal. The frequency increasing unit 1072 is configured to generate the second signal to be counted CK3 according to the initial signal to be counted CK1 or the first signal to be counted CT in the second mode M2. In this embodiment, there is no limitation on the source of the initial signal to be counted CK1 or the first signal to be counted CT required to be obtained by the first switch unit 1071, nor on the source of the first switch control signal. In other words, there is no limitation on the connection method between the first switch unit 1071 and the outside world.

[0051] Specifically, the first switching unit 1071 may include a first switching transistor Q100. The gate of the first switching transistor Q100 may be loaded with the first switching signal, the source of the first switching transistor Q100 may be loaded with the initial signal to be counted CK1 or the first signal to be counted CT (in FIG. 7 , only the initial signal to be counted CK1 is used as an example), and the drain of the first switching transistor Q100 may be electrically connected to the frequency increasing unit 1072. The first switching signal may be an active voltage in the second mode M2 ​​to turn on the first switching transistor Q100, so that the initial signal to be counted CK1 or the first signal to be counted CT is transmitted to the frequency increasing unit 1072 via the first switching transistor Q100. The frequency increasing unit 1072 then generates the second signal to be counted CK3 with a smaller period based on the initial signal to be counted CK1 or the first signal to be counted CT, which has a larger period and a smaller frequency.

[0052] In one embodiment, as shown in combination with FIG6 and FIG7, the frequency up-conversion unit 1072 includes: a first delay subunit 10721, electrically connected to the first switch unit 1071, for generating a first transition signal CK2 according to one of the initial signal to be counted CK1 and the first signal to be counted CT (herein, the initial signal to be counted CK1 is taken as an example) and a first control signal Ctrl1 in the second mode M2, wherein the first transition signal CK2 is a signal obtained by delaying the first signal to be counted CT by a first preset time length H1, and the first preset time length H1 is not equal to 0; a first XOR subunit 10722, electrically connected to the first delay subunit 10721 and the first switch unit 1071, for generating a first transition signal CK2 according to one of the initial signal to be counted CK1 and the first signal to be counted CT (herein, the initial signal to be counted CT is taken as an example) in the second mode M2. The first XOR subunit 10722 generates the second to-be-counted signal CK3 or the second transition signal CK11 (taking the generation of the second transition signal CK11 as an example here) and the first transition signal CK2 to generate the second to-be-counted signal CK3 or the second transition signal CK11 (taking the generation of the second transition signal CK11 as an example here). The second transition signal CK11 is used to generate the second to-be-counted signal CK3. The second to-be-counted signal CK3 or the second transition signal CK11 generated by the first XOR subunit 10722 is a signal obtained by an XOR operation of the initial to-be-counted signal CK1, one of the first to-be-counted signal CT (taking the initial to-be-counted signal CK1 as an example here) and the first transition signal CK2. The period of the second to-be-counted signal CK3 or the second transition signal CK11 generated by the first XOR subunit 10722 is half of the period transmitted to one of the initial to-be-counted signal CK1 or the first to-be-counted signal CT.

[0053] It can be understood that the first delay sub-unit 10721 in the frequency up-conversion unit 1072 in this embodiment can perform delay processing on the received initial signal to be counted CK1 or the first signal to be counted CT (here taking the initial signal to be counted CK1 as an example) under the action of the first control signal Ctrl1. For example, the initial signal to be counted CK1 with a period of 4UI can be delayed by 1UI to obtain the first transition signal CK2 with a period of still 4UI. Furthermore, the first XOR sub-unit 10722 in the frequency up-conversion unit 1072 can perform an XOR operation on the received initial signal to be counted CK1 and the first transition signal CK2 to obtain the second transition signal CK11 with a period of 2UI, thereby realizing the halving of the period of the initial signal to be counted CK1.

[0054] Similarly, since the period of the second transition signal CK11 is also shorter than the period of the first signal to be counted CT, the second transition signal CK11 can be directly set as the second signal to be counted CK3 for counting by the counting module 101. As discussed above, in this case, under the condition that other conditions are the same, the end time of the second delayed sub-signal can also be earlier than the end time of the first delayed sub-signal, thereby achieving a smaller "minimum gear" in the second mode M2, thereby being suitable for two source driver chips 10 corresponding to smaller "distance differences". Of course, the second transition signal CK11 can also be further frequency-upgraded to obtain the second signal to be counted CK3 with a smaller period.

[0055] 7 and 11 , the first delay sub-unit 10721 may be a gated D latch, which may be, but is not limited to, a transmission-gated D latch or a logic-gated D latch. The latter is used as an example herein. The first delay sub-unit 10721 may include NOR gates G1 and G2, AND gates G3 and G4, and a NOT gate G5 electrically connected according to the connection relationship in FIG. 11 , wherein one input terminal of the AND gate G3 and one input terminal of the AND gate G4 may be configured as a data input terminal D (which may be loaded with the initial to-be-counted signal CK1) and an enable terminal E (which may be loaded with the first control signal Ctrl1) of the logic-gated D latch, respectively. A NOT gate G5 may be connected between the other input terminal of the AND gate G4 and the data input terminal D. G1, G2, G3, G4 and their connection relationship may constitute an SR latch. The output terminal of the NOR gate G2 and the output terminal of the NOR gate G1 may be configured as an output terminal Q (which may output the first transition signal CK2) and an inverting output terminal `Q' of the logic-gated D latch, respectively. Since the circuit will be locked in the state determined by the initial to-be-counted signal CK1 immediately before the value of the first control signal Ctrl changes from 1 to 0, the state of the logic-gated D latch can be kept unchanged when the value of the first control signal Ctrl1 is 0, so that 1-bit binary data can be stored. Moreover, when the value of the first control signal Ctrl1 is 1, the first transition signal CK2 outputted from the output terminal Q can change in accordance with the state of the initial to-be-counted signal CK1 loaded at the data input terminal D. Therefore, the first transition signal CK2 can be obtained by delaying the initial to-be-counted signal CK1, and the waveforms can be the same.

[0056] As shown in conjunction with FIG7 and FIG12 , the first XOR subunit 10722 can be an XOR gate, which can include NOT gates G6, G7, G8, and G9 electrically connected as shown in FIG12 . The two input terminals of NOT gate G6 are configured as input terminal A (which can be loaded with the initial signal to be counted CK1) and input terminal B (which can be loaded with the first transition signal CK2) of the XOR gate, respectively. The output terminal of NOT gate G9 can be configured as output terminal Y of the XOR gate (which can output the second transition signal CK11). Due to the characteristic of the XOR gate being "the same is 0, the different is 1," that is, when the value of the initial signal to be counted CK1 and the value of the first transition signal CK2 are both 0 or both 1, the output value of the second transition signal CK11 is 0. When one of the two values ​​is 0 and the other is 1, the output value of the second transition signal CK11 is 1.

[0057] In one embodiment, as shown in combination with FIG6 and FIG7, the first XOR subunit 10722 is used to generate the second transition signal CK11, and the frequency up-conversion unit 1072 further includes: a second delay subunit 10723, electrically connected to the first XOR subunit 10722, and used to generate a third transition signal CK22 according to the second transition signal CK11 and the second control signal Ctrl2 in the second mode M2, wherein the third transition signal CK22 is a signal obtained by delaying the second transition signal CK11 by a second preset time length H2, and the second preset time length H2 is not equal to 0; The second XOR sub-unit 10724 is electrically connected to the second delay sub-unit 10723 and the first XOR sub-unit 10722, and is used to generate the second signal to be counted CK3 based on the third transition signal CK22 and the second transition signal CK11. The second signal to be counted CK3 generated by the XOR module is a signal obtained by an XOR operation of the third transition signal CK22 and the second transition signal CK11. The period of the second signal to be counted CK3 generated by the second XOR sub-unit 10724 is half of the period of the second transition signal CK11.

[0058] It can be understood that in this embodiment, a second delay sub-unit 10723 and a second XOR sub-unit 10724 are further provided in the frequency up-conversion unit 1072. The second delay sub-unit 10723 can perform delay processing on the received second transition signal CK11 under the action of the second control signal Ctrl2. For example, the second transition signal CK11 with a period of 2UI can be delayed by (1 / 2) UI to obtain a third transition signal CK22 with a period of the same 2UI. Furthermore, the second XOR sub-unit 10724 can perform an XOR operation on the received third transition signal CK22 and the second transition signal CK11 to obtain a second signal to be counted CK3 with a period of 1UI, thereby reducing the period of the initial signal to be counted CK1 to 1 / 4 of the original period.

[0059] At this time, the period of the second to-be-counted signal CK3 can be further reduced to achieve a further smaller “minimum gear” in the second mode M2 ​​, thereby being suitable for two source driver chips 10 corresponding to a smaller “distance difference”.

[0060] Among them, the second delay sub-unit 10723 can also be a gated D latch, which can be understood by referring to the above discussion on the first delay sub-unit 10721. Among them, the second transition signal CK11, the second control signal Ctrl2, and the third transition signal CK22 can be understood by analogy with the above-mentioned initial to-be-counted signal CK1, the first control signal Ctrl1, and the first transition signal CK2, respectively.

[0061] Similarly, the second XOR sub-unit 10724 can also be an XOR gate, which can be understood by referring to the above discussion on the first XOR sub-unit 10722, wherein the second transition signal CK11, the third transition signal CK22, and the second to-be-counted signal CK3 can be understood by analogy with the above-mentioned first transition signal CK2, the initial to-be-counted signal CK1, and the second transition signal CK11, respectively.

[0062] In one embodiment, as shown in FIG1 , the source driver chip 10 further includes a selection module 108 electrically connected to the counting module 101 and configured to control the counting module 101 to load the first signal to be counted CT to enter the first mode M1 or to load the second signal to be counted CK3 to enter the second mode M2 ​​based on an input signal Input. It is understood that, as previously discussed, the counting module 101 can receive the first signal to be counted CT generated by an external source (e.g., but not limited to, a timing control chip) or the second signal to be counted CK3 generated by the signal to be counted generation module 107. Furthermore, in this embodiment, the selection module 108 is further configured to control the counting module 101 to load the first signal to be counted CT with a larger period or the second signal to be counted CK3 with a smaller period based on the input signal Input (which can be set in advance based on the distances between the current source driver chip 10 and the previous source driver chip 10 and the plurality of sub-pixels), thereby achieving an appropriate "minimum gear."

[0063] In combination with the above discussion, it can be seen that whether the source driver chip 10 should currently be in the first mode M1 or the second mode M2 ​​can be set according to the current input signal Input. The input signal Input can be determined based on the pre-debugging results of the two adjacent source driver chips 10 in the display panel. For example, the distance between the two adjacent source driver chips 10 in the display panel is relatively close, that is, the accuracy requirement for the "minimum gear" is relatively high. At this time, the specific value of the input signal Input may be set to make the selection module 108 determine that the source driver chip 10 should be in the second mode M2. The specific value of Input can be determined based on the results of the previous debugging (that is, the split-screen phenomenon of the display panel can be eliminated).

[0064] In which, the selection module 108 may essentially include a comparator circuit or a switching circuit. If the selection module 108 is a comparator, the two input ends of the comparator can be loaded with the input signal Input and the reference signal respectively. The comparator can output a corresponding signal according to the size relationship between the input signal Input and the reference signal to control the counting module 101 to load the first signal to be counted CT or the second signal to be counted CK3. Similarly, if the selection module 108 is a switching circuit, the input end of the switching circuit is loaded with the input signal Input, and the output end of the switching circuit can output a corresponding signal according to the size of the input signal Input to control the counting module 101 to load the first signal to be counted CT or the second signal to be counted CK3.

[0065] In one embodiment, as shown in conjunction with FIG1 and FIG7 , the source driver chip 10 further includes: a logic module 109 electrically connected between the counting module 101 and the latch signal generating module, configured to generate first judgment data based on the first data in the first mode M1, and to generate second judgment data based on the second data in the second mode M2; wherein, as shown in FIG8 , the latch signal generating module includes: a second switch unit 1021 electrically connected to the logic module, configured to control the end time of the first delayed sub-signal in the first latch signal TP1 based on the first judgment data in the first mode M1, and to control the end time of the second delayed sub-signal in the second latch signal TP2 based on the second judgment data in the second mode M2. wherein, the initial to-be-counted signal CK1 can be generated by, but is not limited to, the logic module and transmitted to the first switch unit 1071.

[0066] Furthermore, the input signal Input can be stored in a register (whether it is integrated into the source driver chip 10 is not limited), and the selection module 108 can read the input signal Input in this register (which can essentially be the value of the register, which can be 0 or 1). Furthermore, the selection module 108 can also be integrated into the logic module 109.

[0067] It should be noted that the source driver chip 10 can be in the first mode M1 or the second mode M2 ​​at any moment, and the counting module 101 generates the first data and the second data in the two modes respectively. Therefore, it can be considered that the data received by the logic module at each moment can be one of the first data and the second data to generate the corresponding first judgment data or the corresponding second judgment data, and then the first judgment data or the second judgment data is applied to the second switching unit to control the end time of the first delayed sub-signal in the first latch signal TP1 or the end time of the second delayed sub-signal in the second latch signal TP2, and combined with the other conditions discussed above, the complete first latch signal TP1 and the second latch signal TP2 are generated respectively.

[0068] Specifically, the second switching unit may include a second switching transistor Q1, wherein the gate of the second switching transistor is electrically connected to the logic module, the source of the second switching transistor is loaded with the operating voltage VDD, the drain of the second switching transistor is electrically connected to a resistor R, and is configured to output the latch signal TP. Here, taking the first mode M1 as an example for illustration, the logic module may compare the first data with a preset first threshold value at each moment. If the first data is less than or equal to the first threshold value, the first determination data may be considered equal to the first value for controlling the second switching transistor to be turned off, and the latch signal TP may maintain its original value. If the first data is greater than the first threshold value, the first determination data may be considered equal to the second value for controlling the second switching transistor to be turned off, and the latch signal TP may change from its original value to equal to the operating voltage VDD (this also marks the end time of the first delayed sub-signal). It is understandable that the first data may gradually increase over time. When the first data is greater than the second threshold value (greater than the first threshold value), the first determination data may be considered equal to the first value for controlling the second switching transistor to be turned off again, and this also marks the end time of the first latch sub-signal.

[0069] It should be noted that the modules or devices mentioned in this application, such as the counting module, latch signal generating module, shift register, first latch, second latch, digital-to-analog converter, buffer, signal generating module to be counted, selection module, logic module, etc., can actually be composed of at least one component, for example, can include at least one of a transistor, a capacitor, a resistor, and wires electrically connected between different components. The specific composition can be referred to the discussion above.

[0070] The present application also provides a display panel, which includes a panel body and a driver chip electrically connected to the panel body, the driver chip including: at least two source driver chips 10 as described above, each source driver chip 10 is used to generate a target data signal data1 according to the initial data signal, and transmit the target data signal data1 to the panel body; a timing control chip, electrically connected to the source driver chip 10, used to control the source driver chip 10 to generate the first latch signal TP1 in the first mode M1, and used to control the source driver chip 10 to generate the second latch signal TP2 in the second mode M2.

[0071] Specifically, in conjunction with the above discussion regarding FIG. 3 , it can be seen that the timing control chip can transmit corresponding image signals RGB Data and latch signals TP to each source driver chip 10 . The shift register in the source driver chip 10 can process the image signals RGB Data to generate initial data signals. The latch in the source driver chip 10 can process the initial data signals based on the latch signals TP to generate data signals, which are then converted into corresponding analog data voltages (constituting target data signals data1) acting on multiple sub-pixels in the panel body via the digital-to-analog converter 105 and the buffer 106 . The first to-be-counted signal CT acting on the counting module 101 in the first mode M1 can be generated by the timing control chip, and the second to-be-counted signal CK3 acting on the counting module 101 in the second mode M2 ​​can be generated by the counting signal generation module.

[0072] The present application also provides a display panel driving method for driving the display panel as described above, as shown in FIG9 , which may include but is not limited to the following steps, and the order of the following steps is not limited.

[0073] S1, generating the first latch signal in the first mode, the first latch signal including a first delayed sub-signal, the end time of the first delayed sub-signal in the first latch signal is used to control the latching of the initial data signal, and the initial data signal is latched according to the first latch signal.

[0074] S2, generates the second latch signal in the second mode, the second latch signal includes a second delayed sub-signal, the end time of the second delayed sub-signal in the second latch signal is used to control the latching of the initial data signal, and the initial data signal is latched according to the second latch signal.

[0075] Wherein, the step S1 may include the following steps:

[0076] generating first data according to a first signal to be counted in the first mode;

[0077] generating the first latch signal according to the first data;

[0078] Wherein, the step S2 may include the following steps:

[0079] generating second data according to a second signal to be counted in the second mode;

[0080] The second latch signal is generated according to the second data.

[0081] Specifically, the selection module 108 can obtain the first signal to be counted for generating the first latch signal and control the counting module 101 to load the first latch signal to be in the first mode, or obtain the second signal to be counted for generating the second latch signal and control the counting module 101 to load the second latch signal to be in the second mode, so that the counting module 101 can generate the first data or the second data, and can be combined with the function of the logic module to control the latch signal generation module to generate the first latch signal or the second latch signal according to the first data or the second data, so as to latch the initial data signal.

[0082] That is, before step S1 and step S2, the following step may be included: according to the input signal, obtaining the first to-be-counted signal for generating the first latch signal to be in the first mode, or obtaining the second to-be-counted signal for generating the second latch signal to be in the second mode.

[0083] Specifically, as shown in FIG10 , regardless of being in the first mode or the second mode, the driving method of the display panel may include but is not limited to the following steps:

[0084] S01, identifying a first signal to be counted or a second signal to be counted;

[0085] The execution subject may be the counting module 101, which may be considered to identify the first signal to be counted in the first mode and the second signal to be counted in the second mode, which may be specifically described above.

[0086] S02, generating first data or second data;

[0087] The execution subject may be the counting module 101, which may be considered to generate the first data according to the first signal to be counted, or to generate the second data according to the second signal to be counted, which may be specifically described above.

[0088] S03, determining whether the current first data is greater than a first critical value, or whether the second data is greater than a third critical value;

[0089] The execution subject may be a logic module, which may be specifically described above;

[0090] If greater than, execute:

[0091] S04, generating a rising edge in the latch signal;

[0092] The execution subject may be a latch signal generation module. This description is based on an example where the amplitude of the delayed sub-signal in the latch signal is less than the amplitude of the corresponding latch sub-signal. This may also be understood as the end time of the delayed sub-signal (i.e., the start time of the latch sub-signal). The details may be described above.

[0093] S05, maintaining the high level state in the latch signal;

[0094] The execution subject may be a latch signal generation module, which may be understood as generating and maintaining a latch sub-signal in the latch signal from this moment on, and the details may be described above.

[0095] S06, determining whether the current first data is greater than a second critical value, or whether the second data is greater than a fourth critical value;

[0096] The execution subject may be a logic module. It should be noted that the first signal to be counted and the second signal to be counted are both periodic signals. The logic module executes step S02 at every moment to generate the first data or the second data corresponding to each moment, so that the first data or the second data is updated in real time. The details can be described above.

[0097] If greater than, execute:

[0098] S07, generates a falling edge in the latch signal and holds it;

[0099] Among them, the execution subject can be a latch signal generation module. It can be understood that at this time, the end time of the latch sub-signal is reached, and the end time of the latch signal is also reached. No rising edge will be generated, so it will remain a falling edge. The details can be described above.

[0100] The above is a detailed introduction to the source driver chip, display panel and driving method thereof provided in the embodiments of the present application. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A source driver chip, the source driver chip having a first mode and a second mode, wherein: The source driver chip comprises: a counting module, configured to generate first data according to a first signal to be counted in the first mode, and to generate second data according to a second signal to be counted in the second mode; a latch signal generating module, electrically connected to the counting module, for generating a first latch signal according to the first data in the first mode, and for generating a second latch signal according to the second data in the second mode; Among them, the first latch signal includes a first delayed sub-signal, the second latch signal includes a second delayed sub-signal, the end time of the first delayed sub-signal in the first latch signal is used to control the latching of the initial data signal, the end time of the second delayed sub-signal in the second latch signal is used to control the latching of the initial data signal, and the end time of the second delayed sub-signal is earlier than the end time of the first delayed sub-signal.

2. The source driver chip according to claim 1, wherein: The first signal to be counted and the second signal to be counted are both periodic signals, and the period of the second signal to be counted is smaller than the period of the first signal to be counted.

3. The source driver chip according to claim 2, wherein: The counting module is used to count once at each rising edge of the first signal to be counted, and the first data is equal to the current count number; The counting module is further used for counting once at each rising edge of the second signal to be counted, and the second data is equal to the current counting number.

4. The source driver chip according to claim 1, wherein: Also includes: a signal-to-be-counted generating module, electrically connected to the counting module, and configured to generate the second signal-to-be-counted; Among them, the signal to be counted generating module is used to generate the second signal to be counted according to the initial signal to be counted or the first signal to be counted, the initial signal to be counted, the first signal to be counted and the second signal to be counted are all periodic signals, and the period of the initial signal to be counted is smaller than the period of the first signal to be counted.

5. The source driver chip according to claim 3, wherein: The to-be-counted signal generating module comprises a first switch unit, an electrically connected first switch unit and a frequency increasing unit, and the frequency increasing unit is electrically connected to the counting module; Wherein, the first switch unit is used for controlling the initial signal to be counted or the first signal to be counted to be transmitted to the frequency up-conversion unit according to the first switch signal in the second mode; The frequency up-conversion unit is used to generate the second signal to be counted according to the initial signal to be counted or the first signal to be counted in the second mode.

6. The source driver chip according to claim 4, wherein: The frequency upscaling unit comprises: a first delay subunit, electrically connected to the first switch unit, for generating a first transition signal according to the initial signal to be counted, one of the first signals to be counted, and a first control signal in the second mode, wherein the first transition signal is a signal obtained by delaying the first signal to be counted by a first preset time length, and the first preset time length is not equal to 0; A first XOR subunit is electrically connected to the first delay subunit and the first switch unit, and is used to generate the second signal to be counted or the second transition signal according to the initial signal to be counted, one of the first signals to be counted and the first transition signal in the second mode, the second transition signal is used to generate the second signal to be counted, the second signal to be counted or the second transition signal generated by the XOR module is a signal obtained by XOR operation of the initial signal to be counted, one of the first signals to be counted and the first transition signal, and the period of the second signal to be counted or the second transition signal generated by the first XOR subunit is half of the period transmitted to the initial signal to be counted or the first signal to be counted.

7. The source driver chip according to claim 5, wherein: The first XOR subunit is used to generate the second transition signal, and the frequency up-conversion unit further includes: A second delay subunit, electrically connected to the first XOR subunit, for generating a third transition signal according to the second transition signal and the second control signal in the second mode, wherein the third transition signal is a signal obtained by delaying the second transition signal by a second preset time length, and the second preset time length is not equal to 0; A second XOR subunit is electrically connected to the second delay subunit and the first XOR subunit, and is used to generate the second signal to be counted according to the third transition signal and the second transition signal. The second signal to be counted generated by the XOR module is a signal obtained by XORing the third transition signal and the second transition signal. The period of the second signal to be counted generated by the second XOR subunit is half of the period of the second transition signal.

8. The source driver chip according to claim 3, wherein: Also includes: The selection module is electrically connected to the counting module, and is used to control the counting module to load the first signal to be counted so as to be in the first mode, or to control the counting module to load the second signal to be counted so as to be in the second mode according to an input signal.

9. The source driver chip according to any one of claims 2 to 8, wherein: Also includes: a logic module, electrically connected between the counting module and the latch signal generating module, and configured to generate first judgment data according to the first data in the first mode, and to generate second judgment data according to the second data in the second mode; Wherein, the latch signal generating module comprises: A second switch unit is electrically connected to the logic module, and is used to control the end time of the first delayed sub-signal in the first latch signal according to the first judgment data in the first mode, and to control the end time of the second delayed sub-signal in the second latch signal according to the second judgment data in the second mode.

10. A display panel, wherein: The invention comprises a panel body and a driving chip electrically connected to the panel body, wherein the driving chip comprises: At least two source driver chips according to claim 1, each of the source driver chips is used to generate a target data signal according to the initial data signal, and transmit the target data signal to the panel body; A timing control chip is electrically connected to the source driver chip, and is used to control the source driver chip to generate the first latch signal in the first mode, and is used to control the source driver chip to generate the second latch signal in the second mode.

11. The display panel according to claim 10, wherein: The first signal to be counted and the second signal to be counted are both periodic signals, and the period of the second signal to be counted is smaller than the period of the first signal to be counted.

12. The display panel according to claim 11, wherein: The counting module is used to count once at each rising edge of the first signal to be counted, and the first data is equal to the current count number; The counting module is further used for counting once at each rising edge of the second signal to be counted, and the second data is equal to the current counting number.

13. The display panel according to claim 10, wherein: Also includes: a signal-to-be-counted generating module, electrically connected to the counting module, and configured to generate the second signal-to-be-counted; Among them, the signal to be counted generating module is used to generate the second signal to be counted according to the initial signal to be counted or the first signal to be counted, the initial signal to be counted, the first signal to be counted and the second signal to be counted are all periodic signals, and the period of the initial signal to be counted is smaller than the period of the first signal to be counted.

14. The display panel according to claim 12, wherein: The to-be-counted signal generating module comprises a first switch unit, an electrically connected first switch unit and a frequency increasing unit, and the frequency increasing unit is electrically connected to the counting module; Wherein, the first switch unit is used for controlling the initial signal to be counted or the first signal to be counted to be transmitted to the frequency up-conversion unit according to the first switch signal in the second mode; The frequency up-conversion unit is used to generate the second signal to be counted according to the initial signal to be counted or the first signal to be counted in the second mode.

15. The display panel according to claim 13, wherein: The frequency upscaling unit comprises: a first delay subunit, electrically connected to the first switch unit, for generating a first transition signal according to the initial signal to be counted, one of the first signals to be counted, and a first control signal in the second mode, wherein the first transition signal is a signal obtained by delaying the first signal to be counted by a first preset time length, and the first preset time length is not equal to 0; A first XOR subunit is electrically connected to the first delay subunit and the first switch unit, and is used to generate the second signal to be counted or the second transition signal according to the initial signal to be counted, one of the first signals to be counted and the first transition signal in the second mode, the second transition signal is used to generate the second signal to be counted, the second signal to be counted or the second transition signal generated by the XOR module is a signal obtained by XOR operation of the initial signal to be counted, one of the first signals to be counted and the first transition signal, and the period of the second signal to be counted or the second transition signal generated by the first XOR subunit is half of the period transmitted to the initial signal to be counted or the first signal to be counted.

16. The display panel according to claim 14, wherein: The first XOR subunit is used to generate the second transition signal, and the frequency up-conversion unit further includes: A second delay subunit, electrically connected to the first XOR subunit, for generating a third transition signal according to the second transition signal and the second control signal in the second mode, wherein the third transition signal is a signal obtained by delaying the second transition signal by a second preset time length, and the second preset time length is not equal to 0; A second XOR subunit is electrically connected to the second delay subunit and the first XOR subunit, and is used to generate the second signal to be counted according to the third transition signal and the second transition signal. The second signal to be counted generated by the XOR module is a signal obtained by XORing the third transition signal and the second transition signal. The period of the second signal to be counted generated by the second XOR subunit is half of the period of the second transition signal.

17. The display panel according to claim 12, wherein: Also includes: The selection module is electrically connected to the counting module, and is used to control the counting module to load the first signal to be counted so as to be in the first mode, or to control the counting module to load the second signal to be counted so as to be in the second mode according to an input signal.

18. The display panel according to any one of claims 11 to 17, wherein: Also includes: a logic module, electrically connected between the counting module and the latch signal generating module, and configured to generate first judgment data according to the first data in the first mode, and to generate second judgment data according to the second data in the second mode; Wherein, the latch signal generating module comprises: A second switch unit is electrically connected to the logic module, and is used to control the end time of the first delayed sub-signal in the first latch signal according to the first judgment data in the first mode, and to control the end time of the second delayed sub-signal in the second latch signal according to the second judgment data in the second mode.

19. A method for driving a display panel, wherein: Used to drive the display panel according to any one of claims 10 to 18, comprising: generating the first latch signal in the first mode, the first latch signal comprising a first delayed sub-signal, the end time of the first delayed sub-signal in the first latch signal being used to control latching of an initial data signal, and latching the initial data signal according to the first latch signal; generating the second latch signal in the second mode, the second latch signal comprising a second delayed sub-signal, the end time of the second delayed sub-signal in the second latch signal being used to control latching of the initial data signal, and latching the initial data signal according to the second latch signal; Wherein, the step of generating the first latch signal in the first mode includes: generating first data according to a first signal to be counted in the first mode; generating the first latch signal according to the first data; Wherein, the step of generating second data according to the second signal to be counted in the second mode includes: generating second data according to a second signal to be counted in the second mode; The second latch signal is generated according to the second data.

20. The method for driving a display panel according to claim 19, wherein: Also includes: According to an input signal, a first to-be-counted signal for generating the first latch signal is acquired to be in the first mode, or a second to-be-counted signal for generating the second latch signal is acquired to be in the second mode.

Images