Encoding method, decoding method, and related product

Abstract

Disclosed in the present application are an encoding method, a decoding method, and a related product. The method can be applied in a low-power consumption scenario. The method comprises: performing CRC encoding on a number K1 of information bits, to obtain a first sequence of bits, the first sequence of bits comprising a number L of CRC bits, K1 being a positive integer, and L being a positive integer less than 24; performing interleaving on the first sequence of bits using a first distributed CRC interleaver, the first distributed CRC interleaver comprising a number (K2+L) of elements, and values of a (K2+L-S)-th element to a (K2+L)-th element of the first distributed CRC interleaver being sequentially (K2+L-1-S) to (K2+L-1); or, the first distributed CRC interleaver comprising a total of (K2+L) natural numbers from 0 to (K2+L-1), P being before Q in the first distributed CRC interleaver, both P and Q being integers greater than or equal to K2, and P being greater than Q. This can reduce decoding power consumption.

Description

Coding method, decoding method and related products

[0001] This application claims priority to the Chinese patent application with application number 202311613726.8 filed with the State Intellectual Property Office of China on November 28, 2023, and priority to the Chinese patent application with the invention name “Encoding method, decoding method and related products”, all contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of communication technology, and in particular to encoding methods, decoding methods and related products. Background Art

[0003] During wireless transmission, channel coding is usually used to encode and decode data, thereby improving the reliability of information transmission and reducing the error probability during transmission.

[0004] In the New Radio (NR) system, a channel coding scheme is used as follows: cyclic redundancy check (CRC) encoding is first performed on the K bits (i.e., payload bits) to be transmitted on the downlink control channel, resulting in 24 CRC bits. These 24 CRC bits are then concatenated to the end of the K bits, resulting in a message sequence consisting of 24 concatenated CRC bits. This message sequence is then interleaved using an interleaver to obtain an interleaved sequence. Finally, polar coding is performed on the interleaved sequence. In this scheme, the payload (i.e., payload bit) size K is less than or equal to 140, and the maximum length of the concatenated 24 CRC bits is 164, so the interleaver length is 164.

[0005] However, this channel coding scheme has the problems of high decoding power consumption and large resource overhead in scenarios such as low power consumption and primary downlink control information (DCI). Summary of the Invention

[0006] The embodiments of the present application disclose an encoding method, a decoding method and related products, in order to reduce decoding power consumption and resource overhead.

[0007] In a first aspect, an embodiment of the present application provides a coding method, the method comprising: performing cyclic redundancy check (CRC) encoding on K1 information bits to obtain a first bit sequence, the first bit sequence comprising the K1 information bits and L CRC bits, K1 being a positive integer, and L being a positive integer less than 24; interleaving the first bit sequence using a first distributed CRC interleaver to obtain a second bit sequence; wherein the first distributed CRC interleaver comprises (K2+L) elements, and the values ​​of the (K2+LS)th element to the (K2+L)th element of the first distributed CRC interleaver are (K2+L-1-S) to (K2+L-1) respectively, S being an integer greater than or equal to 0 and less than or equal to L, and K2 being an integer greater than or equal to K1; or, the first distributed CRC interleaver comprises a total of (K2+L) natural numbers from 0 to (K2+L-1), P in the first distributed CRC interleaver precedes Q, P and Q are both integers greater than or equal to K2, and P is greater than Q. The values ​​of the (K2+LS)th element to the (K2+L)th element of the first distributed CRC interleaver are (K2+L-1-S) to (K2+L-1) respectively, which can be replaced by: the first distributed CRC interleaver includes L natural numbers sorted from small to large and greater than or equal to K2.

[0008] In an embodiment of the present application, cyclic redundancy check (CRC) encoding is performed on K1 information bits to obtain a first bit sequence, wherein the number of CRC check bits is less than 24. The first bit sequence is interleaved using a first distributed CRC interleaver. The first distributed CRC interleaver supports DCRC encoding of shorter payloads, and a receiving end performs decoding using a deinterleaver corresponding to the first distributed CRC interleaver, thereby reducing decoding power consumption and resource overhead.

[0009] In a possible implementation, L is equal to 6, 11 or 16.

[0010] In a possible implementation, K2 is equal to 32, 40, 48, 54, 64, 70 or 100.

[0011] In a possible implementation, the first distributed CRC interleaver is obtained by arranging L element sequences in sequence, any two element sequences among the L element sequences are a first element sequence and a second element sequence, the elements included in the first element sequence are obtained based on the positions of information bits associated with the first check column, and the elements included in the second element sequence are obtained based on the positions of information bits associated with the second check column, the first check column and the second check column are any two columns in a check matrix obtained based on an L-length CRC generator polynomial, and when the maximum element in the first element sequence representing the position of the information bit associated with the first check column is greater than the maximum element in the second element sequence representing the position of the information bit associated with the second check column, the first element sequence in the first distributed CRC interleaver is sorted after the second element sequence.

[0012] In this implementation, when the maximum element representing the position of the information bit associated with the first check column in the first element sequence is greater than the maximum element representing the position of the information bit associated with the second check column in the second element sequence, the first element sequence in the first distributed CRC interleaver is sorted after the second element sequence, so that the receiving end can detect the CRC check failure earlier during decoding, thereby saving decoding power consumption.

[0013] In a possible implementation, performing cyclic redundancy check (CRC) encoding on the K1 information bits to obtain the first bit sequence includes: performing CRC encoding on the K1 information bits based on a CRC generator polynomial to obtain the first bit sequence, wherein L is equal to 6, K2 is equal to 70, the CRC generator polynomial is D^6+D^5+1, and the values ​​of the elements in the first distributed CRC interleaver are sequentially

[0014] In one possible implementation, performing cyclic redundancy check (CRC) encoding on the K1 information bits to obtain a first bit sequence includes: performing CRC encoding on the K1 information bits based on a CRC generator polynomial to obtain the first bit sequence, wherein L is equal to 6, K2 is equal to 70, the CRC generator polynomial is D^6+D^5+D^4+D^3+1, and the elements in the first distributed CRC interleaver are:

[0015] In a possible implementation, performing cyclic redundancy check (CRC) encoding on the K1 information bits to obtain a first bit sequence includes: performing CRC encoding on the K1 information bits based on a CRC generator polynomial to obtain the first bit sequence, wherein L is equal to 6, K2 is equal to 70, the CRC generator polynomial is D^6+D^4+D^3+D+1, and the elements in the first distributed CRC interleaver are

[0016] In a possible implementation, performing cyclic redundancy check (CRC) encoding on the K1 information bits to obtain a first bit sequence includes: performing CRC encoding on the K1 information bits based on a CRC generator polynomial to obtain the first bit sequence, wherein L is equal to 6, K2 is equal to 70, the CRC generator polynomial is D^6+D^3+D^2+D+1, and the elements in the first distributed CRC interleaver are

[0017] In a possible implementation, performing cyclic redundancy check (CRC) encoding on the K1 information bits to obtain the first bit sequence includes: performing CRC encoding on the K1 information bits based on a CRC generator polynomial to obtain the first bit sequence, wherein L is equal to 6, K2 is equal to 70, the CRC generator polynomial is D^6+D^5+D^2+1, and the elements in the first distributed CRC interleaver are selected.

[0018] In a possible implementation, performing cyclic redundancy check (CRC) encoding on the K1 information bits to obtain a first bit sequence includes: performing CRC encoding on the K1 information bits based on a CRC generator polynomial to obtain the first bit sequence, wherein L is equal to 6, K2 is equal to 70, the CRC generator polynomial is D^6+D^5+D^4+D^2+1, and the elements in the first distributed CRC interleaver are:

[0019] In a possible implementation, performing cyclic redundancy check (CRC) encoding on the K1 information bits to obtain the first bit sequence includes: performing CRC encoding on the K1 information bits based on a CRC generator polynomial to obtain the first bit sequence, wherein L is equal to 6, K2 is equal to 70, the CRC generator polynomial is D^6+D^3+D^2+1, and the elements in the first distributed CRC interleaver are selected.

[0020] In a possible implementation, performing cyclic redundancy check (CRC) encoding on the K1 information bits to obtain a first bit sequence includes: performing CRC encoding on the K1 information bits based on a CRC generator polynomial to obtain the first bit sequence, wherein L is equal to 6, K2 is equal to 70, the CRC generator polynomial is D^6+D^5+D^3+D^2+1, and the elements in the first distributed CRC interleaver are:

[0021] In a possible implementation, performing cyclic redundancy check (CRC) encoding on the K1 information bits to obtain the first bit sequence includes: performing CRC encoding on the K1 information bits based on a CRC generator polynomial to obtain the first bit sequence, wherein L is equal to 6, K2 is equal to 70, the CRC generator polynomial is D^6+D^5+D^4+D^3+D^2+1, and the first distributed CRC interleaver is

[0022] In a possible implementation, performing cyclic redundancy check (CRC) encoding on the K1 information bits to obtain the first bit sequence includes: performing CRC encoding on the K1 information bits based on a CRC generator polynomial to obtain the first bit sequence, wherein L is equal to 6, K2 is equal to 70, the CRC generator polynomial is D^6+D^5+D^4+D^3+D+1, and the elements in the first distributed CRC interleaver are:

[0023] In a possible implementation, performing cyclic redundancy check (CRC) encoding on the K1 information bits to obtain a first bit sequence includes: performing CRC encoding on the K1 information bits based on a CRC generator polynomial to obtain the first bit sequence, wherein L is equal to 6, K2 is equal to 70, the CRC generator polynomial is D^6+D^4+D^2+D+1, and the elements in the first distributed CRC interleaver are

[0024] In a possible implementation, performing cyclic redundancy check (CRC) encoding on the K1 information bits to obtain the first bit sequence includes: performing CRC encoding on the K1 information bits based on a CRC generator polynomial to obtain the first bit sequence, wherein L is equal to 11, K2 is equal to 70, the CRC generator polynomial is D^11+D^10+D^9+D^5+1, and the elements in the first distributed CRC interleaver are:

[0025] In a possible implementation, performing cyclic redundancy check (CRC) encoding on the K1 information bits to obtain a first bit sequence includes: performing CRC encoding on the K1 information bits based on a CRC generator polynomial to obtain the first bit sequence, wherein L is equal to 11, K2 is equal to 70, the CRC generator polynomial is D^11+D^7+D^6+D^2+1, and the elements in the first distributed CRC interleaver are:

[0026] In one possible implementation, performing cyclic redundancy check (CRC) encoding on the K1 information bits to obtain a first bit sequence includes: performing CRC encoding on the K1 information bits based on a CRC generator polynomial to obtain the first bit sequence, wherein L is equal to 11, K2 is equal to 70, the CRC generator polynomial is D^11+D^10+D^9+D^6+D^4+D^2+1, and the first distributed CRC interleaving

[0027] In one possible implementation, performing cyclic redundancy check (CRC) encoding on the K1 information bits to obtain a first bit sequence includes: performing CRC encoding on the K1 information bits based on a CRC generator polynomial to obtain the first bit sequence, wherein L is equal to 11, K2 is equal to 70, the CRC generator polynomial is D^11+D^10+D^9+D^7+D^5+D+1, and the first distributed CRC interleaver

[0028] In a possible implementation, performing cyclic redundancy check (CRC) encoding on the K1 information bits to obtain a first bit sequence includes: performing CRC encoding on the K1 information bits based on a CRC generator polynomial to obtain the first bit sequence, wherein L is equal to 11, K2 is equal to 70, the CRC generator polynomial is D^11+D^9+D^8+D^6+D^5+D+1, and the first distributed CRC interleaver

[0029] In a possible implementation, performing cyclic redundancy check (CRC) encoding on the K1 information bits to obtain a first bit sequence includes: performing CRC encoding on the K1 information bits based on a CRC generator polynomial to obtain the first bit sequence, wherein L is equal to 11, K2 is equal to 70, the CRC generator polynomial is D^11+D^10+D^9+D^8+D^7+D^5+D^4+D+1, and the first distributed

[0030] In one possible implementation, performing cyclic redundancy check (CRC) encoding on the K1 information bits to obtain a first bit sequence includes: performing CRC encoding on the K1 information bits based on a CRC generator polynomial to obtain the first bit sequence, wherein L is equal to 11, K2 is equal to 70, the CRC generator polynomial is D^11+D^10+D^3+D+1, and the elements in the first distributed CRC interleaver are:

[0031] In a possible implementation, performing cyclic redundancy check (CRC) encoding on the K1 information bits to obtain a first bit sequence includes: performing CRC encoding on the K1 information bits based on a CRC generator polynomial to obtain the first bit sequence, wherein L is equal to 11, K2 is equal to 70, the CRC generator polynomial is D^11+D^5+D^3+D+1, and the elements in the first distributed CRC interleaver are

[0032] In a possible implementation, performing cyclic redundancy check (CRC) encoding on the K1 information bits to obtain a first bit sequence includes: performing CRC encoding on the K1 information bits based on a CRC generator polynomial to obtain the first bit sequence, wherein L is equal to 11, K2 is equal to 70, the CRC generator polynomial is D^11+D^10+D^9+D^8+D^6+D^5+D^3+D+1, and the first distributed

[0033] In a possible implementation, performing cyclic redundancy check (CRC) encoding on the K1 information bits to obtain the first bit sequence includes: performing CRC encoding on the K1 information bits based on a CRC generator polynomial to obtain the first bit sequence, wherein L is equal to 11, K2 is equal to 70, the CRC generator polynomial is D^11+D^10+D^8+D^7+D^6+D^5+D^3+D+1, and the first distributed

[0034] In a possible implementation, performing cyclic redundancy check (CRC) encoding on the K1 information bits to obtain the first bit sequence includes: performing CRC encoding on the K1 information bits based on a CRC generator polynomial to obtain the first bit sequence, where L is equal to 11, K2 is equal to 70, the CRC generator polynomial is D^11+D^9+D^7+D^6+D^5+D^4+D^3+D+1, and the first distributed CRC

[0035] In a possible implementation, performing cyclic redundancy check (CRC) encoding on the K1 information bits to obtain a first bit sequence includes: performing CRC encoding on the K1 information bits based on a CRC generator polynomial to obtain the first bit sequence, wherein L is equal to 11, K2 is equal to 70, the CRC generator polynomial is D^11+D^10+D^9+D^7+D^6+D^3+D^2+D+1, and the first distributed

[0036] In a possible implementation, performing cyclic redundancy check (CRC) encoding on the K1 information bits to obtain the first bit sequence includes: performing CRC encoding on the K1 information bits based on a CRC generator polynomial to obtain the first bit sequence, where L is equal to 11, K2 is equal to 70, the CRC generator polynomial is D^11+D^8+D^6+D^5+D^4+D^3+D^2+D+1, and the first distributed CRC

[0037] In a possible implementation, performing cyclic redundancy check (CRC) encoding on the K1 information bits to obtain a first bit sequence includes: performing CRC encoding on the K1 information bits based on a CRC generator polynomial to obtain the first bit sequence, wherein L is equal to 16, K2 is equal to 100, the CRC generator polynomial is D^16+D^12+D^5+1, and the elements in the first distributed CRC interleaver are

[0038] In a possible implementation, performing cyclic redundancy check (CRC) encoding on the K1 information bits to obtain the first bit sequence includes: performing CRC encoding on the K1 information bits based on a CRC generator polynomial to obtain the first bit sequence, wherein L is equal to 6, K2 is equal to 70, the CRC generator polynomial is D^6+D^5+1, and the values ​​of the elements in the first distributed CRC interleaver are sequentially

[0039] In a possible implementation, performing cyclic redundancy check (CRC) encoding on the K1 information bits to obtain the first bit sequence includes: performing CRC encoding on the K1 information bits based on a CRC generator polynomial to obtain the first bit sequence, wherein L is equal to 11, K2 is equal to 70, the CRC generator polynomial is D^11+D^10+D^9+D^5+1, and the elements in the first distributed CRC interleaver are:

[0040] In a second aspect, an embodiment of the present application provides a decoding method, the method comprising: obtaining a sequence to be decoded; verifying the sequence to be decoded based on a first CRC generating polynomial, the sequence to be decoded being obtained based on a second bit sequence obtained by interleaving a first bit sequence, the first bit sequence comprising K1 information bits and L CRC bits, K1 being a positive integer, and L being a positive integer less than 24; when the sequence to be decoded passes the verification, deinterleaving the second bit sequence using a first distributed CRC deinterleaver to obtain the K1 information bits; wherein the first distributed CRC deinterleaver corresponds to the first distributed interleaver, the first distributed CRC interleaver comprising (K2+L) elements, the values ​​of the (K2+LS)th element to the (K2+L)th element of the first distributed CRC interleaver being (K2+L-1-S) to (K2+L-1) respectively, S being an integer greater than or equal to 0 and less than or equal to L, and K2 being an integer greater than or equal to K1.

[0041] In the embodiment of the present application, if the sequence to be decoded passes the check, the first distributed CRC deinterleaver is used to deinterleave the second bit sequence to obtain K1 information bits. The first distributed CRC deinterleaver supports DCRC encoding of shorter payloads, which can reduce decoding power consumption and resource overhead.

[0042] In a possible implementation, the first distributed CRC interleaver is obtained by arranging L element sequences in sequence, any two element sequences among the L element sequences are a first element sequence and a second element sequence, the elements included in the first element sequence are obtained based on the positions of information bits associated with the first check column, and the elements included in the second element sequence are obtained based on the positions of information bits associated with the second check column, the first check column and the second check column are any two columns in a check matrix obtained based on an L-length CRC generator polynomial, and when the maximum element in the first element sequence representing the position of the information bit associated with the first check column is greater than the maximum element in the second element sequence representing the position of the information bit associated with the second check column, the first element sequence in the first distributed CRC interleaver is sorted after the second element sequence.

[0043] For various possible implementations of the second aspect, reference may be made to various possible implementations of the first aspect.

[0044] For the technical effects brought about by various possible implementations of the second aspect, reference may be made to the introduction to the technical effects of various possible implementations of the first aspect.

[0045] In a third aspect, an embodiment of the present application provides a communication device having the function of implementing the behavior in the method embodiment of the first aspect above. The communication device can be a network device, or a component of a network device (such as a processor, a chip, or a chip system, etc.), or a logic module or software that can implement all or part of the functions of the network device. Alternatively, the communication device can be a terminal device, or a component of a terminal device (such as a processor, a chip, or a chip system, etc.), or a logic module or software that can implement all or part of the functions of the terminal device. The functions of the communication device can be implemented by hardware, or by hardware executing corresponding software implementations, and the hardware or software includes one or more modules or units corresponding to the above functions. In one possible implementation, the communication device includes a processing module, wherein: the processing module is configured to perform cyclic redundancy check (CRC) encoding on K1 information bits to obtain a first bit sequence, the first bit sequence including the K1 information bits and L CRC bits, K1 is a positive integer, and L is a positive integer less than 24; use a first distributed CRC interleaver to interleave the first bit sequence to obtain a second bit sequence; wherein the first distributed CRC interleaver includes (K2+L) elements, and the values ​​of the (K2+LS)th element to the (K2+L)th element of the first distributed CRC interleaver are (K2+L-1-S) to (K2+L-1) respectively, S is an integer greater than or equal to 0 and less than or equal to L, and K2 is an integer greater than or equal to K1; or, the first distributed CRC interleaver includes a total of (K2+L) natural numbers from 0 to (K2+L-1), P in the first distributed CRC interleaver precedes Q, P and Q are both integers greater than or equal to K2, and P is greater than Q. Optionally, the communication device further includes a transceiver module, configured to send a signal carrying a sequence to be decoded obtained based on the second bit sequence.

[0046] For possible implementations of the communication device of the third aspect, reference may be made to various possible implementations of the first aspect.

[0047] For the technical effects brought about by various possible implementations of the third aspect, reference may be made to the introduction to the technical effects of various possible implementations of the first aspect.

[0048] In a fourth aspect, an embodiment of the present application provides a communication device having the function of implementing the behavior in the method embodiment of the second aspect above. The communication device can be a network device, or a component of a network device (such as a processor, a chip, or a chip system, etc.), or a logic module or software that can implement all or part of the functions of the network device. Alternatively, the communication device can be a terminal device, or a component of a terminal device (such as a processor, a chip, or a chip system, etc.), or a logic module or software that can implement all or part of the functions of the terminal device. The functions of the communication device can be implemented by hardware, or by hardware executing corresponding software implementations, and the hardware or software includes one or more modules or units corresponding to the above functions. In one possible implementation, the communication device includes a processing module, wherein: the processing module is used to obtain a sequence to be decoded; verify the sequence to be decoded based on a first CRC generator polynomial, the sequence to be decoded is obtained based on a second bit sequence obtained by interleaving a first bit sequence, the first bit sequence includes K1 information bits and L CRC bits, K1 is a positive integer, and L is a positive integer less than 24; if the sequence to be decoded passes the verification, use a first distributed CRC deinterleaver to deinterleave the second bit sequence to obtain the K1 information bits; wherein the first distributed CRC deinterleaver corresponds to the first distributed interleaver, the first distributed CRC interleaver includes (K2+L) elements, and the values ​​of the (K2+LS)th element to the (K2+L)th element of the first distributed CRC interleaver are (K2+L-1-S) to (K2+L-1) respectively, S is an integer greater than or equal to 0 and less than or equal to L, and K2 is an integer greater than or equal to K1. Optionally, the communication device further includes a transceiver module, and the transceiver module is used to carry the signal of the sequence to be decoded.

[0049] Possible implementations of the communication device of the fourth aspect may refer to the various possible implementations of the second aspect.

[0050] For the technical effects brought about by various possible implementation methods of the fourth aspect, reference may be made to the introduction to the technical effects of various possible implementation methods of the second aspect.

[0051] In a fifth aspect, an embodiment of the present application provides another communication device, which includes one or more processors, and the one or more processors are used to process data or signaling so that the method of any one of the first aspect to the second aspect mentioned above is implemented.

[0052] Optionally, the communication device further includes a memory storing a program or instruction. When the program or instruction is executed by the processor, the communication device performs the method described in the first or second aspect. Exemplarily, the communication device may be a chip, the processor may be a processing circuit in the chip, and the memory may be a random access memory or cache in the chip.

[0053] In one possible implementation, during the execution of the above method, the process of sending information (or signals) in the above method can be understood as the process of outputting information based on instructions from the processor. When outputting information, the processor outputs the information to the transceiver for transmission by the transceiver. After being output by the processor, the information may undergo further processing before reaching the transceiver. Similarly, when the processor receives input information, the transceiver receives the information and inputs it into the processor. Furthermore, after receiving the information, the transceiver may undergo further processing before inputting it into the processor.

[0054] For operations such as sending and / or receiving involved in the processor, unless otherwise specified, or unless they conflict with their actual functions or internal logic in the relevant descriptions, they can be generally understood as instructions output based on the processor.

[0055] During implementation, the processor may be a processor specifically configured to execute these methods, or may be a processor that executes computer instructions in a memory to execute these methods, such as a general-purpose processor. For example, the processor may also be configured to execute a program stored in a memory. When the program is executed, the communication device performs the method described in the first aspect or any possible implementation of the first aspect.

[0056] In a possible implementation, the memory is located outside the communication device. In a possible implementation, the memory is located inside the communication device.

[0057] In a possible implementation, the processor and the memory may also be integrated into one device, that is, the processor and the memory may also be integrated together.

[0058] In a possible implementation, the communication device further includes a transceiver, and the transceiver is configured to receive signals or send signals.

[0059] In a sixth aspect, the present application provides another communication device, which includes a processing circuit and an interface circuit, wherein the interface circuit is used to acquire data or output data; the processing circuit is used to execute the method shown in any one of the first to second aspects above.

[0060] In the seventh aspect, the present application provides a computer-readable storage medium, which stores a computer program, and the computer program includes program instructions, which, when executed, enable the computer to execute the method shown in any one of the above-mentioned first to second aspects.

[0061] In an eighth aspect, the present application provides a computer program product, which includes a computer program, and the computer program includes program instructions, which, when executed, enable the computer to execute the method shown in any one of the above-mentioned first to second aspects.

[0062] In a ninth aspect, the present application provides a chip comprising a communication interface and a processor; the communication interface is used for transmitting and receiving signals of the chip; the processor is used for executing computer program instructions so that a communication device comprising the chip executes a method as described in any one of the first to second aspects above.

[0063] In the tenth aspect, an embodiment of the present application provides a communication system, comprising the communication device described in the third aspect or any possible implementation of the third aspect, and the communication device described in the fourth aspect or any possible implementation of the fourth aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0064] Figure 1 shows a schematic diagram of the working principle of the downlink low-power wake-up signal of a low-power device;

[0065] FIG2 is a schematic diagram of the architecture of a communication system to which an embodiment of the present application may be applied;

[0066] FIG3 is a flow chart of a communication system;

[0067] FIG4 is a flow chart of an encoding method provided in an embodiment of the present application;

[0068] FIG5 is a flow chart of another encoding method provided in an embodiment of the present application;

[0069] FIG6 is an example of a DCRC encoding matrix corresponding to a first distributed CRC interleaver provided in an embodiment of the present application;

[0070] FIG7 is an example of a DCRC encoding matrix corresponding to another first distributed CRC interleaver provided in an embodiment of the present application;

[0071] FIG8 is an example of a DCRC encoding matrix corresponding to another first distributed CRC interleaver provided in an embodiment of the present application;

[0072] FIG9 is an example of a DCRC encoding matrix corresponding to another first distributed CRC interleaver provided in an embodiment of the present application;

[0073] FIG10 is an example of a DCRC encoding matrix corresponding to another first distributed CRC interleaver provided in an embodiment of the present application;

[0074] FIG11 is an example of a DCRC encoding matrix corresponding to another first distributed CRC interleaver provided in an embodiment of the present application;

[0075] FIG12 is an example of a DCRC encoding matrix corresponding to another first distributed CRC interleaver provided in an embodiment of the present application;

[0076] FIG13 is an example of a DCRC encoding matrix corresponding to another first distributed CRC interleaver provided in an embodiment of the present application;

[0077] FIG14 is an example of a DCRC encoding matrix corresponding to another first distributed CRC interleaver provided in an embodiment of the present application;

[0078] FIG15 is an example of a DCRC encoding matrix corresponding to another first distributed CRC interleaver provided in an embodiment of the present application;

[0079] FIG16 is an example of a DCRC encoding matrix corresponding to another first distributed CRC interleaver provided in an embodiment of the present application;

[0080] FIG17 is an example of a DCRC encoding matrix corresponding to another first distributed CRC interleaver provided in an embodiment of the present application;

[0081] FIG18 is an example of a DCRC encoding matrix corresponding to another first distributed CRC interleaver provided in an embodiment of the present application;

[0082] FIG19 is an example of a DCRC encoding matrix corresponding to another first distributed CRC interleaver provided in an embodiment of the present application;

[0083] FIG20 is an example of a DCRC encoding matrix corresponding to another first distributed CRC interleaver provided in an embodiment of the present application;

[0084] FIG21 is an example of a DCRC encoding matrix corresponding to another first distributed CRC interleaver provided in an embodiment of the present application;

[0085] FIG22 is an example of a DCRC encoding matrix corresponding to another first distributed CRC interleaver provided in an embodiment of the present application;

[0086] FIG23 is an example of a DCRC encoding matrix corresponding to another first distributed CRC interleaver provided in an embodiment of the present application;

[0087] FIG24 is an example of a DCRC encoding matrix corresponding to another first distributed CRC interleaver provided in an embodiment of the present application;

[0088] FIG25 is an example of a DCRC encoding matrix corresponding to another first distributed CRC interleaver provided in an embodiment of the present application;

[0089] FIG26 is an example of a DCRC encoding matrix corresponding to another first distributed CRC interleaver provided in an embodiment of the present application;

[0090] FIG27 is an example of a DCRC encoding matrix corresponding to another first distributed CRC interleaver provided in an embodiment of the present application;

[0091] FIG28 is an example of a DCRC encoding matrix corresponding to another first distributed CRC interleaver provided in an embodiment of the present application;

[0092] FIG29 is an example of a DCRC encoding matrix corresponding to another first distributed CRC interleaver provided in an embodiment of the present application;

[0093] FIG30 is an example of a DCRC encoding matrix corresponding to another first distributed CRC interleaver provided in an embodiment of the present application;

[0094] FIG31 is an example of a DCRC encoding matrix corresponding to another first distributed CRC interleaver provided in an embodiment of the present application;

[0095] FIG32 is an example of a DCRC encoding matrix corresponding to another first distributed CRC interleaver provided in an embodiment of the present application;

[0096] FIG33 is a flow chart of another encoding method provided in an embodiment of the present application;

[0097] FIG34 is a flow chart of another encoding method provided in an embodiment of the present application;

[0098] FIG35 is a schematic structural diagram of a communication device 3500 provided in an embodiment of the present application;

[0099] FIG36 is a schematic structural diagram of another device 360 ​​provided in an embodiment of the present application. DETAILED DESCRIPTION

[0100] The terms "first" and "second" in the specification, claims and drawings of the present application are only used to distinguish different objects, rather than to describe a specific order. It will be understood that the various digital numbers involved in the embodiments of the present application are only for the convenience of description and are not used to limit the scope of the embodiments of the present application. The size of the sequence number of each of the above processes does not mean the order of execution, and the order of execution of each process should be determined by its function and inherent logic. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but optionally also includes steps or units that are not listed, or optionally also includes other steps or units inherent to these processes, methods, products or devices.

[0101] The "embodiment" mentioned in this document means that the specific features, structures or characteristics described in conjunction with the embodiment may be included in at least one embodiment of the present application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It can be understood explicitly and implicitly by those skilled in the art that the embodiments described herein can be combined with other embodiments. In this application, the naming of messages is only used to distinguish different messages and should not be understood as a limitation. In other words, the name of any message in this application can be replaced with other names, and this application is not limited.

[0102] The terms used in the following embodiments of the present application are only for the purpose of describing specific embodiments and are not intended to limit the present application. As used in the specification of the present application and the appended claims, the singular expressions "one", "a kind of", "said", "above", "the" and "this" are intended to also include plural expressions, unless there is a clear contrary indication in the context. It should also be understood that the term "and / or" used in the present application refers to and includes any or all possible combinations of one or more listed items. For example, "A and / or B" can mean: only A exists, only B exists, and A and B exist at the same time, where A and B can be singular or plural. The term "multiple" used in the present application refers to two or more. In the textual description of the present application, the character " / " generally indicates that the objects associated before and after are in an "or" relationship.

[0103] It is understood that in each embodiment of the present application, "A corresponds to B" means that there is a corresponding relationship between A and B, and B can be determined according to A. However, it should also be understood that determining (or generating) B according to (or based on) A does not mean that B is determined (or generated) only according to (or based on) A, and B can also be determined (or generated) according to (or based on) A and / or other information.

[0104] It should be understood that, in this application, indication includes direct indication (also known as explicit indication) and implicit indication. Direct indication of information A refers to including information A; implicit indication of information A refers to indicating information A through the correspondence between information A and information B and the direct indication of information B. The correspondence between information A and information B can be predefined, pre-stored, pre-burned, or pre-configured.

[0105] It should be understood that, in this application, information C is used to determine information D, which includes both information D being determined solely based on information C and information D being determined based on information C and other information. Furthermore, information C can also be used to determine information D indirectly, for example, where information D is determined based on information E, and information E is determined based on information C.

[0106] In addition, in each embodiment of the present application, "network element A sends information A to network element B" can be understood as the destination end of the information A or the intermediate network element in the transmission path between the destination end and the network element B, which may include directly or indirectly sending information to network element B. "Network element B receives information A from network element A" can be understood as the source end of the information A or the intermediate network element in the transmission path between the source end and the network element A, which may include directly or indirectly receiving information from network element A. The information may be processed as necessary between the source end and the destination end of the information transmission, such as format changes, but the destination end can understand the valid information from the source end. Similar expressions in this application can be understood similarly and will not be elaborated here.

[0107] To facilitate understanding of the solutions of the present application, the following first introduces the terms and technical solutions involved in the embodiments of the present application.

[0108] Low-power wakeup signal (LP-WUS): If the user equipment (UE)'s main receiver is turned off or placed in a deep sleep state before being awakened, the UE's power consumption can be significantly reduced. UE awakening can be achieved by using a wakeup signal to trigger a low-power wakeup receiver with low-power monitoring capabilities. Figure 1 illustrates the working principle of a downlink low-power wakeup signal for a low-power device. As shown in Figure 1, the UE is equipped with a main receiver and a low-power wakeup receiver, each with independent radio frequency (RF) circuitry and antennas. The main receiver is used for data transmission and reception. If not awakened by the wakeup signal, it is turned off or placed in a deep sleep state. The low-power wakeup receiver serves as a supplementary chip to power up and down the main receiver. This low-power wakeup receiver receives the LP-WUS via a separate antenna, potentially allowing the main receiver to enter an ultra-deep sleep state when there is limited or no traffic activity. The UE wakes up the main receiver after detecting the LP-WUS via the low-power wakeup receiver. Exemplarily, before sending data to the UE, the base station may first send an LP-WUS to the UE; when the main receiver of the UE is awakened, a new radio (NR) signal is sent to the UE to transmit data.

[0109] Cyclic Redundancy Check (CRC): Cyclic redundancy check (CRC) is widely used in serial transmission (disks, communications). CRC also adds several check bits (check bits) to the information code (i.e., information bits) to increase the code length and error detection and correction capabilities of the entire coding system. The basic principle of CRC is: K bits of information code are followed by R bits of check bits, resulting in an N-bit code length. Therefore, this type of code is also called an (N, K) code. For a given (N, K) code, it can be proven that a polynomial G(x) with a maximum power of NK = R exists. Based on G(x), a check code for the K-bit information code can be generated. G(x) is called the CRC generator polynomial (or simply the generator polynomial). The specific process for generating the check code is as follows: Assuming that the transmitted information is represented by the information polynomial C(x), shifting C(x) left by R bits can be expressed as C(x) * 2R. This leaves R bits to the right of C(x), which is where the check code is located. The remainder obtained by dividing C(x)*2 by the CRC generator polynomial G(x) is the checksum. The CRC generator polynomial is a binary number agreed upon between the receiver (or receiving end) and the sender (or transmitting end). It remains unchanged throughout the transmission process. At the sender, the CRC generator polynomial is used to perform a modulo-2 division on the message polynomial to generate the checksum. At the receiver, the CRC generator polynomial is used to perform a modulo-2 division on the received coded polynomial to detect and locate errors. The CRC generator polynomial must meet the following conditions: a) The highest and lowest bits of the CRC generator polynomial must be 1; b) If any bit in the transmitted information (CRC code) is incorrect, the modulo-2 division of the generator polynomial must leave a non-zero remainder.

[0110] The following describes a communication system to which the technical solution provided by this application is applicable.

[0111] The technical solution provided in this application can be applied to various communication systems, such as: narrowband Internet of Things (NB-IoT) system, global system for mobile communications (GSM), enhanced data rate for GSM evolution (EDGE), fifth generation (5G) or new radio (NR) system, long term evolution (LTE) system, LTE frequency division duplex (FDD) system, wireless local area network (WLAN) system, satellite communication system, future communication system, such as sixth generation (6G) mobile communication system, or a fusion system of multiple systems. The technical solution provided in this application can also be applied to device-to-device (D2D) communication, vehicle-to-everything (V2X) communication, machine-to-machine (M2M) communication, machine type communication (MTC), and Internet of Things (IoT) communication systems or other communication systems. The technical solution provided in the embodiment of this application is also applicable to other communication systems involving channel coding. The above-mentioned communication system to which the technical solution provided in the embodiment of this application is applicable is only an example, and the communication system to which the technical solution provided in this application is applicable is not limited thereto. They are uniformly described here and will not be repeated below.

[0112] A first device in a communication system can send a signal to a second device or receive a signal from a third device. The signal may include information, signaling, or data, etc. The device may also be replaced by an entity, a network entity, a communication device, a communication module, a node, a communication node, etc. The present disclosure uses a network element as an example for description. The first device may be a network device or a terminal device, the second device may be a network device or a terminal device, and the third device may be a network device or a terminal device. For example, the communication system may include at least one terminal device and at least one network device. The network device may send a downlink signal to the terminal device, and / or the terminal device may send an uplink signal to the network device. It is understandable that the terminal device in the present disclosure may be replaced by the first device, and the network device may be replaced by the second device, and both perform the corresponding communication method in the present disclosure.

[0113] Figure 2 is a schematic diagram of the architecture of a communication system to which an embodiment of the present application can be applied. As shown in Figure 2, the communication system includes a network device 110, a terminal device 120, and a terminal device 130. The communication system to which an embodiment of the present application can be applied includes one or more terminal devices, with terminal device 120 and terminal device 130 being examples of terminal devices in the communication system. Figure 2 is only a schematic diagram, and the embodiment of the present application does not limit the number of network devices and terminal devices included in the communication system. Terminal device 120 and terminal device 130 can access network device 110 and communicate with network device 110. The technical solution provided in the present application is applicable to low-power consumption scenarios, for example, the terminal device in Figure 2 is a low-power consumption device.

[0114] In an embodiment of the present application, the terminal device may also be referred to as user equipment (UE), access terminal, user unit, user station, mobile station, mobile station, remote station, remote terminal, mobile device, user terminal, terminal, wireless communication device, user agent or user device.

[0115] The terminal device may be a device that provides voice / data, such as a handheld device or vehicle-mounted device with a wireless connection function. At present, some examples of terminals are: mobile phones, tablet computers, laptop computers, PDAs, mobile internet devices (MIDs), wearable devices, virtual reality (VR) devices, augmented reality (AR) devices, wireless terminals in industrial control, wireless terminals in self-driving, wireless terminals in remote medical surgery, wireless terminals in smart grids, wireless terminals in transportation safety, wireless terminals in smart cities, wireless terminals in smart homes, cellular phones, cordless phones, session initiation protocol (SIP) phones, wireless local loop (WLL) stations, personal digital assistants (PDAs), handheld devices with wireless communication capabilities, computing devices or other processing devices connected to wireless modems, wearable devices, terminal devices in 5G networks or future evolved public land mobile communication networks (PLMNs). The terminal equipment in the network (PLMN), etc., is not limited to this in the embodiments of the present application.

[0116] As an example and not a limitation, in the embodiment of the present application, the terminal device may also be a wearable device. Wearable devices may also be called wearable smart devices, which are a general term for wearable devices that are intelligently designed and developed using wearable technology for daily wear, such as glasses, gloves, watches, clothing, and shoes. A wearable device is a portable device that is worn directly on the body or integrated into the user's clothes or accessories. Wearable devices are not only hardware devices, but also achieve powerful functions through software support, data interaction, and cloud interaction. Broadly speaking, wearable smart devices include those that are fully functional, large in size, and can achieve complete or partial functions without relying on smartphones, such as smart watches or smart glasses, as well as those that only focus on a certain type of application function and need to be used in conjunction with other devices such as smartphones, such as various smart bracelets and smart jewelry for vital sign monitoring.

[0117] In the embodiments of the present application, the device for realizing the function of the terminal device can be a terminal device, or a device capable of supporting the terminal device to realize the function, such as a chip system, which can be installed in the terminal device or used in combination with the terminal device. In the embodiments of the present application, the chip system can be composed of a chip, or it can include a chip and other discrete devices. In the embodiments of the present application, only the terminal device is used as an example for description, and the embodiments of the present application are not limited to the solutions of the embodiments of the present application.

[0118] The network device in the embodiments of the present application may be a device for communicating with a terminal device, and may also be referred to as an access network device or a radio access network device. For example, the network device may be a base station. The network device in the embodiments of the present application may refer to a radio access network (RAN) node (or device) that connects a terminal device to a wireless network. A base station may broadly cover various names as follows, or replace the following names, such as: RAN node, NodeB, evolved NodeB (eNB), next generation NodeB (gNB), relay station, access point, transmitting and receiving point (TRP), transmitting point (TP), master station, secondary station, multi-standard radio (motor slide retainer, MSR) node, home base station, network controller, access node, wireless node, access point (AP), transmission node, transceiver node, baseband unit (BBU), remote radio unit (RRU), active antenna unit (AAU), remote radio head (RRH), central unit (CU), distributed unit (DU), radio unit (RU), positioning node, etc. A base station may be a macro base station, a micro base station, a relay node, a donor node, or the like, or a combination thereof. The base station may also refer to a communication module, modem or chip used to be set in the aforementioned equipment or device. The base station may also be a mobile switching center and a device that performs the base station function in D2D, V2X, and M2M communications, a network side device in a 6G network, a device that performs the base station function in future communication systems, etc. The base station can support networks with the same or different access technologies. Optionally, the RAN node may also be a server, a wearable device, a vehicle or an on-board device, etc. For example, the access network device in the vehicle to everything (V2X) technology may be a road side unit (RSU). The embodiments of the present application do not limit the specific technology and specific device form adopted by the network device. The base station may be fixed or mobile. For example, a helicopter or a drone may be configured to act as a mobile base station, and one or more cells may move according to the location of the mobile base station. In other examples, a helicopter or a drone may be configured to be used as a device for communicating with another base station.

[0119] In some deployments, the network devices mentioned in the embodiments of the present application may include a CU, a DU, or both a CU and a DU, or a control plane CU node (central unit-control plane (CU-CP)), a user plane CU node (central unit-user plane (CU-UP)), and a DU node. For example, the network devices may include a gNB-CU-CP, a gNB-CU-UP, and a gNB-DU.

[0120] In some deployments, multiple RAN nodes collaborate to assist terminals in achieving wireless access, with different RAN nodes implementing portions of the base station's functionality. For example, a RAN node can be a CU, DU, CU-CP, CU-UP, or RU. The CU and DU can be separate or included in the same network element, such as the BBU. The RU can be included in a radio frequency device or radio unit, such as an RRU, AAU, or RRH.

[0121] In the embodiments of the present application, the device for implementing the functions of the network device can be a network device; it can also be a device that can support the network device to implement the functions, such as a chip system, a hardware circuit, a software module, or a hardware circuit and a software module. The device can be installed in the network device or used in conjunction with the network device. In the embodiments of the present application, only the device for implementing the functions of the network device is used as an example to illustrate, and does not constitute a limitation on the solutions of the embodiments of the present application.

[0122] It should be noted that the network architecture described in the embodiments of this application is intended to more clearly illustrate the technical solutions of the embodiments of this application and does not constitute a limitation on the technical solutions provided in the embodiments of this application. Those skilled in the art will appreciate that, with the evolution of network architecture and the emergence of new business scenarios, the technical solutions provided in the embodiments of this application are equally applicable to similar technical problems.

[0123] FIG3 is a flow chart of a communication system. As shown in FIG3 , at the transmitting end, the information source undergoes source coding, channel coding, rate matching (optional step), and modulation in sequence before being sent out. At the receiving end, it is output to the destination through demodulation, rate matching (optional step), channel decoding, and source decoding in sequence. The embodiments of the present application mainly relate to channel coding and channel decoding (referred to as channel coding and decoding for short), wherein the channel coding part is located between the information source coding and modulation, and is responsible for channel coding the bits generated by the information source, and the channel decoding part is located between the demodulation and the information source decoding, and is responsible for recovering the information source bit stream.

[0124] In the low-power scenario to which the technical solution provided by the present application is applied, the channel coding method involved in the low-power device (such as a terminal device) may be only one, that is, the data channel and the control channel adopt the same coding strategy. The main principle of the technical solution provided by the present application is: the channel coding adopts a distributed CRC interleaver (hereinafter referred to as a DCRC interleaver) that supports a smaller payload and a shorter CRC length; in order to meet the energy efficiency, coverage and false alarm rate (FAR) requirements of low-power devices. In one possible implementation, both the data channel and the control channel adopt the channel coding method proposed by the present application. In one possible implementation, LP-WUS also adopts the above-mentioned channel coding method. For example, when the number of payload bits to be sent by the transmitter is reduced, a 24-bit CRC is not required, so the DCRC interleaver must also be shortened and redesigned accordingly. The CRC length can be 6, 11, 16 or other values, which are not limited by the present application. The size of the payload can be less than or equal to 70.

[0125] The following first introduces the technical solution provided by this application in conjunction with Figure 4. Figure 4 is a flow chart of an encoding method provided by an embodiment of this application. As shown in Figure 4, the method includes:

[0126] 401. The transmitting end performs CRC encoding on K1 information bits to obtain a first bit sequence.

[0127] In one possible implementation, the transmitting end is a network device, and the receiving end is a terminal device. In one possible implementation, the transmitting end is a terminal device, and the receiving end is a network device. The first bit sequence includes the K1 information bits and L CRC bits, where K1 is a positive integer and L is a positive integer less than 24. Exemplarily, the K1 information bits may be obtained by the transmitting end performing source coding on multiple bits to be transmitted, and the K1 information bits are the bits to be channel coded.

[0128] In a possible implementation, L is equal to 6, 11, or 16. L may also be another integer less than 24, which is not limited in this application.

[0129] In a possible implementation, K1 is equal to 32, 40, 48, 54, 64, 70, or 100. K1 may also be other integers less than 140, which is not limited in this application.

[0130] 402. The transmitting end uses a first distributed CRC interleaver to interleave the first bit sequence to obtain a second bit sequence.

[0131] The first distributed CRC interleaver includes (K2+L) elements, and the values ​​of the (K2+LS)th element to the (K2+L)th element of the first distributed CRC interleaver are (K2+L-1-S) to (K2+L-1), respectively, where S is an integer greater than or equal to 0 and less than or equal to L, and K2 is an integer greater than or equal to K1. (K2+L) is less than 164. Alternatively, the first distributed CRC interleaver includes (K2+L) natural numbers from 0 to (K2+L-1), P in the first distributed CRC interleaver precedes Q, P and Q are both integers greater than or equal to K2, and P is greater than Q. Alternatively, the first distributed CRC interleaver includes (K2+L) natural numbers from 1 to (K2+L), P in the first distributed CRC interleaver precedes Q, P and Q are both integers greater than or equal to K2, and P is greater than Q. For example, K2 is 70, P is 75, and Q is 72. In this article, the elements in the DCRC interleaver can start from 0, that is, 0 represents the first position, and the elements in the DCRC interleaver can also start from 1, that is, 1 represents the first position, and there is no restriction here.

[0132] In one possible implementation, K2 is equal to 70 or 100. K2 can also be other integers less than 140 and greater than or equal to K1, which is not limited in this application. Exemplarily, K2 is equal to 70, L=6, S=0, and the 76th element (i.e., the last element) of the first distributed CRC interleaver is 75; wherein, the 75th element of the first distributed CRC interleaver may not be 74. Exemplarily, K2 is equal to 70, L=11, S=1, the 80th element (i.e., the last element) of the first distributed CRC interleaver is 79, and the 81st element is 80; wherein, the 79th element of the first distributed CRC interleaver may not be 78, or, the 78th element of the first distributed CRC interleaver may not be 77, or, the 77th element of the first distributed CRC interleaver may not be 76.

[0133] In a possible implementation, the first distributed CRC interleaver is obtained by arranging L element sequences in sequence, any two element sequences among the L element sequences are the first element sequence and the second element sequence, the elements included in the first element sequence are obtained based on the positions of the information bits associated with the first check column, and the elements included in the second element sequence are obtained based on the positions of the information bits associated with the second check column, the first check column and the second check column are any two columns in a check matrix obtained based on an L-length CRC generator polynomial, and when the maximum element in the first element sequence representing the position of the information bit associated with the first check column is greater than the maximum element in the second element sequence representing the position of the information bit associated with the second check column, the first element sequence in the first distributed CRC interleaver is sorted after the second element sequence. Exemplarily, the second element sequence is [2 3 40 72], where the second element sequence represents the first check column (i.e., the 73rd column of the check matrix is ​​associated with the 2nd, 3rd, and 40th information bits); and the first element sequence is [1 60 71], where the first element sequence represents the second check column (i.e., the 72nd column of the check matrix is ​​associated with the 1st and 60th information bits). In this implementation, when the maximum element in the first element sequence representing the position of the information bit associated with the first check column is greater than the maximum element in the second element sequence representing the position of the information bit associated with the second check column, the first element sequence in the first distributed CRC interleaver is sorted after the second element sequence, so that the receiving end can detect CRC check failure earlier during decoding, thereby saving decoding power consumption.

[0134] An example of obtaining the first distributed CRC interleaver based on a CRC generator polynomial of length L is as follows: the transmitting end obtains the position of the information bit associated with each column of the check matrix generated by the CRC generator polynomial of length L, wherein a CRC generator polynomial gL of length L is given, such as gL=D^6+D^5+1, and the CRC generator polynomial corresponds to a matrix Gcrc of K rows and (K+L) columns, wherein the first K rows and K columns of Gcrc are a unit matrix, and the last K rows and L columns of Gcrc are C The check matrix generated by the RC generator polynomial is used to generate L-bit CRC check bits, K is equal to 70, L is equal to 6, the first check column of the check matrix (the 71st column of the matrix Gcrc) is associated with the 023456713181923252829303133373839424547485051525455585961636566676869th information bit, the second check column of the check matrix (the 72nd column of the matrix Gcrc) is associated with the 1st 2 3 8142024263234404346495356606264 information bits, the third check column of the check matrix (the 73rd column of the matrix Gcrc) is associated with the 8th 9th 14th 15212735414457th information bits, the fourth check column of the check matrix (the 74th column of the matrix Gcrc) is associated with the 101622 27 36th information bits, the fifth check column of the check matrix (the 75th column of the matrix Gcrc) is associated with the 111728313965th information bits, and the sixth check column of the check matrix (the 76th column of the matrix Gcrc) is associated with the 5th 12th 25th 34 information bits; the transmitting end obtains element sequence #1 [023456713181923252829303133373839424547485051525455585961636566676869] based on the position of the information bits associated with the second parity column, obtains element sequence #2 [1 2 3 8142024263234404346495356606264] based on the position of the information bits associated with the third parity column, obtains element sequence #3 [8 9 14 15212735414457] based on the position of the information bits associated with the fourth parity column, and obtains element sequence #4 [101622 27 36], based on the position of the information bits associated with the fifth parity column, obtain the element sequence #5 [111728313965], and based on the position of the information bits associated with the sixth parity column, obtain the element sequence #6 [5 12 25 34];The sender arranges the elements in the sequence corresponding to each check column in ascending order according to the maximum value: [5 12 25 34], [101622 27 36], [8 9 14 15212735414457], [1 2 38142024263234404346495356606264], [111728313965], [023456713181923252829303133373839424547485051525455585961636566676869]; the sender packs [5 12 25 34] and the position of the sixth check column (i.e. 75) and places them in the first 5 positions; [101622 27 36] and the position (73) of the column where the fourth check column is located are packed as a whole and placed at the end of the first packing sequence; [8 9 14 15212735414457] and the position (72) of the column where the third check column is located are packed as a whole and placed at the end of the second packing sequence; [1 2 20242632404346495356606264] and the position (71) of the column where the second check column is located are packed as a whole and placed at the end of the third packing sequence. Note that the elements in the latter packing need to remove the elements that already exist in the previous packing; and so on, the final DCRC interleaver is obtained.

[0135] 403. The transmitting end performs polarization coding on the second bit sequence to obtain a third bit sequence.

[0136] The transmitting end may employ an existing polarization encoding method for polarization encoding the second bit sequence, which will not be described in detail here. Step 403 is optional. The transmitting end may employ other encoding methods for the second bit sequence, or may not encode the second bit sequence. It should be noted that this step is optional only when polarization encoding of the second bit sequence is required. If there is no such requirement, this step may be omitted in the actual encoding process. In this case, the third bit sequence in step 404 is the second bit sequence.

[0137] 404. The transmitting end performs some or all of the steps including but not limited to rate matching, modulation, analog-to-digital conversion, frequency conversion, etc. on the third bit sequence and then sends the obtained sequence to be decoded.

[0138] Accordingly, the receiving end receives the sequence to be decoded from the transmitting end. The sequence to be decoded received by the transmitting end may be a data signal carrying the sequence to be decoded sent via a data channel, and the K1 information bits may be data sent by the transmitting end to the receiving end; or a control signal carrying the sequence to be decoded sent via a control channel, and the K1 information bits may be control information sent by the transmitting end to the receiving end.

[0139] It should be noted that the rate matching step in step 404 is optional. If the encoded code length is the same as the target code length, rate matching is not required. Since the embodiment of the present application does not focus on step 404, it will not be described in detail here. For example, in a possible implementation, those skilled in the art can also refer to the practices in the prior art.

[0140] 405. The receiving end decodes the sequence to be decoded to obtain a sequence to be checked.

[0141] The receiving end may obtain the sequence to be decoded based on the signal carrying the sequence to be decoded from the transmitting end, which is not limited in this application. The sequence to be decoded is obtained based on polarization coding of the second bit sequence, and the sequence to be checked may be the second bit sequence.

[0142] 406. The receiving end performs CRC check on the sequence to be checked.

[0143] In one possible implementation, step 401 is: the transmitting end performs CRC encoding on K1 information bits based on the CRC generator polynomial to obtain a first bit sequence; step 406 is: the receiving end performs CRC check on the sequence to be checked based on the CRC generator polynomial.

[0144] 407. When the sequence to be checked passes the check, the receiving end uses the first distributed CRC deinterleaver to deinterleave the second bit sequence to obtain the K1 information bits.

[0145] When the sequence to be checked passes the check, the sequence to be checked is the second bit sequence. The above-mentioned first distributed CRC deinterleaver corresponds to the first distributed interleaver. In other words, the first distributed CRC deinterleaver is obtained based on the first distributed interleaver. Obtaining a deinterleaver corresponding to an interleaver based on an interleaver is a common technical means in this field. Here, an example is used to illustrate the relationship between the interleaver and the deinterleaver: if the interleaver is [2 4 1 3] (i.e., the second position is interleaved to the first position, the fourth position is interleaved to the second position, the first position is interleaved to the third position, and the third position is interleaved to the last position); then the corresponding deinterleaver is [3 1 4 2], that is, the third position in the interleaved sequence is swapped to the first position, the first position is placed in the second position, the fourth position is placed in the third position, and the second position is placed in the last position, so that the sequence before interleaving can be obtained.

[0146] In one possible implementation, if the sequence to be verified fails verification, the receiving end stops further parsing of the sequence to be verified, such as deinterleaving. Alternatively, if the sequence to be verified fails verification, decoding is terminated prematurely. Optionally, the receiving end sends information to the transmitting end indicating that the receiving end failed to correctly receive the sequence to be decoded.

[0147] In an embodiment of the present application, cyclic redundancy check (CRC) encoding is performed on K1 information bits to obtain a first bit sequence, wherein the number of CRC check bits is less than 24. The first bit sequence is interleaved using a first distributed CRC interleaver. The first distributed CRC deinterleaver supports DCRC encoding of shorter payloads, thereby reducing decoding power consumption and resource overhead.

[0148] FIG5 is a flow chart of another encoding method provided in an embodiment of the present application. The method flow in FIG5 is a possible implementation of the method described in FIG4. As shown in FIG5, the method includes:

[0149] 501. The transmitting end performs CRC encoding on K1 information bits based on a CRC generator polynomial to obtain a first bit sequence.

[0150] In one possible implementation, the transmitting end is a network device and the receiving end is a terminal device. In one possible implementation, the transmitting end is a terminal device and the receiving end is a network device. The above-mentioned first bit sequence includes the above-mentioned K1 information bits and L CRC bits, K1 is a positive integer, and L is a positive integer less than 24. Exemplarily, the K1 information bits can be obtained by the transmitting end after performing source encoding on multiple bits to be transmitted, and the K1 information bits are bits to be channel encoded. In one possible implementation, L is equal to 6, 11 or 16. L can also be other integers less than 24, which is not limited in this application. In one possible implementation, K1 is equal to 32, 40, 48, 54, 64, 70 or 100. K1 can also be other integers less than 140, which is not limited in this application.

[0151] Exemplarily, the CRC generator polynomial is any of the following:

[0152] D^6+D^5+1, or 43 (hex), where 43 (hex) is the hexadecimal representation of the CRC generator polynomial;

[0153] D^6+D^5+D^4+D^3+1, or 4F(hex), where 4F(hex) is the hexadecimal representation of the CRC generator polynomial;

[0154] D^6+D^4+D^3+D+1, or 6D(hex);

[0155] D^6+D^3+D^2+D+1, or 79(hex);

[0156] D^6+D^5+D^2+1, or 53 (hex);

[0157] D^6+D^5+D^4+D^2+1, or 57(hex);

[0158] D^6+D^3+D^2+1, or 59 (hex);

[0159] D^6+D^5+D^3+D^2+1, or 5B(hex);

[0160] D^6+D^5+D^4+D^3+D^2+1, or 5F(hex);

[0161] D^6+D^5+D^4+D^3+D+1, or 6F(hex);

[0162] D^6+D^4+D^2+D+1, or 75(hex);

[0163] D^11+D^10+D^9+D^5+1, or 847(hex);

[0164] D^11+D^7+D^6+D^2+1, or A31 (hex);

[0165] D^11+D^10+D^9+D^6+D^4+D^2+1, or AA7(hex);

[0166] D^11+D^10+D^9+D^7+D^5+D+1, or C57(hex);

[0167] D^11+D^9+D^8+D^6+D^5+D+1, or C6D(hex);

[0168] D^11+D^10+D^9+D^8+D^7+D^5+D^4+D+1, or CDF(hex);

[0169] D^11+D^10+D^3+D+1, or D03 (hex);

[0170] D^11+D^5+D^3+D+1, or D41 (hex);

[0171] D^11+D^10+D^9+D^8+D^6+D^5+D^3+D+1, or D6F(hex);

[0172] D^11+D^10+D^8+D^7+D^6+D^5+D^3+D+1, or D7B(hex);

[0173] D^11+D^9+D^7+D^6+D^5+D^4+D^3+D+1, or DF5(hex);

[0174] D^11+D^10+D^9+D^7+D^6+D^3+D^2+D+1, or F37(hex);

[0175] D^11+D^8+D^6+D^5+D^4+D^3+D^2+D+1, or FE9(hex);

[0176] D^16+D^12+D^5+1, or 10811(hex).

[0177] 502. The transmitting end uses a first distributed CRC interleaver to interleave the first bit sequence to obtain a second bit sequence.

[0178] Step 502 can refer to step 402 in Figure 4. The first distributed CRC interleaver can be obtained based on a CRC generator polynomial. An example of obtaining the first distributed CRC interleaver based on a CRC generator polynomial is as follows: first, calculate the corresponding check matrix (K rows and L columns, K=16, L=3 below) according to the L-length CRC generator polynomial, then look at the positions of the message bits associated with the first check column (i.e., the first column of the check matrix), pack these positions into a group and interleave them as a whole to the front (for example, the first check column is associated with the message bits [1 23 4 5 6 7 8], then [1 2 3 4 5 6 7 8] and the position K+1=17 of the first check column are placed in the first 9 positions). Similarly, the positions of the message bits associated with the second check column and the position of the second check column are packed as a whole and placed after the first packing sequence. For example, if the positions of the message bits associated with the second check column are [7 9 11 16], then [9 11 16] are placed at the end of the first packing sequence. The three message positions (16) and the second parity column position (K+2=16+2=18 bits) are packaged and placed after the first package. Note that the message bit 7 in the message position [7 9 11 16] associated with the second parity column is already in the first packet, so it needs to be removed in the second packet. Then, the message bit positions [5 8 10 11 12 13 14 15 16] associated with the third parity column are deduplicated from the existing message positions in the previous packet, and packaged together with the third parity column position (K+3=16+3=19) and placed after all previous packets. That is, the six bits [10 12 13 14 15 19] are placed after the second package, resulting in the final DCRC interleaver. Note that the DCRC interleaver and CRC generator polynomial have a message bit length of K, and the DCRC interleaver length is equal to (K+L). In the above example, distributed CRC encoding is supported for messages with K less than or equal to 16 (up to 16).

[0179] Given a CRC generating polynomial gL of length L, such as gL=D^6+D^5+1, the CRC generating polynomial corresponds to a matrix Gcrc with K rows and (K+L) columns, where the first K rows and K columns of Gcrc are a unit matrix, and the last K rows and L columns of Gcrc are a check matrix generated by the CRC generating polynomial, which is used to generate L-bit CRC check bits. The transmitting end uses the first distributed CRC interleaver to interleave the first bit sequence, and the obtained second bit sequence can be: after the first bit sequence (including K1 information bits+L CRC bits) is interleaved by the first distributed CRC interleaver, the second bit sequence (i.e., the interleaved CRC code sequence) is obtained. The DCRC code matrix GDcrc corresponding to the first distributed CRC interleaver can have the following two forms: one is an upper triangular form GDcrc1, that is, DCRC interleaving is performed on both K rows and (K+L) columns of Gcrc, wherein the interleaver used for interleaving the K rows is an interleaver composed of K elements with values ​​greater than or equal to (76-K) read from the DCRC interleaver in a natural order, and the interleaver used for interleaving the (K+L) columns is the DCRC interleaver with the above (K+L) length; the other form is also a matrix with K rows and (K+L) columns, but is not upper triangular, i.e., GDcrc2, which is generated by interleaving only the (K+L) columns of Gcrc and not interleaving the K rows of the matrix. If the K1 information bits are a = a0, a1, a2, ..., a69, that is, the payload bits are K1 = 70 bits, and the sequence a after DCRC encoding is a bit sequence b = b0, b1, b2, ..., b75 of length K + L = 70 + 6 = 76, then b = a·GDcrc1 or b = a·GDcrc2. GDcrc1 is the upper triangular matrix shown in Figure 6. Figure 6 is an example of a DCRC encoding matrix corresponding to a first distributed CRC interleaver provided in an embodiment of the present application.

[0180] GDcrc2 is a non-upper triangular matrix shown in Figure 7 below, that is, only the columns of Gcrc are interleaved. Figure 7 is an example of a DCRC coding matrix corresponding to another first distributed CRC interleaver provided in an embodiment of the present application. The advantage of GDcrc2 is that it is more convenient to nest and read the DCRC coding matrix. For payloads with K<70, it is only necessary to skip the first (70-K) rows of the matrix and use the inverse K rows of the matrix for DCRC coding. However, if GDcrc1 wants to support DCRC coding with K less than 70 bits, it takes two steps to read the submatrix of K rows (K+L) columns. The first step is to determine, based on the DCRC interleaver above (i.e., the first distributed CRC interleaver), the elements whose values ​​are greater than or equal to (70-K) (i.e., skipping elements less than (70-K)) to form a sequence of length K. The second step is to select the rows of the corresponding positions from GDcrc1 to form a DCRC coding matrix according to the sequence of length K obtained in the first step.

[0181] In one possible implementation, the transmitter multiplies the matrix corresponding to the K1 information bits by the DCRC encoding matrix corresponding to the first distributed CRC interleaver to obtain a second bit sequence. For example, the matrix corresponding to the K1 information bits is a = a0, a1, a2, ..., a69, GDcrc1 is the DCRC encoding matrix corresponding to the first distributed CRC interleaver, and the second bit sequence is b = a·GDcrc1. For another example, the matrix corresponding to the K1 information bits is a = a0, a1, a2, ..., a69, GDcrc2 is the DCRC encoding matrix corresponding to the first distributed CRC interleaver, and the second bit sequence is b = a·GDcrc2.

[0182] 503. The transmitting end performs polarization coding on the second bit sequence to obtain a third bit sequence.

[0183] 504. The transmitting end performs some or all of the steps including but not limited to rate matching, modulation, analog-to-digital conversion, frequency conversion, etc. on the third bit sequence and then sends the obtained sequence to be decoded.

[0184] 505. The receiving end decodes the sequence to be decoded to obtain a sequence to be checked.

[0185] 506. The receiving end performs CRC check on the sequence to be checked.

[0186] 507. When the sequence to be checked passes the check, the receiving end uses the first distributed CRC deinterleaver to deinterleave the second bit sequence to obtain the K1 information bits.

[0187] Steps 503 to 507 may refer to steps 403 to 407 in Figure 4. In a possible implementation, if the sequence to be checked fails the check, the decoding is terminated early.

[0188] In an embodiment of the present application, K1 information bits are CRC-encoded based on a CRC generator polynomial to obtain a first bit sequence, wherein the number of CRC check bits is less than 24. The first bit sequence is interleaved using a first distributed CRC interleaver. The first distributed CRC deinterleaver supports DCRC encoding of shorter payloads, thereby reducing decoding power consumption.

[0189] The following introduces an example of a CRC generator polynomial and an example of a first distributed CRC interleaver obtained based on the CRC generator polynomial.

[0190] In Example 1, L is equal to 6, K2 is equal to 70, and the CRC generator polynomial is D^6+D^5+1. The values ​​of the elements in the first distributed CRC interleaver obtained based on the CRC generator polynomial are as follows: 75. An example of the DCRC encoding matrix GDcrc corresponding to the first distributed CRC interleaver is the upper triangular matrix shown in Figure 6. Another example of the DCRC encoding matrix GDcrc corresponding to the first distributed CRC interleaver is the non-upper triangular matrix shown in Figure 7.

[0191] The first distributed CRC interleaver in Example 1 is obtained based on D^6+D^5+1. The method for obtaining the first distributed CRC interleaver in Example 1 based on D^6+D^5+1 can be similar to the method in the example of obtaining the first distributed CRC interleaver based on the CRC generator polynomial in step 502, and will not be repeated here.

[0192] In Example 1', L is equal to 6, K2 is equal to 70, and the CRC generator polynomial is D^6+D^5+1. The values ​​of the elements in the first distributed CRC interleaver obtained based on the CRC generator polynomial are as follows:

[0193] The first distributed CRC interleaver in Example 1' is obtained based on D^6+D^5+1. The method of obtaining the first distributed CRC interleaver in Example 1' based on D^6+D^5+1 can be similar to the method in an example of obtaining the first distributed CRC interleaver based on the L-length CRC generator polynomial in step 402, and will not be repeated here. The first distributed CRC interleaver in Example 1 and the first distributed CRC interleaver in Example 1' are obtained based on the same CRC generator polynomial, with the difference that: when the first distributed CRC interleaver in Example 1 is obtained based on D^6+D^5+1, the positions of the message bits associated with each check column and the positions of each check column are packaged as a whole according to the order of the positions of each check column; when the first distributed CRC interleaver in Example 1' is obtained based on D^6+D^5+1, the positions of the message bits associated with each check column and the positions of each check column are packaged as a whole according to the maximum value in the element sequence corresponding to each check column (that is, the position of the last message bit checked by each check column) in ascending order. By comparing Example 1 and Example 1', it can be found that the second check position 71 of the first distributed CRC interleaver in Example 1 becomes the first check position of the first distributed CRC interleaver in Example 1', the third check position 72 of the first distributed CRC interleaver in Example 1 becomes the second check position of the first distributed CRC interleaver in Example 1', the fourth check position 73 of the first distributed CRC interleaver in Example 1 becomes the third check position of the first distributed CRC interleaver in Example 1', the fifth check position 74 of the first distributed CRC interleaver in Example 1 becomes the fourth check position of the first distributed CRC interleaver in Example 1', the first check position 70 of the first distributed CRC interleaver in Example 1 becomes the fifth check position of the first distributed CRC interleaver in Example 1', and the sixth check position of the first distributed CRC interleaver in Example 1 is still the sixth check position of the first distributed CRC interleaver in Example 1'. It should be noted that the message position checked by each check position also changes with the change of the check position.

[0194] In the present application, for any CRC generating polynomial, a corresponding distributed CRC interleaver can be generated in a manner similar to the method in the example of obtaining a first distributed CRC interleaver based on the CRC generating polynomial in step 502; or a corresponding distributed CRC interleaver can be generated in a manner similar to the method in an example of obtaining a first distributed CRC interleaver based on an L-length CRC generating polynomial in step 402.

[0195] Example 2: L is equal to 6, K2 is equal to 70, the CRC generator polynomial is D^6+D^5+D^4+D^3+1, and the values ​​of the elements in the first distributed CRC interleaver are as follows: An example of the DCRC coding matrix GDcrc corresponding to the CRC interleaver is the upper triangular matrix shown in Figure 8. Figure 8 is an example of a DCRC coding matrix corresponding to another first distributed CRC interleaver provided in an embodiment of the present application. If the payload bits are K = 50 bits a = a0, a1, a2, ..., a49, and the sequence of a after DCRC encoding is a bit sequence b = b0, b1, b2, ..., b55 with a length of K + L = 50 + 6 = 56, then b = a·GDcrc, GDcrc can be a submatrix of the upper triangular matrix shown in Figure 8, or a submatrix of the non-upper triangular matrix in Figure 9 below. Figure 9 is an example of a DCRC coding matrix corresponding to another first distributed CRC interleaver provided in an embodiment of the present application. If a non-upper triangular matrix is ​​used, the submatrix is ​​extracted by extracting the last K rows of the non-upper triangular matrix and skipping the first 20 rows. If a non-upper triangular matrix is ​​used for DCRC encoding, the submatrix is ​​extracted by skipping the elements less than 20 in the DCRC interleaver, selecting the remaining elements with values ​​greater than 20 as row indices, and extracting these rows from the upper triangular matrix to form a matrix of 50 rows and 56 columns for DCRC encoding.

[0196] Example 3: L is equal to 6, K2 is equal to 70, the CRC generator polynomial is D^6+D^4+D^3+D+1, and the values ​​of the elements in the first distributed CRC interleaver are as follows: 75. An example of a DCRC encoding matrix GDcrc corresponding to the first distributed CRC interleaver is the upper triangular matrix shown in Figure 10. Figure 10 is an example of another DCRC encoding matrix corresponding to the first distributed CRC interleaver provided in an embodiment of the present application. In this document, nz (none zero) in the figure represents the number of non-zero elements.

[0197] In Example 4, L is equal to 6, K2 is equal to 70, the CRC generator polynomial is D^6+D^3+D^2+D+1, and the values ​​of the elements in the first distributed CRC interleaver are as follows: An example of a DCRC encoding matrix GDcrc corresponding to the CRC interleaver is an upper triangular matrix shown in Figure 11. Figure 11 is an example of a DCRC encoding matrix corresponding to another first distributed CRC interleaver provided in an embodiment of the present application.

[0198] Example 5: L is equal to 6, K2 is equal to 70, the CRC generator polynomial is D^6+D^5+D^2+1, and the values ​​of the elements in the first distributed CRC interleaver are as follows: FIG12 is an example of a DCRC coding matrix corresponding to another first distributed CRC interleaver provided in an embodiment of the present application.

[0199] Example 6: L is equal to 6, K2 is equal to 70, the CRC generator polynomial is D^6+D^5+D^4+D^2+1, and the values ​​of the elements in the first distributed CRC interleaver are as follows: An example of a DCRC encoding matrix GDcrc corresponding to a distributed CRC interleaver is an upper triangular matrix shown in Figure 13. Figure 13 is an example of a DCRC encoding matrix corresponding to another first distributed CRC interleaver provided in an embodiment of the present application.

[0200] In Example 7, L is equal to 6, K2 is equal to 70, the CRC generator polynomial is D^6+D^3+D^2+1, and the values ​​of the elements in the first distributed CRC interleaver are as follows: An example of a DCRC encoding matrix GDcrc corresponding to a distributed CRC interleaver is an upper triangular matrix shown in Figure 14. Figure 14 is an example of a DCRC encoding matrix corresponding to another first distributed CRC interleaver provided in an embodiment of the present application.

[0201] Example 8: L is equal to 6, K2 is equal to 70, the CRC generator polynomial is D^6+D^5+D^3+D^2+1, and the values ​​of the elements in the first distributed CRC interleaver are as follows: 75. An example of the DCRC encoding matrix GDcrc corresponding to the first distributed CRC interleaver is the upper triangular matrix shown in Figure 15. Figure 15 is an example of another DCRC encoding matrix corresponding to the first distributed CRC interleaver provided in an embodiment of the present application.

[0202] Example 9: L is equal to 6, K2 is equal to 70, the CRC generator polynomial is D^6+D^5+D^4+D^3+D^2+1, and the values ​​of the elements in the first distributed CRC interleaver are as follows: 75. An example of the DCRC encoding matrix GDcrc corresponding to the first distributed CRC interleaver is the upper triangular matrix shown in Figure 16. Figure 16 is an example of another DCRC encoding matrix corresponding to the first distributed CRC interleaver provided in an embodiment of the present application.

[0203] In Example 10, L is equal to 6, K2 is equal to 70, the CRC generator polynomial is D^6+D^5+D^4+D^3+D+1, and the values ​​of the elements in the first distributed CRC interleaver are as follows: 75. An example of the DCRC encoding matrix GDcrc corresponding to the first distributed CRC interleaver is the upper triangular matrix shown in Figure 17. Figure 17 is an example of another DCRC encoding matrix corresponding to the first distributed CRC interleaver provided in an embodiment of the present application.

[0204] In Example 11, L is equal to 6, K2 is equal to 70, the CRC generator polynomial is D^6+D^4+D^2+D+1, and the values ​​of the elements in the first distributed CRC interleaver are as follows: An example of a DCRC encoding matrix GDcrc corresponding to a distributed CRC interleaver is an upper triangular matrix shown in Figure 18. Figure 18 is an example of a DCRC encoding matrix corresponding to another first distributed CRC interleaver provided in an embodiment of the present application.

[0205] In Example 12, L is equal to 11, K2 is equal to 70, the CRC generator polynomial is D^11+D^10+D^9+D^5+1, and the values ​​of the elements in the first distributed CRC interleaver are as follows:

[0206] The first distributed CRC interleaver in Example 12 is obtained based on D^11+D^10+D^9+D^5+1. The method for obtaining the first distributed CRC interleaver in Example 12 based on D^11+D^10+D^9+D^5+1 can be similar to the method in the example of obtaining the first distributed CRC interleaver based on the CRC generator polynomial in step 502, and will not be repeated here.

[0207] The DCRC encoding matrix GDcrc corresponding to the first distributed CRC interleaver can have the following two forms, one is the upper triangular form GDcrc1, that is, DCRC interleaving is performed on the K rows and (K+L) columns of Gcrc, wherein the interleaver used for the interleaving of the K rows is an interleaver composed of K elements with values ​​less than K read out from the DCRC interleaver in a natural order; the interleaver used for the interleaving of the (K+L) columns is the DCRC interleaver with the length of (K+L) above; another form of the DCRC encoding matrix is ​​also a matrix with K rows and (K+L) columns, but it is not upper triangular, that is, GDcrc2, which is generated by interleaving only the (K+L) columns of Gcrc, and not interleaving the K rows of the matrix. If the payload bits are K = 70 bits a = a0, a1, a2, ..., a69, and the sequence after DCRC encoding is a bit sequence b = b0, b1, b2, ..., b80 of length K + L = 70 + 11 = 81, then b = a · GDcrc1 or b = a · GDcrc2. GDcrc1 is the upper triangular matrix shown in Figure 19. Figure 19 is an example of a DCRC encoding matrix corresponding to a first distributed CRC interleaver provided in an embodiment of the present application. GDcrc2 is a non-upper triangular matrix shown in Figure 20 below, that is, only the columns of Gcrc are interleaved. Figure 20 is an example of a DCRC encoding matrix corresponding to another first distributed CRC interleaver provided in an embodiment of the present application. The advantage of GDcrc2 is that it is more convenient to nestedly read the DCRC encoding matrix. For payloads with K < 70, it is only necessary to skip the first (70-K) rows of the matrix and use the inverse K rows of the matrix for DCRC encoding.

[0208] In Example 12', L is equal to 11, K2 is equal to 70, the CRC generator polynomial is D^11+D^10+D^9+D^5+1, and the values ​​of the elements in the first distributed CRC interleaver are as follows:

[0209] The first distributed CRC interleaver in Example 12' is obtained based on D^11+D^10+D^9+D^5+1. The method for obtaining the first distributed CRC interleaver in Example 12' based on D^11+D^10+D^9+D^5+1 can be similar to the method in the example of obtaining the first distributed CRC interleaver based on the L-length CRC generator polynomial in step 402, and is not repeated here. The first distributed CRC interleaver in Example 12 and the first distributed CRC interleaver in Example 12' are obtained based on the same CRC generating polynomial, and the difference is that: when the first distributed CRC interleaver in Example 12 is obtained based on D^11+D^10+D^9+D^5+1, the positions of the message bits associated with each check column and the positions of each check column are packaged as a whole in the order of the positions of each check column; when the first distributed CRC interleaver in Example 12' is obtained based on D^11+D^10+D^9+D^5+1, the positions of the message bits associated with each check column and the positions of each check column are packaged as a whole in order from small to large according to the maximum value in the element sequence corresponding to each check column (that is, the position of the last message bit checked by each check column).By comparing Example 12 and Example 12', it can be found that the 7th check position 76 of the first distributed CRC interleaver in Example 12 becomes the first check position of the first distributed CRC interleaver in Example 12'; the 3rd check position 72 of the first distributed CRC interleaver in Example 12 becomes the 2nd check position of the first distributed CRC interleaver in Example 12', the 8th check position 77 of the first distributed CRC interleaver in Example 12 becomes the 3rd check position of the first distributed CRC interleaver in Example 12', the 4th check position 73 of the first distributed CRC interleaver in Example 12 is still the 4th check position of the first distributed CRC interleaver in Example 12', the 9th check position 78 of the first distributed CRC interleaver in Example 12 becomes the 5th check position of the first distributed CRC interleaver in Example 12'; the 5th check position 74 of the first distributed CRC interleaver in Example 12 becomes the 5th check position of the first distributed CRC interleaver in Example 12' The 6th check position of the distributed CRC interleaver; the 10th check position 79 of the first distributed CRC interleaver in Example 12 becomes the 7th check position of the first distributed CRC interleaver in Example 12'; the 1st check position 70 of the first distributed CRC interleaver in Example 12 becomes the 8th check position of the first distributed CRC interleaver in Example 12'; the 2nd check position 71 of the first distributed CRC interleaver in Example 12 becomes the 9th check position of the first distributed CRC interleaver in Example 12'; the 6th check position 75 of the first distributed CRC interleaver in Example 12 becomes the 10th check position of the first distributed CRC interleaver in Example 12'; the 11th check position 80 of the first distributed CRC interleaver in Example 12 is still the 11th check position of the first distributed CRC interleaver in Example 12'; and the message position checked by each check position also changes with the change of the check position.

[0210] In Example 13, L is equal to 11, K2 is equal to 70, the CRC generator polynomial is D^11+D^7+D^6+D^2+1, and the values ​​of the elements in the first distributed CRC interleaver are as follows: It is the upper triangular matrix shown in Figure 21. Figure 21 is an example of a DCRC encoding matrix corresponding to another first distributed CRC interleaver provided in an embodiment of the present application.

[0211] In Example 14, L is equal to 11, K2 is equal to 70, the CRC generator polynomial is D^11+D^10+D^9+D^6+D^4+D^2+1, and the values ​​of the elements in the first distributed CRC interleaver are as follows: It is the upper triangular matrix shown in Figure 22. Figure 22 is an example of a DCRC encoding matrix corresponding to another first distributed CRC interleaver provided in an embodiment of the present application.

[0212] In Example 15, L is equal to 11, K2 is equal to 70, the CRC generator polynomial is D^11+D^10+D^9+D^7+D^5+D+1, and the values ​​of the elements in the first distributed CRC interleaver are as follows: FIG23 is an example of a DCRC encoding matrix corresponding to another first distributed CRC interleaver provided in an embodiment of the present application.

[0213] In Example 16, L is equal to 11, K2 is equal to 70, the CRC generator polynomial is D^11+D^9+D^8+D^6+D^5+D+1, and the values ​​of the elements in the first distributed CRC interleaver are as follows: It is the upper triangular matrix shown in Figure 24. Figure 24 is an example of a DCRC encoding matrix corresponding to another first distributed CRC interleaver provided in an embodiment of the present application.

[0214] In Example 17, L is equal to 11, K2 is equal to 70, the CRC generator polynomial is D^11+D^10+D^9+D^8+D^7+D^5+D^4+D+1, and the values ​​of the elements in the first distributed CRC interleaver are as follows: It is the upper triangular matrix shown in Figure 25. Figure 25 is an example of a DCRC encoding matrix corresponding to another first distributed CRC interleaver provided in an embodiment of the present application.

[0215] In Example 18, L is equal to 11, K2 is equal to 70, the CRC generator polynomial is D^11+D^10+D^3+D+1, and the values ​​of the elements in the first distributed CRC interleaver are as follows: It is the upper triangular matrix shown in Figure 26. Figure 26 is an example of a DCRC encoding matrix corresponding to another first distributed CRC interleaver provided in an embodiment of the present application.

[0216] In Example 19, L is equal to 11, K2 is equal to 70, the CRC generator polynomial is D^11+D^5+D^3+D+1, and the values ​​of the elements in the first distributed CRC interleaver are as follows: FIG27 is an example of a DCRC encoding matrix corresponding to another first distributed CRC interleaver provided in an embodiment of the present application.

[0217] In Example 20, L is equal to 11, K2 is equal to 70, the CRC generator polynomial is D^11+D^10+D^9+D^8+D^6+D^5+D^3+D+1, and the values ​​of the elements in the first distributed CRC interleaver are as follows: It is the upper triangular matrix shown in Figure 28. Figure 28 is an example of a DCRC encoding matrix corresponding to another first distributed CRC interleaver provided in an embodiment of the present application.

[0218] In Example 21, L is equal to 11, K2 is equal to 70, the CRC generator polynomial is D^11+D^10+D^8+D^7+D^6+D^5+D^3+D+1, and the values ​​of the elements in the first distributed CRC interleaver are as follows: It is the upper triangular matrix shown in Figure 29. Figure 29 is an example of a DCRC encoding matrix corresponding to another first distributed CRC interleaver provided in an embodiment of the present application.

[0219] In Example 22, L is equal to 11, K2 is equal to 70, the CRC generator polynomial is D^11+D^9+D^7+D^6+D^5+D^4+D^3+D+1, and the values ​​of the elements in the first distributed CRC interleaver are as follows: It is the upper triangular matrix shown in Figure 30. Figure 30 is an example of a DCRC encoding matrix corresponding to another first distributed CRC interleaver provided in an embodiment of the present application.

[0220] In Example 23, L is equal to 11, K2 is equal to 70, the CRC generator polynomial is D^11+D^10+D^9+D^7+D^6+D^3+D^2+D+1, and the values ​​of the elements in the first distributed CRC interleaver are as follows: It is the upper triangular matrix shown in Figure 31. Figure 31 is an example of a DCRC encoding matrix corresponding to another first distributed CRC interleaver provided in an embodiment of the present application.

[0221] In Example 24, L is equal to 11, K2 is equal to 70, the CRC generator polynomial is D^11+D^8+D^6+D^5+D^4+D^3+D^2+D+1, and the values ​​of the elements in the first distributed CRC interleaver are as follows: It is the upper triangular matrix shown in Figure 32. Figure 32 is an example of a DCRC encoding matrix corresponding to another first distributed CRC interleaver provided in an embodiment of the present application.

[0222] In Example 25, L is equal to 16, K2 is equal to 100, the CRC generator polynomial is D^16+D^12+D^5+1, and the values ​​of the elements in the first distributed CRC interleaver are as follows:

[0223] In one possible implementation, the low-power device may use only one channel coding method, such as the data channel, broadcast channel and control channel of the passive IoT all use NR control channel coding, that is, the channel coding method provided in this application, but the maximum and minimum mother code lengths are changed to further reduce power consumption. For example, the minimum mother code length Nm can be less than 32, such as Nm=16; the maximum mother code length Nmax can be reduced to the following values ​​{32, 64, 128, 256}. Figure 33 is a flow chart of another encoding method provided in an embodiment of the present application. The method flow in Figure 33 is a possible implementation of the method described in Figure 4. The method flow in Figure 33 can be applied to low-power scenarios. As shown in Figure 33, the method includes:

[0224] 3301. The transmitter performs CRC encoding on K1 information bits based on a CRC generator polynomial to obtain a first bit sequence.

[0225] 3302. The transmitter uses a first distributed CRC interleaver to interleave the first bit sequence to obtain a second bit sequence.

[0226] 3303. The transmitting end performs polarization encoding on the second bit sequence to obtain a third bit sequence.

[0227] Illustratively, the minimum mother code length Nm may be less than 32, such as Nm=16; the maximum mother code length Nmax may be reduced to the following values ​​{32, 64, 128, 256}.

[0228] 3304. The transmitting end performs some or all of the steps including but not limited to rate matching, modulation, analog-to-digital conversion, and frequency conversion on the third bit sequence and then sends the obtained first sequence to be decoded.

[0229] Correspondingly, the receiving end receives the signal carrying the first sequence to be decoded from the transmitting end.

[0230] In one possible implementation, in step 3304, the first sequence to be decoded obtained by the transmitting end may be a transmit data signal, i.e., a data signal for decoding by the receiving end to obtain K1 information bits. Steps 3301 to 3304 comprise the process of the transmitting end performing channel coding on the K1 information bits to be transmitted via the data channel.

[0231] In one possible implementation, in step 3304, the first sequence to be decoded obtained by the transmitter may be a broadcast signal, i.e., a broadcast signal that is decoded by the receiver to obtain K1 information bits. Steps 3301 to 3304 comprise the process of the transmitter performing channel coding on the K1 information bits to be transmitted via the broadcast channel.

[0232] 3305. The receiving end decodes the first sequence to be decoded to obtain a first sequence to be checked.

[0233] The receiving end may obtain the first sequence to be decoded based on the signal carrying the first sequence to be decoded from the transmitting end, which is not limited in this application.

[0234] 3306. The receiving end performs CRC check on the first sequence to be checked.

[0235] 3307. When the first sequence to be checked passes the check, the receiving end uses the first distributed CRC deinterleaver to deinterleave the second bit sequence to obtain the above-mentioned K1 information bits.

[0236] When the first sequence to be checked passes the check, the sequence to be checked becomes the second bit sequence. Steps 3301 to 3307 may refer to steps 401 to 407 in Figure 4. In one possible implementation, if the first sequence to be checked fails the check, decoding is terminated early.

[0237] 3308. The transmitter performs CRC encoding on the K3 control bits based on the CRC generator polynomial to obtain a fourth bit sequence.

[0238] K3 is an integer greater than 0.

[0239] 3309. The transmitter uses the first distributed CRC interleaver to interleave the fourth bit sequence to obtain a fifth bit sequence.

[0240] 3310. The transmitting end performs polarization encoding on the fifth bit sequence to obtain a sixth bit sequence.

[0241] 3311. The transmitting end performs some or all of the steps including but not limited to rate matching, modulation, analog-to-digital conversion, and frequency conversion on the sixth bit sequence and then sends the obtained second sequence to be decoded.

[0242] Correspondingly, the receiving end receives the signal carrying the second sequence to be decoded from the transmitting end.

[0243] In step 3311, the second sequence to be decoded sent by the transmitter can be a transmission control signal, i.e., a control signal for the receiver to decode to obtain K3 control bits. Steps 3308 to 3311 comprise the process of the transmitter performing channel coding on the K3 control bits to be sent via the control channel. Exemplarily, the second sequence to be decoded sent by the transmitter is carried on the LP-WUS.

[0244] 3312. The receiving end decodes the second sequence to be decoded to obtain a second sequence to be checked.

[0245] 3313. The receiving end performs CRC check on the second sequence to be checked.

[0246] 3314. When the second sequence to be checked passes the check, the receiving end uses the first distributed CRC deinterleaver to deinterleave the fifth bit sequence to obtain the above-mentioned K3 control bits.

[0247] If the second sequence to be checked passes verification, the sequence to be checked becomes the fifth bit sequence. Steps 3308 to 3314 can refer to steps 401 to 407 in Figure 4 . The order of steps 3301 to 3307 and steps 3308 to 3314 is not limited. In one possible implementation, if the second sequence to be checked fails verification, decoding is terminated early.

[0248] In an embodiment of the present application, the control channel and the data channel share the NR control channel coding, that is, the channel coding method provided by the present application is friendly and compatible with the NR standard, and the coding complexity is reduced.

[0249] FIG34 is a flow chart of another encoding method provided by an embodiment of the present application. The method flow in FIG34 is a possible implementation of the method described in FIG4 . The method flow in FIG34 can be applied to low power consumption scenarios. As shown in FIG34 , the method includes:

[0250] 3401. The transmitter performs CRC encoding on K3 control bits based on a CRC generator polynomial to obtain a fourth bit sequence.

[0251] K3 is an integer greater than 0.

[0252] 3402. The transmitter uses a first distributed CRC interleaver to interleave the fourth bit sequence to obtain a fifth bit sequence.

[0253] 3403. The transmitting end performs polarization encoding on the fifth bit sequence to obtain a sixth bit sequence.

[0254] 3404. The transmitting end sends a low-power wake-up signal to the receiving end, wherein the low-power wake-up signal carries a second sequence to be decoded obtained after the transmitting end performs part or all of the steps including but not limited to rate matching, modulation, analog-to-digital conversion, frequency conversion, etc. on the sixth bit sequence.

[0255] Correspondingly, the receiving end receives the low-power wake-up signal from the transmitting end.

[0256] The low-power wake-up signal is used to wake up the main receiver of the receiving end. The receiving end may include the main receiver and the low-power wake-up receiver as described above in FIG1 .

[0257] 3405. The receiving end decodes the second sequence to be decoded to obtain a second sequence to be checked.

[0258] 3406. The receiving end performs CRC check on the second sequence to be checked.

[0259] 3407. When the second sequence to be checked passes the check, the receiving end uses the first distributed CRC deinterleaver to deinterleave the fifth bit sequence to obtain the above-mentioned K3 control bits.

[0260] Steps 3401 to 3407 may refer to steps 401 to 407 in Figure 4. In a possible implementation, if the second sequence to be checked fails the check, the decoding is terminated early.

[0261] 3408. The transmitter performs CRC encoding on the K1 information bits based on the CRC generator polynomial to obtain a first bit sequence.

[0262] 3409. The transmitter uses a first distributed CRC interleaver to interleave the first bit sequence to obtain a second bit sequence.

[0263] 3410. The transmitter performs polarization encoding on the second bit sequence to obtain a third bit sequence.

[0264] 3411. The transmitter sends an NR signal to the receiver, where the NR signal carries a first sequence to be decoded obtained after the transmitter performs some or all of the steps including but not limited to rate matching, modulation, analog-to-digital conversion, and frequency conversion on a third bit sequence.

[0265] Correspondingly, the receiving end receives the NR signal from the transmitting end.

[0266] In one possible implementation, in step 3411, the first sequence to be decoded obtained by the transmitter may be a transmit data signal, i.e., a data signal decoded by the receiver to obtain K1 information bits. Steps 3408 to 3411 comprise the process of the transmitter performing channel coding on the K1 information bits to be transmitted via the data channel.

[0267] In one possible implementation, in step 3411, the first sequence to be decoded obtained by the transmitter may be a broadcast signal, i.e., a broadcast signal that is decoded by the receiver to obtain K1 information bits. Steps 3408 to 3411 comprise the process of the transmitter performing channel coding on the K1 information bits to be transmitted via the broadcast channel.

[0268] 3412. The receiving end decodes the first sequence to be decoded to obtain a first sequence to be checked.

[0269] 3413. The receiving end performs CRC check on the first sequence to be checked.

[0270] 3414. When the first sequence to be checked passes the check, the receiving end uses the first distributed CRC deinterleaver to deinterleave the second bit sequence to obtain the above-mentioned K1 information bits.

[0271] Steps 3408 to 3414 may refer to steps 401 to 407 in Figure 4. In a possible implementation, if the first sequence to be checked fails the check, the decoding is terminated early.

[0272] In an embodiment of the present application, the low-power wake-up signal and the NR signal share the NR control channel coding, that is, the channel coding method provided by the present application is friendly and compatible with the NR standard, and the coding complexity is reduced.

[0273] The following, in conjunction with the accompanying drawings, describes the structure of a transmitter capable of implementing the encoding method provided in the embodiments of the present application, as well as the structure of a receiver capable of implementing the decoding method provided in the embodiments of the present application. In this application, both the transmitter and the receiver may be communication devices. The following is a brief description using the transmitter and the receiver as communication devices. For implementation details, please refer to the description of the method embodiments above and will not be repeated here.

[0274] Figure 35 is a schematic diagram of the structure of a communication device 3500 provided in an embodiment of the present application. The communication device 3500 can implement the functions or steps implemented by the transmitting end in each of the above-mentioned method embodiments, and can also implement the functions or steps implemented by the receiving end in each of the above-mentioned method embodiments. The communication device may include a processing module 3510 and a transceiver module 3520. In one possible implementation, it may also include a storage unit, which can be used to store instructions (code or program) and / or data. The processing module 3510 and the transceiver module 3520 can be coupled to the storage unit. For example, the processing module 3510 can read the instructions (code or program) and / or data in the storage unit to implement the corresponding method. The above-mentioned units can be provided independently or partially or fully integrated. For example, the transceiver module 3520 may include a transmitting module and a receiving module. The transmitting module can be a transmitter, and the receiving module can be a receiver. The entity corresponding to the transceiver module 3520 can be a transceiver circuit, such as a transceiver or a communication interface.

[0275] In some possible implementations, the communication device 3500 can implement the behaviors and functions of the transmitting end in the above-described method embodiments. For example, the communication device 3500 can be a transmitting end, or a component (e.g., a chip or circuit) used in the transmitting end. The transceiver module 3520 can, for example, be used to perform all receiving or transmitting operations performed by the transmitting end in the embodiments of Figures 3, 4, 33, or 34. The processing module 3510 can, for example, be used to perform all operations performed by the transmitting end in the embodiments of Figures 3, 4, 33, or 34 except for the transmitting and receiving operations.

[0276] In some possible implementations, the communication device 3500 can implement the corresponding behaviors and functions of the receiving end in the above-mentioned method embodiments. For example, the communication device 3500 can be a receiving end, or it can be a component (such as a chip or circuit) used in the receiving end. The transceiver module 3520 can be used to perform all receiving or sending operations performed by the receiving end in the embodiments of Figures 3, 4, 33, or 34. The processing module 3510 can be used to perform all operations performed by the receiving end in the embodiments of Figures 3, 4, 33, or 34, except for the transceiver operations.

[0277] Figure 36 is a schematic diagram of the structure of another device 360 ​​provided in an embodiment of the present application. The device in Figure 36 can be the aforementioned transmitter or a chip used in the transmitter, or the aforementioned receiver or a chip used in the receiver. As shown in Figure 36 , the device 360 ​​includes a processing circuit 3610 and a transceiver circuit 3620.

[0278] In some embodiments of the present application, the processing circuit 3610 and the transceiver circuit 3620 may be configured to execute functions or operations performed by the transmitting end. The transceiver circuit 3620 may, for example, be configured to execute all receiving or transmitting operations performed by the transmitting end in the embodiments of FIG. 3 , FIG. 4 , FIG. 33 , or FIG. 34 . The processing circuit 3610 may, for example, be configured to execute all operations performed by the transmitting end in the embodiments of FIG. 3 , FIG. 4 , FIG. 33 , or FIG. 34 , except for the transceiver operations.

[0279] In some embodiments of the present application, the processing circuit 3610 and the transceiver circuit 3620 may be configured to execute functions or operations performed by the receiving end. The transceiver circuit 3620, for example, may be configured to execute all receiving or transmitting operations performed by the receiving end in the embodiments of FIG. 3 , FIG. 4 , FIG. 33 , or FIG. 34 . The processing circuit 3610, for example, may be configured to execute all operations performed by the receiving end in the embodiments of FIG. 3 , FIG. 4 , FIG. 33 , or FIG. 34 , except for the transceiver operations.

[0280] In one possible implementation, the transceiver circuit 3620 includes at least one transceiver, and the processing circuit 3610 includes at least one processor, or a circuit in at least one processor for processing or control.

[0281] The transceiver is used to communicate with other devices / apparatuses via a transmission medium. The processor uses the transceiver to send and receive data and / or signaling, and is used to implement the method in the above-mentioned method embodiment. The processor can implement the functions of the processing module 3510, and the transceiver can implement the functions of the transceiver module 3520. Optionally, the transceiver may include a radio frequency circuit and an antenna, and the radio frequency circuit is mainly used for converting baseband signals into radio frequency signals and processing radio frequency signals. The antenna is mainly used to send and receive radio frequency signals in the form of electromagnetic waves. Input and output devices, such as touch screens, display screens, keyboards, etc. are mainly used to receive data input by users and output data to users.

[0282] Optionally, device 360 ​​may further include at least one memory for storing program instructions and / or data. The memory and processor are coupled. Coupling in the embodiments of the present application is an indirect coupling or communication connection between devices, units, or modules, which may be electrical, mechanical, or other forms, and is used for information exchange between devices, units, or modules. The processor may operate in conjunction with the memory. The processor may execute program instructions stored in the memory. At least one of the at least one memory may be included in the processor.

[0283] The processor can read software programs in the memory, interpret and execute the instructions of the software programs, and process the data of the software programs. When data needs to be transmitted wirelessly, the processor performs baseband processing on the data to be transmitted and outputs the baseband signal to the radio frequency circuit. The radio frequency circuit performs radio frequency processing on the baseband signal and then transmits the radio frequency signal to the outside in the form of electromagnetic waves via the antenna. When data is sent to device 360, the radio frequency circuit receives the radio frequency signal via the antenna, converts the radio frequency signal into a baseband signal, and outputs the baseband signal to the processor. The processor converts the baseband signal into data and processes the data.

[0284] In another implementation, the RF circuit and antenna may be arranged independently of the processor performing baseband processing. For example, in a distributed scenario, the RF circuit and antenna may be arranged remotely from the device 360 ​​.

[0285] The specific connection medium between the above-mentioned transceiver, processor and memory is not limited in the embodiments of the present application.

[0286] In the embodiments of the present application, the processor may be one of the following devices: a general-purpose processor, a digital signal processor, an application-specific integrated circuit, a field programmable gate array or other programmable logic device, a discrete gate or transistor logic device, a discrete hardware component, or all or part of the circuits used for processing functions in the aforementioned devices, which may implement or execute the various methods, steps, and logic block diagrams disclosed in the embodiments of the present application. A general-purpose processor may be a microprocessor or any conventional processor, etc. The steps of the method disclosed in conjunction with the embodiments of the present application may be directly embodied as being executed by a hardware processor, or may be executed by a combination of hardware and software modules in the processor.

[0287] In one possible implementation, the processing circuit 3610 includes at least one logic circuit, and the transceiver circuit 3620 includes at least one interface. The processing module 3510 in Figure 35 can be implemented using a logic circuit, and the transceiver module 3520 in Figure 35 can be implemented using an interface. The logic circuit can be a chip, a processing circuit, an integrated circuit, or a system on chip (SoC) chip, and the interface can be a communication interface, an input / output interface, etc. In the embodiment of the present application, the logic circuit and the interface can also be coupled to each other. The embodiment of the present application does not limit the specific connection method of the logic circuit and the interface.

[0288] The present application also provides a computer-readable storage medium, in which a computer program or instruction is stored. When the computer program or instruction is executed on a computer, the computer executes the method of the above embodiment.

[0289] The present application also provides a computer program product, which includes instructions or a computer program. When the instructions or the computer program are run on a computer, the method in the above embodiment is executed.

[0290] The present application also provides a communication system, comprising the above-mentioned transmitting end and the above-mentioned receiving end.

[0291] The present application also provides a chip, which includes: a communication interface and a processor; the communication interface is used for sending and receiving signals of the above-mentioned chip; the processor is used to execute computer program instructions so that the communication device including the above-mentioned chip executes the method in the above-mentioned embodiment.

[0292] In the above embodiments, all or part of the embodiments may be implemented using software, hardware, firmware, or any combination thereof. When implemented using software, all or part of the embodiments may be implemented in the form of a computer program product. The computer program product includes one or more computer programs or instructions. When the computer program or instructions are loaded and executed on a computer, the processes or functions described in the embodiments of the present application are performed in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, a network device, a user device, or other programmable device. The computer program or instructions may be stored in a computer-readable storage medium or transferred from one computer-readable storage medium to another. For example, the computer program or instructions may be transferred from one website, computer, server, or data center to another website, computer, server, or data center via wired or wireless means. The computer-readable storage medium may be any available medium that can be accessed by a computer or a data storage device such as a server or data center that integrates one or more available media. The available medium may be a magnetic medium, such as a floppy disk, hard disk, or magnetic tape; an optical medium, such as a digital video disk; or a semiconductor medium, such as a solid-state drive. The computer-readable storage medium may be a volatile or nonvolatile storage medium, or may include both volatile and nonvolatile types of storage media.

[0293] In the various embodiments of the present application, unless otherwise specified or there is a logical conflict, the terms and / or descriptions between different embodiments are consistent and can be referenced by each other. The technical features in different embodiments can be combined to form new embodiments according to their inherent logical relationships.

Claims

1. A coding method, characterized in that: include: Performing cyclic redundancy check (CRC) encoding on K1 information bits to obtain a first bit sequence, where the first bit sequence includes the K1 information bits and L CRC bits, where K1 is a positive integer and L is a positive integer less than 24; Interleave the first bit sequence using a first distributed CRC interleaver to obtain a second bit sequence; Among them, the first distributed CRC interleaver includes (K2+L) elements, and the values ​​of the (K2+LS)th element to the (K2+L)th element of the first distributed CRC interleaver are (K2+L-1-S) to (K2+L-1) respectively, S is an integer greater than or equal to 0 and less than or equal to L, and K2 is an integer greater than or equal to K1; or, the first distributed CRC interleaver includes a total of (K2+L) natural numbers from 0 to (K2+L-1), P in the first distributed CRC interleaver is before Q, P and Q are both integers greater than or equal to K2, and P is greater than Q.

2. The encoding method according to claim 1, characterized in that The L is equal to 6, 11 or 16.

3. The encoding method according to claim 2, characterized in that The K2 is equal to 32, 40, 48, 54, 64, 70 or 100.

4. The encoding method according to any one of claims 1 to 3, characterized in that: The first distributed CRC interleaver is obtained by arranging L element sequences in order, any two element sequences among the L element sequences are a first element sequence and a second element sequence, the elements included in the first element sequence are obtained based on the positions of information bits associated with the first check column, the elements included in the second element sequence are obtained based on the positions of information bits associated with the second check column, the first check column and the second check column are any two columns in a check matrix obtained based on a CRC generating polynomial of length L, and when the maximum element in the first element sequence representing the position of the information bit associated with the first check column is greater than the maximum element in the second element sequence representing the position of the information bit associated with the second check column, the first element sequence in the first distributed CRC interleaver is sorted after the second element sequence.

5. The encoding method according to any one of claims 1 to 4, characterized in that: The step of performing cyclic redundancy check (CRC) encoding on the K1 information bits to obtain a first bit sequence comprises: The K1 information bits are CRC-encoded based on a CRC generator polynomial to obtain the first bit sequence, where L is equal to 6, K2 is equal to 70, the CRC generator polynomial is D^6+D^5+1, and the values ​​of the elements in the first distributed CRC interleaver are as follows:

6. The encoding method according to any one of claims 1 to 4, characterized in that: The step of performing cyclic redundancy check (CRC) encoding on the K1 information bits to obtain a first bit sequence comprises: The K1 information bits are CRC-encoded based on a CRC generator polynomial to obtain the first bit sequence, where L is equal to 6, K2 is equal to 70, the CRC generator polynomial is D^6+D^5+D^4+D^3+1, and the values ​​of the elements in the first distributed CRC interleaver are as follows:

7. The encoding method according to any one of claims 1 to 4, characterized in that: The step of performing cyclic redundancy check (CRC) encoding on the K1 information bits to obtain a first bit sequence comprises: The K1 information bits are CRC-encoded based on a CRC generator polynomial to obtain the first bit sequence, where L is equal to 6, K2 is equal to 70, the CRC generator polynomial is D^6+D^4+D^3+D+1, and the values ​​of the elements in the first distributed CRC interleaver are as follows:

8. The encoding method according to any one of claims 1 to 4, characterized in that: The step of performing cyclic redundancy check (CRC) encoding on the K1 information bits to obtain a first bit sequence comprises: The K1 information bits are CRC-encoded based on a CRC generator polynomial to obtain the first bit sequence, where L is equal to 6, K2 is equal to 70, the CRC generator polynomial is D^6+D^3+D^2+D+1, and the values ​​of the elements in the first distributed CRC interleaver are as follows:

9. The encoding method according to any one of claims 1 to 4, characterized in that: The step of performing cyclic redundancy check (CRC) encoding on the K1 information bits to obtain a first bit sequence comprises: The K1 information bits are CRC-encoded based on a CRC generator polynomial to obtain the first bit sequence, where L is equal to 6, K2 is equal to 70, the CRC generator polynomial is D^6+D^5+D^2+1, and the values ​​of the elements in the first distributed CRC interleaver are as follows:

10. The encoding method according to any one of claims 1 to 4, characterized in that: The step of performing cyclic redundancy check (CRC) encoding on the K1 information bits to obtain a first bit sequence comprises: The K1 information bits are CRC-encoded based on a CRC generator polynomial to obtain the first bit sequence, where L is equal to 6, K2 is equal to 70, the CRC generator polynomial is D^6+D^5+D^4+D^2+1, and the values ​​of the elements in the first distributed CRC interleaver are as follows:

11. The encoding method according to any one of claims 1 to 4, characterized in that: The step of performing cyclic redundancy check (CRC) encoding on the K1 information bits to obtain a first bit sequence comprises: The K1 information bits are CRC-encoded based on a CRC generator polynomial to obtain the first bit sequence, where L is equal to 6, K2 is equal to 70, the CRC generator polynomial is D^6+D^3+D^2+1, and the values ​​of the elements in the first distributed CRC interleaver are as follows:

12. The encoding method according to any one of claims 1 to 4, characterized in that: The step of performing cyclic redundancy check (CRC) encoding on the K1 information bits to obtain a first bit sequence comprises: The K1 information bits are CRC-encoded based on a CRC generator polynomial to obtain the first bit sequence, where L is equal to 6, K2 is equal to 70, the CRC generator polynomial is D^6+D^5+D^3+D^2+1, and the values ​​of the elements in the first distributed CRC interleaver are as follows:

13. The encoding method according to any one of claims 1 to 4, characterized in that: The step of performing cyclic redundancy check (CRC) encoding on the K1 information bits to obtain a first bit sequence comprises: The K1 information bits are CRC-encoded based on a CRC generator polynomial to obtain the first bit sequence, where L is equal to 6, K2 is equal to 70, the CRC generator polynomial is D^6+D^5+D^4+D^3+D^2+1, and the values ​​of the elements in the first distributed CRC interleaver are as follows:

14. The encoding method according to any one of claims 1 to 4, characterized in that: The step of performing cyclic redundancy check (CRC) encoding on the K1 information bits to obtain a first bit sequence comprises: The K1 information bits are CRC-encoded based on a CRC generator polynomial to obtain the first bit sequence, where L is equal to 6, K2 is equal to 70, the CRC generator polynomial is D^6+D^5+D^4+D^3+D+1, and the values ​​of the elements in the first distributed CRC interleaver are as follows:

15. The encoding method according to any one of claims 1 to 4, characterized in that: The step of performing cyclic redundancy check (CRC) encoding on the K1 information bits to obtain a first bit sequence comprises: The K1 information bits are CRC-encoded based on a CRC generator polynomial to obtain the first bit sequence, where L is equal to 6, K2 is equal to 70, the CRC generator polynomial is D^6+D^4+D^2+D+1, and the values ​​of the elements in the first distributed CRC interleaver are as follows:

16. The encoding method according to any one of claims 1 to 4, characterized in that: The step of performing cyclic redundancy check (CRC) encoding on the K1 information bits to obtain a first bit sequence comprises: The K1 information bits are CRC-encoded based on a CRC generator polynomial to obtain the first bit sequence, where L is equal to 11, K2 is equal to 70, the CRC generator polynomial is D^11+D^10+D^9+D^5+1, and the values ​​of the elements in the first distributed CRC interleaver are as follows:

17. The encoding method according to any one of claims 1 to 4, characterized in that: The step of performing cyclic redundancy check (CRC) encoding on the K1 information bits to obtain a first bit sequence comprises: The K1 information bits are CRC-encoded based on a CRC generator polynomial to obtain the first bit sequence, where L is equal to 11, K2 is equal to 70, the CRC generator polynomial is D^11+D^7+D^6+D^2+1, and the values ​​of the elements in the first distributed CRC interleaver are as follows:

18. The encoding method according to any one of claims 1 to 4, characterized in that: The step of performing cyclic redundancy check (CRC) encoding on the K1 information bits to obtain a first bit sequence comprises: The K1 information bits are CRC-encoded based on a CRC generator polynomial to obtain the first bit sequence, where L is equal to 11, K2 is equal to 70, the CRC generator polynomial is D^11+D^10+D^9+D^6+D^4+D^2+1, and the values ​​of the elements in the first distributed CRC interleaver are as follows:

19. The encoding method according to any one of claims 1 to 4, characterized in that: The step of performing cyclic redundancy check (CRC) encoding on the K1 information bits to obtain a first bit sequence comprises: The K1 information bits are CRC-encoded based on a CRC generator polynomial to obtain the first bit sequence, where L is equal to 11, K2 is equal to 70, the CRC generator polynomial is D^11+D^10+D^9+D^7+D^5+D+1, and the values ​​of the elements in the first distributed CRC interleaver are as follows:

20. The encoding method according to any one of claims 1 to 4, characterized in that: The step of performing cyclic redundancy check (CRC) encoding on the K1 information bits to obtain a first bit sequence comprises: The K1 information bits are CRC-encoded based on a CRC generator polynomial to obtain the first bit sequence, where L is equal to 11, K2 is equal to 70, the CRC generator polynomial is D^11+D^9+D^8+D^6+D^5+D+1, and the values ​​of the elements in the first distributed CRC interleaver are as follows:

21. The encoding method according to any one of claims 1 to 4, characterized in that: The step of performing cyclic redundancy check (CRC) encoding on the K1 information bits to obtain a first bit sequence comprises: The K1 information bits are CRC-encoded based on a CRC generator polynomial to obtain the first bit sequence, where L is equal to 11, K2 is equal to 70, the CRC generator polynomial is D^11+D^10+D^9+D^8+D^7+D^5+D^4+D+1, and the values ​​of the elements in the first distributed CRC interleaver are as follows:

22. The encoding method according to any one of claims 1 to 4, characterized in that: The step of performing cyclic redundancy check (CRC) encoding on the K1 information bits to obtain a first bit sequence comprises: The K1 information bits are CRC-encoded based on a CRC generator polynomial to obtain the first bit sequence, where L is equal to 11, K2 is equal to 70, the CRC generator polynomial is D^11+D^10+D^3+D+1, and the values ​​of the elements in the first distributed CRC interleaver are as follows:

23. The encoding method according to any one of claims 1 to 4, characterized in that: The step of performing cyclic redundancy check (CRC) encoding on the K1 information bits to obtain a first bit sequence comprises: The K1 information bits are CRC-encoded based on a CRC generator polynomial to obtain the first bit sequence, where L is equal to 11, K2 is equal to 70, the CRC generator polynomial is D^11+D^5+D^3+D+1, and the values ​​of the elements in the first distributed CRC interleaver are as follows:

24. The encoding method according to any one of claims 1 to 4, characterized in that: The step of performing cyclic redundancy check (CRC) encoding on the K1 information bits to obtain a first bit sequence comprises: The K1 information bits are CRC-encoded based on a CRC generator polynomial to obtain the first bit sequence, where L is equal to 11, K2 is equal to 70, the CRC generator polynomial is D^11+D^10+D^9+D^8+D^6+D^5+D^3+D+1, and the values ​​of the elements in the first distributed CRC interleaver are as follows:

25. The encoding method according to any one of claims 1 to 4, characterized in that: The step of performing cyclic redundancy check (CRC) encoding on the K1 information bits to obtain a first bit sequence comprises: The K1 information bits are CRC-encoded based on a CRC generator polynomial to obtain the first bit sequence, where L is equal to 11, K2 is equal to 70, the CRC generator polynomial is D^11+D^10+D^8+D^7+D^6+D^5+D^3+D+1, and the values ​​of the elements in the first distributed CRC interleaver are as follows:

26. The encoding method according to any one of claims 1 to 4, characterized in that: The step of performing cyclic redundancy check (CRC) encoding on the K1 information bits to obtain a first bit sequence comprises: The K1 information bits are CRC-encoded based on a CRC generator polynomial to obtain the first bit sequence, where L is equal to 11, K2 is equal to 70, the CRC generator polynomial is D^11+D^9+D^7+D^6+D^5+D^4+D^3+D+1, and the values ​​of the elements in the first distributed CRC interleaver are as follows:

27. The encoding method according to any one of claims 1 to 4, characterized in that: The step of performing cyclic redundancy check (CRC) encoding on the K1 information bits to obtain a first bit sequence comprises: The K1 information bits are CRC-encoded based on a CRC generator polynomial to obtain the first bit sequence, where L is equal to 11, K2 is equal to 70, the CRC generator polynomial is D^11+D^10+D^9+D^7+D^6+D^3+D^2+D+1, and the values ​​of the elements in the first distributed CRC interleaver are as follows:

28. The encoding method according to any one of claims 1 to 4, characterized in that: The step of performing cyclic redundancy check (CRC) encoding on the K1 information bits to obtain a first bit sequence comprises: The K1 information bits are CRC-encoded based on a CRC generator polynomial to obtain the first bit sequence, where L is equal to 11, K2 is equal to 70, the CRC generator polynomial is D^11+D^8+D^6+D^5+D^4+D^3+D^2+D+1, and the values ​​of the elements in the first distributed CRC interleaver are as follows:

29. The encoding method according to any one of claims 1 to 4, characterized in that: The step of performing cyclic redundancy check (CRC) encoding on the K1 information bits to obtain a first bit sequence comprises: The K1 information bits are CRC-encoded based on a CRC generator polynomial to obtain the first bit sequence, where L is equal to 16, K2 is equal to 100, the CRC generator polynomial is D^16+D^12+D^5+1, and the values ​​of the elements in the first distributed CRC interleaver are as follows:

30. The encoding method according to any one of claims 1 to 4, characterized in that: The step of performing cyclic redundancy check (CRC) encoding on the K1 information bits to obtain a first bit sequence comprises: The K1 information bits are CRC-encoded based on a CRC generator polynomial to obtain the first bit sequence, where L is equal to 6, K2 is equal to 70, the CRC generator polynomial is D^6+D^5+1, and the values ​​of the elements in the first distributed CRC interleaver are as follows:

31. The encoding method according to any one of claims 1 to 4, characterized in that: The step of performing cyclic redundancy check (CRC) encoding on the K1 information bits to obtain a first bit sequence comprises: The K1 information bits are CRC-encoded based on a CRC generator polynomial to obtain the first bit sequence, where L is equal to 11, K2 is equal to 70, the CRC generator polynomial is D^11+D^10+D^9+D^5+1, and the values ​​of the elements in the first distributed CRC interleaver are as follows:

32. A decoding method, characterized in that: include: Obtain a sequence to be decoded; The sequence to be decoded is checked based on a first cyclic redundancy check (CRC) generator polynomial, where the sequence to be decoded is obtained based on a second bit sequence obtained by interleaving a first bit sequence, where the first bit sequence includes K1 information bits and L CRC bits, where K1 is a positive integer and L is a positive integer less than 24; When the sequence to be decoded passes the check, deinterleave the second bit sequence using a first distributed CRC deinterleaver to obtain the K1 information bits; Among them, the first distributed CRC deinterleaver corresponds to the first distributed interleaver, the first distributed CRC interleaver includes (K2+L) elements, the values ​​of the (K2+LS)th element to the (K2+L)th element of the first distributed CRC interleaver are (K2+L-1-S) to (K2+L-1) respectively, S is an integer greater than or equal to 0 and less than or equal to L, and K2 is an integer greater than or equal to K1.

33. The encoding method according to claim 32, characterized in that The first distributed CRC interleaver is obtained by arranging L element sequences in order, any two element sequences among the L element sequences are a first element sequence and a second element sequence, the elements included in the first element sequence are obtained based on the positions of information bits associated with the first check column, the elements included in the second element sequence are obtained based on the positions of information bits associated with the second check column, the first check column and the second check column are any two columns in a check matrix obtained based on a CRC generating polynomial of length L, and when the maximum element in the first element sequence representing the position of the information bit associated with the first check column is greater than the maximum element in the second element sequence representing the position of the information bit associated with the second check column, the first element sequence in the first distributed CRC interleaver is sorted after the second element sequence.

34. A communication device, characterized in that: Comprising modules for implementing the method according to any one of claims 1 to 31.

35. A communication device, characterized in that: Comprising modules for implementing the method of claim 32 or 33.

36. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, wherein the computer program includes program instructions. When the program instructions are executed by a processor, the method according to any one of claims 1 to 33 is executed.

37. A communication device, characterized in that: The device comprises a processor, wherein the processor is configured to cause the communication device to perform the method according to any one of claims 1 to 33 when executing instructions.

38. A chip, characterized in that: include: A communication interface, used for sending and receiving signals of the chip; A processor, configured to execute computer program instructions so that a communication device including the chip executes the method according to any one of claims 1 to 33.

39. A computer program product, characterized in that When the computer program product is run on a computer, the computer is caused to execute the method according to any one of claims 1 to 33.

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