Display device and electronic device comprising same

Abstract

This display device comprises: a first conductive layer including a first uppermost layer and lower layers; a first insulating layer covering the first conductive layer; a gate insulating layer disposed on the first insulating layer; a second conductive layer which is disposed on the gate insulating layer and which includes a second uppermost layer and lower layers; a second insulating layer covering the second conductive layer; and a third conductive layer disposed on the second insulating layer, and connected to each of the first conductive layer and the second conductive layer through a first contact hole defined to pass through the first and second insulating layers so as to expose a portion of the first uppermost layer and a second contact hole defined to pass through the second insulating layer so as to expose a portion of the second uppermost layer. The third conductive layer is in contact with the portions of the first and second uppermost layers exposed by the first and second contact holes.

Description

Display device and electronic device including same

[0001] The present disclosure relates to a display device and an electronic device including the same.

[0002] A display device typically includes a plurality of pixels. Each of the pixels can emit light, and thus, the display device can display an image by combining the light emitted from the pixels.

[0003] Each of the plurality of pixels may include various components, such as transistors, wiring, and electrodes. These various components may be implemented by electrical connections between multiple conductive layers and at least one semiconductor layer, which are arranged on different layers. In this case, the aforementioned electrical connections may be achieved by forming contact holes in an insulating layer interposed between the components arranged on different layers.

[0004] The purpose of the present disclosure is to provide a display device having improved display quality by improving the reliability of conductive layers included in the display device, and an electronic device including the same.

[0005] A display device according to embodiments of the present disclosure includes: a substrate; a first conductive layer disposed on the substrate, the first conductive layer including a first uppermost layer and a first lower layer below the first uppermost layer; a first insulating layer disposed on the substrate to cover the first conductive layer; a gate insulating layer disposed on the first insulating layer; a second conductive layer disposed on the gate insulating layer, the second conductive layer including a second uppermost layer and a second lower layer below the second uppermost layer; a second insulating layer disposed on the first insulating layer to cover the second conductive layer; and a third conductive layer disposed on the second insulating layer, the third conductive layer being connected to the first conductive layer and the second conductive layer through a first contact hole and a second contact hole, respectively. The first contact hole is defined to penetrate the first insulating layer and the second insulating layer, exposing a first portion of the first uppermost layer. The second contact hole is defined to penetrate the second insulating layer, exposing a first portion of the second uppermost layer. The third conductive layer is disposed within the first contact hole and the second contact hole, and is in contact with the first portion of the first uppermost layer and the first portion of the second uppermost layer. An upper surface of the second portion of the first uppermost layer is not in contact with the third conductive layer. An upper surface of the second portion of the second uppermost layer is not in contact with the third conductive layer. A thickness of the second portion of the second uppermost layer is greater than a thickness of the first portion of the second uppermost layer. A thickness of the second portion of the first uppermost layer is greater than or equal to a thickness of the first portion of the first uppermost layer.

[0006] In one embodiment, the thickness of the second portion of the second uppermost layer may be greater than the thickness of the second portion of the first uppermost layer.

[0007] In one embodiment, the thickness of the second portion of the second uppermost layer may be from about 300 angstroms to about 800 angstroms, and the thickness of the second portion of the first uppermost layer may be from about 100 angstroms to about 700 angstroms.

[0008] In one embodiment, each of the first uppermost layer and the second uppermost layer may comprise titanium, and each of the first lowermost layer and the second lowermost layer may comprise aluminum.

[0009] In one embodiment, the difference between the depth of the first contact hole and the depth of the second contact hole may be from about 2000 angstroms to about 6000 angstroms.

[0010] In one embodiment, a first depth may be defined as the difference between the thickness of the second portion of the first uppermost layer and the thickness of the first portion of the first uppermost layer, and a second depth may be defined as the difference between the thickness of the second portion of the second uppermost layer and the thickness of the first portion of the second uppermost layer. The second depth may be greater than the first depth.

[0011] In one embodiment, the difference between the second depth and the first depth may be proportional to the ratio of the etching rate of the second uppermost layer to the average etching rate of the insulating layers between the first conductive layer and the second conductive layer in dry etching.

[0012] In one embodiment, the difference between the second depth and the first depth may be proportional to the difference between the depth of the first contact hole and the depth of the second contact hole.

[0013] In one embodiment, the thickness of the first portion of the second uppermost layer may be greater than or equal to about 10 angstroms.

[0014] In one embodiment, the contact resistance at the contact surface between the third conductive layer and the second conductive layer may be about 1 ohm or less.

[0015] In one embodiment, the display device may further include a semiconductor layer disposed between the gate insulating layer and the first insulating layer. The third conductive layer may be connected to the semiconductor layer through a contact hole defined to penetrate the second insulating layer. The semiconductor layer may include polycrystalline silicon, monocrystalline silicon, low-temperature polycrystalline silicon, amorphous silicon, or an oxide semiconductor.

[0016] In one embodiment, the thickness of the second portion of the first uppermost layer may be greater than or equal to about 3% and less than or equal to about 18% of the total thickness of the first conductive layer.

[0017] In one embodiment, the thickness of the second portion of the second uppermost layer may be greater than or equal to about 13% and less than or equal to about 20% of the total thickness of the second conductive layer, and the thickness of the first portion of the second uppermost layer may be greater than or equal to about 0.5% of the total thickness of the second conductive layer.

[0018] A display device according to embodiments of the present disclosure includes: a substrate; a first conductive layer disposed on the substrate, the first conductive layer including a first upper titanium layer and a first lower aluminum layer; a first insulating layer disposed on the substrate to cover the first conductive layer; a gate insulating layer disposed on the first insulating layer; a second conductive layer disposed on the gate insulating layer, the second conductive layer including a second upper titanium layer and a second lower aluminum layer; a second insulating layer disposed on the first insulating layer to cover the second conductive layer; and a third conductive layer disposed on the second insulating layer, the third conductive layer being connected to the first conductive layer and the second conductive layer through a first contact hole and a second contact hole, respectively. The first contact hole is defined to penetrate the first insulating layer and the second insulating layer, exposing a first portion of the first upper titanium layer. The second contact hole is defined to penetrate the second insulating layer, exposing a first portion of the second upper titanium layer. The third conductive layer is disposed within the first contact hole and the second contact hole, and contacts the first portion of the first upper titanium layer and the first portion of the second upper titanium layer. An upper surface of the second portion of the first upper titanium layer is not in contact with the third conductive layer. An upper surface of the second portion of the second upper titanium layer is not in contact with the third conductive layer. A thickness of the second portion of the second upper titanium layer is greater than a thickness of the first portion of the second upper titanium layer. A thickness of the second portion of the first upper titanium layer is greater than or equal to a thickness of the first portion of the first upper titanium layer.

[0019] In one embodiment, the thickness of the second portion of the second upper titanium layer may be greater than the thickness of the second portion of the first upper titanium layer.

[0020] In one embodiment, the thickness of the second portion of the second upper titanium layer may be from about 300 angstroms to about 800 angstroms. The thickness of the second portion of the first upper titanium layer may be from about 100 angstroms to about 700 angstroms.

[0021] In one embodiment, the difference between the depth of the first contact hole and the depth of the second contact hole may be from about 2000 angstroms to about 6000 angstroms.

[0022] In one embodiment, a first depth may be defined as the difference between the thickness of the second portion of the first upper titanium layer and the thickness of the first portion of the first upper titanium layer, and a second depth may be defined as the difference between the thickness of the second portion of the second upper titanium layer and the thickness of the first portion of the second upper titanium layer. The second depth may be greater than the first depth.

[0023] In one embodiment, the difference between the second depth and the first depth may be proportional to a ratio of an etching rate of the second upper titanium layer to an average etching rate of insulating layers between the first conductive layer and the second conductive layer in dry etching.

[0024] In one embodiment, the difference between the second depth and the first depth may be proportional to the difference between the depth of the first contact hole and the depth of the second contact hole.

[0025] In one embodiment, the thickness of the first portion of the second upper titanium layer may be greater than or equal to about 10 angstroms.

[0026] In one embodiment, the contact resistance at the contact surface between the third conductive layer and the second conductive layer may be about 1 ohm or less.

[0027] In one embodiment, the display device may further include a semiconductor layer disposed between the gate insulating layer and the first insulating layer. The third conductive layer may be connected to the semiconductor layer through a contact hole defined to penetrate the second insulating layer. The semiconductor layer may include polycrystalline silicon, monocrystalline silicon, low-temperature polycrystalline silicon, amorphous silicon, or an oxide semiconductor.

[0028] In one embodiment, the thickness of the second portion of the first upper titanium layer may be greater than or equal to about 3% and less than or equal to about 18% of the total thickness of the first conductive layer.

[0029] In one embodiment, the thickness of the second portion of the second upper titanium layer may be greater than or equal to about 13% and less than or equal to about 20% of the total thickness of the second conductive layer, and the thickness of the first portion of the second upper titanium layer may be greater than or equal to about 0.5% of the total thickness of the second conductive layer.

[0030] An electronic device according to embodiments of the present disclosure includes: a processor that provides input image data; a display device that displays an image based on the input image data; and a power supply that supplies power to the display device. The display device includes: a substrate; a first conductive layer disposed on the substrate, the first conductive layer including a first uppermost layer and a first lower layer below the first uppermost layer; a first insulating layer disposed on the substrate to cover the first conductive layer; a gate insulating layer disposed on the first insulating layer; a second conductive layer disposed on the gate insulating layer, the second conductive layer including a second uppermost layer and a second lower layer below the second uppermost layer; a second insulating layer disposed on the first insulating layer to cover the second conductive layer; and a third conductive layer disposed on the second insulating layer, the third conductive layer being connected to the first conductive layer and the second conductive layer through a first contact hole and a second contact hole, respectively. The first contact hole is defined to penetrate the first insulating layer and the second insulating layer, thereby exposing a first portion of the first uppermost layer. The second contact hole is defined to penetrate the second insulating layer and expose a first portion of the second uppermost layer. The third conductive layer is disposed within the first contact hole and the second contact hole and contacts the first portion of the first uppermost layer and the first portion of the second uppermost layer. An upper surface of the second portion of the first uppermost layer is not in contact with the third conductive layer. An upper surface of the second portion of the second uppermost layer is not in contact with the third conductive layer. A thickness of the second portion of the second uppermost layer is greater than a thickness of the first portion of the second uppermost layer. A thickness of the second portion of the first uppermost layer is greater than or equal to a thickness of the first portion of the first uppermost layer.

[0031] An electronic device according to embodiments of the present disclosure includes: a processor that provides input image data; a display device that displays an image based on the input image data; and a power supply that supplies power to the display device. The display device includes: a substrate; a first conductive layer disposed on the substrate, the first conductive layer including a first upper titanium layer and a first lower aluminum layer; a first insulating layer disposed on the substrate to cover the first conductive layer; a gate insulating layer disposed on the first insulating layer; a second conductive layer disposed on the gate insulating layer, the second conductive layer including a second upper titanium layer and a second lower aluminum layer; a second insulating layer disposed on the first insulating layer to cover the second conductive layer; and a third conductive layer disposed on the second insulating layer, the third conductive layer being connected to the first conductive layer and the second conductive layer through a first contact hole and a second contact hole, respectively. The first contact hole is defined to penetrate the first insulating layer and the second insulating layer, thereby exposing a first portion of the first upper titanium layer. The second contact hole is defined to penetrate the second insulating layer and expose a first portion of the second upper titanium layer. The third conductive layer is disposed within the first contact hole and the second contact hole and contacts the first portion of the first upper titanium layer and the first portion of the second upper titanium layer. An upper surface of the second portion of the first upper titanium layer is not in contact with the third conductive layer. An upper surface of the second portion of the second upper titanium layer is not in contact with the third conductive layer. A thickness of the second portion of the second upper titanium layer is greater than a thickness of the first portion of the second upper titanium layer. A thickness of the second portion of the first upper titanium layer is greater than or equal to a thickness of the first portion of the first upper titanium layer.

[0032] According to embodiments of the present disclosure, it is possible to effectively prevent hillocks or voids from occurring in each of the conductive layers disposed on different layers.

[0033] In addition, according to the present disclosure, when conductive layers disposed on different layers are connected (or electrically contacted) through contact holes, it is possible to effectively prevent excessive increase in contact resistance at the contact surface between the conductive layers.

[0034] FIG. 1 is a drawing for explaining a display device according to one embodiment of the present disclosure.

[0035] FIG. 2 is a circuit diagram for explaining a pixel according to one embodiment of the present disclosure.

[0036] Figure 3 is a drawing schematically illustrating various configurations included in the pixels of Figure 2.

[0037] FIG. 4 is a drawing for explaining a structure in which the configurations illustrated in FIG. 3 are electrically connected to each other by contact holes defined in an insulating layer array.

[0038] Figure 5 is an enlarged view of area A of Figure 4.

[0039] Figure 6 is an enlarged view of area B of Figure 4.

[0040] FIG. 7 is a cross-sectional view illustrating an embodiment in which the first transistor, the first capacitor, and the second capacitor of FIG. 2 are implemented by the conductive layers illustrated in FIGS. 3 to 6.

[0041] FIG. 8 is a cross-sectional view showing an embodiment in which the second transistor and the third transistor of FIG. 2 are implemented by the conductive layers shown in FIGS. 3 to 6.

[0042] Figure 9 is an enlarged view of the X1 area and X2 area of ​​Figure 7.

[0043] Figure 10 is an enlarged view of the Y1 area of ​​Figure 7 and the Y2 area of ​​Figure 8.

[0044] FIGS. 11 to 18 are drawings for explaining a method of manufacturing a display device according to one embodiment of the present disclosure.

[0045] Figure 19 is a graph illustrating the thickness of the second top layer required to prevent excessive increase in contact resistance between the second conductive layer and the third conductive layer relative to the thickness of the over-etched portion of the insulating layers.

[0046] FIG. 20 is a drawing for explaining an electronic device including a display device of the present disclosure.

[0047] Figure 21 is a drawing showing an example of the electronic device of Figure 20 implemented as a smartphone.

[0048] FIG. 22 is a drawing showing an example in which the electronic device of FIG. 20 is implemented as a tablet PC.

[0049] The present invention will be described in more detail below with reference to the accompanying drawings, which illustrate various embodiments. However, the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Like reference numerals designate like elements throughout.

[0050] When an element is said to be "on" another element, it can be understood that it is either directly on top of the other element, or that there may be intervening elements between them. Conversely, when an element is said to be "directly on" another element, there are no intervening elements.

[0051] Throughout the specification, when a part is said to be "connected" to another part, this includes not only cases where it is "directly connected" but also cases where it is "indirectly connected" with other elements in between.

[0052] The terminology used herein is used only to describe particular embodiments and is not intended to be limiting. The singular forms "a," "an," and "the" as used herein do not denote limitations on quantity and are intended to cover both the singular and the plural, unless the context clearly dictates otherwise. Thus, references in the claims to the singular form "said" or "said" may refer to one element or to a plurality of elements. For example, "an element" has the same meaning as "at least one element," unless the context clearly dictates otherwise. "At least one" should not be construed as being limited to the singular form. "Or" can mean "and / or." As used herein, the term "and / or" includes any combination of one or more of the associated listed items. "At least one of X, Y, and Z", or "at least one selected from X, Y, and Z" can be interpreted as one X, one Y, one Z, or any combination of two or more of X, Y, and Z (e.g., XYZ, XYY, YZ, ZZ). It will be understood that the term "comprises" as used herein specifies the presence of stated features, regions, integers, steps, operations, and / or elements, but does not preclude the presence or addition of one or more other features, regions, integers, steps, operations, and / or elements.

[0053] Although the terms "first," "second," "third," etc. may be used to describe various elements, regions, layers, and / or sections, such elements, regions, layers, and / or sections should not be limited by such terms. Such terms are used only to distinguish one element, region, layer, and / or section from another element, region, layer, and / or section. Thus, a "first element," "region," "layer," or "section" described below could also be referred to as a "second element," "region," "layer," or "section" without departing from the present disclosure.

[0054] Spatially relative terms such as "below," "lower," "above," and the like may be used herein for ease of description to describe the relationship of one element or feature to another element(s) or feature(s) as depicted in the drawings. It will be understood that spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the drawings. For example, if the device in the drawings were turned over, an element described as being "below" another element or feature would now be oriented "above" the other element or feature. Thus, the term "below" can encompass both the above and below orientations. The device can be oriented in other orientations (rotated 90 degrees or otherwise) and the spatially relative descriptors used herein interpreted accordingly.

[0055] As used herein, "about" or "approximately" includes the stated value and means within an acceptable range of deviation from the stated value as determined by one of ordinary skill in the art, taking into account the measurement in question and the error associated with measuring the particular quantity (i.e., limitations of the measurement system). For example, "about" can mean within one or more standard deviations, or within ±30%, 20%, 10%, or 5% of the stated value.

[0056] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. Terms defined in commonly used dictionaries should be interpreted as having a meaning consistent with the relevant art and the context of the current disclosure, and should not be interpreted in an idealized or overly formal sense unless explicitly defined herein.

[0057] The embodiments are described herein with reference to cross-sectional drawings that are schematic illustrations of idealized embodiments. Therefore, variations in the shapes of the examples are expected, for example, as a result of manufacturing techniques and / or tolerances. Therefore, the embodiments described herein should not be construed as limited to the specific shapes of the regions described herein, but should encompass, for example, variations in shape that occur during manufacturing. For example, regions illustrated or described as being flat may generally be rough or have non-linear features. Furthermore, sharp angles illustrated may be rounded. Therefore, the regions illustrated in the drawings are schematic in nature, and their shapes are not intended to illustrate the precise shapes of the regions and are not intended to limit the scope of the claims.

[0058] FIG. 1 is a drawing for explaining a display device according to one embodiment of the present disclosure.

[0059] Referring to FIG. 1, a display device (10) of one embodiment may include a timing control unit (11), a data driving unit (12), a scan driving unit (13), and a pixel unit (14).

[0060] The timing control unit (11) can receive input image data including gradations for an image (or frame). The gradations can include a first color gradation, a second color gradation, and a third color gradation. The first color gradation can be a gradation for expressing a first color, the second color gradation can be a gradation for expressing a second color, and the third color gradation can be a gradation for expressing a third color.

[0061] Additionally, the timing control unit (11) can receive a control signal for the image. The control signal can include a horizontal synchronization signal, a vertical synchronization signal, and a data enable signal.

[0062] The vertical synchronization signal may include multiple pulses, and each pulse may be generated at a point in time when the previous frame period ends and the current frame period begins. In this case, the interval between adjacent pulses of the vertical synchronization signal may correspond to one frame period.

[0063] A horizontal synchronization signal may include multiple pulses, and each pulse may be generated at a point in time that marks the end of a previous horizontal period and the beginning of a new horizontal period. In this case, the interval between adjacent pulses of the horizontal synchronization signal may correspond to one horizontal period.

[0064] The data enable signal can have an enable level for certain horizontal periods and a disable level for the remaining periods. When the data enable signal is at the enable (or active) level, color gradations can be supplied in the corresponding horizontal periods.

[0065] The timing control unit (11) can provide rendered or corrected gradations to the data driving unit (12) to match the specifications of the display device (10). In addition, the timing control unit (11) can provide a clock signal, a scan start signal, etc. to the scan driving unit (13).

[0066] The data driving unit (12) can generate data voltages to be provided to the data lines (DL1, DL2, DL3, ..., DLj, ..., DLn) using the grayscales and control signals received from the timing control unit (11). In one embodiment, for example, the data driving unit (12) can sample the grayscales using a clock signal and apply data voltages corresponding to the grayscales to the data lines (DL1 to DLn) in pixel row units. Here, n can be an integer greater than 0, and a pixel row means pixels connected to the same scan line.

[0067] The injection driving unit (13) can receive a clock signal, an injection start signal, etc. from the timing control unit (11) and generate injection signals to be provided to the injection lines (GWL1, GRL1, EML1, EMBL1, ..., GWLi, GRLi, GILi, EMLi, EMBLi, ..., GWLm, GRLm, GILm, EMLm, EMBLm). Here, m can be an integer greater than 0. In one embodiment, for example, the scan driver (13) may include a first sub-scan driver connected to the first scan lines (GWL1, ..., GWLi, ..., GWLm), a second sub-scan driver connected to the second scan lines (GRL1, ..., GRLi, ..., GRLm), a third sub-scan driver connected to the third scan lines (GIL1, ..., GILi, ..., GILm), a fourth sub-scan driver connected to the fourth scan lines (EML1, ..., EMLi, ..., EMLm), and a fifth sub-scan driver connected to the fifth scan lines (EMBL1, ..., EMBLi, ..., EMBLm).

[0068] In one embodiment, for example, the first sub-scan driver may sequentially provide scan signals having pulses of a turn-on level to the first scan lines (GWL1 to GWLm). In one embodiment, for example, the first sub-scan driver may be configured in the form of a shift register, and may generate scan signals by sequentially transmitting a scan start signal in the form of a pulse of a turn-on level to a next stage circuit under the control of a clock signal. Since the second to fifth sub-scan drivers may also be implemented in a manner substantially identical or similar to the first sub-scan driver described above, a redundant description will be omitted.

[0069] The pixel unit (14) includes pixels. A pixel (PXij) can be connected to a corresponding data line, scan line, and emission line. Here, i and j can each independently be integers greater than 0. A pixel (PXij) can mean a pixel connected to an i-th scan line and a j-th data line.

[0070] The pixel unit (14) can define a display area. That is, the area in which the pixel unit (14) is placed in the display device (10) can be defined as a display area in which an image is displayed.

[0071] The pixel unit (14) may include first pixels emitting light of a first color, second pixels emitting light of a second color, and third pixels emitting light of a third color. The first color, the second color, and the third color may be different colors. In one embodiment, for example, the first color may be one of red, green, and blue, the second color may be one of red, green, and blue other than the first color, and the third color may be a color other than the first and second colors among red, green, and blue. In addition, magenta, cyan, and yellow may be used instead of red, green, and blue as the first to third colors.

[0072] FIG. 2 is a circuit diagram for explaining a pixel according to one embodiment of the present disclosure.

[0073] Referring to FIG. 2, a pixel (PXij) of one embodiment may include a pixel circuit (PXCij) and a light emitting element (LDij) electrically connected to the pixel circuit (PXCij).

[0074] The pixel circuit (PXCij) may include at least one transistor and at least one capacitor. In one embodiment, for example, the pixel circuit (PXCij) may include transistors (T1, T2, T3, T4, T5, T6), a first capacitor (C1), and a second capacitor (C2). However, the number of transistors and the number of capacitors included in the pixel circuit (PXCij) are not limited to the above-described description. The pixel circuit (PXCij) may include more or fewer transistors and / or capacitors to suit its operating characteristics.

[0075] Hereinafter, an embodiment in which all transistors of the pixel circuit (PXCij) are configured as N-type transistors will be described. However, those skilled in the art will be able to design a circuit configured as P-type transistors by changing the polarity of the voltage applied to the gate terminal. Similarly, those skilled in the art will be able to design a circuit configured as a combination of P-type transistors and N-type transistors. Here, a P-type transistor is a general term for a transistor in which the amount of current increases when the voltage difference between the gate electrode and the source electrode increases in the negative direction, and an N-type transistor is a general term for a transistor in which the amount of current increases when the voltage difference between the gate electrode and the source electrode increases in the positive direction. The transistor can be configured in various forms such as a TFT (thin film transistor), a FET (field effect transistor), and a BJT (bipolar junction transistor).

[0076] In one embodiment, the transistors (T1, T2, T3, T4, T5, T6) may be configured as N-type oxide thin film transistors. In another embodiment, the transistors (T1, T2, T3, T4, T5, T6) may be P-type silicon thin film transistors. In yet another embodiment, some of the transistors (T1, T2, T3, T4, T5, T6) may be N-type oxide thin film transistors and others may be P-type silicon thin film transistors.

[0077] The oxide thin film transistor may be a low temperature polycrystalline oxide (LTPO) thin film transistor in which the semiconductor layer includes an oxide. However, this is merely exemplary, and N-type transistors are not limited thereto. In one embodiment, for example, the semiconductor layer included in the N-type transistor may include an inorganic semiconductor (e.g., amorphous silicon, monocrystalline silicon, polysilicon), an organic semiconductor, or the like. The silicon thin film transistor may be a low temperature poly-silicon (LTPS) thin film transistor in which the semiconductor layer includes amorphous silicon, monocrystalline silicon, polysilicon, or the like.

[0078] The first transistor (T1) may include a first electrode connected to the second electrode of the fifth transistor (T5), and a second electrode connected to the second node (N2). The first transistor (T1) may control the amount of driving current flowing from the first power line (ELVDDL) to the second power line (ELVSSL). Therefore, the first transistor (T1) may be referred to as a driving transistor.

[0079] In one embodiment, the first transistor (T1) may have a double gate structure including a first gate electrode connected to a first node (N1) and a second gate electrode connected to a second node (N2). In the above-described embodiment, the first gate electrode of the first transistor (T1) may be referred to as a top gate electrode, and the second gate electrode of the first transistor (T1) may be referred to as a bottom gate electrode. The second gate electrode of the first transistor (T1) may be for adjusting the characteristics of the output current versus the input voltage of the first transistor (T1). In one embodiment, for example, the first transistor (T1) mainly operates in a saturation state. In the absence of the second gate electrode of the first transistor (T1), the magnitude of the output current may vary depending on a change in the drain-source voltage even though the gate-source voltage is the same. According to the present embodiment, the characteristics of the first transistor (T1) are adjusted to be insensitive to changes in the drain-source voltage, so that the first transistor (T1) can output substantially the same current for the same gate-source voltage.

[0080] The second transistor (T2) may include a gate electrode connected to the first scan line (GWLi), a first electrode connected to the data line (DLj), and a second electrode connected to the first node (N1). The second transistor (T2) may receive a data voltage applied to the data line (DLj). Therefore, the second transistor (T2) may be referred to as a data write transistor.

[0081] The third transistor (T3) may include a gate electrode connected to the second scan line (GRLi), a first electrode connected to the reference voltage line (VREFL) to receive a reference voltage, and a second electrode connected to the first node (N1). The third transistor (T3) may apply the reference voltage to the first node (N1) to initialize the voltage of the first node (N1) to the reference voltage. Therefore, the third transistor (T3) may be referred to as a first initialization transistor.

[0082] The fourth transistor (T4) may include a gate electrode connected to the third scan line (GILi), a first electrode connected to the initialization voltage line (VINTL) to receive an initialization voltage, and a second electrode connected to the third node (N3). The fourth transistor (T4) may apply the initialization voltage to the third node (N3) to initialize the voltage of the third node (N3) to the initialization voltage. Therefore, the fourth transistor (T4) may be referred to as a second initialization transistor.

[0083] The fifth transistor (T5) may include a gate electrode connected to the fourth scan line (EMLi), a first electrode connected to the first power line (ELVDDL), and a second electrode connected to the first electrode of the first transistor (T1). The fifth transistor (T5) may control the opening and closing of a driving current path connected from the first power line (ELVDDL) to the second power line (ELVSSL). Therefore, the fifth transistor (T5) may be referred to as a first light emission control transistor.

[0084] The sixth transistor (T6) may include a gate electrode connected to the fifth scan line (EMBLi), a first electrode connected to the second node (N2), and a second electrode connected to the third node (N3). The sixth transistor (T6) may control the opening and closing of a driving current path connected from the first power line (ELVDDL) to the second power line (ELVSSL). Therefore, the sixth transistor (T6) may be referred to as a second light emission control transistor.

[0085] The first capacitor (C1) may include a first terminal connected to a first node (N1) and a second terminal connected to a second node (N2). The second capacitor (C2) may include a first terminal connected to a first power line (ELVDDL) and a second terminal connected to a second node (N2).

[0086] The light-emitting element (LDij) may include an anode electrode connected to a third node (N3) and a cathode electrode connected to a second power line (ELVSSL). The light-emitting element (LDij) may be a light-emitting diode. The light-emitting element (LDij) may be composed of an organic light-emitting diode, an inorganic light-emitting diode, a quantum dot / well light-emitting diode, or the like. In the present embodiment, only one light-emitting element (LDij) is provided in each pixel, but in other embodiments, a plurality of light-emitting elements may be provided in each pixel. In the above-described embodiments, the plurality of light-emitting elements may be connected in series, in parallel, in series-parallel, or the like. The light-emitting element (LDij) of each pixel may emit light in one of a first color, a second color, and a third color.

[0087] A first power voltage may be applied to a first power line (ELVDDL), and a second power voltage may be applied to a second power line (ELVSSL). In one embodiment, for example, the first power voltage may be greater than the second power voltage.

[0088] Figure 3 is a drawing schematically illustrating various configurations included in the pixels of Figure 2.

[0089] Referring to FIG. 3, a pixel (PXij) may include a substrate (SUB), an insulating layer array (INSA), a first conductive layer (CDL1), a second conductive layer (CDL2), a semiconductor layer (SCL), a third conductive layer (CDL3), a first via layer (VIA1), a fourth conductive layer (CDL4), a second via layer (VIA2), and a light emitting element layer (LDL).

[0090] The substrate (SUB) may be rigid or flexible. In one embodiment, for example, the substrate (SUB) may comprise glass or plastic. The substrate (SUB) may serve as a base layer that provides a base for components placed on the substrate (SUB).

[0091] The insulating layer array (INSA) may include a plurality of insulating layers sequentially stacked along a first direction (DR1). Here, the first direction (DR1) may be a thickness direction of the substrate (SUB). In one embodiment, each of the plurality of insulating layers included in the insulating layer array (INSA) may be an inorganic insulating layer including at least one selected from various known inorganic insulating materials. In one embodiment, each of the plurality of insulating layers included in the insulating layer array (INSA) may have a single-layer or multi-layer structure.

[0092] A first via layer (VIA1) and a second via layer (VIA2) may be sequentially stacked along a first direction (DR1) on an insulating layer array (INSA). In one embodiment, each of the first via layer (VIA1) and the second via layer (VIA2) may be an organic insulating layer including at least one selected from various organic insulating materials known in the art, and may have a single-layer or multi-layer structure. However, the embodiments of the present disclosure are not limited thereto. In one embodiment, each of the first via layer (VIA1) and the second via layer (VIA2) may have a bilayer structure including an inorganic insulating layer and an organic insulating layer.

[0093] A fourth conductive layer (CDL4) may be disposed between the first via layer (VIA1) and the second via layer (VIA2). The fourth conductive layer (CDL4) may be disposed over the first via layer (VIA1), and the second via layer (VIA2) may cover the fourth conductive layer (CDL4) over the first via layer (VIA1).

[0094] A third conductive layer (CDL3) may be disposed between the insulator layer array (INSA) and the first via layer (VIA1). The third conductive layer (CDL3) may be disposed over the insulator layer array (INSA), and the first via layer (VIA1) may cover the third conductive layer (CDL3) over the insulator layer array (INSA).

[0095] The first conductive layer (CDL1), the semiconductor layer (SCL), and the second conductive layer (CDL2) may be disposed below the third conductive layer (CDL3). Each of the first conductive layer (CDL1), the semiconductor layer (SCL), and the second conductive layer (CDL2) may be disposed above (or below) any one of the plurality of insulating layers included in the insulating layer array (INSA).

[0096] In one embodiment, the insulating layer array (INSA) may include a first insulating layer (INS1), a gate insulating layer (GI), and a second insulating layer (INS2). In one embodiment, the first conductive layer (CDL1) may be disposed on a substrate (SUB), and the first insulating layer (INS1) may cover the first conductive layer (CDL1) over the substrate (SUB). In one embodiment, the semiconductor layer (SCL) may be disposed on the first insulating layer (INS1). In one embodiment, the gate insulating layer (GI) may be disposed over the semiconductor layer (SCL) and the first insulating layer (INS1). In one embodiment, the second conductive layer (CDL2) may be disposed on the gate insulating layer (GI), and the second insulating layer (INS2) may cover the semiconductor layer (SCL), the gate insulating layer (GI), and the second conductive layer (CDL2) over the first insulating layer (INS1).

[0097] In one embodiment, the first conductive layer (CDL1) may include a first lower conductive layer (BML1) and a second lower conductive layer (BML2) disposed on a different layer from the first lower conductive layer (BML1). In this case, in one embodiment, the first insulating layer (INS1) may include a first first insulating layer (hereinafter referred to as a “1-1 insulating layer”) (INS1-1) and a first second insulating layer (hereinafter referred to as a “1-2 insulating layer”) (INS1-2) disposed on the 1-1 insulating layer (INS1-1). The first lower conductive layer (BML1) may be disposed on the substrate (SUB), and the 1-1 insulating layer (INS1-1) may cover the first lower conductive layer (BML1) on the substrate (SUB). The second lower conductive layer (BML2) may be disposed on the first-first insulating layer (INS1-1), and the first-second insulating layer (INS1-2) may cover the second lower conductive layer (BML2) on the first-first insulating layer (INS1-1). In this way, the first conductive layer (CDL1) may include two or more conductive layers disposed at different layers below the second conductive layer (CDL2).

[0098] The first to fourth conductive layers (CDL1, CDL2, CDL3, CDL4) and the semiconductor layer (SCL) can constitute a pixel circuit (PXCij). In one embodiment, for example, each of the first to fourth conductive layers (CDL1, CDL2, CDL3, CDL4) and the semiconductor layer (SCL) can include portions patterned into preset shapes, as illustrated in FIG. 3. Transistors (T1 to T6 in FIG. 2), wirings (GWLi, GRLi, GILi, EMLi, EMBLi, ELVDDL, ELVSSL, and DLj in FIG. 2), capacitors (C1, C2 in FIG. 2), electrodes (or wirings) connecting the wirings to the transistors and / or the capacitors, etc. can be implemented (or defined) by the patterned portions of the first to fourth conductive layers (CDL1, CDL2, CDL3, CLD4). In this case, according to the electrical connection relationship of each component in the circuit diagram illustrated in Fig. 2, the conductive layers (CDL1, CDL2, CDL3, CDL4) and the semiconductor layer (SCL) may be electrically connected to each other through contact holes defined in the insulating layers (INSA, VIA1, VIA2). The electrical connection through these contact holes will be described later with reference to Fig. 4.

[0099] The light emitting element layer (LDL) may be disposed on the second via layer (VIA2). The light emitting element layer (LDL) may include a light emitting element (LDij). The light emitting element (LDij) may be electrically connected to the pixel circuit (PXCij). In one embodiment, for example, the light emitting element (LDij) may be electrically connected to the fourth conductive layer (CDL4) through a contact hole defined (or formed) in the second via layer (VIA2), thereby being electrically connected to the pixel circuit (PXCij).

[0100] In Fig. 3, an embodiment in which a pixel circuit (PXCij) is implemented by four conductive layers (CDL1, CDL2, CDL3, CDL4) and one semiconductor layer (SCL) is exemplarily described. However, the number of conductive layers and the number of semiconductor layers for implementing the pixel circuit (PXCij) are not limited to the above-described description. In addition, in Fig. 3, an embodiment in which a semiconductor layer (SCL) is disposed between a first conductive layer (CDL1) and a second conductive layer (CDL2) is exemplarily described. However, the arrangement of the semiconductor layer (SCL) is not limited to the above-described description.

[0101] A person skilled in the art will be able to design the pixel circuit (PXCij) by appropriately modifying the number of conductive layers and semiconductor layers, and the arrangement of the conductive layers and semiconductor layers, so as to match the operating characteristics of the pixel circuit (PXCij). For example, a person skilled in the art will be able to design the pixel circuit (PXCij) by additionally arranging at least one conductive layer and / or at least one semiconductor layer between the first conductive layer (CDL1) and the semiconductor layer (SCL).

[0102] FIG. 4 is a drawing for explaining a structure in which the configurations illustrated in FIG. 3 are electrically connected to each other by contact holes defined in an insulating layer array. FIG. 5 is an enlarged view of area A of FIG. 4. FIG. 6 is an enlarged view of area B of FIG. 4.

[0103] Referring to FIGS. 3 to 6, in one embodiment of the present disclosure, the conductive layers (CDL1, CDL2) may have a multilayer structure, and the upper surfaces of the conductive layers (CDL1, CDL2) may be at least partially covered by insulating layers included in the insulating layer array (INSA).

[0104] In one embodiment, as illustrated in FIG. 6, the first conductive layer (CDL1) may include a first uppermost layer (UL1) and a first lower layer (LL1) disposed below the first uppermost layer (UL1) and covered by the first uppermost layer (UL1). In one embodiment, for example, the first conductive layer (CDL1) may have a bilayer structure of titanium (Ti) / aluminum (Al). In this case, the first uppermost layer (UL1) may be referred to as a first upper titanium layer, and the first lower layer (LL1) may be referred to as a first lower aluminum layer. In another embodiment, for example, the first conductive layer (CDL1) may have a trilayer structure of titanium (Ti) / aluminum (Al) / titanium (Ti). In this case, the first uppermost layer (UL1) may be referred to as a first upper titanium layer, the first lowermost layer (LL1) may be referred to as a first lower aluminum layer, and a lower titanium layer (not shown) may be disposed under the first lowermost layer (LL1). However, the embodiments are not limited thereto. The embodiments of the present disclosure may be applied to various cases, for example, where the first conductive layer (CDL1) includes a lower aluminum layer (e.g., the first lowermost layer (LL1)) covered by the uppermost layer (e.g., the first uppermost layer (UL1)), and the uppermost layer may be disposed on the lower aluminum layer to serve as a capping layer that prevents hillocks or voids from occurring in the lower aluminum layer.

[0105] In one embodiment, when the first conductive layer (CDL1) has a triple-layer structure of titanium (Ti) / aluminum (Al) / titanium (Ti) as described above, the thickness (t1) of the first uppermost layer (UL1), which is the first upper titanium layer, may be about 100 angstroms to about 700 angstroms, the thickness of the first lower layer (LL1), which is the first lower aluminum layer, may be about 2000 angstroms to about 4000 angstroms, and the thickness of the lower titanium layer disposed under the first lower layer (LL1) may be about 100 angstroms to about 200 angstroms.

[0106] In this case, in one embodiment, the thickness (t1) of the first uppermost layer (UL1) of the first lower conductive layer (BML1) may be from about 100 angstroms to about 700 angstroms, or from about 300 angstroms to about 500 angstroms, and the thickness of the first lower layer (LL1) of the first lower conductive layer (BML1) may be from about 2000 angstroms to about 3000 angstroms, or from about 2400 angstroms to about 2600 angstroms. Additionally, in one embodiment, the thickness (t1) of the first uppermost layer (UL1) of the second lower conductive layer (BML2) may be from about 100 angstroms to about 700 angstroms, or from about 300 angstroms to about 500 angstroms, and the thickness of the first lower layer (LL1) of the second lower conductive layer (BML2) may be from about 3000 angstroms to about 4000 angstroms, or from about 3400 angstroms to about 3600 angstroms.

[0107] In one embodiment, when the first lower conductive layer (BML1) has a triple layer structure of titanium (Ti) / aluminum (Al) / titanium (Ti), the thickness (t1) of the first uppermost layer (UL1) of the first lower conductive layer (BML1) may be about 200 angstroms to about 400 angstroms, about 250 angstroms to about 350 angstroms, or about 300 angstroms.

[0108] In the above-described embodiment, the thickness (t1) of the first uppermost layer (UL1) of the first lower conductive layer (BML1) may be about 5% or more and about 14% or less of the total thickness of the first lower conductive layer (BML1). When the thickness (t1) of the first uppermost layer (UL1) of the first lower conductive layer (BML1) satisfies the above-described numerical range, the film quality of the first uppermost layer (UL1) can be improved because the first uppermost layer (UL1) is not formed to be excessively thin, and the risk of undercut occurrence can be reduced and mass productivity can be improved because the first uppermost layer (UL1) is not formed to be excessively thick.

[0109] In addition, in the above-described embodiment, the thickness of the first lower layer (LL1) of the first lower conductive layer (BML1) may be about 81% or more and about 91% or less of the total thickness of the first lower conductive layer (BML1). When the thickness of the first lower layer (LL1) of the first lower conductive layer (BML1) satisfies the above-described numerical range, since the total thickness of the first lower conductive layer (BML1) is not formed excessively thick, the problem of components disposed on the first lower conductive layer (BML1) being disconnected due to a step generated by the first lower conductive layer (BML1) may not occur.

[0110] In addition, in the above-described embodiment, the thickness of the lower titanium layer of the first lower conductive layer (BML1) may be about 4.5% or more and about 5.4% or less of the total thickness of the first lower conductive layer (BML1). When the thickness of the lower titanium layer of the first lower conductive layer (BML1) satisfies the above-described numerical range, the film quality of the lower titanium layer may be improved, the risk of undercut occurrence may be reduced, and mass productivity may be improved.

[0111] In one embodiment, when the first lower conductive layer (BML1) has a triple layer structure of titanium (Ti) / aluminum (Al) / titanium (Ti), the thickness (t1) of the first uppermost layer (UL1) of the first lower conductive layer (BML1) may be about 400 angstroms to about 600 angstroms, about 450 angstroms to about 550 angstroms, or about 500 angstroms.

[0112] In the above-described embodiment, the thickness (t1) of the first uppermost layer (UL1) of the first lower conductive layer (BML1) may be about 13% or more and about 18% or less of the total thickness of the first lower conductive layer (BML1). When the thickness (t1) of the first uppermost layer (UL1) of the first lower conductive layer (BML1) satisfies the above-described numerical range, the film quality of the first uppermost layer (UL1) can be improved because the first uppermost layer (UL1) is not formed to be excessively thin, and the risk of undercut occurrence can be reduced and mass productivity can be improved because the first uppermost layer (UL1) is not formed to be excessively thick.

[0113] In addition, in the above-described embodiment, the thickness of the first lower layer (LL1) of the first lower conductive layer (BML1) may be about 77% or more and about 83% or less of the total thickness of the first lower conductive layer (BML1). When the thickness of the first lower layer (LL1) of the first lower conductive layer (BML1) satisfies the above-described numerical range, since the total thickness of the first lower conductive layer (BML1) is not formed to be excessively thick, the problem of components disposed on the first lower conductive layer (BML1) being disconnected due to a step generated by the first lower conductive layer (BML1) may not occur.

[0114] In addition, in the above-described embodiment, the thickness of the lower titanium layer of the first lower conductive layer (BML1) may be about 4.2% or more and about 5.1% or less of the total thickness of the first lower conductive layer (BML1). When the thickness of the lower titanium layer of the first lower conductive layer (BML1) satisfies the above-described numerical range, the film quality of the lower titanium layer may be improved, the risk of undercut occurrence may be reduced, and mass productivity may be improved.

[0115] In one embodiment, when the second lower conductive layer (BML2) has a triple layer structure of titanium (Ti) / aluminum (Al) / titanium (Ti), the thickness (t1) of the first uppermost layer (UL1) of the second lower conductive layer (BML2) may be about 200 angstroms to about 400 angstroms, about 250 angstroms to about 350 angstroms, or about 300 angstroms.

[0116] In the above-described embodiment, the thickness (t1) of the first uppermost layer (UL1) of the second lower conductive layer (BML2) may be about 3% or more and about 11% or less of the total thickness of the second lower conductive layer (BML2). When the thickness (t1) of the first uppermost layer (UL1) of the second lower conductive layer (BML2) satisfies the above-described numerical range, the film quality of the first uppermost layer (UL1) can be improved because the first uppermost layer (UL1) is not formed to be excessively thin, and the risk of undercut occurrence can be reduced and mass productivity can be improved because the first uppermost layer (UL1) is not formed to be excessively thick.

[0117] In addition, in the above-described embodiment, the thickness of the first lower layer (LL1) of the second lower conductive layer (BML2) may be about 85% or more and about 94% or less of the total thickness of the second lower conductive layer (BML2). When the thickness of the first lower layer (LL1) of the second lower conductive layer (BML2) satisfies the above-described numerical range, since the total thickness of the second lower conductive layer (BML2) is not formed to be excessively thick, the problem of components disposed on the second lower conductive layer (BML2) being disconnected due to the step generated by the second lower conductive layer (BML2) may not occur.

[0118] In addition, in the above-described embodiment, the thickness of the lower titanium layer of the second lower conductive layer (BML2) may be about 3.1% or more and about 4.3% or less of the total thickness of the second lower conductive layer (BML2). When the thickness of the lower titanium layer of the second lower conductive layer (BML2) satisfies the above-described numerical range, the film quality of the lower titanium layer may be improved, the risk of undercut occurrence may be reduced, and mass productivity may be improved.

[0119] In one embodiment, when the second lower conductive layer (BML2) has a triple layer structure of titanium (Ti) / aluminum (Al) / titanium (Ti), the thickness (t1) of the first uppermost layer (UL1) of the second lower conductive layer (BML2) may be about 400 angstroms to about 600 angstroms, about 450 angstroms to about 550 angstroms, or about 500 angstroms.

[0120] In the above-described embodiment, the thickness (t1) of the first uppermost layer (UL1) of the second lower conductive layer (BML2) may be about 9% or more and about 14% or less of the total thickness of the second lower conductive layer (BML2). When the thickness (t1) of the first uppermost layer (UL1) of the second lower conductive layer (BML2) satisfies the above-described numerical range, the film quality of the first uppermost layer (UL1) can be improved because the first uppermost layer (UL1) is not formed to be excessively thin, and the risk of undercut occurrence can be reduced and mass productivity can be improved because the first uppermost layer (UL1) is not formed to be excessively thick.

[0121] In addition, in the above-described embodiment, the thickness of the first lower layer (LL1) of the second lower conductive layer (BML2) may be about 82% or more and about 88% or less of the total thickness of the second lower conductive layer (BML2). When the thickness of the first lower layer (LL1) of the second lower conductive layer (BML2) satisfies the above-described numerical range, since the total thickness of the second lower conductive layer (BML2) is not formed excessively thick, the problem of components disposed on the second lower conductive layer (BML2) being disconnected due to the step generated by the second lower conductive layer (BML2) may not occur.

[0122] In addition, in the above-described embodiment, the thickness of the lower titanium layer of the second lower conductive layer (BML2) may be about 2.9% or more and about 4.1% or less of the total thickness of the second lower conductive layer (BML2). When the thickness of the lower titanium layer of the second lower conductive layer (BML2) satisfies the above-described numerical range, the film quality of the lower titanium layer may be improved, the risk of undercut occurrence may be reduced, and mass productivity may be improved.

[0123] In one embodiment, the second conductive layer (CDL2) may include a second uppermost layer (UL2) and a second lower layer (LL2) disposed below and covered by the second uppermost layer (UL2), as illustrated in FIG. 5. In one embodiment, for example, the second conductive layer (CDL2) may have a bilayer structure of titanium (Ti) / aluminum (Al). In the above-described embodiment, the second uppermost layer (UL2) may be referred to as a second upper titanium layer, and the second lower layer (LL2) may be referred to as a second lower aluminum layer. In another embodiment, for example, the second conductive layer (CDL2) may have a trilayer structure of titanium (Ti) / aluminum (Al) / titanium (Ti). In this case, the second uppermost layer (UL2) may be referred to as a second upper titanium layer, the second lowermost layer (LL2) may be referred to as a second lower aluminum layer, and a lower titanium layer (not shown) may be disposed under the second lowermost layer (LL2). However, the embodiments are not limited thereto. The embodiments of the present disclosure may be applied to various cases, for example, where the second conductive layer (CDL2) includes a lower aluminum layer (e.g., the second lowermost layer (LL2)) covered by the uppermost layer (e.g., the second uppermost layer (UL2)), and the uppermost layer may be disposed on the lower aluminum layer to serve as a capping layer that prevents hillocks or voids from occurring in the lower aluminum layer.

[0124] In one embodiment, when the second conductive layer (CDL2) has a triple layer structure of titanium (Ti) / aluminum (Al) / titanium (Ti) as described above, the thickness (t2) of the second uppermost layer (UL2), which is the second upper titanium layer, may be about 300 angstroms to about 800 angstroms, or about 450 angstroms to about 650 angstroms, the thickness of the second lower layer (LL2), which is the second lower aluminum layer, may be about 2000 angstroms to about 3000 angstroms, or about 2400 angstroms to about 2600 angstroms, and the thickness of the lower titanium layer disposed under the second lower layer (LL2) may be about 100 angstroms to about 200 angstroms.

[0125] In one embodiment, when the second conductive layer (CDL2) has a triple layer structure of titanium (Ti) / aluminum (Al) / titanium (Ti), the thickness (t2) of the second uppermost layer (UL2) of the second conductive layer (CDL2) may be about 300 angstroms to about 800 angstroms, about 450 angstroms to about 550 angstroms, or about 500 angstroms.

[0126] In the above-described embodiment, the thickness (t2) of the second uppermost layer (UL2) may be about 13% or more and about 20% or less of the total thickness of the second conductive layer (CDL2). When the thickness (t2) of the second uppermost layer (UL2) satisfies the above-described numerical range, the film quality of the second uppermost layer (UL2) can be improved because the second uppermost layer (UL2) is not formed to be excessively thin, and the risk of undercut occurrence can be reduced and mass productivity can be improved because the second uppermost layer (UL2) is not formed to be excessively thick.

[0127] In addition, in the above-described embodiment, the thickness of the second lower layer (LL2) may be about 75% or more and about 83% or less of the total thickness of the second conductive layer (CDL2). When the thickness of the second lower layer (LL2) satisfies the above-described numerical range, since the total thickness of the second conductive layer (CDL2) is not formed to be excessively thick, the problem of components disposed on the second conductive layer (CDL2) being disconnected due to the step generated by the second conductive layer (CDL2) may not occur.

[0128] In addition, in the above-described embodiment, the thickness of the lower titanium layer of the second conductive layer (CDL2) may be about 4.2% or more and about 5% or less of the total thickness of the second conductive layer (CDL2). When the thickness of the lower titanium layer of the second conductive layer (CDL2) satisfies the above-described numerical range, the film quality of the lower titanium layer may be improved, the risk of undercut occurrence may be reduced, and mass productivity may be improved.

[0129] In one embodiment, each of the third conductive layer (CDL3) and the fourth conductive layer (CDL4) may be configured substantially identically (or similarly) to the first conductive layer (CDL1) and the second conductive layer (CDL2) described above, but embodiments of the present disclosure are not limited thereto. In another embodiment, for example, at least one of the third conductive layer (CDL3) and the fourth conductive layer (CDL4) may have a single-layer structure comprising one of various conductive materials known in the art.

[0130] In one embodiment of the present disclosure, the third conductive layer (CDL3) may be connected to (or electrically contacted with) each of the first conductive layer (CDL1), the second conductive layer (CDL2), and the semiconductor layer (SCL).

[0131] In one embodiment, the third conductive layer (CDL3) can be connected to the first conductive layer (CDL1) through a first contact hole (CNT1) that penetrates the insulating layer array (INSA) and exposes at least a portion of the first conductive layer (CDL1). In one embodiment, the first contact hole (CNT1) can be defined (or formed) to penetrate the second insulating layer (INS2) and the first insulating layer (INS1). In the above-described embodiment, as illustrated in FIG. 6, the first contact hole (CNT1) can expose a first portion (p11) (hereinafter, referred to as “the 1-1 portion”) of the first uppermost layer (UL1), and the third conductive layer (CDL3) can be arranged to fill the first contact hole (CNT1) and be connected (or electrically contacted) with the 1-1 portion (p11). Here, the second portion (p12) (hereinafter referred to as “the first-second portion”) of the first uppermost layer (UL1) may be a portion other than the first-first portion (p11). In one embodiment, the upper surface of the first-second portion (p12) may not be in contact with the third conductive layer (CDL3) and may be covered by the first insulating layer (INS1).

[0132] In one embodiment, the third conductive layer (CDL3) can be connected to the second conductive layer (CDL2) via a second contact hole (CNT2) that penetrates the insulating layer array (INSA) and exposes at least a portion of the second conductive layer (CDL2). In one embodiment, the second contact hole (CNT2) can be defined (or formed) to penetrate the second insulating layer (INS2). In this case, as illustrated in FIG. 5, the second contact hole (CNT2) can expose a first portion (p21) (hereinafter, referred to as “the second-first portion”) of the second uppermost layer (UL2), and the third conductive layer (CDL3) can be arranged to fill the second contact hole (CNT2) and be connected (or electrically contacted) with the second-first portion (p21). Here, the second portion (p22) of the second uppermost layer (UL2) (hereinafter referred to as “the second-1 portion”) may be a portion other than the second-1 portion (p21). In one embodiment, the upper surface of the second-2 portion (p22) may not be in contact with the third conductive layer (CDL3) and may be covered by the second insulating layer (INS2).

[0133] In one embodiment, the third conductive layer (CDL3) can be connected to the semiconductor layer (SCL) via a third contact hole (CNT3) that penetrates the insulating layer array (INSA) and exposes at least a portion of the semiconductor layer (SCL). In one embodiment, the third contact hole (CNT3) can be defined (or formed) so as to penetrate the second insulating layer (INS2). In this case, the third conductive layer (CDL3) can be arranged to fill the third contact hole (CNT3) and be connected (or electrically contacted) with the semiconductor layer (SCL).

[0134] In one embodiment, contact holes (CNT1, CNT2, CNT3) formed (or defined) in the insulating layer array (INSA) can be formed simultaneously at different locations through a single mask process (e.g., the same dry etching process using a single mask), and then a third conductive layer (CDL3) is formed on the insulating layer array (INSA) to fill the contact holes (CNT1, CNT2, CNT3), thereby connecting (or contacting) the first conductive layer (CDL1), the second conductive layer (CDL2), and the semiconductor layer (SCL). This single mask process will be described in detail below with reference to FIGS. 11 to 18.

[0135] When the single mask process described above is performed, since the first conductive layer (CDL1) and the second conductive layer (CDL2) are arranged in different layers (or at different heights), the depth (D1) of the first contact hole (CNT1) in the first direction (DR1) may be formed to be greater than the depth (D2) of the second contact hole (CNT2) in the first direction (DR1). In one embodiment, for example, the difference between the depth (D1) of the first contact hole (CNT1) and the depth (D2) of the second contact hole (CNT2) may be about 2000 angstroms to about 6000 angstroms. Accordingly, when the single mask process described above is performed, the second uppermost layer (UL2) of the second conductive layer (CDL2) may be relatively over-etched compared to the first uppermost layer (UL1) of the first conductive layer (CDL1). In this case, if the thickness of the second uppermost layer (UL2) in the first direction (DR1) is set to be substantially the same as (or similar to) the thickness of the first uppermost layer (UL1) in the first direction (DR1) before performing the aforementioned single mask process, the second lower layer (LL2) may be exposed through the second contact hole (CNT2) as the second uppermost layer (UL2) is over-etched while performing the aforementioned single mask process. When the second lower layer (LL2) is exposed, the contact resistance at the contact surface between the second conductive layer (CDL2) and the third conductive layer (CDL3) may increase due to oxidation of the second lower layer (LL2) (e.g., an aluminum layer), which may deteriorate the display quality of the display device. In this way, when the second uppermost layer (UL2) is over-etched and the second lower layer (LL2) is exposed through the second contact hole (CNT2), the contact resistance may be, for example, about 3.57 ohms.

[0136] In order to prevent the aforementioned contact resistance from increasing excessively, in one embodiment, the thickness (t2) of the 2-2 portion (p22) may be greater than the thickness (t1) of the 1-2 portion (p12). That is, the thickness of the uppermost layer (e.g., the 2-2 portion (p22) of the second uppermost layer (UL2)) of the conductive layer (e.g., the second conductive layer (CDL2)) which is closer to the third conductive layer (CDL3) in the first direction (DR1) may be set to be relatively large. Accordingly, in the aforementioned single mask process, it is possible to effectively prevent the uppermost layer included in each conductive layer from being over-etched and the lower layer under the uppermost layer from being exposed.

[0137] In one embodiment, as illustrated in FIG. 5, the thickness (t2) of the 2-2 portion (p22) in the first direction (DR1) may be greater than the thickness (t2') of the 2-1 portion (p21) in the first direction (DR1). In this case, a second recess (GR2) having a depth (d2) corresponding to the difference (i.e., t2-t2') between the thickness (t2) of the 2-2 portion (p22) and the thickness (t2') of the 2-1 portion (p21) may be defined (or formed) in the second uppermost layer (UL2).

[0138] This may be because, when the single mask process described above is performed, even if the formation of the second contact hole (CNT2) is completed, dry etching may be performed for an additional time to complete the formation of the first contact hole (CNT1) having a depth (D1) greater than the depth (D2) of the second contact hole (CNT2), and during the additional time, damage due to the dry etching may accumulate in the second conductive layer (CDL2) positioned closer to the third conductive layer (CDL3) than to the first conductive layer (CDL1), resulting in over-etching of the second uppermost layer (UL2). That is, when the single mask process described above is performed, the over-etched portion of the second uppermost layer (UL2) may be a portion corresponding to the second recessed portion (GR2).

[0139] In one embodiment, as illustrated in FIG. 6, the thickness (t1) of the 1-2nd portion (p12) in the first direction (DR1) may be greater than the thickness (t1') of the 1-1st portion (p11) in the first direction (DR1). In this case, a first recessed portion (GR1) having a depth (d1) corresponding to the difference (i.e., t1-t1') between the thickness (t1) of the 1-2nd portion (p12) and the thickness (t1') of the 1-1st portion (p11) may be defined (or formed) in the first uppermost layer (UL1). Here, when the single mask process described above is performed, the over-etched portion of the first uppermost layer (UL1) may be a portion corresponding to the first recessed portion (GR1).

[0140] In another embodiment, the 1-1 portion (p11) may not be over-etched when performing the aforementioned single mask process. In one embodiment, for example, by appropriately controlling the time for which dry etching is performed when performing the aforementioned single mask process, the first uppermost layer (UL1) may be substantially free from damage caused by the dry etching. In this case, the first recessed portion (GR1) may not be defined (or formed) in the first uppermost layer (UL1). In this embodiment, the thickness (t1') of the 1-1 portion (p11) may be substantially the same as the thickness (t1) of the 1-2 portion (p12).

[0141] In one embodiment, because the second top layer (UL2) may be over-etched compared to the first top layer (UL1) as described above (or, because the second top layer (UL2) receives more cumulative damage from dry etching than the first top layer (UL1), the depth (d2) of the second recess (GR2) defined in the second top layer (UL2) may be greater than the depth (d1) of the first recess (GR1) defined in the first top layer (UL1).

[0142] In one embodiment, the difference (i.e., d2-d1) between the depth (d2) of the second recessed portion (GR2) and the depth (d1) of the first recessed portion (GR1) may be proportional to the ratio (i.e., ER1:ER2) of the etching rate (ER1) of the second uppermost layer (UL2) to the average etching rate (ER2) of the over-etched portion of the insulating layers (e.g., the second insulating layer (INS2) and the first insulating layer (INS1)) in an etching process (e.g., a dry etching process in the same mask process described above). In one embodiment, the ratio (i.e., ER1:ER2) may be about 1:8. Here, the over-etched portion of the insulating layers may refer to portions of the insulating layers located between the upper surface of the first conductive layer (CDL1) and the upper surface of the second conductive layer (CDL2) among the insulating layers included in the insulating layer array (INSA). This may refer to a portion where etching is performed during a period between the completion of the formation of the second contact hole (CNT2) and the completion of the formation of the first contact hole (CNT1) in a single mask process for simultaneously forming the first and second contact holes (CNT1, CNT2).

[0143] In one embodiment, the thickness (t2) of the second-second portion (p22) may be a thickness that can be set such that the thickness (t2') of the second-first portion (p21) is greater than or equal to about 10 angstroms. Accordingly, it is possible to effectively prevent an increase in contact resistance at the contact surface between the third conductive layer (CDL3) and the second conductive layer (CDL2) due to over-etching of the second uppermost layer (UL2) by the single mask process described above. In one embodiment, for example, the contact resistance at the contact surface between the third conductive layer (CDL3) and the second conductive layer (CDL2) may be less than or equal to about 1 ohm.

[0144] Similarly, the thickness (t1) of the first-second portion (p12) may be set such that the thickness (t1') of the first-first portion (p11) is greater than or equal to 10 angstroms. Accordingly, an increase in contact resistance at the contact surface between the third conductive layer (CDL3) and the first conductive layer (CDL1) can be effectively prevented.

[0145] As described above, in the present disclosure, the first and second uppermost layers (UL1, UL2) included in the first and second conductive layers (CDL1, CDL2) can effectively perform a role of preventing exposure of the first and second lower layers (LL1, LL2). Accordingly, the first lower layer (LL1) may not be exposed by the first contact hole (CNT1), and the second lower layer (LL2) may not be exposed by the second contact hole (CNT2).

[0146] In this case, the electrical connection between the third conductive layer (CDL3) and the first lower layer (LL1) can be made through the first uppermost layer (LL1) which is in electrical contact with each of the third conductive layer (CDL3) and the first lower layer (LL1). That is, the third conductive layer (CDL3) may not be in direct contact with the first lower layer (LL1).

[0147] Similarly, the electrical connection between the third conductive layer (CDL3) and the second lower layer (LL2) can be made through the second uppermost layer (UL2) which is in electrical contact with each of the third conductive layer (CDL3) and the second lower layer (LL2). That is, the third conductive layer (CDL3) may not be in direct contact with the second lower layer (LL2).

[0148] In one embodiment, the thickness (t1') of the first-first portion (p11) may have a value substantially equal to or similar to the thickness (t2') of the second-first portion (p21). For example, the thickness (t1') of the first-first portion (p11) may be about 90% or more and about 110% or less of the thickness (t2') of the second-first portion (p21).

[0149] In one embodiment, the thickness (t2') of the 2-1 portion (p21) may be about 10 angstroms to about 500 angstroms. When the thickness (t2') of the 2-1 portion (p21) satisfies the above-described numerical range, the second uppermost layer (UL2) can effectively function as a capping layer that prevents hillocks or voids from occurring in the second lower layer (LL2), and further, the manufacturing cost required for forming the second uppermost layer (UL2) can be effectively reduced. In this case, the thickness (t2') of the 2-1 portion (p21) may be, for example, about 0.5% or more and about 13.5% or less of the total thickness of the second conductive layer (CDL2).

[0150] In one embodiment, the contact holes (CNT1, CNT2, CNT3) may be formed through a contact hole formation process (i.e., the single mask process described above) after the formation of the insulating layer array (INSA) is completed. In other words, separate contact holes may not be formed before the formation of the insulating layer array (INSA) is completed. In this case, in one embodiment, the first conductive layer (CDL1), the second conductive layer (CDL2), and the semiconductor layer (SCL), which are arranged on different layers, may not be in direct contact with each other.

[0151] In one embodiment, electrical connection of the first conductive layer (CDL1), the second conductive layer (CDL2), and the semiconductor layer (SCL) arranged on different layers can be made through at least the third conductive layer (CDL3).

[0152] In one embodiment, for example, when the first conductive layer (CDL1) and the semiconductor layer (SCL) are electrically connected to each other, the electrical connection path between the first conductive layer (CDL1) and the semiconductor layer (SCL) may include at least a portion of the third conductive layer (CDL3). In other words, the first conductive layer (CDL1) and the semiconductor layer (SCL) may not be electrically connected without passing through the third conductive layer (CDL3).

[0153] In another embodiment, for example, when the first conductive layer (CDL1) and the second conductive layer (CDL2) are electrically connected to each other, the electrical connection path between the first conductive layer (CDL1) and the second conductive layer (CDL2) may include at least a portion of the third conductive layer (CDL3). In other words, the first conductive layer (CDL1) and the second conductive layer (CDL2) may not be electrically connected without passing through the third conductive layer (CDL3).

[0154] In one embodiment, although not shown in FIGS. 4 to 6, the fourth conductive layer (CDL4) may be connected to (or electrically contacted with) the third conductive layer (CDL3). For example, a contact hole (not shown) exposing at least a portion of the third conductive layer (CDL3) may be defined (or formed) in the first via layer (VIA1) in some areas, and the fourth conductive layer (CDL4) may be connected to (or electrically contacted with) the third conductive layer (CDL3) through the contact hole (not shown).

[0155] FIG. 7 is a cross-sectional view illustrating an embodiment in which the first transistor, the first capacitor, and the second capacitor of FIG. 2 are implemented by the conductive layers illustrated in FIGS. 3 to 6. In FIG. 7, for convenience of illustration and explanation, the first via layer (VIA1) and the components disposed on the first via layer (VIA1) are omitted.

[0156] Referring to FIG. 7, the first region (AR1), the second region (AR2), and the third region (AR3) may each independently be some regions among the regions where the pixel circuit (PXCij) described with reference to FIG. 2 is arranged.

[0157] The insulating layer array (INSA of FIG. 3) may include a first insulating layer (INS1), a gate insulating layer (GI), and a second insulating layer (INS2). The first insulating layer (INS1) may include a first-first insulating layer (INS1-1) and a first-second insulating layer (INS1-2). The first-first insulating layer (INS1-1), the first-second insulating layer (INS1-2), the gate insulating layer (GI), and the second insulating layer (INS2) may be substantially the same as those described with reference to FIGS. 3 to 6. Therefore, description of overlapping content is omitted.

[0158] The first conductive layer (CDL1) may include a first lower conductive layer (BML1) and a second lower conductive layer (BML2).

[0159] The first lower conductive layer (BML1) can be patterned into preset shapes. In one embodiment, the patterned portions of the first lower conductive layer (BML1) can include (or define) a first lower capacitor electrode (CSTE) and a second lower capacitor electrode (CHE). In the above-described embodiment, each of the first lower capacitor electrode (CSTE) and the second lower capacitor electrode (CHE) can be configured similarly to the first conductive layer (CDL1) described with reference to FIGS. 3 to 6.

[0160] Each of the first lower capacitor electrode (CSTE) and the second lower capacitor electrode (CHE) can be disposed between the substrate (SUB) and the first-first insulating layer (INS1-1).

[0161] The first lower capacitor electrode (CSTE) can serve as the first terminal of the first capacitor (C1) described with reference to Fig. 2. The first lower capacitor electrode (CSTE) can be arranged in the third region (AR3).

[0162] The second lower capacitor electrode (CHE) can serve as the first terminal of the second capacitor (C2) described with reference to Fig. 2. The second lower capacitor electrode (CHE) can be arranged in the first region (AR1) and the second region (AR2).

[0163] The first lower capacitor electrode (CSTE) and the second lower capacitor electrode (CHE) may be separated from each other. That is, the first lower capacitor electrode (CSTE) and the second lower capacitor electrode (CHE) may not be in direct contact with each other.

[0164] The second lower conductive layer (BML2) can be patterned into preset shapes. In one embodiment, the patterned portions of the second lower conductive layer (BML2) can include an upper capacitor electrode (CE). In the above-described embodiment, the upper capacitor electrode (CE) can be configured similarly to the first conductive layer (CDL1) described with reference to FIGS. 3 to 6.

[0165] The upper capacitor electrode (CE) may be disposed between the first-first insulating layer (INS1-1) and the first-second insulating layer (INS1-2). The upper capacitor electrode (CE) may be disposed directly on the first-first insulating layer (INS1-1).

[0166] The upper capacitor electrode (CE) can overlap the first lower capacitor electrode (CSTE) in the first direction (DR1) in the third region (AR3). In the above-described embodiment, the upper capacitor electrode (CE) in the third region (AR3) can serve as the second terminal of the first capacitor (C1) described with reference to FIG. 2.

[0167] In one embodiment, the upper capacitor electrode (CE) may overlap the second lower capacitor electrode (CHE) in the first direction (DR1) in the second region (AR2). In this case, the upper capacitor electrode (CE) in the second region (AR2) may function as the second terminal of the second capacitor (C2) described with reference to FIG. 2.

[0168] In one embodiment, in FIG. 7, the upper capacitor electrode (CE) is illustrated as being disposed in the second region (AR2) and the third region (AR3), respectively. However, the upper capacitor electrode (CE) disposed in the second region (AR2) and the upper capacitor electrode (CE) disposed in the third region (AR3) may be connected to each other by extending to another region not illustrated in FIG. 7 and formed into an integral, non-separated configuration.

[0169] The semiconductor layer (SCL) can be patterned into preset shapes. In one embodiment, the patterned portions of the semiconductor layer (SCL) can include a first semiconductor pattern (A1). In the above-described embodiment, the first semiconductor pattern (A1) can be configured similarly to the semiconductor layer (SCL) described with reference to FIGS. 3 to 6.

[0170] A portion of the first semiconductor pattern (A1) may be disposed between the first-second insulating layer (INS1-2) and the gate insulating layer (GI). The first semiconductor pattern (A1) may be disposed directly on the first-second insulating layer (INS1-2).

[0171] The first semiconductor pattern (A1) may include a first semiconductor portion (A1_S) and a first conductor portion (A1_C1) and a second conductor portion (A2_C2) adjacent to both opposing sides of the first semiconductor portion (A1_S).

[0172] The first conductor portion (A1_C1) and the second conductor portion (A1_C2) may be portions having relatively high conductivity in the first semiconductor pattern (A1). In one embodiment, for example, the first conductor portion (A1_C1) and the second conductor portion (A1_C2) may be portions that become conductive by being exposed to etching particles during a dry etching process for patterning the second conductive layer (CDL2). In the above-described embodiment, the first conductor portion (A1_C1) and the second conductor portion (A1_C2) may serve as electrodes, wiring, or the like.

[0173] In one embodiment, the first conductor portion (A1_C1) may serve as the first electrode of the first transistor (T1) described with reference to FIG. 2. In addition, the second conductor portion (A1_C2) may serve as the second electrode of the first transistor (T1) described with reference to FIG. 2.

[0174] The first semiconductor portion (A1_S) may have semiconductor properties. In one embodiment, for example, the first semiconductor portion (A1_S) may be a portion that is substantially not exposed to etching particles during a dry etching process for patterning the second conductive layer (CDL2). In the above-described embodiment, the first semiconductor portion (A1_S) may serve as a channel of the transistor. Specifically, the first semiconductor portion (A1_S) may serve as a channel of the first transistor (T1).

[0175] In one embodiment, the first semiconductor pattern (A1) may be arranged in the second region (AR2). In the above-described embodiment, the upper capacitor electrode (CE) overlapping the first semiconductor portion (A1_S) in the first direction (DR1) in the second region (AR2) may serve as the second gate electrode of the first transistor (T1) described with reference to FIG. 2.

[0176] The second conductive layer (CDL2) can be patterned into preset shapes. In one embodiment, the patterned portions of the second conductive layer (CDL2) can include a first gate electrode pattern (T1_G). In this case, the first gate electrode pattern (T1_G) can be configured similarly to the second conductive layer (CDL2) described with reference to FIGS. 3 to 6 .

[0177] The first gate electrode pattern (T1_G) may be disposed between the gate insulating layer (GI) and the second insulating layer (INS2). The first gate electrode pattern (T1_G) may be disposed directly on the gate insulating layer (GI).

[0178] The first gate electrode pattern (T1_G) may overlap the first semiconductor portion (A1_S) in the first direction (DR1) in the second region (AR2). In the above-described embodiment, the first gate electrode pattern (T1_G) in the second region (AR2) may serve as the first gate electrode of the first transistor (T1) described with reference to FIG. 2.

[0179] In one embodiment, the first gate electrode pattern (T1_G) may also be disposed in the third region (AR3). In the above-described embodiment, the first gate electrode pattern (T1_G) in the third region (AR3) may not overlap the semiconductor layer (SCL) in the first direction (DR1). In one embodiment, the first gate electrode pattern (T1_G) disposed in the second region (AR2) and the first gate electrode pattern (T1_G) disposed in the third region (AR3) may be connected to each other by extending to another region not shown in FIG. 7, thereby forming an integral, non-separated configuration.

[0180] The third conductive layer (CDL3) can be patterned into preset shapes. In one embodiment, the patterned portions of the third conductive layer (CDL3) can include a first pattern (P1), a second pattern (P2), a third pattern (P3), a first electrode pattern (T1_E1), and a second electrode pattern (T1_E2). In the above-described embodiment, each of the first pattern (P1), the second pattern (P2), the third pattern (P3), the first electrode pattern (T1_E1), and the second electrode pattern (T1_E2) can be configured similarly to the third conductive layer (CDL3) described with reference to FIGS. 3 to 6.

[0181] Each of the first pattern (P1), the second pattern (P2), the third pattern (P3), the first electrode pattern (T1_E1), and the second electrode pattern (T1_E2) may be disposed between the second insulating layer (INS2) and the first via layer (VIA1 of FIG. 3) not shown in FIG. 6.

[0182] The first electrode pattern (T1_E1) may be connected (or electrically contacted) with the first conductor portion (A1_C1) in the second region (AR2) through the third contact hole (CNT3a). In addition, the first electrode pattern (T1_E1) may be connected (or electrically contacted) with the upper capacitor electrode (CE) in the second region (AR2) through the first contact hole (CNT1a). Here, the first contact hole (CNT1a) and the third contact hole (CNT3a) may be configured similarly to the first contact hole (CNT1) and the third contact hole (CNT3) described with reference to FIGS. 4 to 6, respectively. Accordingly, the first conductor portion (A1_C1) and the upper capacitor electrode (CE) may be electrically connected to each other through the first electrode pattern (T1_E1). In this case, the first electrode pattern (T1_E1) can define the second node (N2) described with reference to FIG. 2.

[0183] The second electrode pattern (T1_E2) can be in electrical contact with the second conductor portion (A1_C2) in the second region (AR2) through the third contact hole (CNT3b). Here, the third contact hole (CNT3b) can be configured similarly to the third contact hole (CNT3) described with reference to FIGS. 4 to 6. In the above-described embodiment, the second electrode pattern (T1_E2) can extend to another region not shown in FIG. 7 and be electrically connected to the second electrode (not shown) of the fifth transistor (T5) described with reference to FIG. 2.

[0184] The first pattern (P1) can be in electrical contact with the first gate electrode pattern (T1_G) in the third region (AR3) through the second contact hole (CNT2a). In addition, the first pattern (P1) can be in electrical contact with the first lower capacitor electrode (CSTE) in the third region (AR3) through the first contact hole (CNT1b). Here, the first contact hole (CNT1b) and the second contact hole (CNT2a) can be configured similarly to the first contact hole (CNT1) and the second contact hole (CNT2) described with reference to FIGS. 4 to 6. Accordingly, the first gate electrode pattern (T1_G) and the first lower capacitor electrode (CSTE) can be electrically connected to each other through the first pattern (P1). In the above-described embodiment, the first pattern (P1) can define the first node (N1) described with reference to FIG. 2.

[0185] The second pattern (P2) can be in electrical contact with the upper capacitor electrode (CE) in the third region (AR3) through the first contact hole (CNT1c). Here, the first contact hole (CNT1c) can be configured similarly to the first contact hole (CNT1) described with reference to FIGS. 4 to 6. In the above-described embodiment, the second pattern (P2) can extend to another region not shown in FIG. 7 and be electrically connected to the first electrode (not shown) of the sixth transistor (T6) described with reference to FIG. 2.

[0186] The third pattern (P3) can be in electrical contact with the second lower capacitor electrode (CHE) in the first region (AR1) through the first contact hole (CNT1d). Here, the first contact hole (CNT1d) can be configured similarly to the first contact hole (CNT1) described with reference to FIGS. 4 to 6. In the above-described embodiment, the third pattern (P3) can serve as the first power line (ELVDDL) described with reference to FIG. 2, or can be electrically connected to the first power line (ELVDDL) described with reference to FIG. 2.

[0187] In one embodiment, the first pattern (P1), the second pattern (P2), the third pattern (P3), the first electrode pattern (T1_E1), and the second electrode pattern (T1_E2) may be separated from each other. That is, the first pattern (P1), the second pattern (P2), the third pattern (P3), the first electrode pattern (T1_E1), and the second electrode pattern (T1_E2) may not be in direct contact with each other.

[0188] In one embodiment, as illustrated in FIG. 7, the first conductive layer (CDL1), the second conductive layer (CDL2), and the semiconductor layer (SCL) may not be in direct contact with each other. In the above-described embodiment, the electrical connection of the first conductive layer (CDL1), the second conductive layer (CDL2), and the semiconductor layer (SCL) may be made at least through the third conductive layer (CDL3).

[0189] In one embodiment, for example, the electrical connection between the upper capacitor electrode (CE) and the first conductor portion (A1_C1) may be made through the first electrode pattern (T1_E1). In another embodiment, for example, the electrical connection between the first gate electrode pattern (T1_G) and the first lower capacitor electrode (CSTE) may be made through the first pattern (P1).

[0190] Fig. 8 is a cross-sectional view illustrating an embodiment in which the second transistor and the third transistor of Fig. 2 are implemented by the conductive layers illustrated in Figs. 3 to 6. In Fig. 8, for convenience of illustration and description, the first via layer (VIA1) and the components arranged on the first via layer (VIA1) are omitted. Hereinafter, descriptions of components identical or similar to those described with reference to Fig. 7 may be omitted.

[0191] Referring to FIG. 8, the fourth region (AR4), the fifth region (AR5), and the sixth region (AR6) may each independently be some regions among the regions where the pixel circuit (PXCij) described with reference to FIG. 2 is placed.

[0192] In one embodiment, the first lower conductive layer (BML1) of the first conductive layer (CDL1) can be patterned into preset shapes. In one embodiment, the patterned portions of the first lower conductive layer (BML1) can include a reference voltage transmission line (VREFL). In this case, the reference voltage transmission line (VREFL) can be configured similarly to the first conductive layer (CDL1) described with reference to FIGS. 3 to 6.

[0193] A reference voltage transmission line (VREFL) may be arranged between the substrate (SUB) and the first-first insulating layer (INS1-1). The reference voltage transmission line (VREFL) may be a pattern to which the reference voltage described with reference to FIG. 2 is applied. In one embodiment, for example, the reference voltage transmission line (VREFL) may be electrically connected to a reference voltage source (not shown) by extending to another area not shown in FIG. 8.

[0194] The semiconductor layer (SCL) can be patterned into preset shapes. In one embodiment, the patterned portions of the semiconductor layer (SCL) can include a second semiconductor pattern (A2). In the above-described embodiment, the second semiconductor pattern (A2) can be configured similarly to the semiconductor layer (SCL) described with reference to FIGS. 3 to 6.

[0195] A portion of the second semiconductor pattern (A2) may be disposed between the first-second insulating layer (INS1-2) and the gate insulating layer (GI). The second semiconductor pattern (A2) may be disposed directly on the first-second insulating layer (INS1-2).

[0196] The second semiconductor pattern (A2) may include a first semiconductor portion (A2_S1), a second semiconductor portion (A2_S2), a first conductor portion (A2_C1), a second conductor portion (A2_C2), and a third conductor portion (A2_C3).

[0197] The first semiconductor portion (A2_S1) may have semiconductor properties. The first semiconductor portion (A2_S1) may be positioned between the first conductor portion (A2_C1) and the second conductor portion (A2_C2) in the fourth region (AR4). The first semiconductor portion (A2_S1) may serve as a channel of the second transistor (T2) described with reference to FIG. 2.

[0198] The second semiconductor portion (A2_S2) may have semiconductor properties. The second semiconductor portion (A2_S2) may be positioned between the second conductor portion (A2_C2) and the third conductor portion (A2_C3) in the fifth region (AR5). The second semiconductor portion (A2_S2) may serve as a channel of the third transistor (T3) described with reference to FIG. 2.

[0199] The first conductive portion (A2_C1) may be a portion having relatively high conductivity. The first conductive portion (A2_C1) may be arranged adjacent to the first semiconductor portion (A2_S1) in the fourth region (AR4). The first conductive portion (A2_C1) may serve as the first electrode of the second transistor (T2) described with reference to FIG. 2.

[0200] The second conductor portion (A2_C2) may be a portion having relatively high conductivity. The second conductor portion (A2_C2) may be disposed in the fourth region (AR4) and the fifth region (AR5). The second conductor portion (A2_C2) may be disposed adjacent to the first semiconductor portion (A2_S1) in the fourth region (AR4), and may be disposed adjacent to the second semiconductor portion (A2_S2) in the fifth region (AR5). The second conductor portion (A2_C2) may serve as a second electrode of the second transistor (T2) described with reference to FIG. 2 in the fourth region (AR4), and may serve as a second electrode of the third transistor (T3) described with reference to FIG. 2 in the fifth region (AR5).

[0201] In one embodiment, the first semiconductor portion (A2_S1) and the second semiconductor portion (A2_S2) may be spaced apart from each other. In this case, the first semiconductor portion (A2_S1) and the second semiconductor portion (A2_S2) may be electrically connected to each other by the second conductor portion (A2_C2). Here, the second conductor portion (A2_C2) may serve as a wiring that electrically connects the second electrode of the second transistor (T2) and the second electrode of the third transistor (T3) described with reference to FIG. 2.

[0202] The third conductor portion (A2_C3) may be a portion having relatively high conductivity. The third conductor portion (A2_C3) may be arranged adjacent to the second semiconductor portion (A2_S2) in the fifth region (AR5). The third conductor portion (A2_C3) may serve as the first electrode of the third transistor (T3) described with reference to FIG. 2 in the fifth region (AR5).

[0203] In one embodiment, the second conductive layer (CDL2) can be patterned into preset shapes. The patterned portions of the second conductive layer (CDL2) can include a second gate electrode pattern (T2_G) and a third gate electrode pattern (T3_G). In the above-described embodiment, each of the second gate electrode pattern (T2_G) and the third gate electrode pattern (T3_G) can be configured similarly to the second conductive layer (CDL2) described with reference to FIGS. 3 to 6.

[0204] Each of the second gate electrode pattern (T2_G) and the third gate electrode pattern (T3_G) may be disposed between the gate insulating layer (GI) and the second insulating layer (INS2). Each of the second gate electrode pattern (T2_G) and the third gate electrode pattern (T3_G) may be disposed directly on the gate insulating layer (GI).

[0205] The second gate electrode pattern (T2_G) may overlap the first semiconductor portion (A2_S1) in the fourth region (AR4). In this case, the second gate electrode pattern (T2_G) in the fourth region (AR4) may serve as the gate electrode of the second transistor (T2) described with reference to FIG. 2.

[0206] In one embodiment, the third gate electrode pattern (T3_G) may overlap the second semiconductor portion (A2_S2) in the first direction (DR1) in the fifth region (AR5). In the above-described embodiment, the third gate electrode pattern (T3_G) in the fifth region (AR5) may serve as a gate electrode of the third transistor (T3) described with reference to FIG. 2.

[0207] In one embodiment, the third conductive layer (CDL3) can be patterned into preset shapes. The patterned portions of the third conductive layer (CDL3) can include a first pattern (P1), a fourth pattern (P4), a fifth pattern (P5), and a sixth pattern (P6). In the above-described embodiment, each of the first pattern (P1), the fourth pattern (P4), the fifth pattern (P5), and the sixth pattern (P6) can be configured similarly to the third conductive layer (CDL3) described with reference to FIGS. 3 to 6.

[0208] Each of the first pattern (P1), the fourth pattern (P4), the fifth pattern (P5), and the sixth pattern (P6) may be placed between the second insulating layer (INS2) and the first via layer (VIA1 of FIG. 3) not shown in FIG. 6.

[0209] The first pattern (P1) is a pattern disposed in the third region (AR3) described with reference to FIG. 7, and may also be disposed in the fourth region (AR4) by extending from the third region (AR3) to another region not illustrated in FIGS. 7 and 8. The first pattern (P1) may be connected (or electrically contacted) through the second conductive portion (A2_C2) and the third contact hole (CNT3c) in the fourth region (AR4). Here, the third contact hole (CNT3c) may be configured similarly to the third contact hole (CNT3) described with reference to FIGS. 4 to 6. Accordingly, the second conductive portion (A2_C2) may be electrically connected to the first gate electrode pattern (T1_G) and the first lower capacitor electrode (CSTE) described with reference to FIG. 7 through the first pattern (P1).

[0210] The fourth pattern (P4) may be connected (or electrically contacted) to the second gate electrode pattern (T2_G) in the fourth region (AR4) through a first contact hole (CNT1e). Here, the first contact hole (CNT1e) may be configured similarly to the first contact hole (CNT1) described with reference to FIGS. 4 to 6.

[0211] The fifth pattern (P5) can be connected (or electrically contacted) with the first conductive portion (A2_C1) in the fourth region (AR4) through a third contact hole (CNT3d). Here, the third contact hole (CNT3d) can be configured similarly to the third contact hole (CNT3) described with reference to FIGS. 4 to 6. The fifth pattern (P5) can serve as the data line (DLj) described with reference to FIG. 2, or can serve as a wiring that electrically connects the data line (DLj) to the first conductive portion (A2_C1).

[0212] The sixth pattern (P6) can be in electrical contact with the third conductor portion (A2_C3) in the fifth region (AR5) through the third contact hole (CNT3e). In addition, the sixth pattern (P6) can be in electrical contact with the reference voltage transmission line (VREFL) in the sixth region (AR6) through the first contact hole (CNT1e). Here, the first contact hole (CNT1e) and the third contact hole (CNT3e) can be configured similarly to the first contact hole (CNT1) and the third contact hole (CNT3) described with reference to FIGS. 4 to 6, respectively. Accordingly, the third conductor portion (A2_C3) and the reference voltage transmission pattern (VREFL) can be electrically connected to each other through the sixth pattern (P6).

[0213] In one embodiment, the first pattern (P1), the fourth pattern (P4), the fifth pattern (P5), and the sixth pattern (P6) may be separated from each other. That is, the first pattern (P1), the fourth pattern (P4), the fifth pattern (P5), and the sixth pattern (P6) may not be in direct contact with each other.

[0214] In one embodiment, as illustrated in FIG. 8, the first conductive layer (CDL1), the second conductive layer (CDL2), and the semiconductor layer (SCL) may not be in direct contact with each other. In this case, the electrical connection between the first conductive layer (CDL1), the second conductive layer (CDL2), and the semiconductor layer (SCL) may be made at least through the third conductive layer (CDL3). For example, the electrical connection between the third conductive portion (A2_C3) and the reference voltage transmission line (VREFL) may be made through the sixth pattern (P6).

[0215] Figure 9 is an enlarged view of the X1 area and X2 area of ​​Figure 7.

[0216] Referring to FIG. 9, in some areas, the second lower conductive layer (BML2) may be arranged to overlap the first lower conductive layer (BML1) in the first direction (DR1), and in other areas, the second lower conductive layer (BML2) may be arranged to not overlap the first lower conductive layer (BML1) in the first direction (DR1).

[0217] In one embodiment, for example, in one region (X1), the upper capacitor electrode (CE) may be arranged to overlap the second lower capacitor electrode (CHE) in the first direction (DR1), but in another region (X2), the upper capacitor electrode (CE) may not overlap the first lower capacitor electrode (CSTE) in the first direction (DR1). Accordingly, a portion of the upper capacitor electrode (CE) arranged in one region (X1) may be arranged above a portion of the upper capacitor electrode (CE) arranged in the other region (X2).

[0218] In one embodiment, a portion of a first conductive layer (CDL1) disposed in a region (X1) (e.g., a portion of the upper capacitor electrode (CE) of the second lower conductive layer (BML2) disposed in a region (X1)) may be disposed above a portion of a second conductive layer (CDL1) disposed in another region (X2) (e.g., a portion of the upper capacitor electrode (CE) of the second lower conductive layer (BML2) disposed in a region (X2). Accordingly, a depth (d1_X1) of a first recessed portion (GR1_X1) defined in a first uppermost layer (UL1) of a portion of a first region of the first conductive layer (CDL1) in a region (X1) may be greater than a depth (d1_X2) of a first recessed portion (GR1_X2) defined in a first uppermost layer (UL1) of a portion of a second region of the first conductive layer (CDL1) in a region (X2).

[0219] In the above-described embodiment, the description of the thickness (t1') of the 1-1 portion (p11) described with reference to FIGS. 4 to 6 may be similarly applied to the thickness (t1'_X1) of the 1-1 portion (p11_X1) in one region (X1) and the thickness (t1'_X1) of the 1-1 portion (p11_X2) in the other region (X2). In one embodiment, for example, the thickness (t1'_X1) of the 1-1 portion (p11_X1) in one region (X1) and the thickness (t1'_X1) of the 1-1 portion (p11_X2) in the other region (X2) may each be about 10 angstroms or more. In the above-described embodiment, the thickness (t1'_X1) of the first-1 part (p11_X1) in one area (X1) may be smaller than the thickness (t1'_X1) of the first-1 part (p11_X2) in the other area (X2).

[0220] Figure 10 is an enlarged view of the Y1 area of ​​Figure 7 and the Y2 area of ​​Figure 8.

[0221] Referring to FIG. 10, in some areas, the second conductive layer (CDL2) may be arranged without overlapping with the semiconductor layer (SCL) in the first direction (DR1), and in other areas, the second conductive layer (CDL2) may be arranged to overlap with the semiconductor layer (SCL) in the first direction (DR1).

[0222] In one embodiment, for example, in one region (Y2), the second gate electrode pattern (T2_G) may be arranged to overlap the second semiconductor pattern (A2) in the first direction (DR1), but in another region (Y1), the first gate electrode pattern (T1_G) may be arranged without overlapping the first semiconductor pattern (A1) in the first direction (DR1). Accordingly, a portion of the first gate electrode pattern (T1_G) arranged in one region (Y2) may be arranged above a portion of the second gate electrode pattern (T2_G) arranged in the other region (Y1).

[0223] In one embodiment, a portion of a region of the second conductive layer (CDL2) disposed in one region (Y2) (e.g., the second gate electrode pattern (T2_G)) may be disposed above a portion of another region of the second conductive layer (CDL2) disposed in another region (Y1) (e.g., the first gate electrode pattern (T1_G)). Accordingly, a depth (d2_Y2) of a second recessed portion (GR2_Y2) defined in a second uppermost layer (UL2) of a portion of a region of the second conductive layer (CDL1) in one region (Y2) may be greater than a depth (d2_Y1) of a second recessed portion (GR2_Y1) defined in a second uppermost layer (UL2) of a portion of another region of the second conductive layer (CDL2) in the other region (Y1).

[0224] In the above-described embodiment, the description of the thickness (t2') of the 2-1 portion (p21) described with reference to FIGS. 4 to 6 may be similarly applied to the thickness (t2'_Y2) of the 2-1 portion (p21_Y2) in one area (Y2) and the thickness (t2'_Y1) of the 2-1 portion (p21_Y1) in the other area (Y2). In one embodiment, for example, the thickness (t2'_Y2) of the 2-1 portion (p21_Y2) in one area (Y2) and the thickness (t2'_Y1) of the 2-1 portion (p21_Y1) in the other area (Y2) may each be about 10 angstroms or more. In the above-described embodiment, the thickness (t2'_Y2) of the second-first portion (p21_Y2) in one area (Y2) may be smaller than the thickness (t2'_Y1) of the second-first portion (p21_Y1) in the other area (Y2).

[0225] FIGS. 11 to 18 are drawings for explaining a method for manufacturing a display device according to one embodiment of the present disclosure. Hereinafter, descriptions of content that overlaps with the content explained with reference to FIGS. 1 to 10 will be omitted.

[0226] Referring to FIG. 11, a method for manufacturing a display device according to one embodiment of the present disclosure may include a series of steps of forming a first conductive layer (S10), forming a semiconductor layer (S20), forming a second conductive layer (S30), forming contact holes (S40), and forming a third conductive layer (S50).

[0227] Hereinafter, a method for manufacturing a display device according to an embodiment of the present disclosure of FIG. 11 will be described in more detail with reference to FIGS. 12 to 18.

[0228] Referring to FIG. 12, in a method for manufacturing a display device according to one embodiment of the present disclosure, a first conductive layer (CDL1) can be formed (S10).

[0229] The first conductive layer (CDL1) may include a first lower layer (LL1) and a first uppermost layer (UL1) covering at least an upper surface of the first lower layer (LL1). In this step (S10), the thickness of the first uppermost layer (UL1) in the first direction (DR1) may correspond to the thickness (t1) of the first-second portion (p12) described with reference to FIG. 6.

[0230] In one embodiment, the present step (S10) may include a patterning process of patterning the first conductive layer (CDL1) after the first conductive layer (CDL1) is formed entirely on the base layer (BSL).

[0231] Referring to Fig. 13, a semiconductor layer (SCL) can be formed (S20). This step (S20) may include a step of forming a first insulating layer (INS1) covering a first conductive layer (CDL1) before forming the semiconductor layer (SCL).

[0232] In one embodiment, the present step (S20) may include a patterning process of forming a semiconductor layer (SCL) entirely on a first insulating layer (INS1) and then patterning the semiconductor layer (SCL).

[0233] In one embodiment, in this step (S20), the semiconductor layer (SCL) and the first conductive layer (CDL1) may not be in direct contact with each other. In one embodiment, for example, a first insulating layer (INS1) may be disposed between the semiconductor layer (SCL) and the first conductive layer (CDL1).

[0234] Referring to Fig. 14, a second conductive layer (CDL2) can be formed (S30). This step (S30) may include a step of forming a gate insulating layer (GI) before forming the second conductive layer (CDL2).

[0235] The second conductive layer (CDL2) may include a second lower layer (LL2) and a second uppermost layer (UL2) covering at least an upper surface of the second lower layer (LL2). In this step (S30), the thickness of the second uppermost layer (UL2) in the first direction (DR1) may correspond to the thickness (t2) of the second-2 portion (p22) described with reference to FIG. 5.

[0236] In one embodiment, the present step (S30) may include a patterning process of forming a gate insulating layer (GI) and a second conductive layer (CDL2) entirely over a first insulating layer (INS1) and a semiconductor layer (SCL), and then patterning the second conductive layer (CDL2) and the gate insulating layer (GI).

[0237] In one embodiment, in the patterning process of patterning the second conductive layer (CDL2) and the gate insulating layer (GI), at least a portion of the semiconductor layer (SCL) that does not overlap the second conductive layer (CDL2) and the gate insulating layer (GI) after the patterning process in the first direction (DR1) may be exposed. In the above-described embodiment, a portion of the exposed semiconductor layer (SCL) may have relatively high conductivity.

[0238] In the above-described embodiment, even if a part of the semiconductor layer (SCL) is exposed, the semiconductor layer (SCL) may not be in direct contact with the second conductive layer (CDL2). In one embodiment, for example, at least a gate insulating layer (GI) may be disposed between the semiconductor layer (SCL) and the second conductive layer (CDL2).

[0239] In this step (S30), the first conductive layer (CDL1), the semiconductor layer (SCL), and the second conductive layer (CDL2) may not be in direct contact with each other. In one embodiment, for example, at least a first insulating layer (INS1) may be disposed between the semiconductor layer (SCL) and the first conductive layer (CDL1). In one embodiment, for example, at least a gate insulating layer (GI) may be disposed between the semiconductor layer (SCL) and the second conductive layer (CDL2). In one embodiment, for example, at least a gate insulating layer (GI) and the first insulating layer (INS1) may be disposed between the second conductive layer (CDL2) and the first conductive layer (CDL1).

[0240] In one embodiment, the present step (S30) may further include a step of forming a second insulating layer (INS2) covering a semiconductor layer (SCL), a gate insulating layer (GI), and a second conductive layer (CDL2) on the first insulating layer (INS1).

[0241] Referring to FIGS. 15 to 17, contact holes (CNT1, CNT2, CNT3) can be formed (S40). In one embodiment, the contact holes (CNT1, CNT2, CNT3) can be formed simultaneously at different locations through a single mask process. In one embodiment, this step (S40) can include a first step (S41), a second step (S42), and a third step (S43).

[0242] Referring to FIG. 15, a first contact hole (CNT1"), a second contact hole (CNT2"), and a third contact hole (CNT3") can be formed (S41).

[0243] In one embodiment, in the first step (S41), the second contact hole (CNT2") may expose at least a portion of the second top layer (UL2).

[0244] In one embodiment, in the first step (S41), the depths of the first contact hole (CNT1"), the second contact hole (CNT2"), and the third contact hole (CNT3") in the first direction (DR1) may be the same.

[0245] Referring to FIG. 16, additional etching (e.g., dry etching) may be performed after the first step (S41), thereby forming a first contact hole (CNT1'), a second contact hole (CNT2'), and a third contact hole (CNT3') (S42).

[0246] In one embodiment, in the second step (S42), the third contact hole (CNT3') may expose at least a portion of the semiconductor layer (SCL).

[0247] In one embodiment, in the second step (S42), the depths of the first contact hole (CNT1') and the third contact hole (CNT3') in the first direction (DR1) may be the same.

[0248] In one embodiment, in the second step (S42), a portion of the second uppermost layer (UL2) may be over-etched, thereby forming a depression in a portion corresponding to a portion exposed by the second contact hole (CNT2') in the second uppermost layer (UL2).

[0249] Referring to FIG. 17, additional etching (e.g., dry etching) may be performed after the second step (S42), thereby forming a first contact hole (CNT1), a second contact hole (CNT2), and a third contact hole (CNT3) (S43).

[0250] In one embodiment, in the third step (S43), the first contact hole (CNT1) may expose at least a portion of the first top layer (UL1).

[0251] In one embodiment, in the third step (S43), a portion of the second uppermost layer (UL2) may be further over-etched compared to the second step (S42), and thus a second recess (GR2) corresponding to a portion of the second uppermost layer (UL2) exposed to the second contact hole (CNT2) may be formed.

[0252] In one embodiment, in the third step (S43), a portion of the first uppermost layer (UL1) may be over-etched. In the above-described embodiment, a first recessed portion (GR1) corresponding to a portion exposed by the first contact hole (CNT1) in the first uppermost layer (UL1) may be formed. Conversely, in another embodiment, in the third step (S43), a portion of the first uppermost layer (UL1) may not be substantially over-etched. In the above-described embodiment, a first recessed portion (GR1) may not be substantially formed in the first uppermost layer (UL1).

[0253] Referring again to FIGS. 15 to 17, contact holes (CNT1, CNT2, CNT3) can be formed simultaneously at different locations through the same etching process. Accordingly, manufacturing efficiency can be improved.

[0254] Since the contact holes (CNT1, CNT2, CNT3) are formed through the same etching process, the second conductive layer (CDL2), which is positioned at the top among the first conductive layer (CDL1), the second conductive layer (CDL2), and the semiconductor layer (SCL), may receive relatively more cumulative damage due to etching. In other words, the second conductive layer (CDL2) may be over-etched. In addition, the first conductive layer (CDL1), which is positioned at the bottom among the first conductive layer (CDL1), the second conductive layer (CDL2), and the semiconductor layer (SCL), may receive relatively less cumulative damage due to etching.

[0255] In the above-described embodiment, since the second uppermost layer (UL2) can have a relatively large thickness (t2) as described with reference to FIGS. 1 to 10, the second uppermost layer (UL2) can effectively protect the second lower layer (LL2) from accumulated damage due to etching. That is, the second lower layer (LL2) may not be exposed by the second contact hole (CNT2). In one embodiment, for example, as described with reference to FIG. 5, the thickness (t2') of the second-1 portion (p21) may be about 10 angstroms or more.

[0256] As in the above-described embodiment, the first uppermost layer (UL1) may have an appropriate thickness (t1) that can protect the first lower layer (LL1) from accumulated damage due to etching. Accordingly, the first lower layer (LL1) may not be exposed by the first contact hole (CNT1). In one embodiment, for example, as described with reference to FIG. 6, the thickness (t1') of the first-first portion (p11) may be about 10 angstroms or more.

[0257] In one embodiment, in this step (S40), the first conductive layer (CDL1), the second conductive layer (CDL2), and the semiconductor layer (SCL) may not be in direct contact with each other. That is, in this step (S40), the first conductive layer (CDL1), the second conductive layer (CDL2), and the semiconductor layer (SCL) may be electrically insulated from each other.

[0258] Referring to Fig. 18, a third conductive layer (CDL3) can be formed (S50).

[0259] In this step (S50), the third conductive layer (CDL3) can fill the first contact hole (CNT1), and thus, the third conductive layer (CDL3) can be connected to (or electrically contacted with) the first conductive layer (CDL1). Similarly, the third conductive layer (CDL3) can fill the second contact hole (CNT2) and the third contact hole (CNT3), and thus, the third conductive layer (CDL3) can be connected to (or electrically contacted with) the second conductive layer (CDL2) and the semiconductor layer (SCL), respectively.

[0260] In one embodiment, the present step (S50) may include a patterning process of forming a third conductive layer (CDL3) entirely over a second insulating layer (INS2) and then patterning the third conductive layer (CDL3).

[0261] In one embodiment, in this step (S50), the third conductive layer (CDL3) can provide an electrical connection path for electrically connecting the first conductive layer (CDL1), the second conductive layer (CDL2), and the semiconductor layer (SCL) to each other.

[0262] In one embodiment, for example, as illustrated in FIG. 7, the electrical connection between the first lower capacitor electrode (CSTE) and the first gate electrode pattern (T1_G) can be made by the first pattern (P1).

[0263] In one embodiment, for example, as illustrated in FIG. 7, the electrical connection between the upper capacitor electrode (CE) and the first conductor portion (A1_C1) can be made through the first electrode pattern (T1_E1).

[0264] In the above-described embodiment, as described above, after the step (S50) is performed, the first conductive layer (CDL1), the second conductive layer (CDL2), and the semiconductor layer (SCL) may be electrically connected to each other at least through the third conductive layer (CDL3). In one embodiment, when the third conductive layer (CDL3) does not exist, the first conductive layer (CDL1), the second conductive layer (CDL2), and the semiconductor layer (ATV) may not be electrically connected to each other.

[0265] Figure 19 is a graph illustrating the thickness of the second top layer to prevent excessive increase in contact resistance between the second conductive layer and the third conductive layer relative to the thickness of the over-etched portion of the insulating layers.

[0266] Referring to FIG. 19, the X-axis of the graph of FIG. 19 may mean the thickness of the over-etched portion of the insulating layers, and the Y-axis of the graph of FIG. 19 may mean the thickness (t2) of the second uppermost layer (UL2) to prevent excessive increase in contact resistance between the second conductive layer (CDL2) and the third conductive layer (CDL3).

[0267] Here, the over-etched portion of the insulating layers may mean portions of the insulating layers (INS1, INS2) located between the lowermost surface of the first contact hole (CNT1") and the upper surface of the first uppermost layer (UL1) in the first step (S41) illustrated in FIG. 15. In other words, the over-etched portion of the insulating layers may mean portions of the insulating layers located between the upper surface of the first conductive layer (CDL1) and the upper surface of the second conductive layer (CDL2) among the insulating layers included in the insulating layer array (INSA).

[0268] In addition, the thickness (t2) of the second uppermost layer (UL2) required to prevent the contact resistance of the second conductive layer (CDL2) and the third conductive layer (CDL3) from excessively increasing may mean a thickness that may be about 10 angstroms or more when the first to third contact holes (CNT1, CNT2, CNT3) are simultaneously formed by a single mask process, such that the thickness (t2') of the second-1 portion (p21) illustrated in FIG. 5 may be about 10 angstroms or more.

[0269] In one embodiment, the thickness (t2) of the second-second portion (p22) may be set to a thickness such that the thickness (t2') of the second-first portion (p21) may be about 10 angstroms or more based on the degree of overetching of the second uppermost layer (UL2) with respect to the first uppermost layer (UL1). Here, the degree of overetching of the second uppermost layer (UL2) with respect to the first uppermost layer (UL1) may mean the difference between the depth (d2, see FIG. 5) of the second recessed portion (GR2) and the depth (d1, see FIG. 6) of the first recessed portion (GR1). In this case, the degree of overetching of the second uppermost layer (UL2) with respect to the first uppermost layer (UL1) may be substantially proportional to the thickness of the overetched portion of the insulating layers, as illustrated in FIG. 19. Accordingly, in the case described above, the difference between the depth (d2) of the second recessed portion (GR2) and the depth (d1) of the first recessed portion (GR1) may be generally proportional to the difference between the depth (D1) of the first contact hole (CNT1) and the depth (D2) of the second contact hole (CNT2).

[0270] In one embodiment, the thicknesses (t1, t2) of the first and second uppermost layers (UL1, UL2) may be set not to be excessively large, taking into consideration the manufacturing cost and the time required for manufacturing. In one embodiment, when each of the first and second uppermost layers (UL1, UL2) is a titanium layer, the thickness (t1) of the first uppermost layer (UL1) may be about 300 angstroms. In the above-described embodiment, for example, the thickness (t2) of the second uppermost layer (UL2) may be about 500 angstroms, which is greater than the thickness (t1) of the first uppermost layer (UL1), based on the thickness of the over-etched portion of the insulating layers (e.g., the X-axis of the graph of FIG. 19).

[0271] In one embodiment, as described above, the thickness (t2) of the second uppermost layer (UL2) can be set based on the difference between the depth (D1) of the first contact hole (CNT1) and the depth (D2) of the second contact hole (CNT2), and the ratio of the etching rate of the second uppermost layer (UL2) to the average etching rate of the insulating layers between the first conductive layer (CDL1) and the second conductive layer (CDL2).

[0272] In embodiments of the present disclosure, the embodiments of the present disclosure are not limited to the first to third conductive layers (CDL1, CDL2, CDL3) described above. In any three conductive layers that constitute the pixel circuit (PXCij) and are arranged in different layers (or at different heights), all conductive layers in which both of the lower two conductive layers are connected to (or electrically contact with) another conductive layer thereon through contact holes formed by penetrating the insulating layers may correspond to the first to third conductive layers (CDL1, CDL2, CDL3) described herein.

[0273] FIG. 20 is a diagram illustrating an electronic device including a display device of the present disclosure. FIG. 21 is a diagram illustrating an example of the electronic device of FIG. 20 implemented as a smartphone. FIG. 22 is a diagram illustrating an example of the electronic device of FIG. 20 implemented as a tablet PC.

[0274] Referring to FIGS. 20 to 22, an electronic device (1000) of one embodiment may include a processor (1010), a memory device (1020), a storage device (1030), an input / output device (1040), a power supply (1050), and a display device (1060). The display device (1060) may be the display device (10) described with reference to FIGS. 1 to 19. In addition, the electronic device (1000) may further include several ports capable of communicating with a video card, a sound card, a memory card, a USB device, or the like, or communicating with other systems. In one embodiment, as illustrated in FIG. 21, the electronic device (1000) may be implemented as a smartphone. In another embodiment, as illustrated in FIG. 22, the electronic device (1000) may be implemented as a tablet PC. However, this is exemplary, and the electronic device (1000) is not limited to the above-described embodiments. In one embodiment, for example, the electronic device (1000) may be implemented as a mobile phone, a video phone, a smart pad, a smart watch, a vehicle navigation system, a computer monitor, a head-mounted display device, etc.

[0275] The processor (1010) can perform specific calculations or tasks. According to an embodiment, the processor (1010) can be a microprocessor, a central processing unit, an application processor, etc. The processor (1010) can be connected to other components via an address bus, a control bus, a data bus, etc. According to an embodiment, the processor (1010) can also be connected to an expansion bus, such as a Peripheral Component Interconnect (PCI) bus. According to an embodiment, the processor (1010) can provide input image data to the display device (1060), and accordingly, the display device (1060) can display an image based on the input image data provided from the processor (1010).

[0276] The memory device (1020) can store data necessary for the operation of the electronic device (1000). In one embodiment, for example, the memory device (1020) may include a non-volatile memory device such as an Erasable Programmable Read-Only Memory (EPROM) device, an Electrically Erasable Programmable Read-Only Memory (EEPROM) device, a flash memory device, a Phase Change Random Access Memory (PRAM) device, a Resistance Random Access Memory (RRAM) device, a Nano Floating Gate Memory (NFGM) device, a Polymer Random Access Memory (PoRAM) device, a Magnetic Random Access Memory (MRAM) device, a Ferroelectric Random Access Memory (FRAM) device, and / or a volatile memory device such as a Dynamic Random Access Memory (DRAM) device, a Static Random Access Memory (SRAM) device, a mobile DRAM device, and the like.

[0277] The storage device (1030) may include a solid state drive (SSD), a hard disk drive (HDD), a CD-ROM, etc.

[0278] The input / output device (1040) may include input means such as a keyboard, keypad, touchpad, touchscreen, mouse, etc., and output means such as a speaker, printer, etc. Depending on the embodiment, the input / output device (1040) may be implemented integrally with the display device (1060).

[0279] The power supply (1050) can supply power required for the operation of the electronic device (1000). In one embodiment, for example, the power supply (1050) can be a power management integrated circuit (PMIC). According to an embodiment, the power supply (1050) can supply power to the display device (1060).

[0280] The display device (1060) can display an image corresponding to visual information of the electronic device (1000). The display device (1060) can be connected to other components via the buses or other communication links.

[0281] The present invention should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concepts of the present invention to those skilled in the art.

[0282] Although the present invention has been particularly described with reference to the embodiments thereof, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit or scope of the invention as defined in the following claims.

Claims

1. Substrate; A first conductive layer disposed on the substrate, the first conductive layer including a first uppermost layer and a first lower layer beneath the first uppermost layer; A first insulating layer disposed on the substrate so as to cover the first challenging layer; A gate insulating layer disposed on the first insulating layer; A second conductive layer disposed on the gate insulating layer and including a second uppermost layer and a second lower layer beneath the second uppermost layer; A second insulating layer disposed on the first insulating layer to cover the second conductive layer; and A third conductive layer is disposed on the second insulating layer and is connected to the first conductive layer and the second conductive layer through the first contact hole and the second contact hole, respectively. The first contact hole is defined to penetrate the first insulating layer and the second insulating layer, thereby exposing a first portion of the first uppermost layer, The second contact hole is defined to penetrate the second insulating layer and expose the first portion of the second uppermost layer, The third conductive layer is arranged in the first contact hole and the second contact hole and is in contact with the first portion of the first uppermost layer and the first portion of the second uppermost layer, The upper surface of the second part of the first uppermost layer is not in contact with the third challenging layer, The upper surface of the second part of the second uppermost layer is not in contact with the third challenging layer, The thickness of the second part of the second uppermost layer is greater than the thickness of the first part of the second uppermost layer, A display device wherein the thickness of the second portion of the first uppermost layer is greater than or equal to the thickness of the first portion of the first uppermost layer.

2. In paragraph 1, A display device, wherein the thickness of the second portion of the second uppermost layer is greater than the thickness of the second portion of the first uppermost layer.

3. In paragraph 1, The thickness of the second portion of the second uppermost layer is from about 300 Angstroms to about 800 Angstroms, A display device, wherein the thickness of the second portion of the first uppermost layer is from about 100 angstroms to about 700 angstroms.

4. In paragraph 3, Each of the first uppermost layer and the second uppermost layer comprises titanium, A display device, wherein each of the first lower layer and the second lower layer comprises aluminum.

5. In paragraph 4, A display device, wherein a difference between the depth of the first contact hole and the depth of the second contact hole is about 2000 angstroms to about 6000 angstroms.

6. In paragraph 1, A first depth is defined as the difference between the thickness of the second portion of the first uppermost layer and the thickness of the first portion of the first uppermost layer, A second depth is defined as the difference between the thickness of the second portion of the second uppermost layer and the thickness of the first portion of the second uppermost layer, A display device wherein the second depth is greater than the first depth.

7. In paragraph 6, A display device wherein the difference between the second depth and the first depth is proportional to the ratio of the etching rate of the second uppermost layer to the average etching rate of the insulating layers between the first conductive layer and the second conductive layer in dry etching.

8. In paragraph 6, A display device, wherein the difference between the second depth and the first depth is proportional to the difference between the depth of the first contact hole and the depth of the second contact hole.

9. In paragraph 1, A display device, wherein the thickness of the first portion of the second uppermost layer is about 10 angstroms or more.

10. In paragraph 9, A display device, wherein the contact resistance at the contact surface between the third conductive layer and the second conductive layer is about 1 ohm or less.

11. In paragraph 1, Further comprising a semiconductor layer disposed between the gate insulating layer and the first insulating layer, The third conductive layer is connected to the semiconductor layer through a contact hole defined to penetrate the second insulating layer, A display device, wherein the semiconductor layer includes polycrystalline silicon, monocrystalline silicon, low-temperature polycrystalline silicon, amorphous silicon, or an oxide semiconductor.

12. In paragraph 1, A display device, wherein the thickness of the second portion of the first uppermost layer is about 3% or more and about 18% or less of the total thickness of the first conductive layer.

13. In paragraph 1, The thickness of the second portion of the second uppermost layer is about 13% or more and about 20% or less of the total thickness of the second challenging layer, A display device, wherein the thickness of the first portion of the second uppermost layer is about 0.5% or more of the total thickness of the second conductive layer.

14. Substrate; A first conductive layer disposed on the substrate and including a first upper titanium layer and a first lower aluminum layer; A first insulating layer disposed on the substrate so as to cover the first challenging layer; A gate insulating layer disposed on the first insulating layer; A second conductive layer disposed on the gate insulating layer and including a second upper titanium layer and a second lower aluminum layer; A second insulating layer disposed on the first insulating layer to cover the second conductive layer; and A third conductive layer is disposed on the second insulating layer and is connected to the first conductive layer and the second conductive layer through the first contact hole and the second contact hole, respectively. The first contact hole is defined to penetrate the first insulating layer and the second insulating layer to expose a first portion of the first upper titanium layer, The second contact hole is defined to penetrate the second insulating layer and expose a first portion of the second upper titanium layer, The third conductive layer is disposed within the first contact hole and the second contact hole and is in contact with the first portion of the first upper titanium layer and the first portion of the second upper titanium layer, The upper surface of the second portion of the first upper titanium layer is not in contact with the third conductive layer, The upper surface of the second portion of the second upper titanium layer is not in contact with the third conductive layer, The thickness of the second portion of the second upper titanium layer is greater than the thickness of the first portion of the second upper titanium layer, A display device wherein the thickness of the second portion of the first upper titanium layer is greater than or equal to the thickness of the first portion of the first upper titanium layer.

15. In paragraph 14, A display device, wherein the thickness of the second portion of the second upper titanium layer is greater than the thickness of the second portion of the first upper titanium layer.

16. In paragraph 14, The thickness of the second portion of the second upper titanium layer is from about 300 angstroms to about 800 angstroms, A display device, wherein the thickness of the second portion of the first upper titanium layer is from about 100 angstroms to about 700 angstroms.

17. In paragraph 14, A display device, wherein a difference between the depth of the first contact hole and the depth of the second contact hole is about 2000 angstroms to about 6000 angstroms.

18. In paragraph 14, A first depth is defined as the difference between the thickness of the second portion of the first upper titanium layer and the thickness of the first portion of the first upper titanium layer, A second depth is defined as the difference between the thickness of the second portion of the second upper titanium layer and the thickness of the first portion of the second upper titanium layer, A display device wherein the second depth is greater than the first depth.

19. In Article 18, A display device wherein the difference between the second depth and the first depth is proportional to the ratio of the etching rate of the second upper titanium layer to the average etching rate of the insulating layers between the first conductive layer and the second conductive layer in dry etching.

20. In paragraph 18, A display device, wherein the difference between the second depth and the first depth is proportional to the difference between the depth of the first contact hole and the depth of the second contact hole.

21. In paragraph 14, A display device, wherein the thickness of the first portion of the second upper titanium layer is about 10 angstroms or more.

22. In paragraph 21, A display device, wherein the contact resistance at the contact surface between the third conductive layer and the second conductive layer is about 1 ohm or less.

23. In paragraph 14, Further comprising a semiconductor layer disposed between the gate insulating layer and the first insulating layer, The third conductive layer is connected to the semiconductor layer through a contact hole defined to penetrate the second insulating layer, A display device, wherein the semiconductor layer includes polycrystalline silicon, monocrystalline silicon, low-temperature polycrystalline silicon, amorphous silicon, or an oxide semiconductor.

24. In paragraph 14, A display device, wherein the ratio of the thickness of the second portion of the first titanium layer to the total thickness of the first challenging layer is about 3% or more and about 18% or less.

25. In paragraph 14, The ratio of the thickness of the second portion of the second titanium layer to the total thickness of the second challenge layer is about 13% or more and about 20% or less, A display device, wherein the ratio of the thickness of the first portion of the second titanium layer to the total thickness of the second challenging layer is about 0.5% or more.

26. A processor providing input image data; A display device that displays an image based on the above input image data; and Includes a power supply for supplying power to the above display device, The above display device: substrate; A first conductive layer disposed on the substrate, the first conductive layer including a first uppermost layer and a first lower layer beneath the first uppermost layer; A first insulating layer disposed on the substrate so as to cover the first challenging layer; A gate insulating layer disposed on the first insulating layer; A second conductive layer disposed on the gate insulating layer and including a second uppermost layer and a second lower layer beneath the second uppermost layer; A second insulating layer disposed on the first insulating layer to cover the second conductive layer; and A third conductive layer is disposed on the second insulating layer and is connected to the first conductive layer and the second conductive layer through the first contact hole and the second contact hole, respectively. The first contact hole is defined to penetrate the first insulating layer and the second insulating layer, thereby exposing a first portion of the first uppermost layer, The second contact hole is defined to penetrate the second insulating layer and expose the first portion of the second uppermost layer, The third conductive layer is arranged in the first contact hole and the second contact hole and is in contact with the first portion of the first uppermost layer and the first portion of the second uppermost layer, The upper surface of the second part of the first uppermost layer is not in contact with the third challenging layer, The upper surface of the second part of the second uppermost layer is not in contact with the third challenging layer, The thickness of the second part of the second uppermost layer is greater than the thickness of the first part of the second uppermost layer, An electronic device wherein the thickness of the second portion of the first uppermost layer is greater than or equal to the thickness of the first portion of the first uppermost layer.

27. A processor providing input image data; A display device that displays an image based on the above input image data; and Includes a power supply for supplying power to the above display device, The above display device: substrate; A first conductive layer disposed on the substrate and including a first upper titanium layer and a first lower aluminum layer; A first insulating layer disposed on the substrate so as to cover the first challenging layer; A gate insulating layer disposed on the first insulating layer; A second conductive layer disposed on the gate insulating layer and including a second upper titanium layer and a second lower aluminum layer; A second insulating layer disposed on the first insulating layer to cover the second conductive layer; and A third conductive layer is disposed on the second insulating layer and is connected to the first conductive layer and the second conductive layer through the first contact hole and the second contact hole, respectively. The first contact hole is defined to penetrate the first insulating layer and the second insulating layer to expose a first portion of the first upper titanium layer, The second contact hole is defined to penetrate the second insulating layer and expose a first portion of the second upper titanium layer, The third conductive layer is disposed within the first contact hole and the second contact hole and is in contact with the first portion of the first upper titanium layer and the first portion of the second upper titanium layer, The upper surface of the second portion of the first upper titanium layer is not in contact with the third conductive layer, The upper surface of the second portion of the second upper titanium layer is not in contact with the third conductive layer, The thickness of the second portion of the second upper titanium layer is greater than the thickness of the first portion of the second upper titanium layer, An electronic device wherein the thickness of the second portion of the first upper titanium layer is greater than or equal to the thickness of the first portion of the first upper titanium layer.

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