Semiconductor device and manufacturing method therefor

Abstract

Provided in the embodiments of the present disclosure are a semiconductor device and a manufacturing method therefor. The manufacturing method comprises: providing a substrate and a stacked structure located on the substrate, wherein the stacked structure comprises semiconductor layers and interlayer insulating layers which are alternately stacked; forming a plurality of channel holes passing through the stacked structure, wherein the semiconductor layer located between adjacent channel holes is configured to form a back gate electrode; performing an oxidation treatment on the semiconductor layer exposed by a side wall of each channel hole to form a first gate dielectric layer; and sequentially forming a channel layer, a second gate dielectric layer and a gate electrode which cover the side walls of the channel holes, wherein the channel layer, the second gate dielectric layer and the gate electrode jointly form a transistor, and the back gate electrode is configured to adjust a threshold voltage of the transistor.

Description

Semiconductor device and manufacturing method thereof

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This disclosure is based on the Chinese patent application with application number 202311686249.8, application date December 4, 2023, and invention name “A semiconductor device and its manufacturing method”, and claims the priority of the Chinese patent application. The entire content of the Chinese patent application is hereby introduced into this disclosure as a reference. Technical Field

[0003] The embodiments of the present disclosure relate to the field of semiconductor technology, and more particularly, to a semiconductor device and a method for manufacturing the same. Background Art

[0004] As memories develop towards higher integration density, the size of memories needs to be scaled down. However, given the extremely small size of current memories, scaling down the size of memories may lead to degradation of the electrical performance of the memories.

[0005] Therefore, the structure and performance of current memories need to be further improved.

[0006] Summary of the Invention

[0007] In view of this, embodiments of the present disclosure provide a semiconductor device and a method for manufacturing the same.

[0008] To achieve the above objectives, the technical solution of the present disclosure is implemented as follows:

[0009] In a first aspect, an embodiment of the present disclosure provides a method for manufacturing a semiconductor device, the method comprising:

[0010] Providing a substrate and a stacked structure located on the substrate, wherein the stacked structure includes alternately stacked semiconductor layers and interlayer insulating layers;

[0011] forming a plurality of channel holes penetrating the stacked structure; wherein the semiconductor layer located between adjacent channel holes is used to form a back gate electrode;

[0012] performing oxidation treatment on the semiconductor layer exposed on the sidewalls of the channel hole to form a first gate dielectric layer;

[0013] A channel layer, a second gate dielectric layer and a gate electrode covering the sidewalls of the channel hole are formed in sequence; wherein the channel layer, the second gate dielectric layer and the gate electrode together form a transistor, and the back gate electrode is used to adjust the threshold voltage of the transistor.

[0014] In some embodiments, before forming a plurality of channel holes penetrating the stacked structure, the manufacturing method further includes:

[0015] A plurality of groove groups are formed that penetrate the stacked structure and are arranged along a first direction, each of the groove groups including a first groove and a second groove arranged in parallel along a second direction; the remaining stacked structure includes a first sub-stacked structure located between the first groove and the second groove, a second sub-stacked structure located between adjacent first grooves, a third sub-stacked structure located between adjacent second grooves, a fourth sub-stacked structure located between adjacent first sub-stacked structures, and a fifth sub-stacked structure located on one side of the first groove and the second sub-stacked structure; wherein the first direction and the second direction are both parallel to the substrate and intersect with each other;

[0016] An isolation material is filled in the first groove and the second groove to form an isolation structure.

[0017] In some embodiments, forming a plurality of channel holes penetrating the stacked structure includes:

[0018] At least the fourth sub-stacked structure in the remaining stacked structure is etched to form a plurality of channel holes penetrating the stacked structure and arranged along the first direction.

[0019] In some embodiments, after sequentially forming the channel layer, the second gate dielectric layer, and the gate electrode covering the sidewalls of the channel hole, the manufacturing method further includes:

[0020] removing the interlayer insulating layer in the first sub-stacked structure to form a first gap; the first gap exposes portions of the channel layer that are oppositely arranged along the first direction;

[0021] removing the channel layer exposed by the first gap;

[0022] An isolation material is filled in the first gap to form a first interlayer isolation layer.

[0023] In some embodiments, removing the interlayer insulating layer in the first sub-stacked structure to form a first gap includes:

[0024] Etching to form a threshold voltage adjustment hole penetrating the first sub-stack structure; the threshold voltage adjustment hole is located between adjacent channel holes, and the remaining semiconductor layer between the adjacent channel holes serves as a back gate electrode;

[0025] The interlayer insulating layer is removed by etching laterally along the threshold voltage adjustment hole to form a first gap; the threshold voltage adjustment hole and the first gap are connected.

[0026] In some embodiments, filling the first gap with an isolation material to form a first interlayer isolation layer includes:

[0027] filling the first gap and the threshold voltage adjustment hole with an isolation material;

[0028] removing the isolation material in the threshold voltage adjustment hole; wherein the isolation material in the first gap forms a first interlayer isolation layer;

[0029] A conductive material is filled in the threshold voltage adjustment hole to form a threshold voltage adjustment structure electrically connected to the back gate electrode; wherein the threshold voltage adjustment structure is used to adjust the threshold voltage of the transistor.

[0030] In some embodiments, after sequentially forming the channel layer, the second gate dielectric layer, and the gate electrode covering the sidewalls of the channel hole, the manufacturing method further includes:

[0031] removing the interlayer insulating layers in the second sub-stacked structure, the third sub-stacked structure, and the fifth sub-stacked structure to form a second gap; wherein the second gap exposes portions of the channel layer that are oppositely arranged along the second direction;

[0032] removing the channel layer exposed by the second gap;

[0033] An isolation material is filled in the second gap to form a second interlayer isolation layer; wherein the first interlayer isolation layer and the second interlayer isolation layer isolate the remaining channel layer in each of the channel holes into channel portions of multiple transistors; two sidewalls of the channel portion opposite to each other along the second direction form a first source and drain and a second source and drain, respectively; multiple transistors arranged along a third direction are connected to the same gate electrode; and the third direction is perpendicular to the substrate.

[0034] In some embodiments, after filling the second gap with an isolation material to form a second interlayer isolation layer, the manufacturing method further includes:

[0035] removing the semiconductor layer within the fifth sub-stacked structure to form a third gap; wherein the third gap exposes the first source and drain;

[0036] A conductive material is filled in the third gap to form a plurality of bit lines extending along the first direction and electrically connected to the first source and drain.

[0037] In some embodiments, after filling the second gap with an isolation material to form a second interlayer isolation layer, the manufacturing method further includes:

[0038] removing the semiconductor layer in the third sub-stacked structure to form a fourth gap; wherein the fourth gap exposes the second source and drain;

[0039] A storage capacitor electrically connected to the second source and drain is formed in the fourth gap.

[0040] In some embodiments, after filling the second gap with an isolation material to form a second interlayer isolation layer, the manufacturing method further includes:

[0041] removing the semiconductor layer within the fifth sub-stacked structure to form a third gap; wherein the third gap exposes the first source and drain;

[0042] Etching to form a threshold voltage adjustment hole penetrating the first sub-stack structure; the threshold voltage adjustment hole is located between adjacent channel holes, and the remaining semiconductor layer between the adjacent channel holes serves as a back gate electrode;

[0043] Conductive material is simultaneously filled in the third gap and the threshold voltage adjustment hole to respectively form a plurality of bit lines extending along the first direction and electrically connected to the first source and drain, and a threshold voltage adjustment structure electrically connected to the back gate electrode; wherein the threshold voltage adjustment structure is used to adjust the threshold voltage of the transistor.

[0044] In a second aspect, an embodiment of the present disclosure provides a semiconductor device, comprising:

[0045] substrate;

[0046] a plurality of channel portions arranged in an array along a first direction and a third direction, wherein the first direction is parallel to the substrate and the third direction is perpendicular to the substrate;

[0047] a gate electrode extending along the third direction and passing through the channel portion;

[0048] a second gate dielectric layer located between the channel portion and the gate electrode; the channel portion, the second gate dielectric layer and the gate electrode together forming a transistor;

[0049] a first gate dielectric layer covering two sidewalls of each channel portion that are opposite to each other along the first direction;

[0050] A back gate electrode is located between adjacent transistors arranged along the first direction; wherein the back gate electrode is in contact with the first gate dielectric layer; and the back gate electrode is used to adjust the threshold voltage of the transistor.

[0051] In some embodiments, two sidewalls of the channel portion disposed opposite to each other along a second direction constitute a first source and a drain, respectively; the second direction is parallel to the substrate and intersects the first direction; the semiconductor device further comprises:

[0052] a bit line extending along the first direction, wherein a plurality of first sources and drains arranged along the first direction are connected to the same bit line;

[0053] A plurality of storage capacitors are provided, and the storage capacitors are connected to the second source and drain.

[0054] In some embodiments, the semiconductor device further comprises:

[0055] A threshold voltage adjustment structure is located between adjacent back gate electrodes of adjacent channel portions arranged along the first direction, wherein the threshold voltage adjustment structure extends along the third direction and electrically connects the plurality of back gate electrodes arranged along the third direction.

[0056] In some embodiments, the channel portion is a ring-shaped structure parallel to the substrate;

[0057] A dimension of the channel portion along the second direction is greater than or equal to a dimension of the back gate electrode along the second direction.

[0058] The present disclosure provides a semiconductor device and a method for manufacturing the same. In the disclosed embodiment, multiple channel holes are formed through a stacked structure, gate electrodes are formed within the channel holes, and the semiconductor layer within the stacked structure serves as a back-gate electrode. This back-gate electrode can be used to adjust the threshold voltage of the transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0059] FIG1 is a schematic diagram of a three-dimensional structure of a semiconductor device provided by an example;

[0060] FIG2 is a schematic flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure;

[0061] 3A to 3P are schematic diagrams of a three-dimensional structure of a semiconductor device during a manufacturing process according to an example;

[0062] 4A to 4F are schematic cross-sectional views of a semiconductor device during a manufacturing process according to an example;

[0063] 5A and 5B are schematic structural diagrams of a semiconductor device provided by an example;

[0064] 6A and 6B are schematic structural diagrams of a semiconductor device provided in another example. DETAILED DESCRIPTION

[0065] The following will clearly and completely describe the technical solutions in the embodiments of the present disclosure in conjunction with the embodiments of the present disclosure and the accompanying drawings. Obviously, the embodiments described are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of the present disclosure.

[0066] In the following description, numerous specific details are provided to provide a more thorough understanding of the present disclosure. However, it will be apparent to those skilled in the art that the present disclosure can be practiced without one or more of these details. In other instances, certain technical features known in the art are not described to avoid confusion with the present disclosure; that is, all features of actual embodiments are not described herein, nor are well-known functions and structures described in detail.

[0067] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0068] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to, or coupled to" another element or layer, it may be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on, directly adjacent to, directly connected to, or directly coupled to" another element or layer, there may be no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer, or part discussed below may be represented as a second element, component, region, layer, or part. However, when the second element, component, region, layer, or part is discussed, it does not necessarily mean that the first element, component, region, layer, or part exists in the present disclosure.

[0069] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," etc., may be used herein for convenience of description to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatially relative terms are intended to include different orientations of the device in use and operation. For example, if the device in the drawings is flipped, then the elements or features described as "under the other elements" or "under it" or "under it" will be oriented as "on" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or in other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0070] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present disclosure. When used herein, the singular forms "a", "an", and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0071] In order to fully understand the present disclosure, detailed steps and detailed structures will be presented in the following description to illustrate the technical solution of the present disclosure. The preferred embodiments of the present disclosure are described in detail below. However, in addition to these detailed descriptions, the present disclosure may also have other implementation methods.

[0072] Referring to FIG1 , FIG1 is a schematic diagram of a three-dimensional structure of a semiconductor device provided in an example. As shown in FIG1 , the semiconductor device 100 includes: a substrate (not shown in FIG1 ) and a plurality of semiconductor pillars 101 located on the substrate, wherein the semiconductor pillars 101 extend along the Y direction and are arranged in an array along the X and Z directions; wherein the semiconductor pillars 101 include a source, a drain, and a channel region located between the source and the drain along the extension direction; a word line 102 surrounding the channel region of the semiconductor pillar 101, wherein the word line 102 extends along the Z direction and the plurality of semiconductor pillars 101 arranged along the Z direction are connected to the same word line 102; a bit line 104 connected to the source or drain of the semiconductor pillar 101, wherein the bit line 104 extends along the X direction and the source or drain of the plurality of semiconductor pillars 101 arranged along the X direction are connected to the same bit line 104; and a storage capacitor 106 connected to the drain or source of the semiconductor pillar 101, wherein the storage capacitor 106 extends along the Y direction.

[0073] In the above example, the angle between the X direction and the Y direction is 90 degrees, and both the X direction and the Y direction are perpendicular to the Z direction. In other examples, the angle between the X direction and the Y direction may be other angles, for example, 30 degrees, 45 degrees, or 90 degrees. This example does not constitute a limitation on the angles between the X direction, the Y direction, and the Z direction.

[0074] As shown in FIG1 , the semiconductor device 100 further includes: a plurality of word line extension lines 103 , each extending along the Z direction and arranged along the X direction, with the bottoms of different word line extension lines 103 connected to different word lines 102 ; and a plurality of bit line extension lines 105 , each extending along the Z direction and arranged along the X direction, with the bottoms of different bit line extension lines 105 connected to different bit lines 104 .

[0075] The semiconductor device 100 further includes an isolation layer 107 extending in the X direction. The word lines 102 are located between adjacent isolation layers 107 in the Y direction. The semiconductor pillars 101 pass through the isolation layer 107 in the Y direction. The isolation layer 107 can separate the word lines 102 from the source and drain of the semiconductor pillars 101, thereby preventing leakage between the source or drain and the channel region of the transistor formed by the semiconductor pillars, thereby preventing the performance of the semiconductor device from being affected.

[0076] The semiconductor device 100 in the above example is a three-dimensional dynamic random access memory (3D DRAM) with a one-transistor and one-storage-capacitor (1T1C) structure. Using indium gallium zinc oxide (IGZO) as the channel material for this DRAM can further reduce leakage and improve the DRAM's electrical performance. Furthermore, the manufacturing process for this DRAM is relatively simple and low-cost, making it a key research topic within the industry.

[0077] However, as an N-type semiconductor material, IGZO has a threshold voltage that is more inclined to negative voltage. But for DRAM, a positive threshold voltage is more conducive to reducing leakage, thereby extending the retention time of stored data.

[0078] In view of this, embodiments of the present disclosure provide a semiconductor device and a method for manufacturing the same.

[0079] Referring to FIG2 , FIG2 is a flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. As shown in FIG2 , an embodiment of the present disclosure provides a method for manufacturing a semiconductor device, the method comprising:

[0080] Step S201: providing a substrate and a stacked structure on the substrate, wherein the stacked structure includes alternately stacked semiconductor layers and interlayer insulating layers;

[0081] Step S202: forming a plurality of channel holes penetrating the stacked structure; wherein the semiconductor layer located between adjacent channel holes is used to form a back gate electrode;

[0082] Step S203: performing oxidation treatment on the semiconductor layer exposed on the sidewalls of the channel hole to form a first gate dielectric layer;

[0083] Step S204: sequentially forming a channel layer, a second gate dielectric layer, and a gate electrode covering the sidewalls of the channel hole; wherein the channel layer, the second gate dielectric layer, and the gate electrode together form a transistor, and the back gate electrode is used to adjust the threshold voltage of the transistor.

[0084] In the embodiment of the present disclosure, a plurality of channel holes are formed through the stacked structure, and a first gate dielectric layer, a channel layer, a second gate dielectric layer and a gate electrode are sequentially formed in the channel holes, wherein the channel layer, the second gate dielectric layer and the gate electrode together form a transistor; and the original semiconductor layer in the stacked structure is used as a back gate electrode, so that the back gate electrode can be used to adjust the threshold voltage of the transistor.

[0085] Referring to Figures 3A to 3P , Figures 3A to 3P are schematic diagrams of the three-dimensional structure of a semiconductor device during manufacturing, according to an example. Referring to Figures 4A to 4F , Figures 4A to 4F are schematic diagrams of the cross-sectional structure of a semiconductor device during manufacturing, according to an example. The manufacturing process of the semiconductor device will be described in detail below, in conjunction with Figures 3A to 3P and Figures 4A to 4F .

[0086] In the embodiment of the present disclosure, in step S201 , a substrate 201 and a stacked structure 202 located on the substrate 201 are provided. The stacked structure 202 includes semiconductor layers 203 and interlayer insulating layers 204 that are alternately stacked.

[0087] As shown in FIG3A , semiconductor layers 203 and interlayer insulating layers 204 are alternately stacked in sequence on a substrate 201 , wherein the alternately stacked semiconductor layers 203 and interlayer insulating layers 204 together form a stacked structure 202 ; and a capping layer 205 is formed on the stacked structure 202 .

[0088] Here, the substrate 201 can be a semiconductor substrate; specifically, it includes at least one elemental semiconductor material (for example, a silicon (Si) substrate, a germanium (Ge) substrate, etc.), at least one III-V compound semiconductor material (for example, a gallium nitride (GaN) substrate, a gallium arsenide (GaAs) substrate, an indium phosphide (InP) substrate, etc.), at least one II-VI compound semiconductor material, at least one organic semiconductor material or other semiconductor materials known in the art, and may also include other substrates containing semiconductor materials, such as a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate, a polycrystalline semiconductor layer on an insulating layer, a silicon-germanium substrate, etc.

[0089] Here, the material of the semiconductor layer 203 may include but is not limited to polysilicon material; the material of the interlayer insulating layer 204 may include but is not limited to silicon oxide material. The present disclosure has no particular limitation on the number and thickness of the semiconductor layers and the interlayer insulating layer.

[0090] Here, the material of the capping layer 205 may include but is not limited to silicon nitride material.

[0091] Here, the process of forming the semiconductor layer 203, the interlayer insulating layer 204 and the capping layer 205 may include but is not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof.

[0092] In the disclosed embodiments, the thickness direction of the substrate is defined as a third direction, namely the Z direction. Alternatively, a direction perpendicular to the substrate surface is defined as the third direction, namely the Z direction. A first and second intersecting directions are defined in a plane perpendicular to the third direction, where the first direction is the X direction and the second direction is the Y direction. In one example, the X direction, the Y direction, and the Z direction can be perpendicular to each other.

[0093] As shown in FIG3B , in some embodiments, before step S202 , the manufacturing method further includes: sequentially etching the cover layer 205 and the stacked structure 202 along the Z direction to form a plurality of groove groups 206 extending through the stacked structure and arranged along a first direction (i.e., the X direction), each groove group 206 including a first groove 207 and a second groove 208 arranged in parallel along a second direction (i.e., the Y direction). FIG3B illustrates three groove groups 206 sequentially arranged along the X direction, each groove group 206 including a first groove 207 and a second groove 208 arranged in parallel along the Y direction.

[0094] Here, the process of forming the first groove 207 and the second groove 208 may include, but is not limited to, wet etching, dry etching, or a combination thereof.

[0095] The first groove 207 and the second groove 208 divide the stacked structure 202 into multiple components. The remaining stacked structure 202 includes: a first sub-stacked structure 209 located between the first groove 207 and the second groove 208; a second sub-stacked structure 210 located between two adjacent first grooves 207 along the X direction (as shown in the dotted circle in FIG. 3B ); a third sub-stacked structure 211 located between two adjacent second grooves 208 along the X direction; a fourth sub-stacked structure 212 located between two adjacent first sub-stacked structures 209 along the X direction (as shown in the dotted square in FIG. 3B ); and a fifth sub-stacked structure 213 located to one side of the first groove 207 and the second sub-stacked structure 210. The fourth sub-stacked structure 212 is also located between the second sub-stacked structure 210 and the third sub-stacked structure 211 arranged along the Y direction. The region where the fourth sub-stacked structure 212 is located is used to form transistors of the semiconductor device.

[0096] Here, the remaining stacked structures are divided to facilitate description of the manufacturing process of the semiconductor device. The only difference between different sub-stacked structures is the relative positional relationship between the first groove and the second groove.

[0097] In addition, for the convenience of illustration, the substrate is not shown in FIG3B to FIG3P .

[0098] As shown in FIG. 3B and FIG. 3C , an isolation material is filled in the first groove 207 and the second groove 208 to form an isolation structure 214 .

[0099] Here, the process of forming the semiconductor layer 203 and the interlayer insulating layer 204 may include, but is not limited to, CVD, PVD, ALD, or any combination thereof.

[0100] Here, the material of the isolation structure 214 may include a low dielectric constant material, such as silicon oxide, silicon nitride, silicon carbide, silicon carbide nitride, or silicon oxynitride. In some embodiments, the materials of the capping layer 205 and the isolation structure 214 may be the same or different. FIG3C illustrates that the capping layer 205 and the isolation structure 214 are the same, i.e., both are made of silicon nitride. The top surface of the capping layer 205 may be flush with the top surface of the isolation structure 214.

[0101] In the embodiment of the present disclosure, in step S202 , a plurality of channel holes 215 penetrating the stacked structure 202 are formed; wherein the semiconductor layer 203 located between adjacent channel holes 215 is used to form a back gate electrode 222 .

[0102] As shown in FIG3D , in some embodiments, step S202 includes sequentially etching the capping layer 205 and at least the fourth sub-stack structure 212 in the stack structure 202 along the Z direction to form a plurality of channel holes 215 that penetrate the stack structure 202 and are arranged along the first direction (i.e., the X direction). Here, the orthographic projection area of ​​the channel holes 215 on the substrate (i.e., the XY plane) is greater than or equal to the orthographic projection area of ​​the fourth sub-stack structure 212 on the substrate (i.e., the XY plane).

[0103] In some examples, only the fourth sub-stack structure 212 of the stacked structure 202 is etched, and the orthographic projection area of ​​the formed channel hole 215 on the XY plane is equal to the orthographic projection area of ​​the fourth sub-stack structure 212 on the XY plane. In some examples, the fourth sub-stack structure 212 and at least a portion of the first sub-stack structure 209 of the stacked structure 202 are etched simultaneously, and the dimension of the formed channel hole 215 along the X direction is larger than the dimension of the fourth sub-stack structure 212 along the X direction, and the orthographic projection area of ​​the channel hole 215 on the XY plane is larger than the orthographic projection area of ​​the fourth sub-stack structure 212 on the XY plane. In some examples, the fourth sub-stack structure 212 and at least a portion of the second sub-stack structure 210 and / or at least a portion of the third sub-stack structure 211 in the stack structure 202 are etched simultaneously, so that the size of the formed channel hole 215 along the Y direction is larger than the size of the fourth sub-stack structure 212 along the Y direction, and the orthographic projection area of ​​the channel hole 215 on the XY plane is larger than the orthographic projection area of ​​the fourth sub-stack structure 212 on the XY plane.

[0104] It should be noted that, when only the fourth sub-stacked structure 212 in the stacked structure 202 is etched, the space occupied by the second sub-stacked structure 210 can be used to form a bit line contact structure subsequently.

[0105] Here, the process of forming the channel hole 215 may include, but is not limited to, wet etching, dry etching, or a combination thereof.

[0106] In the embodiment of the present disclosure, the orthographic projection of the channel hole 215 on the XY plane can be a quadrilateral, and the channel hole 215 includes four sidewalls, wherein two sidewalls are arranged opposite to each other along the X direction, and the other two sidewalls are arranged opposite to each other along the Y direction. In other embodiments, the orthographic projection of the channel hole 215 on the XY plane can also be a circle, an ellipse, etc., in which case the channel hole 215 includes at least two end portions arranged opposite to each other along the Y direction. The present disclosure does not specifically limit the shape of the orthographic projection of the channel hole 215 on the XY plane.

[0107] In the embodiment of the present disclosure, in step S203 , the semiconductor layer 203 exposed on the sidewalls of the channel hole 215 is oxidized to form a first gate dielectric layer 216 .

[0108] Figure 3D does not illustrate the internal structure of the channel hole 215. Reference is made here to Figure 4A, which illustrates an XZ cross-sectional view of the structure along the AA section in Figure 3D. As shown in Figure 4A, the bottom of the channel hole 215 formed by etching exposes the substrate 201. The sidewalls of the channel hole 215 expose the sidewalls of the alternately stacked semiconductor layer 203 and interlayer insulating layer 204, as well as the sidewalls of the capping layer 205. The semiconductor layer 203 exposed by the sidewalls of the channel hole 215 is oxidized to form a first gate dielectric layer 216.

[0109] Here, the material of the semiconductor layer 203 may include but is not limited to polysilicon material, which may be formed into silicon oxide material after oxidation treatment.

[0110] In the embodiment of the present disclosure, in step S204, a channel layer 217, a second gate dielectric layer 218, and a gate electrode 219 are sequentially formed to cover the sidewalls of the channel hole 215; wherein the channel layer 217, the second gate dielectric layer 218, and the gate electrode 219 together form a transistor 220, and the back gate electrode 222 is used to adjust the threshold voltage of the transistor 220. In some examples, the semiconductor layer 203 can be a P-type heavily doped polysilicon material with a doping concentration of 1E21 to 1E23 cm -3 , the work function is 4~5.5eV.

[0111] 3E , a channel layer 217 is formed to cover the sidewalls of the channel hole 215 . The channel layer 217 and the alternately exposed first gate dielectric layers 216 and interlayer insulating layer 204 on the sidewalls of the channel hole 215 are in direct contact with each other.

[0112] Here, the material of the channel layer 217 may include but is not limited to oxide semiconductor materials, such as IGZO, zinc tin oxide (ZTO), indium zinc oxide (IZO), zinc oxide, indium gallium silicon oxide (IGSO), and indium oxide.

[0113] 3F , a second gate dielectric layer 218 is formed to cover the sidewalls of the channel hole 215 . The second gate dielectric layer 218 is in direct contact with the channel layer 217 in the channel hole 215 .

[0114] Here, the material of the second gate dielectric layer 218 may include, but is not limited to, a high dielectric constant material, a silicon oxide material, a silicon nitride material, a silicon oxynitride material, or the like, or a combination thereof.

[0115] 3G , the channel hole 215 is filled with a conductive material to form a gate electrode 219 . The gate electrode 219 is in direct contact with the second gate dielectric layer 218 in the channel hole 215 .

[0116] Exemplarily, a conductive material is filled in the channel hole 215, and the conductive material may also be located on the surface of the covering layer 205 while filling the channel hole 215; the conductive material is planarized so that the surface of the conductive material in the channel hole 215 and the surface of the covering layer 205 are basically flush, so as to expose the surface of the covering layer 205; wherein, the conductive material located in the channel hole 215 forms a gate electrode 219.

[0117] Here, the material of the gate electrode 219 may include, but is not limited to, a metal, a metal compound, or an alloy. The metal may be, for example, copper, aluminum, tungsten, gold, or silver; the metal compound may be, for example, tantalum nitride or titanium nitride; and the alloy may be an alloy formed by at least two metal elements selected from copper, aluminum, tungsten, gold, or silver.

[0118] Here, the process of forming the channel layer 217 , the second gate dielectric layer 218 , and the gate electrode 219 may include, but is not limited to, CVD, PVD, ALD, or any combination thereof.

[0119] Referring to FIG4B , FIG4B is a schematic diagram of the XZ cross-sectional structure along the BB section in FIG3G . As shown in FIG4B , the channel hole 215 includes a first gate dielectric layer 216, a channel layer 217, a second gate dielectric layer 218, and a gate electrode 219 in the radially inward direction. The semiconductor layers 203 and the interlayer insulating layer 204 alternately stacked in the stacked structure surround the channel hole 215, and the semiconductor layers 203 are in direct contact with the first gate dielectric layer 216. The channel layer 217, the second gate dielectric layer 218, and the gate electrode 219 shown in FIG3G and FIG4B together form a transistor 220. The transistor 220 can be a transistor with a vertical annular channel structure (Channel All Around, CAA), wherein the second gate dielectric layer 218 surrounds the gate electrode 219, and the channel layer 217 surrounds the second gate dielectric layer 218.

[0120] In addition, for the convenience of illustration, the substrate is not shown in FIG. 4B to FIG. 4F .

[0121] In some embodiments, after step S204, the manufacturing method further includes:

[0122] The interlayer insulating layer 204 in the first sub-stack structure 209 is removed to form a first gap 223 ; the first gap 223 exposes a portion of the channel layer 217 oppositely disposed along the first direction;

[0123] removing the channel layer 217 exposed by the first gap 223;

[0124] An isolation material is filled in the first gap 223 to form a first interlayer isolation layer 224 .

[0125] As shown in FIG3H , in some embodiments, the interlayer insulating layer 204 in the first sub-stack structure 209 is removed to form a first gap 223, including: etching the capping layer 205 and the first sub-stack structure 209 in the stack structure 202 in sequence along the Z direction to form a threshold voltage adjustment hole 221 that penetrates the first sub-stack structure 209; the threshold voltage adjustment hole 221 is located between adjacent channel holes 215 along the X direction, and the remaining semiconductor layer 203 between adjacent channel holes 215 along the X direction serves as a back gate electrode 222; etching and removing the interlayer insulating layer 204 in the first sub-stack structure 209 through the threshold voltage adjustment hole 221 in the transverse direction (i.e., the X direction) along the threshold voltage adjustment hole 221 to form the first gap 223; the threshold voltage adjustment hole 221 and the first gap 223 are connected.

[0126] Here, the process of forming the threshold voltage adjusting hole 221 and the first gap 223 may include, but is not limited to, wet etching, dry etching, or a combination thereof.

[0127] Referring to FIG4C , FIG4C is a schematic diagram of the XZ cross-sectional structure along the CC section in FIG3H . As shown in FIG3H and FIG4C , after the threshold voltage adjustment hole 221 and the first gap 223 are formed, the first gap 223 now exposes portions of the channel layer 217 that are positioned opposite each other along the X direction. In other words, the first gap 223 now exposes the channel layer 217 located on two opposite sidewalls of the channel hole 215 along the X direction.

[0128] Here, the remaining semiconductor layer between adjacent channel holes 215 along the X direction serves as the back gate electrode 222 , the first gate dielectric layer 216 is located between the channel layer 217 and the back gate electrode 222 , and the second gate dielectric layer 218 is located between the channel layer 217 and the gate electrode 219 .

[0129] In the disclosed embodiments, a semiconductor layer and an interlayer insulating layer are alternately stacked. Subsequently, the remaining semiconductor layer between adjacent channel holes is etched to serve as a back-gate electrode, eliminating the need for a separate back-gate electrode. This simplifies the semiconductor device manufacturing process. Furthermore, the back-gate electrode can be used to adjust the threshold voltage of the transistor, reducing leakage current in the semiconductor device, thereby improving the electrical performance of the semiconductor device.

[0130] Referring to Figures 3I and 4D, Figure 4D is a schematic diagram of the XZ cross-sectional structure along the DD section in Figure 3I. As shown in Figures 3I and 4D, lateral etching is performed to remove the channel layer 217 exposed by the first gap 223. At this time, the first gap 223 exposes portions of the second gate dielectric layer 218 that are located opposite each other along the X direction. In other words, the first gap 223 exposes the second gate dielectric layer 218 located on two opposite sidewalls of the channel hole 215 along the X direction.

[0131] Here, the process of removing the channel layer 217 exposed by the first gap 223 may include, but is not limited to, wet etching, dry etching, or a combination thereof.

[0132] Referring to Figures 3J and 4E , Figure 4E is a schematic diagram of the XZ cross-sectional structure along section EE in Figure 3J . As shown in Figures 3J and 4E , in some embodiments, filling the first gap 223 with an isolation material to form a first interlayer isolation layer 224 includes: filling the first gap 223 and the threshold voltage adjustment hole 221 with the isolation material through the threshold voltage adjustment hole 221, such that at least the first gap 223 is completely filled with the isolation material; wherein the isolation material in the first gap 223 forms the first interlayer isolation layer 224.

[0133] Here, the first interlayer isolation layer 224 is in direct contact with the second gate dielectric layer 218 on two opposite sidewalls of the channel hole 215 along the X direction. FIG4E illustrates that the channel layer 217 on two opposite sidewalls of the channel hole 215 along the X direction is isolated by multiple first interlayer isolation layers 224, so that the channel layer 217 is isolated by the first interlayer isolation layers 224 in the XZ cross-sectional structural diagram.

[0134] Here, the material of the first interlayer isolation layer 224 may include, but is not limited to, a low dielectric constant material, for example, at least one of silicon oxide, silicon nitride, silicon carbide, silicon carbide nitride, or silicon oxynitride.

[0135] As shown in Figures 3J and 4E, the isolation material in the threshold voltage adjustment hole 221 is removed; a conductive material is filled in the threshold voltage adjustment hole 221 to form a threshold voltage adjustment structure 225 electrically connected to the back gate electrode 222; wherein the threshold voltage adjustment structure 225 is used to adjust the threshold voltage of the transistor 220.

[0136] Here, two sidewalls of the threshold voltage adjustment structure 225 that are opposite to each other along the Z direction are in contact with the back gate electrode.

[0137] In the embodiment of the present disclosure, a threshold voltage adjustment structure can also be formed. While the back gate electrode is used to adjust the threshold voltage of the transistor, the threshold voltage adjustment structure can also be used to further adjust the threshold voltage of the transistor, thereby enhancing the adjustment effect on the threshold voltage of the transistor.

[0138] Here, the material of the threshold voltage adjustment structure 225 may include, but is not limited to, a metal, a metal compound, or an alloy. The metal may be, for example, copper, aluminum, tungsten, gold, or silver; the metal compound may be, for example, tantalum nitride or titanium nitride; and the alloy may be an alloy formed by at least two of the following metal elements: copper, aluminum, tungsten, gold, or silver.

[0139] Here, the process of forming the first interlayer isolation layer 224 and the threshold voltage adjustment structure 225 may include, but is not limited to, CVD, PVD, ALD, or any combination thereof.

[0140] As shown in FIG3K , in some embodiments, after sequentially forming the channel layer 217, the second gate dielectric layer 218, and the gate electrode 219 covering the sidewalls of the channel hole 215, the manufacturing method further includes: etching away the interlayer insulating layer 204 within the second sub-stack structure 210, the third sub-stack structure 211, and the fifth sub-stack structure 213 to form a second gap 226. The second gap 226 exposes portions of the channel layer 217 that are oppositely disposed along the Y direction. In other words, the second gap 226 exposes the channel layer 217 located on two opposite sidewalls of the channel hole 215 along the Y direction.

[0141] Here, the process of forming the second gap 226 may include, but is not limited to, wet etching, dry etching, or a combination thereof.

[0142] As shown in FIG3K , the channel layer 217 exposed by the second gap 226 is removed. The second gap 226 now exposes portions of the second gate dielectric layer 218 that are oppositely disposed along the Y direction. In other words, the second gap 226 now exposes the second gate dielectric layer 218 located on two opposite sidewalls of the channel hole 215 along the Y direction.

[0143] Here, the process of removing the channel layer 217 exposed by the second gap 226 may include, but is not limited to, wet etching, dry etching, or a combination thereof.

[0144] By removing a portion of the channel layer 217 corresponding to the interlayer insulating layer 204 , the channel layer 217 between each transistor 220 is self-aligned and disconnected along the Z direction to form a channel portion 228 , thereby avoiding mutual interference between adjacent transistors 220 and reducing leakage of the transistor 220 .

[0145] Still as shown in Figure 3L, an isolation material is filled in the second gap 226 to form a second interlayer isolation layer 227; the first interlayer isolation layer 224 and the second interlayer isolation layer 227 isolate the remaining channel layer 217 in each channel hole 215 into channel portions 228 of multiple transistors 220, so that the channel layer 217 in the XZ cross-sectional structural schematic diagram and the YZ cross-sectional structural schematic diagram are both isolated by the first interlayer isolation layer 224 and the second interlayer isolation layer 227.

[0146] Referring to Figure 4F, Figure 4F is a schematic diagram of the YZ cross-sectional structure along the FF section in Figure 3L. As shown in Figures 3L and 4F, the second interlayer isolation layer 227 contacts the second gate dielectric layer 218 on two opposing sidewalls of the channel hole 215 along the Y direction. The channel layer 217 on two opposing sidewalls of the channel hole 215 along the X direction is isolated by multiple first interlayer isolation layers 224. That is, the first interlayer isolation layers 224 and the second interlayer isolation layers 227 jointly isolate the channel layer 217 within each channel hole 215 into channel portions 228 of multiple transistors 220, thereby forming multiple transistors 220 arranged along the Z direction. The multiple transistors 220 arranged along the Z direction are connected to the same gate electrode 219, while the multiple transistors 220 arranged along the X direction are connected to different gate electrodes 219.

[0147] Here, the material of the second interlayer isolation layer 227 may include, but is not limited to, a low dielectric constant material, for example, at least one of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, or silicon oxynitride.

[0148] Here, the process of forming the second interlayer isolation layer 227 may include, but is not limited to, CVD, PVD, ALD, or any combination thereof.

[0149] In the embodiment of the present disclosure, the interlayer insulating layer 204 in the first sub-stack structure 209 is first etched away to form a first gap 223, and then the interlayer insulating layer 204 in the second sub-stack structure 210, the third sub-stack structure 211 and the fifth sub-stack structure 213 is etched away to form a second gap 226; that is, the first interlayer isolation layer 224 is formed first and then the second interlayer isolation layer 227 is formed.

[0150] In other embodiments, the second gap may be formed first and then the first gap, that is, the second isolation layer may be formed first and then the first isolation layer. In other embodiments, the second gap and the first gap may be formed simultaneously, and the exposed channel layer may be partially removed through the second gap and the first gap at the same time. The present disclosure does not specifically limit the process sequence for forming the first gap and the second gap, as long as the channel layer can be isolated into multiple channel portions arranged along the Z direction.

[0151] In the disclosed embodiment, transistors are arranged in an array along the X and Z directions. The first interlayer isolation layer and the second interlayer isolation layer isolate the transistors arranged along the Z direction. There is no additional isolation structure between the multiple transistors arranged along the X direction. The occupied area of ​​a single transistor is reduced, which is conducive to improving the integration density of the semiconductor device.

[0152] Still as shown in FIG. 4F , in some embodiments, two sidewalls of the channel portion 228 opposite to each other in the second direction (ie, the Y direction) form a first source / drain 229 and a second source / drain 230 , respectively.

[0153] It should be noted that in the disclosed embodiment, the first source-drain 229 is used to connect to the bit line, and the second source-drain 230 is used to connect to the storage capacitor. When the first source-drain serves as the source of the transistor, the corresponding second source-drain serves as the drain of the transistor; when the first source-drain serves as the drain of the transistor, the corresponding second source-drain serves as the source of the transistor.

[0154] As shown in Figure 3M, in some embodiments, after filling the second gap 226 with an isolation material to form a second interlayer isolation layer 227, the manufacturing method further includes: etching and removing the semiconductor layer 203 in the fifth sub-stack structure 213 to form a third gap 231; at this time, the third gap 231 exposes the first source and drain 229.

[0155] It should be noted that, as previously described, if only the fourth sub-stack structure 212 of the stacked structure 202 is etched during the formation of the channel hole 215, then the semiconductor layer 203 within the second sub-stack structure 210 also needs to be removed, and a bit line contact structure is formed in the space occupied by the semiconductor layer 203 within the second sub-stack structure 210. If the fourth sub-stack structure 212 and the second sub-stack structure 210 of the stacked structure 202 have already been etched during the formation of the channel hole 215, then only the semiconductor layer 203 within the fifth sub-stack structure 213 needs to be removed to form the third gap 231.

[0156] Here, the process of forming the third gap 231 may include, but is not limited to, wet etching, dry etching, or a combination thereof.

[0157] As shown in FIG. 3N , in some embodiments, a conductive material is filled in the third gap 231 to form a plurality of bit lines 232 extending along the first direction (i.e., the X direction) and electrically connected to the first source and drain electrodes 229 . The plurality of first source and drain electrodes 229 arranged along the X direction are connected to the same bit line 232 .

[0158] Here, the material of the bit line 232 may include, but is not limited to, a metal, a metal compound, or an alloy. The metal may be, for example, copper, aluminum, tungsten, gold, or silver; the metal compound may be, for example, tantalum nitride or titanium nitride; and the alloy may be an alloy formed by at least two of the following metal elements: copper, aluminum, tungsten, gold, or silver.

[0159] Here, the process of forming the bit line 232 may include, but is not limited to, wet etching, dry etching, or a combination thereof.

[0160] In some embodiments, bit line extension lines may be further formed, and bottom portions of different bit line extension lines are connected to different bit lines.

[0161] Here, the materials of the bit line and the bit line extension line may be the same or different.

[0162] As shown in FIG3O , in some embodiments, after filling the second gap 226 with an isolation material to form a second interlayer isolation layer 227 , the manufacturing method further includes: etching away the semiconductor layer 203 in the third sub-stack structure 211 to form a fourth gap 233 ; at this time, the fourth gap 233 exposes the second source and drain 230 .

[0163] Here, the process of forming the fourth gap 233 may include, but is not limited to, wet etching, dry etching, or a combination thereof.

[0164] As shown in Figure 3P, in some embodiments, a storage capacitor 234 electrically connected to the second source and drain 230 is formed in the fourth gap 233. The storage capacitors 234 are arranged in an array along the X direction and the Z direction, and each storage capacitor 234 extends along the Y direction. This is conducive to increasing the aspect ratio of the storage capacitor, that is, the ratio of length to width or diameter, thereby increasing the distance between the storage capacitors of adjacent transistors and avoiding the generation of integrated capacitance between the storage capacitors. The present disclosure does not specifically limit the specific structure of the storage capacitor, and the storage capacitor structure in any related technical solution can be used in this solution.

[0165] In the embodiment of the present disclosure, the semiconductor layer 203 in the fifth sub-stacked structure 213 is first etched away to form the third gap 231, and then the semiconductor layer 203 in the third sub-stacked structure 211 is etched away to form the fourth gap 233; that is, the bit line 232 is formed first and then the storage capacitor 234 is formed.

[0166] In other embodiments, the fourth gap may be formed first and then the third gap, that is, the storage capacitor may be formed first and then the bit line. The present disclosure has no particular limitation on the process sequence of forming the third gap and the fourth gap.

[0167] In the embodiment illustrated in FIG. 3A to FIG. 3P , a threshold voltage adjustment structure 225 is formed in the threshold voltage adjustment hole 221 after the first interlayer isolation layer 224 is formed in the first gap 223 .

[0168] In some embodiments, after forming the first interlayer isolation layer in the first gap, a sacrificial structure can be formed in the threshold voltage adjustment hole, and after forming the bit line in the third gap and the storage capacitor in the fourth gap, the threshold voltage adjustment hole can be formed by etching, and the threshold voltage adjustment structure can be formed in the threshold voltage adjustment hole.

[0169] In other embodiments, a sacrificial structure may be formed in the threshold voltage adjustment hole after the first interlayer isolation layer is formed in the first gap, and a conductive material may be subsequently filled in the third gap and the threshold voltage adjustment hole at the same time to form a bit line in the third gap and a threshold voltage adjustment structure in the threshold voltage adjustment hole, respectively.

[0170] In the above embodiment, after filling the second gap 226 with an isolation material to form the second interlayer isolation layer 227, the manufacturing method further includes:

[0171] The semiconductor layer 203 in the fifth sub-stacked structure 213 is removed to form a third gap 231 ; the third gap 231 exposes the first source and drain 229 ;

[0172] A threshold voltage adjustment hole 221 is formed by etching through the first sub-stack structure 209 ; the threshold voltage adjustment hole 221 is located between adjacent channel holes 215 , and the remaining semiconductor layer 203 between the adjacent channel holes 215 serves as a back gate electrode 222 ;

[0173] Conductive material is simultaneously filled in the third gap 231 and the threshold voltage adjustment hole 221 to respectively form a plurality of bit lines 232 extending along the first direction (i.e., the X direction) and electrically connected to the first source and drain 229 and a threshold voltage adjustment structure 225 electrically connected to the back gate electrode 222; wherein the threshold voltage adjustment structure 225 is used to adjust the threshold voltage of the transistor 220.

[0174] Here, the process of forming the third gap 231 and the threshold voltage adjusting hole 221 may include, but is not limited to, wet etching, dry etching, or a combination thereof.

[0175] In the embodiment of the present disclosure, the third gap 231 and the threshold voltage adjustment hole 221 are filled with conductive material at the same time, which can save manufacturing time and reduce manufacturing costs.

[0176] 5A and 5B , FIG5A is a schematic diagram of a three-dimensional structure of a semiconductor device provided in an example, and FIG5B is a schematic diagram of an XY cross-sectional structure of a semiconductor device provided in an example. As shown in Figures 5A and 5B, an embodiment of the present disclosure provides a semiconductor device 200, which includes: a substrate (not shown in Figures 5A and 5B); a plurality of channel portions 228 arranged in an array along a first direction (i.e., the X direction) and a third direction (i.e., the Z direction); a gate electrode 219 extending along the Z direction and penetrating the channel portion 228; a second gate dielectric layer 218 located between the channel portion 228 and the gate electrode 219; the channel portion 228, the second gate dielectric layer 218, and the gate electrode 219 together constitute a transistor 220; a first gate dielectric layer 216 covering two sidewalls of each channel portion 228 arranged opposite each other along the X direction; a back gate electrode 222 located between adjacent transistors 220 arranged along the X direction; wherein the back gate electrode 222 is in direct contact with the first gate dielectric layer 216; and the back gate electrode 222 is used to adjust the threshold voltage of the transistor 220.

[0177] In some embodiments, the material of the channel portion 228 may include, but is not limited to, an oxide semiconductor material, for example, IGZO, ZTO, IZO, zinc oxide, IGSO, and indium oxide.

[0178] In some embodiments, the back gate electrode 222 may be made of P-type heavily doped polysilicon material with a doping concentration of 1E21-1E23 cm -3 , with a work function of 4 to 5.5 eV. Since the threshold voltage of transistors formed of IGZO material is generally negative, the provision of back-gate electrode 222 can adjust the threshold voltage of transistor 220 to a positive voltage, thereby reducing transistor leakage and extending the retention time of stored data.

[0179] By providing the back gate electrodes 222 between adjacent transistors 220 arranged along the X direction to separate the transistors 220 , no additional isolation structure is required, thereby improving the integration of the transistors 220 .

[0180] Here, the second gate dielectric layer 218 surrounds the gate electrode 219 , and the channel portion 228 surrounds the second gate dielectric layer 218 .

[0181] In some embodiments, two sidewalls of the channel portion 228 that are opposite to each other along the Y direction respectively constitute a first source and drain 229 (as indicated by the dotted box in FIG5B ) and a second source and drain 230 (as indicated by the dotted box in FIG5B ); the semiconductor device 200 further includes: a bit line 232 extending along the X direction, and a plurality of first source and drain electrodes 229 arranged along the X direction are connected to the same bit line 232; and a plurality of storage capacitors 234, and the storage capacitors 234 are connected to the second source and drain 230.

[0182] Here, a plurality of first source and drain electrodes 229 arranged along the Z direction are connected to different bit lines 232 .

[0183] In some embodiments, the first source / drain 229 and the second source / drain 230 are aligned with two opposite sidewalls of the back-gate electrode 222 along the Y direction. That is, in the Y direction, the size of the back-gate electrode 222 is equal to the spacing between the first source / drain 229 and the second source / drain 230. The plurality of first source / drains 229 arranged along the Z direction are connected to different bit lines 232 via bit line contact structures.

[0184] In some embodiments, a plurality of first source and drain electrodes 229 arranged along the Z direction are directly connected to different bit lines 232. The first source and drain electrodes 229 protrude from the sidewalls of the back gate electrode 222 along the Y direction. An isolation structure 214 is disposed between the back gate electrode 222 and the bit lines. The isolation structure 214 may include a low-k material, such as silicon oxide, silicon nitride, silicon carbide, silicon carbide nitride, or silicon oxynitride. The isolation structure 214 can reduce coupling between the bit lines 232 and the back gate electrode 222, thereby reducing parasitic capacitance therebetween.

[0185] In some embodiments, the first source and drain 229 and the second source and drain 230 are not aligned with the two side walls of the back gate electrode 222 that are opposite to each other along the Y direction. The first source and drain 229 protrudes from the side wall of the back gate electrode 222 along the Y direction and toward the bit line 232, and the second source and drain 230 protrudes from the side wall of the back gate electrode 222 along the Y direction and away from the bit line 232, thereby increasing the channel length of the channel portion 228 and reducing the short channel effect.

[0186] Referring to Figures 6A and 6B , Figure 6A is a schematic diagram of a three-dimensional structure of a semiconductor device according to an example, and Figure 6B is a schematic diagram of an XY cross-sectional structure of a semiconductor device according to an example. In some embodiments, the semiconductor device 200 further includes a threshold voltage adjustment structure 225 located between adjacent back-gate electrodes 222 of adjacent channel portions 228 arranged along the X direction. The threshold voltage adjustment structure 225 extends along the Z direction and electrically connects the plurality of back-gate electrodes 222 arranged along the Z direction. The threshold voltage adjustment structure 225 can be used to apply a voltage to the back-gate electrodes 222 to further adjust the threshold voltage of the transistor 220.

[0187] In some embodiments, the channel portion 228 is a ring-shaped structure parallel to the substrate; the dimension of the channel portion 228 along the Y direction is greater than or equal to the dimension of the back gate electrode 222 along the Y direction.

[0188] Here, the channel portions 228 are arranged in an array along the X direction and the Z direction, and each channel portion 228 is a ring structure parallel to the XY plane.

[0189] It should be understood that “one embodiment” or “an embodiment” mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present disclosure. Therefore, “in one embodiment” or “in an embodiment” appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present disclosure, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments.

[0190] The above description is only a preferred embodiment of the present disclosure and does not limit the patent scope of the present disclosure. All equivalent structural transformations made by using the contents of the present disclosure and the drawings under the inventive concept of the present disclosure, or direct / indirect application in other related technical fields are included in the patent protection scope of the present disclosure. Industrial Applicability

[0191] The present disclosure provides a semiconductor device and a method for manufacturing the same. In the disclosed embodiment, multiple channel holes are formed through a stacked structure, gate electrodes are formed within the channel holes, and the semiconductor layer within the stacked structure serves as a back-gate electrode. This back-gate electrode can be used to adjust the threshold voltage of the transistor.

Claims

1. A manufacturing method of a semiconductor device (200), the manufacturing method comprises: providing a substrate (201) and a stacked structure (202) located on the substrate (201), the stacked structure (202) including alternately stacked semiconductor layers (203) and interlayer insulating layers (204); forming a plurality of channel holes (215) penetrating through the stacked structure (202); wherein, the semiconductor layer (203) located between adjacent channel holes (215) is used to form a back gate electrode (222); performing an oxidation treatment on the semiconductor layer (203) exposed on the sidewalls of the channel holes (215) to form a first gate dielectric layer (216); sequentially forming a channel layer (217), a second gate dielectric layer (218), and a gate electrode (219) covering the sidewalls of the channel holes (215); wherein, the channel layer (217), the second gate dielectric layer (218), and the gate electrode (219) together form a transistor (220), and the back gate electrode (222) is used to adjust the threshold voltage of the transistor (220).

2. The manufacturing method of the semiconductor device (200) according to claim 1, wherein, before forming the plurality of channel holes (215) penetrating through the stacked structure (202), the manufacturing method further comprises: forming a plurality of groove groups (206) penetrating through the stacked structure (202) and arranged in a first direction, each groove group (206) including a first groove (207) and a second groove (208) arranged side by side in a second direction; the remaining stacked structure (202) includes a first sub-stacked structure (209) located between the first groove (207) and the second groove (208), a second sub-stacked structure (210) located between adjacent first grooves (207), a third sub-stacked structure (211) located between adjacent second grooves (208), a fourth sub-stacked structure (212) located between adjacent first sub-stacked structures (209), and a fifth sub-stacked structure (213) located on one side of the first groove (207) and the second sub-stacked structure (210); wherein, both the first direction and the second direction are parallel to the substrate (201) and the first direction and the second direction intersect; filling the first groove (207) and the second groove (208) with an isolation material to form an isolation structure (214).

3. The manufacturing method of the semiconductor device (200) according to claim 2, wherein, forming the plurality of channel holes (215) penetrating through the stacked structure (202) includes: etching at least the fourth sub-stacked structure (212) in the remaining stacked structure (202) to form a plurality of channel holes (215) penetrating through the stacked structure (214) and arranged in the first direction.

4. The manufacturing method of the semiconductor device (200) according to claim 3, wherein, After successively forming a channel layer (217), a second gate dielectric layer (218), and a gate electrode (219) that cover the sidewalls of the channel holes (215), the manufacturing method further includes: Removing the interlayer insulating layer (204) within the first sub-stack structure (209) to form a first gap (223); the first gap (223) exposes a part of the channel layer (217) that is oppositely disposed along the first direction; Removing the channel layer (217) exposed by the first gap (223); Filling the first gap (223) with an isolation material to form a first interlayer isolation layer (224).

5. The manufacturing method of the semiconductor device (200) according to claim 4, wherein, The removing the interlayer insulating layer (204) within the first sub-stack structure (209) to form a first gap (223) includes: Etching to form a threshold voltage adjustment hole (221) that penetrates the first sub-stack structure (209); the threshold voltage adjustment hole (221) is located between adjacent channel holes (215), and the remaining semiconductor layer (203) between adjacent channel holes (215) serves as a back gate electrode (222); Transversely etching along the threshold voltage adjustment hole (221) to remove the interlayer insulating layer (204) to form a first gap (223); the threshold voltage adjustment hole (221) and the first gap (223) are in communication.

6. The manufacturing method of the semiconductor device (200) according to claim 5, wherein, The filling the first gap (223) with an isolation material to form a first interlayer isolation layer (224) includes: Filling the first gap (223) and the threshold voltage adjustment hole (221) with an isolation material; Removing the isolation material within the threshold voltage adjustment hole (221); wherein, the isolation material located within the first gap (223) forms a first interlayer isolation layer (224); Filling the threshold voltage adjustment hole (221) with a conductive material to form a threshold voltage adjustment structure (225) that electrically connects the back gate electrode (222); wherein, the threshold voltage adjustment structure (225) is used to adjust the threshold voltage of the transistor (220).

7. The manufacturing method of the semiconductor device (200) according to any one of claims 4 to 6, wherein, After successively forming a channel layer (217), a second gate dielectric layer (218), and a gate electrode (219) that cover the sidewalls of the channel holes (215), the manufacturing method further includes: Removing the interlayer insulating layer (204) within the second sub-stack structure (210), the third sub-stack structure (211), and the fifth sub-stack structure (213) to form a second gap (226); the second gap (226) exposes a part of the channel layer (217) that is oppositely disposed along the second direction; Removing the channel layer (217) exposed by the second gap (226); An isolation material is filled in the second gap (226) to form a second interlayer isolation layer (227); wherein, the first interlayer isolation layer (224) and the second interlayer isolation layer (227) isolate the remaining channel layer (217) in each channel hole (215) into channel portions (228) of a plurality of transistors (220); first source / drain electrodes (229) and second source / drain electrodes (230) are respectively formed on two sidewalls of the channel portion (228) oppositely arranged in the second direction; a plurality of transistors (220) arranged in the third direction are connected to the same gate electrode (219); the third direction is perpendicular to the substrate (201).

8. The manufacturing method of the semiconductor device (200) according to claim 7, wherein, after filling the isolation material in the second gap (226) to form the second interlayer isolation layer (227), the manufacturing method further includes: removing the semiconductor layer (203) in the fifth sub-stack structure (213) to form a third gap (231); the third gap (231) exposes the first source / drain electrode (229); filling a conductive material in the third gap (231) to form a plurality of bit lines (232) extending along the first direction and electrically connected to the first source / drain electrode (229).

9. The manufacturing method of the semiconductor device (200) according to claim 7 or 8, wherein, after filling the isolation material in the second gap (226) to form the second interlayer isolation layer (227), the manufacturing method further includes: removing the semiconductor layer (203) in the third sub-stack structure (211) to form a fourth gap (233); the fourth gap (233) exposes the second source / drain electrode (230); forming a storage capacitor (234) electrically connected to the second source / drain electrode (230) in the fourth gap (223).

10. The manufacturing method of the semiconductor device (200) according to any one of claims 7 to 9, wherein, after filling the isolation material in the second gap (226) to form the second interlayer isolation layer (227), the manufacturing method further includes: removing the semiconductor layer (203) in the fifth sub-stack structure (213) to form a third gap (231); the third gap (231) exposes the first source / drain electrode (229); etching to form a threshold voltage adjustment hole (221) penetrating through the first sub-stack structure (209); the threshold voltage adjustment hole (221) is located between adjacent channel holes (215), and the remaining semiconductor layer (203) between adjacent channel holes (215) serves as a back gate electrode (222). A conductive material is filled in the third gap (231) and the threshold voltage adjustment hole (221) simultaneously to form a plurality of bit lines (232) extending along the first direction and electrically connected to the first source / drain (229) and a threshold voltage adjustment structure (225) electrically connected to the back gate electrode (222) respectively; wherein, the threshold voltage adjustment structure (225) is used for adjusting the threshold voltage of the transistor (220).

11. A semiconductor device (200), the semiconductor device (200) comprises: a substrate (201); a plurality of channel portions (228) arranged in an array along a first direction and a third direction, the first direction being parallel to the substrate (201), and the third direction being perpendicular to the substrate (201); a gate electrode (219) extending along the third direction and penetrating through the channel portions (228); a second gate dielectric layer (218) located between the channel portions (228) and the gate electrode (219); the channel portions (228), the second gate dielectric layer (218) and the gate electrode (219) together constitute a transistor (220); a first gate dielectric layer (216) covering two sidewalls of each of the channel portions (228) oppositely arranged along the first direction; a back gate electrode (222) located between adjacent transistors (220) arranged along the first direction; wherein, the back gate electrode (222) is in contact with the first gate dielectric layer (216); the back gate electrode (222) is used for adjusting the threshold voltage of the transistor (220).

12. The semiconductor device (200) according to claim 11, wherein, two sidewalls of the channel portion (228) oppositely arranged along a second direction respectively constitute a first source / drain (229) and a second source / drain (230); the second direction is parallel to the substrate (201) and intersects with the first direction; the semiconductor device (200) further comprises: a bit line (232) extending along the first direction, and a plurality of the first source / drains (229) arranged along the first direction are connected to the same bit line (232); a plurality of storage capacitors (234), and the storage capacitors (234) are connected to the second source / drain (230).

13. The semiconductor device (200) according to claim 11 or 12, wherein, the semiconductor device (200) further comprises: a threshold voltage adjustment structure (225) located between adjacent back gate electrodes (222) of adjacent channel portions (228) arranged along the first direction, the threshold voltage adjustment structure (225) extends along the third direction and is electrically connected to a plurality of back gate electrodes (222) arranged along the third direction.

14. The semiconductor device (200) according to any one of claims 11 to 13, wherein, the channel portion (228) is in a ring structure parallel to the substrate (201); the dimension of the channel portion (228) along the second direction is greater than or equal to the dimension of the back gate electrode (222) along the second direction.

15. The semiconductor device (200) according to any one of claims 11 to 13, wherein, the material of the back gate electrode (222) includes polysilicon.

16. The semiconductor device (200) according to claim 16, wherein, The doping concentration of the back gate electrode (222) is 1E21 to 1E23 cm -3 .

17. The semiconductor device (200) according to claim 12, wherein, an isolation structure (214) is provided between the back gate electrode (222) and the bit line (232).

18. The semiconductor device (200) according to claim 17, wherein, the material of the isolation structure (214) may include a low dielectric constant material.

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