Array substrate and display panel

Abstract

The present application provides an array substrate and a display panel. In the array substrate, the orthogonal projections of a first scanning line connected to a first oxide transistor and a second scanning line connected to a second oxide transistor on a substrate do not overlap with the orthogonal projections of a first connection line connected between the first oxide transistor and a first transistor and a second connection line connected between the first oxide transistor and the second oxide transistor on the substrate, so as to alleviate the problem of horizontal crosstalk.

Description

Array substrate and display panel Technical Field

[0001] The present application relates to the field of display technology, and in particular to an array substrate and a display panel. Background Art

[0002] Flat-panel display panels have numerous advantages, including thinness, power efficiency, and radiation-free design, and have therefore gained widespread adoption. Existing flat-panel display panels primarily include liquid crystal display (LCD) panels and organic light-emitting diode (OLED) panels. Thin-film transistors (TFTs) are a key component of flat-panel display panels. TFTs can be formed on glass or plastic substrates and are typically used as switching and driving components in flat-panel display panels such as LCDs and OLEDs.

[0003] Currently, most OLED panels use LTPS (Low Temperature Poly-silicon) TFT display panel technology. LTPS display panels offer advantages such as high resolution, high response speed, high brightness, and a high aperture ratio, but they also have the disadvantages of high production costs and high power consumption. Therefore, with the development of display technology, LTPO (Low Temperature Polycrystalline Oxide) display panel technology has emerged. This is a combination of LTPS and oxide display panel technologies, resulting in LTPO display panels containing both LTPS and oxide thin-film transistors. LTPO display panels not only have the advantages of LTPS display panels, such as high resolution, high response speed, high brightness, and a high aperture ratio, but also have the advantages of low production costs and low power consumption.

[0004] However, in current LTPO display panels, there is a large coupling capacitance between the scanning line of the oxide thin film transistor and the connection line connecting the Q point in the pixel circuit, resulting in serious lateral crosstalk problems in the LTPO display panel. SUMMARY OF THE INVENTION

[0005] The present application provides an array substrate and a display panel to alleviate the technical problem of severe lateral crosstalk in existing LTPO display panels.

[0006] To solve the above problems, the technical solutions provided by this application are as follows:

[0007] In a first aspect, an embodiment of the present application provides an array substrate comprising a substrate and a plurality of sub-pixels arranged in an array on the substrate, wherein each sub-pixel comprises a first transistor and a first oxide transistor and a second oxide transistor connected to the first transistor, wherein the drain of the first oxide transistor is connected to the gate of the first transistor and to the source of the second oxide transistor, and the drain of the second oxide transistor is connected to the drain of the first transistor;

[0008] The array substrate further includes:

[0009] a first connecting line connected between the drain of the first oxide transistor and the gate of the first transistor;

[0010] a second connecting line connected between the drain of the first oxide transistor and the source of the second oxide transistor;

[0011] a first scan line connected to the gate of the first oxide transistor; and

[0012] a second scanning line connected to the gate of the second oxide transistor;

[0013] The orthographic projection of the first scanning line on the substrate is separated from the orthographic projections of the first connecting line and the second connecting line on the substrate, and the orthographic projection of the second scanning line on the substrate is separated from the orthographic projections of the first connecting line and the second connecting line on the substrate.

[0014] In a second aspect, an embodiment of the present application further provides a display panel, comprising an array substrate, the array substrate comprising a substrate and a plurality of sub-pixels arrayed on the substrate, each of the sub-pixels comprising a first transistor and a first oxide transistor and a second oxide transistor connected to the first transistor, the drain of the first oxide transistor being connected to the gate of the first transistor and to the source of the second oxide transistor, and the drain of the second oxide transistor being connected to the drain of the first transistor;

[0015] The array substrate further includes:

[0016] a first connecting line connected between the drain of the first oxide transistor and the gate of the first transistor;

[0017] a second connecting line connected between the drain of the first oxide transistor and the source of the second oxide transistor;

[0018] a first scan line connected to the gate of the first oxide transistor; and

[0019] a second scanning line connected to the gate of the second oxide transistor;

[0020] The orthographic projection of the first scanning line on the substrate is separated from the orthographic projections of the first connecting line and the second connecting line on the substrate, and the orthographic projection of the second scanning line on the substrate is separated from the orthographic projections of the first connecting line and the second connecting line on the substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions in the embodiments or the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0022] FIG1 is a schematic diagram of a pixel circuit of a sub-pixel in an existing LTPO display panel.

[0023] FIG2 is a planar schematic diagram of a sub-pixel in an existing LTPO display panel.

[0024] FIG3 is a plan view of FIG2 with some vertical wiring removed.

[0025] FIG4 is a schematic diagram of the arrangement of pixels on an array substrate provided in an embodiment of the present application.

[0026] FIG. 5 is a schematic diagram of a pixel circuit of a sub-pixel in FIG. 3 .

[0027] FIG6 is a schematic plan view of a sub-pixel in FIG3 .

[0028] FIG. 7 is a plan view schematically showing the structure of FIG. 6 after the first data line and the first power line are removed.

[0029] FIG8 is a partial plan view of the second metal layer, the third metal layer, and the second semiconductor layer in FIG7 .

[0030] FIG9 is a schematic diagram of the film layer structure of part of the transistor in FIG7 . Modes for Carrying Out the Invention

[0031] The following descriptions of the embodiments are with reference to the attached diagrams to illustrate specific embodiments that the present application can be implemented in. The directional terms mentioned in this application, such as [up], [down], [front], [back], [left], [right], [inside], [outside], [side], etc., are only with reference to the directions of the attached drawings. Therefore, the directional terms used are used to illustrate and understand the present application, rather than to limit the present application. In the figures, units with similar structures are represented by the same reference numerals. In the accompanying drawings, the thickness of some layers and areas is exaggerated for clarity of understanding and ease of description. That is, the size and thickness of each component shown in the drawings are arbitrarily shown, but the present application is not limited to this.

[0032] In existing LTPO display panels, there is a large coupling capacitance between the scanning line of the oxide thin-film transistor and the connecting line connected to the Q point in the pixel circuit, which causes serious lateral crosstalk problems in the LTPO display panel. The inventors of this application found in their research that this is mainly because there is an overlapping area between the scanning line of the oxide thin-film transistor and the connecting line connected to the Q point in the pixel circuit, which in turn leads to a large coupling capacitance between the scanning line and the connecting line.

[0033] Specifically, referring to Figures 1 to 3, Figure 1 is a schematic diagram of the pixel circuit of a sub-pixel in a conventional LTPO display panel, Figure 2 is a plan view schematic diagram of a sub-pixel in a conventional LTPO display panel, and Figure 3 is a plan view schematic diagram after removing some vertical traces in Figure 2. With reference to Figures 1 to 3, each sub-pixel includes a first transistor T1, a second transistor T2, a third transistor T3, and a fourth transistor T4. The first transistor T1 and the second transistor T2 are both polysilicon transistors, the third transistor T3 and the fourth transistor T4 are oxide transistors, wherein the first transistor T1 is a drive transistor, and the second transistor T2 is a switch transistor.

[0034] The drain of the fourth transistor T4 is connected to the gate of the first transistor T1, and the drain of the fourth transistor T4 is also connected to the source of the third transistor T3. The gate of the fourth transistor T4 is connected to the first scan line Nscan-T4, which is arranged on the same layer as the gate of the fourth transistor T4. The drain of the third transistor T3 is connected to the drain of the first transistor T1, and the gate of the third transistor T3 is connected to the second scan line Nscan-T3. The gate of the third transistor T3 is arranged on the same layer as the gate of the fourth transistor T4, and the second scan line Nscan-T3 is arranged on the same layer as the gate of the third transistor T3. Point Q is located between the fourth transistor T4, the first transistor T1, and the third transistor T3. The voltage at point Q is also the voltage on the connection line ZL connecting the fourth transistor T4, the first transistor T1, and the third transistor T3.

[0035] 2 and 3 , there is an overlapping area OL between the second scan line Nscan-T3 and the connecting line ZL connecting the fourth transistor T4 and the first transistor T1, so that there is a large coupling capacitance between the second scan line Nscan-T3 and the connecting line ZL. The large coupling capacitance will seriously affect the potential of the Q point, thereby causing serious lateral crosstalk problems in the LTPO display panel.

[0036] To this end, the inventors of the present application, after further in-depth research, proposed an array substrate and a display panel to solve the above-mentioned problem of lateral crosstalk.

[0037] In an array substrate provided in an embodiment of the present application, the array substrate includes a substrate and a plurality of sub-pixels arranged in an array on the substrate, each of the sub-pixels includes a first transistor and a first oxide transistor and a second oxide transistor connected to the first transistor, the drain of the first oxide transistor being connected to the gate of the first transistor and to the source of the second oxide transistor, and the drain of the second oxide transistor being connected to the drain of the first transistor;

[0038] The array substrate further includes:

[0039] a first connecting line connected between the drain of the first oxide transistor and the gate of the first transistor;

[0040] a second connecting line connected between the drain of the first oxide transistor and the source of the second oxide transistor;

[0041] a first scan line connected to the gate of the first oxide transistor; and

[0042] a second scanning line connected to the gate of the second oxide transistor;

[0043] The orthographic projection of the first scanning line on the substrate is separated from the orthographic projections of the first connecting line and the second connecting line on the substrate, and the orthographic projection of the second scanning line on the substrate is separated from the orthographic projections of the first connecting line and the second connecting line on the substrate.

[0044] In the array substrate provided in an embodiment of the present application, the first scan line and the second scan line both extend along a first direction and are spaced apart along a second direction, and the first direction and the second direction are different; the first connecting line extends along the second direction, and the first scan line is located on a side of the first connecting line away from the first transistor or away from the first oxide transistor; and / or, the second scan line is located on a side of the first connecting line away from the first transistor or away from the first oxide transistor.

[0045] In the array substrate provided in the embodiment of the present application, in the second direction, the first transistor and the first oxide transistor are respectively located at two ends of the first connecting line, and the first scan line and the second scan line are both located on the side of the first connecting line away from the first transistor.

[0046] In the array substrate provided in an embodiment of the present application, in the second direction, the second oxide transistor is located between the first transistor and the first oxide transistor, the second connecting line is connected between the first oxide transistor and the second oxide transistor, and the first scanning line is located on the side of the second scanning line away from the second connecting line.

[0047] In the array substrate provided in the embodiment of the present application, the array substrate also includes a third connecting line and a fourth connecting line, and the third connecting line and the fourth connecting line both extend along the second direction, the third connecting line is connected between the first scanning line and the gate of the first oxide transistor, and the fourth connecting line is connected between the second scanning line and the gate of the second oxide transistor; the orthographic projection of the third connecting line on the substrate is separated from the orthographic projection of the first connecting line and the second connecting line on the substrate, and the orthographic projection of the fourth connecting line on the substrate is separated from the orthographic projection of the first connecting line and the second connecting line on the substrate.

[0048] In the array substrate provided in an embodiment of the present application, the gate of the first oxide transistor includes a first gate and a second gate arranged opposite to each other, the first gate is electrically connected to the second gate, and the third connecting line is electrically connected to one of the first gate and the second gate;

[0049] The gate of the second oxide transistor includes a third gate and a fourth gate that are oppositely disposed, the third gate is electrically connected to the fourth gate, and the fourth connection line is electrically connected to one of the third gate and the fourth gate.

[0050] In the array substrate provided in an embodiment of the present application, the gate of the first oxide transistor includes a first gate and a second gate arranged opposite to each other, the third connecting line includes a first sub-line and a second sub-line, the first sub-line is connected between the first scan line and the first gate, and the second sub-line is connected between the first scan line and the second gate;

[0051] The gate of the second oxide transistor includes a third gate and a fourth gate arranged opposite to each other, the fourth connecting line includes a third sub-line and a fourth sub-line, the third sub-line is connected between the second scan line and the third gate, and the fourth sub-line is connected between the second scan line and the fourth gate.

[0052] In the array substrate provided in the embodiment of the present application, the first gate and the third gate are arranged on the same layer, the second gate and the fourth gate are arranged on the same layer, the first sub-line and the first gate are arranged on the same layer, the second sub-line and the second gate are arranged on the same layer, the third sub-line and the third gate are arranged on the same layer, and the fourth sub-line and the fourth gate are arranged on the same layer.

[0053] In the array substrate provided in the embodiment of the present application, the first scan line and the first gate and the second gate are located in different layers, the second scan line and the third gate and the fourth gate are located in different layers, the first scan line is connected to the first sub-line through a first connection point, and is connected to the second sub-line through a second connection point, the second scan line is connected to one of the third sub-line and the fourth sub-line through a third connection point, and the third sub-line and the fourth sub-line are connected through a fourth connection point.

[0054] In the array substrate provided in an embodiment of the present application, the orthographic projection of the first sub-line on the substrate at least partially overlaps with the orthographic projection of the second sub-line on the substrate, and the orthographic projection of the third sub-line on the substrate at least partially overlaps with the orthographic projection of the fourth sub-line on the substrate.

[0055] In the array substrate provided in the embodiment of the present application, each of the sub-pixels further includes a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a storage capacitor, and a compensation capacitor, wherein the third transistor and the fourth transistor are oxide transistors, the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor are polysilicon transistors, the fourth transistor is the first oxide transistor, and the third transistor is the second oxide transistor;

[0056] In which, the drain of the fourth transistor is also connected to the first plate of the storage capacitor and the first plate of the compensation capacitor, the first plate of the storage capacitor is integrally arranged with the gate of the first transistor, the second plate of the compensation capacitor is connected to the gate of the second transistor, the second plate of the storage capacitor is connected to the source of the fifth transistor, the drain of the fifth transistor is connected to the source of the first transistor, the drain of the first transistor is connected to the drain of the third transistor and the source of the sixth transistor, the drain of the sixth transistor is connected to the drain of the seventh transistor, and the source of the first transistor, the drain of the second transistor and the drain of the fifth transistor are all connected to the drain of the eighth transistor.

[0057] In the array substrate provided in the embodiment of the present application, the array substrate further includes:

[0058] a first semiconductor layer disposed on the substrate, wherein the first semiconductor layer includes an active layer of the first transistor;

[0059] a first metal layer, disposed on a side of the first semiconductor layer away from the substrate, the first metal layer including a gate of the first transistor;

[0060] a second metal layer, disposed on a side of the first metal layer away from the first semiconductor layer;

[0061] a second semiconductor layer, disposed on a side of the second metal layer away from the first metal layer, the second semiconductor layer including the active layer of the first oxide transistor, the active layer of the second oxide transistor, the first connecting line, and the second connecting line;

[0062] a third metal layer, disposed on a side of the second semiconductor layer away from the second metal layer, wherein the gate of the first oxide transistor and the gate of the second oxide transistor are formed on the third metal layer and the second metal layer;

[0063] The fourth metal layer is disposed on a side of the third metal layer away from the second semiconductor layer, and the fourth metal layer includes the first scan line and the second scan line.

[0064] An embodiment of the application further provides a display panel, which includes the array substrate of one of the aforementioned embodiments.

[0065] In the array substrate and display panel provided in the present application, the array substrate includes a substrate and a plurality of sub-pixels arranged in an array on the substrate, each of the sub-pixels includes a first transistor and a first oxide transistor and a second oxide transistor connected to the first transistor, and the array substrate also includes: a first connecting line connected between the drain of the first oxide transistor and the gate of the first transistor; a second connecting line connected between the drain of the first oxide transistor and the source of the second oxide transistor; a first scanning line connected to the gate of the first oxide transistor, and a second scanning line connected to the gate of the second oxide transistor, the orthographic projection of the first scanning line on the substrate is separated from the orthographic projection of the first connecting line and the second connecting line on the substrate, and the orthographic projection of the second scanning line on the substrate is separated from the orthographic projection of the first connecting line and the second connecting line on the substrate, so that the first scanning line and the second scanning line have no overlapping parts with the first connecting line and the second connecting line, thereby reducing the coupling capacitance between the first scanning line and the second scanning line and the first connecting line and the second connecting line, thereby solving the technical problem of serious lateral crosstalk in the existing LTPO display panel.

[0066] The implementation of the above embodiments will be described in detail below with reference to the accompanying drawings:

[0067] Specifically, referring to Figures 4 to 9, Figure 4 is a schematic diagram of the pixel arrangement on an array substrate 100 provided in an embodiment of the present application. Figure 5 is a schematic diagram of the pixel circuit of a subpixel SP in Figure 3. Figure 6 is a plan view schematic diagram of a subpixel SP in Figure 3. Figure 7 is a plan view schematic diagram of Figure 6 with the first data line and the first power line removed. Figure 8 is a partial plan view schematic diagram of the second metal layer, the third metal layer, and the second semiconductor layer in Figure 7. Figure 9 is a schematic diagram of the film layer structure of a portion of the transistor in Figure 7. Referring to Figure 4, the array substrate 100 includes a substrate 10 and a plurality of pixels P arranged in an array on the substrate 10. Each pixel P includes at least three subpixels SP of different colors, for example, a red subpixel R, a green subpixel G, and a blue subpixel B. Subpixels SP of the same color are arranged in subpixel rows, and subpixels SP of different colors are arranged in subpixel columns.

[0068] 5 , 6 , and 7 , each of the sub-pixels SP includes a first transistor T1 and a first oxide transistor T4 and a second oxide transistor T3 connected to the first transistor T1. The drain of the first oxide transistor T4 is connected to the gate of the first transistor T1 and to the source of the second oxide transistor T3. The drain of the second oxide transistor T3 is connected to the drain of the first transistor T1.

[0069] Specifically, each sub-pixel SP includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a storage capacitor C1, and a compensation capacitor C2, wherein the third transistor T3 and the fourth transistor T4 are oxide transistors, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are polysilicon transistors, the fourth transistor T4 is a first oxide transistor T4, and the third transistor T3 is a second oxide transistor T3. In the following description, the first oxide transistor T4 and the second oxide transistor T3 are used for explanation. It should be noted that the embodiment of the present application only uses the pixel circuit architecture of 8T2C as an example to illustrate the structure of each sub-pixel SP, but the present application is not limited thereto. The sub-pixels SP of the present application may also adopt pixel circuit architectures such as 7T2C, 7T1C, 6T1C, and 5T1C.

[0070] 5 , the drain of the first oxide transistor T4 is further connected to the first plate of the storage capacitor C1 and the first plate of the compensation capacitor C2. The first plate of the storage capacitor C1 is integrally provided with the gate of the first transistor T1. The second plate of the compensation capacitor C2 is connected to the gate of the second transistor T2. The second plate of the storage capacitor C1 is connected to the source of the fifth transistor T5. The drain of the fifth transistor T5 is connected to the source of the first transistor T1. The drain of the first transistor T1 is connected to the drain of the second oxide transistor T3 and the source of the sixth transistor T6. The drain of the sixth transistor T6 is connected to the drain of the seventh transistor T7. The source of the first transistor T1, the drain of the second transistor T2, and the drain of the fifth transistor T5 are all connected to the drain of the eighth transistor T8.

[0071] 5 and 6 , the array substrate 100 further includes a plurality of scan lines and a plurality of signal lines, such as a first scan line Nscan-T4 connected to the gate of the first oxide transistor T4, a first signal line VI-T4-2 connected to the source of the first oxide transistor T4; a second scan line Nscan-T3 connected to the gate of the second oxide transistor T3; a third scan line Pscan connected to the gate of the second transistor T2, a first data line Data1 connected to the source of the second transistor T2; a second signal line EM1 connected to the gates of the fifth transistor T5 and the sixth transistor T6, a first power line VDD connected to the source of the fifth transistor T5; a fourth scan line Pscan2 connected to the gate of the seventh transistor T7, a third signal line VI-A-3 connected to the source of the seventh transistor T7; a fourth scan line Pscan2 connected to the gate of the eighth transistor T8, and a fourth signal line VI-T8-1 connected to the source of the eighth transistor T8.

[0072] Furthermore, the array substrate 100 further includes a first connecting line ZL1 and a second connecting line ZL2. The first connecting line ZL1 is connected between the drain of the first oxide transistor T4 and the gate of the first transistor T1. The second connecting line ZL2 is connected between the drain of the first oxide transistor T4 and the source of the second oxide transistor T3. The voltages on the first connecting line ZL1 and the second connecting line ZL2 both affect the potential of the Q point. The orthographic projection of the first scan line Nscan-T4 on the substrate 10 is separated from the orthographic projections of the first connecting line ZL1 and the second connecting line ZL2 on the substrate 10. The orthographic projection of the second scan line Nscan-T3 on the substrate 10 is separated from the orthographic projections of the first connecting line ZL1 and the second connecting line ZL2 on the substrate 10. Among them, adjacent orthographic projections means that there is no overlapping part between the two orthographic projections. For example, the orthographic projection of the first scanning line Nscan-T4 on the substrate 10 is separated from the orthographic projections of the first connecting line ZL1 and the second connecting line ZL2 on the substrate 10, which means that the orthographic projection of the first scanning line Nscan-T4 on the substrate 10 and the orthographic projections of the first connecting line ZL1 and the second connecting line ZL2 on the substrate 10 do not overlap.

[0073] In this way, the first scan line Nscan-T4 and the second scan line Nscan-T3 have no overlapping parts with the first connection line ZL1 and the second connection line ZL2, thereby reducing the coupling capacitance between the first scan line Nscan-T4 and the second scan line Nscan-T3 and the first connection line ZL1 and the second connection line ZL2, thereby solving the technical problem of severe lateral crosstalk in existing LTPO display panels.

[0074] The following will specifically describe how to achieve separation between the orthographic projections of the first scanning line Nscan-T4 and the second scanning line Nscan-T3 and the orthographic projections of the first connecting line ZL1 and the second connecting line ZL2.

[0075] 6 and 7 , the first scan line Nscan-T4 and the second scan line Nscan-T3 both extend along a first direction X and are spaced apart along a second direction Y. The first direction X and the second direction Y are different. For example, the first direction X is a row direction, the second direction Y is a column direction, and the first direction X is perpendicular to the second direction Y. The row direction is the arrangement direction of the sub-pixel rows, and the column direction is the arrangement direction of the sub-pixel columns. Optionally, the third scan line Pscan, the fourth scan line Pscan2, the first signal line VI-T4-2, the second signal line EM1, the third signal line VI-A-3, and the fourth signal line VI-T8-1 all extend along the first direction X, and the first data line Data1 and the first power line VDD both extend along the second direction Y.

[0076] The first connection line ZL1 extends along the second direction Y, and the first scan line Nscan-T4 is located on a side of the first connection line ZL1 away from the first transistor T1 or the first oxide transistor T4; and / or the second scan line Nscan-T3 is located on a side of the first connection line ZL1 away from the first transistor T1 or the first oxide transistor T4. This embodiment of the application uses an example in which both the first scan line Nscan-T4 and the second scan line Nscan-T3 are located on a side of the first connection line ZL1 away from the first transistor T1.

[0077] In the second direction Y, the first transistor T1 and the first oxide transistor T4 are respectively located at both ends of the first connection line ZL1, and the first scan line Nscan-T4 and the second scan line Nscan-T3 are both located on the side of the first connection line ZL1 away from the first transistor T1. Furthermore, in the second direction Y, the second oxide transistor T3 is located between the first transistor T1 and the first oxide transistor T4, and the second connection line ZL2 is connected between the first oxide transistor T4 and the second oxide transistor T3. The second connection line ZL2 first extends along the first direction and then extends along the second direction. The first scan line Nscan-T4 is located on the side of the second scan line Nscan-T3 away from the second connection line ZL2, which facilitates the connection between the first scan line Nscan-T4 and the first oxide transistor T4, and the connection between the second scan line Nscan-T3 and the second oxide transistor T3.

[0078] The connection between the first scan line Nscan-T4 and the first oxide transistor T4, and the connection between the second scan line Nscan-T3 and the second oxide transistor T3 can be achieved in the following manner:

[0079] Continuing with reference to Figures 6 and 7, the array substrate 100 further includes a third connection line ZL3 and a fourth connection line ZL4, both of which extend along the second direction Y. The third connection line ZL3 is connected between the first scan line Nscan-T4 and the gate of the first oxide transistor T4, and the fourth connection line ZL4 is connected between the second scan line Nscan-T3 and the gate of the second oxide transistor T3.

[0080] The orthographic projection of the third connecting line ZL3 on the substrate 10 is separated from the orthographic projections of the first connecting line ZL1 and the second connecting line ZL2 on the substrate 10. The orthographic projection of the fourth connecting line ZL4 on the substrate 10 is separated from the orthographic projections of the first connecting line ZL1 and the second connecting line ZL2 on the substrate 10. As such, the third connecting line ZL3 and the fourth connecting line ZL4 do not overlap with the first connecting line ZL1 and the second connecting line ZL2, thereby reducing the coupling capacitance between the third connecting line ZL3 and the fourth connecting line ZL4 and the first connecting line ZL1 and the second connecting line ZL2. This further improves the severe lateral crosstalk problem in existing LTPO display panels.

[0081] With reference to Figures 7 and 8 , the gate of the first oxide transistor T4 includes a first gate GE1 and a second gate GE2 disposed opposite each other. The third connecting line ZL3 includes a first sub-line ZL3-1 and a second sub-line ZL3-2. The first sub-line ZL3-1 is connected between the first scan line Nscan-T4 and the first gate GE1 of the first oxide transistor T4, and the second sub-line ZL3-2 is connected between the first scan line Nscan-T4 and the second gate GE2 of the first oxide transistor T4. The first gate GE1 and the second gate GE2 are located on different layers, and the orthographic projection of the first gate GE1 on the substrate 10 is within the range of the orthographic projection of the second gate GE2 on the substrate 10. The first sub-line ZL3-1 is disposed on the same layer as the first gate GE1, and the second sub-line ZL3-2 is disposed on the same layer as the second gate GE2.

[0082] The first scan line Nscan-T4 and the first gate GE1 and second gate GE2 of the first oxide transistor T4 are located on different layers. The first scan line Nscan-T4 is connected to the first sub-line ZL3-1 via a first connection point HD1 and to the second sub-line ZL3-2 via a second connection point HD2. In other words, the first sub-line ZL3-1 and the second sub-line ZL3-2 are connected to the first scan line Nscan-T4 via different connection points, and the voltages on the first sub-line ZL3-1 and the second sub-line ZL3-2 are the same. This allows the orthographic projections of the first sub-line ZL3-1 and the second sub-line ZL3-2 on the substrate 10 to at least partially overlap, saving wiring space.

[0083] Correspondingly, the gate of the second oxide transistor T3 includes a third gate GE3 and a fourth gate GE4 disposed opposite each other. The third gate GE3 is disposed on the same layer as the first gate GE1, and the fourth gate GE4 is disposed on the same layer as the second gate GE2. The fourth connecting line ZL4 includes a third sub-line ZL4-1 and a fourth sub-line ZL4-2. The third sub-line ZL4-1 is connected between the second scan line Nscan-T3 and the third gate GE3 of the second oxide transistor T3, and the fourth sub-line ZL4-2 is connected between the second scan line Nscan-T3 and the fourth gate GE4 of the second oxide transistor T3. The third gate GE3 and the fourth gate GE4 are located on different layers, and the orthographic projection of the third gate GE3 on the substrate 10 is within the range of the orthographic projection of the fourth gate GE4 on the substrate 10. The third sub-line ZL4-1 is disposed on the same layer as the third gate GE3, and the fourth sub-line ZL4-2 is disposed on the same layer as the fourth gate GE4.

[0084] The second scan line Nscan-T3 and the third gate GE3 and the fourth gate GE4 of the second oxide transistor T3 are located on different layers. The second scan line Nscan-T3 is connected to one of the third sub-line ZL4-1 and the fourth sub-line ZL4-2 via a third connection point HD3. This embodiment uses the example of the second scan line Nscan-T3 being connected to the third sub-line ZL4-1 via the third connection point HD3. The third sub-line ZL4-1 and the fourth sub-line ZL4-2 are connected via a fourth connection point HD4. That is, the third sub-line ZL4-1 and the fourth sub-line ZL4-2 are connected to the second scan line Nscan-T3 via different connection points, and the voltages on the third sub-line ZL4-1 and the fourth sub-line ZL4-2 are the same. This allows the orthographic projection of the third sub-line ZL4-1 on the substrate 10 to at least partially overlap with the orthographic projection of the fourth sub-line ZL4-2 on the substrate 10, thereby saving wiring space.

[0085] It should be noted that "disposed in the same layer" in this application means that during the manufacturing process, a film layer formed of the same material is patterned to obtain at least two different structures, and the at least two different structures are disposed in the same layer. For example, in this embodiment, the first sub-wire ZL3-1, the third sub-wire ZL4-1, the first gate GE1, and the third gate GE3 are obtained by patterning the same conductive film layer. Therefore, the first sub-wire ZL3-1, the third sub-wire ZL4-1, the first gate GE1, and the third gate GE3 are disposed in the same layer.

[0086] In another embodiment, the gate of the first oxide transistor T4 includes a first gate GE1 and a second gate GE2 arranged opposite to each other, the first gate GE1 is electrically connected to the second gate GE2, and the third connection line ZL3 is electrically connected to one of the first gate GE1 and the second gate GE2. That is, the first gate GE1 and the second gate GE2 are first electrically connected, and then one of the first gate GE1 and the second gate GE2 is electrically connected to the first scan line Nscan-T4 through the third connection line ZL3. In this way, the number of the third connection lines ZL3 can be saved, saving wiring space.

[0087] Correspondingly, the gate of the second oxide transistor T3 includes a third gate GE3 and a fourth gate GE4 arranged opposite to each other, the third gate GE3 is electrically connected to the fourth gate GE4, and the fourth connection line ZL4 is electrically connected to one of the third gate GE3 and the fourth gate GE4, that is, the third gate GE3 and the fourth gate GE4 are first electrically connected, and then one of the third gate GE3 and the fourth gate GE4 is electrically connected to the second scan line Nscan-T3 through the fourth connection line ZL4. In this way, the number of the fourth connection line ZL4 can be saved, saving wiring space.

[0088] Next, the positional relationship among the first scan line Nscan-T4, the second scan line Nscan-T3, the first connection line ZL1 and the second connection line ZL2 in the film structure of the array substrate 100 will be described using the first transistor T1 and the third transistor T3 in the sub-pixel SP as an example.

[0089] 7 and 9 , the array substrate 100 further includes:

[0090] The first semiconductor layer 20 is provided on the substrate 10, and the first semiconductor layer 20 includes the active layer AS of the first transistor T1; of course, the first semiconductor layer 20 also includes the active layers of the second transistor T2, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7 and the eighth transistor T8.

[0091] The first metal layer 30 is arranged on the side of the first semiconductor layer 20 away from the substrate 10. The first metal layer 30 includes the gate GE of the first transistor T1; of course, the first metal layer 30 also includes the gates of the second transistor T2, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7 and the eighth transistor T8.

[0092] The second metal layer 40 is arranged on the side of the first metal layer 30 away from the first semiconductor layer 20. The second metal layer 40 includes the second electrode 41 of the storage capacitor C1, the third gate GE3 of the second oxide transistor T3, and the third sub-line ZL4-1 connected to the third gate GE3; of course, the second metal layer 40 also includes the first gate GE1 of the first oxide transistor T4 and the first sub-line ZL3-1 connected to the first gate GE1.

[0093] The second semiconductor layer 50 is arranged on the side of the second metal layer 40 away from the first metal layer 30. The second semiconductor layer 50 includes the active layer OX of the second oxide transistor T3, the first connecting line ZL1 and the second connecting line ZL2 (it should be noted that the first connecting line ZL1 and the second connecting line ZL2 here can both be prepared by conducting the second semiconductor layer 50). The second connecting line ZL2 is schematically shown in Figure 9; of course, the second semiconductor layer 50 also includes the active layer of the first oxide transistor T4.

[0094] The third metal layer 60 is arranged on the side of the second semiconductor layer 50 away from the second metal layer 40. The third metal layer 60 includes the fourth gate GE4 of the second oxide transistor T3 and the fourth sub-line ZL4-2 connected to the fourth gate GE4, that is, the gate of the second oxide transistor T3 is formed in the third metal layer 60 and the second metal layer 40; of course, the third metal layer 60 also includes the second gate GE2 of the first oxide transistor T4 and the second sub-line ZL3-2 connected to the second gate GE2, that is, the gate of the first oxide transistor T4 is also formed in the third metal layer 60 and the second metal layer 40.

[0095] a fourth metal layer 70 disposed on a side of the third metal layer 60 away from the second semiconductor layer 50 , the fourth metal layer 70 including the first scan line Nscan-T4, the second scan line Nscan-T3, the drain D1 of the first transistor T1, and the drain D3 of the second oxide transistor T3, as schematically shown in FIG9 ;

[0096] The fifth metal layer 80 is disposed on a side of the fourth metal layer 70 away from the third metal layer 60 . The fifth metal layer 80 includes the first data line Data1 and the first power line VDD. FIG. 9 schematically shows the first data line Data1 .

[0097] The first metal layer 30, the second metal layer 40, the third metal layer 60, the fourth metal layer 70, and the fifth metal layer 80 can be formed of one or more metals selected from molybdenum (Mo), copper (Cu), aluminum (Al), titanium (Ti), or any combination thereof, or one or more alloys formed from other suitable materials. Furthermore, the first metal layer 30, the second metal layer 40, the third metal layer 60, the fourth metal layer 70, and the fifth metal layer 80 can also be a single-layer or multi-layer structure. The material of the first semiconductor layer 20 includes low-temperature polysilicon, etc. The second semiconductor layer 50 can be a single-layer or multi-layer structure formed of indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), or indium gallium zinc tin oxide (IGZTO).

[0098] Optionally, the array substrate 100 may further include a light-shielding layer 90 disposed between the substrate 10 and the first semiconductor layer 20. The light-shielding layer 90 includes a light-shielding electrode 91 disposed corresponding to the active layer AS of the first transistor T1 to shield the active layer AS of the first transistor T1 from light. The substrate 10 may be a rigid substrate or a flexible substrate. A rigid substrate may include a rigid substrate such as a glass substrate, a quartz substrate, or a silicon wafer. A flexible substrate may include a flexible substrate such as a polyimide (PI) film or an ultra-thin glass film. This embodiment of the present application uses a double-layer polyimide substrate as an example. The light-shielding layer 90 may be made of a material with light-shielding properties, such as a light-shielding metal.

[0099] Of course, the array substrate 100 also includes multiple insulating layers arranged between each metal layer and semiconductor layer, for example, the multiple insulating layers include: a first buffer layer 11 arranged between the substrate 10 and the light-shielding layer 90; a second buffer layer 12 arranged between the light-shielding layer 90 and the first semiconductor layer 20; a first gate insulating layer 13 arranged between the first semiconductor layer 20 and the first metal layer 30; a second gate insulating layer 14 arranged between the first metal layer 30 and the second metal layer 40; a third gate insulating layer 15 arranged between the second metal layer 40 and the second semiconductor layer 50; a fourth gate insulating layer 16 arranged between the second semiconductor layer 50 and the third metal layer 60; an interlayer insulating layer 17 arranged between the third metal layer 60 and the fourth metal layer 70; a first planarization layer 18 arranged between the fourth metal layer 70 and the fifth metal layer 80; and a second planarization layer 19 covering the fifth metal layer 80. The first buffer layer 11, the second buffer layer 12, the first gate insulating layer 13, the second gate insulating layer 14, the third gate insulating layer 15, the fourth gate insulating layer 16, and the interlayer insulating layer 17 are made of inorganic materials such as silicon oxide and silicon nitride. The first planarization layer 18 and the second planarization layer 19 are made of organic materials such as organic photoresist.

[0100] Based on the same inventive concept, an embodiment of the present application further provides a display panel, which includes the array substrate 100 of one of the aforementioned embodiments. The display panel includes an organic light emitting diode display panel, etc.

[0101] According to the above embodiments, it can be seen that:

[0102] The present application provides an array substrate and a display panel, wherein the array substrate includes a substrate and a plurality of sub-pixels arranged in an array on the substrate, each of the sub-pixels including a first transistor and a first oxide transistor and a second oxide transistor connected to the first transistor, and the array substrate further includes: a first connecting line connected between the drain of the first oxide transistor and the gate of the first transistor; a second connecting line connected between the drain of the first oxide transistor and the source of the second oxide transistor; a first scanning line connected to the gate of the first oxide transistor, and a second scanning line connected to the gate of the second oxide transistor, wherein the orthographic projection of the first scanning line on the substrate is separated from the orthographic projections of the first connecting line and the second connecting line on the substrate, and the orthographic projection of the second scanning line on the substrate is separated from the orthographic projections of the first connecting line and the second connecting line on the substrate, so that the first scanning line and the second scanning line have no overlapping parts with the first connecting line and the second connecting line, thereby reducing the coupling capacitance between the first scanning line and the second scanning line and the first connecting line and the second connecting line, thereby solving the technical problem of severe lateral crosstalk in existing LTPO display panels.

[0103] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0104] The above is a detailed introduction to the embodiments of the present application. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. An array substrate, which includes a substrate and a plurality of sub-pixels arranged in an array on the substrate. Each sub-pixel includes a first transistor, a first oxide transistor, and a second oxide transistor connected to the first transistor. The drain of the first oxide transistor is connected to the gate of the first transistor and is also connected to the source of the second oxide transistor. The drain of the second oxide transistor is connected to the drain of the first transistor. The array substrate further includes: A first connection line connected between the drain of the first oxide transistor and the gate of the first transistor; A second connection line connected between the drain of the first oxide transistor and the source of the second oxide transistor; A first scan line connected to the gate of the first oxide transistor; and A second scan line connected to the gate of the second oxide transistor; Wherein, the orthographic projection of the first scan line on the substrate is separated from the orthographic projections of the first connection line and the second connection line on the substrate, and the orthographic projection of the second scan line on the substrate is separated from the orthographic projections of the first connection line and the second connection line on the substrate.

2. The array substrate according to claim 1, Wherein, Both the first scan line and the second scan line extend along a first direction and are arranged at intervals along a second direction, and the first direction and the second direction are different; the first connection line extends along the second direction, and the first scan line is located on one side of the first connection line away from the first transistor or away from the first oxide transistor; And / or, the second scan line is located on one side of the first connection line away from the first transistor or away from the first oxide transistor.

3. The array substrate according to claim 2, Wherein, In the second direction, the first transistor and the first oxide transistor are respectively located at both ends of the first connection line, and both the first scan line and the second scan line are located on the side of the first connection line away from the first transistor.

4. The array substrate according to claim 3, Wherein, In the second direction, the second oxide transistor is located between the first transistor and the first oxide transistor, the second connection line is connected between the first oxide transistor and the second oxide transistor, and the first scan line is located on the side of the second scan line away from the second connection line.

5. The array substrate according to claim 2, Wherein, The array substrate further includes a third connection line and a fourth connection line. Both the third connection line and the fourth connection line extend along the second direction. The third connection line is connected between the first scan line and the gate of the first oxide transistor, and the fourth connection line is connected between the second scan line and the gate of the second oxide transistor; The positive projection of the third connection line on the substrate is separated from the positive projections of the first connection line and the second connection line on the substrate, and the positive projection of the fourth connection line on the substrate is separated from the positive projections of the first connection line and the second connection line on the substrate.

6. The array substrate according to claim 5, wherein, the gate of the first oxide transistor includes a first gate and a second gate which are oppositely arranged, the first gate is electrically connected to the second gate, and the third connection line is electrically connected to one of the first gate and the second gate; the gate of the second oxide transistor includes a third gate and a fourth gate which are oppositely arranged, the third gate is electrically connected to the fourth gate, and the fourth connection line is electrically connected to one of the third gate and the fourth gate.

7. The array substrate according to claim 5, wherein, the gate of the first oxide transistor includes a first gate and a second gate which are oppositely arranged, the third connection line includes a first sub-line and a second sub-line, the first sub-line is connected between the first scan line and the first gate, and the second sub-line is connected between the first scan line and the second gate; the gate of the second oxide transistor includes a third gate and a fourth gate which are oppositely arranged, the fourth connection line includes a third sub-line and a fourth sub-line, the third sub-line is connected between the second scan line and the third gate, and the fourth sub-line is connected between the second scan line and the fourth gate.

8. The array substrate according to claim 7, wherein, the first gate and the third gate are arranged in the same layer, the second gate and the fourth gate are arranged in the same layer, the first sub-line and the first gate are arranged in the same layer, the second sub-line and the second gate are arranged in the same layer, the third sub-line and the third gate are arranged in the same layer, and the fourth sub-line and the fourth gate are arranged in the same layer.

9. The array substrate according to claim 8, wherein, the first scan line and the first gate and the second gate are located in different layers, the second scan line and the third gate and the fourth gate are located in different layers, the first scan line is connected to the first sub-line through a first connection point and is connected to the second sub-line through a second connection point, the second scan line is connected to one of the third sub-line and the fourth sub-line through a third connection point, and the third sub-line and the fourth sub-line are connected through a fourth connection point.

10. The array substrate according to claim 7, wherein, the positive projection of the first sub-line on the substrate at least partially overlaps with the positive projection of the second sub-line on the substrate, and the positive projection of the third sub-line on the substrate at least partially overlaps with the positive projection of the fourth sub-line on the substrate.

11. The array substrate according to claim 1, wherein, Each of the sub-pixels further includes a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a storage capacitor, and a compensation capacitor. Among them, the third transistor and the fourth transistor are oxide transistors, the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor are polysilicon transistors, the fourth transistor is the first oxide transistor, and the third transistor is the second oxide transistor; Among them, the drain of the fourth transistor is further connected to the first electrode plate of the storage capacitor and the first electrode plate of the compensation capacitor. The first electrode plate of the storage capacitor is integrally provided with the gate of the first transistor. The second electrode plate of the compensation capacitor is connected to the gate of the second transistor. The second electrode plate of the storage capacitor is connected to the source of the fifth transistor. The drain of the fifth transistor is connected to the source of the first transistor. The drain of the first transistor is connected to the drain of the third transistor and the source of the sixth transistor. The drain of the sixth transistor is connected to the drain of the seventh transistor. The source of the first transistor, the drain of the second transistor, and the drain of the fifth transistor are all connected to the drain of the eighth transistor.

12. The array substrate according to claim 1, wherein, the array substrate further includes: a first semiconductor layer disposed on the substrate, and the first semiconductor layer includes the active layer of the first transistor; a first metal layer disposed on a side of the first semiconductor layer away from the substrate, and the first metal layer includes the gate of the first transistor; a second metal layer disposed on a side of the first metal layer away from the first semiconductor layer; a second semiconductor layer disposed on a side of the second metal layer away from the first metal layer, and the second semiconductor layer includes the active layer of the first oxide transistor, the active layer of the second oxide transistor, the first connection line, and the second connection line; a third metal layer disposed on a side of the second semiconductor layer away from the second metal layer, and the gate of the first oxide transistor and the gate of the second oxide transistor are formed between the third metal layer and the second metal layer; a fourth metal layer disposed on a side of the third metal layer away from the second semiconductor layer, and the fourth metal layer includes the first scan line and the second scan line.

13. A display panel, which includes an array substrate. The array substrate includes a substrate and a plurality of sub-pixels arranged in an array on the substrate. Each of the sub-pixels includes a first transistor, a first oxide transistor, and a second oxide transistor connected to the first transistor. The drain of the first oxide transistor is connected to the gate of the first transistor and is connected to the source of the second oxide transistor. The drain of the second oxide transistor is connected to the drain of the first transistor; the array substrate further includes: The first connection line is connected between the drain of the first oxide transistor and the gate of the first transistor; The second connection line is connected between the drain of the first oxide transistor and the source of the second oxide transistor; The first scanning line is connected to the gate of the first oxide transistor; and The second scanning line is connected to the gate of the second oxide transistor; Wherein, the orthographic projection of the first scanning line on the substrate is separated from the orthographic projections of the first connection line and the second connection line on the substrate, and the orthographic projection of the second scanning line on the substrate is separated from the orthographic projections of the first connection line and the second connection line on the substrate.

14. The display panel according to claim 13, Wherein, Both the first scanning line and the second scanning line extend along a first direction and are spaced apart along a second direction, and the first direction and the second direction are different; the first connection line extends along the second direction, and the first scanning line is located on one side of the first connection line away from the first transistor or away from the first oxide transistor; And / or, the second scanning line is located on one side of the first connection line away from the first transistor or away from the first oxide transistor.

15. The display panel according to claim 14, Wherein, In the second direction, the first transistor and the first oxide transistor are respectively located at two ends of the first connection line, and both the first scanning line and the second scanning line are located on the side of the first connection line away from the first transistor.

16. The display panel according to claim 15, Wherein, In the second direction, the second oxide transistor is located between the first transistor and the first oxide transistor, the second connection line is connected between the first oxide transistor and the second oxide transistor, and the first scanning line is located on the side of the second scanning line away from the second connection line.

17. The display panel according to claim 14, Wherein, The array substrate further includes a third connection line and a fourth connection line, both the third connection line and the fourth connection line extend along the second direction, the third connection line is connected between the first scanning line and the gate of the first oxide transistor, and the fourth connection line is connected between the second scanning line and the gate of the second oxide transistor; The orthographic projection of the third connection line on the substrate is separated from the orthographic projections of the first connection line and the second connection line on the substrate, and the orthographic projection of the fourth connection line on the substrate is separated from the orthographic projections of the first connection line and the second connection line on the substrate.

18. The display panel according to claim 17, Wherein, The gate of the first oxide transistor includes a first gate and a second gate arranged oppositely, the first gate and the second gate are electrically connected, and the third connection line is electrically connected to one of the first gate and the second gate; The gate of the second oxide transistor includes a third gate and a fourth gate which are oppositely arranged. The third gate is electrically connected to the fourth gate, and the fourth connection line is electrically connected to one of the third gate and the fourth gate.

19. The display panel according to claim 17, wherein, the gate of the first oxide transistor includes a first gate and a second gate which are oppositely arranged. The third connection line includes a first sub-line and a second sub-line. The first sub-line is connected between the first scan line and the first gate, and the second sub-line is connected between the first scan line and the second gate; the gate of the second oxide transistor includes a third gate and a fourth gate which are oppositely arranged. The fourth connection line includes a third sub-line and a fourth sub-line. The third sub-line is connected between the second scan line and the third gate, and the fourth sub-line is connected between the second scan line and the fourth gate.

20. The display panel according to claim 19, wherein, the first gate and the third gate are arranged on the same layer, the second gate and the fourth gate are arranged on the same layer, the first sub-line and the first gate are arranged on the same layer, the second sub-line and the second gate are arranged on the same layer, the third sub-line and the third gate are arranged on the same layer, and the fourth sub-line and the fourth gate are arranged on the same layer.

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