Stack substrate and method for manufacturing stack substrate

Abstract

This stack substrate includes a first substrate, a second substrate, and an electronic component. The first substrate has a first base material and a first wiring layer formed of a conductive material on a first main surface of the first base material. The second substrate has a second base material, and a second wiring layer formed of a conductive material on a second main surface of the second base material. A recess is formed in the first main surface. The second main surface faces the recess, and has a component arrangement region in which the electronic component is disposed. The electronic component is connected to the second wiring layer in a space defined by the recess and the component arrangement region. One of the first wiring layer and the second wiring layer has a protrusion. A groove is formed in the other of the first wiring layer and the second wiring layer. The protrusion and the groove surround the component arrangement region in the plan view. The first base material and the second base material are stacked such that the first main surface and the second main surface face each other by the groove and the protruding section being fitted.

Description

Stack substrate and method for manufacturing the stack substrate

[0001] The present disclosure relates to a stack substrate and a method for manufacturing a stack substrate.

[0002] Japanese Patent Laid-Open Publication No. 2017-112015 (Patent Document 1) describes a stack substrate. The stack substrate described in Patent Document 1 has a first substrate and a second substrate. The first substrate has a first main surface. The second substrate has a second main surface. The first substrate and the second substrate are arranged overlapping each other with the first main surface and the second main surface facing each other. A concave fitting portion is formed on the first main surface. A convex fitting portion is formed on the second main surface. When the first substrate and the second substrate are overlapped, the concave fitting portion and the convex fitting portion are fitted together.

[0003] Japanese Patent Application Laid-Open No. 2017-112015

[0004] In the stacked substrate described in Patent Document 1, the concave and convex mating portions are not formed of metal, and the concave and convex mating portions do not have an electromagnetic shielding function. This disclosure has been made in consideration of the problems of the conventional technology described above. More specifically, this disclosure provides a stacked substrate that can electromagnetically shield circuit blocks.

[0005] The stack substrate of the present disclosure includes a first substrate, a second substrate, and an electronic component. The first substrate has a first base material and a first wiring layer formed of a conductive material on a first main surface of the first substrate. The second substrate has a second base material and a second wiring layer formed of a conductive material on a second main surface of the second substrate. A recess is formed in the first main surface. The second main surface faces the recess and has a component placement area in which an electronic component is placed. The electronic component is connected to the second wiring layer within a space defined by the recess and the component placement area. One of the first wiring layer and the second wiring layer has a protrusion. The other of the first wiring layer and the second wiring layer has a groove. The protrusion and the groove surround the component placement area in a plan view. The first substrate and the second substrate are stacked such that the groove and the protrusion fit together and the first main surface and the second main surface face each other.

[0006] According to the stack substrate of the present disclosure, the circuit blocks can be electromagnetically shielded.

[0007] 1 is a cross-sectional view of a stack substrate 100. FIG. 2 is a diagram illustrating a manufacturing process of the stack substrate 100. FIG. 3 is a cross-sectional view illustrating a preparation step S11. FIG. 4 is a cross-sectional view illustrating a substrate processing step S12. FIG. 5 is a cross-sectional view illustrating a first plating step S13. FIG. 6 is a cross-sectional view illustrating a wiring layer patterning step S14. FIG. 7 is a cross-sectional view illustrating a second plating step S15. FIG. 8 is a cross-sectional view illustrating a preparation step S21. FIG. 9 is a cross-sectional view illustrating a substrate processing step S22. FIG. 10 is a cross-sectional view illustrating a first plating step S23. FIG. 11 is a cross-sectional view illustrating a wiring layer patterning step S24. FIG. 12 is a cross-sectional view illustrating a second plating step S25. FIG. 13 is a cross-sectional view illustrating an electronic component mounting step S4. FIG. 14 is a perspective view of a substrate 20 in a stack substrate 100 according to a first modification. FIG. 15 is a cross-sectional view of a stack substrate 100 according to a second modification. FIG. 16 is a cross-sectional view of a stack substrate 200.

[0008] First Embodiment A stack substrate according to the first embodiment will be described. The stack substrate according to the first embodiment is designated as a stack substrate 100.

[0009] (Configuration of Stack Substrate 100) The configuration of the stack substrate 100 will be described below.

[0010] Fig. 1 is a cross-sectional view of a stack substrate 100. As shown in Fig. 1, the stack substrate 100 includes a substrate 10, a substrate 20, a substrate 30, an electronic component 40, and an electronic component 41.

[0011] The substrate 10 has a base material 11, a wiring layer 12, and a wiring layer 13. The base material 11 has a main surface 11a and a main surface 11b. The main surface 11a and the main surface 11b are end surfaces in the thickness direction of the base material 11. The main surface 11b is the surface opposite to the main surface 11a. A through hole 11c is formed in the base material 11. The through hole 11c penetrates the base material 11 in the thickness direction. The base material 11 is made of glass cloth and a resin material impregnated into the glass cloth.

[0012] A recess 11d is formed in the main surface 11a. The main surface 11a is recessed toward the main surface 11b at the recess 11d. A recess 11e is formed in the main surface 11b. The main surface 11b is recessed toward the main surface 11a at the recess 11e.

[0013] The wiring layer 12 is disposed on the main surface 11a. The wiring layer 13 is disposed on the main surface 11b. Each of the wiring layer 12 and the wiring layer 13 has an underlayer 14 and a plating layer 15. The underlayer 14 has a first layer 14a and a second layer 14b. The constituent materials of the underlayer 14 and the plating layer 15 are, for example, copper, nickel, gold, etc.

[0014] The first layer 14a, which forms part of the wiring layer 12, is disposed on the main surface 11a. The first layer 14a, which forms part of the wiring layer 13, is disposed on the main surface 11b. The second layer 14b is disposed on the first layer 14a. The second layer 14b is also disposed on the inner wall surface of the through hole 11c. The wiring layer 12 and the wiring layer 13 are electrically connected to each other by the second layer 14b disposed on the inner wall surface of the through hole 11c. The second layer 14b is also disposed on the bottom and side surfaces of the recess 11d and the bottom and side surfaces of the recess 11e. Note that on the bottom and side surfaces of the recess 11d and the bottom and side surfaces of the recess 11e, the base layer 14 is composed only of the second layer 14b.

[0015] The plating layer 15 is disposed on the underlayer 14. However, the plating layer 15 is not disposed on the underlayer 14 (second layer 14b) on the bottom and side surfaces of the recess 11d and the bottom and side surfaces of the recess 11e. The through hole 11c is filled with a filling material 16. The constituent material of the filling material 16 is, for example, copper, a conductive resin compounded with metal powder and resin, a hole filling resin, etc.

[0016] The substrate 20 has a base material 21, a wiring layer 22, and a wiring layer 23. The base material 21 has a main surface 21a and a main surface 21b. The main surfaces 21a and 21b are end surfaces of the base material 21 in the thickness direction. The main surface 21b is the surface opposite to the main surface 21a. A through hole 21c is formed in the base material 21. The through hole 21c penetrates the base material 21 in the thickness direction. The base material 21 is made of glass cloth and a resin material impregnated into the glass cloth. The main surface 21a has a component placement region 21d.

[0017] The wiring layer 22 is disposed on the main surface 21 a. The wiring layer 23 is disposed on the main surface 21 b. Each of the wiring layer 22 and the wiring layer 23 has an underlayer 24 and a plating layer 25. The underlayer 24 has a first layer 24 a and a second layer 24 b. The constituent materials of the underlayer 24 and the plating layer 25 are, for example, copper, nickel, gold, etc.

[0018] The first layer 24a, which forms part of the wiring layer 22, is disposed on the main surface 21a. The first layer 24a, which forms part of the wiring layer 23, is disposed on the main surface 21b. The second layer 24b is disposed on the first layer 24a. The second layer 24b is also disposed on the inner wall surface of the through hole 21c. The wiring layer 22 and the wiring layer 23 are electrically connected to each other by the second layer 24b disposed on the inner wall surface of the through hole 21c. The plating layer 25 is disposed on the underlayer 24. The through hole 21c is filled with a filling material 26. The constituent material of the filling material 26 is, for example, a conductive resin formed by compounding copper, metal powder, and resin, a hole filling resin, etc.

[0019] The substrate 30 has a base material 31, a wiring layer 32, and a wiring layer 33. The base material 31 has a main surface 31a and a main surface 31b. The main surfaces 31a and 31b are end surfaces of the base material 31 in the thickness direction. The main surface 31b is the surface opposite to the main surface 31a. A through hole 31c is formed in the base material 31. The through hole 31c penetrates the base material 31 in the thickness direction. The base material 31 is made of glass cloth and a resin material impregnated into the glass cloth. The main surface 31a has a component placement area 31d.

[0020] The wiring layer 32 is disposed on the main surface 31a. The wiring layer 33 is disposed on the main surface 31b. Each of the wiring layer 32 and the wiring layer 33 has an underlayer 34 and a plating layer 35. The underlayer 34 has a first layer 34a and a second layer 34b. The constituent materials of the underlayer 34 and the plating layer 35 are, for example, copper, nickel, gold, etc.

[0021] The first layer 34a, which forms part of the wiring layer 32, is disposed on the main surface 31a. The first layer 34a, which forms part of the wiring layer 33, is disposed on the main surface 31b. The second layer 34b is disposed on the first layer 34a. The second layer 34b is also disposed on the inner wall surface of the through hole 31c. The wiring layer 32 and the wiring layer 33 are electrically connected to each other by the second layer 34b disposed on the inner wall surface of the through hole 31c. The plating layer 35 is disposed on the base layer 34. The through hole 31c is filled with a filling material 36. The filling material 36 may be made of, for example, a conductive resin formed by compounding copper, metal powder, and resin, or a hole filling resin.

[0022] The substrates 10, 20, and 30 are stacked. When the substrates 10, 20, and 30 are stacked, the main surfaces 11a and 21a face each other, and the main surfaces 11b and 31a face each other. When the substrates 10, 20, and 30 are stacked, the recess 11d faces the component placement area 21d, and the recess 11e faces the component placement area 31d.

[0023] A groove 12a is formed in the wiring layer 12. A groove 13a is formed in the wiring layer 13. The groove 12a is formed in a plating layer 15 that forms part of the wiring layer 12. The groove 13a is formed in a plating layer 15 that forms part of the wiring layer 13. The wiring layer 22 has a protruding portion 22a. The protruding portion 22a is made of a plating layer 25 that forms part of the wiring layer 22. The wiring layer 32 has a protruding portion 32a. The protruding portion 32a is made of a plating layer 35 that forms part of the wiring layer 32.

[0024] The protrusion 22a surrounds the component placement region 21d in a plan view. The protrusion 32a surrounds the component placement region 31d in a plan view. The protrusion 22a may extend around the periphery of the component placement region 21d multiple times in a plan view, and the protrusion 32a may extend around the periphery of the component placement region 21d multiple times in a plan view.

[0025] Groove 12a surrounds component placement region 21d in plan view. Groove 13a surrounds component placement region 31d in plan view. Groove 12a may extend around component placement region 21d multiple times in plan view, and groove 13a may extend around component placement region 31d multiple times in plan view.

[0026] The protrusions 22a and 32a face the grooves 12a and 13a, respectively. The substrates 10, 20, and 30 are held in a stacked state by fitting the protrusions 22a and 32a into the grooves 12a and 13a, respectively. Although not shown, the substrates 10, 20, and 30 may be fixed to each other by screwing or the like after fitting the protrusions 22a and 32a into the grooves 12a and 13a, respectively.

[0027] The protrusions 22a and 32a may be formed on the through holes 21c on which the second layer 24b is formed and filled with the filling material 26, and on the through holes 31c on which the second layer 34b is formed and filled with the filling material 36, respectively. The grooves 12a facing the protrusions 22a and the grooves 13a facing the protrusions 32a may be formed on the through holes 11c on which the second layer 14b is formed and filled with the filling material 16. This allows the protrusions 22a and 32a to fit into the grooves 12a and 13a directly above the through holes 11c, 21c, and 31c, respectively, improving the thermal conductivity between the substrates 10, 20, and 30.

[0028] That is, the stack substrate 100 has a first via hole portion and a second via hole portion. The first via hole portion is composed of a through hole 11c penetrating the substrate 10, a second layer 14b of the base layer 14 provided on the inner wall surface of the through hole 11c, and a filling material 16 that fills the through hole 11c with the second layer 14b. The second via hole portion is composed of a through hole 21c penetrating the substrate 20, a second layer 24b of the base layer 24 provided on the inner wall surface of the through hole 21c, and a filling material 26 that fills the through hole 21c with the second layer 24b.

[0029] A plating layer 15 is formed in a first via hole portion including the filling material 16 on the main surface 11a, and a plating layer 25 is formed in a second via hole portion including the filling material 26 on the main surface 21a. A protrusion 22a is formed in the plating layer 25 on the second via hole. A groove 12a is formed in the plating layer 15 on the first via hole. The groove 12a and the protrusion 22a are fitted together, and the substrates 10 and 20 are stacked together such that the first via hole portion on the main surface 11a and the second via hole portion on the main surface 21a face each other. Alternatively, a groove may be formed in the plating layer 25 on the second via hole, and a protrusion may be formed in the plating layer 15 on the first via hole, and the groove and the protrusion may be fitted together, such that the first via hole portion on the main surface 11a and the second via hole portion on the main surface 21a face each other, and the substrates 10 and 20 may be stacked together.

[0030] The stack substrate 100 also has a third via hole portion. The third via hole portion is composed of a through hole 31c penetrating the substrate 30, a second layer 34b of the base layer 34 provided on the inner wall surface of the through hole 31c, and a filling material 36 that fills the through hole 31c in which the second layer 34b is provided.

[0031] A plating layer 35 is formed in the third via hole portion including the filling material 36 on the main surface 31a. A protrusion 32a is formed in the plating layer 35 above the third via hole. A groove 13a is formed in the plating layer 15 above the first via hole on the main surface 11b side of the substrate 10. The groove 13a and the protrusion 32a are fitted together, and the substrates 10 and 30 are stacked together so that the first via hole portion on the main surface 11b and the third via hole portion on the main surface 31a face each other. Alternatively, a groove may be formed in the plating layer 35 above the third via hole, and a protrusion may be formed in the plating layer 15 above the first via hole, and the groove and the protrusion may be fitted together so that the first via hole portion on the main surface 11b and the second via hole portion on the main surface 31a face each other.

[0032] The electronic component 40 is connected to the wiring layer 22 within the space defined by the recess 11d and the component placement region 21d. The electronic component 40 in the component placement region 21d forms one circuit block. The electronic component 41 is connected to the wiring layer 32 within the space defined by the recess 11e and the component placement region 31d. The electronic component 41 in the component placement region 31d forms one circuit block. The connection between the electronic component 40 and the wiring layer 22 and the connection between the electronic component 41 and the wiring layer 32 are made by, for example, soldering.

[0033] (Method for Manufacturing Stack Substrate 100) A method for manufacturing the stack substrate 100 will be described below.

[0034] 2 is a manufacturing process diagram of the stack substrate 100. As shown in FIG. 2, the manufacturing method of the stack substrate 100 includes a first substrate forming process S1, a second substrate forming process S2, a third substrate forming process S3, an electronic component mounting process S4, and a substrate assembling process S5.

[0035] The first substrate forming step S1 includes a preparation step S11, a base material processing step S12, a first plating step S13, a wiring layer patterning step S14, and a second plating step S15.

[0036] 3 is a cross-sectional view illustrating the preparation step S11. As shown in FIG. 3, in the preparation step S11, a substrate 11 is prepared. The substrate 11 prepared in the preparation step S11 has a first layer 14a disposed on a main surface 11a and a main surface 11b.

[0037] 4 is a cross-sectional view illustrating the substrate processing step S12. As shown in FIG. 4, in the substrate processing step S12, a hole is drilled in the substrate 11. As a result, a through hole 11c is formed in the substrate 11. Also, in the substrate processing step S12, a countersink is drilled in the substrate 11. As a result, a recess 11d and a recess 11e are formed.

[0038] 5 is a cross-sectional view illustrating the first plating step S13. As shown in FIG. 5, in the first plating step S13, a second layer 14b is formed on the first layer 14a by electroless plating, copper sulfate plating, or the like. At this time, the second layer 14b is also formed on the inner wall surface of the through hole 11c, the side and bottom surfaces of the recess 11d, and the side and bottom surfaces of the recess 11e. After the second layer 14b is formed, the through hole 11c is filled with a filling material 16.

[0039] 6 is a cross-sectional view illustrating the wiring layer patterning step S14. As shown in FIG. 6, in the wiring layer patterning step S14, the underlayer 14 is patterned by etching using a resist pattern formed on the underlayer 14 as a mask.

[0040] FIG. 7 is a cross-sectional view illustrating the second plating step S15. As shown in FIG. 7, in the second plating step S15, a plating layer 15 is formed. In the second plating step S15, first, a resist pattern is formed on the base layer 14. The base layer 14 is exposed through openings in the resist pattern. Second, for example, electrolytic plating is performed to grow the plating layer 15 on the base layer 14 exposed through the openings in the resist pattern. That is, in the second plating step S15, the plating layer 15 is formed by, for example, a semi-additive method. After the second plating step S15 is performed, post-processing such as contour processing, solder resist application, and surface treatment is performed.

[0041] The second substrate forming step S2 includes a preparation step S21, a base material processing step S22, a first plating step S23, a wiring layer patterning step S24, and a second plating step S25.

[0042] 8 is a cross-sectional view illustrating the preparation step S21. As shown in FIG. 3, in the preparation step S21, the base material 21 is prepared. The base material 21 prepared in the preparation step S21 has the first layer 24a disposed on the main surface 21a and the main surface 21b.

[0043] FIG. 9 is a cross-sectional view illustrating the substrate processing step S22. In the substrate processing step S22, as shown in FIG. 9, a hole is drilled in the substrate 21 to form a through hole 21c in the substrate 21. FIG. 10 is a cross-sectional view illustrating the first plating step S23. As shown in FIG. 10, in the first plating step S23, a second layer 24b is formed on the first layer 24a by electroless plating, copper sulfate plating, or the like. At this time, the second layer 24b is also formed on the inner wall surface of the through hole 21c. After the second layer 24b is formed, the through hole 21c is filled with a filling material 26.

[0044] FIG. 11 is a cross-sectional view illustrating the wiring layer patterning step S24. As shown in FIG. 11 , in the wiring layer patterning step S24, the base layer 24 is patterned by etching using a resist pattern formed on the base layer 24 as a mask. FIG. 12 is a cross-sectional view illustrating the second plating step S25. As shown in FIG. 12 , in the second plating step S25, a plating layer 25 is formed. In the second plating step S25, first, a resist pattern is formed on the base layer 24. The base layer 24 is exposed through openings in the resist pattern. Second, the plating layer 25 is grown on the base layer 24 exposed through the openings in the resist pattern by, for example, electrolytic plating. That is, in the second plating step S25, the plating layer 25 is formed by, for example, a semi-additive method. After the second plating step S25 is performed, post-processing such as contour processing, solder resist application, and surface treatment is performed.

[0045] In the third substrate forming step S3, a substrate 30 is formed. The third substrate forming step S3 is similar to the second substrate forming step S2, and therefore a description thereof will be omitted here.

[0046] 13 is a cross-sectional view illustrating the electronic component mounting step S4. As shown in FIG. 13, in the electronic component mounting step S4, an electronic component 40 is mounted on the wiring layer 12 in the component placement area 21d. The electronic component 40 is mounted, for example, by soldering. Although not shown, an electronic component 41 is also similarly mounted on the wiring layer 32 in the component placement area 31d.

[0047] In the substrate assembly process S5, first, the substrates 10, 20, and 30 are arranged so that the main surfaces 11a and 11b face the main surfaces 21a and 21b, respectively. More specifically, the substrates 10, 20, and 30 are arranged so that the protrusions 22a and 32a face the grooves 12a and 13a, respectively. Second, the substrates 20 and 30 are pressed toward the substrate 10. This causes the protrusions 22a and 32a to fit into the grooves 12a and 13a, respectively. Furthermore, the substrates 10, 20, and 30 may be fixed to one another by, for example, screwing. As a result of the above, the structure of the stack substrate 100 shown in FIG. 1 is formed.

[0048] Alternatively, a first via hole portion composed of through hole 11c, second layer 14b provided on the inner wall surface of through hole 11c, and filling material 16 may be provided; a second via hole portion composed of through hole 21c, second layer 24b provided on the inner wall surface of through hole 21c, and filling material 26; and a third via hole portion composed of through hole 31c, second layer 34b provided on the inner wall surface of through hole 31c, and filling material 36 may be provided; and plating layers 15, 25, and 35 may be provided on each via hole portion. In this case, grooves 12a and 13a may be formed in plating layer 15, protrusions 22a may be formed in plating layer 25, and protrusions 32a may be formed in plating layer 35. Then, groove 12a may be fitted with protrusions 22a, and groove 13a may be fitted with protrusions 32a. Alternatively, protrusions may be formed in plating layer 15, grooves in plating layer 25, and grooves in plating layer 35, and substrates 10, 20, and 30 may be stacked together by fitting these grooves into the protrusions.

[0049] (Effects of the Stacked Substrate 100) The effects of the stacked substrate 100 will be described below.

[0050] In the stack substrate 100, the protrusion 22a (protrusion 32a) is fitted into the groove 12a (groove 13a) and surrounds the component placement area 21d (component placement area 31d) in a planar view, making it possible to electromagnetically shield the circuit block consisting of the electronic component 40 (electronic component 41).

[0051] In the stack substrate 100, the shielding structure composed of the protrusion 22a (protrusion 32a) and the groove 12a (groove 13a) can be formed using a normal substrate manufacturing process, so the arrangement of the shielding structure can be freely determined. Furthermore, in the stack substrate 100, the protrusion 22a (protrusion 32a) is formed using a semi-additive method, so the width of the protrusion 22a (protrusion 32a) can be reduced to approximately 50 μm. In other words, the stack substrate 100 makes it possible to reduce the area in which the shielding structure is formed.

[0052] When the protrusion 22a (protrusion 32a) surrounds the component placement area 21d (component placement area 31d) over multiple circumferences in a planar view, i.e., when the shielding structure has a labyrinth structure, the shielding structure becomes less susceptible to deformation of the substrate 10 or substrate 20 (substrate 30), and the shielding properties are improved.

[0053] Conventional circuit block shielding designs have employed methods such as attaching a case that grounds the circuit block or arranging bumps using solder (e.g., BGA (Ball Grid Array) soldering) at a pitch of less than one-quarter of the wavelength of the electromagnetic wave. However, attaching a case requires securing a sufficient area for the case, which requires additional processes. Furthermore, adjusting the bump pitch inevitably leaves gaps between the bumps, which can cause the circuit block to malfunction due to external interference or oscillations from within the circuit block that are not considered in the design. The stacked substrate 100 eliminates the concepts of bump pitch and gaps between the bumps, eliminating the need to design with the bump pitch in mind.

[0054] Furthermore, by fitting the substrates together over the via holes, the thermal conductivity between the substrates, that is, between the substrate 10 and the substrate 20 and between the substrate 10 and the substrate 30, is improved.

[0055] 14 is a perspective view of the substrate 20 in the stack substrate 100 according to Modification 1. As shown in Fig. 14, the shape of the protrusion 22a in plan view is not particularly limited. The shape of the protrusion 22a in plan view may be rectangular, circular, or polygonal in accordance with the arrangement of the electronic components 40.

[0056] (Variation 2) Fig. 15 is a cross-sectional view of a stack substrate 100 according to Variation 2. As shown in Fig. 15, the stack substrate 100 may further include a bonding material 50. The bonding material 50 is, for example, an anisotropic conducting film (ACF), solder, or a conductive paste. The bonding material 50 is a material that can be bonded at a temperature lower than the soldering temperature of the electronic components 40 and 41. The protrusion 22a and the groove 12a may be fitted together with the bonding material 50 interposed therebetween, and the protrusion 32a and the groove 13a may be fitted together with the bonding material 50 interposed therebetween. This makes it possible to correct warping and twisting of each substrate (substrate 10, substrate 20, substrate 30).

[0057] (Modification 3) Fig. 16 is a cross-sectional view of a stack substrate 100 according to Modification 3. As shown in Fig. 16, the stack substrate 100 may further include a filler 60. The filler 60 is filled between the electronic component 40 and the wiring layer 12 in the recess 11d, and also between the electronic component 41 and the wiring layer 13 in the recess 11e. The filler 60 is a thermally conductive material such as silicone. This makes it easier for heat from the electronic component 40 and the electronic component 41 to be dissipated through the filler 60. The filler 60 may be a radio wave absorbing material.

[0058] (Variant 4) In the above, an example has been described in which the wiring layer 22 and the wiring layer 32 have protrusions (protrusions 22a, protrusions 32a) and grooves (grooves 12a, grooves 13a) are formed in the wiring layer 12 and the wiring layer 13, but the wiring layer 12 and the wiring layer 13 may also have protrusions, and grooves may be formed in the wiring layer 22 and the wiring layer 32.

[0059] Second Embodiment A stack substrate according to a second embodiment will be described. The stack substrate according to the first embodiment is referred to as a stack substrate 200. Here, differences from the stack substrate 100 will be mainly described, and overlapping descriptions will not be repeated.

[0060] (Configuration of Stack Substrate 200) The configuration of the stack substrate 200 will be described below.

[0061] Fig. 17 is a cross-sectional view of the stack substrate 200. As shown in Fig. 17, the stack substrate 100 includes a substrate 10, a substrate 20, a substrate 30, an electronic component 40, and an electronic component 41. In this respect, the configuration of the stack substrate 200 is common to the configuration of the stack substrate 100.

[0062] In the stack substrate 200, the wiring layer 22 and the wiring layer 23 do not have a plating layer 25, and the wiring layer 32 and the wiring layer 33 do not have a plating layer 35. In the stack substrate 200, the wiring layer 12 has a protruding portion 12b, and the wiring layer 13 has a protruding portion 13b. In a plan view, the protruding portion 12b surrounds the component placement region 21d. In a plan view, the protruding portion 13b surrounds the component placement region 31d. In the stack substrate 200, the groove 22b is formed in the wiring layer 22, and the groove 32b is formed in the wiring layer 32. More specifically, the groove 22b is formed in the base layer 24 that forms part of the wiring layer 22, and the groove 32b is formed in the base layer 34 that forms part of the wiring layer 32. The protruding portion 12b and the protruding portion 13b are fitted into the groove 22b and the groove 32b, respectively. In these respects, the configuration of the stack substrate 200 is different from the configuration of the stack substrate 100 .

[0063] (Effects of the Stacked Substrate 200) The effects of the stacked substrate 200 will be described below.

[0064] In the stack substrate 200, the protrusion 12b (protrusion 13b) is fitted into the groove 22b (groove 32b) and surrounds the component placement area 21d (component placement area 31d) in a planar view, so that, similar to the stack substrate 100, it is possible to electromagnetically shield the circuit block consisting of the electronic component 40 (electronic component 41).

[0065] In the stack substrate 200, the plating layers 25 and 35 are not formed, and the plating process for forming the plating layers 25 and 35 can be omitted when forming the substrates 20 and 30, which simplifies the manufacturing process compared to the stack substrate 100. In the stack substrate 200, the plating layers 25 and 35 are not formed, and as a result, the thicknesses of the wiring layers 22 and 32 can be reduced, which in turn enables the patterns of the wiring layers 22 and 23 to be made finer.

[0066] In the first and second embodiments, examples have been described in which the substrate 11, the substrate 21, and the substrate 31 are composed of glass cloth and a resin material impregnated into the glass cloth. In addition to the case in which the substrate 11, the substrate 21, and the substrate 22 are composed of glass cloth and a resin material impregnated into the glass cloth, they may also be made of materials that do not contain glass cloth, such as a composite substrate epoxy substrate in which a paper substrate is impregnated with an epoxy resin, or a polyimide substrate in which a paper substrate is impregnated with a polyimide resin. The substrate 11, the substrate 21, and the substrate 31 may also be made of a material in which a filler is compounded with a resin material. The substrate 11, the substrate 21, and the substrate 31 may also be made of a material in which glass cloth is impregnated with an epoxy resin or a PTFE resin (tetrafluoroethylene resin).

[0067] (Appendix) Various aspects of the present disclosure are summarized as appendices.

[0068] <Supplementary Note 1> A stack substrate comprising: a first substrate; a second substrate; and electronic components; the first substrate has a first base material and a first wiring layer formed of a conductive material on a first main surface of the first substrate; the second substrate has a second base material and a second wiring layer formed of a conductive material on a second main surface of the second substrate; a recess is formed in the first main surface; the second main surface faces the recess and has a component placement area in which the electronic components are placed; the electronic components are connected to the second wiring layer in a space defined by the recess and the component placement area; one of the first wiring layer and the second wiring layer has a protrusion;

[0069] <Supplementary Note 2> The stack substrate according to Supplementary Note 1, further comprising a bonding material, wherein the protrusion and the groove are fitted together with the bonding material interposed therebetween.

[0070] <Supplementary Note 3> The stack substrate according to Supplementary Note 1 or Supplementary Note 2, further comprising a filler material interposed between the electronic component and the first wiring layer in the recess.

[0071] <Supplementary Note 4> The stack substrate according to Supplementary Note 3, wherein the filler is a heat transfer material or an electromagnetic wave absorbing material.

[0072] <Supplementary Note 5> The stack substrate according to any one of Supplementary Note 1 to Supplementary Note 4, wherein the first wiring layer has a first base layer and a first plating layer disposed on the first base layer, the second wiring layer has a second base layer and a second plating layer disposed on the second base layer, one of the first plating layer and the second plating layer forms the protrusion, and the other of the first plating layer and the second plating layer has the groove formed therein.

[0073] <Supplementary Note 6> The stack substrate according to any one of Supplementary Note 1 to Supplementary Note 4, wherein the first wiring layer has a first base layer and a first plating layer disposed on the first base layer, the second wiring layer has a second base layer, the first plating layer forms the protrusion, and the second base layer has the groove formed therein.

[0074] <Supplementary Note 7> A semiconductor device includes: a first via hole portion configured with a first through hole penetrating the first substrate, the first base layer provided on an inner wall surface of the first through hole, and a first filling material filling the first through hole provided with the first base layer; and a second via hole portion configured with a second through hole penetrating the second substrate, the second base layer provided on an inner wall surface of the second through hole, and a second filling material filling the second through hole provided with the second base layer, wherein the first plating layer is formed on the first via hole portion including the first filling material on the first main surface, and the second plating layer is formed on the second via hole portion including the second filling material on the second main surface, one of the first plating layer and the second plating layer forms the protruding portion, and the groove is formed in the other of the first plating layer and the second plating layer, A stack substrate as described in Appendix 5, wherein the groove and the protrusion are fitted together, and the first via hole portion of the first main surface and the second via hole portion of the second main surface are stacked facing each other.

[0075] forming a first wiring layer made of a conductive material on the first main surface; forming a second wiring layer made of a conductive material on the second main surface of a second substrate; when a component placement area on the second main surface facing the recess and in which the electronic component is placed is seen in a plan view, forming a protrusion in one of the first wiring layer and the second wiring layer so as to surround the component placement area, and forming a groove in the other of the first wiring layer and the second wiring layer so as to surround the component placement area; connecting the electronic component to the second wiring layer in a space defined by the recess and the component placement area; and stacking the first substrate and the second substrate so that the first main surface and the second main surface face each other by fitting the protrusion into the groove.

[0076] <Supplementary Note 9> The first wiring layer is a laminated film of a first underlayer and a first plating layer disposed on the first underlayer, and the second wiring layer is a laminated film of a second underlayer and a second plating layer disposed on the second underlayer, comprising the steps of forming a first through hole penetrating the first substrate, forming the first underlayer on an inner wall surface of the first through hole, and filling the first through hole provided with the first underlayer with a first filling material to form a first via hole portion; forming a second through hole penetrating the second substrate, forming the second underlayer on an inner wall surface of the second through hole, and filling the second through hole provided with the second underlayer with a second filling material to form a second via hole portion; and forming the first plating layer on the first via hole portion including the first filling material on the first main surface, and forming the second plating layer on the second via hole portion including the second filling material on the second main surface, The method for manufacturing a stack substrate described in Appendix 8 further includes a step of forming the groove in the other of the first plating layer and the second plating layer, and a step of fitting the groove and the protrusion, and stacking the first via hole portion of the first main surface and the second via hole portion of the second main surface so that they face each other.

[0077] The embodiments disclosed herein should be considered to be illustrative in all respects and not restrictive. The scope of this application is defined by the claims, not the above description, and is intended to include all modifications within the meaning and scope of the claims.

[0078] 100 Stack substrate, 10 Substrate, 11 Base material, 11a, 11b Main surface, 11c Through hole, 11d, 11e Recess, 12 Wiring layer, 12a Groove, 12b Protrusion, 13 Wiring layer, 13a Groove, 13b Protrusion, 14 Underlayer, 14a First layer, 14b Second layer, 15 Plating layer, 16 Filling material, 20 Substrate, 21 Base material, 21a, 21b Main surface, 21c Through hole, 21d Component placement area, 22 Wiring layer, 22a Protrusion, 22b Groove, 23 Wiring layer, 24 Underlayer, 24a First layer, 24b Second layer, 25 Plating layer, 26 Filling material, 30 Substrate, 31 Base material, 31a, 31b Main surface, 31c Through hole, 31d Component placement area, 32 wiring layer, 32a protrusion, 32b groove, 33 wiring layer, 34 base layer, 34a first layer, 34b second layer, 35 plating layer, 36 embedding material, 40 electronic component, 41 electronic component, 50 bonding material, 60 filler, 200 stack substrate, S1 first substrate forming process, S2 second substrate forming process, S3 third substrate forming process, S4 electronic component mounting process, S5 assembly process, S11 preparation process, S12 substrate processing process, S13 first plating process, S14 wiring layer patterning process, S15 second plating process, S21 preparation process, S22 substrate processing process, S23 first plating process, S24 wiring layer patterning process, S25 second plating process.

Claims

1. A stack substrate comprising a first substrate, a second substrate, and electronic components, the first substrate having a first base material and a first wiring layer formed of a conductive material on a first main surface of the first substrate, the second substrate having a second base material and a second wiring layer formed of a conductive material on a second main surface of the second substrate, a recess formed in the first main surface, the second main surface facing the recess and having a component placement area in which the electronic components are placed, the electronic components being connected to the second wiring layer within a space defined by the recess and the component placement area, one of the first wiring layer and the second wiring layer having a protrusion, and the other of the first wiring layer and the second wiring layer having a groove, the protrusion and the groove surrounding the component placement area in a plan view, and the first substrate and the second substrate being stacked such that the groove and the protrusion are fitted together and the first main surface and the second main surface are facing each other.

2. The stack substrate according to claim 1, further comprising a bonding material, wherein the protrusion and the groove are fitted together with the bonding material interposed therebetween.

3. The stack substrate according to claim 1 or 2, further comprising a filler material interposed between the electronic component and the first wiring layer in the recess.

4. The stack substrate according to claim 3, wherein the filler is a heat conductive material or an electromagnetic wave absorbing material.

5. A stack substrate as described in any one of claims 1 to 4, wherein the first wiring layer has a first base layer and a first plating layer disposed on the first base layer, the second wiring layer has a second base layer and a second plating layer disposed on the second base layer, one of the first plating layer and the second plating layer forms the protrusion, and the other of the first plating layer and the second plating layer has the groove formed therein.

6. A stack substrate as described in any one of claims 1 to 4, wherein the first wiring layer has a first base layer and a first plating layer disposed on the first base layer, the second wiring layer has a second base layer, the first plating layer forms the protruding portion, and the second base layer has the groove formed therein.

7. A stack substrate as claimed in claim 5, comprising: a first via hole portion consisting of a first through hole penetrating the first substrate, the first base layer provided on the inner wall surface of the first through hole, and a first filling material filling the first through hole with the first base layer provided therein; and a second via hole portion consisting of a second through hole penetrating the second substrate, the second base layer provided on the inner wall surface of the second through hole, and a second filling material filling the second through hole with the second base layer provided therein; wherein the first plating layer is formed in the first via hole portion including the first filling material on the first main surface, and the second plating layer is formed in the second via hole portion including the second filling material on the second main surface, one of the first plating layer and the second plating layer forming the protruding portion, and the groove is formed in the other of the first plating layer and the second plating layer, and the groove and the protruding portion are fitted together so that the first via hole portion on the first main surface and the second via hole portion on the second main surface are stacked facing each other.

8. A method for manufacturing a stack substrate, comprising the steps of: preparing a first substrate, a second substrate, and an electronic component; forming a recess in a first main surface of a first substrate constituting the first substrate; forming a first wiring layer made of a conductive material on the first main surface; forming a second wiring layer made of a conductive material on a second main surface of a second substrate constituting the second substrate; forming a protrusion surrounding the component placement region on one of the first wiring layer and the second wiring layer and forming a groove surrounding the component placement region on the other of the first wiring layer and the second wiring layer when a component placement region facing the recess in the second main surface and in which the electronic component is placed is viewed in a plan view; connecting the electronic component to the second wiring layer within a space defined by the recess and the component placement region; and overlapping the first substrate and the second substrate so that the first main surface and the second main surface face each other by fitting the protrusion into the groove.

9. The first wiring layer is a laminated film of a first base layer and a first plating layer disposed on the first base layer, and the second wiring layer is a laminated film of a second base layer and a second plating layer disposed on the second base layer, comprising the steps of forming a first through hole penetrating the first substrate, forming the first base layer on an inner wall surface of the first through hole, and filling the first through hole provided with the first base layer with a first filling material to form a first via hole portion, forming a second through hole penetrating the second substrate, forming the second base layer on an inner wall surface of the second through hole, and filling the second through hole provided with the second base layer with a second filling material to form a second via hole portion, and forming the first plating layer on the first via hole portion including the first filling material on the first main surface, and forming the second plating layer on the second via hole portion including the second filling material on the second main surface, and one of the first plating layer and the second plating layer forms the protruding portion, 9. The method for manufacturing a stack substrate according to claim 8, further comprising the steps of: forming the groove in the other of the first plating layer and the second plating layer; and fitting the groove and the protrusion to stack the first via hole portion of the first main surface and the second via hole portion of the second main surface so as to face each other.

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