Memory device

Abstract

The present invention shortens write time. A memory device according to the present invention includes a memory cell pair and a write circuit. The memory cell pair of the memory device includes a first memory cell and a second memory cell each having a magnetoresistive effect element in which a state of internal resistance changes to a high resistance state or a low resistance state in accordance with an applied voltage, and a selection element that is connected in series to the magnetoresistive effect element. The write circuit that the memory device has simultaneously writes to the first memory cell and the second memory cell.

Description

memory device

[0001] The present disclosure relates to memory devices.

[0002] Memories have been developed that employ magnetoresistive elements such as MTJ (Magnetic Tunnel Junction) elements as nonvolatile memory elements. These magnetoresistive elements are two-terminal elements that can assume two states: a high resistance state (high resistance state) and a low resistance state (low resistance state). These two states allow one bit of data to be stored. Data can be written by applying a write voltage to the magnetoresistive element to alternately transition it between the high resistance state and the low resistance state. A memory has been proposed that includes such a magnetoresistive element and a memory cell having a cell transistor that selects the magnetoresistive element (see, for example, Patent Document 1).

[0003] The above-mentioned memory has a problem in that it takes a long time to read data. This is because a wide margin is required when measuring the resistance of the magnetoresistive element. Therefore, a memory that stores one bit of data per unit of two memory cells has been proposed. In this memory, the magnetoresistive element of one of the two memory cells is set to a high resistance state, and the magnetoresistive element of the other memory cell is set to a low resistance state. Data can be stored depending on which of these two memory cells is in the high resistance state. This method widens the read margin for the resistance value of the magnetoresistive element, thereby shortening the time required for reading.

[0004] Japanese Patent Application Laid-Open No. 2018-085155

[0005] However, the above-mentioned conventional technology has a problem in that writing to each of the two memory cells takes a long time.

[0006] Therefore, this disclosure proposes a method for shortening the write time of a memory device that stores data in units of two memory cells.

[0007] The memory device of the present disclosure comprises a memory cell pair including a first memory cell and a second memory cell, each having a magnetoresistive effect element whose internal resistance state changes between a high resistance state and a low resistance state depending on an applied voltage, and a selection element connected in series to the magnetoresistive effect element, and a write circuit that simultaneously writes to the first memory cell and the second memory cell.

[0008] FIG. 1 is a diagram illustrating an example configuration of a memory system according to a first embodiment of the present disclosure. FIG. 2 is a diagram illustrating an example configuration of a memory cell array according to the first embodiment of the present disclosure. FIG. 3 is a diagram illustrating an example configuration of a memory cell according to the first embodiment of the present disclosure. FIG. 4 is a diagram illustrating an example configuration of a write according to the first embodiment of the present disclosure. FIG. 5 is a diagram illustrating an example configuration of a write according to the first embodiment of the present disclosure. FIG. 6 is a diagram illustrating an example processing procedure of a write process according to the first embodiment of the present disclosure. FIG. 7 is a diagram illustrating an example processing procedure of a read process according to the first embodiment of the present disclosure. FIG. 8 is a diagram illustrating an example processing procedure of a read process according to the first embodiment of the present disclosure. FIG. 9 is a diagram illustrating voltage dependence of magnetic anisotropy of a magnetoresistive effect element according to an embodiment of the present disclosure. FIG. 10 is a diagram illustrating writing to a magnetoresistive effect element according to the first embodiment of the present disclosure. FIG. 11 is a diagram illustrating writing to a magnetoresistive effect element according to the first embodiment of the present disclosure. FIG. 12 is a diagram illustrating an example configuration of a memory system according to a second embodiment of the present disclosure. FIG. 13 is a diagram illustrating an example configuration of a memory cell array according to the second embodiment of the present disclosure. FIG. 14 is a diagram illustrating an example configuration of a memory cell according to the second embodiment of the present disclosure. FIG. 15 is a diagram illustrating an example configuration of a write according to the second embodiment of the present disclosure. FIG. 1 is a diagram showing an example of a read operation according to a second embodiment of the present disclosure. FIG. 2 is a diagram showing an example of a processing procedure of a write operation according to a second embodiment of the present disclosure. FIG. 3 is a diagram showing an example of a write operation according to a second embodiment of the present disclosure. FIG. 4 is a diagram showing an example of a read operation according to a second embodiment of the present disclosure. FIG. 5 is a diagram showing writing to a magnetoresistive effect element according to a second embodiment of the present disclosure. FIG. 6 is a diagram showing writing to a magnetoresistive effect element according to a second embodiment of the present disclosure. FIG. 7 is a diagram showing an example of a configuration of a memory system according to a third embodiment of the present disclosure. FIG. 8 is a diagram showing an example of a configuration of a memory cell array according to a third embodiment of the present disclosure. FIG. 9 is a diagram showing an example of a configuration of a memory cell according to a third embodiment of the present disclosure. FIG. 10 is a diagram showing an example of a write operation according to a third embodiment of the present disclosure.10 is a diagram illustrating an example of a read according to a third embodiment of the present disclosure. FIG. 11 is a diagram illustrating an example of a processing procedure of a write processing according to a third embodiment of the present disclosure. FIG. 12 is a diagram illustrating an example of a write processing according to a third embodiment of the present disclosure. FIG. 13 is a diagram illustrating an example of a read processing according to a third embodiment of the present disclosure. FIG. 14 is a diagram illustrating writing to a magnetoresistive effect element according to a third embodiment of the present disclosure. FIG. 15 is a diagram illustrating writing to a magnetoresistive effect element according to a third embodiment of the present disclosure. FIG. 16 is a diagram illustrating an example of a processing procedure of a write processing according to a fourth embodiment of the present disclosure. FIG. 17 is a diagram illustrating another example of a processing procedure of a write processing according to a fourth embodiment of the present disclosure. FIG. 18 is a diagram illustrating an example of a processing procedure of a write processing according to a fourth embodiment of the present disclosure. FIG. 19 is a diagram illustrating an example of a processing procedure of a write processing according to a fifth embodiment of the present disclosure. FIG. 19 is a diagram illustrating another example of a processing procedure of a write processing according to the fifth embodiment of the present disclosure. FIG. 19 is a diagram illustrating an example of a processing procedure of a write processing according to the fifth embodiment of the present disclosure. 10 is a diagram showing an example of the configuration of a memory cell according to a seventh embodiment of the present disclosure. FIG. 11 is a diagram showing an example of the configuration of a memory system according to an eighth embodiment of the present disclosure. FIG. 12 is a diagram showing an example of the configuration of a memory cell array according to an eighth embodiment of the present disclosure. FIG. 13 is a diagram showing an example of the configuration of a memory cell according to the eighth embodiment of the present disclosure. FIG. 14 is a diagram showing an example of the configuration of a memory system according to a ninth embodiment of the present disclosure. FIG. 15 is a diagram showing an example of the configuration of a memory cell array according to a ninth embodiment of the present disclosure. FIG. 16 is a diagram showing an example of the configuration of a memory cell according to the ninth embodiment of the present disclosure. FIG. 17 is a diagram showing an example of an example of a write according to the ninth embodiment of the present disclosure. FIG. 18 is a diagram showing an example of an example of a write according to the ninth embodiment of the present disclosure. FIG. 19 is a diagram showing an example of a read according to the ninth embodiment of the present disclosure. FIG. 19 is a diagram showing an example of a processing procedure of a write process according to the ninth embodiment of the present disclosure. FIG. 19 is a diagram showing an example of a write process according to the ninth embodiment of the present disclosure.Fig. 13 is a diagram illustrating an example of a write process according to a ninth embodiment of the present disclosure. Fig. 14 is a diagram illustrating an example of a processing procedure of a read process according to a ninth embodiment of the present disclosure. Fig. 15 is a diagram illustrating an example of a read process according to a ninth embodiment of the present disclosure.

[0009] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. The description will be given in the following order. Note that in the following embodiments, the same components will be assigned the same reference numerals to avoid redundant description. 1. First embodiment 2. Second embodiment 3. Third embodiment 4. Fourth embodiment 5. Fifth embodiment 6. Sixth embodiment 7. Seventh embodiment 8. Eighth embodiment 9. Ninth embodiment

[0010] 1 is a diagram showing an example of the configuration of a memory system according to a first embodiment of the present disclosure. The memory system 1 includes an interface unit 2, a memory control unit 3, and a memory device 4.

[0011] The interface unit 2 is used to communicate with a host system or the like that uses the memory system 1 .

[0012] The memory control unit 3 controls the entire memory system 1. This memory control unit 3 communicates with a host system or the like and controls the memory device 4. Specifically, the memory control unit 3 receives commands from the host system or the like and controls the writing and reading of data in the memory device 4 based on the received commands. When writing, the memory control unit 3 outputs a write command, address, and write data to the memory device 4. When reading, the memory control unit 3 also outputs a read command and address and receives read data from the memory device 4.

[0013] The memory device 4 includes a plurality of memory cells for storing data, a memory cell array 10, a word line address decoder 60, a word line control circuit 20, a bit line and source line address decoder 50, a bit line and source line control circuit 30, and a sense amplifier 40. The memory device 4 also includes a gate voltage generation circuit 70, a write voltage generation circuit 80, and a read voltage generation circuit 90.

[0014] The memory cell array 10 is configured by arranging memory cells 110 and 120 in a two-dimensional matrix. Each of the memory cells 110 and 120 includes a magnetoresistive element 101 and a selection element 102. The memory cell 110 is an example of a "first memory cell" in the present disclosure. The memory cell 120 is an example of a "second memory cell" in the present disclosure.

[0015] Furthermore, word lines 11, bit lines 12, and source lines 13 are arranged in the memory cell array 10. The word lines 11 are composed of a plurality of word lines WL. The bit lines 12 are composed of a plurality of bit lines BL1 and BL2. The source lines 13 are composed of a plurality of source lines SL. The bit lines BL1 are an example of a "first bit line" in the present disclosure. The bit lines BL2 are an example of a "second bit line" in the present disclosure.

[0016] The magnetoresistive element 101 may be, for example, a magnetoresistive element such as an MTJ (Magnetic Tunnel Junction) element. The MTJ element is an element in which a nonmagnetic insulating layer is disposed between two ferromagnetic layers, and the resistance value changes depending on the magnetization directions of the two ferromagnetic layers. The MTJ element is in a high-resistance state when the magnetization directions of the two ferromagnetic layers are different, and in a low-resistance state when the magnetization directions are the same. Note that a state in which the magnetization directions are the same is called a parallel state, and a state in which the magnetization directions are different is called an anti-parallel state.

[0017] The magnetoresistive effect element 101 can have a configuration including a reference layer, a tunnel barrier layer, and a free layer. The reference layer and the free layer correspond to the above-mentioned ferroelectric layers. The reference layer is a magnetic layer whose magnetization direction is fixed, and is also called a fixed layer. The magnetization of the reference layer is fixed, for example, in the positive direction of the Z axis. The tunnel barrier layer is a non-magnetic layer provided between the reference layer and the free layer. The free layer is a magnetic layer whose magnetization direction changes, and is also called a memory layer. The magnetization of the free layer changes, for example, between the positive direction of the Z axis and the negative direction of the Z axis.

[0018] The MTJ also has a VCMA (Voltage Controlled Magnetic Anisotropy) effect, and an external magnetic field Hext is embedded in the element. The high-resistance state and low-resistance state are reversed by rotating the magnetization vector (spin). When a voltage is applied to an MTJ with VCMA, the magnetic anisotropy decreases. At this time, the magnetization vector rotates and precesses around the external magnetic field Hext. The high-resistance state and low-resistance state can be switched by stopping the application of voltage at the timing when the magnetization direction is reversed by this precession.

[0019] The selection element 102 is connected to one end of the magnetoresistive element 101 and controls the application of a voltage to the magnetoresistive element 101. For example, an n-channel MOS transistor can be used for the selection element 102.

[0020] In the memory cell array 10 of FIG. 1 , a memory cell pair 100 consisting of a memory cell 110 and a memory cell 120 constitutes a unit memory element. That is, one bit of data can be stored in the memory cell pair 100. The magnetoresistive element 101 of the memory cell 110 and the magnetoresistive element 101 of the memory cell 120 are in different resistance states. Data is retained based on which of the magnetoresistive element 101 of the memory cell 110 and the magnetoresistive element 101 of the memory cell 120 is in a high resistance state. Data can be rewritten by inverting the state of the magnetoresistive element 101 of the memory cell 110 and the magnetoresistive element 101 of the memory cell 120. The memory control unit 3 simultaneously writes data to the memory cells 110 and 120 of the memory cell pair 100.

[0021] A word line WL for transmitting a control signal and bit lines BL1 and BL2 are connected to the memory cells 110 and 120. A source line SL for transmitting a signal from the magnetoresistive element 101 is also arranged on the memory cells 110 and 120. In the memory cell array 10, a plurality of word lines are wired in the row direction, and a plurality of bit lines and source lines are wired in the column direction.

[0022] The word line address decoder 60 selects a word line of the memory cell array 10 based on a control signal from the memory control unit 3 .

[0023] The word line control circuit 20 outputs a control signal to a word line selected by the word line address decoder 60 .

[0024] The bit line and source line address decoder 50 selects the bit lines BL 1 and BL 2 and the source line SL of the memory cell array 10 based on control signals from the memory control unit 3 .

[0025] The bit line and source line control circuit 30 turns on the bit lines BL1 and BL2 and the source line SL selected by the bit line and source line address decoder 50.

[0026] The sense amplifier 40 reads data by detecting the current flowing through the memory cell pair 100 during reading. The read data is output to the memory control unit 3.

[0027] The write voltage generating circuit 80 generates a write voltage for the memory cell 110 and the memory cell 120. The write voltage generating circuit 80 generates two write voltages (write voltages V 1 , V 2 , V 3 ) of different magnitudes. Ｌ→Ｈ and the write voltage V Ｈ→Ｌ ) to generate the

[0028] The read voltage generating circuit 90 generates a voltage to be applied when reading from the memory cell pair 100 .

[0029] The gate voltage generating circuit 70 generates a voltage to be applied to the gate of the selected element. The gate voltage generating circuit 70 generates two voltages (Vg_write and Vg_read, which will be described later) of different magnitudes.

[0030] The memory control unit 3 is an example of a "writing circuit" in the present disclosure. The memory system 1 is an example of a "memory device" in the present disclosure.

[0031] 2 is a diagram showing a configuration example of a memory cell array according to the first embodiment of the present disclosure. The diagram shows a configuration example of a memory cell array 10 and peripheral circuits. The diagram further shows a word line address decoder 60, a bit line and source line control circuit 30, a sense amplifier 40, a write voltage generation circuit 80, and a read voltage generation circuit 90.

[0032] 2 also shows a bit line address decoder 51 and a source line address decoder 52 that constitute the bit line and source line address decoder 50. The bit line address decoder 51 selects the bit lines BL1 and BL2 based on the bit line address, and the source line address decoder 52 selects the source line SL based on the source line address.

[0033] A bit line BL1 is connected to the memory cell 110, and a bit line BL2 is connected to the memory cell 120. A source line SL is connected in common to the memory cells 110 and 120. A word line WL is also connected in common to the memory cells 110 and 120.

[0034] In the memory cell 110, one of the two terminals of the magnetoresistive element 101 is connected to the bit line BL1, and the other terminal is connected to the drain terminal of the selection element 102. In addition, the gate terminal of the selection element 102 of the memory cell 110 is connected to the word line WL, and the source terminal is connected to the source line SL.

[0035] In the memory cell 120, one of the two terminals of the magnetoresistive element 101 is connected to the bit line BL2, and the other terminal is connected to the drain terminal of the selection element 102. In addition, the gate terminal of the selection element 102 of the memory cell 120 is connected to the word line WL, and the source terminal is connected to the source line SL.

[0036] 2 also shows selector units 33 to 35 that configure the bit line and source line control circuit 30. The selector unit 33 is provided for each bit line BL1 and selects one of two write voltages generated by the write voltage generation circuit 80 and outputs it to the bit line BL1. The selector unit 34 is provided for each bit line BL2 and selects one of two write voltages generated by the write voltage generation circuit 80 and outputs it to the bit line BL2. The selector unit 35 is provided for each source line SL and selects one of the read voltage generated by the read voltage generation circuit 90 or the ground potential and outputs it to the source line SL.

[0037] 2 further illustrates a selection unit 71 and a selection unit 21 that configure the word line control circuit 20. The selection unit 71 selects and outputs one of two gate voltages generated by the gate voltage generation circuit 70. The selection unit 21 is provided for each word line WL, and selects either the gate voltage selected by the selection unit 71 or the ground potential and outputs the selected voltage to the word line WL.

[0038] 2, switch elements 41 and 42 are arranged between the bit lines BL1 and BL2 and the sense amplifier 40. These switch elements 41 and 42 are switch elements that connect the bit lines BL1 and BL2 to the sense amplifier 40 during reading.

[0039] The bit line and source line control circuit 30 outputs a write voltage only to the bit line BL1 and bit line BL2 connected to the memory cell pair 100 to be accessed, based on the control of the bit line and source line address decoder 50. The bit line BL1 and bit line BL2 connected to the memory cell pair 100 not to be accessed are set to a floating state. The word line control circuit 20 outputs a gate voltage only to the word line WL connected to the memory cell pair 100 to be accessed, based on the control of the word line address decoder 60. The word line WL connected to the memory cell pair 100 not to be accessed is set to ground potential. As a result, the selection elements 102 of the memory cells 110 and the like of the memory cell pairs 100 not to be accessed are set to an off state.

[0040] 3 is a diagram showing an example of the configuration of a memory cell according to the first embodiment of the present disclosure. The diagram shows voltages and the like applied to the memory cell 110 and the memory cell 120. Note that the selection unit 21 is omitted from the diagram. The read voltage generation circuit 90 generates a read voltage Vread. This read voltage Vread is output to the source line SL via the selection unit 35.

[0041] The write voltage generating circuit 80 generates a write voltage V Ｌ→Ｈ and the write voltage V Ｈ→Ｌ The write voltage V Ｌ→Ｈ is a write voltage that puts the magnetoresistive element 101 into a high resistance state. Ｈ→Ｌ is a write voltage that puts the magnetoresistive element 101 into a low resistance state. Ｌ→Ｈ is an example of a "high resistance state write voltage" in the present disclosure. Ｈ→Ｌ is an example of the "low resistance state write voltage" of the present disclosure.

[0042] The gate voltage generation circuit 70 also generates a gate voltage Vg_read and a gate voltage Vg_write. The gate voltage Vg_read is a voltage applied to the gate of the selection element 102 during reading. This gate voltage Vg_read is a gate voltage that puts the selection element 102 into a conductive state. The gate voltage Vg_write is a voltage applied to the gate of the selection element 102 during writing. This gate voltage Vg_write is a gate voltage that puts the selection element 102 into a predetermined on-resistance. The gate voltage Vg_read and the gate voltage Vg_write are selected by the selection unit 71 and input to the memory cells 110 and 120.

[0043] 4 is a diagram showing an example of writing according to the first embodiment of the present disclosure. The figure shows an example in which the magnetoresistive effect element 101 of the memory cell 110 is set to a high resistance state and the magnetoresistive effect element 101 of the memory cell 120 is set to a low resistance state. As shown in the figure, a write voltage V Ｌ→Ｈ is applied to the bit line BL2, and the write voltage V Ｈ→Ｌ The source line SL is set to the ground potential. The word line WL is applied with a gate voltage Vg_write. This causes the memory cell 110 to receive a write voltage V Ｌ→Ｈ is applied to the memory cell 120, and a write voltage V Ｈ→Ｌ is applied. The switch elements 41 and 42 are turned off.

[0044] 5 is a diagram showing an example of writing according to the first embodiment of the present disclosure. The figure shows an example in which the magnetoresistive element 101 of the memory cell 110 is set to a low resistance state and the magnetoresistive element 101 of the memory cell 120 is set to a high resistance state. As shown in the figure, a write voltage V Ｈ→Ｌ is applied to the bit line BL2, and the write voltage V Ｌ→Ｈ The source line SL is set to the ground potential. The word line WL is applied with a gate voltage Vg_write. This causes the memory cell 110 to receive a write voltage V Ｈ→Ｌ is applied to the memory cell 120, and a write voltage V Ｌ→Ｈis applied. The switch elements 41 and 42 are turned off.

[0045] FIG. 6 is a diagram showing an example of reading according to the first embodiment of the present disclosure. This diagram illustrates a case where data is read from the memory cell 110 and the memory cell 120. As shown in this diagram, the bit lines BL1 and BL2 are set to a floating state. A read voltage Vread is applied to the source line SL. A gate voltage Vg_read is applied to the word line WL. The switch elements 41 and 42 are set to an ON state. This causes a current corresponding to the state of the magnetoresistive element 101 of the memory cell 110 or the like to flow to the sense amplifier 40 via the bit line BL1 or the like. The sense amplifier 40 can read data by detecting the difference between the current of the bit line BL1 and the current of the bit line BL2.

[0046] [Write Process] FIG. 7 is a diagram showing an example of a write process procedure according to the first embodiment of the present disclosure. This figure is a flowchart showing an example of a write process procedure in the memory device 4. First, the bit line and source line control circuit 30 sets the voltage applied to the source line SL to the ground level (step S101). Next, the word line control circuit 20 sets the voltage applied to the word line WL to the gate voltage Vg_write (step S102). Next, the data to be written to the memory cell pair 100 is referenced (step S103). Specifically, if the memory cell 110 is to be put into a high-resistance state (step S103, Yes), the process proceeds to step S104. On the other hand, if the memory cell 110 is not to be put into a high-resistance state (step S103, No), the process proceeds to step S107.

[0047] In step S104, the bit line and source line control circuit 30 applies a write voltage V Ｌ→Ｈ Next, the bit line and source line control circuit 30 sets the write voltage V Ｈ→Ｌ (Step S105). Next, the process proceeds to Step S106.

[0048] In step S107, the bit line and source line control circuit 30 applies a write voltage V Ｈ→Ｌ Next, the bit line and source line control circuit 30 sets the write voltage V Ｌ→Ｈ (Step S108). Next, the process proceeds to Step S106.

[0049] In step S106, a write voltage is applied to the memory cell pair 100. This can be done by the write voltage generation circuit 80 generating a write voltage and applying it to the memory cell pair 100 via the bit line and source line control circuit 30.

[0050] 8 and 9 are diagrams illustrating an example of a write process according to the first embodiment of the present disclosure. FIGS. 8 and 9 are timing charts illustrating an example of a write process in the memory device 4. FIG. 8 illustrates a case where the memory cell 110 is in a high resistance state and the memory cell 120 is in a low resistance state. FIG. 9 illustrates a case where the memory cell 110 is in a low resistance state and the memory cell 120 is in a high resistance state.

[0051] "WL Voltage Config" and "WL Enable" in Figures 8 and 9 represent logic control signals from the memory control unit 3 to the word line control circuit 20. Also, "BL1 Voltage Config", "BL2 Voltage Config", "SL Voltage Config", and "BL / SL Enable" represent logic control signals from the memory control unit 3 to the bit line and source line control circuit 30. Also, "V_W" represents the voltage waveform of the word line WL. Also, "V_BL1" represents the voltage waveform of the bit line BL1. Also, "V_BL2" represents the voltage waveform of the bit line BL2. Also, "V_SL" represents the voltage waveform of the source line SL.

[0052] 8, a gate voltage is set during periods T1 to T4, and the word line WL is enabled. As a result, a gate voltage Vg_write is applied to the gate of the selection element 102. Also, a write voltage is set.

[0053] During the period from T2 to T3, the bit line BL1, the bit line BL2, and the source line SL are enabled. As a result, the write voltage V Ｌ→Ｈ is supplied to the bit line BL2, and the write voltage V Ｈ→Ｌ The source line SL is at the ground potential.

[0054] 9, a gate voltage is set during periods T1 to T4, and the word line WL is enabled. As a result, a gate voltage Vg_write is applied to the gate of the selection element 102. Also, a write voltage is set.

[0055] During the period from T2 to T3, the bit line BL1, the bit line BL2, and the source line SL are enabled. As a result, the write voltage V Ｈ→Ｌ is supplied to the bit line BL2, and the write voltage V Ｌ→Ｈ The source line SL is at the ground potential.

[0056] [Read Process] Figure 10 is a diagram showing an example of a processing procedure for a read process according to the first embodiment of the present disclosure. This figure is a flowchart showing an example of a processing procedure for a read process in the memory device 4. First, the bit line and source line control circuit 30 sets the voltage applied to the source line SL to the read voltage Vread (step S111). Next, the word line control circuit 20 sets the voltage applied to the word line WL to the gate voltage Vg_read (step S112). Next, a read voltage is applied to the memory cell pair 100 (step S113). This can be achieved by the read voltage generation circuit 90 generating the read voltage Vread and applying it to the memory cell pair 100 via the bit line and source line control circuit 30.

[0057] 11 is a diagram showing an example of a read process according to the first embodiment of the present disclosure. The diagram is a timing chart showing an example of a read process in the memory device 4.

[0058] During the period from T5 to T8, the gate voltage is set and the word line WL is enabled, whereby the gate voltage Vg_read is applied to the gate of the selection element 102. Also, the read voltage is set.

[0059] During the period from T6 to T7, the source line SL is enabled, and the read voltage Vread is supplied to the source line SL. The bit lines BL1 and BL2 are in a floating state.

[0060] 12 is a diagram showing the voltage dependence of the magnetic anisotropy of the magnetoresistive element according to an embodiment of the present disclosure. This figure is a graph showing the voltage dependence of the magnetic anisotropy of the magnetoresistive element 101. The horizontal axis of the graph represents voltage. The vertical axis of the graph represents the magnetic anisotropy of the recording layer of the magnetoresistive element 101. Note that in regions where the magnetic anisotropy is positive, perpendicular magnetic anisotropy is achieved, and in regions where the magnetic anisotropy is negative, in-plane magnetic anisotropy is achieved.

[0061] As shown in FIG. 12, perpendicular magnetic anisotropy is approximately zero near the voltage VC. Furthermore, perpendicular magnetic anisotropy is present at a voltage VL that is lower than the voltage VC, and in-plane magnetic anisotropy exists at a voltage VH that is higher than the voltage VC. The greater the perpendicular magnetic anisotropy, the easier it is for the free layer to be magnetized in the perpendicular direction. Specifically, when the magnetic anisotropy is positive, the free layer is easily magnetized in the perpendicular direction (Z-axis direction). Furthermore, when the magnetic anisotropy is negative, the free layer is easily magnetized in the horizontal direction (XY plane direction).

[0062] Here, "perpendicular" refers to the z-axis direction perpendicular to the x-y plane to which the external magnetic field is applied, and "in-plane" refers to the x-y plane. When there is in-plane magnetic anisotropy, the magnetization vector rotates in the x-y plane, but does not rotate in the z-axis direction, and therefore does not reverse.

[0063] In contrast, when the applied voltage to the magnetoresistive element 101 is VC, the magnetic anisotropy is approximately 0, and therefore the magnetization vector rotates and precesses around the external magnetic field Hext as its axis. By stopping the application of voltage at the timing when the magnetization direction is reversed by this precession, the magnetoresistive element 101 can be switched between a high resistance state and a low resistance state.

[0064] [Writing] Figures 13A and 13B are diagrams showing writing to the magnetoresistive element according to the first embodiment of the present disclosure. Figures 13A and 13B are diagrams showing changes in the resistance state of the magnetoresistive element 101. Figures 13A and 13B also show the voltages of the selection element 102 and the magnetoresistive element 101 when a write voltage is applied to the memory cell 110 or the like. The write voltage is divided according to the resistances of the selection element 102 and the magnetoresistive element 101, which are connected in series. The rectangle marked "Selection element" represents the voltage of the selection element 102. The rectangle marked "Magnetoresistive element" represents the voltage of the magnetoresistive element 101.

[0065] The resistance value of the magnetoresistive element 101 in the high resistance state can be, for example, 1.0 MΩ. The resistance value of the magnetoresistive element 101 in the low resistance state can be, for example, 300 kΩ to 600 kΩ. The ratio between the low resistance state and the high resistance state is preferably 1.5 or more and 3.0 or less.

[0066] Furthermore, the resistance value (on-resistance) of the selection element 102 in the conductive state can be set to approximately the same resistance value as that of the magnetoresistive element 101 during writing. That is, the on-resistance of the selection element 102 during writing can be set to a value ranging from an intermediate value between the resistance values ​​of the magnetoresistive element 101 in the low resistance state and the high resistance state to the resistance value of the magnetoresistive element 101 in the high resistance state. The on-resistance of the selection element 102 during reading is set to a value sufficiently smaller than the resistance value of the magnetoresistive element 101. For example, the on-resistance of the selection element 102 during reading can be set to approximately 1 / 100 of the resistance value of the magnetoresistive element 101. When applied to the above-mentioned magnetoresistive element 101, the on-resistance can be set to less than 10 kΩ.

[0067] 13A shows a case where the magnetoresistive element 101 is put into a high resistance state as a result of writing. In the figure, the write voltage V Ｌ→Ｈis applied to the memory cell 110 etc. The left side of the figure shows the case where the magnetoresistive element 101 is in a low resistance state. The right side of the figure shows the case where the magnetoresistive element 101 is in a high resistance state. When the magnetoresistive element 101 is in a low resistance state, the write voltage V Ｌ→Ｈ This write voltage V Ｌ→Ｈ When the magnetoresistive element 101 is in a high resistance state, the voltage division to the magnetoresistive element 101 becomes large.

[0068] The magnetoresistive element 101 applies a write voltage V to the memory cell 110 in the low resistance state. Ｌ→Ｈ When the voltage V is applied to the magnetoresistive element 101, the voltage division of the magnetoresistive element 101 becomes VC. Therefore, the resistance state of the magnetoresistive element 101 is reversed, and the magnetoresistive element 101 changes to a high resistance state. On the other hand, when the magnetoresistive element 101 applies a write voltage V to the memory cell 110 etc. in the high resistance state, Ｌ→Ｈ When the write voltage V is applied, the divided voltage of the magnetoresistive element 101 becomes a voltage (VH) that is larger than VC. Therefore, the resistance state of the magnetoresistive element 101 is not reversed, and the magnetoresistive element 101 maintains the high resistance state. Ｌ→Ｈ When the voltage is applied to the memory cell 110, the magnetoresistive element 101 of the memory cell 110 becomes in a high resistance state.

[0069] 13B shows a case where the magnetoresistive element 101 is put into a low resistance state as a result of writing. In the figure, the write voltage V Ｈ→Ｌ is applied to the memory cell 110 etc. The left side of the figure shows the case where the magnetoresistive element 101 is in a high resistance state. The right side of the figure shows the case where the magnetoresistive element 101 is in a low resistance state. When the magnetoresistive element 101 is in a high resistance state, the write voltage V Ｈ→Ｌ This write voltage V Ｈ→Ｌ When the magnetoresistive element 101 is in a low resistance state, the voltage division to the magnetoresistive element 101 is small.

[0070] The magnetoresistive element 101 applies a write voltage VＨ→Ｌ When the voltage V is applied to the magnetoresistive element 101, the voltage division of the magnetoresistive element 101 becomes VC. Therefore, the resistance state of the magnetoresistive element 101 is reversed, and the magnetoresistive element 101 changes to a low resistance state. On the other hand, when the magnetoresistive element 101 applies a write voltage V to the memory cell 110 etc. in the low resistance state, Ｈ→Ｌ When the write voltage V is applied, the divided voltage of the magnetoresistive element 101 becomes a voltage (VL) smaller than VC. Therefore, the resistance state of the magnetoresistive element 101 is not reversed, and the magnetoresistive element 101 maintains the low resistance state. Ｈ→Ｌ When the voltage is applied to the memory cell 110, the magnetoresistive element 101 of the memory cell 110 is brought into a low resistance state.

[0071] The selection element 102 is connected to a write voltage V Ｌ→Ｈ When applying a voltage such as the above, the on-resistance of the magnetoresistive element 101 must be set to a voltage close to VC. By adjusting the gate voltage of the selection element 102, the selection element 102 can be set to a desired on-resistance.

[0072] Write voltage V Ｌ→Ｈ and the write voltage V Ｈ→Ｌ The pulse width is preferably, for example, 0.1 ns or more and 20 ns or less. If the pulse width is 0.1 ns or more, precession can be reliably generated. If the pulse width is 20 ns or less, the precession settles (stabilizes). On the other hand, if the pulse width exceeds 20 ns, the magnetization is completely oriented in the direction of the external magnetic field, and the precession ends.

[0073] In this way, the memory device 4 according to the first embodiment of the present disclosure stores data in units of memory cell pairs 100 each including a memory cell 110 and a memory cell 120. Furthermore, writing is performed by simultaneously applying a write voltage to the memory cells 110 and 120. This reduces the time required for writing. Furthermore, it is also possible to omit the initial writing process required in conventional memory elements.

[0074] Furthermore, by shortening the write time, it is possible to speed up the write time to the same level as the read time. This allows write and read operations to be performed in the same clock cycle, just like in an SRAM, thereby improving the convenience of the memory system 1.

[0075] (2. Second Embodiment) The memory device 4 of the first embodiment described above applies a write voltage to the memory cells 110 and 120. In contrast, the memory device 4 of the second embodiment of the present disclosure differs from the first embodiment described above in that a write current is passed through the memory cells 110 and 120.

[0076] [Configuration of Memory System] Fig. 14 is a diagram showing a configuration example of a memory system according to the second embodiment of the present disclosure. Similar to Fig. 1, Fig. 14 is a block diagram showing a configuration example of a memory system 1. The memory system 1 in Fig. 1 differs from the memory system 1 in Fig. 1 in that it includes a write current generation circuit 210 instead of the write voltage generation circuit 80.

[0077] The write current generating circuit 210 generates a write current for the memory cell 110 and the memory cell 120. In the memory device 4 according to the second embodiment of the present disclosure, a voltage for writing is applied to the magnetoresistive effect element 101 by passing a predetermined write current through the memory cell 110 etc. The write current generating circuit 210 generates two write currents of different magnitudes (write currents I Ｌ→Ｈ and the write current I Ｈ→Ｌ ) to generate the

[0078] 15 is a diagram showing a configuration example of a memory cell array according to a second embodiment of the present disclosure. Similar to FIG. 2, this diagram shows a configuration example of the memory cell array 10 and its surrounding circuits. The circuit in FIG. 15 differs from the circuit in FIG. 2 in that it includes a write current generation circuit 210 instead of the write voltage generation circuit 80, and the gate voltage generation circuit 70 generates a single gate voltage.

[0079] 15 selects one of the two write currents generated by the write current generation circuit 210 and outputs it to the bit line BL1. The selection unit 34 in FIG. 15 selects one of the two write currents generated by the write current generation circuit 210 and outputs it to the bit line BL2. The gate voltage generation circuit 70 in FIG. 15 outputs the generated gate voltage to the selection unit 21.

[0080] 16 is a diagram showing a configuration example of a memory cell according to the second embodiment of the present disclosure. Similar to FIG. 3, this diagram shows voltages applied to the memory cell 110 and the memory cell 120.

[0081] The write current generating circuit 210 generates a write current I Ｌ→Ｈ and the write current I Ｈ→Ｌ The write current I Ｌ→Ｈ is a write current that puts the magnetoresistive element 101 into a high resistance state. Ｈ→Ｌ is a write current that puts the magnetoresistive element 101 into a low resistance state. Ｌ→Ｈ is applied to the magnetoresistive element 101, a write voltage V Ｌ→Ｈ Also, a write current I Ｈ→Ｌ is applied to the magnetoresistive element 101, a write voltage V Ｈ→Ｌ is generated.

[0082] The gate voltage generating circuit 70 generates a gate voltage Vg, which is a gate voltage that puts the selection element 102 into a conductive state.

[0083] 17 is a diagram showing an example of writing according to the second embodiment of the present disclosure. As in FIG. 4, this figure shows an example in which the magnetoresistive element 101 of the memory cell 110 is set to a high resistance state and the magnetoresistive element 101 of the memory cell 120 is set to a low resistance state. As shown in this figure, a write current I Ｌ→Ｈ is supplied to the bit line BL2, and a write current I Ｈ→Ｌ The source line SL is set to the ground potential. The word line WL is applied with a gate voltage Vg. This causes a write current IＬ→Ｈ is supplied to the memory cell 120, and a write current I Ｈ→Ｌ is supplied.

[0084] 18 is a diagram showing an example of writing according to the second embodiment of the present disclosure. As in FIG. 5, this figure shows an example in which the magnetoresistive element 101 of the memory cell 110 is set to a low resistance state and the magnetoresistive element 101 of the memory cell 120 is set to a high resistance state. As shown in this figure, a write current I Ｈ→Ｌ is supplied to the bit line BL2, and a write current I Ｌ→Ｈ The source line SL is set to the ground potential. The word line WL is applied with a gate voltage Vg. This causes a write current I Ｈ→Ｌ is supplied to the memory cell 120, and a write current I Ｌ→Ｈ is supplied.

[0085] 19 is a diagram showing an example of reading according to the second embodiment of the present disclosure. Similar to FIG. 6, this diagram illustrates a case where reading is performed from memory cells 110 and 120. As shown in this diagram, bit lines BL1 and BL2 are set to a floating state, and a read voltage Vread is applied to the source line SL. A gate voltage Vg is applied to the word line WL. Furthermore, switch elements 41 and 42 are turned on. As a result, a current corresponding to the state of the magnetoresistive effect element 101 of the memory cell 110 or the like flows to the sense amplifier 40 via the bit line BL1 or the like.

[0086] [Write Process] FIG. 20 is a diagram showing an example of a processing procedure of a write process according to the second embodiment of the present disclosure. The same figure is a flowchart showing an example of a processing procedure of a write process in the memory device 4. First, the source line control circuit 30 sets the applied voltage of the source line SL to the ground level (step S121). Next, the data to be written to the memory cell pair 100 is referenced (step S123). Specifically, if the memory cell 110 is to be put into a high-resistance state (step S123, Yes), the process proceeds to step S124. On the other hand, if the memory cell 110 is not to be put into a high-resistance state (step S123, No), the process proceeds to step S127.

[0087] In step S124, the bit line and source line control circuit 30 supplies a write current I Ｌ→Ｈ Next, the bit line and source line control circuit 30 sets the write current I to the bit line BL2 (step S124). Ｈ→Ｌ (step S125). Next, the process proceeds to step S126.

[0088] In step S127, the bit line and source line control circuit 30 supplies a write current I Ｈ→Ｌ Next, the bit line and source line control circuit 30 sets the write current I to the bit line BL2. Ｌ→Ｈ (step S128). Next, the process proceeds to step S126.

[0089] In step S126, a write current is supplied to the memory cell pair 100. This can be done by the write current generating circuit 210 generating a write current and supplying it to the memory cell pair 100 via the bit line and source line control circuit 30.

[0090] 21 and 22 are diagrams showing an example of a write process according to the second embodiment of the present disclosure. Similar to FIGS. 8 and 9, FIGS. 22 and 22 are timing charts showing an example of a write process in the memory device 4. FIG. 21 shows a case where the memory cell 110 is set to a high resistance state and the memory cell 120 is set to a low resistance state. FIG. 22 shows a case where the memory cell 110 is set to a low resistance state and the memory cell 120 is set to a high resistance state.

[0091] 22 and 22A, "BL1 Current Config" and "BL2 Current Config" represent logic control signals from the memory control unit 3 to the bit line and source line control circuit 30. Also, "I_BL1" represents the current waveform of the bit line BL1. Also, "I_BL2" represents the current waveform of the bit line BL2. Other than this, the same notations as in FIG. 8 are used.

[0092] 21, a gate voltage is set during periods T1 to T4, and the word line WL is enabled. As a result, a gate voltage Vg is applied to the gate of the selection element 102. Also, a write current is set.

[0093] During the period from T2 to T3, the bit line BL1, the bit line BL2, and the source line SL are enabled. As a result, a write current I Ｌ→Ｈ is supplied to the bit line BL2, and a write current I Ｈ→Ｌ The source line SL is at the ground potential.

[0094] 22, a gate voltage is set during periods T1 to T4, and the word line WL is enabled, whereby a gate voltage Vg is applied to the gate of the selection element 102.

[0095] During the period from T2 to T3, the bit line BL1, the bit line BL2, and the source line SL are enabled. As a result, a write current I Ｈ→Ｌ is supplied to the bit line BL2, and a write current I Ｌ→Ｈ The source line SL is at the ground potential.

[0096] [Reading Process] The reading process of the memory device 4 according to the second embodiment of the present disclosure will be described below. Note that the processing procedure of the reading process is the same as that shown in FIG. 10, and therefore the description thereof will be omitted.

[0097] 23 is a diagram showing an example of a read process according to the second embodiment of the present disclosure. The diagram is a timing chart showing an example of a read process in the memory device 4.

[0098] During the period from T5 to T8, the gate voltage is set and the word line WL is enabled, whereby the gate voltage Vg_read is applied to the gate of the selection element 102. Also, the read voltage is set.

[0099] During the period from T6 to T7, the source line SL is enabled, and the read voltage Vread is supplied to the source line SL. The bit lines BL1 and BL2 are in a floating state.

[0100] 24A and 24B are diagrams showing writing to the magnetoresistive effect element according to the second embodiment of the present disclosure. Similar to FIGS. 13A and 13B, FIGS. 24A and 24B are diagrams showing changes in the resistance state of the magnetoresistive effect element 101. Also, FIGS. 24A and 24B show the voltages of the selection element 102 and the magnetoresistive effect element 101 when a write current is supplied to the memory cell 110 or the like.

[0101] 24A shows a case where the magnetoresistive element 101 is put into a high resistance state as a result of writing. In the figure, the write current I Ｌ→Ｈ is supplied to the memory cell 110 etc. The left side of the figure shows the case where the magnetoresistive element 101 is in a low resistance state. The right side of the figure shows the case where the magnetoresistive element 101 is in a high resistance state. The resistance value of the magnetoresistive element 101 in the low resistance state is Rlow. When the magnetoresistive element 101 is in the low resistance state, the write current I Ｌ→Ｈ In this case, the write current I Ｌ→Ｈ is expressed by the following formula: Ｌ→Ｈ =VC / Rlow The voltage V_MTJ applied to the magnetoresistive element 101 is expressed by the following equation: V_MTJ=I Ｌ→Ｈ ×RMTJ where RMTJ is the resistance value of the magnetoresistive element 101. This write current I Ｌ→Ｈ When the magnetoresistive element 101 is in a high resistance state, the voltage applied to the magnetoresistive element 101 increases.

[0102] The magnetoresistive element 101 supplies a write current I to the memory cell 110 in the low resistance state. Ｌ→Ｈ When the current I flows, the voltage of the magnetoresistive element 101 becomes VC. Therefore, the resistance state of the magnetoresistive element 101 is reversed, and the magnetoresistive element 101 changes to a high resistance state. On the other hand, when the magnetoresistive element 101 is in a high resistance state, a write current I Ｌ→ＨWhen the write current I flows, the voltage of the magnetoresistive element 101 becomes a voltage (VH) that is higher than VC. Therefore, the resistance state of the magnetoresistive element 101 is not reversed, and the magnetoresistive element 101 maintains the high resistance state. Ｌ→Ｈ is supplied to the memory cells 110, the magnetoresistive elements 101 of the memory cells 110, etc., enter a high resistance state.

[0103] 24B shows a case where the magnetoresistive element 101 is put into a low resistance state as a result of writing. In the figure, the write current I Ｈ→Ｌ is supplied to the memory cell 110 etc. The left side of the figure shows the case where the magnetoresistive effect element 101 is in a high resistance state. The right side of the figure shows the case where the magnetoresistive effect element 101 is in a low resistance state. The resistance value of the magnetoresistive effect element 101 in the high resistance state is Rhigh. When the magnetoresistive effect element 101 is in the high resistance state, the write current I Ｈ→Ｌ In this case, the write current I Ｈ→Ｌ is expressed by the following formula: Ｈ→Ｌ =VC / Rhigh The voltage V_MTJ applied to the magnetoresistive element 101 is expressed by the following equation: V_MTJ=I Ｈ→Ｌ ×RMTJ This write current I Ｈ→Ｌ When the magnetoresistive element 101 is in a low resistance state, the voltage applied to the magnetoresistive element 101 is small.

[0104] The magnetoresistive element 101 supplies a write current I to the memory cell 110 in the high resistance state. Ｈ→Ｌ When the current I flows, the voltage of the magnetoresistive element 101 becomes VC. Therefore, the resistance state of the magnetoresistive element 101 is reversed, and the magnetoresistive element 101 changes to a low resistance state. On the other hand, when the magnetoresistive element 101 is in a low resistance state, a write current I Ｈ→Ｌ When the write current I flows, the voltage of the magnetoresistive element 101 becomes a voltage (VL) smaller than VC. Therefore, the resistance state of the magnetoresistive element 101 is not reversed, and the magnetoresistive element 101 maintains the low resistance state. Ｈ→Ｌis supplied to the memory cells 110, the magnetoresistive elements 101 of the memory cells 110, etc., are brought into a low resistance state.

[0105] The configuration of the memory device 4 other than that described above is the same as the configuration of the memory device 4 in the first embodiment of the present disclosure, and therefore description thereof will be omitted.

[0106] In this way, the memory device 4 according to the second embodiment of the present disclosure can simultaneously write to the memory cell 110 and the memory cell 120 by supplying a write current, thereby shortening the write time.

[0107] (3. Third Embodiment) The memory device 4 of the first embodiment described above applies different write voltages to the memory cells 110 and 120. In contrast, the memory device 4 of the third embodiment of the present disclosure differs from the first embodiment described above in that the write voltages are applied to the memory cells 110 and 120 via load resistors.

[0108] [Configuration of Memory System] Fig. 25 is a diagram showing a configuration example of a memory system according to a third embodiment of the present disclosure. Similar to Fig. 1, this figure is a block diagram showing a configuration example of a memory system 1. The memory system 1 in Fig. 25 differs from the memory system 1 in Fig. 1 in that it further includes a load resistance circuit 220.

[0109] The load resistance circuit 220 is a circuit having a load resistance that adjusts the write voltage. In the memory device 4 according to the third embodiment of the present disclosure, the write voltage is applied to the memory cells 110 and the like via the load resistance. By adjusting this load resistance, different write voltages can be generated.

[0110] 26 is a diagram showing a configuration example of a memory cell array according to a third embodiment of the present disclosure. Similar to FIG. 2, this diagram shows a configuration example of the memory cell array 10 and surrounding circuits. The circuit in this diagram differs from the circuit in FIG. 2 in that a load resistance circuit 220 is connected between the write voltage generation circuit 80 and the bit line and source line control circuit 30.

[0111] The load resistance circuit 220 includes load resistors 221 and 222. The load resistors 221 and 222 are connected between the output of the write voltage generation circuit 80 and the selection units 33 and 34. The selection unit 33 in FIG. 26 selects one of the wirings to which the load resistors 221 and 222 are respectively connected. The same applies to the selection unit 34 in FIG. 26. The gate voltage generation circuit 70 in FIG. 26 outputs the generated gate voltage to the selection unit 21.

[0112] 27 is a diagram showing a configuration example of a memory cell according to a third embodiment of the present disclosure. Similar to FIG. 3, this diagram shows voltages applied to the memory cell 110 and the memory cell 120.

[0113] The load resistors 221 and 222 are arranged between the output of the write voltage generating circuit 80 and the bit line BL1, etc. That is, the load resistors 221 and 222 are connected in series to the magnetoresistive element 101. A voltage divided by the load resistor 221 or the load resistor 222 and the magnetoresistive element 101 is applied to the magnetoresistive element 101. By adjusting the values ​​of the load resistors 221 and 222, the write voltage V Ｈ→Ｌ and the write voltage V Ｌ→Ｈ can be applied to the magnetoresistive element 101. The load resistor 221 is Ｌ→Ｈ The resistance value of the load resistor 221 is R Ｌ→Ｈ The load resistor 222 is expressed by the write voltage V Ｈ→Ｌ The resistance value of the load resistor 222 is R Ｈ→Ｌ It is expressed as:

[0114] The gate voltage generating circuit 70 generates a gate voltage Vg, which is a gate voltage that puts the selection element 102 into a conductive state.

[0115] 28 is a diagram showing an example of writing according to the third embodiment of the present disclosure. As with FIG. 4, this figure shows an example in which the magnetoresistive effect element 101 of the memory cell 110 is set to a high resistance state, and the magnetoresistive effect element 101 of the memory cell 120 is set to a low resistance state. As shown in this figure, a write voltage is supplied to the bit line BL1 via a load resistor 221, and a write voltage is supplied to the bit line BL2 via a load resistor 222. In addition, the source line SL is set to ground potential. In addition, a gate voltage Vg is applied to the word line WL. As a result, the memory cell 110 is supplied with the write voltage V Ｌ→Ｈ is applied to the memory cell 120, and a write voltage V Ｈ→Ｌ is applied.

[0116] 29 is a diagram showing an example of writing according to the third embodiment of the present disclosure. As with FIG. 5, this figure shows an example in which the magnetoresistive effect element 101 of the memory cell 110 is set to a low resistance state and the magnetoresistive effect element 101 of the memory cell 120 is set to a high resistance state. As shown in this figure, a write voltage is supplied to the bit line BL1 via a load resistor 222, and a write voltage is supplied to the bit line BL2 via a load resistor 221. In addition, the source line SL is set to ground potential. In addition, a gate voltage Vg is applied to the word line WL. As a result, the memory cell 110 is supplied with the write voltage V Ｈ→Ｌ is applied to the memory cell 120, and a write voltage V Ｌ→Ｈ is applied.

[0117] 30 is a diagram showing an example of reading according to the third embodiment of the present disclosure. Similar to FIG. 6, this diagram illustrates a case where reading is performed from memory cells 110 and 120. As shown in this diagram, bit lines BL1 and BL2 are set to a floating state, and a read voltage Vread is applied to the source line SL. A gate voltage Vg is applied to the word line WL. Furthermore, switch elements 41 and 42 are turned on. As a result, a current corresponding to the state of the magnetoresistive effect element 101 of the memory cell 110 or the like flows to the sense amplifier 40 via the bit line BL1 or the like.

[0118] [Write Process] FIG. 31 is a diagram showing an example of a processing procedure of a write process according to the third embodiment of the present disclosure. The same figure is a flowchart showing an example of a processing procedure of a write process in the memory device 4. First, the source line control circuit 30 sets the applied voltage of the source line SL to the ground level (step S131). Next, the data to be written to the memory cell pair 100 is referenced (step S133). Specifically, if the memory cell 110 is to be put into a high-resistance state (step S133, Yes), the process proceeds to step S134. On the other hand, if the memory cell 110 is not to be put into a high-resistance state (step S133, No), the process proceeds to step S137.

[0119] In step S134, the bit line and source line control circuit 30 sets the load resistance of the bit line BL1 to R Ｌ→Ｈ Next, the bit line and source line control circuit 30 sets the load resistance of the bit line BL2 to R Ｈ→Ｌ (step S135). Next, the process proceeds to step S136.

[0120] In step S137, the bit line and source line control circuit 30 sets the load resistance of the bit line BL1 to R Ｈ→Ｌ Next, the bit line and source line control circuit 30 sets the load resistance of the bit line BL2 to R Ｌ→Ｈ (step S138). Next, the process proceeds to step S136.

[0121] In step S136, a write voltage is supplied to the memory cell pair 100. This can be done by the write voltage generating circuit 80 generating and outputting the write voltage.

[0122] 32 and 33 are diagrams showing an example of a write process according to the third embodiment of the present disclosure. Similar to FIGS. 8 and 9, FIGS. 32 and 33 are timing charts showing an example of a write process in the memory device 4. FIG. 32 shows a case where the memory cell 110 is set to a high resistance state and the memory cell 120 is set to a low resistance state. FIG. 33 shows a case where the memory cell 110 is set to a low resistance state and the memory cell 120 is set to a high resistance state.

[0123] 32 and 33, "BL1 Resistance Config" and "BL2 Resistance Config" represent logic control signals from the memory control unit 3 to the bit line and source line control circuit 30. Other than this, the same notation as in FIG. 8 is used.

[0124] 32, a gate voltage is set during the period from T1 to T4, and the word line WL is enabled. As a result, the gate voltage Vg is applied to the gate of the selection element 102. In addition, R Ｌ→Ｈ A load resistor R is connected to the bit line BL2. Ｈ→Ｌ A load resistor of

[0125] During the period from T2 to T3, the bit line BL1, the bit line BL2, and the source line SL are enabled. As a result, the write voltage V Ｌ→Ｈ is supplied to the bit line BL2, and the write voltage V Ｈ→Ｌ The source line SL is at the ground potential. The voltages of the bit line BL1 and the like have waveforms that correspond to the change in resistance of the magnetoresistive element 101.

[0126] 33, a gate voltage is set during the period from T1 to T4, and the word line WL is enabled. As a result, the gate voltage Vg is applied to the gate of the selection element 102. In addition, R Ｈ→Ｌ A load resistor R is connected to the bit line BL2. Ｌ→Ｈ A load resistor of

[0127] During the period from T2 to T3, the bit line BL1, the bit line BL2, and the source line SL are enabled. As a result, the write voltage V Ｈ→Ｌ is supplied to the bit line BL2, and the write voltage V Ｌ→Ｈ The source line SL is at the ground potential.

[0128] [Reading Process] The reading process of the memory device 4 according to the second embodiment of the present disclosure will be described below. Note that the processing procedure of the reading process is the same as that shown in FIG. 10, and therefore the description thereof will be omitted.

[0129] 34 is a diagram showing an example of a read process according to the third embodiment of the present disclosure. The diagram is a timing chart showing an example of a read process in the memory device 4.

[0130] During the period from T5 to T8, the gate voltage is set and the word line WL is enabled, whereby the gate voltage Vg_read is applied to the gate of the selection element 102. Also, the read voltage is set.

[0131] During the period from T6 to T7, the source line SL is enabled, and the read voltage Vread is supplied to the source line SL. The bit lines BL1 and BL2 are in a floating state.

[0132] 35A and 35B are diagrams illustrating writing to the magnetoresistive element according to the third embodiment of the present disclosure. Similar to FIGS. 13A and 13B, these diagrams illustrate changes in the resistance state of the magnetoresistive element 101.

[0133] 35A shows a case where the magnetoresistive element 101 is put into a high resistance state as a result of writing. In this figure, the write voltage is applied to the resistance value R Ｌ→Ｈ This write voltage is designated as Vwrite. The left side of the figure shows the case where the magnetoresistive element 101 is in a low resistance state. The right side of the figure shows the case where the magnetoresistive element 101 is in a high resistance state. When the magnetoresistive element 101 is in a low resistance state, the resistance value R at which the voltage of the magnetoresistive element 101 becomes the above-mentioned VC is Ｌ→Ｈ The voltage V_MTJ applied to the magnetoresistive element 101 is expressed by the following equation: V_MTJ=Vwrite / (1+R Ｌ→Ｈ / RMTJ)

[0134] The magnetoresistive element 101 has a resistance value R Ｌ→ＨWhen a write voltage Vwrite is applied via a load resistance of , the voltage of the magnetoresistive element 101 becomes VC. Therefore, the resistance state of the magnetoresistive element 101 is reversed, and the magnetoresistive element 101 changes to a high resistance state. On the other hand, when the magnetoresistive element 101 is applied to the memory cell 110 etc. in the high resistance state, the resistance value R Ｌ→Ｈ When a write voltage Vwrite is applied via a load resistance of R, the voltage of the magnetoresistive element 101 becomes a voltage (VH) that is higher than VC. Therefore, the resistance state of the magnetoresistive element 101 is not reversed, and the magnetoresistive element 101 maintains a high resistance state. Ｌ→Ｈ When a write voltage is applied to the memory cell 110 etc. via the load resistance, the magnetoresistive element 101 of the memory cell 110 etc. becomes in a high resistance state.

[0135] 35B shows a case where the magnetoresistive element 101 is put into a low resistance state as a result of writing. In the figure, the write voltage Vwrite is applied to the resistance value R Ｈ→Ｌ The left side of the figure shows the case where the magnetoresistive element 101 is in a high resistance state. The right side of the figure shows the case where the magnetoresistive element 101 is in a low resistance state. When the magnetoresistive element 101 is in a high resistance state, the resistance value R at which the voltage of the magnetoresistive element 101 becomes the above-mentioned VC is Ｈ→Ｌ The voltage V_MTJ applied to the magnetoresistive element 101 is expressed by the following equation: V_MTJ=Vwrite / (1+R Ｈ→Ｌ / RMTJ)

[0136] The magnetoresistive element 101 has a resistance value R Ｈ→Ｌ When a write voltage Vwrite is applied via a load resistance of , the voltage of the magnetoresistive element 101 becomes VC. Therefore, the resistance state of the magnetoresistive element 101 is reversed, and the magnetoresistive element 101 changes to a low resistance state. On the other hand, when the magnetoresistive element 101 applies a resistance value R Ｈ→ＬWhen a write voltage Vwrite is applied via a load resistance of R, the voltage of the magnetoresistive element 101 becomes a voltage (VL) smaller than VC. Therefore, the resistance state of the magnetoresistive element 101 is not reversed, and the magnetoresistive element 101 maintains the low resistance state. Ｈ→Ｌ When a write voltage is applied to the memory cell 110 etc. via the load resistance, the magnetoresistive element 101 of the memory cell 110 etc. goes into a low resistance state.

[0137] The configuration of the memory device 4 other than that described above is the same as the configuration of the memory device 4 in the first embodiment of the present disclosure, and therefore description thereof will be omitted.

[0138] In this way, the memory device 4 according to the third embodiment of the present disclosure can simultaneously write to the memory cell 110 and the memory cell 120 by applying a write voltage via a load resistor, thereby reducing the write time.

[0139] (4. Fourth Embodiment) In the memory device 4 of the above-described embodiment, the write voltage, etc. is applied only once. In contrast, the memory device 4 of the fourth embodiment of the present disclosure differs from the first embodiment in that the write voltage, etc. is applied multiple times.

[0140] [Write Process] Fig. 36 is a diagram showing an example of a processing procedure of a write process according to the fourth embodiment of the present disclosure. The figure is a flow chart showing an example of a processing procedure of a write process in the memory device 4. The figure also corresponds to the processing of Fig. 7. First, the processing up to step S106 is performed. Next, a write voltage is applied to the memory cell pair 100 (step S161). Next, a write voltage is applied to the memory cell pair 100 (step S162). In this way, the write voltage is supplied three times.

[0141] 37 is a diagram showing another example of the processing procedure of the write process according to the fourth embodiment of the present disclosure. The figure is a flowchart showing another example of the processing procedure of the write process in the memory device 4. The figure also corresponds to the processing in FIG. 20. First, the processing up to step S126 is performed. Next, a write current is supplied to the memory cell pair 100 (step S164). Next, a write current is supplied to the memory cell pair 100 (step S165). In this manner, the write current is supplied three times.

[0142] 38 is a diagram showing an example of a processing procedure of a write process according to the fourth embodiment of the present disclosure. The figure is a flowchart showing an example of a processing procedure of a write process in the memory device 4. The figure also corresponds to the processing of FIG. 31. First, the processing up to step S136 is performed. Next, a write voltage is applied to the memory cell pair 100 (step S167). Next, a write voltage is applied to the memory cell pair 100 (step S168). In this manner, the write voltage is applied three times.

[0143] The configuration of the memory device 4 other than that described above is the same as the configuration of the memory device 4 in the first embodiment of the present disclosure, and therefore description thereof will be omitted.

[0144] In this way, the memory device 4 according to the fourth embodiment of the present disclosure applies the write voltage etc. multiple times, thereby ensuring complete writing.

[0145] (5. Fifth Embodiment) In the memory device 4 of the first embodiment described above, the write voltage etc. is applied only once. In contrast, the memory device 4 of the fifth embodiment of the present disclosure differs from the first embodiment described above in that the write result is verified.

[0146] [Write Processing] FIG. 39 is a diagram showing an example of a processing procedure of a write processing according to the fifth embodiment of the present disclosure. This diagram is a flowchart showing an example of a processing procedure of a write processing in the memory device 4. This diagram corresponds to the processing of FIG. 7. First, processing up to step S106 is performed. Next, a read is performed on the memory cell pair 100 to which data has been written (step S110). This read can be performed according to the processing procedure of FIG. 10. Next, the memory control unit 3 determines whether the read data matches the expected value (step S109). As a result, if the read data does not match the expected value (step S109, No), the memory control unit 3 proceeds to processing of step S101. On the other hand, if the read data matches the expected value (step S109, Yes), the memory control unit 3 completes the processing. In this way, the processing procedure of FIG. 39 verifies the written data. Depending on the verification result, a write processing is performed again.

[0147] FIG. 40 is a diagram showing another example of the processing procedure of the write process according to the fifth embodiment of the present disclosure. This figure is a flowchart showing another example of the processing procedure of the write process in the memory device 4. This figure corresponds to the processing of FIG. 20 . First, processing up to step S126 is performed. Next, a read is performed on the memory cell pair 100 to which writing has been performed (step S110). Next, the memory control unit 3 determines whether the read data matches the expected value (step S129). As a result, if the read data does not match the expected value (step S129, No), the memory control unit 3 proceeds to processing of step S121. On the other hand, if the read data matches the expected value (step S129, Yes), the memory control unit 3 completes the processing. In this way, the processing procedure of FIG. 40 verifies the written data. Depending on the verification result, the write process is performed again.

[0148] FIG. 41 is a diagram showing an example of a processing procedure of a write process according to the fifth embodiment of the present disclosure. This diagram is a flowchart showing an example of a processing procedure of a write process in the memory device 4. This diagram corresponds to the processing of FIG. 31. First, processing up to step S136 is performed. Next, a read is performed on the memory cell pair 100 to which writing has been performed (step S110). Next, the memory control unit 3 determines whether the read data matches the expected value (step S139). As a result, if the read data does not match the expected value (step S139, No), the memory control unit 3 proceeds to processing of step S131. On the other hand, if the read data matches the expected value (step S139, Yes), the memory control unit 3 completes the processing. In this way, the processing procedure of FIG. 41 verifies the written data. Depending on the verification result, the write process is performed again.

[0149] The configuration of the memory device 4 other than that described above is the same as the configuration of the memory device 4 in the first embodiment of the present disclosure, and therefore description thereof will be omitted.

[0150] In this way, the memory device 4 according to the fifth embodiment of the present disclosure verifies the write data and writes it again depending on the verification result, thereby ensuring that the write is complete.

[0151] (6. Sixth Embodiment) In the memory device 4 of the first embodiment described above, a common source line SL is wired to the memory cells 110 and the memory cells 120. In contrast, the memory device 4 of the sixth embodiment of the present disclosure differs from the first embodiment described above in that a source line SL is arranged for each of the memory cells 110 and the memory cells 120.

[0152] [Configuration of Memory System] Fig. 42 is a diagram showing a configuration example of a memory system according to the sixth embodiment of the present disclosure. Similar to Fig. 1, the figure is a block diagram showing a configuration example of a memory system 1. The memory system 1 in the figure differs from the memory system 1 in Fig. 1 in that it includes a source line SL1 and a source line SL2.

[0153] The source line SL1 is wired to the memory cell 110. The source line SL2 is wired to the memory cell 120.

[0154] 43 is a diagram showing a configuration example of a memory cell array according to a sixth embodiment of the present disclosure. Similar to FIG. 2, this diagram shows a configuration example of the memory cell array 10 and surrounding circuits. The circuit in this diagram differs from the circuit in FIG. 2 in that it further includes a selection unit 36. This selection unit 36 ​​is connected to source line SL2. Furthermore, a selection unit 35 in this diagram is connected to source line SL1.

[0155] 44 is a diagram showing a configuration example of a memory cell according to the sixth embodiment of the present disclosure. Similar to FIG. 3, this diagram shows voltages applied to the memory cell 110 and the memory cell 120.

[0156] The configuration of the memory device 4 other than that described above is the same as the configuration of the memory device 4 in the first embodiment of the present disclosure, and therefore description thereof will be omitted.

[0157] In this way, in the memory device 4 according to the sixth embodiment of the present disclosure, a source line SL is arranged for each of the memory cells 110 and the memory cells 120 .

[0158] (7. Seventh Embodiment) In the memory device 4 of the second embodiment described above, a common source line SL is wired to the memory cells 110 and 120. In contrast, the memory device 4 of the seventh embodiment of the present disclosure differs from the first embodiment described above in that a source line SL is arranged for each of the memory cells 110 and 120.

[0159] [Configuration of Memory System] Fig. 45 is a diagram showing a configuration example of a memory system according to the seventh embodiment of the present disclosure. Similar to Fig. 14, the figure is a block diagram showing a configuration example of a memory system 1. The memory system 1 in the figure differs from the memory system 1 in Fig. 14 in that it includes a source line SL1 and a source line SL2.

[0160] The source line SL1 is wired to the memory cell 110. The source line SL2 is wired to the memory cell 120.

[0161] 46 is a diagram showing a configuration example of a memory cell array according to a seventh embodiment of the present disclosure. Similar to FIG. 15, this diagram shows a configuration example of the memory cell array 10 and surrounding circuits. The circuit in this diagram differs from the circuit in FIG. 15 in that it further includes a selection unit 36. This selection unit 36 ​​is connected to source line SL2. Furthermore, the selection unit 35 in this diagram is connected to source line SL1.

[0162] 47 is a diagram showing a configuration example of a memory cell according to the seventh embodiment of the present disclosure. Similar to FIG. 16, this diagram shows voltages applied to the memory cell 110 and the memory cell 120.

[0163] The configuration of the memory device 4 other than that described above is the same as the configuration of the memory device 4 in the second embodiment of the present disclosure, and therefore description thereof will be omitted.

[0164] In this manner, in the memory device 4 according to the seventh embodiment of the present disclosure, a source line SL is arranged for each of the memory cells 110 and the memory cells 120 .

[0165] (8. Eighth Embodiment) In the memory device 4 of the third embodiment described above, a common source line SL is wired to the memory cells 110 and the memory cells 120. In contrast, the memory device 4 of the eighth embodiment of the present disclosure differs from the first embodiment described above in that a source line SL is arranged for each of the memory cells 110 and the memory cells 120.

[0166] [Configuration of Memory System] Figure 48 is a diagram showing a configuration example of a memory system according to an eighth embodiment of the present disclosure. Similar to Figure 25, this figure is a block diagram showing a configuration example of a memory system 1. The memory system 1 in this figure differs from the memory system 1 in Figure 25 in that it includes a source line SL1 and a source line SL2.

[0167] The source line SL1 is wired to the memory cell 110. The source line SL2 is wired to the memory cell 120.

[0168] 49 is a diagram showing a configuration example of a memory cell array according to an eighth embodiment of the present disclosure. Similar to FIG. 26, this diagram shows a configuration example of the memory cell array 10 and surrounding circuits. The circuit in this diagram differs from the circuit in FIG. 15 in that it further includes a selection unit 36. This selection unit 36 ​​is connected to source line SL2. Furthermore, the selection unit 35 in this diagram is connected to source line SL1.

[0169] 50 is a diagram showing a configuration example of a memory cell according to the eighth embodiment of the present disclosure. Similar to FIG. 27, this diagram shows voltages applied to the memory cell 110 and the memory cell 120.

[0170] The configuration of the memory device 4 other than that described above is the same as the configuration of the memory device 4 in the third embodiment of the present disclosure, and therefore description thereof will be omitted.

[0171] In this way, in the memory device 4 according to the eighth embodiment of the present disclosure, a source line SL is arranged for each of the memory cells 110 and the memory cells 120 .

[0172] (9. Ninth Embodiment) The memory device 4 of the first embodiment described above uses a selection element 102 configured with an n-channel MOS transistor. In contrast, the memory device 4 of the ninth embodiment of the present disclosure differs from the first embodiment described above in that it uses a selection element 102 configured with a p-channel MOS transistor.

[0173] [Configuration of Memory System] Figure 51 is a diagram showing a configuration example of a memory system according to a ninth embodiment of the present disclosure. Similar to Figure 1, this figure is a block diagram showing a configuration example of a memory system 1. The memory system 1 in this figure differs from the memory system 1 in Figure 1 in that it includes a selection element 103 instead of the selection element 102 of the memory cell 110 and the memory cell 120. A p-channel MOS transistor can be applied to the selection element 103.

[0174] 52 is a diagram showing a configuration example of a memory cell array according to a ninth embodiment of the present disclosure. Similar to FIG. 2, this diagram shows a configuration example of a memory cell array 10 and peripheral circuits.

[0175] In the memory cell 110, one of the two terminals of the magnetoresistive element 101 is connected to the bit line BL, and the other terminal is connected to the source terminal of the selection element 103. In addition, the gate terminal of the selection element 103 of the memory cell 110 is connected to the word line WL, and the drain terminal is connected to the source line SL1.

[0176] In the memory cell 120, one of the two terminals of the magnetoresistive element 101 is connected to the bit line BL, and the other terminal is connected to the source terminal of the selection element 103. The gate terminal of the selection element 103 of the memory cell 120 is connected to the word line WL, and the drain terminal is connected to the source line SL2. The source line SL1 is an example of a "first source line" in the present disclosure. The source line SL2 is an example of a "second source line" in the present disclosure.

[0177] 53 is a diagram showing a configuration example of a memory cell according to the ninth embodiment of the present disclosure. Similar to FIG. 3, this diagram shows voltages applied to the memory cell 110 and the memory cell 120.

[0178] 54 is a diagram showing an example of writing according to the ninth embodiment of the present disclosure. As in FIG. 4, this figure shows an example in which the magnetoresistive effect element 101 of the memory cell 110 is set to a high resistance state and the magnetoresistive effect element 101 of the memory cell 120 is set to a low resistance state. As shown in this figure, when a write voltage V Ｌ→Ｈ is applied to the source line SL2, and a write voltage V Ｈ→Ｌ The bit line BL is set to the ground potential. The word line WL is applied with a gate voltage Vg_write. This causes the memory cell 110 to receive a write voltage V Ｌ→Ｈ is applied to the memory cell 120, and a write voltage V Ｈ→Ｌ is applied.

[0179] 55 is a diagram showing an example of writing according to the ninth embodiment of the present disclosure. As in FIG. 5, this figure shows an example in which the magnetoresistive effect element 101 of the memory cell 110 is set to a low resistance state and the magnetoresistive effect element 101 of the memory cell 120 is set to a high resistance state. As shown in this figure, when a write voltage V Ｈ→Ｌis applied to the source line SL2, and a write voltage V Ｌ→Ｈ The bit line BL is set to the ground potential. The word line WL is applied with _write. This causes the memory cell 110 to receive the write voltage V Ｈ→Ｌ is applied to the memory cell 120, and a write voltage V Ｌ→Ｈ is applied.

[0180] FIG. 56 is a diagram showing an example of reading according to the ninth embodiment of the present disclosure. Similar to FIG. 6, this diagram illustrates a case where reading is performed from the memory cells 110 and 120. As shown in this diagram, the source lines SL1 and SL2 are set to a floating state, and a read voltage Vread is applied to the bit line BL. A gate voltage Vg_read is applied to the word line WL. Furthermore, the switch elements 41 and 42 are turned on. As a result, a current corresponding to the state of the magnetoresistive effect element 101 of the memory cell 110 or the like flows to the sense amplifier 40 via the source line SL1 or the like.

[0181] [Write Process] FIG. 57 is a diagram showing an example of a processing procedure of a write process according to the ninth embodiment of the present disclosure. This figure is a flowchart showing an example of a processing procedure of a write process in the memory device 4. First, the bit line and source line control circuit 30 sets the voltage applied to the bit line BL to the ground level (step S141). Next, the word line control circuit 20 sets the voltage applied to the word line WL to the gate voltage Vg_write (step S142). Next, the data to be written to the memory cell pair 100 is referenced (step S143). Specifically, if the memory cell 110 is to be put into a high-resistance state (step S143, Yes), the process proceeds to step S144. On the other hand, if the memory cell 110 is not to be put into a high-resistance state (step S143, No), the process proceeds to step S147.

[0182] In step S144, the bit line and source line control circuit 30 applies a write voltage V Ｌ→Ｈ Next, the bit line and source line control circuit 30 sets the write voltage V Ｈ→Ｌ (step S145). Next, the process proceeds to step S146.

[0183] In step S147, the bit line and source line control circuit 30 applies a write voltage V Ｈ→Ｌ Next, the bit line and source line control circuit 30 sets the write voltage V Ｌ→Ｈ (step S148). Next, the process proceeds to step S146.

[0184] In step S146, a write voltage is applied to the memory cell pair 100. This can be done by the write voltage generation circuit 80 generating a write voltage and applying it to the memory cell pair 100 via the bit line and source line control circuit 30.

[0185] 58 and 59 are diagrams showing an example of a write process according to the ninth embodiment of the present disclosure. Similar to FIGS. 8 and 9, FIGS. 58 and 59 are timing charts showing an example of a write process in the memory device 4. FIG. 58 shows a case where the memory cell 110 is set to a high resistance state and the memory cell 120 is set to a low resistance state. FIG. 59 shows a case where the memory cell 110 is set to a low resistance state and the memory cell 120 is set to a high resistance state.

[0186] "SL1 Voltage Config," "SL2 Voltage Config," and "BL Voltage Config" in Figures 58 and 59 represent logic control signals from the memory control unit 3 to the bit line and source line control circuit 30. Also, "V_SL1" represents the voltage waveform of the source line SL1. Also, "V_SL2" represents the voltage waveform of the source line SL2. Other than this, the same notations as in Figure 8 are used.

[0187] 58, a gate voltage is set during periods T1 to T4, and the word line WL is enabled. As a result, a gate voltage Vg_write is applied to the gate of the selection element 103. Also, a write voltage is set.

[0188] During the period from T2 to T3, the source line SL1, the source line SL2, and the bit line BL are enabled. As a result, the source line SL1 is applied with a write voltage V Ｌ→Ｈis supplied to the source line SL2, and a write voltage V Ｈ→Ｌ The bit line BL is at the ground potential.

[0189] 59, a gate voltage is set during periods T1 to T4, and the word line WL is enabled. As a result, a gate voltage Vg_write is applied to the gate of the selection element 103. Also, a write voltage is set.

[0190] During the period from T2 to T3, the source line SL1, the source line SL2, and the bit line BL are enabled. As a result, the source line SL1 is applied with a write voltage V Ｈ→Ｌ is applied to the source line SL2, and a write voltage V Ｌ→Ｈ is applied to the bit line BL, and the bit line BL is set to the ground potential.

[0191] [Read Process] Figure 60 is a diagram showing an example of a processing procedure for a read process according to the ninth embodiment of the present disclosure. Similar to Figure 10, this figure is a flowchart showing an example of a processing procedure for a read process in the memory device 4. First, the bit line and source line control circuit 30 sets the voltage applied to the bit line BL to the read voltage Vread (step S151). Next, the word line control circuit 20 sets the voltage applied to the word line WL to the gate voltage Vg_read (step S152). Next, a read voltage is applied to the memory cell pair 100 (step S153). This can be achieved by the read voltage generation circuit 90 generating the read voltage Vread and applying it to the memory cell pair 100 via the bit line and source line control circuit 30.

[0192] 61 is a diagram showing an example of a read process according to the ninth embodiment of the present disclosure. The diagram is a timing chart showing an example of a read process in the memory device 4.

[0193] During the period from T5 to T8, the gate voltage is set and the word line WL is enabled, so that the gate voltage Vg_read is applied to the gate of the selection element 102.

[0194] During the period from T6 to T7, the bit line BL is enabled, and the read voltage Vread is supplied to the bit line BL. The source lines SL1 and SL2 are in a floating state.

[0195] The configuration of the memory device 4 other than that described above is the same as the configuration of the memory device 4 in the first embodiment of the present disclosure, and therefore description thereof will be omitted.

[0196] As described above, in the memory device 4 according to the ninth embodiment of the present disclosure, the memory cells 110 and 120 are provided with the selection elements 102 each configured by a p-channel MOS transistor.

[0197] The configuration of the ninth embodiment of the present disclosure can be applied to other embodiments. Specifically, the memory cell 110 and the memory cell 120 in FIG. 51 can be applied to the second to eighth embodiments of the present disclosure.

[0198] The effects described in this specification are merely examples and are not limiting, and other effects may also be present.

[0199] The present technology can also be configured as follows. (1) A memory device including a memory cell pair including a first memory cell and a second memory cell, each including a magnetoresistive element whose internal resistance changes between a high resistance state and a low resistance state in response to an applied voltage and a selection element connected in series to the magnetoresistive element, and a write circuit that simultaneously writes data to the first memory cell and the second memory cell. (2) The memory device described in (1), in which the memory cell pair has the magnetoresistive element of the first memory cell and the magnetoresistive element of the second memory cell in different states and retains data based on which of the magnetoresistive element of the first memory cell and the magnetoresistive element of the second memory cell is in the high resistance state. (3) The memory device described in (2), in which the write circuit simultaneously applies a high resistance state write voltage that changes the magnetoresistive element to the high resistance state and a low resistance state write voltage that changes the magnetoresistive element to the low resistance state to the first memory cell and the second memory cell. (4) The memory device according to (3), wherein the write circuit simultaneously applies the high-resistance state write voltage and the low-resistance state write voltage, each having a pulse width of 0.1 ns or more and 20 ns or less, to the first memory cell and the second memory cell. (5) The memory device according to (2), wherein the write circuit simultaneously supplies, to the first memory cell and the second memory cell, currents that cause the magnetoresistive element to generate a high-resistance state write voltage that changes the magnetoresistive element to the high-resistance state and a low-resistance state write voltage that changes the magnetoresistive element to the low-resistance state, respectively, to perform writing.(6) The memory device according to (2), further comprising a write voltage generation unit that generates write voltages for the first memory cell and the second memory cell, wherein the write circuit simultaneously applies the write voltage to the first memory cell and the second memory cell to perform writing, and when applying a high-resistance state write voltage that changes the magnetoresistive element to the high-resistance state, applies the write voltage through a resistor that generates the high-resistance state write voltage from the write voltage, and when applying a low-resistance state write voltage that changes the magnetoresistive element to the low-resistance state, applies the write voltage through a resistor that generates the low-resistance state write voltage from the write voltage. (7) The memory device according to any of (1) to (6), wherein the selection element has a drain terminal, a source terminal, and a gate terminal, the magnetoresistive effect element is configured as a two-terminal element, the first memory cell has two terminals of the magnetoresistive effect element, one of which is connected to a first bit line and the other of which is connected to the drain terminal of the selection element, and the gate terminal of the selection element is connected to a word line and a source terminal of the selection element is connected to a source line, and the second memory cell has two terminals of the magnetoresistive effect element, one of which is connected to a second bit line and the other of which is connected to the drain terminal of the selection element, and the gate terminal of the selection element is connected to the word line and a source terminal of the selection element is connected to the source line. (8) The memory device according to any of (1) to (6), wherein the selection element has a drain terminal, a source terminal, and a gate terminal, the magnetoresistive element is configured as a two-terminal element, the first memory cell has two terminals of the magnetoresistive element, one of which is connected to a bit line and the other of which is connected to a source terminal of the selection element, the gate terminal of the selection element is connected to a word line, and the drain terminal is connected to a first source line, and the second memory cell has two terminals of the magnetoresistive element, one of which is connected to the bit line and the other of which is connected to a source terminal of the selection element, the gate terminal of the selection element is connected to the word line, and the drain terminal is connected to a second source line.

[0200] REFERENCE SIGNS LIST 1 memory system 3 memory control unit 4 memory device 10 memory cell array 11 word line 12 bit line 13 source line 80 write voltage generating circuit 100 memory cell pair 101 magnetoresistive effect element 102, 103 selection element 110 memory cell 120 memory cell 210 write current generating circuit 220 load resistance circuit 221, 222 load resistance

Claims

1. A memory device having a pair of memory cells including a first memory cell and a second memory cell, each of which has a magnetoresistive element whose internal resistance state changes between a high resistance state and a low resistance state in response to an applied voltage and a selection element connected in series to the magnetoresistive element; and a write circuit that simultaneously writes to the first memory cell and the second memory cell.

2. The memory device of claim 1, wherein the pair of memory cells retains data based on whether the magnetoresistance effect element of the first memory cell and the magnetoresistance effect element of the second memory cell are in different states and whether the magnetoresistance effect element of the first memory cell or the magnetoresistance effect element of the second memory cell is in the high resistance state.

3. The memory device of claim 2, wherein the write circuit performs writing by simultaneously applying a high resistance state write voltage that changes the magnetoresistance effect element to the high resistance state and a low resistance state write voltage that changes the magnetoresistance effect element to the low resistance state to the first memory cell and the second memory cell.

4. The memory device according to claim 3, wherein said write circuit simultaneously applies said high-resistance state write voltage and said low-resistance state write voltage, each having a pulse width of 0.1 ns or more and 20 ns or less, to said first memory cell and said second memory cell.

5. The memory device of claim 2, wherein the write circuit performs writing by simultaneously supplying to the first memory cell and the second memory cell currents that cause the magnetoresistive element to generate a high resistance state write voltage that changes the magnetoresistive element to the high resistance state and a low resistance state write voltage that changes the magnetoresistive element to the low resistance state, respectively.

6. A memory device as described in claim 2, further comprising a write voltage generation unit which generates write voltages for the first memory cell and the second memory cell, wherein the write circuit performs writing by simultaneously applying the write voltage to the first memory cell and the second memory cell, and when applying a high resistance state write voltage that changes the magnetoresistance effect element to the high resistance state, the write voltage is applied via a resistor which generates the high resistance state write voltage from the write voltage, and when applying a low resistance state write voltage that changes the magnetoresistance effect element to the low resistance state, the write voltage is applied via a resistor which generates the low resistance state write voltage from the write voltage.

7. The memory device of claim 1, wherein the selection element has a drain terminal, a source terminal and a gate terminal, the magnetoresistance effect element is configured as a two-terminal element, the first memory cell has two terminals of the magnetoresistance effect element, one of which is connected to a first bit line and the other of which is connected to the drain terminal of the selection element, and the gate terminal of the selection element is connected to a word line and a source terminal of the selection element is connected to a source line, and the second memory cell has two terminals of the magnetoresistance effect element, one of which is connected to a second bit line and the other of which is connected to the drain terminal of the selection element, and the gate terminal of the selection element is connected to the word line and a source terminal of the selection element is connected to the source line.

8. The memory device of claim 1, wherein the selection element has a drain terminal, a source terminal and a gate terminal, the magnetoresistance effect element is configured as a two-terminal element, the first memory cell has two terminals of the magnetoresistance effect element, one of which is connected to a bit line and the other of which is connected to a source terminal of the selection element, and the gate terminal of the selection element is connected to a word line and a drain terminal of the selection element is connected to a first source line, and the second memory cell has two terminals of the magnetoresistance effect element, one of which is connected to the bit line and the other of which is connected to a source terminal of the selection element, and the gate terminal of the selection element is connected to the word line and a drain terminal of the selection element is connected to a second source line.

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