Display driving device and method capable of controlling brightness of pixel

Abstract

The present disclosure relates to a display driving device and method capable of controlling the brightness of a pixel. The display driving device according to one embodiment of the present disclosure comprises: a pixel driving circuit connected to a plurality of LEDs forming at least one row and at least one column and driving the LEDs in a PWM scheme; a control unit determining a PWM duty ratio (PWM ON Duty) indicating a light emitting time period of the LEDs during one frame period; and a timing controller generating a first clock signal according to the PWM duty ratio and supplying the first clock signal to the pixel driving circuit in units of rows or columns through a shift register, wherein if the PWM duty ratio is changed, the timing controller may generate a second clock signal corresponding to the changed PWM duty ratio, and selectively supply the first clock signal or the second clock signal to the pixel driving circuit.

Description

Display driving device and method capable of controlling the brightness of pixels

[0001] The present invention relates to a display driving device and method capable of detailed brightness control using multiple clock signals. In addition, the present invention relates to a display driving device and method capable of detailed brightness control using a dummy signal.

[0002] The present invention relates to a display driving device and method, and more particularly, to a display driving device and method capable of flexibly controlling a change in PWM ON Duty that adjusts the light-emitting time of a pixel.

[0003] A typical display driver device includes multiple pixels, and is composed of M * N pixels arranged in a row. Each pixel may include one or more light-emitting elements, and is typically composed of three light-emitting elements (R, G, B). Each light-emitting element is called a subpixel.

[0004] Among the various methods for controlling the operation of sub-pixels, there is a PWM control method that stores video data for controlling the light emission of sub-frames during a single frame in the built-in memory and controls the grayscale through a PWM (Pulse Width Modulation) signal.

[0005] In the case of a pixel driven by PWM, image data is stored in the pixel memory for a certain period of time (pixel programming). Then, the sub-pixel emits light during the emission time (On duty) within one frame according to the image data stored in the pixel memory. At this time, the brightness of the sub-pixel is controlled by the PWM method. A gray clock signal for PWM control is input to the driving circuit of the sub-pixel, as illustrated in Fig. 1. At this time, the number of gray clock signals (MSB, MSB-1, MSB-2, 쪋, LSB) is determined according to the number of bits of the image data.

[0006] The emission of sub-pixels can be controlled by changing the emission time, and the change in emission time can be controlled by adjusting the PWM ON Duty.

[0007] However, when the emission time is changed to control the brightness of the subpixel, an error occurs because the output signal before the change is affected by the changed gray clock signal as the gray clock signal changes.

[0008] In addition, controlling the brightness of pixels by the PWM method with a limited number of driving signals has the problem of difficulty in fine brightness control. For example, since the period of the gray clock signal input to the driving circuit of the sub-pixel is constant, if it is shifted at a constant rate with the period of the gray clock signal, there is a problem in that fine brightness control based on a time interval of a value smaller than the period of the gray clock signal is difficult.

[0009] The background technology described above is technical information that the inventor possessed for the purpose of deriving the present invention or acquired in the process of deriving the present invention, and cannot necessarily be considered as publicly known technology disclosed to the general public prior to the application for the present invention.

[0010] The present invention provides a display driving device and method capable of detailed brightness control using multiple clock signals. In addition, the present invention provides a display driving device capable of detailed brightness control using a dummy signal.

[0011] The problems addressed by the present invention are not limited to those mentioned above. Other problems and advantages of the present invention not mentioned above can be understood through the following description and will be more clearly understood through embodiments of the present invention. Furthermore, it will be appreciated that the problems and advantages addressed by the present invention can be realized by the means and combinations thereof set forth in the claims.

[0012] As a technical means for achieving the above-described technical problem, one embodiment of the present disclosure may provide a display driving device, including: a pixel driving circuit that is respectively connected to a plurality of LEDs forming at least one row and column and drives the LEDs in a PWM manner; a control unit that determines a PWM duty ratio (PWM ON Duty) indicating a light-emitting time period of the LEDs during one frame period; and a timing controller that generates a first clock signal according to the PWM duty ratio and supplies the first clock signal to the pixel driving circuit in units of rows or columns through a shift register; wherein, when the PWM duty ratio is changed, the timing controller generates a second clock signal that matches the changed PWM duty ratio and selectively supplies the first clock signal or the second clock signal to the pixel driving circuit.

[0013] Another embodiment of the present disclosure may provide a display driving device including: a pixel driving circuit that is connected to a plurality of LEDs forming at least one row and column and drives the LEDs in a PWM manner; a scan driving circuit that sequentially outputs a first signal to LEDs arranged in a first direction among LEDs connected to the pixel driving circuit; a data driving circuit that outputs a second signal to LEDs arranged in a second direction among LEDs connected to the pixel driving circuit; and the timing controller.

[0014] Another embodiment of the present disclosure provides a method for controlling a display driving device, comprising: receiving a first clock signal corresponding to a first frame period and a second clock signal corresponding to a second frame period consecutive to the first frame period; receiving a first selection signal; a first frame driving step of transmitting the first selection signal to a selection signal shift register corresponding to a first row of a plurality of LEDs, selecting the first clock signal based on the first selection signal, and transmitting the first clock signal to a clock signal shift register connected to the first row; sequentially performing the first frame driving step during the first frame period up to an Nth row of the plurality of LEDs; receiving a second selection signal; a second frame driving step of transmitting the second selection signal to a selection signal shift register corresponding to the first row, selecting the second clock signal based on the second selection signal, and transmitting the second clock signal to a clock signal shift register connected to the first row; And a step of sequentially performing the second frame driving step during the second frame section up to the Nth row; and a method can be provided, characterized in that at least one row in which the first frame driving step and the second frame driving step overlap is operated only by the first clock signal.

[0015] In addition, other methods for implementing the present invention, other systems, and computer-readable recording media storing a computer program for executing the method may be further provided.

[0016] Other aspects, features and advantages other than those described above will become apparent from the following drawings, claims and detailed description of the invention.

[0017] According to the problem solving means of the present disclosure described above, the present disclosure can control the brightness of a display panel in more detail than the conventional technology.

[0018] In addition, according to the problem solving means of the present disclosure, optimal brightness control is possible depending on display quality or power consumption.

[0019] In addition, according to the problem solving means of the present disclosure, it is possible to solve an output error of a shift register that may occur when controlling the brightness of a display panel.

[0020] In addition, according to the problem solving means of the present disclosure, more fine brightness control is possible when controlling the brightness of the display panel.

[0021] The effects of the present invention are not limited to those mentioned above, and other effects not mentioned will be clearly understood by those skilled in the art from the description below.

[0022] Fig. 1 is a driving circuit diagram of a sub-pixel according to a conventional technology.

[0023] FIG. 2 is a block diagram schematically illustrating the configuration of a display driving device according to one embodiment.

[0024] FIG. 3 is a block diagram schematically illustrating the configuration of a display driving device including a timing controller according to one embodiment.

[0025] Fig. 4 is a block diagram schematically illustrating an example of a PWM clock signal output by a timing controller.

[0026] Fig. 5 is a timing diagram showing another example of a PWM clock signal output by a timing controller when a single clock is used.

[0027] Figure 6 is a timing diagram schematically illustrating a problem with a pulse signal output by a timing controller when a single clock is used.

[0028] Figure 7 is a block diagram schematically illustrating the configuration of a timing controller according to one embodiment.

[0029] FIG. 8 is a timing diagram illustrating an example of a timing controller selecting a CLK signal according to one embodiment.

[0030] FIG. 9 is a block diagram schematically illustrating the configuration of a timing controller including a MUX according to one embodiment.

[0031] FIG. 10 is a timing diagram illustrating an example of a PWM clock signal output by a timing controller according to one embodiment.

[0032] FIG. 11 is a flowchart illustrating an example of a method for controlling a display driving device according to one embodiment.

[0033] Figure 12 is a timing diagram schematically illustrating a problem with a PWM clock signal output by a timing controller that does not use a dummy signal.

[0034] FIG. 13 is a timing diagram schematically illustrating a PWM clock signal output by a timing controller according to one embodiment.

[0035] Fig. 14 is a circuit diagram schematically illustrating the configuration of a timing controller according to one embodiment.

[0036] FIG. 15 is a circuit diagram schematically illustrating the configuration of a timing controller that generates a dummy clock signal according to one embodiment.

[0037] FIG. 16 is a flowchart illustrating an example of a method for controlling the brightness of a pixel using a dummy signal according to one embodiment.

[0038] According to one embodiment of the present disclosure, a display driving device includes: a pixel driving circuit that is connected to a plurality of LEDs forming at least one row and column and drives the LEDs in a PWM manner; a control unit that determines a PWM duty ratio (PWM ON Duty) indicating a light-emitting time period of the LED during one frame period; and a timing controller that generates a first clock signal according to the PWM duty ratio and supplies the first clock signal to the pixel driving circuit in units of rows or columns through a shift register; wherein, when the PWM duty ratio is changed, the timing controller generates a second clock signal that matches the changed PWM duty ratio and can selectively supply the first clock signal or the second clock signal to the pixel driving circuit.

[0039] The terms used in the examples are selected from widely used, current terms, as much as possible. However, these terms may vary depending on the intentions of those skilled in the art, precedents, the emergence of new technologies, etc. Furthermore, in certain cases, the applicant may arbitrarily select terms, in which case their meanings will be described in detail in the relevant description. Therefore, the terms used in the specification should be defined based on their intended meaning and the overall content of the specification, rather than simply their names.

[0040] When a part of the specification is said to “include” a certain component, this does not mean that other components are excluded, but rather that other components may be included, unless otherwise specifically stated. Furthermore, terms such as “unit,” “module,” etc., used in the specification refer to a unit that processes at least one function or operation, which may be implemented in hardware, software, or a combination of hardware and software. Furthermore, a “unit” may be a hardware component, such as a processor or circuit, and / or a software component executed by a hardware component, such as a processor.

[0041] Additionally, terms including ordinal numbers, such as “first” or “second,” used in the specification may be used to describe various components, but the components should not be limited by the terms. The terms may be used to distinguish one component from another.

[0042] When one element is referred to as being "connected to" another element, this includes both direct connection to the other element or connection with another element intervening therebetween.

[0043] Below, embodiments are described in detail with reference to the attached drawings. However, the embodiments may be implemented in various different forms and are not limited to the examples described herein.

[0044] FIG. 2 is a block diagram schematically illustrating the configuration of a display driving device according to one embodiment.

[0045] Referring to FIG. 2, a display driving device (101) according to one embodiment may include a display panel (111), a scan driving circuit (130), a data driving circuit (140), and a control unit (150). Meanwhile, a timing controller (not shown) may be included in the control unit (150), but is not limited thereto. For example, the display driving device (101) may include a display panel (111), a scan driving circuit (130), a data driving circuit (140), a control unit (150), and a timing controller (not shown).

[0046] The display panel (111) may include a plurality of pixels (PX). The plurality of pixels (PX) may be arranged in a matrix form in a number of m X n (m, n is a natural number). However, the pattern in which the plurality of pixels are arranged may be arranged in various patterns, such as a zigzag shape, depending on the embodiment.

[0047] The display panel (111) may be implemented as one of an LCD (liquid crystal display), an LED (light emitting diode) display, an OLED (organic LED) display, an AMOLED (active-matrix OLED) display, an ECD (Electrochromic Display), a DMD (Digital Mirror Device), an AMD (Actuated Mirror Device), a GLV (Grating Light Valve), a PDP (Plasma Display Panel), an ELD (Electro Luminescent Display), and a VFD (Vacuum Fluorescent Display), and may also be implemented as another type of flat panel display or flexible display. In this specification, an LED display panel will be described as an example.

[0048] Each pixel (PX) may include one or more light-emitting elements. The light-emitting elements may be light-emitting diodes (LEDs). The light-emitting diodes may be micro LEDs having a size of 80 μm or less. One pixel (PX) may output various colors through multiple light-emitting elements having different colors. For example, one pixel (PX) may include light-emitting elements composed of red, green, and blue. As another example, if a white light-emitting element may be further included, the white light-emitting element may replace any one of the red, green, and blue light-emitting elements. In an embodiment in which multiple light-emitting elements are included in one pixel (PX), each light-emitting element included in one pixel (PX) may be referred to as a 'sub-pixel'.

[0049] Each subpixel can store data related to the brightness of the color to be output during one image frame, i.e., gradation. The size of the gradation-related data may vary, and this specification will describe 10 bits as an example. However, the display driving device (101) according to this specification is not limited to the above example.

[0050] Each pixel (PX) may include a pixel driving circuit that drives a light-emitting element included in the pixel, i.e., a sub-pixel. The pixel driving circuit may drive a turn-on or turn-off operation of the sub-pixel by a signal output from a scan driving circuit (130) and / or a data driving circuit (140). As an example, the pixel driving circuit may include at least one transistor, at least one capacitor, etc. The pixel driving circuit may be implemented on a semiconductor wafer to form a stacked structure with the light-emitting element and be connected thereto, or may be arranged on a side of the light-emitting element and connected thereto, thereby controlling light emission of the light-emitting element.

[0051] Meanwhile, the display panel (111) may include one or more scan lines (SL1 to SLm) arranged in a first direction and one or more data lines (DL1 to DLn) arranged in a second direction. Here, the first direction means a row direction or a column direction, and the second direction means a column direction or a row direction. As an example, the first direction may be a row direction and the second direction may be a column direction. As another example, the first direction may be a column direction and the second direction may be a row direction.

[0052] Meanwhile, a pixel (PX) may be positioned at an intersection of one or more scan lines (SL1 to SLm) and one or more data lines (DL1 to DLn). Each pixel (PX) may be connected to one scan line (SLk) and one data line (DLk). One or more scan lines (SL1 to SLm) may be connected to a scan driving circuit (130), and one or more data lines (DL1 to DLn) may be connected to a data driving circuit (140).

[0053] The scan driving circuit (130) can output a signal (hereinafter, a first signal) that causes one or more pixels connected to one or more scan lines (SL1 to SLm) to be driven. Preferably, the scan driving circuit (130) can sequentially select one or more scan lines (SL1 to SLm). As an example, a pixel connected to a first scan line (SL1) can be driven during a first scan driving period, and a pixel connected to a second scan line (SL2) can be driven during a second scan driving period.

[0054] The data driving circuit (140) can output a signal related to gradation (hereinafter, a second signal) to each pixel through one or more data lines (DL1 to DLn). As an example, as shown in FIG. 2, one data line is connected to one or more pixels in the vertical direction, but a signal related to gradation can be input only to pixels connected to a scan line selected by the scan driving circuit (130).

[0055] The control unit (150) can output a control signal to execute the operations of the scan driving circuit (130) and the data driving circuit (140). The control unit (150) can output a control signal corresponding to image data corresponding to one image frame to the scan driving circuit (130) or the data driving circuit (140). The control unit (150) can determine a PWM duty ratio (PWM ON DUTY) indicating the light-emitting time period of the LED during one frame period.

[0056] Meanwhile, the scan driving circuit (130) and the data driving circuit (140) may include a processor, an application-specific integrated circuit (ASIC), another chipset, a logic circuit, a register, a communication modem, a data processing device, etc. known in the technical field to which the present invention pertains in order to execute various control logics. In addition, when the control logic is implemented in software, the scan driving circuit (130) and the data driving circuit (140) may be implemented as a set of program modules. At this time, the program modules may be stored in a memory device and executed by the processor. As an example, the scan driving circuit (130) may include at least one shift register. Here, the shift register may correspond to any one of the plurality of shift registers (120_1, 120_2, ……, 120_k) of FIG. 3. In addition, the shift register may correspond to the timing controller (120) of FIG. 9 or the timing controller (1120) of FIG. 14, which will be described below.

[0057] A program may include code coded in a computer language, such as C / C++, C#, JAVA, Python, or machine language, that a computer's processor (CPU) can read through the computer's device interface, so that the computer reads the program and executes the methods implemented in the program. Such code may include functional code related to functions that define the necessary functions for executing the methods, and may include control code related to the execution procedure required for the computer's processor to execute the functions according to a predetermined procedure. In addition, such code may further include memory reference-related code regarding which location (address) in the computer's internal or external memory should reference additional information or media required for the computer's processor to execute the functions. In addition, if the computer's processor needs to communicate with any other remote computer or server in order to execute the functions, the code may further include communication-related code regarding how to communicate with any other remote computer or server using the computer's communication module, and what information or media should be sent and received during the communication.

[0058] The storage medium in which a program is stored refers to a medium that stores data semi-permanently and can be read by a device, rather than a medium that stores data for a short period of time, such as a register or cache memory. Specifically, examples of storage media include, but are not limited to, ROM, RAM, CD-ROM, magnetic tape, floppy disks, and optical data storage devices. In other words, a program can be stored on various storage media on various servers accessible by a computer or on various storage media on a user's computer. Furthermore, the storage media can be distributed across network-connected computer systems, allowing computer-readable code to be stored in a distributed manner.

[0059] FIG. 3 is a block diagram schematically illustrating the configuration of a display driving device including a timing controller according to one embodiment.

[0060] Referring to FIG. 3, the display driving device (100) may include a display panel (110) and a plurality of shift registers (120_1, 120_2, ......, 120_k).

[0061] For convenience of explanation, a plurality of shift registers (120_1, 120_2, ……, 120_k) are illustrated in FIG. 3, but the present invention is not limited thereto. In other words, there may be one shift register. Preferably, there may be one shift register or as many shift registers as the number of lines of the display panel, and a PWM clock signal for controlling the PWM driving section of a pixel may be supplied to each line. Hereinafter, a means for generating or supplying a PWM clock signal including a shift register or a plurality of shift registers (120_1, 120_2, …, 120_k) is defined as a timing controller (120). Meanwhile, the timing controller (120) may include at least one of the scan driving circuit (130) or the data driving circuit (140) of FIG. 2.

[0062] Meanwhile, as described above, the scan driving circuit (130) of FIG. 2 may include at least one shift register. That is, the scan driving circuit (130) of FIG. 2 corresponds to a plurality of shift registers (120_1, 120_2, ……, 120_k) of FIG. 3. Although the data driving circuit (140) and the control unit (150) of FIG. 2 are not illustrated in FIG. 3, a person skilled in the art will readily understand that the data driving circuit and the control unit of FIG. 3 may also be configured as in FIG. 2. Accordingly, the display driving device (100) and the display panel (110) correspond to the display driving device (101) and the display panel (111) of FIG. 2. Hereinafter, descriptions of the display driving device (100) and the display panel (110) that overlap with those of FIG. 2 will be omitted.

[0063] As an example, the timing controller (120) can generate a first clock signal according to a PWM duty ratio and supply the first clock signal to the pixel driving circuit in units of rows or columns through a shift register. In addition, when the PWM duty ratio of the timing controller (120) is changed, the timing controller (120) can generate a second clock signal that matches the changed PWM duty ratio and selectively supply the first clock signal or the second clock signal to the pixel driving circuit.

[0064] As another example, the timing controller (120) may generate a first clock signal according to a PWM duty ratio, generate a PWM clock signal based on the first clock signal through a shift register, and supply the PWM clock signal to the pixel driving circuit in units of rows or columns. In addition, when the PWM duty ratio is changed, the timing controller (120) may generate a second clock signal according to the changed PWM duty ratio, select the first clock signal or the second clock signal, generate a PWM clock signal based on the selected clock signal, and supply the PWM clock signal to the pixel driving circuit.

[0065] As another example, the timing controller (120) can generate a first clock signal according to a PWM duty ratio, generate a dummy clock signal based on the first clock signal, and control the brightness of an LED using the first clock signal and the dummy clock signal.

[0066] As another example, the timing controller (120) may generate a dummy clock signal by delaying the first clock signal by a predetermined time interval. Here, the predetermined time interval may refer to the time that the dummy clock signal is delayed with respect to the first clock signal. When the dummy clock signal is generated by delaying the first clock signal by 1H-ΔT, the predetermined time interval may be 1H-ΔT.

[0067] As another example, the timing controller (120) can generate a PWM clock signal based on a clock signal and supply the PWM clock signal to the pixel driving circuit in units of rows or columns.

[0068] As another example, the timing controller (120) may generate a dummy signal based on a dummy clock signal, and the dummy signal may not be supplied to the pixel driving circuit.

[0069] The timing controller (120) can output pulse signals to multiple pixel lines at a constant cycle using pulse signals and dummy signals having a width to control the brightness of the display panel.

[0070] A pixel line refers to an electrical connection through which a PWM clock signal output from a timing controller (120) is input to the pixel. A pixel line may be connected in parallel to all pixels connected to the same row or column. For example, if 'm' is 533, the timing controller (120) may include 533 pixel lines.

[0071] Fig. 4 is a block diagram schematically illustrating an example of a PWM clock signal output by a timing controller.

[0072] Referring to FIG. 4, a timing diagram can be seen in which a PWM clock signal is sequentially output to pixel lines by a timing controller using a single clock. Here, the timing controller may include a shift register. Specifically, the ST signal is a pulse signal for a PWM ON Duty period in which an LED emits light in relation to PWM control. The CLK signal is a signal input to a plurality of flip-flops or MUXs within the timing controller. The PWM clock signal is a signal output to the pixel lines, and is a signal in which the ST signal is output in synchronization with the cycle of the CLK signal.

[0073] Looking at the block diagram of the timing controller (120) of Fig. 4, an ST signal is input to the timing controller (120). At this time, the ST signal is shifted by the CLK signal and sequentially output to each pixel line.

[0074] Looking at the timing diagram shown on the right side of Fig. 4, it can be confirmed that the ST signal is input and sequentially shifted from the first line to the Nth line by the CLK signal, thereby being output as a PWM clock signal to each pixel line. The characteristic of this PWM clock signal is that it is output to the pixel line in the order in which the ST signal is shifted to the CLK signal. Therefore, there is a time difference determined by the CLK signal for each PWM clock signal of each line.

[0075] Fig. 5 is a timing diagram showing another example of a PWM clock signal output by a timing controller when a single clock is used.

[0076] The Hsync signal indicates the timing at which a signal moves for each row within the display. Referring to Fig. 5, for example, assuming that the panel is simply composed of four ROW Lines and the LED is driven with PWM ON Duty 100%, which indicates the maximum brightness of the LED, an ST signal having a length four times the pulse period (1H) included in the Hsync can be generated.

[0077] As an example, the CLK signal is a signal input to the MUX, and the ST signal input to the timing controller can be shifted in response to the CLK signal and output to the pixel line.

[0078] As another example, the CLK signal is a signal input to multiple flip-flops within a shift register, and is formed as a pulse with a period identical to the pulse period within the Hsync signal. Therefore, the ST signal input to the first flip-flop by the CLK signal can be output from the next flip-flop in synchronization with the pulse period of the Hsync signal.

[0079] As another example, the CLK signal is a signal input to multiple flip-flops within a timing controller, and is formed as a pulse with a period identical to the pulse period within the Hsync signal. Therefore, the ST signal input to the first flip-flop by the CLK signal can be synchronized with the pulse period of the Hsync signal and output from the next flip-flop.

[0080] Figure 6 is a timing diagram schematically illustrating a problem with a pulse signal output by a timing controller when a single clock is used.

[0081] Referring to Fig. 6, assuming that the PWM ON Duty is adjusted during the PWM driving time period of the first ST signal, and the second ST signal is changed to drive the LED by adjusting the brightness to, for example, PWM On Duty 75%, a problem that occurs when an 'ST' signal with a changed width is input to a timing controller using a single clock can be confirmed. Specifically, the width of the ST signal can be changed to change the driving, such as the brightness of the display. At this time, if the width of the ST signal is changed, the period of the CLK signal also changes. At this time, the changed period of the CLK signal can affect the entire circuit through the shift register. Therefore, at the point in time when the period of the CLK signal is changed, the pulse signal output to the Nth pixel line by the ST signal before the width of the ST signal is changed is affected by the changed CLK signal, which causes an error in the output, which has a problem.

[0082] In summary, timing controllers using a single clock signal only use a single CLK signal. Therefore, the altered CLK signal, depending on the width of the ST signal, will affect the pulse signal generated by the existing ST signal. This can result in errors such as signal flickering or off.

[0083] Figure 7 is a block diagram schematically illustrating the configuration of a timing controller according to one embodiment.

[0084] Referring to Fig. 7, it can be confirmed that the configuration of the timing controller (120) includes a MUX (124). In Fig. 7, the MUX (124) is illustrated as being included in the timing controller (120), but it may be configured separately without being included in the timing controller (120), and is not limited thereto.

[0085] Meanwhile, although MUX (124) is illustrated as a configuration for selecting a clock signal, it can be implemented by other configurations of the display driving device and is not limited thereto. Accordingly, the operation of MUX (124) described below can be implemented by a timing controller (120), a scan driving circuit (130), a data driving circuit (140), a control unit (150), or more devices, respectively.

[0086] First, the MUX (124) included in the configuration of the timing controller (120) can select one clock signal from among the clock signals of the CLK 1 signal and the CLK 2 signal. Specifically, when an ST signal having a constant width is initially input to the timing controller (120), each PWM clock signal is sequentially output to the pixel line according to the corresponding CLK 1 signal. Then, when an ST signal having a different width from the initial ST signal is input to the timing controller, each PWM clock signal is sequentially output to the pixel line according to the corresponding CLK 2 signal.

[0087] Even if an ST signal with a different width is input to the shift register (121), since a clock signal different from the initial ST signal is used, the CLK signal changed according to the ST signal with a changed width does not affect the pulse signal by the existing ST signal. Therefore, the problem of the CLK signal changed according to the ST signal with a changed width affecting the pulse signal by the existing ST signal by using only one CLK signal like the timing controller of Fig. 6 is solved.

[0088] Meanwhile, the MUX (124) receives multiple clock signals from at least one clock input terminal and selects one clock signal among them. By using the MUX (124), a CLK signal that matches the PWM On Duty ratio applied to each line can be selected, and therefore, even if the light emission time is changed to adjust the brightness of the sub-pixel, the output signal before the change is not affected by the changed clock signal when the clock signal is changed, so that no error occurs.

[0089] As an example, MUX (124) can receive two clock signals from two clock input terminals, and select one clock signal from among them. Specifically, it receives CLK 1 signal and CLK 2 signal from the clock input terminals, and MUX (124) selects one clock signal from among them.

[0090] Meanwhile, MUX (124) can receive multiple clock signals from at least one clock input terminal using a switch and select one clock signal from among them.

[0091] In addition, the timing controller (120) may include at least one flip-flop including an output terminal connected to the pixel driving circuit and at least one MUX (124) for selecting a clock signal input to a clock terminal of at least one flip-flop. As an example, the MUX (124) may receive a plurality of clock signals from at least one clock input terminal, and select one clock signal input to a clock terminal of at least one flip-flop among the plurality of clock signals. As another example, the MUX (124) may select one clock signal input to a clock terminal of at least one flip-flop using a switch.

[0092] FIG. 8 is a timing diagram illustrating an example of a timing controller selecting a CLK signal according to one embodiment.

[0093] Referring to Fig. 8, if the width of the ST signal is determined to drive an LED with, for example, PWM ON Duty 100%, the corresponding clock signal CLK 1 signal is input by shifting by 1H for each ROW line through the timing controller with the period determined to match the width of the ST signal. Afterwards, if the width of the ST signal is changed to drive the LED by adjusting the PWM ON Duty to 75%, the clock period of the corresponding CLK signal is also adjusted, and the clock signal changed to the CLK 2 signal is input through the timing controller. At this time, in order to prevent the pulse signal output to the Nth pixel line by the ST signal for driving with the previous PWM ON Duty 100% from being affected by the signal of the changed CLK 2 signal and causing an error in the output, even if the CLK 2 signal is input, the existing CLK 1 signal is also input through the MUX so that the shift register can select and use the CLK 1 signal or CLK 2 signal appropriate for the corresponding line.

[0094] FIG. 9 is a block diagram schematically illustrating the configuration of a timing controller including a MUX according to one embodiment.

[0095] The timing controller (120) includes a multiplexer (MUX), a selection signal shift register (SEL SHIFT), and a PWM signal shift register (PWM SHIFT). The PWM signal shift register may be a clock signal shift register. In addition, although not shown in FIG. 9, the timing controller (120) may include a clock signal selection unit (not shown). The clock signal selection unit (not shown) outputs a selection signal (SEL signal) that selects one clock signal from among a plurality of clock signals based on driving information of the pixel driving circuit.

[0096] For convenience of explanation, two MUXs (124_1, 124_2) are shown in FIG. 9, but it can be driven by one MUX and is not limited thereto.

[0097] The SEL signal is a signal for selecting one CLK signal among a plurality of CLK signals, and the timing controller (120) can receive the SEL signal or generate the SEL signal and transmit the SEL signal to the MUX through the SEL SHIFT. In addition, the MUX (124_1, 124_2) can select one CLK signal based on the SEL signal received from the SEL SHIFT and transmit the selected CLK signal to the shift register. As an example, the SEL SHIFT can output a selection signal (SEL signal) for selecting a first clock signal (CLK1 signal) or a second clock signal (CLK2 signal) based on driving information of a pixel driving circuit for each pixel line. In addition, the MUX can output the first clock signal or the second clock signal based on the selection signal (SEL signal). The first clock signal and the second clock signal are characterized in that they operate independently of each other with respect to the pixel driving circuit.

[0098] Referring to FIG. 9, SEL SHIFT (121_1, 121_2) refers to a shift register that shifts the SEL signal in response to a clock cycle. A clock signal selection unit (not shown) transmits a selection signal (SEL signal) for selecting a first clock signal or a second clock signal based on driving information of a pixel driving circuit to SEL SHIFT (121_1). The SEL signal is a signal that selects one signal from among the CLK 1 signal and the CLK 2 signal. As an example, by transmitting a signal composed of 0 or 1 to the MUX, when the SEL signal is composed of 1, the MUX can transmit the CLK 1 signal, and when the SEL signal is composed of 0, the MUX can transmit the CLK 2 signal. SEL SHIFT (121_1) receives the SEL signal and the CLK SEL signal. The SEL signal is input to the SEL SHIFT and shifted, thereby being sequentially output for each pixel line unit. PWM SHIFT (122_1, 122_2) refers to a shift register that outputs the ST signal for each pixel line by shifting it in response to the clock cycle. The CLK SEL signal is a clock signal for the SEL signal, and as the ST signal is shifted by the CLK signal in PWM SHIFT (122_1, 122_2), the SEL signal is also shifted by the SEL CLK signal in SEL SHIFT (121_1, 121_2), thereby allowing the same CLK signal to be selected for the same ST signal. The MUX (124_1) receives the SEL signal from the SEL SHIFT (121_1). The MUX (124_1) receives the ST 1 signal and the ST 2 signal, and the CLK 1 signal and the CLK 2 signals for the ST signal (the ST 1 signal and the ST 2 signal). Here, MUX (124_1) selects the CLK 1 signal and ST 1 signal based on the received SEL signal and transmits them to PWM SHIFT (122_1).At this time, MUX (124_1) can use a switch to select a clock signal. For example, MUX (124_1) can transmit CLK 1 signal by receiving SEL signal consisting of 1 and turning on the switch. PWM SHIFT (122_1) shifts ST 1 signal and transmits it to 1st Line. Similarly, MUX (124_2) receives SEL signal and CLK SEL signal from SEL SHIFT (121_2). Here, the SEL signal received by MUX (124_2) is a signal shifted once by SEL SHIFT (121_1). MUX (124_2) receives CLK 1 signal and CLK 2 signal. Then, MUX (124_2) selects CLK 1 signal or CLK 2 signal according to the received SEL signal and transmits it to PWM SHIFT (122_2). Here, MUX (124_2) selects the CLK 1 signal according to the SEL signal and transmits it to PWM SHIFT (122_2). PWM SHIFT (122_2) shifts the ST 1 signal based on the ST 1 signal received from PWM SHIFT (122_1) and the CLK 1 signal received from MUX (124_2) and transmits it to the 2nd Line.

[0099] While the ST 1 signal and the CLK 1 signal are transmitted for each line through the shift register, the SEL SHIFT (121_1) can transmit the SEL signal as a selection signal for selecting the CLK 2 signal to the MUX (124_1). The MUX (124_1) selects the CLK 2 signal as a clock signal and the ST 2 signal as an ST signal according to the received SEL signal and transmits them to the PWM SHIFT (122_1). The PWM SHIFT (122_1) shifts the ST 2 signal and transmits it to the 1st Line. Similarly, the MUX (124_2) receives the SEL signal and the CLK SEL signal from the SEL SHIFT (121_2). Here, the SEL signal may be a signal shifted once by the SEL SHIFT (121_1). The MUX (124_2) receives the CLK 1 signal and the CLK 2 signal. And, MUX (124_2) selects CLK 1 signal or CLK 2 signal according to the received SEL signal and transmits it to PWM SHIFT (122_2). Here, MUX (124_2) selects CLK 2 signal according to SEL signal and transmits it to PWM SHIFT (122_2). PWM SHIFT (122_2) shifts ST 2 signal based on ST 2 signal received from PWM SHIFT (122_1) and CLK 2 signal received from MUX (124_2) and transmits it to 2nd Line.

[0100] Since the SEL signal is shifted for each pixel line through SEL SHIFT and input to the MUX, the ST 2 signal and the CLK 2 signal are not affected by the SEL signal while the ST 1 signal and the CLK 1 signal are shifted for each pixel line through PWM SHIFT. That is, while the ST 1 signal and the CLK 1 signal are sequentially transmitted through the shift register to the first pixel line to the Nth pixel line, even if the ST 2 signal and the CLK 2 signal are transmitted to the first pixel line again through the shift register, the ST 1 signal and the CLK 1 signal that are already being transmitted are not affected by the ST 2 signal and the CLK 2 signal, so no error occurs.

[0101] Therefore, by using multiple clock signals, different clock signals are applied to each changed ST signal, so that the clock signal after the change does not affect the shift register being driven based on the clock signal before the change, and thus no error occurs.

[0102] In Fig. 9, MUX (124_1, 124_2) is illustrated as being included in the timing controller (120), but may be configured individually without being included in the timing controller (120), and is not limited thereto. In addition, MUX (124_1, 124_2) and SEL SHIFT (121_1, 121_2) are illustrated as a configuration for selecting a clock signal, but may be implemented by other configurations of the display driving device, and is not limited thereto.

[0103] The operations of the clock signal selector (not shown), MUX (124_1, 124_2), SEL SHIFT (121_1, 121_2) and PWM SHIFT (122_1, 122_2) described above can be implemented by a single device (e.g., timing controller, clock signal selector, MUX, SEL SHIFT and PWM SHIFT) or can be implemented by more devices.

[0104] Additionally, the timing controller (120) may include a pulse signal input terminal (ST) and a clock input terminal (CLK).

[0105] The pulse signal input terminals (ST 1, ST 2) input a pulse signal for the time for which the LED emits light in relation to PWM control. The pulse signal input terminals (ST 1, ST 2) input a pulse signal corresponding to the brightness of the display panel. Specifically, the pulse signal input terminals (ST 1, ST 2) can input a pulse signal having a width adjusted according to the brightness control of the display panel.

[0106] The clock input terminals (CLK 1, CLK 2) receive multiple clock signals that are input to the MUX (124_1, 124_2) in the timing controller (120). There may be at least one clock input terminal (CLK 1, CLK 2). The clock signal input terminals (CLK 1, CLK 2) may receive multiple clock signals that are input to the clock terminals of the MUX (124_1, 124_2).

[0107] FIG. 10 is a timing diagram illustrating an example of a PWM clock signal output by a timing controller according to one embodiment.

[0108] Referring to FIG. 10, the timing of the 'VSYNC' signal for aligning the synchronization between frames, the image data recording section, the LED light emission section according to the PWM clock signal (PWM1, PWM 2) output by the timing controller, and the SEL signal for selecting the CLK signal according to the PWM On Duty ratio for each VSYNC section can be confirmed.

[0109] For convenience of explanation, an embodiment is provided as an example in which the first PWM duty ratio (PWM ON Duty) is set to correspond to PWM 1 in the first frame period, the second PWM duty ratio is set to correspond to PWM 2 in the second frame period, the first PWM duty ratio is set to correspond to PWM 1 again in the third frame period, and the second PWM duty ratio is set to correspond to PWM 2 again in the fourth frame period.

[0110] Therefore, PWM 1 is a PWM clock signal output by the timing controller based on the ST 1 signal and the CLK 1 signal. PWM 2 is a PWM clock signal output by the timing controller based on the ST 2 signal and the CLK 2 signal. Each of PWM 1 and PWM 2 is expressed as a trapezoid to indicate that it is sequentially output by shifting by 1H from the 1st pixel line to the Nth pixel line in pixel line units.

[0111] In PWM 1, the CLK 1 signal is selected by shifting the SEL signal high from the 1st pixel line to the Nth pixel line. In PWM 2, the CLK 2 signal can be selected by shifting the SEL signal low from the 1st pixel line to the Nth pixel line in synchronization with the VSYNC section. At this time, if the PWM clock signal is being output from the 1st pixel line to the Nth pixel line in PWM 1, even if the CLK 2 signal is selected for the 1st pixel line in PWM 2, the CLK 1 signal of the Nth pixel line is not affected by the CLK 2 signal due to the SEL signal that has already become high. Similarly, in PWM 2, the CLK 2 signal is selected by shifting the SEL signal low from the 1st pixel line to the Nth pixel line. When a PWM clock signal is being output from PWM 2 to the Nth pixel line through the first pixel line, even if the CLK 1 signal is selected from PWM 1 to the first pixel line, the CLK 2 signal of the Nth pixel line is not affected by the CLK 1 signal due to the SEL signal that has already been set low.

[0112] FIG. 11 is a flowchart illustrating an example of a method for controlling a display driving device according to one embodiment.

[0113] Referring to FIG. 11, the timing controller selectively supplies multiple clock signals to the pixel driving circuit. Any details that overlap with those described in FIGS. 2 to 10 regarding the timing controller supplying clock signals to the pixel driving circuit will be omitted.

[0114] At step 1001, the timing controller receives a first clock signal corresponding to a first frame period and a second clock signal corresponding to a second frame period consecutive to the first frame period.

[0115] At step 1002, the timing controller receives a first selection signal. The first selection signal is a selection signal that selects a first clock signal.

[0116] In step 1003, the timing controller transmits a first selection signal to a selection signal shift register corresponding to a first row of a plurality of LEDs, selects a first clock signal based on the first selection signal, and transmits the first clock signal to a clock signal shift register connected to the first row. Step 1003 is referred to as a first frame driving step.

[0117] In step 1004, the timing controller sequentially performs the first frame driving step for the first frame period up to the Nth row of the plurality of LEDs. The selection signal shift register sequentially shifts the first selection signal to the Nth row and transmits the first clock signal to the clock signal shift register based on the sequentially transmitted first selection signal.

[0118] At step 1005, a second selection signal is received. The second selection signal is a selection signal that selects the second clock signal.

[0119] In step 1006, a second selection signal is transmitted to a selection signal shift register corresponding to the first row, a second clock signal is selected based on the second selection signal, and the second clock signal is transmitted to a clock signal shift register connected to the first row. Step 1006 is referred to as a second frame driving step.

[0120] In step 1007, the second frame driving step is sequentially performed during the second frame period up to the Nth row. The selection signal shift register transmits the second selection signal by sequentially shifting it up to the Nth row, and the second clock signal is transmitted to the clock signal shift register based on the second selection signal that is sequentially transmitted. It is characterized in that the row where the first frame driving step and the second frame driving step overlap is operated only by the first clock signal. The first frame driving step is driven based on the first selection signal, and the second frame driving step is driven based on the second selection signal. Even if the first frame driving step and the second frame driving step are driven simultaneously at overlapping times, the first frame driving step is driven based on the first selection signal, and thus is independently driven without being affected by the second clock signal based on the second selection signal. In other words, at least one row in which the first frame driving step and the second frame driving step overlap can be operated by the first clock signal without being affected by the second clock signal based on the first selection signal when the second clock signal is supplied while being driven based on the first clock signal.

[0121] According to one embodiment of the present invention, when a pixel driving circuit is supplied with a second clock signal while being driven based on a first clock signal, the pixel driving circuit is driven by the first clock signal without being affected by the second clock signal based on a first selection signal.

[0122] Figure 12 is a timing diagram schematically illustrating a problem with a PWM clock signal output by a timing controller that does not use a dummy signal.

[0123] Referring to Fig. 12, a problem that occurs when an ST signal is input to a timing controller that does not use a dummy signal can be confirmed. Specifically, by changing the width of the ST signal, the driving changes such as the brightness of the display can be made. The cycle of the CLK signal also changes in response to the change in the ST signal. The changed cycle of the CLK signal is immediately applied to the entire circuit of the timing controller. At this time, since the ST signal is shifted at regular time intervals based on the cycle of the CLK, a problem occurs in that it is not shifted for a fine time interval of ΔT. That is, there is a limit to the control for a fine time interval of ΔT as shown in Fig. 12. When the ST signal is output by shifting it based on the cycle of the CLK signal by a timing controller that does not use a dummy signal, there is a problem in that the control of the display brightness is limited because the control for a fine time interval of ΔT as shown in Fig. 12 is impossible.

[0124] FIG. 13 is a timing diagram schematically illustrating a PWM clock signal output by a timing controller according to one embodiment.

[0125] Referring to Figure 13, it can be confirmed that the PWM clock signal is output with a fine time interval adjustment of ΔT.

[0126] As the ST signal is shifted based on the CLK signal, a PWM clock signal is sequentially output to a plurality of pixel lines. The CLK signal is composed of a first clock signal and a dummy clock signal. The first clock signal has a period (1H) for controlling sequential output to a plurality of pixel lines. The dummy clock signal is generated based on the first clock signal. As an example, the CLK signal is composed of a first clock signal having a period of 1H and a dummy signal delayed by a time interval of 1H-ΔT from the first clock signal. The dummy signal is generated by shifting the ST signal by the first dummy clock signal constituting the CLK signal. The dummy signal generated at this time is not output to the pixel line. In addition, the PWM clock signal is generated by shifting the ST signal once by the first dummy clock signal by the second first clock signal constituting the CLK signal. That is, the ST signal is shifted once by the first clock signal and then shifted once again by the dummy clock signal, thereby generating a PWM clock signal output to the 1st pixel line through a total of two shifts. Here, the PWM clock signal generated by the second shift by the first clock signal is adjusted by the ON-time by the fourth dummy clock signal.

[0127] When generating a dummy clock signal based on the first clock signal, the dummy clock signal can be generated by delaying the first clock signal corresponding to the desired ON-time of the PWM clock signal. The dummy clock signal can be generated corresponding to the desired ON-time without any time interval limitation within the cycle (1H) of the first clock signal. The PWM clock signal adjusted to the desired ON-time is output to the 1st pixel line. According to the present invention, by using the dummy signal, it is possible to adjust the time interval as fine as ΔT for the PWM clock signal. Similarly, in the same process as above, the second dummy signal is generated based on the second dummy clock signal. Then, the PWM clock signal is generated by the third first clock signal, and the generated PWM clock signal is output to the 2nd pixel line. The PWM clock signal output to the 2nd pixel line has its ON-time adjusted by the fifth dummy clock signal.

[0128] As an example, an ST signal is input to a shift register, and the ST signal input to the first sub flip-flop within the shift register is shifted based on a dummy clock signal to generate a dummy signal. At this time, the generated dummy signal is not output to the pixel line. Then, the ST signal that has been shifted once is received by the main flip-flop and shifted based on the first clock signal to generate a PWM clock signal. The specific details are described in Fig. 14.

[0129] The dummy clock signal is generated based on the first clock signal. As an example, the dummy clock signal can be generated by delaying the first clock signal by a predetermined time interval. As another example, the dummy clock signal can be generated by delaying the first clock signal by 1H-ΔT to reduce the ON-time of the PWM clock signal by ΔT.

[0130] The timing controller outputs a single PWM clock signal using two shifts. Specifically, the timing controller does not output a dummy signal generated through a single shift to the pixel line, but instead outputs a PWM clock signal generated through two shifts to the pixel line.

[0131] Meanwhile, the PWM clock signal generated by the first clock signal constituting the CLK signal is output to the pixel line, but the dummy signal generated by the dummy clock signal constituting the CLK signal is not output to the pixel line.

[0132] According to one embodiment of the present invention, by generating a dummy signal and a PWM clock signal based on one clock signal (CLK signal), the brightness of an LED can be finely controlled by controlling the ON-time of the PWM clock signal.

[0133] Fig. 14 is a circuit diagram schematically illustrating the configuration of a timing controller according to one embodiment.

[0134] Referring to FIG. 14, the timing controller (1120) may include m first flip-flops (1121_1, 1121_2, ......, 1121_m) and m second flip-flops (1122_1, 1122_2, ......, 1122_m) respectively connected to the m first flip-flops (1121_1, 1121_2, ......, 1121_m). The m first flip-flops and the m second flip-flops may be connected in series. Accordingly, a signal output from a first flip-flop may be input to a next second flip-flop, and a signal output from a second flip-flop may be input to a next first flip-flop. Through the serial connection of the m first flip-flops and the m second flip-flops, a signal may be sequentially transmitted to the next flip-flop.

[0135] Meanwhile, the first flip-flop receives the signal first. However, unlike the example illustrated in the drawings of this specification, the first signal may be input to the first flip-flop illustrated at the top. That is, the input direction of the signal may be selected according to the designer, and the display driving device (100, 101) according to this specification is not limited by the example illustrated in this specification. As an example, the first flip-flop (1121_1) receives a signal, and generates a dummy signal by shifting the ST signal once. The dummy signal is not output to the pixel line. Then, the ST signal that has been shifted once is input to the second flip-flop (1122_1), and generates a PWM clock signal by shifting it once again. At this time, the generated PWM clock signal is output to the pixel line as the first PWM clock signal.

[0136] Additionally, the timing controller (1120) may include a pulse signal input terminal (ST) and a clock input terminal (CLK). The timing controller may include one shift register (not shown) or multiple shift registers (not shown). Each shift register (not shown) may include a pulse signal input terminal (ST) and a clock input terminal (CLK).

[0137] The pulse signal input terminal (ST) receives a pulse signal for the time at which the LED emits light in relation to PWM control. The pulse signal input terminal (ST) receives a pulse signal corresponding to the brightness of the display panel. Specifically, the pulse signal having a width adjusted according to the brightness control of the display panel can be input to the pulse signal input terminal (ST). The lengths of the pulse signals input to the pulse signal input terminals (ST) of each shift register may be different from each other. More specifically, the lengths of the pulse signals input to the pulse signal input terminals (ST) of adjacent shift registers may have a difference of two times from each other. The shift register corresponding to the most significant bit (MSB) of the grayscale data input to the pixel is referred to as the first shift register, and the shift register corresponding to the next most significant bit is referred to as the second shift register. At this time, the length of the pulse signal input to the pulse signal input terminal (ST) of the first shift register is twice the length of the pulse signal input to the pulse signal input terminal (ST) of the second shift register. For example, if the size of the grayscale data input to the pixel is 10 bits, the length of the pulse signal input to the pulse signal input terminal (ST) of the first shift register may be 512 times the length of the pulse signal input to the pulse signal input terminal (ST) of the 10th shift register corresponding to the least significant bit (LSB).

[0138] A clock signal is input to the clock terminals of m first flip-flops (1121_1, 1121_2, ......, 1121_m) and m second flip-flops (1122_1, 1122_2, ......, 1122_m) through the clock input terminal (CLK). As an example, a clock signal composed of a first clock signal and a dummy clock signal may be input.

[0139] Meanwhile, the timing controller (1120) can generate a first clock signal according to the PWM duty ratio. In addition, the timing controller (1120) can generate a dummy clock signal based on the first clock signal. As an example, the timing controller (1120) can include a clock generation unit (1123). The clock generation unit (1123) can generate a first clock signal according to the PWM duty ratio. In addition, the clock generation unit (1123) can generate a dummy clock signal based on the first clock signal.

[0140] FIG. 15 is a circuit diagram schematically illustrating the configuration of a timing controller that generates a dummy clock signal according to one embodiment.

[0141] The timing controller may include a circuit as shown in FIG. 15. As an example, the timing controller may include a clock generation unit as shown in FIG. 15, but is not limited thereto.

[0142] Referring to FIG. 15, a timing controller receives a CLK signal. The timing controller may include a DLY that generates a dummy clock signal by delaying the received CLK signal by a predetermined time interval. In addition, the timing controller may include an XOR gate or an OR gate that selectively outputs the dummy clock signal and the CLK signal. As an example, the timing controller receives a first clock signal according to a PWM duty ratio. In addition, the timing controller generates a dummy clock signal by delaying the first clock signal by a predetermined period through the DLY. The timing controller sequentially outputs the first clock signal and the dummy clock signal through the XOR gate or the OR gate and through OUT. Therefore, the output clock signal is composed of the first clock signal and the dummy clock signal.

[0143] However, the structure for generating a dummy clock signal of a timing controller such as that shown in FIG. 15 is merely an example and is merely specified to aid understanding of the invention. Therefore, the structure for generating a dummy clock signal according to the present invention is not limited by FIG. 15.

[0144] FIG. 16 is a flowchart illustrating an example of a method for controlling the brightness of a pixel using a dummy signal according to one embodiment.

[0145] Referring to FIG. 16, the timing controller controls the brightness of a pixel by outputting a PWM clock signal to a pixel line using a dummy signal. The overlapping content described in FIGS. 2 to 15 regarding the timing controller generating a first clock signal and a dummy clock signal, generating a PWM clock signal and a dummy signal based on the first clock signal and the dummy clock signal, and supplying the PWM clock signal to the pixel driving circuit will be omitted.

[0146] At step 1601, the timing controller generates a first clock signal based on the PWM duty ratio.

[0147] At step 1602, the timing controller generates a dummy clock signal based on the first clock signal. As an example, the timing controller generates the dummy clock signal by delaying the first clock signal by a predetermined time interval.

[0148] At step 1603, the timing controller generates a PWM clock signal and a dummy signal based on the first clock signal and the dummy clock signal.

[0149] At step 1604, the timing controller supplies a PWM clock signal to the pixel driver circuit. As an example, the timing controller supplies the PWM clock signal to the pixel driver circuit and does not supply a dummy signal to the pixel driver circuit.

[0150] Those skilled in the art will appreciate that the present invention can be implemented in modified forms without departing from the essential characteristics of the above-described invention. Therefore, the disclosed methods should be considered illustrative rather than restrictive. The scope of the claims, not the foregoing description, is defined by the scope of the patent, and should be interpreted to encompass all differences within the scope equivalent thereto.

Claims

1. A pixel driving circuit that is respectively connected to a plurality of LEDs forming at least one row and column and drives the LEDs in a PWM manner; A control unit that determines a PWM duty ratio (PWM ON Duty) representing the light-emitting period of the LED during one frame period; and A timing controller is included that generates a first clock signal according to the PWM duty ratio and supplies the first clock signal to the pixel driving circuit in units of rows or columns through a shift register; A display driving device, characterized in that the timing controller generates a second clock signal suitable for the changed PWM duty ratio when the PWM duty ratio is changed, and selectively supplies the first clock signal or the second clock signal to the pixel driving circuit.

2. In paragraph 1, The above timing controller, Generating a first clock signal according to the PWM duty ratio, generating a PWM clock signal based on the first clock signal through a shift register, and supplying the PWM clock signal to the pixel driving circuit in units of rows or columns, A display driving device characterized in that, when the PWM duty ratio is changed, a second clock signal suitable for the changed PWM duty ratio is generated, the first clock signal or the second clock signal is selected, a PWM clock signal is generated based on the selected clock signal, and the PWM clock signal is supplied to the pixel driving circuit.

3. In paragraph 1, The above timing controller, Generating a first selection signal for selecting the first clock signal and a second selection signal for selecting the second clock signal, and selectively supplying the first clock signal and the second clock signal to the pixel driving circuit based on the first selection signal and the second selection signal, The above first clock signal and the above second clock signal, A display driving device characterized in that the pixel driving circuits above operate independently of each other.

4. In paragraph 1, The above timing controller, At least one flip-flop including an output terminal connected to the pixel driving circuit; and A display driving device, comprising at least one MUX for selecting a clock signal input to a clock terminal of at least one flip-flop.

5. In paragraph 4, The above timing controller, A pulse signal input terminal into which a pulse signal corresponding to the brightness of the LED is input; and A display driving device further comprising: at least one clock input terminal to which a plurality of clock signals are input.

6. In paragraph 5, The above MUX is, A display driving device that receives the plurality of clock signals from at least one clock input terminal and selects one clock signal input to the clock terminal of at least one flip-flop among the plurality of clock signals.

7. In paragraph 6, The above MUX is, A display driving device that selects one clock signal input to a clock terminal of at least one flip-flop using a switch.

8. In paragraph 1, The above timing controller, A clock signal selection unit that outputs a selection signal for selecting a first clock signal or a second clock signal based on the driving information of the pixel driving circuit; and A display driving device, comprising: a MUX that outputs a first clock signal or a second clock signal based on a selection signal output from the clock signal selection unit.

9. A pixel driving circuit that is respectively connected to a plurality of LEDs forming at least one row and column and drives the LEDs in a PWM manner; A scan driving circuit that sequentially outputs a first signal to LEDs arranged in a first direction among LEDs connected to the above pixel driving circuit; A data driving circuit that outputs a second signal to LEDs arranged in a second direction among the LEDs connected to the pixel driving circuit; and A display driving device comprising a timing controller according to any one of claims 1 to 8.

10. A method for controlling a display driving device, A step of receiving a first clock signal corresponding to a first frame section and a second clock signal corresponding to a second frame section consecutive to the first frame section; A step of receiving a first selection signal; A first frame driving step of transmitting the first selection signal to a selection signal shift register corresponding to a first row of a plurality of LEDs, selecting the first clock signal based on the first selection signal, and transmitting the first clock signal to a clock signal shift register connected to the first row; A step of sequentially performing the first frame driving step during the first frame section up to the Nth row of the plurality of LEDs; A step of receiving a second selection signal; A second frame driving step of transmitting the second selection signal to a selection signal shift register corresponding to the first row, selecting the second clock signal based on the second selection signal, and transmitting the second clock signal to a clock signal shift register connected to the first row; and A step of sequentially performing the second frame driving step during the second frame section up to the Nth row; A method, characterized in that at least one row in which the first frame driving step and the second frame driving step overlap is operated only by the first clock signal.

Images