Amplifier circuit, memory circuit, and electronic device

Abstract

The present invention provides an amplifier circuit that writes to, or reads from, a memory cell with reduced power consumption. The amplifier circuit includes first to sixth switches and a sense amplifier. The sense amplifier is of the latch type and has a first input / output terminal and a second input / output terminal. A first terminal of the first switch is electrically connected to a first terminal of the second switch, and a second terminal of the second switch is electrically connected to a first terminal of the third switch and the first input / output terminal of the sense amplifier. A first terminal of the fourth switch is electrically connected to a first terminal of the fifth switch, and a second terminal of the fifth switch is electrically connected to a first terminal of the sixth switch and the second input / output terminal of the sense amplifier. Each of a control terminal of the first switch and a control terminal of the fifth switch is electrically connected to first wiring, and each of a control terminal of the third switch and a control terminal of the sixth switch is electrically connected to second wiring.

Description

Amplification circuit, memory circuit and electronic device

[0001] One embodiment of the present invention relates to an amplifier circuit, a memory circuit, and an electronic device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. The technical field of the invention disclosed in this specification and the like relates to an object, an operating method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, manufacture, or a composition of matter. Therefore, specific examples of the technical field of one embodiment of the present invention disclosed in this specification include semiconductor devices, display devices (including liquid crystal display devices), light-emitting devices, power storage devices, imaging devices, memory devices, processing devices, signal processing devices, sensors, arithmetic devices (including processors), electronic devices, systems, driving methods thereof, manufacturing methods thereof, and inspection methods thereof.

[0003] In recent years, with the increase in the amount of data handled, there has been a demand for memory devices with larger storage capacities. In order to increase the storage capacity per unit area, it is effective to have a configuration in which multiple memory cells are stacked above a drive circuit (Patent Document 1). By stacking the memory cells, the storage capacity per unit area can be increased according to the number of stacked memory cells (sometimes referred to as memory cells in this specification).

[0004] Furthermore, increasing the number of memory cells in the same layer can also increase the storage capacity of a storage device. However, increasing the number of memory cells may also increase the risk of reading incorrect data. For example, in a gain cell type memory cell, the greater the number of unselected memory cells, the greater the leakage current flowing from those memory cells to the read bit line, which may cause the potential of the read bit line to deviate from the correct potential. Patent Document 2 discloses a configuration in which a circuit for canceling leakage current is provided in a column circuit (referred to herein as an amplifier circuit, write circuit, read circuit, etc.) to correct the potential of the read bit line to the correct potential.

[0005] An example of a storage device is a cache memory included in a CPU (Central Processing Unit). For example, Non-Patent Document 1 describes, as a CPU cache memory, a static random access memory (SRAM) that uses transistors using indium gallium zinc oxide, which is an oxide semiconductor.

[0006] International Publication No. WO 2022 / 238798 International Publication No. WO 2018 / 73708

[0007] S. Yamazaki and M. Fujita, “Physics and Technology of Crystalline Oxide Semiconductor CAAC-IGZO: Application to LSI”, (USA), Wiley-SID Series in Display Technology, 2016, pp. 181-192

[0008] As described in Patent Document 2, a column circuit including an amplifier such as a sense amplifier is required for writing data to a gain cell type memory cell and reading data from the memory cell. The column circuit is connected to wiring for applying a precharge potential, wiring for applying a potential that serves as a comparison potential (sometimes referred to as a reference potential), wiring for applying a power supply potential to the sense amplifier, and the like.

[0009] The column circuit is provided with a plurality of switches, and by controlling the on / off state of each switch, the column circuit can obtain each potential provided by the above-mentioned wiring. Note that, depending on the on / off state of each switch, a through current may occur between the above-mentioned wirings, which may cause an increase in power consumption of the amplifier circuit.

[0010] For example, if a wiring for applying a high power supply potential is connected to the high power supply potential input terminal of the above-mentioned sense amplifier and a wiring for applying a low power supply potential is connected to the low power supply potential input terminal, when the sense amplifier is in an active state, one of the two input / output terminals of the sense amplifier will be in a conductive state with the wiring for applying the low power supply potential, and the other of the two input / output terminals of the sense amplifier will be in a conductive state with the wiring for applying the high power supply potential. At this time, if one of the two input / output terminals of the sense amplifier is in a conductive state with the wiring for applying a precharge potential or the like, a through current may occur between the wiring for applying the low power supply potential and the wiring for applying the precharge potential or the like. The occurrence of this through current may increase the power consumption of the amplifier circuit.

[0011] Furthermore, since the sense amplifier amplifies the potentials of the two input / output terminals to high and low levels, it is preferable to make the parasitic capacitances of the two input / output terminals as close to each other as possible in order to perform sensing correctly. Furthermore, it is preferable to reduce the value of the parasitic capacitance in order to speed up the operation of the sense amplifier.

[0012] According to Patent Document 2, the column circuit includes a logic circuit that functions as a switch between one of the two input / output terminals of the sense amplifier and the memory cell. When different circuit elements are connected to the two input / output terminals of the sense amplifier, a difference in the parasitic capacitances of the two input / output terminals of the sense amplifier occurs, which can result in incorrect data being read from the memory cell and incorrect sensing. Similarly, data being written to the memory cell can also be incorrectly sensed and incorrect data being written.

[0013] In addition, in a gain cell type memory cell, in order to prevent deterioration of the stored data, the potential of the node provided in the memory cell that stores the data is refreshed at an appropriate timing. By performing the refresh operation more frequently, the data in the memory cell can be stored for a longer period of time, but the more frequently the refresh operation is performed, the greater the power consumption.

[0014] An object of one embodiment of the present invention is to provide an amplifier circuit with reduced power consumption. Another object of one embodiment of the present invention is to provide an amplifier circuit capable of writing data to or reading data from a memory cell. Another object of one embodiment of the present invention is to provide an amplifier circuit in which a through current is unlikely to occur or can be extremely reduced between a wiring that supplies a high power supply potential and a wiring that supplies a low power supply potential. Another object of one embodiment of the present invention is to provide an amplifier circuit that correctly senses data during reading or writing. Another object of one embodiment of the present invention is to provide a memory circuit including the above amplifier circuit. Another object of one embodiment of the present invention is to provide an electronic device including the above memory circuit. Another object of one embodiment of the present invention is to provide a novel amplifier circuit, a novel memory circuit, or a novel electronic device.

[0015] Note that the problem of one embodiment of the present invention is not limited to the above problem. The above problem does not preclude the existence of other problems. Note that the other problems are problems not mentioned in this section, which will be described below. Problems not mentioned in this section can be derived by a person skilled in the art from the description in the specification or drawings, and can be appropriately extracted from these descriptions. Note that one embodiment of the present invention solves at least one of the above problem and other problems, and does not necessarily solve all of the above problem and other problems.

[0016] In view of the above, one embodiment of the present invention provides an amplifier circuit including a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch, and a sense amplifier. In particular, the sense amplifier is a latch type and has a function of amplifying the potential of one of the first input / output terminal or the second input / output terminal to a high-level potential and amplifying the potential of the other of the first input / output terminal or the second input / output terminal to a low-level potential, depending on the potentials of the first input / output terminal and the second input / output terminal, respectively.

[0017] In the amplifier circuit, a write bit line is connected to a first input / output terminal of the sense amplifier via a second switch, and a read bit line is connected to a second input / output terminal of the sense amplifier via a fifth switch. Note that a gain cell type memory cell, to which data is written or read by the amplifier circuit, is connected to the write bit line and the read bit line.

[0018] A wiring for applying a first potential is connected to the write bit line via a first switch, and a wiring for applying a second potential is connected to the read bit line via a fourth switch.

[0019] A first data line is connected to a first input / output terminal of the sense amplifier via a third switch, and a second data line is connected to a second input / output terminal of the sense amplifier via a sixth switch. The first and second data lines are paired wires that input and output complementary data, such as data to be written or data read from a memory cell.

[0020] As described above, the amplifier circuit of one embodiment of the present invention uses a latch-type sense amplifier and controls the on and off states of each switch to amplify a potential corresponding to data written to a gain cell-type memory cell, amplify a potential corresponding to data read from a gain cell-type memory cell, or rewrite (sometimes referred to as write-back or refresh) a potential held in a gain cell-type memory cell.

[0021] Below, examples of an amplifier circuit, a memory circuit, and an electronic device for solving the above problems will be described.

[0022] (1) One aspect of the present invention is an amplifier circuit including a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch, and a sense amplifier, wherein the sense amplifier has a first input / output terminal and a second input / output terminal.

[0023] The first terminal of the first switch is electrically connected to the first terminal of the second switch, the second terminal of the second switch is electrically connected to the first terminal of the third switch and the first input / output terminal of the sense amplifier, the first terminal of the fourth switch is electrically connected to the first terminal of the fifth switch, and the second terminal of the fifth switch is electrically connected to the first terminal of the sixth switch and the second input / output terminal of the sense amplifier. The control terminals of the first switch and the fifth switch are each electrically connected to the first wiring, and the control terminals of the third switch and the sixth switch are each electrically connected to the second wiring.

[0024] The sense amplifier is a latch type and has the function of amplifying the potential of one of the first input / output terminal or the second input / output terminal to a high-level potential, and amplifying the potential of the other of the first input / output terminal or the second input / output terminal to a low-level potential, depending on the respective potentials of the first input / output terminal and the second input / output terminal.

[0025] (2) Alternatively, according to one aspect of the present invention, in the circuit of (1), the first switch, the second switch, and the fifth switch may each be an analog switch, the third switch may include a first transistor, the fourth switch may include a second transistor, and the sixth switch may include a third transistor. One of a source or a drain of the first transistor corresponds to a first terminal of the third switch, and a gate of the first transistor corresponds to a control terminal of the third switch. One of a source or a drain of the second transistor corresponds to a first terminal of the fourth switch, and a gate of the second transistor corresponds to a control terminal of the fourth switch. One of a source or a drain of the third transistor corresponds to a first terminal of the sixth switch, and a gate of the third transistor corresponds to a control terminal of the sixth switch.

[0026] (3) Alternatively, according to one embodiment of the present invention, in the above-described (2), the first transistor and the third transistor can be n-channel transistors, and the second transistor can be a p-channel transistor.

[0027] In particular, each of the first to third transistors preferably has silicon in a channel formation region.

[0028] (4) Another embodiment of the present invention is a memory circuit including the amplifier circuit according to any one of (1) to (3) above and a memory cell, wherein the memory cell includes a fourth transistor, a fifth transistor, and a capacitor.

[0029] The first terminal of the first switch and the first terminal of the second switch are each electrically connected to the third wiring, the first terminal of the fourth switch and the first terminal of the fifth switch are each electrically connected to the fourth wiring, one of the source and the drain of the fourth transistor is electrically connected to the gate of the fifth transistor and the first terminal of the capacitance element, the other of the source and the drain of the fourth transistor is electrically connected to the third wiring, and one of the source and the drain of the fifth transistor is electrically connected to the fourth wiring.

[0030] (5) Alternatively, according to one embodiment of the present invention, in the above-described (4), each of the fourth transistor and the fifth transistor can include an oxide semiconductor in a channel formation region.

[0031] The oxide semiconductor contains one or more elements selected from indium, zinc, and an element M. The element M is one or more elements selected from aluminum, gallium, silicon, yttrium, tin, copper, vanadium, chromium, manganese, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, calcium, strontium, barium, cobalt, and antimony.

[0032] (6) Another embodiment of the present invention is an electronic device including the memory circuit described in (5) above and a housing.

[0033] The amplifier circuit of one embodiment of the present invention has the structure described in any one of (1) to (3) above, and can perform an operation method in which a through current is unlikely to occur or can be extremely small between a wiring that supplies a high power supply potential and a wiring that supplies a low power supply potential when writing data to a gain cell-type memory cell or reading data from the gain cell-type memory cell, thereby reducing the power consumption of the amplifier circuit.

[0034] Furthermore, the above-described operation method allows a data rewrite operation to be performed when reading data from a gain cell type memory cell. That is, since a rewrite operation can be performed simultaneously with a read operation, the number of times data is refreshed in the memory cell can be reduced. By reducing the number of times refresh is performed, the power consumption of the amplifier circuit can be reduced.

[0035] According to one embodiment of the present invention, an amplifier circuit with reduced power consumption can be provided. Alternatively, according to one embodiment of the present invention, an amplifier circuit capable of writing data to or reading data from a memory cell can be provided. Alternatively, according to one embodiment of the present invention, an amplifier circuit in which a through current is unlikely to occur or can be extremely reduced between a wiring that supplies a high power supply potential and a wiring that supplies a low power supply potential can be provided. Alternatively, according to one embodiment of the present invention, an amplifier circuit that correctly senses data during reading or writing can be provided. Alternatively, according to one embodiment of the present invention, a memory circuit including the above amplifier circuit can be provided. Alternatively, according to one embodiment of the present invention, an electronic device including the above memory circuit can be provided. Alternatively, according to one embodiment of the present invention, a novel amplifier circuit, a novel memory circuit, or a novel electronic device can be provided.

[0036] Note that the effects of one embodiment of the present invention are not limited to the above-described effects. The above-described effects do not preclude the existence of other effects. Furthermore, the other effects are effects not mentioned in this section, which will be described below. Effects not mentioned in this section can be derived by a person skilled in the art from the description in the specification or drawings, and can be extracted as appropriate from these descriptions. Note that one embodiment of the present invention has at least one of the above-described effects and other effects. Therefore, one embodiment of the present invention may not have the effects listed above in some cases.

[0037] FIG. 1 is a circuit diagram showing an example of an amplifier circuit. FIG. 2 is a circuit diagram showing an example of an amplifier circuit. FIG. 3 is a circuit diagram showing an example of an amplifier circuit. FIG. 4 is a circuit diagram showing an example of a memory cell and an amplifier circuit. FIGS. 5A and 5B are circuit diagrams showing an example of a memory cell and an amplifier circuit. FIG. 6 is a timing chart showing an example of operation of a memory cell and an amplifier circuit. FIG. 7 is a timing chart showing an example of operation of a memory cell and an amplifier circuit. FIG. 8 is a timing chart showing an example of operation of a memory cell and an amplifier circuit. FIG. 9 is a timing chart showing an example of operation of a memory cell and an amplifier circuit. FIG. 10A is a perspective view illustrating an example of a configuration of a memory circuit, and FIG. 10B is a block diagram illustrating an example of a configuration of a memory circuit. FIG. 11 is a block diagram showing an example of a configuration of a memory circuit. FIG. 12 is a schematic cross-sectional view showing an example of a configuration of a memory circuit. FIGS. 13A and 13B are schematic perspective views showing an example of a configuration of a transistor. FIG. 14A is a schematic plan view showing an example of a configuration of a transistor, and FIGS. 14B to 14D are schematic cross-sectional views showing example of configurations of transistors. 15A to 15C are cross-sectional schematic diagrams showing an example of the configuration of a transistor. FIG. 16A is a plan view showing an example of the configuration of a transistor, and FIGS. 16B to 16D are cross-sectional schematic diagrams showing an example of the configuration of a transistor. FIGS. 17A and 17B are perspective views showing an example of the configuration of a transistor. FIG. 18 is a cross-sectional schematic diagram showing an example of the configuration of a memory circuit. FIG. 19A is a plan view showing an example of the configuration of a transistor, and FIG. 19B is a cross-sectional schematic diagram showing an example of the configuration of a transistor. FIG. 20 is a cross-sectional schematic diagram showing an example of the configuration of a memory circuit. FIG. 21 is a perspective view showing an example of the configuration of a processing device. FIGS. 22A and 22B are views showing various memory devices by layer. FIGS. 23A to 23D are views showing an example of electronic components. FIGS. 24A and 24B are views showing an example of electronic equipment, and FIG. 24C is a view showing an example of a mainframe computer. FIG. 25 is a view showing an example of space equipment. FIG. 26 is a view showing an example of a storage system applicable to a data center. 27A1 to 27A7 and 27B1 to 27B6 are circuit diagrams for explaining electrical connections.

[0038] (Additional Notes Related to the Present Specification) In the present specification and the like, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (for example, a transistor, a diode, and a photodiode), or a device having such a circuit. A semiconductor device also refers to any device that can function by utilizing semiconductor characteristics. An example of a semiconductor device is an integrated circuit. Another example of a semiconductor device is a chip equipped with an integrated circuit, and another example of a semiconductor device is an electronic component that houses a chip in a package. For example, a memory device, a display device, a light-emitting device, a lighting device, and an electronic device may themselves be a semiconductor device, or may include a semiconductor device.

[0039] In this specification, "connection" includes, for example, "electrical connection."

[0040] When expressing "electrical connection" to define the connection relationship between circuit elements as a physical entity, "electrical connection" includes, for example, "direct connection" and "indirect connection." "A and B are directly connected" refers to a case where A and B are connected without a circuit element (e.g., a transistor or a switch; wiring is not considered a circuit element). On the other hand, "A and B are indirectly connected" refers to a case where A and B are connected via one or more circuit elements.

[0041] Here, when "A and B are indirectly connected," it refers to the following connection relationship, for example. That is, assuming that a circuit is operating, if there is a time during the operation of the circuit when electrical signal transmission or potential interaction occurs between A and B, such a circuit can be defined as an entity, and "A and B are indirectly connected." Note that even if there is a time when electrical signal transmission or potential interaction does not occur between A and B, if there is a time during the operation of the circuit when electrical signal transmission or potential interaction occurs between A and B, it can be defined as "A and B are indirectly connected." Note that "A and B are indirectly connected" is a definition of the connection relationship between circuit elements as an entity. Therefore, for example, even when a power supply voltage is not supplied to a circuit and the circuit is not operating, the circuit can be defined as an entity, and "A and B are indirectly connected" (however, for example, this is limited to the case where electrical signal transmission or potential interaction occurs between A and B during the operation of the circuit when a power supply voltage is supplied to the circuit and the circuit is operating).

[0042] Specific examples of "indirect connection" are shown below. First, an example of "A and B are indirectly connected" is when A and B are connected via the source and drain of one or more transistors, as shown in FIGS. 27A1 and 27A2. Another example of "A and B are indirectly connected" is when A and B are connected via one or more switches. When "A and B are indirectly connected," it is assumed that, assuming the circuit is operating, there is at least one time when a transistor between A and B is in an on state, a conductive state, or a state in which a current can flow. Note that "A and B are indirectly connected" also includes cases where a transistor between A and B is in an off state or a non-conductive state. When "A and B are indirectly connected," if multiple transistors are connected between A and B, it is assumed that, assuming the circuit is operating, each of the multiple transistors between A and B is in an on state, a conductive state, or a state in which a current can flow at least one time. In other words, when "A and B are indirectly connected," it is not necessary for all of the multiple transistors to be in an on state, a conductive state, or a state in which current can flow simultaneously. Therefore, when "A and B are indirectly connected," it also includes cases in which the multiple transistors between A and B are in an off state or a non-conductive state at the same time or at different times. As another example, as shown in FIG. 27A3, when A and C are connected via the source and drain of transistor TrP and B and C are connected via the source and drain of transistor TrQ, it can be defined as "A and C are indirectly connected," "B and C are indirectly connected," or "A and B are indirectly connected." However, as will be described later, when a constant potential V is supplied to C from a power supply, GND, or the like, it can be said that "A and C are indirectly connected" or "B and C are indirectly connected," but it cannot be said that "A and B are indirectly connected."

[0043] While we have provided examples of cases where an "indirect connection" can and cannot be established, we will now present another example of a case where an "indirect connection" cannot be established. Even if an electrical signal exchange or potential interaction occurs between A and B during the operation of the circuit, there are exceptional cases where it cannot be said that "A and B are indirectly connected." An example of such an exceptional case is when A and B are connected via an insulator. In other words, when A and B are connected via an insulator, it cannot be said that "A and B are indirectly connected." A specific example of a case where A and B are connected via an insulator is when a capacitive element is connected between A and B, as shown in FIG. 27A4. Another example of a case where A and B are connected via an insulator is when a gate insulating film of a transistor is interposed between A and B, as shown in FIG. 27A5. In this case, it cannot be said that "A (the gate of the transistor) and B (the source or drain of the transistor) are indirectly connected."

[0044] Another example of a case where it cannot be said that "A and B are indirectly connected" is a case where there is no timing when an electrical signal is exchanged or when potential interaction occurs between A and B. An example of this is when, as shown in Figures 27A6 and 27A7, multiple transistors are connected via their sources and drains to the path from A to B, and a constant potential V is supplied to a node between the transistors from a power supply, GND, or the like. In this case, it cannot be said that "A and B are indirectly connected," but it is possible to say that "A and V are indirectly connected" or "B and V are indirectly connected." In addition, in Figure 27A3, if A and C are connected via the source and drain of transistor TrP, and B and C are connected via the source and drain of transistor TrQ, and a constant potential V is supplied to C from a power supply or GND, etc., the relationship will be the same as in Figures 27A6 and 27A7, so it cannot be said that "A and B are indirectly connected," but it can be said that "A and C are indirectly connected," or "B and C are indirectly connected."

[0045] Although an example of "indirect connection" has been given above, as an example, the definition of "indirect connection" is included in the definition of "electrical connection," so if "A and B are indirectly connected," it can also be said that "A and B are electrically connected."

[0046] Next, specific examples of "direct connection" are shown. Examples of "A and B are directly connected" include cases where A and B are connected without any circuit elements between them, as shown in FIGS. 27B1, 27B2, and 27B3. When A and B are connected to a power supply that supplies a constant potential V or to GND without any circuit elements between them, as shown in FIGS. 27B4 and 27B5, it can be said that "A and B are directly connected," "A and V are directly connected," or "B and V are directly connected." It can also be said that "A and B are directly connected," when A (or B) is connected to a constant potential V via the source and drain of a transistor, as shown in FIG. 27B6. Because A and V or B and V are connected via the source and drain of a transistor, they cannot be said to be directly connected, but rather that "A and V are indirectly connected" or "B and V are indirectly connected."

[0047] Although an example of "direct connection" has been given above, as an example, the definition of "direct connection" is included in the definition of "electrical connection," so when "A and B are directly connected," it can also be said that "A and B are electrically connected."

[0048] In addition, in this specification, the expression "multiple circuit elements connected in series" includes the case where multiple circuit elements are connected in series by connecting the terminals of two adjacent circuit elements. This connection also includes "electrical connection."

[0049] Note that even when independent components are shown as being connected to each other in a circuit diagram, one component may have the functions of multiple components. For example, if part of a wiring also functions as an electrode, one conductive film has the functions of both a wiring and an electrode. Therefore, in this specification, the term "connection" also includes such cases where one conductive film has the functions of multiple components.

[0050] Furthermore, in this specification, a "resistance element" can be, for example, a circuit element having a resistance value higher than 0Ω, or a wiring having a resistance value higher than 0Ω. Therefore, in this specification, a "resistance element" includes a wiring having a resistance value, a transistor in which a current flows between a source and a drain, a diode, or a coil. Therefore, the term "resistance element" can sometimes be replaced with the terms "resistance," "load," or "region having a resistance value." Conversely, the terms "resistance," "load," or "region having a resistance value" can sometimes be replaced with the term "resistance element." The resistance value can be, for example, preferably 1 mΩ or more and 10 Ω or less, more preferably 5 mΩ or more and 5 Ω or less, and even more preferably 10 mΩ or more and 1 Ω or less. Furthermore, for example, a resistance value can be, for example, 1 Ω or more and 1×10 ９ It can be made smaller than Ω.

[0051] Furthermore, in this specification, a "capacitive element" can refer to, for example, a circuit element having a capacitance value higher than 0 F, a wiring region having a capacitance value higher than 0 F, a parasitic capacitance, or a gate capacitance of a transistor. The terms "capacitive element," "parasitic capacitance," or "gate capacitance" can sometimes be replaced with the term "capacitance." Conversely, the term "capacitance" can sometimes be replaced with the terms "capacitive element," "parasitic capacitance," or "gate capacitance." A "capacitive element" (including a "capacitive element" with three or more terminals) includes an insulator and a pair of conductors sandwiching the insulator. Therefore, the term "pair of conductors" in "capacitance" can be replaced with "pair of electrodes," "pair of conductive regions," "pair of regions," or "pair of terminals." The terms "one of the pair of terminals" and "the other of the pair of terminals" may be referred to as a first terminal and a second terminal, respectively. The capacitance value can be, for example, 0.05 fF to 10 pF. It can also be, for example, 1 pF to 10 μF.

[0052] In this specification, a switch refers to a device that can be turned on or off and has the function of controlling whether or not a current flows, or a device that has the function of selecting and switching a path through which a current flows.

[0053] In this specification, a "conductive state" refers to a state in which a current can flow between two input / output terminals, and a "non-conductive state" refers to a state in which the two input / output terminals are considered to be electrically disconnected. In this specification, the on state of a switch falls under the category of a "conductive state," and the off state of a switch falls under the category of a "non-conductive state." Therefore, in this specification, the "conductive state" and the "on state" of a switch are interchangeable, and the "non-conductive state" and the "off state" are interchangeable.

[0054] Furthermore, the switch may have two or more terminals for passing current in addition to the control terminal. For example, an electrical switch, a mechanical switch, or the like may be used. In other words, the switch is not limited to a specific type as long as it has the function of controlling current.

[0055] Examples of electrical switches include transistors (e.g., bipolar transistors, MOS transistors, etc.), diodes (e.g., PN diodes, PIN diodes, Schottky diodes, MIM (Metal Insulator Metal) diodes, MIS (Metal Insulator Semiconductor) diodes, and diode-connected transistors), or logic circuits combining these. When a transistor is used as a switch, the "conductive state" or "on state" of the transistor refers to a state in which a current can flow between the source electrode and the drain electrode of the transistor. The "non-conductive state" or "off state" of the transistor refers to a state in which the source electrode and the drain electrode of the transistor can be considered to be electrically disconnected. When a transistor is operated simply as a switch, the polarity (conductivity type) of the transistor is not particularly limited.

[0056] An example of a mechanical switch is a switch that uses MEMS (microelectromechanical systems) technology. This switch has a mechanically movable electrode, and the movement of the electrode controls the conductive and non-conductive states.

[0057] In this specification, a transistor has three terminals called a gate, a source, and a drain. The gate is a control terminal that controls switching between a conductive state and a non-conductive state of the transistor. The two terminals that function as a source or a drain are input / output terminals of the transistor. One of the two input / output terminals serves as a source and the other as a drain depending on the conductivity type (n-channel or p-channel) of the transistor and the level of the potential applied to the three terminals of the transistor. Therefore, in this specification, the terms "source" and "drain" may be interchangeable. In addition, in this specification, when describing the connection relationship of a transistor, the terms "one of the source and the drain" and "the other of the source and the drain" are used. In this specification, one of the source and the drain may be referred to as a "first electrode of the transistor" or a "first terminal of the transistor," and the other of the source and the drain may be referred to as a "second electrode of the transistor" or a "second terminal of the transistor." Note that, depending on the structure of a transistor, a backgate may be provided in addition to the three terminals described above. In this case, in this specification, one of the gate or back gate of the transistor may be referred to as a first gate, and the other of the gate or back gate of the transistor may be referred to as a second gate. Furthermore, for the same transistor, the terms "gate" and "back gate" may be interchangeable. Furthermore, when a transistor has three or more gates, in this specification, the respective gates may be referred to as a first gate, a second gate, a third gate, etc.

[0058] For example, in this specification, a transistor having a multi-gate structure with two or more gate electrodes can be used as an example of a transistor. With a multi-gate structure, the channel formation regions are connected in series, resulting in a structure in which multiple transistors are connected in series. Therefore, the multi-gate structure can reduce the off-state current and improve the breakdown voltage (reliability) of the transistor. Alternatively, when operating in the saturation region, the multi-gate structure can provide voltage-current characteristics with a flat slope, such that the current between the drain and source does not change significantly even when the voltage between the drain and source changes. By utilizing voltage-current characteristics with a flat slope, an ideal current source circuit or an active load with a very high resistance value can be realized. As a result, a differential circuit or a current mirror circuit with excellent characteristics can be realized.

[0059] Furthermore, even when a single circuit element is shown on a circuit diagram, the circuit element may include multiple circuit elements. For example, when a circuit diagram shows one resistor, this includes two or more resistors connected in series. For example, when a circuit diagram shows one capacitance element, this includes two or more capacitance elements connected in parallel. For example, when a circuit diagram shows one transistor, this includes two or more transistors connected in series, with the gates of the transistors connected to each other. Similarly, when a circuit diagram shows one switch, this includes two or more transistors connected in series or in parallel, with the gates of the transistors connected to each other.

[0060] Furthermore, in this specification and the like, a node can be referred to as a terminal, a wiring, an electrode, a conductive layer, a conductor, an impurity region, etc. depending on the circuit configuration and device structure. Furthermore, a terminal, a wiring, etc. can be referred to as a node.

[0061] Furthermore, in this specification and the like, a selector may refer to, for example, a circuit having multiple input terminals and one output terminal, selecting one of the multiple input terminals, and establishing a conductive state between the selected input terminal and the one output terminal. In other words, a selector may refer to a circuit that selects one of the input signals input to each of the multiple input terminals and outputs the selected input signal to the output terminal. Alternatively, a selector may refer to, for example, a circuit having multiple output terminals and one input terminal, selecting one of the multiple output terminals, and establishing a conductive state between the selected output terminal and the one input terminal. In other words, a selector may refer to a circuit that selects one of the multiple output terminals and outputs an input signal input to the input terminal to the selected output terminal. In other words, a selector may refer to a multiplexer or a demultiplexer. In particular, when inputting or outputting an analog potential or an analog current, a selector may refer to an analog multiplexer or an analog demultiplexer.

[0062] Furthermore, in this specification and the like, the terms "voltage" and "potential" can be interchanged as appropriate. "Voltage" refers to the potential difference from a reference potential. For example, if the reference potential is the ground potential (earth potential), then "voltage" can be interchanged with "potential." Note that ground potential does not necessarily mean 0 V. Furthermore, potential is relative, and as the reference potential changes, the potential applied to wiring, the potential applied to a circuit, etc., the potential output from a circuit, etc. also changes.

[0063] Furthermore, in this specification and the like, the terms "high-level potential" and "low-level potential" do not mean specific potentials. For example, when two wirings are both described as "functioning as wirings that supply a high-level potential," the high-level potentials applied to the two wirings may be different from each other. Similarly, when two wirings are both described as "functioning as wirings that supply a low-level potential," the low-level potentials applied to the two wirings may be different from each other.

[0064] Furthermore, "current" refers to the phenomenon of charge transfer (electrical conduction). For example, the statement "electrical conduction of a positively charged body is occurring" can be rephrased as "electrical conduction of a negatively charged body is occurring in the opposite direction." Therefore, in this specification, unless otherwise specified, "current" refers to the phenomenon of charge transfer (electrical conduction) associated with the movement of carriers. Examples of carriers here include electrons, holes, anions, cations, and complex ions, and the carriers differ depending on the system through which the current flows (e.g., semiconductor, metal, electrolyte, and vacuum). Furthermore, the "direction of current" in wiring, etc., refers to the direction in which positively charged carriers move and is expressed as a positive current amount. In other words, the direction in which negatively charged carriers move is opposite to the direction of current and is expressed as a negative current amount. Therefore, in this specification, unless otherwise specified regarding the positive / negative sign of the current (or the direction of current), the statement "current flows from element A to element B" can be rephrased as "current flows from element B to element A." Furthermore, the statement "current is input to element A" can be rephrased as "current is output from element A."

[0065] Furthermore, in this specification, ordinal numbers such as "first," "second," and "third" are used to avoid confusion between components. Therefore, they do not limit the number of components. Furthermore, they do not limit the order of the components. For example, a component referred to as "first" in one embodiment of this specification may be a component referred to as "second" in another embodiment or in the claims. Furthermore, for example, a component referred to as "first" in one embodiment of this specification may be omitted in another embodiment or in the claims.

[0066] Furthermore, in this specification, terms indicating position, such as "above" and "below," may be used for convenience in describing the positional relationship between components with reference to the drawings. Furthermore, the positional relationship between components changes as appropriate depending on the direction in which each configuration is depicted. Therefore, the terms are not limited to those described in the specification, and can be rephrased appropriately depending on the situation. For example, the expression "insulator located on the upper surface of a conductor" can be rephrased as "insulator located on the lower surface of a conductor" by rotating the orientation of the drawing by 180 degrees.

[0067] Furthermore, the terms "above" and "below" do not limit the positional relationship of components to being directly above or below and in direct contact with each other. For example, the expression "electrode B on insulating layer A" does not require that electrode B be formed in direct contact with insulating layer A, and does not exclude the inclusion of other components between insulating layer A and electrode B. Similarly, the expression "electrode B above insulating layer A" does not require that electrode B be formed in direct contact with insulating layer A, and does not exclude the inclusion of other components between insulating layer A and electrode B. Similarly, the expression "electrode B below insulating layer A" does not require that electrode B be formed in direct contact below insulating layer A, and does not exclude the inclusion of other components between insulating layer A and electrode B.

[0068] Furthermore, in this specification, terms such as "row" and "column" may be used to describe components arranged in a matrix and their positional relationships. Furthermore, the positional relationships between components change as appropriate depending on the direction in which each component is depicted. Therefore, the terms are not limited to those used in the specification, and may be rephrased appropriately depending on the situation. For example, the expression "row direction" may be rephrased as "column direction" by rotating the orientation of the drawing by 90 degrees.

[0069] Furthermore, in this specification and the like, the terms "film" and "layer" can be interchanged depending on the situation. For example, the term "conductive layer" may be changed to the term "conductive film." Or, for example, the term "insulating film" may be changed to the term "insulating layer." Or, in some cases or depending on the situation, the terms "film" and "layer" may not be used and may be replaced with other terms. For example, the term "conductive layer" or "conductive film" may be changed to the term "conductor." Or, for example, the term "insulating layer" or "insulating film" may be changed to the term "insulator."

[0070] Furthermore, in this specification and the like, terms such as "electrode," "wiring," and "terminal" do not functionally limit these components. For example, an "electrode" may be used as part of a "wiring," and vice versa. Furthermore, terms such as "electrode" or "wiring" include cases where multiple "electrodes" or "wirings" are integrally formed. Furthermore, for example, a "terminal" may be used as part of a "wiring" or "electrode," and vice versa. Furthermore, the term "terminal" includes cases where one or more selected from "electrode," "wiring," and "terminal" are integrally formed. Therefore, for example, an "electrode" can be part of a "wiring" or "terminal," and a "terminal" can be part of a "wiring" or "electrode." Furthermore, the terms "electrode," "wiring," and "terminal" may be replaced with the term "region" in some cases.

[0071] Furthermore, in this specification and the like, terms such as "wiring," "signal line," and "power line" may be interchangeable depending on the circumstances. For example, the term "wiring" may be changed to the term "signal line." For example, the term "wiring" may be changed to the term "power line." Vice versa, terms such as "signal line" or "power line" may be changed to the term "wiring." A term such as "power line" may be changed to the term "signal line." Vice versa, a term such as "signal line" may be changed to the term "power line." Furthermore, a term such as "potential" applied to a wiring may be changed to the term "signal" depending on the circumstances. Vice versa, a term such as "signal" may be changed to the term "potential."

[0072] In addition, timing charts may be used in this specification and the like to explain an operation method of a semiconductor device. The timing charts used in this specification and the like illustrate ideal operation examples, and the periods, magnitudes, and timings of signals (e.g., potentials or currents) described in the timing charts are not limited unless otherwise specified. The magnitudes and timings of signals (e.g., potentials or currents) input to each wiring (including a node) in the timing charts described in this specification and the like can be changed depending on the situation. For example, even if two periods are shown at equal intervals in a timing chart, the lengths of the two periods may be different. For example, even if one period is shown as being long and the other period is shown as being short, the lengths of the two periods may be equal, or one period may be short and the other period may be long.

[0073] In this specification and the like, a metal oxide refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as oxide semiconductors or simply as OSs), and the like. For example, when a metal oxide is contained in a channel formation region of a transistor, the metal oxide may be referred to as an oxide semiconductor. In other words, when a metal oxide can form a channel formation region of a transistor having at least one of an amplifying function, a rectifying function, and a switching function, the metal oxide can be referred to as a metal oxide semiconductor. Furthermore, an OS transistor can be referred to as a transistor including a metal oxide or an oxide semiconductor.

[0074] In this specification and the like, nitrogen-containing metal oxides may also be collectively referred to as metal oxides. Nitrogen-containing metal oxides may also be referred to as metal oxynitrides.

[0075] In this specification and the like, the term "impurities" in a semiconductor refers to, for example, elements other than the main component constituting the semiconductor layer. For example, an element with a concentration of less than 0.1 atomic % is an impurity. The presence of impurities may cause one or more of the following: an increase in the defect level density of the semiconductor, a decrease in carrier mobility, and a decrease in crystallinity. When the semiconductor is an oxide semiconductor, impurities that change the characteristics of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main component, particularly, for example, hydrogen (also contained in water), lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen.

[0076] In this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, it also includes cases where the angle is -5° or more and 5° or less. Furthermore, "substantially parallel" or "roughly parallel" refers to a state in which two straight lines are arranged at an angle of -30° or more and 30° or less. Furthermore, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, it also includes cases where the angle is 85° or more and 95° or less. Furthermore, "substantially perpendicular" or "approximately perpendicular" refers to a state in which two straight lines are arranged at an angle of 60° or more and 120° or less.

[0077] In this specification and the like, the configurations shown in each embodiment can be appropriately combined with the configurations shown in other embodiments to form one aspect of the present invention. In addition, when multiple configuration examples are shown in one embodiment, the configuration examples can be appropriately combined with each other.

[0078] In addition, the content described in one embodiment can be applied, combined, or replaced with another content described in that embodiment and at least one of the content described in another embodiment.

[0079] The contents described in the embodiments refer to the contents described in each embodiment using various figures or the contents described using text in the specification.

[0080] Furthermore, a figure described in one embodiment can be combined with another portion of that figure and at least one figure described in one or more other embodiments to form even more figures.

[0081] The embodiments described in this specification are described with reference to the drawings. However, it will be readily understood by those skilled in the art that the embodiments can be implemented in many different ways, and that various changes in form and details can be made without departing from the spirit and scope of the invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments. Note that in the configuration of the invention of the embodiments, the same reference numerals are used in different drawings for the same parts or parts having similar functions, and repeated description thereof may be omitted. Also, in perspective views and the like, the description of some components may be omitted to ensure clarity of the drawings.

[0082] In this specification, when the same reference numeral is used for multiple elements, and particularly when it is necessary to distinguish between them, an identification symbol such as "_1", "[n]", "[m, n]" may be added to the reference numeral. Also, when an identification symbol such as "_1", "[n]", "[m, n]" is added to the reference numeral in the drawings, etc., the identification symbol may not be added if it is not necessary to distinguish between them in this specification.

[0083] In addition, in the drawings of this specification, the size, layer thickness, or region may be exaggerated for clarity. Therefore, the drawings are not necessarily limited to the scale. Note that the drawings are schematic illustrations of ideal examples, and are not limited to the shapes or values ​​shown in the drawings. For example, variations in signals, voltages, or currents due to noise, or variations in signals, voltages, or currents due to timing differences may be included.

[0084] Embodiment 1 In this embodiment, an amplifier circuit according to one embodiment of the present invention will be described.

[0085] 1 is an example of an amplifier circuit that can be provided in a memory circuit. The amplifier circuit WRC has a function of amplifying a potential corresponding to data to be written to a memory cell and a function of amplifying a potential corresponding to data read from the memory cell. Therefore, the amplifier circuit WRC can be called a write circuit or a read circuit.

[0086] The amplifier circuit WRC is an amplifier circuit that can write and read data to and from gain cell type memory cells, for example. Gain cell type memory cells will be described later, but the amplifier circuit WRC can write and read data to and from gain cell type memory cells such as 2T (transistor) 0C (capacitor) type, 2T1C type, and 3T1C type.

[0087] The amplifier circuit WRC includes, for example, a switch WSW1, a switch WSW2, a switch RSW1, a switch RSW2, a switch DSW, a switch DBSW, and a sense amplifier LTSA.

[0088] 1 is a latch-type sense amplifier, for example. The sense amplifier LTSA has two input / output terminals, a terminal IT and a terminal ITB. The sense amplifier LTSA also has an inverter INV1, an inverter INV2, a switch HSW, and a switch LSW.

[0089] A first terminal of the switch WSW1 and a first terminal of the switch WSW2 are connected to the wiring WBL. A second terminal of the switch WSW1 is connected to the wiring VRE. A second terminal of the switch WSW2, a first terminal of the switch DSW, and a terminal IT of the sense amplifier LTSA are connected to the wiring BL. A second terminal of the switch DSW is connected to the wiring DBL.

[0090] The first terminal of the switch RSW1 and the first terminal of the switch RSW2 are connected to the wiring RBL. The second terminal of the switch RSW1 is connected to the wiring VPE. The second terminal of the switch RSW2, the first terminal of the switch DBSW, and the terminal ITB of the sense amplifier LTSA are connected to the wiring BLB.

[0091] The control terminals of the switches WSW1 and RSW2 are connected to the wiring RE. The control terminal of the switch RSW1 is connected to the wiring PREB. The control terminal of the switch WSW2 is connected to the wiring WE. The control terminals of the switches DSW and DBSW are connected to the wiring CSEL.

[0092] In the sense amplifier LTSA, the input terminal of the inverter INV1 and the output terminal of the inverter INV2 are each connected to the terminal IT. The input terminal of the inverter INV2 and the output terminal of the inverter INV1 are each connected to the terminal ITB. The first terminal of the switch HSW is connected to the high power supply potential input terminal of each of the inverters INV1 and INV2, and the first terminal of the switch LSW is connected to the low power supply potential input terminal of each of the inverters INV1 and INV2. The second terminal of the switch HSW is connected to the wiring VDE, and the control terminal of the switch HSW is connected to the wiring SWEB. The second terminal of the switch LSW is connected to the wiring VSE, and the control terminal of the switch LSW is connected to the wiring SWE.

[0093] For example, the wiring BL functions as a wiring for connecting the wiring WBL and the wiring DBL. For example, the wiring BL functions as a wiring for transmitting data to be written to a memory cell. The wiring BL may also be called a bit line. Note that in FIG. 1 , the connection portion between the second terminal of the switch WSW2, the first terminal of the switch DSW, and the terminal IT of the sense amplifier LTSA is shown as the wiring BL, but the wiring BL may not be treated as a wiring but may be treated as a connection region or a node.

[0094] For example, the wiring BLB functions as a wiring for connecting the wiring RBL and the wiring DBLB. For example, the wiring BLB functions as a wiring for transmitting data to be written to a memory cell or data read from a memory cell. The wiring BLB may be called an inverted bit line in contrast to the wiring BL, which is a bit line. Note that in FIG. 1 , the connection portion between the second terminal of the switch RSW2, the first terminal of the switch DBSW, and the terminal ITB of the sense amplifier LTSA is shown as the wiring BLB, but the wiring BLB may not be treated as a wiring but may be treated as a connection region or a node.

[0095] For example, the wiring WBL functions as a write bit line connected to the memory cell, and the wiring RBL functions as a read bit line connected to the memory cell.

[0096] For example, the wiring VRE functions as a wiring for applying a fixed potential to the wiring WBL. The fixed potential is preferably lower than a fixed potential applied by a wiring VPE, which will be described later.

[0097] For example, the wiring VPE functions as a wiring for applying a fixed potential to the wiring RBL. The fixed potential is preferably, for example, a high-level potential.

[0098] For example, the wiring VDE functions as a wiring that supplies a high-level potential as a fixed potential to the high power supply potential input terminals of the inverters INV1 and INV2. Note that the high-level potential supplied by the wiring VDE can be made equal to the high-level potential supplied by the wiring VPE.

[0099] For example, the wiring VSE functions as a wiring that applies a fixed potential to the low power supply potential input terminals of the inverters INV1 and INV2. The fixed potential is preferably a low-level potential, a ground potential, a negative potential, or the like that is lower than the high-level potential that is the fixed potential applied by the wirings VPE and VDE.

[0100] The wiring PREB functions as a wiring for transmitting a control signal for switching the switch RSW1 between an on state and an off state.

[0101] The wiring RE functions as a wiring that transmits a control signal for switching the switches WSW1 and RSW2 between an on state and an off state. The wiring RE may be called a read enable wiring, and the control signal may be called a read enable signal.

[0102] The wiring WE functions as a wiring that transmits a control signal for switching the switch WSW2 between an on state and an off state. The wiring WE may be called a write enable wiring, and the control signal may be called a write enable signal.

[0103] The line CSEL functions as a line that transmits a control signal for switching the switches DSW and DBSW between an on state and an off state. The line CSEL may also be called a column selection line.

[0104] The wiring SWE functions as a wiring for transmitting a control signal for switching the switch LSW between an on state and an off state. The wiring SWE may be called a sense amplifier enable wiring, and the control signal may be called a sense amplifier enable signal.

[0105] The wiring SWEB functions as a wiring that transmits a control signal for switching the switch HSW between an on state and an off state. The logic of the control signal is the inverse of the logic of the control signal transmitted by the wiring SWE. For this reason, the wiring SWEB is sometimes referred to as an inverted sense amplifier enable wiring, and the control signal is sometimes referred to as an inverted sense amplifier enable signal.

[0106] The wiring DBL and the wiring DBLB each function as a wiring for inputting data to be written to the memory cell as complementary data to the amplifier circuit WRC. The wiring DBL and the wiring DBLB also function as a wiring for outputting data read from the memory cell from the amplifier circuit WRC to the outside as complementary data. For this reason, the wiring DBL may be referred to as a data bit line, and the wiring DBLB may be referred to as an inverted data bit line. The wiring DBL and the wiring DBLB may be precharged to the same potential in advance in order to output data from the amplifier circuit WRC.

[0107] For example, an electrical switch (e.g., an analog switch or a transistor) can be applied to each of the switches WSW1, WSW2, RSW1, RSW2, DSW, DBSW, HSW, and LSW. In addition to the electrical switches, a mechanical switch can also be applied.

[0108] 1, analog switches can be applied as electrical switches to the switches WSW1, WSW2, and RSW2, and transistors can be applied as electrical switches to the switches RSW1, DSW, DBSW, HSW, and LSW. As described above, FIG. 2 shows the circuit configuration of an amplifier circuit WRCA as an example in which analog switches and transistors are applied to the switches in the amplifier circuit WRC.

[0109] In particular, in the amplifier circuit WRCA of FIG. 2, the switch RSW1 has a p-channel transistor MP1, the switch HSW has a p-channel transistor MP2, the switch LSW has an n-channel transistor MN1, the switch DSW1 has an n-channel transistor MN2, and the switch DBSW has an n-channel transistor MN3.

[0110] The first terminal of each transistor shown in FIG. 2 corresponds to the first terminal of the switch that includes that transistor, the second terminal of each transistor corresponds to the second terminal of the switch that includes that transistor, and the gate of each transistor corresponds to the control terminal of the switch that includes that transistor.

[0111] Furthermore, it is preferable that each of the transistors MP1, MP2, MN1, MN2, and MN3 be a transistor having silicon in a channel formation region (hereinafter referred to as a Si transistor). Depending on the situation, each of the transistors MP1, MP2, MN1, MN2, and MN3 may be an OS transistor, a transistor including germanium in a channel formation region, a transistor including a compound semiconductor such as zinc selenide, cadmium sulfide, gallium arsenide, indium phosphide, gallium nitride, or silicon germanium in a channel formation region, a transistor including a carbon nanotube in a channel formation region, or a transistor including an organic semiconductor in a channel formation region, other than a Si transistor.

[0112] 2, the wiring SWEB preferably functions as a paired wiring with the wiring SWE. Specifically, the wiring SWEB has a function of transmitting a signal whose logic is inverted from that of the signal transmitted to the wiring SWE. For example, when a high-level potential is applied to the wiring SWE, a low-level potential is applied to the wiring SWEB, and when a low-level potential is applied to the wiring SWE, a high-level potential is applied to the wiring SWEB.

[0113] In addition, in the amplifier circuit WRCA of Fig. 2, the analog switch has two control terminals, and therefore two wirings for control signals for switching the analog switch between an on state and an off state are illustrated in Fig. 2. In addition, hereinafter, the two control terminals of the analog switch will be referred to as a first control terminal and a second control terminal, respectively.

[0114] In addition, in the analog switch described in this specification, when a high-level potential is applied to the first control terminal and a low-level potential is applied to the second control terminal, the analog switch is in an ON state, and when a low-level potential is applied to the first control terminal and a high-level potential is applied to the second control terminal, the analog switch is in an OFF state.

[0115] 2, for example, the first control terminal of the switch WSW1 is connected to the wiring RE, and the second control terminal of the switch WSW1 is connected to the wiring REB. The first control terminal of the switch RSW2 is connected to the wiring REB, and the second control terminal of the switch RSW2 is connected to the wiring REB. The first control terminal of the switch WSW2 is connected to the wiring WE, and the second control terminal of the switch WSW2 is connected to the wiring WEB.

[0116] The wiring REB is a pair of wirings RE and has a function of transmitting a signal whose logic is inverted from that of the signal transmitted to the wiring RE. For example, when a high-level potential is applied to the wiring RE, a low-level potential is applied to the wiring REB, and when a low-level potential is applied to the wiring REB, a high-level potential is applied to the wiring REB.

[0117] Similarly, the wiring WEB is a pair of wirings WE and has a function of transmitting a signal whose logic is inverted from that of the signal transmitted to the wiring WE. For example, when a high-level potential is applied to the wiring WE, a low-level potential is applied to the wiring WEB, and when a low-level potential is applied to the wiring WE, a high-level potential is applied to the wiring WEB.

[0118] 2, each of the analog switches WSW1, WSW2, and RSW2 may include an n-channel transistor and a p-channel transistor, and similarly, each of the inverters INV1 and INV2 may include an n-channel transistor and a p-channel transistor.

[0119] 3 is the same as the amplifier circuit WRCA in FIG. 2, except that the switch WSW1 includes transistors MP4 and MN5, the switch WSW2 includes transistors MP5 and MN6, the switch RSW2 includes transistors MP6 and MN7, the inverter INV1 includes transistors MP8 and MN9, and the inverter INV2 includes transistors MP7 and MN8. Note that the transistors MP4 to MP8 are p-channel transistors, and the transistors MN5 to MP9 are n-channel transistors.

[0120] In the switch WSW1, the first terminal of the transistor MP4 and the first terminal of the transistor MN5 correspond to the first terminal of the switch WSW1, the second terminal of the transistor MP4 and the second terminal of the transistor MN5 correspond to the second terminal of the switch WSW1, the gate of the transistor MN5 corresponds to the first control terminal of the switch WSW1, and the gate of the transistor MP4 corresponds to the second control terminal of the switch WSW1.

[0121] In the switch WSW2, the first terminal of the transistor MP5 and the first terminal of the transistor MN6 correspond to the first terminal of the switch WSW2, the second terminal of the transistor MP5 and the second terminal of the transistor MN6 correspond to the second terminal of the switch WSW2, the gate of the transistor MN6 corresponds to the first control terminal of the switch WSW2, and the gate of the transistor MP5 corresponds to the second control terminal of the switch WSW2.

[0122] In the switch RSW2, the first terminal of the transistor MP6 and the first terminal of the transistor MN7 correspond to the first terminal of the switch RSW2, the second terminal of the transistor MP6 and the second terminal of the transistor MN7 correspond to the second terminal of the switch RSW2, the gate of the transistor MN7 corresponds to the first control terminal of the switch RSW2, and the gate of the transistor MP6 corresponds to the second control terminal of the switch RSW2.

[0123] In the sense amplifier LTSA, the first terminal of transistor MP2 is connected to the first terminal of transistor MP7 and the first terminal of transistor MP8. The first terminal of transistor MN1 is connected to the first terminal of transistor MN8 and the first terminal of transistor MN9. The terminal IT of the sense amplifier LTSA is connected to the second terminal of transistor MP7, the second terminal of transistor MN8, the gate of transistor MP8, and the gate of transistor MN9. The terminal ITB of the sense amplifier LTSA is connected to the gate of transistor MP7, the gate of transistor MN8, the second terminal of transistor MP8, and the second terminal of transistor MN9.

[0124] The first terminal of the transistor MP8 corresponds to the high power supply potential input terminal of the inverter INV1, the first terminal of the transistor MN9 corresponds to the low power supply potential input terminal of the inverter INV1, the first terminal of the transistor MP7 corresponds to the high power supply potential input terminal of the inverter INV2, and the first terminal of the transistor MN8 corresponds to the low power supply potential input terminal of the inverter INV2.

[0125] Furthermore, it is preferable that transistors MP4 to MP8, MN5, and MN9 are Si transistors. In particular, by using Si transistors for transistors MP4 to MP8, MN5, and MN9, as well as transistors MP1 to MP3, MN1, and MN4, these transistors can be formed on a semiconductor substrate containing silicon, and the amplifier circuit WRCA can be fabricated on the semiconductor substrate.

[0126] As each of the transistors MP4 to MP8 and the transistors MN5 and MN9, a transistor other than a Si transistor can be used, similar to the transistors MP1 to MP3 and the transistors MN1 and MN4, an OS transistor, a transistor including germanium in a channel formation region, a transistor including a compound semiconductor such as zinc selenide, cadmium sulfide, gallium arsenide, indium phosphide, gallium nitride, or silicon germanium in a channel formation region, a transistor including a carbon nanotube in a channel formation region, or a transistor including an organic semiconductor in a channel formation region.

[0127] In the amplifier circuit WRC shown in FIG. 1 or the amplifier circuit WRCA shown in FIGS. 2 and 3, the terminal IT of the sense amplifier LTSA is connected to the second terminal of the switch WSW2 and the first terminal of the switch DSW, and the terminal ITB of the sense amplifier LTSA is connected to the second terminal of the switch RSW2 and the first terminal of the switch DBSW. In this way, the types or numbers of circuit elements connected to the terminal IT and the terminal ITB of the sense amplifier LTSA are the same, so the parasitic capacitances of the terminal IT and the terminal ITB of the sense amplifier LTSA can be made as equal as possible. This improves the accuracy of data sensing during write or read operations using the amplifier circuit WRC or the amplifier circuit WRCA, and prevents erroneous data from being written or read.

[0128] 2 and 3, the switches WSW1, WSW2, RSW1, RSW2, DSW, and DBSW do not use logic circuits, so the number of transistors included in the amplifier circuit WRCA can be reduced. This allows the circuit area of ​​the amplifier circuit WRCA to be reduced. Furthermore, because no logic circuits are used, the power consumption of the amplifier circuit WRCA can also be reduced.

[0129] <Configuration Example of Memory Cell> Next, a configuration example of a memory cell that can be arranged in a cell array of a memory circuit including an amplifier circuit WRC will be described.

[0130] 4 is a circuit diagram showing an example of the circuit configuration of a memory cell MC. In addition to the memory cell MC, Fig. 4 also shows a memory cell array MCA including the memory cell MC and the amplifier circuit WRCA shown in Fig. 2.

[0131] The memory cell MC shown in FIG. 4 is a 2T1C type memory cell, and includes, as an example, a transistor MN11, a transistor MN12, and a capacitance element C1.

[0132] The transistor MN11 functions as a write transistor in the memory cell MC, and therefore preferably functions as a switching transistor.

[0133] The transistor MN12 functions as a read transistor in the memory cell MC, and therefore preferably functions as an amplifying transistor.

[0134] For example, the transistors MN11 and MN12 are preferably OS transistors. Examples of metal oxides for the channel formation regions of OS transistors include indium oxide, gallium oxide, and zinc oxide. The metal oxide preferably includes one or more elements selected from the group consisting of indium, an element M, and zinc. The element M is one or more elements selected from aluminum, gallium, silicon, yttrium, tin, copper, vanadium, chromium, manganese, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, calcium, strontium, barium, cobalt, and antimony. The element M is preferably one or more elements selected from the group consisting of aluminum, gallium, yttrium, and tin.

[0135] In particular, as the metal oxide used for the semiconductor layer, an oxide containing indium (In), gallium (Ga), and zinc (Zn) (also referred to as IGZO) is preferably used. Alternatively, an oxide containing indium, tin, and zinc (also referred to as ITZO (registered trademark)) is preferably used. Alternatively, an oxide containing indium, gallium, tin, and zinc is preferably used. Alternatively, an oxide containing indium (In), aluminum (Al), and zinc (Zn) (also referred to as IAZO) is preferably used. Alternatively, an oxide containing indium (In), aluminum (Al), gallium (Ga), and zinc (Zn) (also referred to as IAGZO) is preferably used. Note that an OS transistor will be described in detail in Embodiment 2.

[0136] Furthermore, the metal oxide included in the channel formation region of the OS transistor preferably has a stacked structure of multiple oxide layers with different chemical compositions. For example, consider a two-layer oxide layer structure consisting of a first layer and a second layer located immediately above the first layer. The atomic ratio of the element M to the main metal element in the metal oxide used for the first layer is preferably larger than the atomic ratio of the element M to the main metal element in the metal oxide used for the second layer. Furthermore, the atomic ratio of the element M to In in the metal oxide used for the first layer is preferably larger than the atomic ratio of the element M to In in the metal oxide used for the second layer. This structure can suppress diffusion of impurities and oxygen from structures formed below the first layer into the second layer.

[0137] In the metal oxide used for the second layer, the atomic ratio of In to the element M is preferably larger than that of In to the element M in the metal oxide used for the first layer. With this structure, the OS transistor can have large on-state current and high frequency characteristics.

[0138] Specifically, for example, the metal oxide used in the first layer may have a composition of In:M:Zn = 1:3:2 (atomic ratio) or a composition thereabout, In:M:Zn = 1:3:4 (atomic ratio) or a composition thereabout, or In:M:Zn = 1:1:0.5 (atomic ratio) or a composition thereabout. Furthermore, the metal oxide used in the second layer may have a composition of In:M:Zn = 1:1:1 (atomic ratio) or a composition thereabout, In:M:Zn = 1:1:1.2 (atomic ratio) or a composition thereabout, In:M:Zn = 1:1:2 (atomic ratio) or a composition thereabout, or In:M:Zn = 4:2:3 (atomic ratio) or a composition thereabout. Note that a composition thereabout includes a range of ±30% of the desired atomic ratio.

[0139] Incidentally, in order to reduce the off-state current of a transistor, it is preferable to use, for example, an oxide containing indium (In), gallium (Ga), and zinc (Zn) as the metal oxide used in the semiconductor layer of the transistor. When the semiconductor layer of the transistor contains an oxide containing indium (In), gallium (Ga), and zinc (Zn), the amount of current flowing between the source and drain of the transistor when the gate-source voltage is 0 V is 1×10 per 1 μm of channel width at room temperature (e.g., 25° C.). −２０ A or less, 1 x 10 at 85°C −１８ A or less, or 1 x 10 at 125°C −１６ In this specification, the state in which the amount of current flowing between the source and drain when the gate-source voltage of a transistor is 0 V is extremely small is referred to as normally-off.

[0140] A first terminal of the transistor MN11 is connected to the gate of the transistor MN12 and the first terminal of the capacitance element C1. A second terminal of the transistor MN11 is connected to the wiring WBL. A gate of the transistor MN11 is connected to the wiring WWL. A first terminal of the transistor MN12 is connected to the wiring RWL. A second terminal of the transistor MN12 is connected to the wiring RBL. A second terminal of the capacitance element C1 is connected to the wiring VGE.

[0141] For example, the wiring VGE functions as a wiring for applying a fixed potential to the second terminal of the capacitor C1. The fixed potential is preferably, for example, a low-level potential, a ground potential, or a negative potential.

[0142] For example, the wiring WWL functions as a wiring that transmits a control signal for switching the transistor MN11 between an on state and an off state. Since the transistor MN11 functions as a write transistor in the memory cell MC, the wiring WWL can be rephrased as a write word line for the memory cell MC.

[0143] For example, the wiring RWL functions as a wiring for applying a predetermined potential to the first terminal of the transistor MN12. Since the transistor MN11 functions as a read transistor in the memory cell MC, the wiring RWL can be rephrased as a read word line for the memory cell MC.

[0144] For example, when data is read from the memory cell MC, the wiring RWL applies a potential corresponding to a select signal, causing a source-drain current to flow between the first and second terminals of the transistor MN12. When data is not read from the memory cell MC, the wiring RWL applies a potential corresponding to a non-select signal, turning off the transistor MN12 or preventing a current from flowing between the first and second terminals of the transistor MN12.

[0145] Note that the memory cell according to one embodiment of the present invention is not limited to the memory cell MC illustrated in Fig. 4. Although the memory cell illustrated in Fig. 4 is a 2T1C memory cell, the amplifier circuit according to one embodiment of the present invention can also write to or read from a 2T0C or 3T1C memory cell.

[0146] Fig. 5A shows an example of a 2T0C type memory cell MC, which is a modified example of the memory cell MC shown in Fig. 4. Specifically, the memory cell MC of Fig. 5A differs from the memory cell MC of Fig. 4 in that it does not have a capacitive element C1, but instead has a parasitic capacitance PCP.

[0147] 5A, one end of the parasitic capacitance PCP is the node ND, and the other end of the parasitic capacitance PCP can be the first terminal of the transistor MN12, the gate of the transistor MN11, etc. In particular, the other end of the parasitic capacitance PCP is preferably the gate of the transistor MN11.

[0148] 5A is preferably performed when a high-level potential is applied to the wiring RWL. That is, during a data write operation, a high-level potential is preferably applied to each of the wirings WWL and RWL. This is because, when the potential of the wiring RWL fluctuates, the potential of the node ND also fluctuates due to capacitive coupling of the parasitic capacitance PCP. Therefore, in order to read correct data from the memory cell MC, a potential corresponding to the data needs to be written to the node of the memory cell MC while a high-level potential is applied to the wiring RWL.

[0149] Fig. 5B shows an example of a 3T1C type memory cell MC, which is a modified example of the memory cell MC shown in Fig. 4. Specifically, the memory cell MC in Fig. 5B differs from the memory cell MC in Fig. 4 in that a new transistor MN13 is provided.

[0150] 5B, a first terminal of the transistor MN12 is connected to the wiring VHE, a second terminal of the transistor MN12 is connected to the first terminal of the transistor MN13, a second terminal of the transistor MN13 is connected to the wiring RBL, and a gate of the transistor MN13 is connected to the wiring RWL.

[0151] The transistor MN13 functions as a switching transistor. When reading the memory cell MC, the potential of the second terminal of the transistor MN12, which is a read transistor, can be read from the wiring RBL by turning on the transistor MN13. Therefore, the wiring RWL of the transistor MN13 functions as a read word line, similar to the memory cell MC in FIG. 4 .

[0152] For example, the wiring VHE functions as a wiring that applies a fixed potential to the first terminal of the transistor MN12. The fixed potential is preferably, for example, a low-level potential, a ground potential, or a negative potential.

[0153] The memory cell MC in Figure 5B has a transistor MN13 that functions as a switching transistor, so when the memory cell MC is not performing a read operation, the read potential, which is the potential of the second terminal of the transistor MN12, can be prevented from being transmitted to the wiring RBL by turning off the transistor MN13.

[0154] <Example of Operation Method of Amplifier Circuit> Next, an example of an operation method of the amplifier circuit of one embodiment of the present invention will be described.

[0155] 6 to 8 are timing charts showing an example of an operation method of the amplifier circuit WRCA shown in Fig. 2 and Fig. 4. The timing charts also show an operation method of the amplifier circuit WRCA when writing and reading data to and from the memory cell MC shown in Fig. 4. Therefore, the timing charts show not only the wiring extending to the amplifier circuit WRCA, but also the wiring WWL and wiring RWL extending to the memory cell array MCA.

[0156] 6 to 8 show changes in the potentials of the wirings PREB, RWL, WE, RE, SWE, WWL, CSEL, BL, BLB, WBL, RBL, the node ND, DBL, and DBLB. Ｈ and the low level potential is V Ｌ It states:

[0157] <<Operation Method Example 1>> The timing chart of Figure 6 shows an example of the operation of the amplifier circuit WRCA and the memory cell MC during periods T01 to T07. Specifically, the timing chart of Figure 6 shows an example of an operation in which a low-level potential is initially held at the first terminal of the capacitance element C1 of the memory cell MC, and the amplifier circuit WRCA reads the low-level potential from the memory cell MC and rewrites the low-level potential at the first terminal of the capacitance element C1 of the memory cell MC to a high-level potential. Note that in the timing chart of Figure 6, a selection signal to the memory cell MC to be written is transmitted not only during period T04, during which the write operation is performed, but also during period T02 (activation period) and period T05 (read operation), which will be described later. During periods T02 and T05, the selection signal is transmitted to the memory cell MC, thereby rewriting (refreshing) data in the memory cell MC.

[0158] [Period T01] During period T01, the wiring PREB is in an idle state. Ｌ is given, and V is given to the wiring RWL. Ｈ is given, and V is given to the wiring WE. Ｈ is given, and V is given to the wiring RE. Ｈ is given, and V is given to the wiring SWE. Ｌ is given, and V is given to the wiring WWL. Ｌ is given, and V is given to the wiring CSEL. Ｌ Furthermore, a capacitance element C1 applies V to the node ND of the memory cell MC. Ｌ is maintained.

[0159] The potential of the wiring PREB is V Ｌ Therefore, the control terminal of the switch RSW1 (the gate of the transistor MP1) is V Ｌ Therefore, the transistor MP1 is turned on, and a potential from the wiring VPE is applied to the wiring RBL. Here, the potential applied by the wiring VPE is V ＰＲＥ And V ＰＲＥ is V Ｈ Therefore, the potential of the wiring RBL is equal to V ＰＲＥ (=V Ｈ )

[0160] The potential of the wiring WE is V Ｈ Therefore, the potential applied by the wiring WEB is a potential obtained by inverting the logic of the potential applied by the wiring WE, and is V Ｌ Therefore, the first control terminal of the switch WSW2, which is an analog switch, is V Ｈ is applied to the second control terminal, and V Ｌ is applied, the switch WSW2 is turned on, thereby establishing electrical continuity between the wiring WBL and the wiring BL.

[0161] The potential of the wiring RE is V Ｈ Therefore, the potential applied by the wiring REB is a potential obtained by inverting the logic of the potential applied by the wiring RE, and is V Ｌ Therefore, the first control terminal of the switch WSW1, which is an analog switch, is V Ｈ is applied to the second control terminal of the switch WSW1, and V Ｌ is applied to the wiring WBL, and the switch WSW1 is turned on. As a result, a potential is applied to the wiring WBL from the wiring VRE. In addition, since the switch WSW2 is turned on, a potential is also applied to the wiring BL from the wiring VRE via the wiring WBL. Here, the potential applied by the wiring VRE is defined as V Ｌ Higher V Ｈ Lower V ＲＥＦ Therefore, the potential of the wiring WBL and the wiring BL is V ＲＥＦ This becomes:

[0162] In addition, the potential of the wiring RE is V Ｈ and the potential of the wiring REB is V Ｌ Therefore, the first control terminal of the switch RSW2, which is an analog switch, is V Ｈ is applied to the second control terminal of the switch RSW2, and V Ｌ is applied to the switch RSW1, turning the switch RSW2 on. This brings the wiring RBL and the wiring BLB into a conductive state. In addition, since the switch RSW1 is on, the wiring BLB receives the potential V ＰＲＥ (=V Ｈ ) is applied. Therefore, the potential of the wiring BLB is V ＰＲＥ (=V Ｈ )

[0163] The potential of the wiring WWL is V Ｌ Therefore, the gate of the transistor MN11 of the memory cell MC is V Ｌ As a result, the transistor MN11 is turned off, and the wiring WBL and the node ND are brought into a non-conductive state.

[0164] The potential of the wiring RWL is V Ｈ Therefore, the second terminal of the transistor MN12 of the memory cell MC is V Ｈ The gate potential of the transistor MN12 is V Ｌ The potential of the first terminal (line RBL) of the transistor MN12 is V ＰＲＥ =V Ｈ Therefore, the transistor MN12 is turned off, and the wiring RWL and the wiring RBL are brought into a non-conductive state.

[0165] The potential of the wiring SWE is V Ｌ Therefore, the potential applied by the wiring SWEB is V Ｈ Therefore, the control terminal of the switch HSW (the gate of the transistor MP2) is V Ｈ is applied to the control terminal of the switch LSW (the gate of the transistor MN1), turning the transistor MP2 off. Ｌ As a result, there is no conduction between the wiring VDE and the high power supply potential input terminals of the inverters INV1 and INV2, and therefore the high power supply potential input terminals of the inverters INV1 and INV2 are supplied with V Ｈ Similarly, since there is no conduction between the wiring VSE and the low power supply potential input terminals of the inverters INV1 and INV2, the V Ｌ Therefore, the inverters INV1 and INV2 are supplied with V Ｈ and V ＬSince no signal is input, the sense amplifier LTSA is in an inactive state.

[0166] The potential of the wiring CSEL is V Ｌ Therefore, the control terminal of the switch DSW (the gate of the transistor MN2) and the control terminal of the switch DBSW (the gate of the transistor MN3) are connected to V Ｌ As a result, the transistors MN2 and MN3 are turned off, the wiring BL and the wiring DBL are brought out of conduction, and the wiring BLB and the wiring DBLB are also brought out of conduction.

[0167] Note that in the period T01 in the timing chart of FIG. 6, the potentials of the wirings DBL and DBLB are set to, for example, V Ｌ However, since no read operation or write operation is performed in the period T01, the potentials of the wiring DBL and the wiring DBLB are not limited to this. This also applies to periods T02 and T03, which will be described later.

[0168] [Periods T02 and T03] During the periods T02 and T03, the amplifier circuit WRCA performs an operation of reading out the low-level potential written in the memory cell MC.

[0169] The period T02 is also called an activation period, and as an example, an operation is performed in which a potential corresponding to data stored in the memory cell is amplified by the sense amplifier LTSA. After the activation in the period T02, the period transitions to the period T03. The period T03 is also called an active period, and is a period during which a transition to a write operation or a read operation is possible.

[0170] In the period T02, first, V Ｈ As a result, the control terminal of the switch RSW1 (the gate of the transistor MP1) is supplied with V Ｈ As a result, the transistor MP1 is turned off, and the wiring RBL and the wiring BLB are brought into a floating state.

[0171] Next, V is applied to the wiring RWL. ＬAs a result, the second terminal of the transistor MN12 of the memory cell MC is supplied with V Ｌ At this time, the potential of the gate of the transistor MN12 is V Ｌ The potential of the first terminal (line RBL) of the transistor MN12 is V ＰＲＥ =V Ｈ Therefore, the transistor MN12 continues to be in the off state from the period T01.

[0172] Next, V is applied to each of the wiring WE and the wiring RE. Ｌ is given.

[0173] Wiring WE to V Ｌ is applied, the potential of the wiring WEB becomes V Ｈ As a result, the first control terminal of the switch WSW2, which is an analog switch, is set to V Ｌ is applied to the second control terminal of the switch WSW2, and V Ｈ is applied, the switch WSW2 is turned off, and the wiring BL is thus brought into a floating state.

[0174] Also, V Ｌ is given, the potential of the wiring REB becomes V Ｈ As a result, the first control terminal of the switch WSW1, which is an analog switch, is set to V Ｌ is applied to the second control terminal of the switch WSW1, and V Ｈ is applied to the first control terminal of the switch RSW2, which is an analog switch, and the switch WSW1 is turned off. This causes the wiring WBL to be in a floating state. Ｌ is applied to the second control terminal of the switch RSW2, and V Ｈ is applied, the switch RSW2 is turned off.

[0175] Next, V is connected to the wiring SWE. Ｈ is given to the wiring SWE. Ｈ is applied, the potential of the wiring SWEB becomes V Ｌ Therefore, the control terminal of the switch HSW (the gate of the transistor MP2) is V Ｌis applied to the control terminal of the switch LSW (the gate of the transistor MN1), and the transistor MP2 is turned on. Ｈ As a result, conduction is established between the wiring VDE and the high power supply potential input terminals of the inverters INV1 and INV2, and therefore the high power supply potential input terminals of the inverters INV1 and INV2 are supplied with V from the wiring VDE. Ｈ Similarly, since the wiring VSE and the low power supply potential input terminals of the inverters INV1 and INV2 are electrically connected, the low power supply potential input terminals of the inverters INV1 and INV2 are supplied with V from the wiring VSE. Ｌ Therefore, the inverters INV1 and INV2 are supplied with V as a power supply potential. Ｈ and V Ｌ is input, the sense amplifier LTSA is activated.

[0176] When the sense amplifier LTSA is activated, the potentials of the terminals IT and ITB of the sense amplifier LTSA are amplified in accordance with each other. Specifically, when the sense amplifier LTSA is activated, the potential of the wiring BL is V ＲＥＦ and the potential of the wiring BLB is V ＰＲＥ (=V Ｈ ), the potential V ＲＥＦ is V Ｌ The potential of the wiring BLB drops to V ＰＲＥ (=V Ｈ ) remains unchanged. Therefore, the low level potential read out from the memory cell MC remains at the potential V Ｌ The potential V Ｈ This becomes:

[0177] Next, V is applied to the wiring PREB. Ｌ is given, and V is applied to each of the wiring RWL, wiring WE, and wiring WWL. Ｈ In particular, a potential V Ｈis given, data is rewritten (refreshed) into the memory cells MC during the period T02.

[0178] The potential of the wiring PREB is V Ｌ Therefore, the control terminal of the switch RSW1 (the gate of the transistor MP1) is V Ｌ Therefore, the transistor MP1 is turned on, and the wiring RBL is supplied with a voltage V ＰＲＥ (=V Ｈ ) is applied. Therefore, the potential of the wiring RBL continues to be V ＰＲＥ (=V Ｈ )

[0179] Wiring WE to V Ｈ is applied, the potential of the wiring WEB becomes V Ｌ As a result, the first control terminal of the switch WSW2, which is an analog switch, is set to V Ｈ is applied to the second control terminal of the switch WSW2, and V Ｌ is applied to the switch WSW2, the switch WSW2 is turned on. This brings the wiring WBL and the wiring BL into a conductive state. Before the switch WSW2 is turned on, the wiring WBL is in a floating state, and the wiring BL is supplied with a potential V Ｌ is given, when the switch WSW2 is turned on, the potential of the wiring WBL becomes V ＲＥＦ From V Ｌ It drops to.

[0180] The potential of the wiring WWL is V Ｈ Therefore, the gate of the transistor MN11 of the memory cell MC is V Ｈ is applied (data is rewritten (refreshed) to the memory cell MC). Therefore, the transistor MN11 is turned on, and electrical continuity is established between the wiring WBL and the node ND. In addition, since the switch WSW2 is turned on, the node ND is supplied with the potential V Ｌ As a result, the potential of the node ND is VＬ This becomes:

[0181] Note that, since the wiring WBL and the node ND are brought into electrical continuity, charge is redistributed between the wiring WBL and the node ND, and therefore the timing chart in FIG. 6 shows an example in which the potential of the node ND is temporarily high. This is because, before electrical continuity is brought into the wiring WBL and the node ND, the potential of the wiring WBL is V ＲＥＦ This is because the positive charges of the wiring WBL temporarily flow into the node ND.

[0182] The potential of the wiring RWL is V Ｈ Therefore, the second terminal of the transistor MN12 of the memory cell MC is V Ｈ At this time, the potential of the gate of the transistor MN12 is V Ｌ The potential of the first terminal (line RBL) of the transistor MN12 is V ＰＲＥ (=V Ｈ ), the transistor MN12 continues to be in the off state.

[0183] As described above, the period T03 can be an active period for the memory cell MC. After the active period of the period T03, the operation can transition from the period T03 to a data write operation to the memory cell MC (period T04) or a data read operation from the memory cell MC (period T05).

[0184] [Period T04] During period T04, the data is written to the memory cell MC.

[0185] First, a potential corresponding to the data to be written in the memory cell MC is applied to the wiring DBL. Ｈ Further, a potential V is applied to the wiring DBLB as a potential whose logic is inverted from the potential applied to the wiring DBL. Ｌ is given.

[0186] Then, V is connected to the wiring CSEL. Ｈ As a result, V is applied to the control terminal of the switch DSW (the gate of the transistor MN2) and the control terminal of the switch DBSW (the gate of the transistor MN3). ＨAs a result, the transistor MN2 is turned on, bringing electrical continuity between the wiring BL and the wiring DBL, and the transistor MN3 is turned on, bringing electrical continuity between the wiring BLB and the wiring DBLB.

[0187] In particular, V given by the wiring DBL Ｈ and V given by wiring DBLB Ｌ is preferably a potential amplified by an amplifier (for example, a sense amplifier) ​​located outside the amplifier circuit WRCA, and in particular, the amplifier is preferably an amplifier capable of supplying a charge sufficient to rewrite the potential held by the sense amplifier LTSA in an active state. When the potential held by the sense amplifier LTSA is rewritten using the amplifier, power consumption may increase, but the operation of the sense amplifier LTSA to be put into an inactive state by the wiring SWE and the wiring SWEB is eliminated, and therefore the operation of the amplifier circuit WRCA can be accelerated.

[0188] On the other hand, if it is desired to reduce power consumption, it is preferable to once inactivate the sense amplifier LTSA before the switches DSW and DBSW are turned on. Ｈ and a potential V Ｌ As described above, by appropriately switching the sense amplifier LTSA between the active state and the inactive state, it is possible to reduce the power consumption in the amplifier circuit WRCA.

[0189] When the transistors MN2 and MN3 are turned on, the potential V Ｈ The wiring BLB is supplied with a potential V Ｌ is given, the terminal IT of the sense amplifier LTSA is V Ｈ The terminal ITB of the sense amplifier LTSA is held at V Ｌ In addition, since the switch WSW2 is in the on state, the potentials of the wirings BL and WBL are VＨ The potential of the wiring BLB is V Ｌ Since the switch RSW2 is in the off state, the potential of the wiring RBL is V Ｈ It remains unchanged.

[0190] In addition, the wiring WWL is connected to the V Ｈ Therefore, the node ND of the memory cell MC receives V from the wiring DBL via the wiring WBL and the wiring BL. Ｈ As a result, V is written to the memory cell MC as write data. Ｈ is written.

[0191] Then, V is connected to the wiring CSEL. Ｌ As a result, V is applied to the control terminal of the switch DSW (the gate of the transistor MN2) and the control terminal of the switch DBSW (the gate of the transistor MN3). Ｌ As a result, the transistor MN2 is turned off, causing a non-conduction state between the wiring BL and the wiring DBL, and the transistor MN3 is turned off, causing a non-conduction state between the wiring BLB and the wiring DBLB.

[0192] [Period T05] In the period T05, the potential held by the sense amplifier LTSA is read. As described above, the active period of the period T03 is directly transitioned to the period T05, and data can be read from the memory cell MC.

[0193] First, the wiring DBL and the wiring DBLB are V Ｈ is precharged to

[0194] Then, V is connected to the wiring CSEL. Ｈ As a result, V is applied to the control terminal of the switch DSW (the gate of the transistor MN2) and the control terminal of the switch DBSW (the gate of the transistor MN3). Ｈ As a result, the transistor MN2 is turned on, bringing electrical continuity between the wiring BL and the wiring DBL, and the transistor MN3 is turned on, bringing electrical continuity between the wiring BLB and the wiring DBLB.

[0195] When the wiring BLB and the wiring DBLB are brought into electrical conduction, charge is redistributed between the wiring BLB and the wiring DBLB. Therefore, the timing chart in FIG. 6 shows an example in which the potential of the wiring BLB is temporarily high. After that, the potential of the wiring BLB and the wiring DBLB is V Ｌ On the other hand, the wiring BL and the wiring DBL are in a conductive state, but both the wiring BL and the wiring DBL are V Ｈ Therefore, potential fluctuation does not occur in either the wiring BL or the wiring DBL.

[0196] As a result, the line DBL receives the V Ｈ Also, V amplified by the sense amplifier LTSA is output to the line DBLB via the terminal ITB and the line BLB. Ｌ will be output.

[0197] In addition, according to the above operation, it is preferable that the potentials held in the sense amplifier LTSA be read after the potentials of the wirings BL and BLB are read to the wirings DBL and DBLB, respectively.

[0198] Then, V is connected to the wiring CSEL. Ｌ As a result, V is applied to the control terminal of the switch DSW (the gate of the transistor MN2) and the control terminal of the switch DBSW (the gate of the transistor MN3). Ｌ As a result, the transistor MN2 is turned off, causing a non-conduction state between the wiring BL and the wiring DBL, and the transistor MN3 is turned off, causing a non-conduction state between the wiring BLB and the wiring DBLB.

[0199] In the period T05, similarly to the period T02, the potential of the wiring WWL is V Ｈ Therefore, the transistor MN11 is turned on, and data is rewritten (refreshed) to the memory cell MC as indicated by the potential fluctuations of the node ND and the wiring WBL.

[0200] [Period T06] During period T06, the data in the memory cell MC is retained and the amplifier circuit WRC is set to an idle state. In this specification, period T06 may also be referred to as a precharge period for transitioning to the idle state.

[0201] In the period T06, first, V Ｌ As a result, the gate of the transistor MN11 is supplied with V Ｌ As a result, the transistor MN11 is turned off, and the node ND receives the potential V Ｈ is maintained.

[0202] Next, V is connected to the wiring SWE. Ｌ is given, and V is applied to the wiring RE. Ｈ is given.

[0203] The potential of the wiring SWE is V Ｌ Therefore, the potential applied by the wiring SWEB is V Ｈ Therefore, the control terminal of the switch HSW (the gate of the transistor MP2) is V Ｈ is applied to the control terminal of the switch LSW (the gate of the transistor MN1), turning the transistor MP2 off. Ｌ As a result, there is no conduction between the wiring VDE and the high power supply potential input terminals of the inverters INV1 and INV2, and therefore the high power supply potential input terminals of the inverters INV1 and INV2 are supplied with V Ｈ Similarly, since there is no conduction between the wiring VSE and the low power supply potential input terminals of the inverters INV1 and INV2, the V Ｌ Therefore, the inverters INV1 and INV2 are supplied with V Ｈ and V Ｌ Since no signal is input, the sense amplifier LTSA is in an inactive state.

[0204] Wiring RE to V Ｈ is given, the potential of the wiring REB becomes V Ｌ As a result, the first control terminal of the switch WSW1, which is an analog switch, is set to V Ｈ is applied to the second control terminal of the switch WSW1, and V Ｌ , the switch WSW1 is turned on. As a result, the potential V ＲＥＦ In addition, since the switch WSW2 is in an on state, the potential V ＲＥＦ is given.

[0205] In addition, the potential of the wiring RE is V Ｈ and the potential of the wiring REB is V Ｌ Therefore, the first control terminal of the analog switch RSW2 is V Ｈ is applied to the second control terminal of the switch RSW2, and V Ｌ Therefore, the switch RSW2 is turned on, and the wiring RBL and the wiring BLB are electrically connected. In addition, since the switch RSW1 is turned on, the potential V ＰＲＥ (=V Ｈ ) is applied. Therefore, the potential of the wiring BLB is V ＰＲＥ (=V Ｈ )

[0206] By the operation during the period T06, the amplifier circuit WRC can be set to the same idle state during the period T07 as during the period T01.

[0207] Note that in the period T06 in the timing chart of FIG. 6, the potentials of the wirings DBL and DBLB are set to, for example, V Ｌ However, since no read operation or write operation is performed in the period T06, the potentials of the wiring DBL and the wiring DBLB are not limited to these values. The same applies to the period T07.

[0208] 6, in the period T02, data is rewritten (refreshed) to the memory cell MC, so that the transistor MN11, which is a write transistor, is turned on at the stage of the data read operation from the memory cell MC to the sense amplifier LTSA. At this time, the potential of the node ND of the memory cell MC is V Ｌ , the potentials of the wirings BL and WBL are V Ｌ Similarly, in the period T15, data is rewritten (refreshed) to the memory cell MC, but the potential of the node ND of the memory cell MC does not change because the potential of the node ND of the memory cell MC is V Ｈ , the potentials of the wirings BL and WBL are V Ｈ Therefore, there is no change in the potential (retained data) at the node ND of the memory cell MC.

[0209] 6, data is rewritten (refreshed) to the memory cell MC in the period T02, so that the transistor MN11, which is a write transistor, can be turned on at an early stage. Therefore, when the data held in the memory cell MC is rewritten after the period T03 (when the period T04 is performed), the potentials of the wiring BL and the wiring WBL can be rewritten, thereby shortening the time required for the write operation.

[0210] Furthermore, in the operation of the timing chart of Figure 6, since a through current is unlikely to occur in the amplifier circuit WRC or the through current can be made extremely small (since there is no timing when a conductive state occurs between the wiring that applies a high power supply potential and the wiring that applies a low power supply potential), the use of the amplifier circuit WRC can reduce the power consumption associated with writing and reading data by the memory cell.

[0211] <<Operation Method Example 2>> The timing chart of Figure 7 is an example of operation different from the timing chart of Figure 6 and shows an example of operation between the amplifier circuit WRCA and the memory cell MC during periods T11 to T17. Specifically, the timing chart of Figure 7 shows an example of an operation in which a high-level potential is initially held at the first terminal of the capacitance element C1 of the memory cell MC, and the amplifier circuit WRCA reads the high-level potential from the memory cell MC and rewrites the high-level potential at the first terminal of the capacitance element C1 of the memory cell MC to a low-level potential. Note that in the timing chart of Figure 7, a selection signal to the memory cell MC to be written is transmitted not only during period T14, during which the write operation is performed, but also during period T12 (activation period) and period T15 (read operation), which will be described later. During periods T12 and T15, the selection signal is transmitted to the memory cell MC, thereby rewriting (refreshing) data in the memory cell MC.

[0212] [Period T11] In the period T11, similarly to the period T01 in the timing chart of FIG. 6, the wiring PREB is in an idle state. Ｌ is given, and V is given to the wiring RWL. Ｈ is given, and V is given to the wiring WE. Ｈ is given, and V is given to the wiring RE. Ｈ is given, and V is given to the wiring SWE. Ｌ is given, and V is given to the wiring WWL. Ｌ is given, and V is given to the wiring CSEL. Ｌ Therefore, the period T01 in the timing chart of FIG. 6 can be referred to for the on / off of each switch included in the amplifier circuit WRCA. ＲＥＦ The potentials of the wirings BLB and RBL are V ＰＲＥ Although not particularly limited, the potentials of the wiring DBL and the wiring DBLB in the period T01 in the timing chart of FIG. Ｌ It states that:

[0213] In the period T11, the node ND of the memory cell MC is connected to the capacitor C1 via V ＨTherefore, during the period T11, the potential of the node ND is V Ｈ It is as follows.

[0214] [Period T12 and Period T13] During the periods T12 and T13, the amplifier circuit WRCA performs an operation of reading out the high-level potential written in the memory cell MC.

[0215] The period T12 is also called an activate period, similar to the period T02 in the timing chart of Fig. 6. The period T13 is also called an active period, similar to the period T03 in the timing chart of Fig. 6.

[0216] In the period T12, first, V Ｈ As a result, the control terminal of the switch RSW1 (the gate of the transistor MP1) is supplied with V Ｈ As a result, the transistor MP1 is turned off, and the wiring RBL and the wiring BLB are brought into a floating state.

[0217] Next, V is applied to the wiring RWL. Ｌ As a result, the second terminal of the transistor MN12 of the memory cell MC is supplied with V Ｌ At this time, the potential of the gate of the transistor MN12 is V Ｈ Therefore, the transistor MN12 is turned on, and the potential of the first terminal (wiring RBL) of the transistor MN12 is V ＰＲＥ =V Ｈ As a result, the potential of the wiring BLB, which is electrically connected to the wiring RWL, also drops. ＲＥＦ shall be lower than

[0218] Next, V is applied to each of the wiring WE and the wiring RE. Ｌ is given.

[0219] Wiring WE to V Ｌ is applied, the potential of the wiring WEB becomes V Ｈ As a result, the first control terminal of the switch WSW2, which is an analog switch, is set to V Ｌis applied to the second control terminal of the switch WSW2, and V Ｈ is applied, the switch WSW2 is turned off, and the wiring BL is thus brought into a floating state.

[0220] Also, V Ｌ is given, the potential of the wiring REB becomes V Ｈ As a result, the first control terminal of the switch WSW1, which is an analog switch, is set to V Ｌ is applied to the second control terminal of the switch WSW1, and V Ｈ is applied to the first control terminal of the switch RSW2, which is an analog switch, and the switch WSW1 is turned off. This causes the wiring WBL to be in a floating state. Ｌ is applied to the second control terminal of the switch RSW2, and V Ｈ is applied, the switch RSW2 is turned off.

[0221] When the switch RSW2 is turned off, the wiring BLB and the wiring RBL are brought into a non-conductive state, and the wiring BLB is brought into a floating state. Therefore, the potential of the wiring BLB stops decreasing. On the other hand, the wiring RBL continues to be electrically connected to the wiring RWL, so the potential of the wiring RBL continues to decrease.

[0222] Next, V is connected to the wiring SWE. Ｈ is given to the wiring SWE. Ｈ is applied, the sense amplifier LTSA is activated, as in the period T02 of the timing chart of FIG.

[0223] When the sense amplifier LTSA is activated, the potentials of the terminals IT and ITB of the sense amplifier LTSA are amplified in accordance with each other. Specifically, when the sense amplifier LTSA is activated, the potential of the wiring BL is V ＲＥＦ and the potential of the wiring BLB is V ＲＥＦ Since the potential of the wiring BL is less than ＲＥＦ is V Ｈ The potential of the wiring BLB rises to V ＬTherefore, the high level potential read out from the memory cell MC is reduced to a potential V Ｈ The potential V Ｌ This becomes:

[0224] Since the switch WSW2 is in the OFF state, there is no conduction between the wiring WBL and the wiring BL, and therefore the potential of the wiring WBL does not change due to amplification by the sense amplifier LTSA.

[0225] Next, V is applied to the wiring PREB. Ｌ is given, and V is applied to each of the wiring RWL, wiring WE, and wiring WWL. Ｈ In particular, a potential V Ｈ is given, data is rewritten (refreshed) into the memory cells MC during the period T12.

[0226] The potential of the wiring PREB is V Ｌ Therefore, the control terminal of the switch RSW1 (the gate of the transistor MP1) is V Ｌ Therefore, the transistor MP1 is turned on, and the wiring RBL is supplied with a voltage V ＰＲＥ (=V Ｈ ) is given. Therefore, the potential of the wiring RBL is V ＰＲＥ (=V Ｈ )

[0227] Wiring WE to V Ｈ is applied, the potential of the wiring WEB becomes V Ｌ As a result, the first control terminal of the switch WSW2, which is an analog switch, is set to V Ｈ is applied to the second control terminal of the switch WSW2, and V Ｌ is applied to the switch WSW2, the switch WSW2 is turned on. This brings the wiring WBL and the wiring BL into a conductive state. Before the switch WSW2 is turned on, the wiring WBL is in a floating state, and the wiring BL is supplied with a potential V Ｈ is given, when the switch WSW2 is turned on, the potential of the wiring WBL becomes V ＲＥＦ From VＨ It will become as high as

[0228] The potential of the wiring WWL is V Ｈ Therefore, the gate of the transistor MN11 of the memory cell MC is V Ｈ is applied (data is rewritten (refreshed) to the memory cell MC). Therefore, the transistor MN11 is turned on, and electrical continuity is established between the wiring WBL and the node ND. In addition, since the switch WSW2 is turned on, the node ND is supplied with the potential V Ｈ As a result, the potential of the node ND is V Ｈ This becomes:

[0229] Note that, since the wiring WBL and the node ND are brought into electrical continuity, charge is redistributed between the wiring WBL and the node ND, and therefore the timing chart in FIG. 7 shows an example in which the potential of the node ND is temporarily low. This is because, before electrical continuity is brought into the wiring WBL and the node ND, the potential of the wiring WBL is V ＲＥＦ This is because the positive charges of the node ND temporarily flow into the wiring WBL.

[0230] The potential of the wiring RWL is V Ｈ Therefore, the second terminal of the transistor MN12 of the memory cell MC is V Ｈ At this time, the potential of the gate of the transistor MN12 is V Ｈ The potential of the first terminal (line RBL) of the transistor MN12 is V ＰＲＥ (=V Ｈ ), the transistor MN12 is in the off state.

[0231] The period T13 can be an active period for the memory cell MC, similar to the period T03 in the timing chart of Fig. 6. After the active period of the period T13, the operation can move from the period T13 to a data write operation to the memory cell MC (period T14) or a data read operation from the memory cell MC (period T15).

[0232] [Period T14] During period T14, the data is written to the memory cell MC.

[0233] First, a potential corresponding to the data to be written in the memory cell MC is applied to the wiring DBL. Ｌ Further, a potential V is applied to the wiring DBLB as a potential whose logic is inverted from the potential applied to the wiring DBL. Ｈ is given.

[0234] Then, V is connected to the wiring CSEL. Ｈ As a result, V is applied to the control terminal of the switch DSW (the gate of the transistor MN2) and the control terminal of the switch DBSW (the gate of the transistor MN3). Ｈ As a result, the transistor MN2 is turned on, bringing electrical continuity between the wiring BL and the wiring DBL, and the transistor MN3 is turned on, bringing electrical continuity between the wiring BLB and the wiring DBLB.

[0235] In particular, V given by the wiring DBL Ｌ and V given by wiring DBLB Ｈ As in period T03 in the timing chart of FIG. 6, it is preferable that the potential be amplified by an amplifier (e.g., a sense amplifier) ​​located outside the amplifier circuit WRCA, and in particular, it is preferable that the amplifier be an amplifier capable of supplying a charge sufficient to rewrite the potential held by the sense amplifier LTSA in an active state.

[0236] When the transistors MN2 and MN3 are turned on, the potential V Ｌ The wiring BLB is supplied with a potential V Ｈ is given, the terminal IT of the sense amplifier LTSA is V Ｌ The terminal ITB of the sense amplifier LTSA is held at V Ｈ In addition, since the switch WSW2 is in the on state, the potentials of the wirings BL and WBL are V Ｌ The potential of the wiring BLB is V Ｈ Since the switch RSW2 is in the off state, the potential of the wiring RBL is VＰＲＥ =V Ｈ It remains unchanged.

[0237] In addition, the wiring WWL is connected to the V Ｈ Therefore, the node ND of the memory cell MC receives V from the wiring DBL via the wiring WBL and the wiring BL. Ｌ As a result, V is written to the memory cell MC as write data. Ｌ is written.

[0238] Then, V is connected to the wiring CSEL. Ｌ As a result, V is applied to the control terminal of the switch DSW (the gate of the transistor MN2) and the control terminal of the switch DBSW (the gate of the transistor MN3). Ｌ As a result, the transistor MN2 is turned off, causing a non-conduction state between the wiring BL and the wiring DBL, and the transistor MN3 is turned off, causing a non-conduction state between the wiring BLB and the wiring DBLB.

[0239] [Period T15] In period T15, the potential held by the sense amplifier LTSA is read, similarly to period T05 in the timing chart of Fig. 6. As described above, the active period of period T13 can be directly transitioned to period T15, and data can be read from the memory cell MC.

[0240] First, the wiring DBL and the wiring DBLB are V Ｈ is precharged to

[0241] Then, V is connected to the wiring CSEL. Ｈ At this time, the voltage V amplified by the sense amplifier LTSA is applied to the wiring DBL via the terminal IT and the wiring BL. Ｌ Also, V amplified by the sense amplifier LTSA is output to the line DBLB via the terminal ITB and the line BLB. Ｈ will be output.

[0242] When the wiring BLB and the wiring DBLB are brought into electrical continuity, charge is redistributed between the wiring BL and the wiring DBL. Since the switch SWS2 and the transistor MN11 are both on, the potentials of the wiring WBL and the node ND simultaneously become the same as the potential of the wiring BL. Therefore, the timing chart in FIG. 7 shows an example in which the potentials of the wiring BL, the wiring WBL, and the node ND are temporarily high. After that, the potentials of the wiring BL, the wiring DBL, and the node ND become V Ｌ On the other hand, the wiring BLB and the wiring DBLB are in a conductive state, but both the wiring BLB and the wiring DBLB are in a V Ｈ Therefore, potential fluctuation does not occur in either the wiring BLB or the wiring DBLB.

[0243] As a result, the line DBL receives the V Ｌ Also, V amplified by the sense amplifier LTSA is output to the line DBLB via the terminal ITB and the line BLB. Ｈ will be output.

[0244] In addition, according to the above operation, it is preferable that the potentials held in the sense amplifier LTSA be read after the potentials of the wirings BL and BLB are read to the wirings DBL and DBLB, respectively.

[0245] Then, V is connected to the wiring CSEL. Ｌ is applied to turn off the transistors MN2 and MN3, thereby bringing the wiring BL and the wiring DBL into a non-conductive state and the wiring BLB and the wiring DBLB into a non-conductive state.

[0246] In the period T15, similarly to the period T12, the potential of the wiring WWL is V Ｈ Therefore, the transistor MN11 is turned on, and data is rewritten (refreshed) to the memory cell MC as indicated by the potential fluctuations of the node ND and the wiring WBL.

[0247] [Period T16] During period T16, the data retention operation of the memory cell MC and the operation of putting the amplifier circuit WRC into an idle state are performed, similar to period T06 in the timing chart of Fig. 6. Note that in this specification, period T16 may also be referred to as a precharge period for transitioning to the idle state.

[0248] In the period T16, first, V Ｌ As a result, the gate of the transistor MN11 is supplied with V Ｌ As a result, the transistor MN11 is turned off, and the node ND receives the potential V Ｌ is maintained.

[0249] Next, V is connected to the wiring SWE. Ｌ is given, and V is applied to the wiring RE. Ｈ is given.

[0250] Wiring SWE to V Ｌ is applied, the sense amplifier LTSA is in an inactive state, similar to the period T06 in the timing chart of FIG.

[0251] Wiring RE to V Ｈ 6, the switch WSW1 is turned on. As a result, the potential V ＲＥＦ In addition, since the switch WSW2 is in an on state, the potential V ＲＥＦ is given.

[0252] In addition, the potential of the wiring RE is V Ｈ and the potential of the wiring REB is V Ｌ 6, the switch RSW2 is turned on, and the wiring RBL and the wiring BLB are electrically connected to each other. Also, because the switch RSW1 is turned on, the potential V ＰＲＥ (=V Ｈ ) is applied. Therefore, the potential of the wiring BLB is V ＰＲＥ (=VＨ )

[0253] By the operation during the period T16 described above, the amplifier circuit WRC can be set to the same idle state during the period T17 as during the period T11.

[0254] Note that in the period T16 in the timing chart of FIG. 7, the potentials of the wirings DBL and DBLB are set to, for example, V Ｌ However, since no read operation or write operation is performed in the period T16, the potentials of the wiring DBL and the wiring DBLB are not limited to this. The same applies to the period T17.

[0255] 7, in the same manner as in the period T02 in the timing chart of FIG. 6, data is rewritten (refreshed) to the memory cell MC in the period T12, so that the transistor MN11, which is the write transistor, is turned on in the read operation stage. At this time, the potential of the node ND of the memory cell MC is V Ｌ , the potentials of the wirings BL and WBL are V Ｌ Therefore, there is no change in the potential (retained data) at the node ND of the memory cell MC.

[0256] 7, data is rewritten (refreshed) to the memory cell MC in the period T12, so that the transistor MN11, which is a write transistor, can be turned on at an early stage. Therefore, as in the timing chart of FIG. 6, when data held in the memory cell MC is rewritten after the period T12 (when the period T14 is performed), the potentials of the wiring BL and the wiring WBL can be rewritten, thereby shortening the time required for the write operation.

[0257] Furthermore, in the operation of the timing chart of Figure 7, as in the timing chart of Figure 6, no through current is generated in the amplifier circuit WRC (because there is no timing when a conductive state occurs between the wiring that applies a high power supply potential and the wiring that applies a low power supply potential), so by using the amplifier circuit WRC, it is possible to reduce the power consumption associated with writing and reading data by the memory cell.

[0258] <<Operation Method Example 3>> The timing chart of Fig. 8 is a modified example of the operation of the timing chart of Fig. 7, and shows an example of the operation of the amplifier circuit WRCA and the memory cell MC during periods T21 to T27. Note that, unlike the timing chart of Fig. 7, the timing chart of Fig. 8 does not rewrite (refresh) data to the memory cell MC during the activation period of period T22, but instead during period T25, which will be described later. Specifically, in the timing chart of Fig. 8, the transmission of a selection signal to the memory cell MC to be written is performed during the same period as the transmission of data from the wiring DBL and the wiring DBLB.

[0259] Since the operation of the timing chart of Figure 8 is a modified example of the operation of the timing chart of Figure 7, in this example of the operation method, only the different parts will be explained, and for the rest, the explanation of the example of the operation method of the timing chart of Figure 7 can be referred to.

[0260] The period T22 is called an activate period, similar to the period T12 in the timing chart of Fig. 7. As described above, data is rewritten (refreshed) in the memory cell MC during the period T12 in the timing chart of Fig. 7, but this is not done during the period T22 in the timing chart of Fig. 8. In other words, during the period T22, the wiring WWL is supplied with a potential V Ｈ Instead, the potential V Ｌ Therefore, in the period T22, the transistor MN11 is in the off state, and there is no conduction between the wiring WBL and the node ND, so the potential of the node ND does not change in accordance with the change in the potential of the wiring WBL.

[0261] The period T23 is called an active period, similar to the period T13 in the timing chart of FIG.

[0262] During the period T24, the data write operation to the memory cell MC is performed in the same manner as during the period T14 in the timing chart of Fig. 7. In the operation of the timing chart of Fig. 8, during the period T24, V Ｈ is input, turning on the transistor MN11. Therefore, at this timing, conduction is established between the node ND and the wiring WBL and between the node ND and the wiring BL.

[0263] In addition, during the period T24, V Ｈ is applied to the wiring DBL, and the transistors MN2 and MN3 are turned on, thereby establishing electrical continuity between the wiring BL and the wiring DBL, and between the wiring BLB and the wiring DBLB. Ｌ is applied to the node ND via the wiring WBL and the wiring BL. Ｌ Further, a potential whose logic is inverted from that of the wiring DBL is input to the wiring DBLB. Ｈ is given.

[0264] During the period T25, the data is read from the memory cell MC in the same manner as during the period T15 in the timing chart of Fig. 7. Note that the read operation during the period T25 can be referred to the read operation during the period T15.

[0265] The period T26 is called a precharge period, similar to the period T16 in the timing chart of Fig. 7. For the operation during this period, the description of the period T16 in the timing chart of Fig. 7 can be referred to.

[0266] As described above, the timing chart of FIG. 8 differs from the operation of the period T12 of the timing chart of FIG. 7 in that data is not rewritten (refreshed) in the memory cells MC during the activation period of the period T22.

[0267] <<Operation Method Example 4>> The timing chart of Fig. 9 is a modified example of the operation of the timing chart of Fig. 8, and shows an example of the operation of the amplifier circuit WRCA and the memory cell MC in the period T31 to the period T36. Note that, unlike the timing chart of Fig. 8, the timing chart of Fig. 9 is an example of operation in which data is not rewritten in the memory cell MC but only reads data. Specifically, in the timing chart of Fig. 9, the wiring WWL is V Ｈ 9 differs from the timing chart of Fig. 8 in that there is no period in which the voltage Vcc is applied. Also, for this reason, in the operation of the timing chart of Fig. 9, data is not rewritten (refreshed) to the memory cells MC.

[0268] Since the operation of the timing chart of Figure 9 is a modified example of the operation of the timing chart of Figure 8, in this example of the operation method, only the different parts will be explained, and for the rest, the explanation of the example of the operation method of the timing chart of Figure 8 can be referred to.

[0269] The operations during the periods T31 and T32 can be similar to those during the periods T21 and T22 in the timing chart of Fig. 8. In particular, the period T32 is an activation period similar to the period T22.

[0270] The period T33 can be the same as the period T23 in the timing chart of Fig. 8. That is, the period T33 is an active period similar to the period T23.

[0271] The period T34 is a period during which a read operation is performed, similar to the period T25 in the timing chart of FIG.

[0272] The operations during the periods T35 and T36 can be similar to those during the periods T26 and T27 in the timing chart of Fig. 8. In particular, the period T35 is a precharge period similar to the period T26.

[0273] If there is no need to rewrite data in the memory cell MC, by performing the operation of the timing chart of Figure 9, the data rewrite operation to the memory cell MC (input of write data to the amplifier circuit WRCA) is eliminated, thereby shortening the time required for the operation method.

[0274] By using the amplifier circuit described in this embodiment, the time required for the operation method can be shortened. Furthermore, in this operation method, no through current flows between a wiring that applies a high power supply potential and a wiring that applies a low power supply potential, so that power consumption can be reduced. Furthermore, in the above-described operation method, the standby power can be reduced by omitting the active period, so that power consumption of the amplifier circuit can be further reduced.

[0275] Note that this embodiment mode can be appropriately combined with the same or other embodiment modes described in this specification. For example, the configuration, structure, method, etc. described in this embodiment mode can be appropriately combined with another configuration, structure, method, etc. described in this embodiment mode. Furthermore, for example, the configuration, structure, method, etc. described in this embodiment mode can be appropriately combined with the configuration, structure, method, etc. described in other embodiment modes.

[0276] Embodiment Mode 2 In this embodiment mode, a configuration example of a memory circuit including the memory cell MC, the amplifier circuit WRC, and the like described in the above embodiment modes will be described.

[0277] Fig. 10A shows a schematic perspective view illustrating a configuration example of the memory circuit MDV. Fig. 10B shows a block diagram illustrating a configuration example of the memory circuit MDV. The memory circuit MDV has a layer SS1 including a substrate 311 and a driver circuit region 50 formed on the substrate 311, and a layer SS2 including the memory cell 10. As shown in Fig. 10A, the layer SS2 can be provided above the layer SS1.

[0278] The substrate 311 may be, for example, a semiconductor substrate (e.g., a single-crystal substrate made of silicon or germanium). Other than semiconductor substrates, examples of materials that may be used include an SOI (Silicon-On-Insulator) substrate, a glass substrate, a quartz substrate, a plastic substrate, a sapphire glass substrate, a metal substrate, a stainless steel substrate, a substrate having stainless steel foil, a tungsten substrate, a substrate having tungsten foil, a flexible substrate, a laminated film, paper containing a fibrous material, or a base film. Examples of glass substrates include barium borosilicate glass, aluminoborosilicate glass, and soda-lime glass. Examples of flexible substrates, laminated films, and base films include plastics such as polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyethersulfone (PES), and polytetrafluoroethylene (PTFE). Another example is a synthetic resin such as acrylic. Other examples include polypropylene, polyester, polyvinyl fluoride, and polyvinyl chloride. Other examples include polyamide, polyimide, aramid, epoxy resin, inorganic vapor deposition film, and paper. If the manufacturing process of the memory circuit MDV includes heat treatment, it is preferable to select a material with high heat resistance for the substrate.

[0279] In this embodiment, the substrate 311 is described as a semiconductor substrate containing silicon.

[0280] The memory cell 10 shown in FIG. 10A can be the memory cell MC described in the first embodiment. The memory circuit MDV has a memory cell array MCA, which has a plurality of memory cells 10. In FIG. 10A , the memory cell array MCA has a plurality of memory cells 10 arranged in a matrix. In FIG. 10B , the memory cell array MCA has a memory cell 10[1,1], a memory cell 10[m,1] (where m is an integer of 1 or more), a memory cell 10[1,n] (where n is an integer of 1 or more), a memory cell 10[m,n], and a memory cell 10[i,j] (where i is an integer of 1 or more and m or less, and j is an integer of 1 or more and n or less) arranged.

[0281] 10A includes a PSW 22 (power switch), a PSW 23, and a peripheral circuit 31. The peripheral circuit 31 includes a peripheral circuit 41, a control circuit 32, and a voltage generating circuit 33.

[0282] In the memory circuit MDV, each circuit, each signal, and each voltage can be appropriately selected or omitted as needed. Alternatively, other circuits or other signals can be added. The signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are input signals from the outside, and the signal RDA is an output signal to the outside. The signal CLK is a clock signal.

[0283] Furthermore, signals BW, CE, and GW are control signals. Signal CE is a chip enable signal, signal GW is a global write enable signal, and signal BW is a byte write enable signal. Signal ADDR is an address signal. Signal WDA is write data, and signal RDA is read data. Signals PON1 and PON2 are power gating control signals. Signals PON1 and PON2 can be generated by the control circuit 32.

[0284] The control circuit 32 is a logic circuit that has the function of controlling the overall operation of the memory circuit MDV. For example, the control circuit performs a logical operation on the signals CE, GW, and BW to determine the operation mode (e.g., write operation or read operation) of the memory circuit MDV. Alternatively, the control circuit 32 generates a control signal for the peripheral circuit 41 so that this operation mode is executed.

[0285] The voltage generating circuit 33 has a function of generating a negative voltage. The signal WAKE has a function of controlling the input of the signal CLK to the voltage generating circuit 33. For example, when an H-level signal is applied to the signal WAKE, the signal CLK is input to the voltage generating circuit 33, and the voltage generating circuit 33 generates a negative voltage.

[0286] The peripheral circuit 41 is a circuit for writing and reading data to and from the memory cell 10. The peripheral circuit 41 includes a row decoder , a column decoder 44, a row driver 43, a column driver 45, an input circuit 47, and an output circuit .

[0287] The row decoder 42 and the column decoder 44 have the function of decoding the signal ADDR. The row decoder 42 is a circuit for specifying the row to be accessed, and the column decoder 44 is a circuit for specifying the column to be accessed. In other words, the row decoder 42 and the column decoder 44 are sometimes called selection circuits that select the memory cell 10 to be written to or read from.

[0288] The row driver 43 has a function of selecting the write and read word lines designated by the row decoder 42 .

[0289] The column driver 45 has a function of writing data to the memory cells 10, a function of reading data from the memory cells 10, and a function of holding the read data. Specifically, for example, as shown in Fig. 10A, the column driver 45 can be provided with a plurality of amplifier circuits 40 each having a function of reading data and a function of holding the read data. Note that the amplifier circuit 40 can be the amplifier circuit WRC described in the first embodiment.

[0290] The column driver 45 also has a function of selecting the write and read bit lines specified by the column decoder 44. Specifically, for example, the column decoder 44 can be connected to the wiring CSEL described in the first embodiment, which allows the column decoder 44 to select a column including the memory cell 10 to be written to or read from. Therefore, the switch DSW and the switch DBSW shown in FIG. 1 can be turned on, and the wiring WBL, which is the write bit line, and the wiring RBL, which is the read bit line of the column can be selected.

[0291] As described above, the column driver 45 contributes to the write operation on the memory cell 10, and therefore may be referred to as a write circuit that transmits write data to the memory cell 10. Similarly, the column driver 45 contributes to the read operation on the memory cell 10, and therefore may be referred to as a read circuit that reads read data from the memory cell 10.

[0292] The input circuit 47 has a function of holding a signal WDA. The data held by the input circuit 47 is output to the column driver 45. The output data of the input circuit 47 is data (Din) to be written to the memory cell 10. The data (Dout) read from the memory cell 10 is amplified by the amplifier circuit 40 included in the column driver 45 and output to the output circuit 48. The output circuit 48 has a function of holding Dout. In addition, the output circuit 48 has a function of outputting Dout to the outside of the memory circuit MDV. The data output from the output circuit 48 is a signal RDA.

[0293] PSW22 has a function of controlling the supply of VDD to the peripheral circuit 31. PSW23 has a function of controlling the supply of VHM to the row driver 43. In this example, the high power supply voltage of the memory circuit MDV is VDD, and the low power supply voltage is GND (ground potential). VHM is a high power supply voltage used to set the word line to a high level and is higher than VDD. Signal PON1 switches PSW22 between the ON and OFF states, and signal PON2 switches PSW23 between the ON and OFF states. In FIG. 10B, the number of power domains to which VDD is supplied in the peripheral circuit 31 is one, but multiple domains may also be used. In this case, it is preferable to provide a power switch for each power domain.

[0294] <Memory Cell Array and Peripheral Circuit> Next, the electrical connection between the memory cell array MCA and the peripheral circuit 41 will be described.

[0295] 11 is a block diagram showing an example of the configuration of a peripheral circuit 41 and a memory cell array MCA. As described above, the memory circuit MDV shown in FIG. 11 shows an example of the configuration in which the memory cell array MCA is provided above the peripheral circuit 41. In FIG. 11, the row decoder 42 and the row driver 43 are connected to the wirings WWL[1] to WWL[m] and the wirings RWL[1] to RWL[m].

[0296] The column decoder 44 is also connected to an amplifier circuit 40[j] and an amplifier circuit 40[j+1] (where j is an integer between 1 and n-1) included in the column driver 45. The amplifier circuit 40[j] is connected to the wiring WBL[j] and the wiring RBL[j], and the amplifier circuit 40[j+1] is connected to the wiring WBL[j+1] and the wiring RBL[j+1].

[0297] Note that the wirings WWL[1] to WWL[m] function as write word lines for the memory cell 10[i, j] as described in Embodiment 1. The wirings RWL[1] to RWL[m] function as read word lines for the memory cell 10[i, j] as described in Embodiment 1. The wirings WBL[j] and WBL[j+1] function as write bit lines for the memory cell 10[i, j] as described in Embodiment 1. The wirings RBL[j] and RBL[j+1] function as read bit lines for the memory cell 10[i, j] as described in Embodiment 1.

[0298] The memory cell 10[i,j] (not shown) arranged in the i-th row and j-th column is electrically connected to the wiring WWL[i], the wiring RWL[i], the wiring WBL[j], and the wiring RBL[j].

[0299] For each memory cell 10, the description of the memory cell MC in FIG. 4, FIG. 5A or FIG. 5B described in the first embodiment can be referred to.

[0300] 11, as an example, the amplifier circuits 40 are arranged in a matrix of 2n rows and 2 columns (where n is an even number). In the column driver 45, the amplifier circuit 40 in the first row functions as a write circuit or read circuit for the memory cells 10 in the odd-numbered rows of the memory cell array MCA, and the amplifier circuit 40 in the second row functions as a write circuit or read circuit for the memory cells 10 in the even-numbered rows of the memory cell array MCA.

[0301] As described above, the area of ​​the memory circuit can be reduced by providing the amplifier circuit WRC described in the first embodiment and the like in the driver circuit region 50 of the layer SS1 and providing the memory cell MC described in the first embodiment in the layer SS2. Furthermore, since the wiring connecting the memory cell MC and the amplifier circuit WRC can be shortened, the parasitic resistance can be reduced, thereby reducing power consumption.

[0302] <Cross-sectional Configuration Example of Memory Circuit> Next, a specific configuration example of the memory circuit MDV shown in Fig. 10A, Fig. 10B, and Fig. 11 will be described. Fig. 12 is a schematic cross-sectional view of an example of the memory circuit MDV shown in Fig. 10A, Fig. 10B, and Fig. 11.

[0303] 12 shows a schematic cross-sectional view of the layer SS1 and the memory layer SS2. Note that the memory circuit MDV in FIG. 12 shows a configuration in which the layer SS1 is formed directly on the layer SS1.

[0304] 12 illustrates a transistor 400 included in the layer SS1. The transistor 400 is provided over a substrate 311 and includes a conductive layer 316 functioning as a gate, insulating layers 315 and 317 functioning as gate insulating films, a semiconductor region 313 including part of the substrate 311, and low-resistance regions 314a and 314b functioning as source and drain regions including part of the substrate. A p-channel transistor or an n-channel transistor can be used as the transistor 400.

[0305] Here, in the transistor 400 shown in FIG. 12 , a semiconductor region 313 (a part of a substrate 311) where a channel is formed has a convex shape. A conductive layer 316 is provided to cover the side and top surfaces of the semiconductor region 313 with an insulating layer 315 interposed therebetween. Note that the conductive layer 316 can be made of a material that adjusts the work function. Such a transistor 400 is also called a fin-type transistor because it utilizes the convex portion of the semiconductor substrate. Note that one method for forming the convex portion is to form an insulating layer on the semiconductor substrate, which functions as a mask for forming the convex portion. While the case where the convex portion is formed by processing a part of the semiconductor substrate has been described, a semiconductor film having a convex shape can also be formed by processing an SOI substrate.

[0306] Note that the transistor 400 illustrated in FIG. 12 is just an example, and the structure is not limited thereto. An appropriate transistor can be used depending on the circuit configuration or driving method.

[0307] The structure of the transistor 400 can be applied to, for example, one or more of the transistors MN1 to MN9 or the transistors MP1 to MP8 described in Embodiment 1.

[0308] Furthermore, one or both of the layer SS1 and the layer SS2 may include a wiring layer provided with an interlayer film, wiring, and plugs. Furthermore, multiple wiring layers may be provided depending on the design. Furthermore, in this specification and the like, wiring and a plug connected to the wiring may be integrated. That is, there are cases where a part of a conductive layer functions as wiring, and cases where a part of a conductive layer functions as a plug.

[0309] For example, an insulating layer 320, an insulating layer 324, and an insulating layer 326 are stacked in this order as an interlayer film over the transistor 400. A conductive layer 328 and the like are embedded in the insulating layer 320. A conductive layer 330 and the like are embedded in the insulating layer 324 and the insulating layer 326. The conductive layer 328 and the conductive layer 330 function as contact plugs or wirings.

[0310] The insulating layer functioning as an interlayer film can also be used as a planarizing film that covers the underlying unevenness. For example, the top surface of the insulating layer 320 can be planarized by a planarization process using a chemical mechanical polishing (CMP) method to improve the planarity.

[0311] A wiring layer can be provided over the insulating layer 326 and the conductive layer 330. For example, in FIG. 12 , an insulating layer 350, an insulating layer 357, an insulating layer 352, and an insulating layer 354 are stacked in this order over the insulating layer 326 and the conductive layer 330. A conductive layer 356 is formed in the insulating layer 350, the insulating layer 357, and the insulating layer 352. The conductive layer 356 functions as a contact plug or a wiring.

[0312] An insulating layer 354 is provided on the insulating layer 352 and the conductive layer 356. Contact plugs or wiring can be embedded in the insulating layer 354 to connect to an upper circuit (e.g., a circuit included in layer SS2).

[0313] 12 also illustrates a memory cell 10 included in the layer SS2. Specifically, the memory cell MC includes a transistor MN11, a transistor MN12, and a capacitance element C1. The memory cell 10 may be the memory cell MC illustrated in FIG. 4 and described in the above embodiment.

[0314] 12, in layer SS2 of memory circuit MDV, transistor MN12 is formed on insulating layer STJ1. Transistor MN11 and capacitor C1 are formed on insulating layer STJ2. In addition, insulating layer STJ2 is located above insulating layer STJ1. Therefore, transistor MN11 and capacitor C1 are located above transistor MN12.

[0315] 12, the transistor MN12 is provided to have one fin-shaped semiconductor layer SC1. Specifically, the gate insulating film and gate electrode of the transistor M2 are formed to overlap one of two regions of the one fin-shaped semiconductor layer SC1.

[0316] A conductive layer functioning as a wiring RWL is connected to one of the source electrode or drain electrode of the transistor MN12. A conductive layer functioning as a wiring RBL is connected to the other of the source electrode or drain electrode of the transistor MN12. The wiring RWL and the wiring RBL are, for example, extended in the channel width direction of the transistor M2. The conductive layer functioning as the wiring RWL is formed so as to overlap the fin-shaped semiconductor layer SC1, and the conductive layer functioning as the wiring RBL is formed so as to overlap the fin-shaped semiconductor layer SC1.

[0317] The transistor MN12 is also provided with a conductive layer MEG that functions as a gate electrode. In particular, the conductive layer MEG is provided so as to overlap the fin-shaped semiconductor layer SC1.

[0318] An insulating layer functioning as an interlayer film is formed between the transistor MN12 and the transistor MN11. An opening is provided in the insulating layer in a region overlapping with the conductive layer MEG of the transistor MN12, and a conductive layer is embedded in the opening. The conductive layer is connected to one of the source electrode and the drain electrode of the transistor MN11. The conductive layer MEG can be part of the node ND shown in FIG. 5 described in the first embodiment.

[0319] As described above, the transistor MN11 is located above the transistor MN12. The transistor MN11 also has a partial region of the fin-shaped semiconductor layer SC2. In addition, an insulating layer region that functions as the dielectric of the capacitance element C1 is formed in a partial region of the conductive layer that functions as one of the source electrode or drain electrode of the transistor MN11, and a conductive layer that functions as the second terminal of the capacitance element C1 is formed in the insulating layer region. The conductive layer functions as the wiring VGE.

[0320] The gate insulating film and gate electrode of the transistor MN11 are formed so as to overlap a portion of the fin-shaped semiconductor layer SC2 of the transistor MN11. In particular, the conductive layer serving as the gate electrode of the transistor MN11 extends in the channel width direction. This conductive layer also functions as the wiring WWL.

[0321] 12, a conductive layer functioning as a back gate can be provided below the insulating layer STJ2 in the transistor MN11. Similarly, a conductive layer functioning as a back gate can be provided below the insulating layer STJ1 in the transistor MN12. By providing a back gate in each transistor and changing the potential of the back gate, the threshold voltage of the transistor can be changed.

[0322] For example, by using a transistor with a back gate as the transistor MN11, the influence of an external electric field can be reduced and the transistor MN11 can be stably maintained in an off state. Therefore, data written to the first terminal of the capacitance element C1 can be stably held. By providing a back gate, the operation of the memory cell 10 can be stabilized and the reliability of the layer SS2 including the memory cell MC can be improved.

[0323] The semiconductor layers in which the channels of the transistors MN11 and MN12 are formed can be made of a single crystal semiconductor, a polycrystalline semiconductor, a microcrystalline semiconductor, an amorphous semiconductor, or a combination of two or more of these. Examples of the semiconductor material include silicon and germanium. Other examples include compound semiconductors such as silicon germanium, silicon carbide, gallium arsenide, oxide semiconductors, and nitride semiconductors.

[0324] Note that the transistors MN11 and MN12 are preferably transistors (OS transistors) that use an oxide semiconductor, which is a type of metal oxide, in a semiconductor layer in which a channel is formed. The band gap of an oxide semiconductor is 2 eV or more, and therefore the off-state current is significantly small. Therefore, the power consumption of the memory cell MC can be reduced. Therefore, the power consumption of the memory circuit MDV including the memory cell 10 can be reduced.

[0325] A memory cell including an OS transistor can be called an “OS memory.” A memory circuit MDV including the memory cell can also be called an “OS memory.”

[0326] Furthermore, the OS transistor operates stably even in a high-temperature environment, and its characteristics fluctuate little. For example, the off-state current hardly increases even in a high-temperature environment. Specifically, the off-state current hardly increases even in an environment of room temperature or higher and 200° C. or lower. Furthermore, the on-state current hardly decreases even in a high-temperature environment. Therefore, the OS memory operates stably even in a high-temperature environment, and high reliability is achieved.

[0327] 13A and 13B are schematic perspective views of an example of the transistor MN12. Note that some insulating layers and some conductive layers are omitted from the schematic perspective views of Fig. 13A and Fig. 13B. In particular, the schematic perspective view of Fig. 13B omits the wiring RWL and wiring WBL from the schematic perspective view of Fig. 13A.

[0328] 13A and 13B show two fin-shaped semiconductor layers SC1 each having a rectangular opening. Therefore, the semiconductor layer SC3 can be said to have a circumferential and fin-shaped structure. The opening shape can be rectangular or a closed curve.

[0329] As shown in Figures 13A and 13B, the wiring RWL, the conductive layer MEG, and the wiring WBL are formed so as to overlap with part of the side surfaces of the two fin-shaped semiconductor layers SC1. In this way, the conductive layer MEG is used to surround the semiconductor layer SC3 in which the channel is formed via a gate insulating film, thereby forming the transistor MN12. This also prevents electric fields generated outside the transistor MN12 from acting on the semiconductor in which the channel is formed. In other words, an electrostatic shielding function against static electricity can be added to the transistor MN12. This prevents fluctuations in the electrical characteristics of the transistor due to the influence of external electric fields such as static electricity.

[0330] <<Configuration Example of Transistor>> Next, the structures of the transistors MN11 and MN12 used in the schematic cross-sectional view of FIG. 12 will be described.

[0331] 14A to 14D are schematic plan views and schematic cross-sectional views showing the structure of a transistor 500mf that includes two fin-shaped, circumferentially shaped semiconductor layers, similar to the above-described transistors MN11 and MN12.

[0332] Fig. 14A is a schematic plan view of a transistor 500mf applicable to each of transistors MN11 and MN12 of the memory circuit MDV of Fig. 12, and Figs. 14B to 14D are schematic cross-sectional views of the transistor 500mf. In particular, Fig. 14B is a schematic cross-sectional view of the portion indicated by dashed-dotted line A1-A2 in Fig. 14A, and is also a schematic cross-sectional view of the transistor 500mf in the channel width direction. Fig. 14C is a schematic cross-sectional view of the portion indicated by dashed-dotted line A3-A4 in Fig. 14A, and is also a schematic cross-sectional view of the transistor 500mf in the channel width direction. Fig. 14D is a schematic cross-sectional view of the portion indicated by dashed-dotted line A5-A6 in Fig. 14A, and is also a schematic cross-sectional view of the transistor 500mf in the channel length direction. Here, the dashed-dotted line A5-A6 is perpendicular to the dashed-dotted line A1-A2 and the dashed-dotted line A3-A4, and the dashed-dotted line A1-A2 and the dashed-dotted line A3-A4 are parallel to each other. Note that in the schematic plan view of FIG. 14A, some elements are omitted for clarity, and some elements are shown transparently. FIG. 15A shows an enlarged view of the vicinity of the conductive layer 560 in FIG. 14D. FIG. 15B shows an enlarged view of the vicinity of the semiconductor layer 530 in FIG. 14B. FIG. 15C shows an enlarged view of the vicinity of the semiconductor layer 530 in FIG. 14C.

[0333] The transistor 500mf includes an insulating layer 516 over the insulating layer 514, an insulating layer 521 over the insulating layer 516, an insulating layer 522 over the insulating layer 521, a semiconductor layer 530 over the insulating layer 522, conductive layers 542a and 542b over the semiconductor layer 530 and the insulating layer 522, an insulating layer 550 over the semiconductor layer 530, and a conductive layer 560 (conductive layer 560a and conductive layer 560b) over the insulating layer 550. Note that hereinafter, the conductive layer 542a and the conductive layer 542b may be collectively referred to as the conductive layer 542.

[0334] An insulating layer 575 is provided over the conductive layer 542, and an insulating layer 580 is provided over the insulating layer 575. The insulating layer 550 and the conductive layer 560 are disposed inside openings provided in the insulating layer 580 and the insulating layer 575. The openings reach the semiconductor layer 530, and the insulating layer 550 is in contact with the semiconductor layer 530 within the openings. An insulating layer 582 is provided over the insulating layer 580 and the conductive layer 560. An insulating layer 583 is provided over the insulating layer 582.

[0335] An insulating layer 541a is provided in contact with the inner wall of an opening of the insulating layer 580 or the like, and a conductive layer 540a is provided in contact with the side surface of the insulating layer 541a. The bottom surface of the conductive layer 540a is in contact with the top surface of the conductive layer 542a. An insulating layer 541b is provided in contact with the inner wall of an opening of the insulating layer 580 or the like, and a conductive layer 540b is provided in contact with the side surface of the insulating layer 541b. The bottom surface of the conductive layer 540b is in contact with the top surface of the conductive layer 542b. Note that hereinafter, the conductive layers 540a and 540b may be collectively referred to as the conductive layer 540. The insulating layers 541a and 541b may be collectively referred to as the insulating layer 541.

[0336] For the insulating layers 541 a and 541 b, an insulating film having a function of suppressing oxygen permeation is preferably used to prevent a decrease in conductivity due to oxidation of the conductive layers 542 a and 542 b. For example, a silicon nitride film is preferably formed by a plasma-enhanced atomic layer deposition (PEALD) method.

[0337] The insulating layer 516, like the insulating layer 320, functions as a planarizing film that flattens steps caused by plugs and the like. For this reason, the insulating layer 516 can be made of a material that functions as a planarizing film like the insulating layer 320. Furthermore, by using a material with a low dielectric constant for the insulating layer 516, the parasitic capacitance between wirings can be reduced. From the above, the insulating layer 516 can be made of, for example, a material that can be used for the insulating layer IS1 described below.

[0338] For the insulating layers 521 and 522, it is preferable to use an insulating layer having a barrier property against one or more selected from hydrogen, oxygen, and water, similar to the insulating layers 324 and 350. Therefore, for the insulating layers 521 and 522, it is preferable to use an insulating layer having a barrier property against one or more selected from hydrogen, oxygen, and water, similar to the insulating layers 324 and 350.

[0339] The semiconductor layer 530 has a region that functions as a channel formation region of the transistor 500mf. The conductive layer 560 has a region that functions as a first gate electrode (upper gate electrode) of the transistor 500mf. The insulating layer 550 has a region that functions as a first gate insulating film of the transistor 500mf.

[0340] In particular, a metal oxide functioning as an oxide semiconductor can be used for the semiconductor layer 530. In this case, the transistor 500mf is an OS transistor. Note that the semiconductor layer 530 corresponds to the semiconductor layer SC1 or SC2 described above.

[0341] An axial growth CAAC (AG CAAC) oxide semiconductor can be used for the semiconductor layer 530. The AG CAAC refers to an oxide semiconductor having a CAAC structure, which is produced in an oxide semiconductor layer including a first layer and a second layer having higher crystallinity than the first layer by solid-phase growth of a metal oxide included in the first layer using the second layer as a nucleus or seed.

[0342] For example, the first layer is preferably formed by atomic layer deposition (ALD) or chemical vapor deposition (CVD). Examples of CVD include plasma enhanced CVD (PECVD), thermal CVD, photo-assisted CVD, and metal organic CVD (MOCVD). The first layer may be formed by a wet process. Alternatively, the first layer may be formed by molecular beam epitaxy (MBE), which is a film formation method for growing a thin film having a crystal structure that reflects the crystal system of the substrate. These film forming methods can cause less damage to the surface on which the film is formed than sputtering methods.

[0343] Next, the second layer is preferably formed by sputtering or pulsed laser deposition (PLD). By forming the second layer after the first layer, in particular, it is possible to prevent a mixed layer from being formed at the interface between the first and second layers. Furthermore, it is possible to prevent impurities contained in the surface on which the second layer is formed from being mixed into the second layer. These factors further enhance the crystallinity of the second layer.

[0344] In addition, methods for solid-phase growth of the metal oxide contained in the first layer using the second layer as a nucleus or seed include, for example, heat treatment, plasma treatment, microwave (typically 2.45 GHz) treatment, microwave plasma treatment, and light (e.g., ultraviolet light) irradiation treatment. Note that several of these treatments can be performed simultaneously or sequentially. For example, heat treatment and microwave plasma treatment can be performed simultaneously. Alternatively, microwave plasma treatment can be performed after heat treatment.

[0345] In this specification, microwaves refer to electromagnetic waves having a frequency of 300 MHz to 300 GHz. Microwave plasma treatment refers to treatment using a device with a power source that generates high-density plasma using microwaves. Microwave plasma treatment can also be called microwave-excited high-density plasma treatment.

[0346] Furthermore, it is more preferable to perform the treatment for increasing the crystallinity of the oxide semiconductor layer multiple times during the formation of the oxide semiconductor layer. For example, when the oxide semiconductor layer is formed by an ALD method, it is preferable to perform a microwave plasma treatment every time an atomic layer is formed. Alternatively, it is preferable to perform a treatment for increasing the crystallinity every time an oxide semiconductor layer having a thickness within a predetermined range is formed, in order to increase productivity. Specifically, it is preferable to form a first oxide semiconductor layer having a thickness of 1 nm to 10 nm, perform the first microwave plasma treatment, and then form a second oxide semiconductor layer having a thickness of 1 nm to 10 nm, and perform the second microwave plasma treatment. Note that the method for forming the first oxide semiconductor layer and the second oxide semiconductor layer is not particularly limited, and ALD or sputtering can be used, respectively. In particular, forming the first oxide semiconductor layer by an ALD method is preferable because it can prevent elements of the layers constituting the formation surface from being mixed (also referred to as mixing) into the first oxide semiconductor layer and the second oxide semiconductor layer. This is particularly suitable when the element contained in the layer constituting the formation surface inhibits crystallization of the oxide semiconductor (for example, when silicon, carbon, or the like is contained). The first oxide semiconductor layer and the second oxide semiconductor layer can have different compositions. Although a stacked structure of the first oxide semiconductor layer and the second oxide semiconductor layer is illustrated here, the present invention is not limited to this. The same treatment can be applied to a single oxide semiconductor layer or a stacked structure of three or more layers.

[0347] Treatment for increasing the crystallinity of the oxide semiconductor layer can be performed after the oxide semiconductor layer is formed. Specifically, the treatment can be performed directly on the formed oxide semiconductor layer or through another film such as an insulating film formed on the oxide semiconductor layer. For example, microwave plasma treatment can be performed after the oxide semiconductor layer is formed, or an insulating film (e.g., a silicon nitride film, a silicon oxide film, or an aluminum oxide film) can be formed after the oxide semiconductor layer is formed, and then heat treatment or microwave plasma treatment can be performed on the oxide semiconductor layer through the insulating film.

[0348] Note that the treatment for increasing the crystallinity of the oxide semiconductor layer can also serve as treatment for removing impurities contained in the oxide semiconductor layer. For example, carbon, hydrogen, nitrogen, and the like contained in the oxide semiconductor layer can be preferably removed. Alternatively, by performing the treatment for increasing the crystallinity of the oxide semiconductor layer in an oxygen gas atmosphere, oxygen vacancies in the oxide semiconductor layer can be reduced.

[0349] When the treatment for increasing the crystallinity of the oxide semiconductor layer is performed, the temperature of the substrate is preferably room temperature or higher, 100° C. or higher and 600° C. or lower, or 300° C. or higher and 450° C. The temperature of the heat treatment is preferably 100° C. or higher and 700° C. or lower, or 300° C. or higher and 450° C.

[0350] In addition to the above-described method for forming an oxide semiconductor layer, treatment for increasing the crystallinity of the oxide semiconductor layer can be performed, whereby a highly reliable transistor can be provided.

[0351] 15B, the semiconductor layer 530 can have a structure including a semiconductor layer 530a, a semiconductor layer 530b in contact with the semiconductor layer 530a, and a semiconductor layer 530c in contact with the semiconductor layer 530b. In addition, the side surfaces of the semiconductor layer 530 (the semiconductor layers 530a to 530c) are preferably perpendicular or approximately perpendicular to the substrate surface.

[0352] As described above, in the cross section of the semiconductor layer 530 (semiconductor layers 530a to 530c) observed using a TEM image, it is confirmed that metal atoms are arranged in layers in a direction parallel to or substantially parallel to the formation surface. In other words, in the cross section of the semiconductor layer 530 (semiconductor layers 530a to 530c) observed using a TEM image, it is confirmed that metal atoms are arranged in layers in a direction perpendicular to or substantially perpendicular to the substrate surface. It can also be said that the c-axis of AG CAAC is substantially parallel to the normal direction to the side surface of the semiconductor layer 530.

[0353] In this way, by using the semiconductor layer 530 made of AG CAAC in the channel formation region of the transistor 500mf, a transistor with large on-state current, high field-effect mobility, a good S value, high frequency characteristics, and good reliability can be provided. Note that the S value is a subthreshold swing value, which indicates the amount of change in gate voltage in the subthreshold region required to change the drain current by one order of magnitude at a constant drain voltage. The smaller the S value, the steeper the slope of the drain current with respect to the gate voltage, resulting in better switching characteristics.

[0354] The semiconductor layers 530a to 530c can be formed, for example, by providing a pillar that functions as a sacrificial layer on the insulating layer 522, depositing a first semiconductor film that will become the semiconductor layer 530a, a second semiconductor film that will become the semiconductor layer 530b, and a third semiconductor film that will become the semiconductor layer 530c on the side surfaces of the pillar in this order, removing the first to third semiconductor films located on the top surfaces of the insulating layer 522 and the pillars, and then removing the pillars.

[0355] Furthermore, when the semiconductor layer 530 has a three-layer structure of semiconductor layers 530a to 530c as described above, the semiconductor layer 530 is formed in the order of semiconductor layer 530a, semiconductor layer 530b, and semiconductor layer 530c, with the region where the pillars were formed at the center. In other words, as shown in Fig. 14A, the semiconductor layer 530 has a structure that surrounds the region where the pillars were formed in plan view.

[0356] A channel formation region and a source region and a drain region sandwiching the channel formation region are formed in the semiconductor layer 530. At least a part of the channel formation region overlaps with the conductive layer 560. The source region overlaps with the conductive layer 542a, and the drain region overlaps with the conductive layer 542b. Note that the source region and the drain region can be interchanged.

[0357] The channel formation region has fewer oxygen vacancies or a lower impurity concentration than the source and drain regions, and is therefore a high-resistance region with a low carrier concentration. Therefore, the channel formation region can be said to be i-type (intrinsic) or substantially i-type.

[0358] The source and drain regions are low-resistance regions with high carrier concentrations due to a large number of oxygen vacancies or high concentrations of impurities such as hydrogen, nitrogen, and metal elements. That is, the source and drain regions are n-type regions (low-resistance regions) with a higher carrier concentration than the channel formation region.

[0359] The carrier concentration in the channel formation region is 1×10 １８ cm −３ Below, 1 x 10 １７ cm −３ Less than 1 x 10 １６ cm −３ Less than 1 x 10 １５ cm −３ Less than 1 x 10 １４ cm −３ Less than 1 x 10 １３ cm −３ Less than 1 x 10 １２ cm −３ Less than 1 x 10 １１ cm −３ Less than or 1 x 10 １０ cm −３ The lower limit of the carrier concentration in the channel formation region is not particularly limited, but is preferably less than 1×10 −９ cm −３ It can be said that:

[0360] Note that when the carrier concentration of the semiconductor layer 530 is reduced, the impurity concentration in the semiconductor layer 530 is reduced to reduce the density of defect states. In this specification and the like, a low impurity concentration and a low density of defect states are referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor (or metal oxide). Note that an oxide semiconductor (or metal oxide) with a low carrier concentration may be referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor (or metal oxide).

[0361] In order to stabilize the electrical characteristics of the transistor 500mf, it is effective to reduce the impurity concentration in the channel formation region in the semiconductor layer 530. Furthermore, in order to reduce the impurity concentration in the semiconductor layer 530, it is preferable to also reduce the impurity concentration in adjacent films. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon. Note that the impurities in the semiconductor layer 530 refer to, for example, elements other than the main components constituting the semiconductor layer 530. For example, an element with a concentration of less than 0.1 atomic % can be considered an impurity.

[0362] Furthermore, it may be difficult to clearly detect the boundaries between regions in the semiconductor layer 530. The concentrations of metal elements and impurity elements such as hydrogen and nitrogen detected in each region may not only vary stepwise from region to region but also vary continuously within each region. That is, the concentrations of metal elements and impurity elements such as hydrogen and nitrogen may decrease in a region closer to the channel formation region.

[0363] In a transistor using an oxide semiconductor for the semiconductor layer 530, impurities and oxygen vacancies are present in a region where a channel is formed in the oxide semiconductor, and the transistor's electrical characteristics are likely to fluctuate, which may result in poor reliability. Ｏ H) and generate electrons that serve as carriers. Therefore, if oxygen vacancies are present in the channel formation region of the oxide semiconductor, the transistor is likely to be normally on. Therefore, in the channel formation region of the oxide semiconductor, impurities, oxygen vacancies, and V ＯIt is preferable that H be reduced as much as possible. In other words, it is preferable that the carrier concentration of a channel formation region in the oxide semiconductor be reduced and that the channel formation region be i-type (intrinsic) or substantially i-type.

[0364] In response to this problem, an insulating layer containing oxygen that is released by heating (hereinafter may be referred to as excess oxygen) is provided near the oxide semiconductor, and heat treatment is performed. This allows oxygen to be supplied from the insulating layer to the oxide semiconductor, thereby eliminating oxygen vacancies and V Ｏ H can be reduced. However, if an excessive amount of oxygen is supplied to the source region or drain region, the on-state current or field-effect mobility of the transistor 500 mf may decrease. Furthermore, variations in the amount of oxygen supplied to the source region or drain region within the substrate surface may cause variations in the characteristics of a semiconductor device including the transistor. Furthermore, if oxygen supplied from the insulating layer to the oxide semiconductor diffuses into a conductive layer such as a gate electrode, a source electrode, or a drain electrode, the conductive layer may be oxidized, resulting in a loss of conductivity, which may adversely affect the electrical characteristics and reliability of the transistor.

[0365] Therefore, in the oxide semiconductor, the channel formation region preferably has a reduced carrier concentration and is i-type or substantially i-type, and the source and drain regions preferably have a high carrier concentration and are n-type. Ｏ It is also preferable to prevent an excessive amount of oxygen from being supplied to the source and drain regions, and to reduce V Ｏ It is preferable to prevent the amount of H from being reduced excessively. Furthermore, it is preferable to have a structure that suppresses a decrease in the conductivity of the conductive layer 560, the conductive layer 542a, the conductive layer 542b, and the like. For example, it is preferable to have a structure that suppresses oxidation of the conductive layer 560, the conductive layer 542a, the conductive layer 542b, and the like. Note that hydrogen in the oxide semiconductor is converted into V Ｏ H can be formed, so V Ｏ To reduce the amount of H, it is necessary to reduce the hydrogen concentration.

[0366] 15B , the insulating layer 550 includes an insulating layer 550a, an insulating layer 550b, an insulating layer 550c, and an insulating layer 550d. The insulating layers 550a to 550d function as part of a first gate insulating film. The insulating layers 550a to 550d are provided in an opening formed in the insulating layer 580, similar to the conductive layer 560 described later. To miniaturize the transistor 500mf, the insulating layers 550a to 550d are preferably thin. The thicknesses of the insulating layers 550a to 550d are preferably 0.1 nm to 10 nm, more preferably 0.1 nm to 5.0 nm, more preferably 0.5 nm to 5.0 nm, still more preferably 1.0 nm to less than 5.0 nm, and even more preferably 1.0 nm to 3.0 nm. Note that each of the insulating layers 550a to 550d preferably has a region with the above-described thickness in at least a part thereof.

[0367] The thickness of the silicon oxide film used as the insulating layer 550 is preferably 0.7 nm to 3 nm.

[0368] In order to thin the insulating layers 550a to 550d as described above, it is preferable to form the insulating layers 550a to 550d by an ALD method. Furthermore, it is preferable to form the insulating layers 550a to 550d in openings in the insulating layer 580 or the like by an ALD method. Examples of the ALD method include a thermal ALD method in which a precursor and a reactant are reacted using only thermal energy, and a PEALD method in which a plasma-excited reactant is used. The PEALD method may be preferable because it enables film formation at a lower temperature by using plasma.

[0369] The ALD method can deposit atoms layer by layer, and therefore has the following advantages: it is possible to form an extremely thin film, it is possible to form a film on a structure with a high aspect ratio, it is possible to form a film with few defects such as pinholes, it is possible to form a film with excellent coverage, it is possible to form a film at a low temperature, etc. Therefore, the insulating layer 550 can be formed with good coverage on the side surface of the opening formed in the insulating layer 580 and with the thin film thickness as described above.

[0370] Note that some precursors used in the ALD method contain carbon and the like. Therefore, films formed by the ALD method may contain more impurities such as carbon than films formed by other film formation methods. Note that the quantity of impurities can be determined using secondary ion mass spectrometry (SIMS), X-ray photoelectron spectroscopy (XPS), or Auger electron spectroscopy (AES).

[0371] Although the insulating layer 550 has been described above as having a four-layer structure of insulating layers 550a to 550d, the present invention is not limited to this. The insulating layer 550 may have a structure including at least one of the insulating layers 550a to 550d. By forming the insulating layer 550 using one, two, or three of the insulating layers 550a to 550d, the manufacturing process of the semiconductor device can be simplified and productivity can be improved.

[0372] For example, the insulating layer 550 may have a three-layer structure. In this case, it is preferable that the insulating layer 550 has a laminated structure of an insulating layer 550a, an insulating layer 550b on the insulating layer 550a, and an insulating layer 550c on the insulating layer 550b. In other words, this is the same as the structure shown in FIG. 15A except that the insulating layer 550d is removed.

[0373] It is preferable to use the ALD process two or more times in forming the insulating layer 550. For example, the insulating layer 550 preferably has a stacked structure of a plurality of insulating films, and it is preferable that two or more of the plurality of insulating films are formed using the ALD process. By forming at least two or more insulating films using the ALD process, it is possible to improve the coverage and film thickness uniformity of the insulating layer 550. Furthermore, it is possible to increase productivity by successively forming two or more different films, for example, two or more insulating films, using the ALD process.

[0374] For example, the insulating layer 550a is preferably made of aluminum oxide, which has a high ability to capture or fix hydrogen. The insulating layer 550b is preferably made of silicon oxide, which has a high dielectric strength. The insulating layer 550c is preferably made of hafnium oxide, which has a high ability to capture or fix hydrogen. The insulating layer 550d is preferably made of silicon nitride, which has a high hydrogen barrier property.

[0375] 14D and other figures show the conductive layer 560 as having a two-layer structure. Here, the conductive layer 560 preferably includes a conductive layer 560a and a conductive layer 560b disposed on the conductive layer 560a. For example, the conductive layer 560a is preferably disposed so as to surround the bottom and side surfaces of the conductive layer 560b. In this case, the conductive layer 560a is preferably made of a conductive material that is resistant to oxidation or a conductive material that has the function of suppressing oxygen diffusion.

[0376] The conductive layer 560a is preferably made of a conductive material that has a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, copper atoms, etc. Alternatively, it is preferably made of a conductive material that has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules).

[0377] Furthermore, since the conductive layer 560a has a function of suppressing oxygen diffusion, it is possible to suppress a decrease in conductivity due to oxidation of the conductive layer 560b caused by oxygen contained in the insulating layer 580, etc. As a conductive material having a function of suppressing oxygen diffusion, for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, ruthenium oxide, or the like is preferably used.

[0378] The conductive layer 560b is preferably a conductive layer with high conductivity. For example, the conductive layer 560b can be formed using a conductive material containing tungsten, copper, or aluminum as a main component. The conductive layer 560b may have a stacked structure, for example, a stacked structure of titanium or titanium nitride and the above-mentioned conductive material.

[0379] In the transistor 500mf, the conductive layer 560 is formed in a self-aligned manner to fill an opening formed in the insulating layer 580 or the like. Here, the side surfaces of the insulating layer 580 in the openings coincide or substantially coincide with the side surfaces of the conductive layers 542a and 542b. Therefore, the conductive layer 560 can be arranged to overlap the region between the conductive layers 542a and 542b without alignment.

[0380] The conductive layer 542a has a region functioning as one of the source electrode and drain electrode of the transistor 500mf. The conductive layer 540a functions as a plug connected to the conductive layer 542a. The conductive layer 542b has a region functioning as the other of the source electrode and drain electrode of the transistor 500mf. The conductive layer 540b functions as a plug connected to the conductive layer 542b.

[0381] For the conductive layers 542a and 542b, it is preferable to use, for example, a conductive material that is resistant to oxidation or a conductive material that has a function of suppressing oxygen diffusion. Examples of such conductive materials include a conductive material containing nitrogen and a conductive material containing oxygen. This can suppress a decrease in the conductivity of the conductive layers 542a and 542b. When a conductive material containing metal and nitrogen is used for the conductive layers 542a and 542b, the conductive layers 542a and 542b become conductive layers containing at least metal and nitrogen. For example, a conductive material that is resistant to oxidation or a conductive material that has a function of suppressing oxygen diffusion can be selected from the materials that can be used for the conductive layer 560 described above.

[0382] The conductive layers 540a and 540b are preferably made of a conductive material containing, for example, tungsten, copper, or aluminum as a main component. The conductive layer 540 may have a layered structure in which a first conductive layer is provided in contact with the side surface of the insulating layer 541 and a second conductive layer is provided further inside. In this case, the above-described conductive material may be used as the second conductive layer. The conductive layers 540a and 540b may be made of any of the materials applicable to the conductive layer 560 described above. Here, the first conductive layer corresponds to the conductive layer 540a1 shown in FIG. 15A , and the second conductive layer corresponds to the conductive layer 540a2 shown in FIG. 15A .

[0383] Furthermore, when the conductive layer 540 has a stacked structure, a first conductive layer disposed near the insulating layer 583, the insulating layer 582, the insulating layer 580, and the insulating layer 575 is preferably formed using a conductive material having a function of suppressing the permeation of impurities such as water and hydrogen. For example, tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium oxide, or the like is preferably used. Furthermore, a conductive material having a function of suppressing the permeation of impurities such as water and hydrogen can be used in a single layer or a stacked layer. With such a structure, impurities such as water and hydrogen contained in layers above the insulating layer 583 can be prevented from entering the semiconductor layer 530 through the conductive layer 540a and the conductive layer 540b.

[0384] For example, the insulating layer 575 is preferably a barrier insulating film against oxygen. Examples of the barrier insulating film against oxygen include oxides containing one or both of aluminum and hafnium, magnesium oxide, gallium oxide, silicon nitride, and silicon nitride oxide. Examples of oxides containing one or both of aluminum and hafnium include aluminum oxide, hafnium oxide, oxides containing aluminum and hafnium (hafnium aluminate), and oxides containing hafnium and silicon (hafnium silicate).

[0385] For example, the insulating layer 580 preferably has a lower dielectric constant than the insulating layer 522. By using a material with a low dielectric constant as an interlayer film, parasitic capacitance occurring between wirings can be reduced. For this reason, the insulating layer 580 preferably uses, as a material with a low dielectric constant, one or more of silicon oxide, silicon oxynitride, silicon oxide to which fluorine has been added, silicon oxide to which carbon has been added, silicon oxide to which carbon and nitrogen have been added, and silicon oxide having vacancies.

[0386] In particular, silicon oxide and silicon oxynitride are preferred because they are thermally stable. In particular, materials such as silicon oxide, silicon oxynitride, and silicon oxide having vacancies are preferred because they can easily form regions containing oxygen that is desorbed by heating.

[0387] The top surfaces of the insulating layers 580 are preferably planarized, so that the insulating layers 580 also preferably function as planarization films.

[0388] As described above, the insulating layer 580 can be formed using a material similar to that of the insulating layer 516 .

[0389] One or both of the insulating layers 582 and 583 preferably function as a barrier insulating layer that suppresses diffusion of oxygen from above the insulating layers 582 and 583 to the transistor 500mf or the like. Therefore, one or both of the insulating layers 582 and 583 can be resistant to hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N ２ O, NO, NO ２ It is preferable to have an insulating material that has a function of suppressing the diffusion of impurities such as copper atoms (i.e., the impurities are less likely to permeate), or that has a function of suppressing the diffusion of oxygen (i.e., the oxygen is less likely to permeate).

[0390] The insulating layers 582 and 583 preferably have an insulating layer that has a function of suppressing the diffusion of impurities such as water and hydrogen, and oxygen, and can be made of, for example, aluminum oxide, magnesium oxide, hafnium oxide, zirconium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), an oxide containing hafnium and zirconium (hafnium zirconium oxide), gallium oxide, silicon nitride, or silicon nitride oxide. For example, the insulating layer 583 is preferably made of silicon nitride, which has a higher hydrogen barrier property. For example, the insulating layer 582 is preferably made of aluminum oxide, which has a high ability to capture or fix hydrogen.

[0391] The semiconductor layer 530 is formed on and in contact with the insulating layer 522. As shown in Figures 15B and 15C, the semiconductor layer 530 has a shape with a high aspect ratio when viewed cross-sectionally in the channel width direction. For this reason, the semiconductor layer 530 can also be said to have a fin-like shape.

[0392] Here, the aspect ratio of the semiconductor layer 530 in a cross-sectional view in the channel width direction refers to the ratio of the length L of the semiconductor layer 530 in the direction of the dashed dotted line A1-A2 (which can also be referred to as the width L of the semiconductor layer 530) to the length H of the semiconductor layer 530 in a direction perpendicular to the surface on which the semiconductor layer 530 is formed (e.g., the insulating layer 522) (which can also be referred to as the height H of the semiconductor layer 530). The aspect ratio of the semiconductor layer 530 is preferably as large as possible within a range in which the semiconductor layer 530 does not collapse during the manufacturing process of the transistor 500mf. In the semiconductor layer 530, the height H of the semiconductor layer 530 is at least longer than the width L of the semiconductor layer 530. The height H of the semiconductor layer 530 is preferably greater than 1 time and less than or equal to 400 times the width L of the semiconductor layer 530, for example, more preferably 2 times to 100 times, even more preferably 5 times to 40 times, and even more preferably 10 times to 20 times. For example, the height H is preferably 2 to 10 times the width L, and for example, the width L is preferably 5 to 100 nm, more preferably 5 to 50 nm, and even more preferably 10 to 30 nm. For example, the height H is preferably 50 to 2000 nm, and more preferably 100 to 1000 nm. For example, the height H can be 50 to 100 nm.

[0393] 15B , in a cross-sectional view in the channel width direction, the angle θ between the side surface of the semiconductor layer 530 and the top surface of the insulating layer 522 is preferably perpendicular or approximately perpendicular. For example, the angle θ is preferably 80° to 100°, more preferably 85° to 95°.

[0394] An insulating layer 550, a conductive layer 560, and a conductive layer 542 are provided to cover the semiconductor layer 530 having such a high aspect ratio. In the transistor 500mf, as shown in FIG. 15B , a portion of the insulating layer 550 and a portion of the conductive layer 560 are provided so as to sandwich the semiconductor layer 530 in two. As a result, in a cross-sectional view in the channel width direction, the semiconductor layer 530 and the conductive layer 560 are provided facing each other with the insulating layer 550 sandwiched between the upper portion, the side surface on the A1 side, and the side surface on the A2 side of the semiconductor layer 530. In other words, the upper portion, the side surface on the A1 side, and the side surface on the A2 side of the semiconductor layer 530 each function as a channel formation region. Therefore, compared to when the semiconductor layer 530 is formed in a planar shape, the channel width of the transistor 500mf is larger by the amount of the side surface on the A1 side and the side surface on the A2 side of the semiconductor layer 530.

[0395] As described above, the increase in channel width allows the on-state current of the transistor 500mf to be increased. Furthermore, the mutual conductance of the transistor 500mf is improved. Furthermore, the frequency characteristics of the transistor 500mf are improved. By using the transistor 500mf in one or both of the pixel circuit and the driver circuit included in a display device, a display device with a high frame frequency can be provided. Furthermore, in the above structure, the provision of the semiconductor layer 530 allows the channel width to be increased without increasing the area occupied by the transistor 500mf. This allows for miniaturization or high integration of the pixel circuit and the driver circuit.

[0396] Furthermore, as shown in FIG. 15B , the upper portion of the semiconductor layer 530 preferably has a curved shape. Such a curved shape can prevent defects such as voids from forming in the insulating layer 550 and the conductive layer 542 near the upper portion of the semiconductor layer 530. Note that, in FIGS. 14B and 15C , a symmetrical structure is shown in which curved shapes are provided on both the A1 side (A3 side) and the A2 side (A4 side) of the upper portion of the semiconductor layer 530, but the present invention is not limited to this. For example, an asymmetrical structure may also be used in which a curved shape is provided on either the A1 side (A3 side) or the A2 side (A4 side) of the upper portion of the semiconductor layer 530.

[0397] Because the semiconductor layer 530 has a shape with a high aspect ratio, it is preferable to form the semiconductor layer 530 by, for example, first forming a pillar and then forming the semiconductor layer 530 in a sidewall shape on the side surface of the pillar. Therefore, it is preferable to form the semiconductor layer 530 using the ALD method, which has good coverage. Furthermore, when the semiconductor layer 530 has a stacked structure, it is preferable to form at least one layer, preferably the layer in contact with the pillar, using the ALD method.

[0398] 14A , by forming the semiconductor layers 530 in a sidewall shape in contact with the side surfaces of the plurality of pillars, the plurality of semiconductor layers 530 can be formed simultaneously. By forming the plurality of semiconductor layers 530 in this manner, the distance between the semiconductor layers 530 can be set in accordance with the size and shape of the pillar. Therefore, the distance between the semiconductor layers 530 can be reduced, the area occupied by the transistors 500mf can be reduced, and a higher integration of the display device can be achieved.

[0399] Since the semiconductor layer 530 is formed in a sidewall shape in contact with the pillar, as shown in FIG. 14A , the top surface shape of the semiconductor layer 530 is a circumferential shape with both ends coinciding (which can also be called a frame shape, annular shape, doughnut shape, or closed curve shape). The semiconductor layer 530 can also be said to have a shape with an opening in the center. Note that in FIG. 14A , the top surface shape of the semiconductor layer 530 is line-symmetrical about the dashed dotted line A1-A2, but the present invention is not limited to this. For example, the top surface shape of the semiconductor layer 530 can also be asymmetrical.

[0400] The structure shown in FIG. 14A includes two pillars arranged in the direction of the dashed dotted line A1-A2, with a circumferential semiconductor layer 530 formed in contact with the side surface of each pillar. As shown in FIG. 14A , the semiconductor layer 530 preferably overlaps the conductive layer 560 at two or more locations in a plan view. That is, the semiconductor layer 530 and the conductive layer 560 have two or more overlapping regions. This structure results in multiple fin-shaped semiconductor layers 530 being formed in a cross-sectional view in the channel width direction, as shown in FIG. 14B . Each of the multiple fin-shaped semiconductor layers 530 functions as a channel formation region. That is, the transistor 500mf functions as a multi-channel transistor. Therefore, the channel width of the transistor 500mf can be further increased. Because the transistor 500mf includes multiple fin-shaped semiconductor layers 530, it is sometimes referred to as a multi-fin structure transistor.

[0401] Although the above description has been given of a configuration in which two circumferential semiconductor layers 530 are provided, the present invention is not limited to this. For example, a configuration in which one or three or more circumferential semiconductor layers 530 are provided may be used. Furthermore, the circumferential semiconductor layers 530 may be joined together to form a semiconductor layer 530 having a shape with a plurality of openings.

[0402] Although the above description has been given of a circumferential semiconductor layer 530, the present invention is not limited to this. For example, the semiconductor layer 530 may have a non-circumferential configuration. For example, the transistor 500mf shown in FIGS. 14A to 14D may have only one fin-shaped semiconductor layer 530 intersecting the conductive layer 540a, the insulating layer 550, the conductive layer 560, and the conductive layer 540b, as in the transistor 500sf shown in FIGS. 16A to 16D . In this case, the perspective schematic diagrams of the transistor are as shown in FIGS. 17A and 17B . By reducing the number of fin-shaped semiconductor layers 530 intersecting the conductive layer 540a, the insulating layer 550, the conductive layer 560, and the conductive layer 540b, the area required for forming the transistor can be reduced, thereby reducing the area occupied by a circuit including the transistor. The drawings and symbols in FIGS. 16A to 16D correspond to those in FIGS. 14A to 14D , and therefore the above content can be referenced for detailed configurations.

[0403] <Cross-Sectional Configuration Example 2> FIG. 18 is a schematic cross-sectional view of an example of the memory circuit MDV shown in FIGS. 10A, 10B, and 11, which is different from FIG.

[0404] The memory circuit MDV in FIG. 18 differs from the memory circuit MDV in FIG. 12 in that the transistors included in the layer SS2 are vertical channel transistors.

[0405] 18, the source electrode and the drain electrode are located at different heights, and the current flowing through the semiconductor layer is in the height direction. That is, the channel length direction can be said to have a component in the height direction (vertical direction), and therefore they are called vertical channel transistors. Note that each of the transistors MN11 and MN12 can also be called a VFET (Vertical Field Effect Transistor), a vertical transistor, a vertical channel transistor, etc., in addition to being called a vertical channel transistor.

[0406] 19A shows a schematic plan view of an example of a memory circuit MDV, and FIG. 19B shows a schematic cross-sectional view of the arithmetic device. FIG. 18 is a schematic cross-sectional view taken along dashed line A1-A2 in FIG. 19A. FIG. 19B is a schematic cross-sectional view taken along dashed line A3-A4 in FIG. 19A. FIG. 19B shows only the transistors and capacitance elements included in layer SS2.

[0407] The structures of the vertical channel transistor and the capacitor included in the memory circuit MDV will be described with reference to FIG. 19B.

[0408] FIG. 19B shows a vertical channel transistor MN12, a capacitance element C1 located above the transistor MN12, and a transistor MN11 located above the capacitance element C1.

[0409] As an example, the layer SS2 has a conductive layer that becomes the wiring RBL, an insulating layer IS1 that functions as an interlayer film, a conductive layer that becomes the wiring RWL, a semiconductor layer SC1 that includes a channel formation region of the transistor MN12, an insulating layer GI1 that functions as a gate insulating film of the transistor MN12, a conductive layer ME3, a conductive layer ME4, an insulating layer DI that functions as a dielectric, a conductive layer that becomes the wiring VGE, an insulating layer IS2 that functions as an interlayer film, a conductive layer that becomes the wiring WBL, the semiconductor layer SC1 that includes the channel formation region of the transistor MN11, an insulating layer GI2 that functions as a gate insulating film of the transistor MN11, a conductive layer ME6, and a conductive layer that becomes the wiring WWL.

[0410] An insulating layer IS1 and a conductive layer that will become the wiring RWL are stacked in this order above the conductive layer that will become the wiring RBL. An opening is formed among the conductive layer that will become the wiring RBL, the insulating layer IS1, and the conductive layer that will become the wiring RWL, and a semiconductor layer SC1 is formed on the side and bottom of the opening. The semiconductor layer SC1 is also formed on the top surface of the conductive layer that will become the wiring RWL. An insulating layer GI1 is formed on the top surface of the semiconductor layer SC1, on the side of the conductive layer that will become the wiring RWL, and above the insulating layer IS1. A conductive layer ME3 is formed on the top surface of the insulating layer GI1 so as to fill the opening. A conductive layer ME4 is formed on the top surface of the conductive layer ME3.

[0411] A part of the conductive layer that becomes the wiring RBL functions as one of the source and drain of the transistor MN12, a part of the conductive layer that becomes the wiring RWL functions as the other of the source and drain of the transistor MN12, and a part of the conductive layer ME3 functions as the gate of the transistor MN12.

[0412] As described above, by forming the insulating layer, conductive layer, and semiconductor layer, a vertical channel transistor can be formed in which the channel length direction has a component in the height direction (vertical direction). Furthermore, the channel length of the vertical channel transistor depends on the film thickness of the insulating layer IS1. The thinner the insulating layer IS1, the shorter the channel length, which allows the on-current of the transistor MN12 to be increased. On the other hand, the thicker the insulating layer IS1, the longer the channel length, which allows the off-current of the transistor MN12 to be reduced.

[0413] 19A, the conductive layer that will become the wiring RBL is provided along the direction of the dashed dotted line A1-A2, and the conductive layer that will become the wiring RWL is provided along the direction of the dashed dotted line A3-A4.

[0414] The wirings connecting the vertical channel transistors are not formed in the same process but in different processes. As a result, the wirings connecting the vertical channel transistors have overlapping regions in a plan view. In other words, the wirings connecting the vertical channel transistors are provided at different heights, which reduces the parasitic capacitance generated in each wiring. This allows the driving frequency of the transistor MN12 to be increased, and the driving speed of the memory circuit MDV to be increased.

[0415] 18 and 19B , the insulating layer DI is formed on the side and top surfaces of the conductive layer ME4, and the conductive layer that will become the wiring VGE is formed so as to include an area that overlaps with the side surface of the conductive layer ME4.

[0416] Here, the capacitance element C1 is formed in a region where the conductive layer ME4 and the conductive layer that will become the wiring VGE overlap with each other via the insulating layer DI. For example, a portion of the conductive layer ME4 functions as one of a pair of electrodes of the capacitance element C1, and a portion of the conductive layer that will become the wiring VGE functions as the other of the pair of electrodes of the capacitance element C1. Note that the conductive layer that will become the wiring VGE is provided along the direction of the dashed dotted line A1-A2, as shown in FIG. 19A .

[0417] Above the conductive layer ME4, an insulating layer DI, an insulating layer IS2, and a conductive layer that will become the wiring WBL are stacked in this order. An opening is formed among the conductive layer ME4, the insulating layer DI, the insulating layer IS2, and the conductive layer that will become the wiring WBL, and a semiconductor layer SC2 is formed on the side and bottom of the opening. The semiconductor layer SC2 is also formed on the top surface of the conductive layer that will become the wiring WBL. An insulating layer GI2 is formed on the top surface of the semiconductor layer SC2, on the side of the conductive layer that will become the wiring WBL, and above the insulating layer IS2. A conductive layer ME6 is formed on the top surface of the insulating layer GI2 so as to fill the opening. A conductive layer that will become the wiring WWL is formed on the top surface of the conductive layer ME6.

[0418] A part of the conductive layer ME4 functions as one of the source and drain of the transistor MN11, a part of the conductive layer that becomes the wiring WBL functions as the other of the source and drain of the transistor MN11, and a part of the conductive layer ME6 functions as the gate of the transistor MN11.

[0419] Similarly to the transistor MN12, the channel length of the transistor MN11 is determined by the film thickness of the insulating layer IS2. Therefore, the thinner the insulating layer IS2, the larger the on-current of the transistor MN11 can be. On the other hand, the thicker the insulating layer IS2, the smaller the off-current of the transistor MN11 can be.

[0420] 19A, the conductive layer that will become the wiring WBL is provided along the direction of the dashed line A1-A2, and the conductive layer that will become the wiring WWL is provided along the direction of the dashed line A3-A4.

[0421] As described above, by using vertical channel transistors for the transistors MN11 and MN12, the transistors MN11 and MN12 can be fabricated to overlap each other, thereby reducing the circuit area of ​​the memory circuit MDV.

[0422] <Cross-Sectional Configuration Example 3> FIG. 20 is a schematic cross-sectional view of an example of the memory circuit MDV shown in FIGS. 10A, 10B, and 11, which is different from FIG. 12.

[0423] The memory circuit MDV in Fig. 20 differs from the memory circuit MDV in Fig. 12 in that it has a plurality of layers SS2 shown in Fig. 10A and Fig. 11. Furthermore, the memory circuit MDV in Fig. 20 illustrates a layer SS2[1] and a layer SS2[2] as the plurality of layers SS2.

[0424] For the layer SS1 of the memory circuit MDV in Fig. 20, the description of the layer SS1 of the memory circuit MDV in Fig. 12 can be referred to. For the layer SS2[1] of the memory circuit MDV in Fig. 20, the description of the layer SS2 of the memory circuit MDV in Fig. 12 can be referred to. That is, the memory circuit MDV in Fig. 20 can be configured such that a layer SS2[2] is provided above the memory circuit MDV in Fig. 12.

[0425] The layer SS2[2] of the memory circuit MDV in Fig. 20 has a substrate BS. Also, a transistor MN11, a transistor MN12, and a capacitance element C1 are formed on the substrate BS. Note that the configuration of the memory cell 10 formed on the substrate BS is the same as the memory cell 10 included in the layer SS2 of the memory circuit MDV in Fig. 12, but the configuration of the memory cell 10 in Fig. 20 can be changed depending on the situation.

[0426] The substrate BS can be a substrate that can be used for the substrate included in the layer SS1 (e.g., the substrate 311). For example, by using a semiconductor substrate made of silicon for the substrate BS, the transistor included in the layer SS2[2] can be a Si transistor. Furthermore, by using through-electrode technology (e.g., TSV: Through Silicon Via) technology, the layer SS2[1] and the layer SS2[2] can be connected via the substrate BS.

[0427] The substrate BS can be mounted on the substrate 311 by flip-chip bonding or wire bonding. A bonding layer can be provided between the substrates to be bonded, and one or both of a surface activated bonding method and a hydrophilic bonding method can be used. Cu-Cu (copper-copper) direct bonding can also be used.

[0428] Note that the semiconductor device of one embodiment of the present invention is not limited to the structures illustrated in Figures 10A, 10B, 11, 12, 18, and 20. The structures of the semiconductor device of one embodiment of the present invention can be modified as appropriate from those illustrated in Figures 10A, 10B, 11, 12, 18, and 20.

[0429] For example, in the memory circuit MDV of Figure 20, two layers, layer SS2[1] and layer SS2[2], are shown as layers including memory cells 10, but the number of layers including memory cells 10 can be three or more.

[0430] Note that this embodiment mode can be appropriately combined with the same or other embodiment modes described in this specification. For example, the configuration, structure, method, etc. described in this embodiment mode can be appropriately combined with another configuration, structure, method, etc. described in this embodiment mode. Furthermore, for example, the configuration, structure, method, etc. described in this embodiment mode can be appropriately combined with the configuration, structure, method, etc. described in other embodiment modes.

[0431] Embodiment 3 In this embodiment, a processing apparatus according to one embodiment of the present invention will be described.

[0432] Fig. 21 shows a schematic perspective view of a processing device 960. The processing device 960 shown in Fig. 21 can be applied to, for example, a CPU. The processing device 960 can also be applied to processors such as a GPU, a TPU (Tensor Processing Unit), or an NPU (Neural Processing Unit) that have a larger number (several tens to several hundreds) of processor cores capable of parallel processing than a CPU.

[0433] The processing device 960 shown in Figure 21 has an ALU 991 (ALU: Arithmetic logic unit, arithmetic circuit), an ALU controller 992, an instruction decoder 993, an interrupt controller 994, a timing controller 995, a register 996, a register controller 997, a bus interface 998, a cache 999, and a cache interface 989 on a substrate 990. The substrate 990 may be a semiconductor substrate, an SOI substrate, a glass substrate, or the like. A rewritable ROM and a ROM interface may be provided. The cache 999 and the cache interface 989 may also be provided on separate chips.

[0434] The cache 999 is connected to a main memory provided on a separate chip via a cache interface 989. The cache interface 989 has a function of supplying part of the data held in the main memory to the cache 999. The cache interface 989 also has a function of outputting part of the data held in the cache 999 to the ALU 991 or register 996 via a bus interface 998.

[0435] The cache 999 may include, for example, the memory circuit MDV described in embodiment 2. In this case, the processing device 960 has the memory cell 10 described in embodiment 2 and the drive circuit region 50. This may enable the processing device 960 to be miniaturized and may also enable the drive frequency of the processing device 960 to be increased.

[0436] The processing device 960 shown in FIG. 21 is merely an example of a simplified configuration, and actual processing devices 960 have a wide variety of configurations depending on their applications. For example, it is preferable to use a configuration including the processing device 960 shown in FIG. 21 as one core, and to include multiple such cores, each of which operates in parallel, in a so-called multi-core configuration. The greater the number of cores, the higher the computing performance. The greater the number of cores, for example, two, preferably four, more preferably eight, even more preferably twelve, and even more preferably sixteen or more. Furthermore, when extremely high computing performance is required, such as for server applications, a multi-core configuration having 16 or more, preferably 32 or more, and even more preferably 64 or more cores is preferable. Furthermore, the number of bits that the processing device 960 can handle via its internal computing circuit, data bus, etc. can be, for example, 8 bits, 16 bits, 32 bits, 64 bits, 128 bits, or more.

[0437] An instruction input to the processing unit 960 via the bus interface 998 is input to the instruction decoder 993, decoded, and then input to the ALU controller 992, interrupt controller 994, register controller 997, and timing controller 995.

[0438] The ALU controller 992, interrupt controller 994, register controller 997, and timing controller 995 perform various controls based on the decoded instructions. Specifically, the ALU controller 992 generates signals for controlling the operation of the ALU 991. Furthermore, the interrupt controller 994 determines and processes interrupt requests from external input / output devices, peripheral circuits, etc. based on their priority, mask status, etc. while the processing unit 960 is executing a program. The register controller 997 generates an address for a register 996 and reads or writes data from or to the register 996 depending on the state of the processing unit 960.

[0439] Furthermore, the timing controller 995 generates signals that control the timing of the operations of the ALU 991, the ALU controller 992, the instruction decoder 993, the interrupt controller 994, and the register controller 997. For example, the timing controller 995 includes an internal clock generation unit that generates an internal clock signal based on a reference clock signal, and supplies the internal clock signal to the various circuits described above.

[0440] 21 , a register controller 997 selects a holding operation in a register 996 in accordance with an instruction from the ALU 991. For example, the register controller 997 can select whether to write data to the register 996 or read data from the register 996 in accordance with an instruction from the ALU 991.

[0441] Note that this embodiment mode can be appropriately combined with the same or other embodiment modes described in this specification. For example, the configurations, structures, methods, and the like described in this embodiment mode can be appropriately combined and used with the configurations, structures, methods, and the like described in the other embodiment modes. For example, the configurations, structures, methods, and the like described in this embodiment mode can be appropriately combined and used with the configurations, structures, methods, and the like described in the other embodiment modes.

[0442] Embodiment 4 In this embodiment, an application example of a memory device including a memory circuit according to one embodiment of the present invention will be described.

[0443] Generally, various memory devices are used in semiconductor devices such as computers depending on the application. FIG. 22A shows various memory devices used in semiconductor devices by layer. The higher the layer, the faster the operating speed of the memory device is required, while the lower the layer, the larger the memory capacity and recording density are required. In FIG. 22A , from the top layer, there are memory integrated as a register in an arithmetic processing unit (sometimes referred to as a processing unit) such as a CPU, an L1 cache, an L2 cache, an L3 cache, a main memory, and storage. Note that while an example having up to an L3 cache is shown here, lower-level caches can also be provided.

[0444] Note that the memory circuit MDV described in Embodiment 2 can be used as a memory included in an arithmetic processing unit. For example, the memory circuit MDV can be used as memories such as a register, an L1 cache, an L2 cache, an L3 cache, or the like.

[0445] The memory embedded as a register in a processing unit such as a CPU is used for temporary storage of calculation results, and is therefore frequently accessed by the processing unit. Therefore, a higher operating speed is required than a larger memory capacity. Registers also have the function of storing setting information for the processing unit.

[0446] A cache has the function of duplicating and storing a portion of the data stored in main memory. By duplicating frequently used data and storing it in the cache, the access speed to the data can be increased. The storage capacity required for a cache is smaller than that of main memory, but it is required to operate at a faster speed than main memory. In addition, data rewritten in the cache is duplicated and supplied to the main memory.

[0447] The main memory has a function of holding programs, data, etc. read from storage.

[0448] Storage has the function of storing data that requires long-term storage, various programs used by processing units, etc. Therefore, storage requires a large memory capacity and high recording density rather than an operating speed. For example, high-capacity, non-volatile storage devices such as 3D NAND can be used.

[0449] A memory device (OS memory) using an oxide semiconductor according to one embodiment of the present invention has high operation speed and can retain data for a long period of time. For example, the OS memory has the characteristics shown in the table below.

[0450]

[0451] By utilizing the characteristics of the OS memory shown in the table above, a storage device according to one aspect of the present invention can be suitably used in both the tier where the cache is located and the tier where the main memory is located, as shown in Fig. 22A. The storage device according to one aspect of the present invention can also be applied to the tier where the storage is located.

[0452] FIG. 22B also shows an example in which an SRAM is used as part of a cache and an OS memory of one embodiment of the present invention is used as the other part of the cache.

[0453] The lowest level cache can be called a last level cache (LLC). While an LLC does not require faster operation speed than higher level caches, it is desirable for the LLC to have a large storage capacity. The OS memory of one embodiment of the present invention has a high operation speed and can retain data for a long period of time, and therefore can be suitably used for an LLC. The OS memory of one embodiment of the present invention can also be applied to a final level cache (FLC).

[0454] For example, as shown in Fig. 22B, a configuration can be adopted in which SRAM is used for the higher-level caches (L1 cache, L2 cache, etc.) and the OS memory according to one aspect of the present invention is used for the LLC. Also, as shown in Fig. 22B, not only the OS memory but also DRAM can be applied to the main memory.

[0455] In supercomputers and servers using supercomputers, the power consumption of the L3 cache and the DRAM serving as the main memory is large, which is one of the causes of global warming. In FIG. 22A , OS memory is used for both the L3 cache and the main memory. In FIG. 22B , OS memory is used for the LLC. In this manner, by using an oxide semiconductor according to one embodiment of the present invention for a storage device, the power consumption of a supercomputer can be reduced, and the power consumption of a supercomputer can be reduced to the same level as that of a personal computer.

[0456] Note that this embodiment mode can be appropriately combined with the same or other embodiment modes described in this specification. For example, the configuration, structure, method, etc. described in this embodiment mode can be appropriately combined with another configuration, structure, method, etc. described in this embodiment mode. Furthermore, for example, the configuration, structure, method, etc. described in this embodiment mode can be appropriately combined with the configuration, structure, method, etc. described in other embodiment modes.

[0457] In this embodiment, an electronic component, an electronic device, a mainframe computer, a space equipment, and a data center (also referred to as a data center (DC)) that can use the memory circuit or a memory device including the memory circuit described in the above embodiment will be described. The electronic component, the electronic device, the mainframe computer, the space equipment, and the data center that use the semiconductor device of one embodiment of the present invention are effective in achieving high performance, such as low power consumption.

[0458] [Electronic Component] Fig. 23A shows a perspective view of electronic component 700. Electronic component 700 shown in Fig. 23A has a substrate 701, a semiconductor device 710 on substrate 701, and a mold 711. In particular, semiconductor device 710 is sealed by mold 711. Note that Fig. 23A omits some parts of electronic component 700 in order to show the interior of electronic component 700.

[0459] The substrate 701 may be, for example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate.

[0460] Electronic component 700 is provided with, for example, a lead frame 712. A portion of lead frame 712 located on substrate 701 is covered with mold 711, and another portion of lead frame 712 is exposed to the outside of mold 711. In particular, lead frame 712 exposed to the outside of mold 711 functions as, for example, a terminal for mounting electronic component 700 on a printed circuit board.

[0461] Within mold 711, electrode pads 713 are provided on lead frame 712, and electrode pads 713 are electrically connected to semiconductor device 710 via wires 714. Electronic component 700 is mounted on a printed circuit board, for example, by contacting lead frame 712 with wiring on the printed circuit board. In this way, a mounted board is completed by combining multiple electronic components and electrically connecting them on the printed circuit board.

[0462] Next, a semiconductor device 710 will be described. For example, as shown in FIG. 23B , the semiconductor device 710 includes a driver circuit layer 715 and a memory layer 716. Note that the memory layer 716 can have a structure in which a plurality of memory cell arrays are stacked. The semiconductor device 710 can also include the memory circuit or memory device described in the above embodiment.

[0463] The stacked configuration of the drive circuit layer 715 and the memory layer 716 can be a monolithic stacked configuration. In a monolithic stacked configuration, the layers can be connected without using bonding technologies such as through-electrode technology (e.g., TSV, etc.) and Cu-Cu (copper-copper) direct bonding. By forming the drive circuit layer 715 and the memory layer 716 in a monolithic stacked configuration, for example, a so-called on-chip memory configuration can be achieved, in which memory is formed directly on the processor. The on-chip memory configuration makes it possible to increase the operation speed of the interface between the processor and the memory.

[0464] Furthermore, by configuring an on-chip memory, it is possible to reduce the size of connection wiring, etc., compared to technologies that use through electrodes such as TSVs, and therefore it is possible to increase the number of connection pins. Increasing the number of connection pins enables parallel operation, which makes it possible to improve the memory bandwidth (also called memory bandwidth).

[0465] It is also preferable that the memory cell arrays included in the memory layer 716 are formed using OS transistors and the memory cell arrays are monolithically stacked. By forming the memory cell arrays in a monolithic stacked structure, it is possible to improve either or both of the memory bandwidth and the memory access latency. Note that the bandwidth refers to the amount of data transferred per unit time, and the access latency refers to the time from access to the start of data exchange. Note that when Si transistors are used for the memory layer 716, it is more difficult to form a monolithic stacked structure than when OS transistors are used. Therefore, it can be said that OS transistors have a superior structure to Si transistors in a monolithic stacked structure.

[0466] The semiconductor device 710 may also be referred to as a die. In this specification and the like, a die refers to a chip piece obtained by forming a circuit pattern on, for example, a disk-shaped substrate (also called a wafer) and cutting it into dices during the semiconductor chip manufacturing process. Semiconductor materials that can be used for the die include, for example, silicon (Si), silicon carbide (SiC), and gallium nitride (GaN). For example, a die obtained from a silicon substrate (also called a silicon wafer) may be called a silicon die.

[0467] Next, Fig. 23C shows a modified example of electronic component 700. Electronic component 700A shown in Fig. 23C does not use lead frame 712, as in electronic component 700, and has a configuration in which electrodes 733 are provided on the bottom of substrate 701. Electrodes 733 function as connection terminals for mounting electronic component 700A on a printed circuit board.

[0468] 23C shows an example in which electrodes 733 are formed using solder balls. By providing solder balls in a matrix on the bottom of substrate 701, BGA (Ball Grid Array) mounting can be achieved. For this purpose, through-hole vias (penetrating vias) are provided in substrate 701, and conductive layers 732 that function as wiring are provided in these vias. Electrode pads 713 are provided above conductive layer 732 on substrate 701 so as to be in contact with them, and electrodes 733 are provided below conductive layer 732 below substrate 701 so as to be in contact with them.

[0469] Furthermore, the electrodes 733 can be formed of conductive pins instead of solder balls. By providing conductive pins in a matrix on the bottom of the substrate 701, PGA (Pin Grid Array) mounting can be achieved.

[0470] Furthermore, electronic component 700A can be mounted on other substrates using various mounting methods other than BGA and PGA, such as staggered pin grid array (SPGA), land grid array (LGA), quad flat package (QFP), quad flat J-leaded package (QFJ), and quad flat non-leaded package (QFN).

[0471] The electronic component of one embodiment of the present invention can be in the form of a system in package (SiP) or a multi-chip module (MCM). For example, an electronic component 700C shown in FIG. 23D includes an interposer 731 provided over a package substrate 734 (printed circuit board), and a semiconductor device 735 and multiple semiconductor devices 710 provided over the interposer 731.

[0472] 23D shows an example in which the semiconductor device 710 is used as a high bandwidth memory (HBM). The semiconductor device 735 can be used as an arithmetic circuit in an integrated circuit such as a CPU, a GPU, or an FPGA (Field Programmable Gate Array).

[0473] The package substrate 734 may be, for example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate, similar to the substrate 701. The interposer 731 may be, for example, a silicon interposer or a resin interposer.

[0474] The interposer 731 has multiple wirings and functions to electrically connect multiple integrated circuits with different terminal pitches. The multiple wirings are provided in a single layer or multiple layers. The interposer 731 also functions to electrically connect the integrated circuits provided on the interposer 731 to electrodes provided on the package substrate 734. For these reasons, the interposer is sometimes called a "rewiring substrate" or "intermediate substrate." In addition, through electrodes may be provided in the interposer 731, and the integrated circuits and the package substrate 734 may be electrically connected using the through electrodes. In addition, with a silicon interposer, a TSV may also be used as the through electrode.

[0475] In an HBM, many wirings must be connected to achieve a wide memory bandwidth. Therefore, the interposer on which the HBM is mounted must have fine and high-density wiring. Therefore, it is preferable to use a silicon interposer for the interposer on which the HBM is mounted.

[0476] Furthermore, in SiP and MCM using silicon interposers, a decrease in reliability due to differences in the coefficient of expansion between the integrated circuit and the interposer is unlikely to occur. Furthermore, since the silicon interposer has a highly flat surface, poor connection between the integrated circuit mounted on the silicon interposer and the silicon interposer is unlikely to occur. In particular, it is preferable to use silicon interposers in 2.5D packages (2.5-dimensional packaging) in which multiple integrated circuits are arranged horizontally on the interposer.

[0477] On the other hand, when electrically connecting multiple integrated circuits with different terminal pitches using a silicon interposer and TSVs, space is required, such as the width of the terminal pitch. Therefore, when attempting to reduce the size of the electronic component 700C, the width of the terminal pitch becomes an issue, and it may be difficult to provide the large number of wirings required to achieve a wide memory bandwidth. Therefore, as described above, a monolithic stacked configuration using OS transistors is preferable. Also, for example, a memory cell array stacked using TSVs and a monolithically stacked memory cell array can be combined. A structure combining a memory cell array stacked using TSVs and a monolithically stacked memory cell array is sometimes called a hybrid structure.

[0478] Furthermore, if the temperature of the electronic component 700C increases due to heat generated by electric current or the like, the characteristics of the circuit elements (e.g., transistors) included in the electronic component 700C may be degraded. Therefore, it is preferable to provide a heat sink (heat sink) on the electronic component 700C so that the heat sink overlaps the electronic component 700C. When providing a heat sink, it is preferable to align the height of the integrated circuit provided on the interposer 731. For example, in the electronic component 700C shown in this embodiment, it is preferable to align the height of the semiconductor device 710 and the semiconductor device 735.

[0479] [Electronic Device] Next, a perspective view of an electronic device 6500 is shown in FIG. 24A . The electronic device 6500 shown in FIG. 24A is a portable information terminal that can be used as a smartphone. The electronic device 6500 includes a housing 6501, a display portion 6502, a power button 6503, a button 6504, a speaker 6505, a microphone 6506, a camera 6507, a light source 6508, and a control device 6509. Note that the control device 6509 includes, for example, one or more selected from a CPU, a GPU, and a memory circuit. The semiconductor device of one embodiment of the present invention can be applied to the display portion 6502, the control device 6509, and the like.

[0480] 24B is an information terminal that can be used as a laptop personal computer. The electronic device 6600 includes a housing 6611, a keyboard 6612, a pointing device 6613, an external connection port 6614, a display portion 6615, and a control device 6616. Note that the control device 6616 includes, for example, one or more selected from a CPU, a GPU, and a memory circuit. The semiconductor device of one embodiment of the present invention can be used for the display portion 6615, the control device 6616, and the like.

[0481] The semiconductor device of one embodiment of the present invention is preferably used for the control devices 6509 and 6616 because power consumption can be reduced.

[0482] [Mainframe] Next, Fig. 24C shows a perspective view of multiple mainframe computers 5600 installed in a server room or the like. The mainframe computer 5600 shown in Fig. 24C has multiple rack-mounted computers 5620 stored in a rack 5610. The mainframe computer 5600 is sometimes called a supercomputer.

[0483] The computer 5620 has a motherboard, which is provided with a plurality of slots, a plurality of connection terminals, etc. For example, one or a plurality of PC cards can be inserted into the slot.

[0484] The PC card is an example of a processing board equipped with a processing unit such as a CPU, a GPU, etc. For example, the electronic component 700 can be used as the processing unit.

[0485] The mainframe computer 5600 can also function as a parallel computer. By using the mainframe computer 5600 as a parallel computer, it is possible to perform large-scale calculations necessary for learning and inference in artificial intelligence, for example.

[0486] [Space Equipment] The semiconductor device of one embodiment of the present invention can be suitably used in space equipment (for example, equipment having a function of processing and storing information).

[0487] The semiconductor device of one embodiment of the present invention can include an OS transistor. The OS transistor exhibits small changes in electrical characteristics due to radiation exposure. That is, the OS transistor has high radiation resistance and can be suitably used in an environment where radiation may be incident. For example, the OS transistor can be suitably used in outer space.

[0488] Fig. 25 shows an artificial satellite 6800 as an example of space equipment. The artificial satellite 6800 has a body 6801, a solar panel 6802, an antenna 6803, a secondary battery 6805, and a control device 6807. In Fig. 25, a planet 6804 is shown in outer space. Note that outer space refers to an altitude of 100 km or higher, for example, but the outer space described in this specification may also include the thermosphere, mesosphere, and stratosphere.

[0489] 25, a battery management system (also referred to as a BMS) or a battery control circuit can be provided for the secondary battery 6805. The use of an OS transistor in the battery management system or the battery control circuit is preferable because it consumes low power and has high reliability even in space.

[0490] Furthermore, outer space is an environment with radiation levels 100 times higher than on Earth. Examples of radiation include electromagnetic waves (electromagnetic radiation) such as X-rays and gamma rays, and particle radiation such as alpha rays, beta rays, neutron rays, proton rays, heavy ion rays, and meson rays.

[0491] When sunlight is irradiated onto the solar panel 6802, the power required for the operation of the satellite 6800 is generated. However, for example, in a situation where sunlight is not irradiated onto the solar panel or where the amount of sunlight irradiating the solar panel is small, the generated power is small. Therefore, there is a possibility that the power required for the operation of the satellite 6800 will not be generated. In order to operate the satellite 6800 even in a situation where the generated power is small, a secondary battery 6805 can be provided on the satellite 6800. Note that the solar panel may also be called a solar cell module.

[0492] The satellite 6800 can generate a signal. The signal is transmitted via an antenna 6803, and can be received, for example, by a receiver on the ground or another satellite. By receiving the signal transmitted by the satellite 6800, the position of the receiver that received the signal can be determined. As described above, the satellite 6800 can constitute a satellite positioning system.

[0493] The control device 6807 has a function of controlling the artificial satellite 6800. The control device 6807 is configured using, for example, one or more selected from a CPU, a GPU, and a memory circuit. Note that the semiconductor device of one embodiment of the present invention is preferably used for the control device 6807. An OS transistor has smaller fluctuations in electrical characteristics due to radiation exposure than a Si transistor. That is, an OS transistor has high reliability even in an environment where radiation may be incident, and can be preferably used.

[0494] The artificial satellite 6800 can also be configured to include a sensor. For example, by including a visible light sensor, the artificial satellite 6800 can have the function of detecting sunlight reflected from an object on the ground. Or, by including a thermal infrared sensor, the artificial satellite 6800 can have the function of detecting thermal infrared rays emitted from the earth's surface. As described above, the artificial satellite 6800 can function as, for example, an earth observation satellite.

[0495] Although an artificial satellite is given as an example of space equipment in this embodiment, the invention is not limited thereto. For example, the semiconductor device of one embodiment of the present invention can be suitably used in space equipment such as a spaceship, a space capsule, or a space probe.

[0496] As described above, OS transistors have excellent advantages over Si transistors, such as the ability to achieve a wide memory bandwidth and high radiation resistance.

[0497] [Data Center] The semiconductor device of one embodiment of the present invention can be suitably used in a storage system applied to, for example, a data center. The data center is required to perform long-term management of data, such as ensuring data immutability. To manage long-term data, the building must be large enough to accommodate the installation of storage and servers for storing a huge amount of data, a stable power supply for maintaining the data, and cooling equipment required for maintaining the data.

[0498] By using the memory circuit of one embodiment of the present invention in a storage system applied to a data center, it is possible to reduce the power required to store data and the size of the memory circuit that stores data. This makes it possible to reduce the size of the storage system, the size of the power supply for storing data, and the scale of cooling equipment. This makes it possible to save space in the data center.

[0499] Furthermore, the memory circuit of one embodiment of the present invention consumes less power, and thus heat generation from the circuit can be reduced. Therefore, adverse effects of the heat generation on the circuit itself, peripheral circuits, and modules can be reduced. Furthermore, by using the memory circuit of one embodiment of the present invention, a data center that operates stably even in a high-temperature environment can be realized. Therefore, the reliability of the data center can be improved.

[0500] Fig. 26 shows a storage system applicable to a data center. The storage system 7000 shown in Fig. 26 has a plurality of servers 7001sb as hosts 7001 (illustrated as Host Computers). It also has a plurality of storage devices 7003md as storage 7003 (illustrated as Storage). The host 7001 and storage 7003 are shown connected via a storage area network 7004 (illustrated as SAN: Storage Area Network) and a storage control circuit 7002 (illustrated as Storage Controller).

[0501] The host 7001 can be a computer that accesses data stored in the storage 7003. The hosts 7001 may be connected to each other via a network.

[0502] Although the storage 7003 uses flash memory to reduce the data access speed, i.e., the time required to store and output data, this time is significantly longer than the time required for DRAM (Dynamic Random Access Memory), which can be used as cache memory within the storage. In order to solve the problem of the long access speed of the storage 7003, a storage system typically provides cache memory within the storage to reduce the time required to store and output data.

[0503] The above-mentioned cache memory is used in the storage control circuit 7002 and the storage 7003. Data exchanged between the host 7001 and the storage 7003 is stored in the cache memory in the storage control circuit 7002 and the storage 7003, and then output to the host 7001 or the storage 7003.

[0504] By using OS transistors as transistors for storing data in the cache memory and holding a potential corresponding to the data, the frequency of refreshing the data can be reduced, and power consumption can be reduced.

[0505] Note that the application of the semiconductor device of one embodiment of the present invention to any one or more selected from electronic components, electronic devices, mainframe computers, space equipment, and data centers is expected to have an effect of reducing power consumption. Therefore, while energy demand is expected to increase with the improvement in performance or high integration of semiconductor devices, the use of the semiconductor device of one embodiment of the present invention is expected to contribute to the reduction of carbon dioxide (CO ２ Furthermore, the semiconductor device of one embodiment of the present invention is effective as a countermeasure against global warming because it consumes low power.

[0506] Note that this embodiment mode can be appropriately combined with the same or other embodiment modes described in this specification. For example, the configuration, structure, method, etc. described in this embodiment mode can be appropriately combined with another configuration, structure, method, etc. described in this embodiment mode. Furthermore, for example, the configuration, structure, method, etc. described in this embodiment mode can be appropriately combined with the configuration, structure, method, etc. described in other embodiment modes.

[0507] ADDR: signal, BL: wiring, BLB: wiring, BS: substrate, BW: signal, CE: signal, CLK: signal, CSEL: wiring, DBL: wiring, DBLB: wiring, DBSW: switch, DI: insulating layer, DSW: switch, GW: signal, HSW: switch, IT: terminal, ITB: terminal, LSW: switch, LTSA: sense amplifier, MC: memory cell, MCA: memory cell array, MDV: memory circuit, MEG: conductive layer, MN11: transistor, MN12: transistor, MN13: transistor, ND: node, PCP: parasitic capacitance, PREB: wiring, RBL: wiring , RDA: signal, RE: wiring, REB: wiring, RWL: wiring, SWE: wiring, SWEB: wiring, T01: period, T02: period, T03: period, T04: period, T05: period, T06: period, T07: period, T11: period, T12: period, T13: period, T14: period, T15: period, T16: period, T17: period, T21: period, T22: period, T23: period, T24: period, T25: period, T26: period, T27: period, T31: period, T32: period, T33: period, T34: period, T35: period, T36: period, TrP: transistor, TrQ: transistor transistor, VDE: wiring, VGE: wiring, VHE: wiring, VPE: wiring, VRE: wiring, VSE: wiring, WAKE: signal, WBL: wiring, WDA: signal, WE: wiring, WEB: wiring, WRC: amplifier circuit, WRCA: amplifier circuit, WWL: wiring, 10: memory cell, 22: PSW, 23: PSW, 31: peripheral circuit, 32: control circuit, 33: voltage generation circuit, 40: amplifier circuit, 41: peripheral circuit, 42: row decoder, 43: row driver, 44: column decoder, 45: column driver, 47: input circuit, 48: output circuit, 50: drive circuit area, 311: substrate, 313 : semiconductor region, 314a: low resistance region, 314b: low resistance region, 315: insulating layer, 316: conductive layer, 317: insulating layer, 320: insulating layer, 324: insulating layer, 326: insulating layer, 328: conductive layer, 330: conductive layer, 350: insulating layer, 352: insulating layer, 354: insulating layer, 356: conductive layer, 357: insulating layer, 400: transistor, 500mf: transistor, 500sf: transistor, 514: insulating layer, 516: insulating layer, 521: insulating layer, 522: insulating layer, 530: semiconductor layer, 530a: semiconductor layer, 530b: semiconductor layer, 530c: semiconductor layer, 540: conductive layer,540a: conductive layer, 540b: conductive layer, 541: insulating layer, 541a: insulating layer, 541b: insulating layer, 542: conductive layer, 542a: conductive layer, 542b: conductive layer, 550: insulating layer, 550a: insulating layer, 550b: insulating layer, 550c: insulating layer, 550d: insulating layer, 560: conductive layer, 560a: conductive layer, 560b: conductive layer, 575: insulating layer, 580: insulating layer, 582: insulating layer, 583: insulating layer, 700: electronic component, 700A: electronic component, 700C: electronic component, 701: Substrate, 710: semiconductor device, 711: mold, 712: lead frame, 713: electrode pad, 714: wire, 715: drive circuit layer, 716: memory layer, 731: interposer, 732: conductive layer, 733: electrode, 734: package substrate, 735: semiconductor device, 960: processing device, 989: cache interface, 990: substrate, 991: ALU, 992: ALU controller, 993: instruction decoder, 994: interrupt controller roller, 995: timing controller, 996: register, 997: register controller, 998: bus interface, 999: cache, 5600: mainframe computer, 5610: rack, 5620: computer, 6500: electronic device, 6501: housing, 6502: display unit, 6503: power button, 6504: button, 6505: speaker, 6506: microphone, 6507: camera, 6508: light source, 6509: control device, 6600: electronic device, 6611 : Housing, 6612: Keyboard, 6613: Pointing device, 6614: External connection port, 6615: Display unit, 6616: Control device, 6800: Satellite, 6801: Airframe, 6802: Solar panel, 6803: Antenna, 6804: Planet, 6805: Secondary battery, 6807: Control device, 7000: Storage system, 7001: Host, 7001sb: Server, 7002: Storage control circuit, 7003: Storage, 7003md: Storage device,

Claims

a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch, and a sense amplifier; the sense amplifier has a first input / output terminal and a second input / output terminal; a first terminal of the first switch electrically connected to a first terminal of the second switch; a second terminal of the second switch is electrically connected to a first terminal of the third switch and to the first input / output terminal; a first terminal of the fourth switch electrically connected to a first terminal of the fifth switch; a second terminal of the fifth switch is electrically connected to a first terminal of the sixth switch and to the second input / output terminal; a control terminal of the first switch and a control terminal of the fifth switch are each electrically connected to a first wiring; a control terminal of the third switch and a control terminal of the sixth switch are each electrically connected to a second wiring; the sense amplifier is of a latch type, and has a function of amplifying a potential of one of the first input / output terminal or the second input / output terminal to a high level potential and amplifying a potential of the other of the first input / output terminal or the second input / output terminal to a low level potential in response to potentials of the first input / output terminal and the second input / output terminal, respectively; Amplification circuit. 　 In claim 1, each of the first switch, the second switch, and the fifth switch is an analog switch; the third switch includes a first transistor; the fourth switch includes a second transistor; the sixth switch includes a third transistor; one of a source and a drain of the first transistor corresponds to a first terminal of the third switch; a gate of the first transistor corresponds to a control terminal of the third switch; one of the source and the drain of the second transistor corresponds to a first terminal of the fourth switch; a gate of the second transistor corresponds to a control terminal of the fourth switch; one of a source and a drain of the third transistor corresponds to a first terminal of the sixth switch; The gate of the third transistor corresponds to the control terminal of the sixth switch. Amplification circuit. 　 In claim 2, each of the first transistor and the third transistor is an n-channel transistor, the second transistor is a p-channel transistor, Each of the first transistor to the third transistor has silicon in a channel formation region. Amplification circuit. 　 A semiconductor memory device comprising: an amplifier circuit according to any one of claims 1 to 3; and a memory cell; the memory cell includes a fourth transistor, a fifth transistor, and a capacitance element; a first terminal of the first switch and a first terminal of the second switch are each electrically connected to a third wiring; a first terminal of the fourth switch and a first terminal of the fifth switch are electrically connected to a fourth wiring; one of a source and a drain of the fourth transistor is electrically connected to a gate of the fifth transistor and a first terminal of the capacitive element; the other of the source and the drain of the fourth transistor is electrically connected to the third wiring; One of the source and the drain of the fifth transistor is electrically connected to the fourth wiring. memory circuit. 　 In claim 4, each of the fourth transistor and the fifth transistor includes an oxide semiconductor in a channel formation region; the oxide semiconductor contains one or more selected from indium, zinc, and an element M; The element M is one or more selected from aluminum, gallium, silicon, yttrium, tin, copper, vanadium, chromium, manganese, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, calcium, strontium, barium, cobalt, and antimony; memory circuit. 　 An electronic device comprising the memory circuit according to claim 5 and a housing.

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