Message processing method and apparatus

Abstract

Embodiments of the present disclosure provide a message processing method and apparatus. The method comprises: an interconnection network receiving a first request message and a first response message that are initiated by a first processing unit, wherein the first request message is sent to a second processing unit by the first processing unit, and the first response message is initiated after the first processing unit processes a second request message initiated by the second processing unit; allocating a first transmitting side virtual channel to the first request message, and allocating a second transmitting side virtual channel to the first response message, wherein the first transmitting side virtual channel and the second transmitting side virtual channel multiplex a physical channel in a periodic time-division mode; and respectively processing the first request message and the first response message by means of the first transmitting side virtual channel and the second transmitting side virtual channel.

Description

A message processing method and device

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This disclosure is based on Chinese patent application CN202311769695.5, filed on December 20, 2023, entitled “A Message Processing Method and Device,” and claims the priority of that patent application, all of whose disclosed contents are incorporated into this disclosure by reference. Technical Field

[0003] The present disclosure relates to the field of communication technologies, and in particular to a message processing method and apparatus. Background Art

[0004] With the rapid development of integrated circuits, chip integration is increasing, significantly improving performance while also placing higher demands on data exchange systems. However, traditional bus-based interconnect technologies suffer from poor performance, parallelism, and scalability, making them unable to meet the performance requirements of ultra-large-scale System-on-Chip (SoC). Consequently, interconnects have evolved from traditional buses to Network-on-Chip (NoC), which has become the preferred communication architecture for multi-core processors on a chip.

[0005] When designing an on-chip interconnect network, multiple considerations must be considered, including routing behavior, transaction types, flow control methods, consistency, and concurrency. When traffic is complex, even the slightest carelessness can lead to poor network performance or deadlock. Protocol-level deadlock is a major issue in NoC systems. This occurs when one type of transaction triggers another, causing interdependent packets in the cache to form a loop and prevent transactions from progressing. This deadlock can cause programs to wait indefinitely or consume significant resources, paralyzing the entire system with a lack of available resources and severely impacting system security and reliability.

[0006] Figure 1 is a schematic diagram of a protocol-level deadlock situation in the related art. As shown in Figure 1, if the network is flooded with request messages and these requests cannot be released before receiving a response, a loop dependency may be caused. In Figure 1, both processing units generate a series of request messages, which occupy all the buffer resources in the network. In this case, each processing unit needs to wait for the remote processing unit to respond to its own request before it can continue to process more unprocessed requests. If the above requests all use the same network buffer resources, the response message will not be received, resulting in a deadlock.

[0007] There is no solution yet for the problem of protocol-level deadlock caused by loop dependency in related technologies.

[0008] Summary of the Invention

[0009] The embodiments of the present disclosure provide a message processing method and apparatus to at least solve the problem of protocol-level deadlock caused by loop dependency in related technologies.

[0010] According to an embodiment of the present disclosure, a message processing method is provided, the method comprising: receiving a first request message and a first response message initiated by a first processing unit, wherein the first request message is sent by the first processing unit to a second processing unit, and the first response message is initiated by the first processing unit after processing the second request message initiated by the second processing unit; allocating a first sending-side virtual channel to the first request message, and allocating a second sending-side virtual channel to the first response message, wherein the first sending-side virtual channel and the second sending-side virtual channel use a periodic time-division multiplexing physical channel; processing the first request message and the first response message through the first sending-side virtual channel and the second sending-side virtual channel, respectively.

[0011] According to another embodiment of the present disclosure, a message processing device is also provided, which includes: a first receiving module, configured to receive a first request message and a first response message initiated by a first processing unit, wherein the first request message is sent by the first processing unit to the second processing unit, and the first response message is initiated by the first processing unit after processing the second request message initiated by the second processing unit; a first allocation module, configured to allocate a first sending side virtual channel to the first request message, and to allocate a second sending side virtual channel to the first response message, wherein the first sending side virtual channel and the second sending side virtual channel use periodic time-division multiplexing physical channels; a first processing module, configured to process the first request message and the first response message through the first sending side virtual channel and the second sending side virtual channel, respectively.

[0012] According to another embodiment of the present disclosure, a message processing system is also provided, which includes: a first processing unit, a second processing unit and an interconnection network, wherein the interconnection network is connected to the first processing unit and the second processing unit through a physical channel, wherein the first processing unit is configured to send a first request message and a first response message to the second processing unit through the interconnection network; the second processing unit is configured to send a second request message to the first processing unit through the interconnection network; the interconnection network is configured to receive the first request message and the first response message, allocate a first sending-side virtual channel to the first request message, allocate a second sending-side virtual channel to the first response message, and process the first request message and the first response message through the first sending-side virtual channel and the second sending-side virtual channel respectively, wherein the first sending-side virtual channel and the second sending-side virtual channel periodically time-division multiplex the physical channel.

[0013] According to another embodiment of the present disclosure, a computer-readable storage medium is provided, in which a computer program is stored. The computer program is configured to execute the steps of any one of the above method embodiments when running.

[0014] According to another embodiment of the present disclosure, an electronic device is provided, including a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to perform the steps in any one of the above method embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] FIG1 is a schematic diagram of a protocol-level deadlock situation in the related art;

[0016] FIG2 is a block diagram of the hardware structure of a computer device of the message processing method according to an embodiment of the present disclosure;

[0017] FIG3 is a flow chart of a message processing method according to an embodiment of the present disclosure;

[0018] FIG4 is a flow chart of a message processing method according to an optional embodiment of the present disclosure;

[0019] FIG5 is a block diagram of a message processing system according to an embodiment of the present disclosure;

[0020] FIG6 is a block diagram 1 of a message processing system according to an optional embodiment of the present disclosure;

[0021] FIG7 is a second block diagram of a message processing system according to an optional embodiment of the present disclosure;

[0022] FIG8 is a schematic diagram of an apparatus for preventing protocol-level deadlock in an interconnected network according to an embodiment of the present disclosure;

[0023] 9 is a flowchart of a method for resolving a protocol-level deadlock in an interconnected network according to an embodiment of the present disclosure;

[0024] FIG10 is a schematic diagram of a cache coherence message format according to an embodiment of the present disclosure;

[0025] FIG11 is a schematic structural diagram of a cache area according to an embodiment of the present disclosure;

[0026] FIG12 is a block diagram of a message processing apparatus according to an embodiment of the present disclosure;

[0027] FIG13 is a block diagram of a message processing apparatus according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0028] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings and in conjunction with embodiments.

[0029] It should be noted that the terms "first", "second", etc. in the specification and claims of the present disclosure and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0030] The method embodiments provided in the embodiments of the present disclosure can be executed in a computer device or a similar computing device. Taking operation on a computer device as an example, FIG2 is a hardware structure block diagram of a computer device of the message processing method of the embodiment of the present disclosure. As shown in FIG2 , the computer device may include one or more (only one is shown in FIG2 ) processors 102 (the processor 102 may include but is not limited to a processing device such as a microprocessor MCU or a programmable logic device) and a memory 104 for storing data, wherein the above-mentioned computer device may also include a transmission device 106 and an input and output device 108 for communication functions. It can be understood by those skilled in the art that the structure shown in FIG2 is only for illustration, and it does not limit the structure of the above-mentioned computer device. For example, the computer device may also include more or fewer components than those shown in FIG2 , or have a configuration different from that shown in FIG2 .

[0031] The memory 104 can be used to store computer programs, for example, software programs and modules of application software, such as the computer program corresponding to the message processing method in the embodiment of the present disclosure. The processor 102 executes various functional applications and single board matching by running the computer program stored in the memory 104, that is, implementing the above-mentioned method. The memory 104 may include a high-speed random access memory and may also include a non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some examples, the memory 104 may further include a memory remotely located relative to the processor 102, and these remote memories can be connected to the computer device via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0032] The transmission device 106 is used to receive or send data via a network. A specific example of the aforementioned network may include a wireless network provided by a communications provider of a computer device. In one embodiment, the transmission device 106 includes a network interface controller (NIC), which can be connected to other network devices via a base station to enable communication with the Internet. In another embodiment, the transmission device 106 may be a radio frequency (RF) module, which is used to communicate with the Internet wirelessly.

[0033] In this embodiment, a message processing method running on the above-mentioned computer device is provided. FIG3 is a flow chart of the message processing method according to an embodiment of the present disclosure. As shown in FIG3 , the message processing method is applied to an interconnected network. The flow chart includes the following steps:

[0034] Step S302: receiving a first request message and a first response message initiated by a first processing unit, wherein the first request message is sent by the first processing unit to the second processing unit, and the first response message is initiated by the first processing unit after processing the second request message initiated by the second processing unit;

[0035] The interconnection network in this embodiment is connected to the first processing unit and the second processing unit through physical channels, and data is transmitted between the first processing unit and the second processing unit through the physical channels.

[0036] Step S304: Allocate a first sending-side virtual channel to the first request message, and allocate a second sending-side virtual channel to the first response message, wherein the first sending-side virtual channel and the second sending-side virtual channel are time-division multiplexed on a physical channel in a periodic manner;

[0037] In the above step S304, different sending-side virtual channels are allocated to the request message and the response message, and different sending-side virtual channels use periodic time-division multiplexing of physical channels so that different types of messages go through different virtual channels.

[0038] Step S306 : Process the first request message and the first response message through the first sending-side virtual channel and the second sending-side virtual channel respectively.

[0039] Through the above steps S302 to S306, the first request message and the first response message initiated by the first processing unit are received, a first sending-side virtual channel is allocated to the first request message, and a second sending-side virtual channel is allocated to the first response message, wherein the first sending-side virtual channel and the second sending-side virtual channel multiplex the physical channel according to periodic time division; the first request message and the first response message are processed through the first sending-side virtual channel and the second sending-side virtual channel respectively, which can solve the problem of protocol-level deadlock caused by loop dependency in related technologies, make different types of messages go through different virtual channels, completely eliminate the dependency between cache area messages, and avoid the occurrence of protocol-level deadlock.

[0040] In one embodiment, before step S306, the method further includes: caching the first request message in a buffer corresponding to the first sender-side virtual channel in the sender-side buffer, and caching the first response message in a buffer corresponding to the second sender-side virtual channel in the sender-side buffer. In the sender-side buffer, different sender-side virtual channels correspond to different buffers.

[0041] In one embodiment, the above-mentioned step S306 may specifically include: sending the first request message in the cache area corresponding to the first sending side virtual channel to the second processing unit through the first sending side virtual channel, and sending the first response message in the cache area corresponding to the second sending side virtual channel to the second processing unit through the second sending side virtual channel, that is, for the receiving side, different types of messages are processed through different cache areas.

[0042] The interconnection network also includes a receiving side, and a receiving side buffer area is correspondingly set on the receiving side. FIG4 is a flow chart of a message processing method according to an optional embodiment of the present disclosure. As shown in FIG4 , the message processing on the receiving side includes the following steps:

[0043] Step S402: receiving a second response message initiated by the second processing unit, wherein the second response message is initiated by the second processing unit after processing the first request message;

[0044] Step S404: Allocate a first receiving-side virtual channel to the second request message, and allocate a second receiving-side virtual channel to the second response message, wherein the first receiving-side virtual channel and the second receiving-side virtual channel are time-division multiplexed on a physical channel in a periodic manner;

[0045] Step S406 : Process the second request message and the second response message through the first receiving-side virtual channel and the second receiving-side virtual channel respectively.

[0046] Through the above steps S402 to S406, for the messages on the receiving side, different types of messages go through different virtual channels, which can also completely eliminate the dependencies between the messages in the buffer area and avoid the occurrence of protocol level deadlock.

[0047] In one embodiment, before step S406, the method further includes: caching the second request message in a buffer corresponding to the first receiving-side virtual channel in the receiving-side buffer, and caching the second response message in a buffer corresponding to the second receiving-side virtual channel in the receiving-side buffer. In the receiving-side buffer, different receiving-side virtual channels correspond to different buffers.

[0048] In one embodiment, the above-mentioned step S406 may specifically include: sending the second request message in the cache area corresponding to the first receiving side virtual channel to the first processing unit through the first receiving side virtual channel, and sending the second response message in the cache area corresponding to the second receiving side virtual channel to the first processing unit through the second receiving side virtual channel, that is, the receiving side also processes different types of messages through different cache areas.

[0049] This embodiment further provides a message processing system. FIG5 is a block diagram of a message processing system according to an embodiment of the present disclosure. As shown in FIG5 , the system includes: a first processing unit 52, a second processing unit 54, and an interconnection network 56. The interconnection network 56 is connected to the first processing unit 52 and the second processing unit 54 through a physical channel, wherein:

[0050] The first processing unit 52 is configured to send a first request message and a first response message to the second processing unit 54 via the interconnection network 56;

[0051] The second processing unit 54 is configured to send a second request message to the first processing unit 52 via the interconnection network 56;

[0052] The interconnection network 56 is configured to receive the first request message and the first response message, allocate a first sending-side virtual channel to the first request message, allocate a second sending-side virtual channel to the first response message, and process the first request message and the first response message through the first sending-side virtual channel and the second sending-side virtual channel, respectively, wherein the first sending-side virtual channel and the second sending-side virtual channel periodically time-division multiplex a physical channel.

[0053] The message processing system in this embodiment can solve the problem of protocol-level deadlock caused by loop dependency in related technologies, allowing different types of messages to go through different virtual channels, completely eliminating the dependency between cache messages and avoiding the occurrence of protocol-level deadlock.

[0054] In one embodiment, the interconnection network 56 is further configured to cache the first request message in a cache area corresponding to the first sending side virtual channel in the sending side cache area, and cache the first response message in a cache area corresponding to the second sending side virtual channel in the sending side cache area.

[0055] In one embodiment, the interconnection network 56 is further configured to send the first request message in the buffer area corresponding to the first sending-side virtual channel to the second processing unit 54 through the first sending-side virtual channel, and send the first response message in the buffer area corresponding to the second sending-side virtual channel to the second processing unit 54 through the second sending-side virtual channel.

[0056] The second processing unit 54 is further configured to receive the first request message and the first response message.

[0057] In one embodiment, FIG6 is a block diagram of a message processing system according to an optional embodiment of the present disclosure. As shown in FIG6 , the interconnection network 56 includes a first virtual channel distributor 62 and a sending side buffer 64, wherein:

[0058] a first virtual channel allocator 62, configured to allocate the first sending-side virtual channel to the first request message based on the message type of the first request message, and allocate the second sending-side virtual channel to the first response message based on the message type of the first response message;

[0059] The sending side buffer area 64 is configured to store the first request message and the first response message.

[0060] In one embodiment, the second processing unit 54 is further configured to send a second response message to the first processing unit 52 through the interconnection network 56 after processing the first request message;

[0061] The interconnection network 56 is further configured to receive the second response message, allocate a first receiving-side virtual channel to the second request message, allocate a second receiving-side virtual channel to the second response message, and process the second request message and the second response message through the first receiving-side virtual channel and the second receiving-side virtual channel, respectively, wherein the first receiving-side virtual channel and the second receiving-side virtual channel periodically time-division multiplex a physical channel.

[0062] In one embodiment, the interconnection network 56 is further configured to cache the second request message in a cache area corresponding to the first receiving side virtual channel in the receiving side cache area, and cache the second response message in a cache area corresponding to the second receiving side virtual channel in the receiving side cache area.

[0063] In one embodiment, the interconnection network 56 is further configured to send the second request message in the buffer area corresponding to the first receiving-side virtual channel to the first processing unit 52 through the first receiving-side virtual channel, and send the second response message in the buffer area corresponding to the second receiving-side virtual channel to the first processing unit 52 through the second receiving-side virtual channel;

[0064] The first processing unit 52 is further configured to receive the second response message.

[0065] In one embodiment, FIG7 is a block diagram of a message processing system according to an optional embodiment of the present disclosure. As shown in FIG7 , the interconnection network 56 includes a second virtual channel distributor and the receiving side buffer area, wherein:

[0066] a second virtual channel allocator 72, configured to allocate the first receiving-side virtual channel to the second request message based on the message type of the second request message, and allocate the second receiving-side virtual channel to the second response message based on the message type of the second response message;

[0067] The receiving side buffer area 74 is configured to store the second request message and the second response message.

[0068] FIG8 is a schematic diagram of a device for preventing protocol-level deadlock in an interconnected network according to an embodiment of the present disclosure. As shown in FIG8 , the device includes: a processing unit (including a first processing unit and a second processing unit), a processing unit buffer, a virtual channel distributor (including a first virtual channel distributor and a second virtual channel distributor), virtual channels (including a first sending-side virtual channel, a second sending-side virtual channel, a first receiving-side virtual channel, and a second receiving-side virtual channel), a sending-side buffer, a receiving-side buffer, and a physical channel. In the above example, the processing unit represents a device that can initiate requests and receive responses. The processing unit buffer can store and track the request processing status and can only release the buffer request after receiving a response. The virtual channel distributor will allocate the corresponding message to the virtual channel of the corresponding buffer according to the type of the message. When sending multiple requests in the virtual channel buffer to the physical channel, a polling arbitration strategy is used. Only when the arbitration wins can the message be transmitted through the physical channel, and the switching granularity is the clock cycle. The virtual channel can transmit messages of the corresponding type. The transmit and receive buffers are variable-length queues composed of dedicated resources and public resources for different virtual channels. Each virtual channel's dedicated resources can only buffer packets of the corresponding type, while public resources can be dynamically allocated based on the current number of packets. The physical channel is the top-level physical interface bus during implementation.

[0069] FIG9 is a flowchart of a method for resolving a protocol-level deadlock in an interconnected network according to an embodiment of the present disclosure. As shown in FIG9 , the method includes:

[0070] S901: The first processing unit initiates a request transaction to the second processing unit, and at the same time, the second processing unit initiates a request transaction to the first processing unit.

[0071] S902 , the interconnection network receives a request transaction from the first processing unit and allocates a first sending-side virtual channel thereto; the interconnection network receives a request transaction from the second processing unit and allocates a first receiving-side virtual channel thereto.

[0072] S903: The interconnection network buffers the received request into a corresponding virtual channel buffer queue.

[0073] S904 , each virtual channel of the interconnection network time-division multiplexes the physical path according to a periodic time division, sends the request in the first sending side virtual channel buffer to the second processing unit, and sends the request in the first receiving side virtual channel buffer to the first processing unit.

[0074] S905, the first processing unit processes the request from the first receiving side virtual channel buffer area and sends a request processing completion response to the interconnection network; the second processing unit processes the request from the first sending side virtual channel buffer area and sends a request processing completion response to the interconnection network.

[0075] S906 , the interconnection network receives a response from the first processing unit and allocates a second sending-side virtual channel thereto, and the interconnection network receives a response from the second processing unit and allocates a second receiving-side virtual channel thereto.

[0076] S907 , each virtual channel of the interconnected network time-division multiplexes the physical path according to a periodic time division, sends the response in the second sending side virtual channel buffer to the second processing unit, and sends the response in the second receiving side virtual channel buffer to the first processing unit.

[0077] S908 , the first processing unit receives the response and releases the buffer resources occupied by the internal request, and the second processing unit receives the response and releases the buffer resources occupied by the internal request.

[0078] FIG10 is a schematic diagram of a cache coherence message format according to an embodiment of the present disclosure. As shown in FIG10 , the virtual channel allocator allocates virtual channels based on message virtual channel number information or message type.

[0079] Figure 11 is a schematic diagram of the structure of the cache area according to an embodiment of the present disclosure. As shown in Figure 11, the total buffer resources are divided into three categories. The first is VC0 dedicated resources; the second is VC1 dedicated resources; and the third is public resources. For new messages, the message type is identified and then the corresponding virtual channel dedicated resources are used for storage. VC0 dedicated resources cannot be used to store VC1 messages of the corresponding type. After the dedicated resources are used up, the messages are stored using public resources. This allows the entire virtual channel resources to be dynamically allocated based on the current traffic of different messages, improving resource utilization.

[0080] This embodiment further provides a message processing device, which is applied to an interconnected network. FIG12 is a block diagram of the message processing device according to an embodiment of the present disclosure. As shown in FIG12 , the device includes:

[0081] a first receiving module 122 configured to receive a first request message and a first response message initiated by a first processing unit, wherein the first request message is sent by the first processing unit to the second processing unit, and the first response message is initiated by the first processing unit after processing the second request message initiated by the second processing unit;

[0082] A first allocation module 124 is configured to allocate a first sending-side virtual channel to the first request message and allocate a second sending-side virtual channel to the first response message, wherein the first sending-side virtual channel and the second sending-side virtual channel use a periodic time-division multiplexing physical channel;

[0083] The first processing module 126 is configured to process the first request message and the first response message through the first sending-side virtual channel and the second sending-side virtual channel respectively.

[0084] In one embodiment, the apparatus further comprises:

[0085] a sending module configured to cache the first request message in a buffer area corresponding to the first sending-side virtual channel in a sending-side buffer area;

[0086] The first cache module is configured to cache the first response message into a cache area corresponding to the second sending-side virtual channel in the sending-side cache area.

[0087] In one embodiment, the first processing module 126 is further configured to send the first request message in the buffer area corresponding to the first sending side virtual channel to the second processing unit through the first sending side virtual channel; and send the first response message in the buffer area corresponding to the second sending side virtual channel to the second processing unit through the second sending side virtual channel.

[0088] FIG13 is a block diagram of a message processing device according to an embodiment of the present disclosure. As shown in FIG13 , the device further includes:

[0089] A second receiving module 132 is configured to receive a second response message initiated by the second processing unit, wherein the second response message is initiated by the second processing unit after processing the first request message;

[0090] A second allocation module 134 is configured to allocate a first receiving-side virtual channel to the second request message and allocate a second receiving-side virtual channel to the second response message, wherein the first receiving-side virtual channel and the second receiving-side virtual channel use a periodic time-division multiplexing physical channel;

[0091] The second processing module 136 is configured to process the second request message and the second response message through the first receiving-side virtual channel and the second receiving-side virtual channel respectively.

[0092] In one embodiment, the apparatus further comprises:

[0093] The second cache module is configured to cache the second request message into the cache area corresponding to the first receiving side virtual channel in the receiving side cache area; and cache the second response message into the cache area corresponding to the second receiving side virtual channel in the receiving side cache area.

[0094] In one embodiment, the second processing module 136 is further configured to send the second request message in the buffer area corresponding to the first receiving side virtual channel to the first processing unit through the first receiving side virtual channel; and send the second response message in the buffer area corresponding to the second receiving side virtual channel to the first processing unit through the second receiving side virtual channel.

[0095] An embodiment of the present disclosure further provides a computer-readable storage medium, in which a computer program is stored. The computer program is configured to execute the steps of any one of the above method embodiments when run.

[0096] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk, or an optical disk.

[0097] An embodiment of the present disclosure further provides an electronic device, including a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to perform the steps in any of the above method embodiments.

[0098] In an exemplary embodiment, the electronic device may further include a transmission device and an input / output device, wherein the transmission device is connected to the processor, and the input / output device is connected to the processor.

[0099] For specific examples in this embodiment, reference may be made to the examples described in the above embodiments and exemplary implementation modes, and this embodiment will not be described in detail here.

[0100] Obviously, those skilled in the art should understand that the modules or steps of the present disclosure described above can be implemented using a general-purpose computing device, they can be concentrated on a single computing device, or distributed across a network composed of multiple computing devices, they can be implemented using program code executable by the computing device, and thus, they can be stored in a storage device and executed by the computing device, and in some cases, the steps shown or described can be performed in a different order than herein, or they can be fabricated into separate integrated circuit modules, or multiple modules or steps can be fabricated into a single integrated circuit module for implementation. Thus, the present disclosure is not limited to any particular combination of hardware and software.

[0101] The foregoing description is merely a preferred embodiment of the present disclosure and is not intended to limit the present disclosure. Those skilled in the art will readily appreciate that various modifications and variations of the present disclosure are possible. Any modifications, equivalent substitutions, or improvements made within the principles of the present disclosure shall be included within the scope of protection of the present disclosure.

Claims

1. A message processing method, applied to an interconnection network, the method comprising: Receiving a first request message and a first response message initiated by a first processing unit, wherein the first request message is sent by the first processing unit to the second processing unit, and the first response message is initiated by the first processing unit after processing the second request message initiated by the second processing unit; Allocate a first sending side virtual channel for the first request message, and allocate a second sending side virtual channel for the first response message, wherein the first sending side virtual channel and the second sending side virtual channel use a physical channel in a periodic time division multiplexing manner; The first request message and the first response message are processed through the first sending-side virtual channel and the second sending-side virtual channel respectively.

2. The method according to claim 1, wherein: Before processing the first request message and the first response message through the first sending-side virtual channel and the second sending-side virtual channel respectively, the method further includes: Cache the first request message in a cache area corresponding to the first sending side virtual channel in a sending side cache area; The first response message is cached in a cache area corresponding to the second sending side virtual channel in the sending side cache area.

3. The method according to claim 2, wherein: Processing the first request message and the first response message through the buffer areas corresponding to the first sending side virtual channel and the second sending side virtual channel respectively includes: Sending the first request message in the buffer area corresponding to the first sending-side virtual channel to the second processing unit through the first sending-side virtual channel; The first response message in the buffer area corresponding to the second sending-side virtual channel is sent to the second processing unit through the second sending-side virtual channel.

4. The method according to any one of claims 1 to 3, wherein: The method further comprises: receiving a second response message initiated by the second processing unit, wherein the second response message is initiated by the second processing unit after processing the first request message; Allocate a first receiving side virtual channel for the second request message, and allocate a second receiving side virtual channel for the second response message, wherein the first receiving side virtual channel and the second receiving side virtual channel use a periodic time division multiplexing physical channel; The second request message and the second response message are processed through the first receiving side virtual channel and the second receiving side virtual channel respectively.

5. The method according to claim 4, wherein: Before processing the second request message and the second response message through the first receiving side virtual channel and the second receiving side virtual channel respectively, the method further includes: Cache the second request message into a cache area corresponding to the first receiving side virtual channel in a receiving side cache area; The second response message is cached in a cache area corresponding to the second receiving side virtual channel in the receiving side cache area.

6. The method according to claim 5, wherein: Processing the second request message and the second response message through the first receiving side virtual channel and the second receiving side virtual channel respectively includes: Sending the second request message in the buffer area corresponding to the first receiving-side virtual channel to the first processing unit through the first receiving-side virtual channel; The second response message in the buffer area corresponding to the second receiving-side virtual channel is sent to the first processing unit through the second receiving-side virtual channel.

7. A message processing device, applied to an interconnected network, comprising: A first receiving module is configured to receive a first request message and a first response message initiated by a first processing unit, wherein the first request message is sent by the first processing unit to the second processing unit, and the first response message is initiated by the first processing unit after processing the second request message initiated by the second processing unit; A first allocation module is configured to allocate a first sending side virtual channel to the first request message, and allocate a second sending side virtual channel to the first response message, wherein the first sending side virtual channel and the second sending side virtual channel use a physical channel in a periodic time division multiplexing manner; The first processing module is configured to process the first request message and the first response message through the first sending side virtual channel and the second sending side virtual channel respectively.

8. A message processing system, the system comprising: A first processing unit, a second processing unit, and an interconnection network, wherein the interconnection network is connected to the first processing unit and the second processing unit through a physical channel, wherein: The first processing unit is configured to send a first request message and a first response message to the second processing unit through the interconnection network; The second processing unit is configured to send a second request message to the first processing unit through the interconnection network; The interconnection network is configured to receive the first request message and the first response message, allocate a first sending side virtual channel for the first request message, allocate a second sending side virtual channel for the first response message, and process the first request message and the first response message through the first sending side virtual channel and the second sending side virtual channel respectively, wherein the first sending side virtual channel and the second sending side virtual channel periodically time-division multiplex a physical channel.

9. The system according to claim 8, wherein: The interconnection network is further configured to cache the first request message in a cache area corresponding to the first sending side virtual channel in the sending side cache area, and cache the first response message in a cache area corresponding to the second sending side virtual channel in the sending side cache area.

10. The system according to claim 9, wherein: The interconnection network is further configured to send the first request message in the buffer area corresponding to the first sending side virtual channel to the second processing unit through the first sending side virtual channel, and send the first response message in the buffer area corresponding to the second sending side virtual channel to the second processing unit through the second sending side virtual channel; The second processing unit is further configured to receive the first request message and the first response message.

11. The system according to claim 9, wherein: The interconnection network includes a first virtual channel distributor and the sending side buffer area, wherein: The first virtual channel allocator is configured to allocate the first sending side virtual channel to the first request message based on the message type of the first request message, and allocate the second sending side virtual channel to the first response message based on the message type of the first response message; The sending side buffer area is configured to store the first request message and the first response message.

12. A system according to any one of claims 8 to 11, wherein: The second processing unit is further configured to send a second response message to the first processing unit through the interconnection network after processing the first request message; The interconnection network is further configured to receive the second response message and allocate a first receiving side for the second request message. virtual channel, allocating a second receiving side virtual channel for the second response message, and processing the second request message and the second response message through the first receiving side virtual channel and the second receiving side virtual channel respectively, wherein the first receiving side virtual channel and the second receiving side virtual channel periodically time-division multiplex a physical channel.

13. The system according to claim 12, wherein: The interconnection network is further configured to cache the second request message into a cache area corresponding to the first receiving side virtual channel in the receiving side cache area, and cache the second response message into a cache area corresponding to the second receiving side virtual channel in the receiving side cache area.

14. The system according to claim 13, wherein: The interconnection network is further configured to send the second request message in the buffer area corresponding to the first receiving side virtual channel to the first processing unit through the first receiving side virtual channel, and send the second response message in the buffer area corresponding to the second receiving side virtual channel to the first processing unit through the second receiving side virtual channel; The first processing unit is further configured to receive the second response message.

15. The system of claim 13, wherein: The interconnection network includes a second virtual channel distributor and the receiving side buffer area, wherein: The second virtual channel allocator is configured to allocate the first receiving-side virtual channel to the second request message based on the message type of the second request message, and allocate the second receiving-side virtual channel to the second response message based on the message type of the second response message; The receiving side buffer area is configured to store the second request message and the second response message.

16. A computer-readable storage medium, wherein a computer program is stored in the storage medium, wherein: The computer program is configured to execute the method according to any one of claims 1 to 6 when executed.

17. An electronic device comprising a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to perform the method according to any one of claims 1 to 6.

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