Shift register, driving circuit, driving method, and display device

Abstract

A shift register (1200), a driving circuit (700a), a driving method, and a display device (800, 900), relating to the technical field of display. The shift register (1200) comprises: an input circuit (1210) configured to provide a first power supply voltage of a first power supply end (VGL) to a first node (N1) under the control of a first clock signal from a first clock end (CK), and provide an input signal from an input end (INPUT) to a second node (N2); a control circuit (1220) configured to provide a potential of the second node (N2) to a third node (N3) under the control of a first enable signal from a first enable end (EN_O), and provide the potential of the second node (N2) to a fourth node (N4) under the control of a second enable signal of a second enable end (EN_E); and an output circuit (1230) configured to output a signal by means of an output end (OUTPUT) under the control of the potentials of the first node (N1), the second node (N2), the third node (N3) and the fourth node (N4).

Description

Shift register, driving circuit, driving method and display device

[0001] This application claims priority to Chinese patent application No. 202311787035.X filed on December 22, 2023, the contents of which are incorporated herein by reference. Technical Field

[0002] The present disclosure relates to the field of display technology, and in particular to a shift register, a driving circuit, a driving method, and a display device. Background Art

[0003] Light-emitting diode (LED) displays are widely used in various scenarios in daily life. Different application scenarios have corresponding requirements for the display viewing angle. For example, in some privacy scenarios, the display needs to have a narrow display viewing angle to achieve anti-peeping. In some public scenarios, the display needs to have a wider display viewing angle to achieve screen information sharing. Therefore, there is an urgent need to develop display devices that have both anti-peeping and sharing modes. Summary of the Invention

[0004] The present disclosure provides a shift register, a driving circuit, a driving method and a display device.

[0005] According to a first aspect, the present disclosure provides a shift register, comprising: an input circuit, configured to provide a first power supply voltage from a first power supply terminal to a first node and an input signal from an input terminal to a second node under the control of a first clock signal from a first clock terminal; a control circuit, configured to provide the potential of a second node to a third node under the control of a first enable signal from a first enable terminal and to provide the potential of the second node to a fourth node under the control of a second enable signal from a second enable terminal; and an output circuit, configured to output a signal through an output terminal under the control of the potentials of the first node, the second node, the third node and the fourth node.

[0006] For example, the input circuit includes a scan input circuit, the control circuit includes a scan control circuit, the output circuit includes a scan output circuit, the input end includes a scan input end, the first node includes a first scan node, the second node includes a second scan node, the third node includes a third scan node, the fourth node includes a fourth scan node, and the output end includes a first scan output end, a second scan output end, and a third scan output end; wherein the scan input circuit is electrically connected to the scan input end, the first power supply end, and the first clock end, and is configured to provide the first power supply voltage of the first power supply end to the first scan node and provide the scan input signal from the scan input end to the second scan node under the control of the first clock signal; the scan control circuit is electrically connected to the first enable end, the second enable end, and the second scan node, and is configured to be controlled by the first enable signal. Under the control of the second enable signal, the potential of the second scan node is provided to the third scan node, and under the control of the second enable signal, the potential of the second scan node is provided to the fourth scan node; and a scan output circuit is electrically connected to the second clock terminal, the first power supply terminal, the second power supply terminal, the first scan node, the second scan node, the third scan node and the fourth scan node, and is configured to provide the second power supply voltage or the second clock signal to the first scan output terminal under the control of the potential of the first scan node and the potential of the third scan node, provide the second power supply voltage or the second clock signal to the second scan output terminal under the control of the potential of the first scan node and the potential of the fourth scan node, and provide the second power supply voltage or the second clock signal to the third scan output terminal under the control of the potential of the first scan node, the potential of the second scan node and the first power supply voltage.

[0007] For example, the scan control circuit includes: a first scan control sub-circuit, electrically connected to the first enable terminal, the second scan node and the third scan node, and configured to provide the potential of the second scan node to the third scan node under the control of the first enable signal; and a second scan control sub-circuit, electrically connected to the second enable terminal, the second scan node and the fourth scan node, and configured to provide the potential of the second scan node to the fourth scan node under the control of the second enable signal.

[0008] For example, the scan output circuit includes: a first scan output sub-circuit, electrically connected to the second clock terminal, the second power supply terminal, the first scan node and the third scan node, and configured to provide the second power supply voltage or the second clock signal to the first scan output terminal under the control of the potential of the first scan node and the potential of the third scan node; a second scan output sub-circuit, electrically connected to the second clock terminal, the second power supply terminal, the first scan node and the fourth scan node, and configured to provide the second power supply voltage or the second clock signal to the second scan output terminal under the control of the potential of the first scan node and the potential of the fourth scan node; and a third scan output sub-circuit, electrically connected to the second clock terminal, the first power supply terminal, the second power supply terminal, the first scan node and the second scan node, and configured to provide the second power supply voltage or the second clock signal to the third scan output terminal under the control of the potential of the first scan node, the potential of the second scan node and the first power supply voltage.

[0009] For example, the scan input circuit is also electrically connected to the second clock terminal and the second power supply terminal, and is configured to provide the second power supply voltage to the second scan node under the control of the potential of the first scan node and the second clock signal, and to provide the first clock signal to the first scan node under the control of the potential of the second scan node.

[0010] For example, the scan input circuit includes: a first scan transistor, a second scan transistor, a third scan transistor, a fourth scan transistor, and a fifth scan transistor; wherein the control electrode of the first scan transistor is electrically connected to the first clock terminal, the first electrode of the first scan transistor is electrically connected to the scan input terminal, and the second electrode of the first scan transistor is electrically connected to the second scan node; the control electrode of the second scan transistor is electrically connected to the first clock terminal, the first electrode of the second scan transistor is electrically connected to the first power supply terminal, and the second electrode of the second scan transistor is electrically connected to the first scan node; the control electrode of the third scan transistor is electrically connected to the second scan node, the first electrode of the third scan transistor is electrically connected to the first clock terminal, and the second electrode of the third scan transistor is electrically connected to the first scan node; the control electrode of the fourth scan transistor is electrically connected to the first scan node, the first electrode of the fourth scan transistor is electrically connected to the second power supply terminal, and the second electrode of the fourth scan transistor is electrically connected to the first electrode of the fifth scan transistor; and the control electrode of the fifth scan transistor is electrically connected to the second clock terminal, and the second electrode of the fifth scan transistor is electrically connected to the second scan node.

[0011] For example, the first scan control subcircuit includes a sixth scan transistor and a seventh scan transistor; wherein the control electrode of the sixth scan transistor is electrically connected to the first enable terminal, the first electrode of the sixth scan transistor is electrically connected to the second scan node, and the second electrode of the sixth scan transistor is electrically connected to the third scan node; and the control electrode and the first electrode of the seventh scan transistor are both electrically connected to the third scan node, and the second electrode of the seventh scan transistor is electrically connected to the first enable terminal.

[0012] For example, the second scan control subcircuit includes an eighth scan transistor and a ninth scan transistor; wherein the control electrode of the eighth scan transistor is electrically connected to the second enable terminal, the first electrode of the eighth scan transistor is electrically connected to the second scan node, and the second electrode of the eighth scan transistor is electrically connected to the fourth scan node; and the control electrode and the first electrode of the ninth scan transistor are both electrically connected to the fourth scan node, and the second electrode of the ninth scan transistor is electrically connected to the second enable terminal.

[0013] For example, the first scan output sub-circuit includes a tenth scan transistor, an eleventh scan transistor, a first scan capacitor and a second scan capacitor; wherein the control electrode of the tenth scan transistor is electrically connected to the first scan node, the first electrode of the tenth scan transistor is electrically connected to the second power supply terminal, and the second electrode of the tenth scan transistor is electrically connected to the first scan output terminal; the control electrode of the eleventh scan transistor is electrically connected to the third scan node, the first electrode of the eleventh scan transistor is electrically connected to the second clock terminal, and the second electrode of the eleventh scan transistor is electrically connected to the first scan output terminal; the first end of the first scan capacitor is electrically connected to the first scan node, and the second end of the first scan capacitor is electrically connected to the second power supply terminal; and the first end of the second scan capacitor is electrically connected to the third scan node, and the second end of the second scan capacitor is electrically connected to the first scan output terminal.

[0014] For example, the second scan output sub-circuit includes a twelfth scan transistor, a thirteenth scan transistor, a third scan capacitor and a fourth scan capacitor; wherein the control electrode of the twelfth scan transistor is electrically connected to the first scan node, the first electrode of the twelfth scan transistor is electrically connected to the second power supply terminal, and the second electrode of the twelfth scan transistor is electrically connected to the second scan output terminal; the control electrode of the thirteenth scan transistor is electrically connected to the fourth scan node, the first electrode of the thirteenth scan transistor is electrically connected to the second clock terminal, and the second electrode of the thirteenth scan transistor is electrically connected to the second scan output terminal; the first end of the third scan capacitor is electrically connected to the first scan node, the second end of the third scan capacitor is electrically connected to the second power supply terminal; and the first end of the fourth scan capacitor is electrically connected to the fourth scan node, and the second end of the fourth scan capacitor is electrically connected to the second scan output terminal.

[0015] For example, the third scan output sub-circuit includes a fourteenth scan transistor, a fifteenth scan transistor, a sixteenth scan transistor, a fifth scan capacitor and a sixth scan capacitor; wherein the control electrode of the fourteenth scan transistor is electrically connected to the first scan node, the first electrode of the fourteenth scan transistor is electrically connected to the second power supply terminal, and the second electrode of the fourteenth scan transistor is electrically connected to the third scan output terminal; the control electrode of the fifteenth scan transistor is electrically connected to the first electrode of the sixteenth scan transistor, the first electrode of the fifteenth scan transistor is electrically connected to the second clock terminal, and the second electrode of the fifteenth scan transistor is electrically connected to the third scan output terminal; the control electrode of the sixteenth scan transistor is electrically connected to the first power supply terminal, and the second electrode of the sixteenth scan transistor is electrically connected to the second scan node; the first end of the fifth scan capacitor is electrically connected to the first scan node, and the second end of the fifth scan capacitor is electrically connected to the second power supply terminal; and the first end of the sixth scan capacitor is electrically connected to the first electrode of the sixteenth scan transistor, and the second end of the sixth scan capacitor is electrically connected to the third scan output terminal.

[0016] For example, the input circuit includes a light-emitting control input circuit, the control circuit includes a light-emitting control circuit, the output circuit includes a light-emitting control output circuit, the input end includes a light-emitting control input end, the first node includes a first light-emitting control node, the second node includes a second light-emitting control node, the third node includes a third light-emitting control node, the fourth node includes a fourth light-emitting control node, and the output end includes a first light-emitting control output end, a second light-emitting control output end, and a third light-emitting control output end; wherein the light-emitting control input circuit is electrically connected to the light-emitting control input end, the first power supply end, and the first clock end, and is configured to provide the first power supply voltage to the first light-emitting control node and the light-emitting control input signal from the light-emitting control input end to the second light-emitting control node under the control of the first clock signal; the light-emitting control circuit is electrically connected to the first enable end, the second enable end, the first power supply end, the second power supply end, the second clock end, the first light-emitting control node, and the second light-emitting control node, and is configured to provide the potential of the second light-emitting control node to the third light-emitting control node under the control of the first enable signal. a control node, which provides the potential of the second light-emitting control node to the fourth light-emitting control node under the control of the second enable signal, and provides the second clock signal or the second power supply voltage to the fifth light-emitting control node under the control of the first power supply voltage, the potential of the second light-emitting control node, the potential of the first light-emitting control node and the second clock signal; and a light-emitting control output circuit, which is electrically connected to the first power supply terminal, the second power supply terminal, the second light-emitting control node, the third light-emitting control node, the fourth light-emitting control node and the fifth light-emitting control node, and is configured to provide the first power supply voltage or the second power supply voltage to the first light-emitting control output terminal under the control of the potential of the third light-emitting control node and the potential of the fifth light-emitting control node, provide the first power supply voltage or the second power supply voltage to the second light-emitting control output terminal under the control of the potential of the fourth light-emitting control node and the potential of the fifth light-emitting control node, and provide the first power supply voltage or the second power supply voltage to the third light-emitting control output terminal under the control of the potential of the second light-emitting control node, the potential of the fifth light-emitting control node and the first power supply voltage.

[0017] For example, the light-emitting control circuit includes: a first light-emitting control subcircuit, electrically connected to the first enable terminal, the second clock terminal, the second light-emitting control node and the third light-emitting control node, and configured to provide the potential of the second light-emitting control node to the third light-emitting control node under the control of the first enable signal and the second clock signal; a second light-emitting control subcircuit, electrically connected to the second enable terminal, the second clock terminal, the second light-emitting control node and the fourth light-emitting control node, and configured to provide the potential of the second light-emitting control node to the fourth light-emitting control node under the control of the second enable signal and the second clock signal; and a third light-emitting control subcircuit, electrically connected to the first power supply terminal, the second power supply terminal, the second clock terminal, the first light-emitting control node, the second light-emitting control node and the fifth light-emitting control node, and configured to provide the second clock signal or the second power supply voltage to the fifth light-emitting control node under the control of the first power supply voltage, the potential of the second light-emitting control node, the potential of the first light-emitting control node and the second clock signal.

[0018] For example, the light-emitting control output circuit includes: a first light-emitting control output sub-circuit, electrically connected to the first power supply terminal, the second power supply terminal, the third light-emitting control node and the fifth light-emitting control node, and configured to provide the first power supply voltage or the second power supply voltage to the first light-emitting control output terminal under the control of the potential of the third light-emitting control node and the potential of the fifth light-emitting control node; a second light-emitting control output sub-circuit, electrically connected to the first power supply terminal, the second power supply terminal, the fourth light-emitting control node and the fifth light-emitting control node, and configured to provide the first power supply voltage or the second power supply voltage to the second light-emitting control output terminal under the control of the potential of the fourth light-emitting control node and the potential of the fifth light-emitting control node; and a third light-emitting control output sub-circuit, electrically connected to the first power supply terminal, the second power supply terminal, the second light-emitting control node and the fifth light-emitting control node, and configured to provide the first power supply voltage or the second power supply voltage to the third light-emitting control output terminal under the control of the potential of the second light-emitting control node, the potential of the fifth light-emitting control node and the first power supply voltage.

[0019] For example, the light-emitting control input circuit is also electrically connected to the second clock terminal and the second power supply terminal, and is configured to provide the second power supply voltage to the second light-emitting control node under the control of the potential of the first light-emitting control node and the second clock signal, and to provide the first clock signal to the first light-emitting control node under the control of the potential of the second light-emitting control node.

[0020] For example, the light-emitting control input circuit includes: a first light-emitting control transistor, a second light-emitting control transistor, a third light-emitting control transistor, a fourth light-emitting control transistor, and a fifth light-emitting control transistor; wherein the control electrode of the first light-emitting control transistor is electrically connected to the first clock terminal, the first electrode of the first light-emitting control transistor is electrically connected to the light-emitting control input terminal, and the second electrode of the first light-emitting control transistor is electrically connected to the second light-emitting control node; the control electrode of the second light-emitting control transistor is electrically connected to the first clock terminal, the first electrode of the second light-emitting control transistor is electrically connected to the first power supply terminal, and the second electrode of the second light-emitting control transistor is electrically connected to the first light-emitting control node; the control electrode of the third light-emitting control transistor is electrically connected to the second light-emitting control node, the first electrode of the third light-emitting control transistor is electrically connected to the first clock terminal, and the second electrode of the third light-emitting control transistor is electrically connected to the first light-emitting control node; the control electrode of the fourth light-emitting control transistor is electrically connected to the first light-emitting control node, the first electrode of the fourth light-emitting control transistor is electrically connected to the second power supply terminal, and the second electrode of the fourth light-emitting control transistor is electrically connected to the first electrode of the fifth light-emitting control transistor; and the control electrode of the fifth light-emitting control transistor is electrically connected to the second clock terminal, and the second electrode of the fifth light-emitting control transistor is electrically connected to the second light-emitting control node.

[0021] For example, the first light-emitting control subcircuit includes a sixth light-emitting control transistor, a seventh light-emitting control transistor and a first light-emitting control capacitor; wherein the control electrode of the sixth light-emitting control transistor is electrically connected to the first enable terminal, the first electrode of the sixth light-emitting control transistor is electrically connected to the second light-emitting control node, and the second electrode of the sixth light-emitting control transistor is electrically connected to the third light-emitting control node; the control electrode and the first electrode of the seventh light-emitting control transistor are both electrically connected to the third light-emitting control node, and the second electrode of the seventh light-emitting control transistor is electrically connected to the first enable terminal; and the first terminal of the first light-emitting control capacitor is electrically connected to the third light-emitting control node, and the second terminal of the first light-emitting control capacitor is electrically connected to the second clock terminal.

[0022] For example, the second light-emitting control subcircuit includes an eighth light-emitting control transistor, a ninth light-emitting control transistor and a second light-emitting control capacitor; wherein the control electrode of the eighth light-emitting control transistor is electrically connected to the second enable terminal, the first electrode of the eighth light-emitting control transistor is electrically connected to the second light-emitting control node, and the second electrode of the eighth light-emitting control transistor is electrically connected to the fourth light-emitting control node; the control electrode and the first electrode of the ninth light-emitting control transistor are both electrically connected to the fourth light-emitting control node, and the second electrode of the ninth light-emitting control transistor is electrically connected to the second enable terminal; and the first terminal of the second light-emitting control capacitor is electrically connected to the fourth light-emitting control node, and the second terminal of the second light-emitting control capacitor is electrically connected to the second clock terminal.

[0023] For example, the third light-emitting control subcircuit includes a tenth light-emitting control transistor, an eleventh light-emitting control transistor, a twelfth light-emitting control transistor, a thirteenth light-emitting control transistor and a third light-emitting control capacitor; wherein the control electrode of the tenth light-emitting control transistor is electrically connected to the first power supply terminal, the first electrode of the tenth light-emitting control transistor is electrically connected to the first light-emitting control node, and the second electrode of the tenth light-emitting control transistor is electrically connected to the control electrode of the eleventh light-emitting control transistor; the first electrode of the eleventh light-emitting control transistor is electrically connected to the second clock terminal, and the second electrode of the eleventh light-emitting control transistor is electrically connected to the first electrode of the twelfth light-emitting control transistor; the control electrode of the twelfth light-emitting control transistor is electrically connected to the second clock terminal, and the second electrode of the twelfth light-emitting control transistor is electrically connected to the fifth light-emitting control node; the control electrode of the thirteenth light-emitting control transistor is electrically connected to the second light-emitting control node, the first electrode of the thirteenth light-emitting control transistor is electrically connected to the second power supply terminal, and the second electrode of the thirteenth light-emitting control transistor is electrically connected to the fifth light-emitting control node; and the first end of the third light-emitting control capacitor is electrically connected to the control electrode of the eleventh light-emitting control transistor, and the second end of the third light-emitting control capacitor is electrically connected to the second electrode of the eleventh light-emitting control transistor.

[0024] For example, the first light-emitting control output subcircuit includes a fourteenth light-emitting control transistor, a fifteenth light-emitting control transistor and a fourth light-emitting control capacitor; wherein the control electrode of the fourteenth light-emitting control transistor is electrically connected to the fifth light-emitting control node, the first electrode of the fourteenth light-emitting control transistor is electrically connected to the second power supply terminal, and the second electrode of the fourteenth light-emitting control transistor is electrically connected to the first light-emitting control output terminal; the control electrode of the fifteenth light-emitting control transistor is electrically connected to the third light-emitting control node, the first electrode of the fifteenth light-emitting control transistor is electrically connected to the first power supply terminal, and the second electrode of the fifteenth light-emitting control transistor is electrically connected to the first light-emitting control output terminal; and the first end of the fourth light-emitting control capacitor is electrically connected to the fifth light-emitting control node, and the second end of the fourth light-emitting control capacitor is electrically connected to the second power supply terminal.

[0025] For example, the second light-emitting control output subcircuit includes a sixteenth light-emitting control transistor, a seventeenth light-emitting control transistor and a fifth light-emitting control capacitor; wherein the control electrode of the sixteenth light-emitting control transistor is electrically connected to the fifth light-emitting control node, the first electrode of the sixteenth light-emitting control transistor is electrically connected to the second power supply terminal, and the second electrode of the sixteenth light-emitting control transistor is electrically connected to the second light-emitting control output terminal; the control electrode of the seventeenth light-emitting control transistor is electrically connected to the fourth light-emitting control node, the first electrode of the seventeenth light-emitting control transistor is electrically connected to the first power supply terminal, and the second electrode of the seventeenth light-emitting control transistor is electrically connected to the second light-emitting control output terminal; and the first end of the fifth light-emitting control capacitor is electrically connected to the fifth light-emitting control node, and the second end of the fifth light-emitting control capacitor is electrically connected to the second power supply terminal.

[0026] For example, the third light-emitting control output subcircuit includes an eighteenth light-emitting control transistor, a nineteenth light-emitting control transistor, a twentieth light-emitting control transistor and a sixth light-emitting control capacitor; wherein, the control electrode of the eighteenth light-emitting control transistor is electrically connected to the fifth light-emitting control node, the first electrode of the eighteenth light-emitting control transistor is electrically connected to the second power supply terminal, and the second electrode of the eighteenth light-emitting control transistor is electrically connected to the third light-emitting control output terminal; the control electrode of the nineteenth light-emitting control transistor is electrically connected to the first electrode of the twentieth light-emitting control transistor, the first electrode of the nineteenth light-emitting control transistor is electrically connected to the first power supply terminal, and the second electrode of the nineteenth light-emitting control transistor is electrically connected to the third light-emitting control output terminal; the control electrode of the twentieth light-emitting control transistor is electrically connected to the first power supply terminal, and the second electrode of the twentieth light-emitting control transistor is electrically connected to the second light-emitting control node; and the first terminal of the sixth light-emitting control capacitor is electrically connected to the control electrode of the nineteenth light-emitting control transistor, and the second terminal of the sixth light-emitting control capacitor is electrically connected to the second clock terminal.

[0027] According to the second aspect, the present disclosure provides a driving circuit, comprising M cascaded shift registers provided by embodiments of the present disclosure, where M is a positive integer greater than 1; the input end of the mth stage shift register is electrically connected to the output end of the m-1th stage shift register, 1<m≤M.

[0028] According to a third aspect, the present disclosure provides a display device, comprising a display panel; and a driving circuit provided by an embodiment of the present disclosure; wherein the display panel comprises a plurality of pixel units, each pixel unit comprises a first sub-pixel group and a second sub-pixel group, the first sub-pixel group is electrically connected to a first scanning output terminal and a first light-emitting control output terminal in the driving circuit, and the second sub-pixel group is electrically connected to a second scanning output terminal and a second light-emitting control output terminal in the driving circuit, wherein the light-emitting angles of the plurality of first sub-pixels included in the first sub-pixel group are smaller than the light-emitting angles of the plurality of second sub-pixels included in the second sub-pixel group, and the light-emitting angle is the angle between the emitted light and a direction perpendicular to the display panel.

[0029] According to the fourth aspect, the present disclosure provides a driving method, which is applied to the scan shift register provided by the embodiment of the present disclosure, including: the first enable signal from the first enable end is the first level and the second enable signal from the second enable end is the second level, controlling the first scan output end to output a pulse signal and the second scan output end to output a DC signal; the first enable signal is the second level and the second enable signal is the first level, controlling the first scan output end to output a DC signal and the second scan output end to output a pulse signal; and the first enable signal and the second enable signal are both the first level, controlling the first scan output end and the second scan output end to output pulse signals. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] FIG1A is a schematic structural diagram of a display panel according to an embodiment of the present disclosure;

[0031] FIG2A is a schematic structural diagram of an exemplary pixel circuit;

[0032] FIG2B is a schematic structural diagram of a pixel circuit of another example;

[0033] FIG3A is a schematic structural diagram of a scan shift register according to an embodiment of the present disclosure;

[0034] FIG3B is a schematic structural diagram of a light emitting control shift register according to an embodiment of the present disclosure;

[0035] FIG4A is a schematic structural diagram of a scan shift register according to another embodiment of the present disclosure;

[0036] FIG4B is a schematic structural diagram of a light emitting control shift register according to another embodiment of the present disclosure;

[0037] FIG5A is a schematic structural diagram of a scan shift register according to another embodiment of the present disclosure;

[0038] 5B and 5C are signal timing diagrams of the scan shift register in FIG5A ;

[0039] FIG6A is a schematic structural diagram of a light emitting control shift register according to another embodiment of the present disclosure;

[0040] 6B and 6C are signal timing diagrams of the light emitting control shift register in FIG. 6A ;

[0041] FIG7A is a schematic structural diagram of a driving circuit according to an embodiment of the present disclosure;

[0042] FIG7B is a schematic structural diagram of a gate driving circuit according to an embodiment of the present disclosure;

[0043] FIG7C is a schematic structural diagram of a light emitting control driving circuit according to an embodiment of the present disclosure;

[0044] FIG8A is a schematic structural diagram of a pixel unit according to an embodiment of the present disclosure;

[0045] FIG8B is a schematic structural diagram of a display device according to an embodiment of the present disclosure;

[0046] FIG9A is a schematic structural diagram of a pixel unit according to another embodiment of the present disclosure;

[0047] FIG9B is a schematic structural diagram of a display device according to another embodiment of the present disclosure;

[0048] FIG10 is a flowchart of a driving method according to an embodiment of the present disclosure;

[0049] FIG11A is a flowchart of a driving method according to another embodiment of the present disclosure;

[0050] FIG11B is a flowchart of a driving method according to another embodiment of the present disclosure; and

[0051] FIG12 is a schematic structural diagram of a shift register according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0052] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of them. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure. It should be noted that throughout the drawings, the same elements are represented by the same or similar figure marks. In the following description, some specific embodiments are only for descriptive purposes and should not be understood as any limitation to the present disclosure, but are only examples of the embodiments of the present disclosure. Conventional structures or configurations will be omitted when they may cause confusion in the understanding of the present disclosure. It should be noted that the shapes and sizes of the components in the figures do not reflect the actual size and proportion, but only illustrate the contents of the embodiments of the present disclosure.

[0053] Unless otherwise defined, technical or scientific terms used in the embodiments of the present disclosure shall have the same general meaning as those skilled in the art. The terms "first," "second," and similar terms used in the embodiments of the present disclosure do not denote any order, quantity, or importance, but are merely used to distinguish different components.

[0054] In addition, in the description of the embodiments of the present disclosure, the term "connected" or "connected to" may refer to a direct connection between two components or a connection between two components via one or more other components. In addition, the two components may be connected or coupled via a wired or wireless manner.

[0055] The source and drain of the switching transistor used in the embodiments of the present disclosure are symmetrical, so the source and drain are interchangeable. In the embodiments of the present disclosure, based on their functions, the gate can be referred to as the control electrode, one of the source and drain can be referred to as the first electrode, and the other of the source and drain can be referred to as the second electrode.

[0056] Furthermore, in the description of the embodiments of the present disclosure, the terms "first power supply voltage" and "second power supply voltage" are used solely to distinguish between the different amplitudes of the two power supply voltages. For example, the following description uses the example of a relatively high voltage as the "first power supply voltage" and a relatively low voltage as the "second power supply voltage." Those skilled in the art will appreciate that the present disclosure is not limited to this example.

[0057] It should be noted that in the description of the embodiments of the present disclosure, the symbol GOUT can represent both the gate drive signal and the level of the gate drive signal. Similarly, the symbol EOUT can represent both the light-emitting control signal and the level of the light-emitting control signal, the symbol GIN can represent both the scan input signal and the level of the scan input signal, the symbol EIN can represent both the light-emitting control input signal and the level of the light-emitting control input signal, the symbol VINT can represent both the predetermined initial voltage terminal and the voltage of the initial signal, the symbol ELVDD can represent both the power supply and the power supply voltage provided by the power supply, INPUT can represent both the input signal terminal and the input signal provided by the input signal terminal, OUTPUT can represent both the output signal terminal and the output signal output by the output signal terminal, and VGH and VGL can represent both the power supply terminal and the power supply voltage provided by the power supply terminal. For example, the first power supply terminal VGL can provide a low voltage, such as ground. The second power supply terminal VGH can provide a high level. The voltage provided by the first power supply terminal VGL is lower than the voltage of the second power supply terminal VGH. The following embodiments are the same as this, and similar parts are not repeated here.

[0058] FIG1A is a schematic structural diagram of a display panel according to an embodiment of the present disclosure.

[0059] 1A , the display panel 100 includes pixel units 101, 102, 103, and 104. It should be noted that the number of pixel units included in the display panel 100 is only for illustration, and the present disclosure does not limit the number of pixel units.

[0060] In the embodiment of the present disclosure, the pixel unit 101 , the pixel unit 102 , the pixel unit 103 and the pixel unit 104 have the same structure, and each pixel unit includes two groups of sub-pixel units.

[0061] The structure of the pixel unit 102 is taken as an example for description.

[0062] In the disclosed embodiment, the pixel unit 102 includes a first sub-pixel group 121 and a second sub-pixel group 122. For example, the first sub-pixel group 121 is used for anti-peeping display, and the second sub-pixel group 122 is used for normal display. The first sub-pixel group 121 includes three first sub-pixel units. For example, the three first sub-pixels can be a red sub-pixel, a blue sub-pixel, and a green sub-pixel. The second sub-pixel group 122 includes three second sub-pixel units. For example, the three second sub-pixels can be a red sub-pixel, a blue sub-pixel, and a green sub-pixel.

[0063] For example, the first sub-pixel group 121 includes a plurality of sub-pixels that are anti-peeping sub-pixels, and the second sub-pixel group 122 includes a plurality of sub-pixels that are display sub-pixels.

[0064] For example, the first sub-pixel group 121 and the second sub-pixel group 122 may also include two sub-pixels respectively. The present disclosure does not limit the number of sub-pixels included in each sub-pixel group.

[0065] In the embodiment of the present disclosure, the light emission angle of the first sub-pixel of the first sub-pixel group 121 is smaller than the light emission angle of the second sub-pixel of the second sub-pixel group 122. The light emission angle is the angle between the emitted light and the direction perpendicular to the display panel.

[0066] For example, a light shielding layer is provided on the surfaces of the first sub-pixel group 121 and the second sub-pixel group 122. Openings are provided in the light shielding layer to allow the sub-pixels of the first sub-pixel group 121 and the second sub-pixel group 122 to emit light normally. The area of ​​the opening corresponding to the first sub-pixel group 121 is smaller than the area of ​​the opening corresponding to the second sub-pixel group 122, so that the light emission range of the first sub-pixel in the first sub-pixel group 121 is smaller than the light emission range of the second sub-pixel in the second sub-pixel group 122.

[0067] For example, the light emission angle of the first sub-pixel of the first sub-pixel group 121 may be in the range of 0-45°, and the light emission angle of the second sub-pixel of the second sub-pixel group 122 may be in the range of 0-90°.

[0068] For example, when the first subpixel of the first subpixel group 121 emits light and the second subpixel of the second subpixel group 122 does not emit light, the maximum viewing angle of the user viewing the display screen can be 90°. That is, when the user views the display screen from the left or right side of the display screen, while the user can view the content on the display screen, the maximum angle between the user's line of sight and the direction perpendicular to the display panel is 45°, thereby achieving the purpose of screen privacy protection. When the first subpixel of the first subpixel group 121 does not emit light and the second subpixel of the second subpixel group 122 emits light, the maximum viewing angle of the user viewing the display screen can be 180°. That is, when the user views the display screen from the left or right side of the display screen, while the user can view the content on the display screen, the maximum angle between the user's line of sight and the direction perpendicular to the display panel is 90°, thereby achieving wide-viewing angle screen content display.

[0069] For example, when the first sub-pixel of the first sub-pixel group 121 and the second sub-pixel of the second sub-pixel group 122 both emit light, the maximum viewing angle of the user viewing the display screen is also 180°, achieving wide-viewing angle screen content display.

[0070] In the embodiment of the present disclosure, the first sub-pixel of the first sub-pixel group 121 and the second sub-pixel of the second sub-pixel group 122 are driven by different driving signals, respectively, so that one group of sub-pixels works while the other group of sub-pixels does not work.

[0071] Figure 2A is a schematic diagram of the structure of an example pixel circuit, and Figure 2B is a schematic diagram of the structure of another example pixel circuit. Figure 2A shows the pixel circuit of the first sub-pixel in the first sub-pixel group 121 in Figure 1, and Figure 2B shows the pixel circuit of the first sub-pixel in the second sub-pixel group 122 in Figure 1.

[0072] As shown in FIG2A and FIG2B , the pixel circuit of the sub-pixel may have a 7T1C structure, that is, each pixel unit includes 7 thin-film transistors TFT and 1 capacitor C. It should be noted that the pixel circuit of the sub-pixel may also have a circuit structure such as 8T1C and 7T2C. The pixel circuits shown in FIG2A and FIG2B are merely exemplary, and the present disclosure does not limit the circuit structure of the pixel circuit.

[0073] As shown in FIG2A , transistors T1 to T7 are all P-type transistors. The gates of transistors T1 , T2 , T4 , and T7 are controlled by a first gate drive signal GOUT_O, and the gates of transistors T5 and T6 are controlled by a first light emission control signal EOUT_O.

[0074] As shown in FIG2B , transistors T1 to T7 are all P-type transistors. The gates of transistors T1 , T2 , T4 , and T7 are controlled by a second gate drive signal GOUT_E, and the gates of transistors T5 and T6 are controlled by a second light emission control signal EOUT_E.

[0075] By controlling the first gate drive signal GOUT_O, the first light-emitting control signal EOUT_O, the second gate drive signal GOUT_E and the second light-emitting control signal EOUT_E, the working states of the first sub-pixel of the first sub-pixel group 121 and the second sub-pixel of the second sub-pixel group 122 shown in Figure 1 can be controlled.

[0076] The first gate driving signal GOUT_O and the second gate driving signal GOUT_E may be provided by a gate driving (Gate On Array, GOA) circuit, and the first emission control signal EOUT_O and the second emission control signal EOUT_E may be provided by an emission control signal driving (Emission On Array, EOA) circuit.

[0077] For example, the GOA circuit may include multiple cascaded GOA units, each level of which provides a drive signal to a row of pixel units in the pixel array. For example, the gate drive signal GOUT(n)_O shown in FIG2A may be the gate drive signal provided by the nth level of GOA units, and the gate drive signal Gate(n-1)_O may be the gate drive signal provided by the n-1th level of GOA units.

[0078] Similarly, the EOA circuit includes a plurality of cascaded EOA units, and each stage of EOA units provides a light emitting control signal EM to a row of pixel units in the pixel array.

[0079] Therefore, in one example, a pixel circuit composed of the pixel units shown in Figures 2A and 2B requires two sets of driving circuits to provide driving signals. Each set of driving circuits includes a GOA circuit and an EOA circuit. In a display device, two sets of driving circuits occupy a large space, which makes it difficult to narrow the display frame and also increases the power consumption of the display device.

[0080] In response to the above problems, the present disclosure provides a scanning shift register and a light-emitting control shift register, which control the signal outputs of the scanning shift register and the light-emitting control shift register through an enable signal, so that a GOA circuit and an EOA circuit can provide gate drive signals and light-emitting control signals to two sub-pixel groups respectively.

[0081] Figure 3A is a schematic structural diagram of a scan shift register according to an embodiment of the present disclosure.

[0082] As shown in FIG. 3A , the scan shift register 300 a includes a scan input circuit 310 , a scan control circuit 320 , and a scan output circuit 330 .

[0083] In the embodiment of the present disclosure, the scan input circuit 310 is electrically connected to a scan input terminal GIN_n, a first power terminal VGL, and a first clock terminal CK. The scan input circuit 310 is configured to provide a first power supply voltage VGL from the first power terminal VGL to a first scan node SN1 and a scan input signal GIN_n from the scan input terminal GIN_n to a second scan node SN2 under the control of a first clock signal CK from the first clock terminal CK.

[0084] In the embodiment of the present disclosure, the scan control circuit 320 is electrically connected to the first enable terminal EN_O, the second enable terminal EN_E, and the second scan node SN2. The scan control circuit 320 is configured to provide the potential of the second scan node SN2 to the third scan node SN3 under the control of the first enable signal EN_O from the first enable terminal EN_O, and to provide the potential of the second scan node SN2 to the fourth scan node SN4 under the control of the second enable signal EN_E from the second enable terminal EN_E.

[0085] In the embodiment of the present disclosure, the scan output circuit 330 is electrically connected to the second clock terminal CB, the first power supply terminal VGL, the second power supply terminal VGH, the first scan node SN1, the second scan node SN2, the third scan node SN3, and the fourth scan node SN4. The scan output circuit 330 is configured to provide the second power supply voltage VGH of the second power supply terminal VGH or the second clock signal CB from the second clock terminal CB to the first scan output terminal GOUT_O under the control of the potential of the first scan node SN1 and the potential of the third scan node SN3, provide the second power supply voltage VGH or the second clock signal CB to the second scan output terminal GOUT_E under the control of the potential of the first scan node SN1 and the potential of the fourth scan node SN4, and provide the second power supply voltage VGH or the second clock signal CB to the third scan output terminal GOUT_n under the control of the potential of the first scan node SN1, the potential of the second scan node SN2, and the first power supply voltage VGL.

[0086] In the embodiment of the present disclosure, the scan shift register 300a may be a driving unit in a gate driving circuit and may output a first gate driving signal GOUT_O, a second gate driving signal GOUT_E, and a third gate driving signal GOUT_n.

[0087] For example, the first gate driving signal GOUT_O is used to drive the pixel circuit of Figure 2A, and the second gate driving signal GOUT_E is used to drive the pixel circuit of Figure 2B. The third gate driving signal GOUT_n is provided to the next stage scan shift register.

[0088] In the embodiment of the present disclosure, the scan input signal GIN_n of the scan input terminal GIN_n may be the third gate drive signal GOUT_n-1 output by the previous-stage scan shift register, and the third scan output terminal GOUT_n may be the scan input signal GIN_n+1 provided by the next-stage scan shift register in the drive circuit. When the scan shift register 300a is the first-stage scan shift register, the scan input signal GIN_1 may be a gate start vertical (GSTV) signal.

[0089] In the disclosed embodiment, the output of the first scan output terminal GOUT_O is controlled by the first enable terminal EN_O, and the output of the second scan output terminal GOUT_E is controlled by the second enable terminal EN_E. This controls the drive of two groups of sub-pixels in the display panel, achieving both anti-peeping display and normal display. Using a single shift register 300a as a drive unit to provide gate drive signals for both groups of sub-pixels reduces the space occupied by the gate drive circuit, facilitating a narrower display frame.

[0090] It should be noted that the first node SN1 , the second node SN2 , the third node SN3 and the fourth node SN4 do not represent actual components, but represent junction points of related circuit connections in the circuit diagram.

[0091] FIG3B is a schematic structural diagram of a light emitting control shift register according to an embodiment of the present disclosure.

[0092] As shown in FIG. 3B , the light emission control shift register 300 b includes a light emission control input circuit 340 , a light emission control circuit 350 , and a light emission control output circuit 360 .

[0093] In the embodiment of the present disclosure, the light emission control input circuit 340 is electrically connected to the light emission control input terminal EIN, the first power supply terminal VGL, and the first clock terminal CK. The light emission control input circuit 340 is configured to provide the first power supply voltage VGL from the first power supply terminal VGL to the first light emission control node EMN1 and provide the light emission control input signal EIN_n from the light emission control input terminal EIN_n to the second light emission control node EMN2 under the control of the first clock signal CK from the first clock terminal CK.

[0094] In the embodiment of the present disclosure, the light control circuit 350 is electrically connected to a first enable terminal EN_O, a second enable terminal EN_E, a first power supply terminal VGL, a second power supply terminal VGH, a second clock terminal CB, a first light control node EMN1, a second light control node EMN2, a third light control node EMN3, a fourth light control node EMN4, and a fifth light control node EMN5. The light control circuit 350 is configured to, under the control of a first enable signal EN_O from the first enable terminal EN_O, provide a potential of the second light control node EMN2 to the third light control node EMN3; under the control of a second enable signal EN_E from the second enable terminal EN_E, provide a potential of the second light control node EMN2 to the fourth light control node EMN4; and, under the control of the first power supply voltage VGL, the potential of the second light control node EMN2, the potential of the first light control node EMN1, and a second clock signal CB from the second clock terminal CB, provide a second clock signal CB or a second power supply voltage VGH from the second power supply terminal VGH to the fifth light control node EMN5.

[0095] In the embodiment of the present disclosure, the emission control output circuit 360 is electrically connected to a first power supply terminal VGL, a second power supply terminal VGH, a second emission control node EMN2, a third emission control node EMN3, a fourth emission control node EMN4, and a fifth emission control node EMN5. The emission control output circuit 360 is configured to provide the first power supply voltage VGL or the second power supply voltage VGH to the first emission control output terminal EOUT_O under the control of the potentials of the third emission control node EMN3 and the fifth emission control node EMN5, to provide the first power supply voltage VGL or the second power supply voltage VGH to the second emission control output terminal EOUT_E under the control of the potentials of the fourth emission control node EMN4 and the fifth emission control node EMN5, and to provide the first power supply voltage VGL or the second power supply voltage VGH to the third emission control output terminal EOUT_n under the control of the potentials of the second emission control node EMN2, the fifth emission control node EOUT_5, and the first power supply voltage VGL.

[0096] In the embodiment of the present disclosure, the light emission control shift register 300b may be a driving unit in the light emission control driving circuit and may output a first light emission control driving signal EOUT_O, a second light emission control driving signal EOUT_E, and a third light emission control driving signal EOUT_n.

[0097] For example, the first light emission control driving signal EOUT_O is used to drive the pixel circuit of Figure 2A, and the second light emission control driving signal EOUT_E is used to drive the pixel circuit of Figure 2B. The third light emission control driving signal EOUT_n is provided to the next stage light emission control shift register.

[0098] In the embodiment of the present disclosure, the light-emitting control input signal EIN_n of the light-emitting control input terminal EIN_n may be the third light-emitting control signal EOUT_n-1 output by the previous-stage light-emitting control shift register, and the third light-emitting control output terminal EOUT_n may be the light-emitting control input signal EIN_n+1 provided by the next-stage light-emitting control shift register in the driving circuit. When the light-emitting control shift register 300b is the first-stage light-emitting control shift register, the light-emitting control input signal EIN_1 may be the emission start vertical (ESTV) signal.

[0099] In the disclosed embodiment, the output of the first emission control output terminal EOUT_O is controlled by the first enable terminal EN_O, and the output of the second emission control output terminal EOUT_E is controlled by the second enable terminal EN_E. This controls the driving of two groups of sub-pixels in the display panel, achieving both anti-peeping display and normal display. Using a single emission control shift register 300b as a drive unit to provide emission control signals to both groups of sub-pixels reduces the space occupied by the emission control drive circuit, facilitating a narrower display frame.

[0100] It should be noted that the first node EMN1 , the second node EMN2 , the third node EMN3 , the fourth node EMN4 and the fifth node EMN5 do not represent actual components, but represent junction points of related circuit connections in the circuit diagram.

[0101] In the embodiment of the present disclosure, the scanning shift register 300a and the light-emitting control shift register 300b may share a clock signal terminal, a power supply terminal, and an enable terminal, or may separately provide a clock signal terminal, a power supply terminal, and an enable terminal for the scanning shift register 300a and the light-emitting control shift register 300b. For example, the first clock terminal CK may include a first clock terminal GCK and a first clock terminal ECK, and the second clock terminal CB may include a second clock terminal GCB and a second clock terminal ECB. The first clock terminal GCK and the second clock terminal GCB are used to provide a clock signal for the scanning shift register 300a, and the first clock terminal ECK and the second clock terminal ECB are used to provide a clock signal for the light-emitting control shift register 300b.

[0102] FIG4A is a schematic structural diagram of a scan shift register according to another embodiment of the present disclosure.

[0103] As shown in FIG4A , the scan shift register 400 a includes a scan input circuit 410, a scan control circuit 420, and a scan output circuit 430. The scan input circuit 410, the scan control circuit 420, and the scan output circuit 430 are similar to the scan input circuit 310, the scan control circuit 320, and the scan output circuit 330 described above, respectively. For the sake of simplicity, the same parts are not repeated here in this disclosure.

[0104] In the embodiment of the present disclosure, the scan input circuit 410 is electrically connected to the scan input terminal GIN_n, the first power terminal VGL, the first clock terminal CK, the second clock terminal CB, and the second power terminal VGH. The scan input circuit 410 is configured to provide the second power supply voltage VGH to the second scan node SN2 under the control of the potential of the first scan node SN1 and the second clock signal CB, and to provide the first clock signal CK to the first scan node SN1 under the control of the potential of the second scan node SN2.

[0105] In the embodiment of the present disclosure, the scan control circuit 420 includes a first scan control sub-circuit 421 and a second scan control sub-circuit 422 .

[0106] The first scan control subcircuit 421 is electrically connected to the first enable terminal EN_O, the second scan node SN2 and the third scan node SN3 and is configured to provide the potential of the second scan node SN2 to the third scan node SN3 under the control of the first enable signal EN_O.

[0107] The second scan control subcircuit 422 is electrically connected to the second enable terminal EN_E, the second scan node SN2 and the fourth scan node SN4 and is configured to provide the potential of the second scan node SN2 to the fourth scan node SN4 under the control of the second enable signal EN_E.

[0108] In the disclosed embodiment, the first enable signal EN_O can control the connection between the second scan node SN2 and the third scan node SN3. The second enable signal EN_E can control the connection between the second scan node SN2 and the fourth scan node SN4. For example, when the second scan node SN2 and the third scan node SN3 are connected, the potential of the second scan node SN2 is provided to the fourth scan node SN4. When the second scan node SN2 and the fourth scan node SN4 are connected, the potential of the second scan node SN2 is provided to the fourth scan node SN4.

[0109] In the embodiment of the present disclosure, the first enable signal EN_O and the second enable signal EN_E may be signals indicating the display mode of the display device. For example, the first enable signal EN_O may be used to control the display device to be in anti-peeping mode, and the scanning shift register 400a may be driven to drive the anti-peeping sub-pixel. The second enable signal EN_E may be used to control the display device to be in normal mode, and the scanning shift register 400a may be driven to drive the display sub-pixel.

[0110] In the embodiment of the present disclosure, the scan output circuit 430 includes a first scan output sub-circuit 431 , a second scan output sub-circuit 432 , and a third scan output sub-circuit 433 .

[0111] The first scan output sub-circuit 431 is electrically connected to the second clock terminal CB, the second power supply terminal VGH, the first scan node SN1, and the third scan node SN3. The first scan output sub-circuit 431 is configured to provide the second power supply voltage VGH or the second clock signal CB to the first scan output terminal GOUT_O under the control of the potential of the first scan node SN1 and the potential of the third scan node SN3.

[0112] The second scan output sub-circuit 432 is electrically connected to the second clock terminal CB, the second power supply terminal VGH, the first scan node SN1, and the fourth scan node SN4. The second scan output sub-circuit 432 is configured to provide the second power supply voltage VGH or the second clock signal CB to the second scan output terminal GOUT_E under the control of the potential of the first scan node SN1 and the potential of the fourth scan node SN4.

[0113] The third scan output sub-circuit 433 is electrically connected to the second clock terminal CB, the first power terminal VGL, the second power terminal VGH, the first scan node SN1, and the second scan node SN2. The third scan output sub-circuit 433 is configured to provide the second power supply voltage VGH or the second clock signal CB to the third scan output terminal GOUT_n under the control of the potential of the first scan node SN1, the potential of the second scan node SN2, and the first power supply voltage VGL.

[0114] In the disclosed embodiment, the first scan output terminal GOUT_O outputs a first gate drive signal GOUT_O for driving the anti-peep sub-pixel. The second scan output terminal GOUT_E outputs a second gate drive signal GOUT_E for driving the display sub-pixel. The third scan output terminal GOUT_n outputs a third gate drive signal GOUT_n for driving the next stage scan shift register.

[0115] In the embodiment of the present disclosure, the second power supply voltage VGH provides a high potential for the first gate drive signal GOUT_O, the second gate drive signal GOUT_E and the third gate drive signal GOUT_n, and the second clock signal CB provides a low potential for the first gate drive signal GOUT_O, the second gate drive signal GOUT_E and the third gate drive signal GOUT_n.

[0116] FIG4B is a schematic structural diagram of a light emitting control shift register according to another embodiment of the present disclosure.

[0117] As shown in FIG4B , the light-emission control shift register 400 b includes a light-emission control input circuit 440, a light-emission control circuit 450, and a light-emission control output circuit 460. The light-emission control input circuit 440, the light-emission control circuit 450, and the light-emission control output circuit 460 are similar to the light-emission control input circuit 340, the light-emission control circuit 350, and the light-emission control output circuit 360 described above, respectively. For the sake of simplicity, the same parts are not repeated here in this disclosure.

[0118] In the embodiment of the present disclosure, the light-emission control input circuit 440 is electrically connected to the light-emission control input terminal EIN_n, the first clock terminal CK, the second clock terminal CB, the first power supply terminal VGL, and the second power supply terminal VGH. The light-emission control input circuit 440 is configured to provide the second power supply voltage VGH to the second light-emission control node EMN2 under the control of the potential of the first light-emission control node EMN1 and the second clock signal CB, and to provide the first clock signal CK to the first light-emission control node EMN1 under the control of the potential of the second light-emission control node EMN2.

[0119] In the embodiment of the present disclosure, the light emitting control circuit 450 includes a first light emitting control sub-circuit 451 , a second light emitting control sub-circuit 452 and a third light emitting control sub-circuit 453 .

[0120] The first light control sub-circuit 451 is electrically connected to a first enable terminal EN_O, a second clock terminal, a second light control node EMN2, and a third light control node EMN3. The first light control sub-circuit 451 is configured to provide a potential at the second light control node EMN2 to the third light control node EMN3 under the control of a first enable signal EN_O and a second clock signal CB.

[0121] The second light-emission control subcircuit 452 is electrically connected to the second enable terminal EN_E, the second clock terminal CB, the second light-emission control node EMN2, and the fourth light-emission control node EMN4. The second light-emission control subcircuit 452 is configured to provide the potential of the second light-emission control node EMN2 to the fourth light-emission control node EMN4 under the control of the second enable signal EN_E and the second clock signal CB.

[0122] The third light-emission control sub-circuit 453 is electrically connected to the first power supply terminal VGL, the second power supply terminal VGH, the second clock terminal CB, the first light-emission control node EMN1, the second light-emission control node EMN2, and the fifth light-emission control node EMN5. The third light-emission control sub-circuit 453 is configured to provide the second clock signal CB or the second power supply voltage VGH to the fifth light-emission control node EMN5 under the control of the first power supply voltage VGL, the potential of the second light-emission control node EMN2, the potential of the first light-emission control node EMN1, and the second clock signal CB.

[0123] In the embodiment of the present disclosure, the connection between the second emission control node EMN2 and the third emission control node EMN3 can be controlled by a first enable signal EN_O. The connection between the second emission control node EMN2 and the fourth emission control node EMN4 can be controlled by a second enable signal EN_E. For example, when the second emission control node EMN2 and the third emission control node EMN3 are electrically connected, the potential of the second emission control node EMN2 is provided to the third emission control node EMN3. When the second emission control node EMN2 and the fourth emission control node EMN4 are electrically connected, the potential of the second emission control node EMN2 is provided to the fourth emission control node EMN4.

[0124] In the embodiment of the present disclosure, the first enable signal EN_O and the second enable signal EN_E may be signals indicating the display mode of the display device. For example, based on the first enable signal EN_O, the display device may be controlled to be in anti-peeping mode, and the light-emission control shift register 400b may drive the anti-peeping sub-pixel. Based on the second enable signal EN_E, the display device may be controlled to be in normal mode, and the light-emission control shift register 400a may drive the display sub-pixel.

[0125] In the embodiment of the present disclosure, the light emission control output circuit 460 includes a first light emission control output sub-circuit 461 , a second light emission control output sub-circuit 462 and a third light emission control output sub-circuit 463 .

[0126] The first light emission control output sub-circuit 461 is electrically connected to the first power supply terminal VGL, the second power supply terminal VGH, the third light emission control node EMN3, and the fifth light emission control node EMN5. The first light emission control output sub-circuit 461 is configured to provide the first power supply voltage VGL or the second power supply voltage VGH to the first light emission control output terminal EOUT_O under the control of the potential of the third light emission control node EMN3 and the potential of the fifth light emission control node EMN5.

[0127] The second light-emission control output sub-circuit 462 is electrically connected to the first power supply terminal VGL, the second power supply terminal VGH, the fourth light-emission control node EMN4, and the fifth light-emission control node EMN5. The second light-emission control output sub-circuit 462 is configured to provide the first power supply voltage VGL or the second power supply voltage VGH to the second light-emission control output terminal EOUT_E under the control of the potential of the fourth light-emission control node EMN4 and the potential of the fifth light-emission control node EMN5.

[0128] The third light-emission control output sub-circuit 463 is electrically connected to the first power supply terminal VGL, the second power supply terminal VGH, the second light-emission control node EMN2, and the fifth light-emission control node EMN5. The third light-emission control output sub-circuit 463 is configured to provide the first power supply voltage VGL or the second power supply voltage VGH to the third light-emission control output terminal EOUT_n under the control of the potential of the second light-emission control node EMN2, the potential of the fifth light-emission control node EMN5, and the first power supply voltage VGL.

[0129] In the disclosed embodiment, the first light-emitting control output terminal EOUT_O outputs a first light-emitting control signal EOUT_O for driving the anti-peeping sub-pixel. The second light-emitting control output terminal EOUT_E outputs a second light-emitting control signal EOUT_E for driving the display sub-pixel. The third light-emitting control output terminal EOUT_n outputs a third light-emitting control signal EOUT_n for driving the next-stage light-emitting control shift register.

[0130] In the embodiment of the present disclosure, the second power supply voltage VGH provides a high potential for the first light-emitting control signal EOUT_O, the second light-emitting control signal EOUT_E and the third light-emitting control signal EOUT_n, and the second clock signal CB provides a low potential for the first light-emitting control signal EOUT_O, the second light-emitting control signal EOUT_E and the third light-emitting control signal EOUT_n.

[0131] FIG5A is a schematic structural diagram of a scan shift register according to another embodiment of the present disclosure.

[0132] As shown in FIG. 5A , the scan shift register 500 includes a scan input circuit 510 , a scan control circuit 520 , and a scan output circuit 530 .

[0133] The scan control circuit 520 includes a first scan control sub-circuit 521 and a second scan control sub-circuit 522. The scan output circuit 530 includes a first scan output sub-circuit 531, a second scan output sub-circuit 532 and a second scan output sub-circuit 533.

[0134] The scan input circuit 510, the scan control circuit 520, and the scan output circuit 530 are similar to the scan input circuit 410, the scan control circuit 420, and the scan output circuit 430 described above, respectively. The first scan control sub-circuit 521 and the second scan control sub-circuit 522 are similar to the first scan control sub-circuit 421 and the second scan control sub-circuit 422 described above, respectively. The first scan output sub-circuit 531, the second scan output sub-circuit 532, and the second scan output sub-circuit 533 are similar to the first scan output sub-circuit 431, the second scan output sub-circuit 432, and the second scan output sub-circuit 433 described above, respectively. For the sake of brevity, identical parts of this disclosure are not repeated here.

[0135] In the embodiment of the present disclosure, the scan input circuit 510 includes a first scan transistor T1, a second scan transistor T2, a third scan transistor T3, a fourth scan transistor T4, and a fifth scan transistor T5. The first scan transistor T1, the second scan transistor T2, the third scan transistor T3, the fourth scan transistor T4, and the fifth scan transistor T5 are P-type transistors and are used as switching transistors.

[0136] The control electrode of the first scan transistor T1 is electrically connected to the first clock terminal GCK, the first electrode of the first scan transistor T1 is electrically connected to the scan input terminal GIN_n, and the second electrode of the first scan transistor T1 is electrically connected to the second scan node SN2. The control electrode of the second scan transistor T2 is electrically connected to the first clock terminal GCK, the first electrode of the second scan transistor T2 is electrically connected to the first power supply terminal VGL, and the second electrode of the second scan transistor T2 is electrically connected to the first scan node SN1. The control electrode of the third scan transistor T3 is electrically connected to the second scan node SN2, the first electrode of the third scan transistor T3 is electrically connected to the first clock terminal GCK, and the second electrode of the third scan transistor T3 is electrically connected to the first scan node SN1.

[0137] A control electrode of the fourth scan transistor T4 is electrically connected to the first scan node SN1, a first electrode of the fourth scan transistor T4 is electrically connected to the second power supply terminal VGH, and a second electrode of the fourth scan transistor T4 is electrically connected to the first electrode of the fifth scan transistor bar. A control electrode of the fifth scan transistor T5 is electrically connected to the second clock terminal GCB, and a second electrode of the fifth scan transistor T5 is electrically connected to the second scan node SN2.

[0138] In the embodiment of the present disclosure, the first scan control sub-circuit 521 includes a sixth scan transistor T6 and a seventh scan transistor T7. The sixth scan transistor T6 and the seventh scan transistor T7 are P-type transistors and are used as switching transistors.

[0139] The control electrode of the sixth scan transistor T6 is electrically connected to the first enable terminal EN_O, the first electrode of the sixth scan transistor T6 is electrically connected to the second scan node SN2, and the second electrode of the sixth scan transistor T6 is electrically connected to the third scan node SN3. The control electrode and the first electrode of the seventh scan transistor T7 are both electrically connected to the third scan node SN3, and the second electrode of the seventh scan transistor T7 is electrically connected to the first enable terminal EN_O.

[0140] In the embodiment of the present disclosure, the second scan control sub-circuit 522 includes an eighth scan transistor T8 and a ninth scan transistor T9. The eighth scan transistor T8 and the ninth scan transistor T9 are P-type transistors and are used as switching transistors.

[0141] The control electrode of the eighth scan transistor T8 is electrically connected to the second enable terminal EN_E, the first electrode of the eighth scan transistor T8 is electrically connected to the second scan node SN2, and the second electrode of the eighth scan transistor T8 is electrically connected to the fourth scan node SN4. The control electrode and the first electrode of the ninth scan transistor T9 are both electrically connected to the fourth scan node SN4, and the second electrode of the ninth scan transistor T9 is electrically connected to the second enable terminal EN_E.

[0142] In the embodiment of the present disclosure, the first scan output sub-circuit 531 includes a tenth scan transistor T10 , an eleventh scan transistor T11 , a first scan capacitor C1 , and a second scan capacitor C2 .

[0143] The control electrode of the tenth scan transistor T10 is electrically connected to the first scan node SN1, the first electrode of the tenth scan transistor T10 is electrically connected to the second power supply terminal VGH, and the second electrode of the tenth scan transistor T10 is electrically connected to the first scan output terminal GOUT_O. The control electrode of the eleventh scan transistor T11 is electrically connected to the third scan node SN3, the first electrode of the eleventh scan transistor T11 is electrically connected to the second clock terminal GCB, and the second electrode of the eleventh scan transistor T11 is electrically connected to the first scan output terminal GOUT_O. The first end of the first scan capacitor C1 is electrically connected to the first scan node SN1, and the second end of the first scan capacitor C1 is electrically connected to the second power supply terminal VGH. The first end of the second scan capacitor C2 is electrically connected to the third scan node SN3, and the second end of the second scan capacitor C2 is electrically connected to the first scan output terminal GOUT_O.

[0144] In the embodiment of the present disclosure, the second scan output sub-circuit 532 includes a twelfth scan transistor T12, a thirteenth scan transistor T13, a third scan capacitor C3, and a fourth scan capacitor C4.

[0145] The control electrode of the twelfth scan transistor T12 is electrically connected to the first scan node SN1, the first electrode of the twelfth scan transistor T12 is electrically connected to the second power supply terminal VGH, and the second electrode of the twelfth scan transistor T12 is electrically connected to the second scan output terminal GOUT_E. The control electrode of the thirteenth scan transistor T13 is electrically connected to the fourth scan node SN4, the first electrode of the thirteenth scan transistor T13 is electrically connected to the second clock terminal GCB, and the second electrode of the thirteenth scan transistor T13 is electrically connected to the second scan output terminal GOUT_E. The first end of the third scan capacitor C3 is electrically connected to the first scan node SN1, and the second end of the third scan capacitor C3 is electrically connected to the second power supply terminal VGH. The first end of the fourth scan capacitor C4 is electrically connected to the fourth scan node SN4, and the second end of the fourth scan capacitor C4 is electrically connected to the second scan output terminal GOUT_E.

[0146] In the embodiment of the present disclosure, the third scan output sub-circuit 533 includes a fourteenth scan transistor T14, a fifteenth scan transistor T15, a sixteenth scan transistor T16, a fifth scan capacitor C5, and a sixth scan capacitor C6.

[0147] The control electrode of the fourteenth scanning transistor T14 is electrically connected to the first scanning node SN1, the first electrode of the fourteenth scanning transistor T14 is electrically connected to the second power supply terminal VGH, and the second electrode of the fourteenth scanning transistor T14 is electrically connected to the third scanning output terminal GOUT_n. The control electrode of the fifteenth scanning transistor T15 is electrically connected to the first electrode of the sixteenth scanning transistor T16, the first electrode of the fifteenth scanning transistor T15 is electrically connected to the second clock terminal GCB, and the second electrode of the fifteenth scanning transistor T15 is electrically connected to the third scanning output terminal GOUT_n. The control electrode of the sixteenth scanning transistor T16 is electrically connected to the first power supply terminal VGL, and the second electrode of the sixteenth scanning transistor T16 is electrically connected to the second scanning node SN2. The first terminal of the fifth scanning capacitor C5 is electrically connected to the first scanning node SN1, and the second terminal of the fifth scanning capacitor C5 is electrically connected to the second power supply terminal VGH. The first terminal of the sixth scanning capacitor C6 is electrically connected to the first electrode of the sixth scanning transistor T16, and the second terminal of the sixth scanning capacitor C6 is electrically connected to the third scanning output terminal GOUT_n.

[0148] In the example of FIG5A , the first scanning transistor T1 through the sixteenth scanning transistor T16 are all P-type transistors, such as thin-film transistors whose active layers are low-temperature doped polysilicon (LTPS). Those skilled in the art will appreciate that, according to the embodiments of the present disclosure, the first scanning transistor T1 through the sixteenth scanning transistor T16 may also be N-type transistors, such as thin-film transistors whose active layers are indium gallium zinc oxide (IGZO), by changing the gate turn-on signal level of each transistor accordingly.

[0149] In addition, those skilled in the art will appreciate that the scan capacitor may be implemented as a single capacitor or a plurality of capacitor units connected in parallel or in series, as long as the corresponding functions can be achieved.

[0150] Figures 5B and 5C are signal timing diagrams for the scanning shift register in Figure 5A. Figures 5B and 5C illustrate the timing waveforms of the various signals in each phase. The following describes the operation of the scanning shift register provided by an embodiment of the present invention, taking the structure of the scanning shift register shown in Figure 5A as an example and combining the signal timing diagrams shown in Figures 5B and 5C. The operation of the shift register includes four phases.

[0151] For example, FIG5B shows the signal timings output by the first scan output terminal GOUT_O, the second scan output terminal GOUT_E, and the third scan output terminal GOUT_n when the first enable signal EN_O is low and the second enable pixel EN_E is high.

[0152] In the first phase S1 , the first scan input signal GIN_n is low, the first clock signal GCK is low, the second clock signal GCB is high, the first enable signal EN_O is low, and the second enable signal EN_E is high.

[0153] Under the control of the first clock signal GCK, the first scanning transistor T1 and the second scanning transistor T2 are turned on, and the first scanning input signal GIN_n is provided to the second scanning node SN2 through the first scanning transistor T1. At this time, the potential of the second scanning node SN2 is at a low level. The first power supply voltage VGL is provided to the first scanning node SN1 through the second scanning transistor T2. At this time, the potential of the first scanning node SN1 is at a low level.

[0154] Under the control of the low level of the first scan node N1, the fourth scan transistor T4, the tenth scan transistor T10, the twelfth scan transistor T12, and the fourteenth scan transistor T14 are turned on. Under the control of the low level of the second scan node SN2, the third scan transistor T3 is turned on. The fifth scan transistor T5 is turned off by the high level of the second clock signal GCB.

[0155] Since the first power supply voltage VGL and the first clock signal GCK are both at a low level, the low level is supplied to the first terminals of the first scan capacitor C1, the third scan capacitor C3, and the fifth scan capacitor C5, and the second power supply voltage VGH is supplied to the second terminals of the first scan capacitor C1, the third scan capacitor C3, and the fifth scan capacitor C5. Therefore, the first power supply voltage VGL and the first clock signal GCK charge the first scan capacitor C1, the third scan capacitor C3, and the fifth scan capacitor C5, causing the first terminals of the first scan capacitor C1, the third scan capacitor C3, and the fifth scan capacitor C5 to store a low level.

[0156] Under the control of the first enable signal EN_O, the sixth scan transistor T6 is turned on, and the low level of the second scan node SN2 is applied to the third scan node SN3. Under the control of the potential of the third scan node SN3, the seventh scan transistor T7 is turned on, and the first enable signal EN_O is provided to the third scan node SN3. Under the control of the low level of the third scan node SN3, the eleventh scan transistor T11 is turned on.

[0157] When the tenth scanning transistor T10 and the eleventh scanning transistor T11 are both turned on, the first power supply voltage VGH and the second clock signal GCB are provided to the first scanning output terminal GOUT_O. At this time, the first gate driving signal GOUT_O output by the first scanning output terminal GOUT_O is at a high level.

[0158] Since the second terminal of the second scan capacitor C2 is at a high level, the first terminal of the second scan capacitor C2 is charged by the low level of the third scan node SN3, and the first terminal of the second scan capacitor C2 stores a low level.

[0159] The eighth scanning transistor T8 is turned off by the high level of the second enable signal EN_E. When the twelfth scanning transistor T12 is turned on, the first power supply voltage VGH is provided to the second scanning output terminal GOUT_E. At this time, the second gate driving signal GOUT_E output by the second scanning output terminal GOUT_E is high level.

[0160] Under the control of the first power supply voltage VGL, the sixteenth scanning transistor T16 is turned on, and the high level of the second scanning node SN2 is provided to the control electrode of the fifteenth scanning transistor T15. The fifteenth scanning transistor T15 is turned off by the high level. When the fourteenth scanning transistor T14 is turned on, the first power supply voltage VGH is provided to the third scanning output terminal GOUT_n. At this time, the third gate drive signal GOUT_n output by the third scanning output terminal GOUT_n is at a high level.

[0161] Since the second terminal of the sixth scan capacitor C6 is at a high level, the first terminal of the sixth scan capacitor C6 is charged by the low level of the second scan node SN2, and the first terminal of the sixth scan capacitor C6 stores a low level.

[0162] In the second phase S2 , the first scan input signal GIN_n is high, the first clock signal GCK is high, the second clock signal GCB is low, the first enable signal EN_O is low, and the second enable signal EN_E is high.

[0163] The first scanning transistor T1 and the second scanning transistor T2 are turned off when the first clock signal GCK is high. Under the control of the first power supply voltage VGL, the sixteenth scanning transistor T16 is turned on. Under the control of the first enable signal EN_O, the sixth scanning transistor T6 is turned on. The low level stored at the first terminals of the second scanning capacitor C2 and the sixth scanning capacitor C6 is applied to the eleventh scanning transistor T11 and the fifteenth scanning transistor T15, turning them on. The low level stored at the first terminals of the second scanning capacitor C2 and the sixth scanning capacitor C6 is applied to the second scanning node SN2 via the sixth scanning transistor T6 and the sixteenth scanning transistor T16. The low level at the second scanning node SN2 turns the third scanning transistor T3 on.

[0164] The first clock signal GCK is provided to the first scan node SN1 through the third scan transistor T3. At this time, the level of the first scan node SN1 is high. The fourth scan transistor T4, the tenth scan transistor T10, the twelfth scan transistor T12, and the fourteenth scan transistor T14 are turned off by the high level of the first scan node SN1. The eighth scan transistor T8 is turned off by the high level of the second enable signal EN_E.

[0165] When the tenth scan transistor T10 is turned off and the eleventh scan transistor T11 is turned on, the second clock signal GCB is provided to the first scan output terminal GOUT_O. At this time, the first gate driving signal GOUT_O output by the first scan output terminal GOUT_O is at a low level.

[0166] When the fourteenth scan transistor T14 is turned off and the fifteenth scan transistor T15 is turned on, the second clock signal GCB is provided to the third scan output terminal GOUT_n. At this time, the third gate driving signal GOUT_n outputted by the third scan output terminal GOUT_n is at a low level.

[0167] Since the second gate drive signal GOUT_E output by the second scan output terminal GOUT_E is at a high level during the S1 phase, the second gate drive signal GOUT_E is used to charge the second terminal of the fourth scan capacitor C4, and the second terminal of the fourth scan capacitor C4 is charged and stores a high level. Therefore, during the S2 phase, the second terminal of the fourth scan capacitor C4 is discharged, and the second gate drive signal GOUT_E output by the second scan output terminal GOUT_E is at a high level.

[0168] In the third phase S3 , the first scan input signal GIN_n is high, the first clock signal GCK is low, the second clock signal GCB is high, the first enable signal EN_O is low, and the second enable signal EN_E is high.

[0169] Under the control of the first clock signal GCK, the first scanning transistor T1 and the second scanning transistor T2 are turned on, and the first scanning input signal GIN_n is provided to the second scanning node SN2 through the first scanning transistor T1. At this time, the potential of the second scanning node SN2 is at a high level. The first power supply voltage VGL is provided to the first scanning node SN1 through the second scanning transistor T2. At this time, the potential of the first scanning node SN1 is at a low level.

[0170] Under the control of the low level of the first scan node N1, the fourth scan transistor T4, the tenth scan transistor T10, the twelfth scan transistor T12, and the fourteenth scan transistor T14 are turned on. The first terminals of the first scan capacitor C1, the third scan capacitor C3, and the fifth scan capacitor C5 store a low level. Under the control of the high level of the second scan node SN2, the third scan transistor T3 is turned on. The fifth scan transistor T5 is turned off by the high level of the second clock signal GCB.

[0171] Under the control of the first enable signal EN_O, the sixth scanning transistor T6 is turned on. Under the action of the first power supply voltage VGL, the sixteenth scanning transistor T16 is turned on. The high level of the second scanning node SN2 is applied to the third scanning node SN3 and the control electrode of the fifteenth scanning transistor T15. The seventh scanning transistor T7, the eleventh scanning transistor T11, and the fifteenth scanning transistor T15 are turned off by the high potential, and the first terminals of the second scanning capacitor C2 and the sixth scanning capacitor C6 store a high level.

[0172] When the tenth scan transistor T10 is turned on and the eleventh scan transistor T11 is turned off, the first power voltage VGH is provided to the first scan output terminal GOUT_O. At this time, the first gate driving signal GOUT_O output by the first scan output terminal GOUT_O is at a high level.

[0173] When the eighth scan transistor T8 is turned off by the high level of the second enable signal EN_E and the twelfth scan transistor T12 is turned on, the first power supply voltage VGH is provided to the second scan output terminal GOUT_E. At this time, the second gate drive signal GOUT_E output by the second scan output terminal GOUT_E is high.

[0174] When the fourteenth scan transistor T14 is turned on and the fifteenth scan transistor T15 is turned off, the first power supply voltage VGH is provided to the third scan output terminal GOUT_n. At this time, the third gate driving signal GOUT_n outputted by the third scan output terminal GOUT_n is at a high level.

[0175] In the fourth phase S4 , the first scan input signal GIN_n is high, the first clock signal GCK is high, the second clock signal GCB is low, the first enable signal EN_O is low, and the second enable signal EN_E is high.

[0176] The first scanning transistor T1 and the second scanning transistor T2 are turned off at the high level of the first clock signal GCK. Under the control of the first power supply voltage VGL, the sixteenth scanning transistor T16 is turned on. Under the control of the first enable signal EN_E, the sixth scanning transistor T6 is turned on.

[0177] Since the first terminals of the second scan capacitor C2 and the sixth scan capacitor C6 store a high level in the S3 phase, the first terminals of the second scan capacitor C2 and the sixth scan capacitor C6 are discharged, and the eleventh scan transistor T11 and the fifteenth scan transistor T15 are turned off by the high potential.

[0178] Since the first terminals of the first, third, and fifth scan capacitors C1, C3, and C5 store a low level in the S3 phase, the fourth, tenth, twelfth, and fourteenth scan transistors T4, T10, T12, and T14 are turned on.

[0179] When the tenth scan transistor T10 is turned on and the eleventh scan transistor T11 is turned off, the first power voltage VGH is provided to the first scan output terminal GOUT_O. At this time, the first gate driving signal GOUT_O output by the first scan output terminal GOUT_O is at a high level.

[0180] When the eighth scan transistor T8 is turned off by the high level of the second enable signal EN_E and the twelfth scan transistor T12 is turned on, the first power supply voltage VGH is provided to the second scan output terminal GOUT_E. At this time, the second gate drive signal GOUT_E output by the second scan output terminal GOUT_E is high.

[0181] When the fourteenth scan transistor T14 is turned on and the fifteenth scan transistor T15 is turned off, the first power supply voltage VGH is provided to the third scan output terminal GOUT_n. At this time, the third gate driving signal GOUT_n outputted by the third scan output terminal GOUT_n is at a high level.

[0182] In the disclosed embodiment, by controlling the first enable signal EN_O to be low and the second enable signal EN_E to be high, the first gate drive signal GOUT_O outputted by the first scan output terminal GOUT_O is a pulse waveform, the second gate drive signal GOUT_E outputted by the second scan output terminal GOUT_E is a DC signal, and the second gate drive signal GOUT_E remains at a high level. In this case, when the first gate drive signal GOUT_O is used to drive the anti-peeping sub-pixel, the anti-peeping sub-pixel operates, and the light-emitting element in the pixel circuit of the anti-peeping sub-pixel emits light. When the second gate drive signal GOUT_E is used to drive the display sub-pixel, the display sub-pixel is driven by the DC second gate drive signal GOUT_E, and the light-emitting element in the pixel circuit of the display sub-pixel does not emit light.

[0183] Since the second gate driving signal GOUT_E is a direct current signal, the logic power consumption generated by the voltage jump of the second gate driving signal GOUT_E can be reduced when the display sub-pixel is not working.

[0184] For example, FIG5C shows the signal timings output by the first scan output terminal GOUT_O, the second scan output terminal GOUT_E, and the third scan output terminal GOUT_n when the first enable signal EN_O is high and the second enable signal EN_E is low.

[0185] FIG5C shows the operation process of the scan shift register 500 shown in FIG5A under signal control, which is similar to the operation process of the scan shift register 500 shown in FIG5A under signal control shown in FIG5B . For simplicity, similar parts are not repeated here.

[0186] In the first phase S1 , the first scan input signal GIN_n is low, the first clock signal GCK is low, the second clock signal GCB is high, the first enable signal EN_O is high, and the second enable signal EN_E is low.

[0187] The first to fourth scanning transistors T1 to T4, the eighth scanning transistor T8, the ninth scanning transistor T9, and the twelfth to sixteenth scanning transistors T12 to T16 are turned on, while the fifth to seventh scanning transistors T5 to T7 and the eleventh scanning transistor T11 are turned off. The potential of the first scanning node SN1 is low, the potential of the second scanning node SN2 is low, and the potential of the fourth scanning node SN4 is low.

[0188] The first gate driving signal GOUT_O outputted by the first scanning output terminal GOUT_O is at a high level. The second gate driving signal GOUT_E outputted by the second scanning output terminal GOUT_E is at a high level. The third gate driving signal GOUT_n outputted by the third scanning output terminal GOUT_n is at a high level.

[0189] In the second phase S2 , the first scan input signal GIN_n is high, the first clock signal GCK is high, the second clock signal GCB is low, the first enable signal EN_O is high, and the second enable signal EN_E is low.

[0190] The third scanning transistor T3, the fifth scanning transistor T5, the eighth scanning transistor T8, the ninth scanning transistor T9, the thirteenth scanning transistor T13, the fifteenth scanning transistor T15, and the sixteenth scanning transistor T16 are turned on, and the first scanning transistor T1, the second scanning transistor T2, the fourth scanning transistor T4, the sixth scanning transistor T6, the seventh scanning transistor T7, the tenth scanning transistor T10 to the twelfth scanning transistor T12, and the fourteenth scanning transistor T14 are turned off. The potential of the first scanning node SN1 is high, the potential of the second scanning node SN2 is low, and the potential of the fourth scanning node SN4 is low.

[0191] The first gate driving signal GOUT_O outputted by the first scanning output terminal GOUT_O is at a high level. The second gate driving signal GOUT_E outputted by the second scanning output terminal GOUT_E is at a low level. The third gate driving signal GOUT_n outputted by the third scanning output terminal GOUT_n is at a low level.

[0192] In the third phase S3 , the first scan input signal GIN_n is high, the first clock signal GCK is low, the second clock signal GCB is high, the first enable signal EN_O is high, and the second enable signal EN_E is low.

[0193] The first scanning transistor T1, the second scanning transistor T2, the fourth scanning transistor T4, the eighth scanning transistor T8, the tenth scanning transistor T10, the twelfth scanning transistor T12, the fourteenth scanning transistor T14, and the sixteenth scanning transistor T16 are turned on, and the third scanning transistor T3, the fifth scanning transistor T5 to the seventh scanning transistor T7, the ninth scanning transistor T9, the eleventh scanning transistor T11, the thirteenth scanning transistor T13, and the fifteenth scanning transistor T15 are turned off. The potential of the first scanning node SN1 is at a low level, the potential of the second scanning node SN2 is at a high level, and the potential of the fourth scanning node SN4 is at a high level.

[0194] The first gate driving signal GOUT_O outputted by the first scanning output terminal GOUT_O is at a high level. The second gate driving signal GOUT_E outputted by the second scanning output terminal GOUT_E is at a high level. The third gate driving signal GOUT_n outputted by the third scanning output terminal GOUT_n is at a high level.

[0195] In the fourth phase S4 , the first scan input signal GIN_n is high, the first clock signal GCK is high, the second clock signal GCB is low, the first enable signal EN_O is high, and the second enable signal EN_E is low.

[0196] The fourth scanning transistor T4, the fifth scanning transistor T5, the eighth scanning transistor T8 to the tenth scanning transistor T10, the twelfth scanning transistor T12, the fourteenth scanning transistor T14, and the sixteenth scanning transistor T16 are turned on, and the first scanning transistor T1 to the third scanning transistor T3, the sixth scanning transistor T6, the seventh scanning transistor T7, the eleventh scanning transistor T11, the thirteenth scanning transistor T13, and the fifteenth scanning transistor T15 are turned off. The potential of the first scanning node SN1 is at a low level, the potential of the second scanning node SN2 is at a high level, and the potential of the fourth scanning node SN4 is at a high level.

[0197] The first gate driving signal GOUT_O outputted by the first scanning output terminal GOUT_O is at a high level. The second gate driving signal GOUT_E outputted by the second scanning output terminal GOUT_E is at a high level. The third gate driving signal GOUT_n outputted by the third scanning output terminal GOUT_n is at a high level.

[0198] In the disclosed embodiment, by controlling the first enable signal EN_O to be high and the second enable signal EN_E to be low, the first gate drive signal GOUT_O outputted by the first scan output terminal GOUT_O is a DC signal. The first gate drive signal GOUT_O remains at a high level, and the second gate drive signal GOUT_E outputted by the second scan output terminal GOUT_E is a pulse waveform. In this case, when the first gate drive signal GOUT_O is used to drive the anti-peeping sub-pixel, the anti-peeping sub-pixel is driven by the DC first gate drive signal GOUT_O, and the light-emitting element in the pixel circuit of the anti-peeping sub-pixel does not emit light. When the second gate drive signal GOUT_E is used to drive the display sub-pixel, the display sub-pixel is activated, and the light-emitting element in the pixel circuit of the display sub-pixel emits light.

[0199] Since the first gate driving signal GOUT_O is a direct current signal, the logic power consumption generated by the voltage jump of the first gate driving signal GOUT_O can be reduced when the anti-peeping sub-pixel is not working.

[0200] When the first enable signal EN_O is low and the second enable signal EN_E is high, the timing of the first gate driving signal GOUT_O outputted by the first scan output terminal GOUT_O is the same as the timing of the third gate driving signal GOUT_n outputted by the third scan output terminal GOUT_n.

[0201] When the first enable signal EN_O is high and the second enable signal EN_E is low, the timing of the second gate driving signal GOUT_E outputted by the second scan output terminal GOUT_E is the same as the timing of the third gate driving signal GOUT_n outputted by the third scan output terminal GOUT_n.

[0202] In an embodiment of the present disclosure, the output of the first gate drive signal GOUT_O is controlled based on the first enable signal EN_O, and the output of the second gate drive signal GOUT_E is controlled based on the second enable signal EN_E. When the first gate drive signal GOUT_O drives the anti-peeping sub-pixel and the second gate drive signal GOUT_E drives the display sub-pixel, the operating state of the anti-peeping sub-pixel can be independently controlled by controlling the first enable signal EN_O, and the operating state of the display sub-pixel can be controlled by controlling the level of the second enable signal EN_E. Accordingly, when the first gate drive signal GOUT_O drives the display sub-pixel and the second gate drive signal GOUT_E drives the anti-peeping sub-pixel, the operating state of the display sub-pixel can be independently controlled by controlling the first enable signal EN_O, and the operating state of the anti-peeping sub-pixel can be controlled by controlling the level of the second enable signal EN_E.

[0203] For example, when the first gate drive signal GOUT_O drives the anti-peeping sub-pixel and the second gate drive signal GOUT_E drives the display sub-pixel, by controlling the level of the first enable signal EN_O to be low, the anti-peeping sub-pixel can be independently controlled to be in an active state. By controlling the level of the first enable signal EN_O to be high, the anti-peeping sub-pixel can be independently controlled to be in an inactive state. By controlling the level of the second enable signal EN_E to be low, the display sub-pixel can be independently controlled to be in an active state. By controlling the level of the second enable signal EN_E to be high, the display sub-pixel can be independently controlled to be in an inactive state.

[0204] In the embodiment of the present disclosure, the seventh scanning transistor T7 can prevent the control electrode of the eleventh scanning transistor T11 from being in a floating state, and the ninth scanning transistor T9 can prevent the control electrode of the thirteenth scanning transistor T13 from being in a floating state.

[0205] In the embodiment of the present disclosure, by providing a signal terminal to which the second electrodes of the seventh scanning transistor T7 and the ninth scanning transistor T9 are electrically connected, a partial refresh of the display image in the display panel can be achieved.

[0206] For example, the scan shift register 500 can be used to set different refresh frequencies for different pixel rows of the pixel array. For example, the display screen may include a static screen and a dynamic screen. For example, the static screen may be the background portion of the display screen where the screen does not change, and the dynamic screen may be the portion of the display screen where the screen changes. When the display is displaying a screen, a static screen may appear on the display screen for a period of time. If both the static screen and the dynamic screen are refreshed at the same refresh rate (for example, a high frequency), a large power consumption will be generated. If the dynamic screen portion is set to maintain the original high-frequency refresh, and the static screen portion is set to refresh the screen at a relatively low refresh frequency, the refresh power consumption can be reduced.

[0207] For example, you can set the frame refresh rate of the dynamic image portion to 120Hz. In 1 second, the display refreshes 120 frames. Correspondingly, you can also set the frame refresh rate of the static image portion to 60Hz or 30Hz. At a frame refresh rate of 60Hz, the display refreshes 60 frames in 1 second. At a frame refresh rate of 30Hz, the display refreshes 30 frames in 1 second.

[0208] By setting the signal timing of the signal terminal electrically connected to the second electrodes of the seventh scanning transistor T7 and the ninth scanning transistor T9, the on and off of the eleventh scanning transistor T11 and the thirteenth scanning transistor T13 can be controlled, thereby controlling the first scanning input terminal GOUT_O and the second scanning input terminal GOUT_E to output a signal or not output a signal.

[0209] For example, when the first scan input terminal GOUT_O outputs the first gate drive signal GOUT_O, the anti-peeping sub-pixel driven by the first gate drive signal GOUT_O refreshes the pixel value. When the first scan input terminal GOUT_O does not output the first gate drive signal GOUT_O, the anti-peeping sub-pixel driven by the first gate drive signal GOUT_O does not refresh the pixel value.

[0210] Therefore, by setting the signal timing output from the signal end electrically connected to the second electrodes of the seventh scanning transistor T7 and the ninth scanning transistor T9, gate drive signals with corresponding frame refresh rates can be provided for different pixel rows, thereby flexibly controlling the refresh rates of different areas in the pixel array, enabling different areas in the pixel array to be refreshed at different refresh rates, thereby reducing refresh power consumption.

[0211] FIG6A is a schematic structural diagram of a light emitting control shift register according to another embodiment of the present disclosure.

[0212] As shown in FIG. 6A , the light emission control shift register 600 includes a light emission control input circuit 640 , a light emission control circuit 650 , and a light emission control output circuit 660 .

[0213] The light control input circuit 650 includes a first light control sub-circuit 651, a second light control sub-circuit 652, and a third light control sub-circuit 653. The light control output circuit 660 includes a first light control output sub-circuit 661, a second light control output sub-circuit 662, and a third light control output sub-circuit 663.

[0214] The light control input circuit 640, the light control circuit 650, and the light control output circuit 660 are similar to the light control input circuit 440, the light control circuit 450, and the light control output circuit 460 described above, respectively. The first light control sub-circuit 651, the second light control sub-circuit 652, and the third light control sub-circuit 653 are similar to the first light control sub-circuit 451, the second light control sub-circuit 452, and the third light control sub-circuit 453 described above, respectively. The first light control output sub-circuit 661, the second light control output sub-circuit 662, and the second light control output sub-circuit 663 are similar to the first light control output sub-circuit 461, the second light control output sub-circuit 462, and the second light control output sub-circuit 463 described above, respectively. For the sake of brevity, the same parts of this disclosure are not repeated here.

[0215] In the embodiment of the present disclosure, the light emission control input circuit 640 includes a first light emission control transistor T1 , a second light emission control transistor T2 , a third light emission control transistor T3 , a fourth light emission control transistor T4 , and a fifth light emission control transistor T5 .

[0216] The control electrode of the first emission control transistor T1 is electrically connected to the first clock terminal ECK, the first electrode of the first emission control transistor T1 is electrically connected to the emission control input terminal EIN_n, and the second electrode of the first emission control transistor T1 is electrically connected to the second emission control node EMN2. The control electrode of the second emission control transistor T2 is electrically connected to the first clock terminal ECK, the first electrode of the second emission control transistor T2 is electrically connected to the first power supply terminal VGL, and the second electrode of the second emission control transistor T2 is electrically connected to the first emission control node EMN1. The control electrode of the third emission control transistor T3 is electrically connected to the second emission control node EMN2, the first electrode of the third emission control transistor T3 is electrically connected to the first clock terminal ECK, and the second electrode of the third emission control transistor T3 is electrically connected to the first emission control node EMN1. The control electrode of the fourth emission control transistor T4 is electrically connected to the first emission control node EMN1, the first electrode of the fourth emission control transistor T4 is electrically connected to the second power supply terminal VGH, and the second electrode of the fourth emission control transistor T4 is electrically connected to the first electrode of the fifth emission control transistor T5. The control electrode of the fifth emission control transistor T5 is electrically connected to the second clock terminal ECB, and the second electrode of the fifth emission control transistor T5 is electrically connected to the second emission control node EMN2.

[0217] In the disclosed embodiment, the first light-emission control subcircuit 651 includes a sixth light-emission control transistor T6, a seventh light-emission control transistor T7, and a first light-emission control capacitor C1. The control electrode of the sixth light-emission control transistor T6 is electrically connected to the first enable terminal EN_O, the first electrode of the sixth light-emission control transistor T6 is electrically connected to the second light-emission control node EMN2, and the second electrode of the sixth light-emission control transistor T6 is electrically connected to the third light-emission control node EMN3. The control electrode and first electrode of the seventh light-emission control transistor T7 are both electrically connected to the third light-emission control node EMN3, and the second electrode of the seventh light-emission control transistor T7 is electrically connected to the first enable terminal EN_O. The first terminal of the first light-emission control capacitor C1 is electrically connected to the third light-emission control node EMN3, and the second terminal of the first light-emission control capacitor C1 is electrically connected to the second clock terminal ECB.

[0218] In the disclosed embodiment, the second light-emission control subcircuit 652 includes an eighth light-emission control transistor T8, a ninth light-emission control transistor T9, and a second light-emission control capacitor C2. The control electrode of the eighth light-emission control transistor T8 is electrically connected to the second enable terminal EN_E, the first electrode of the eighth light-emission control transistor T8 is electrically connected to the second light-emission control node EMN2, and the second electrode of the eighth light-emission control transistor T8 is electrically connected to the fourth light-emission control node EMN4. The control electrode and first electrode of the ninth light-emission control transistor T9 are both electrically connected to the fourth light-emission control node EMN4, and the second electrode of the ninth light-emission control transistor T9 is electrically connected to the second enable terminal EN_E. The first terminal of the second light-emission control capacitor C2 is electrically connected to the fourth light-emission control node EMN4, and the second terminal of the second light-emission control capacitor C2 is electrically connected to the second clock terminal ECB.

[0219] In the disclosed embodiment, the third light-emission control subcircuit 653 includes a tenth light-emission control transistor T10, an eleventh light-emission control transistor T11, a twelfth light-emission control transistor T12, a thirteenth light-emission control transistor T13, and a third light-emission control capacitor C3. The control electrode of the tenth light-emission control transistor T10 is electrically connected to the first power supply terminal VGL, the first electrode of the tenth light-emission control transistor T10 is electrically connected to the first light-emission control node EMN1, and the second electrode of the tenth light-emission control transistor T10 is electrically connected to the control electrode of the eleventh light-emission control transistor T11. The first electrode of each of the eleventh light-emission control transistors T11 is electrically connected to the second clock terminal ECB, the second electrode of the eleventh light-emission control transistor T11 is electrically connected to the first electrode of the twelfth light-emission control transistor T12, the control electrode of the twelfth light-emission control transistor T12 is electrically connected to the second clock terminal ECB, and the second electrode of the twelfth light-emission control transistor T12 is electrically connected to the fifth light-emission control node EMN5. A control electrode of the thirteenth emission control transistor T13 is electrically connected to the second emission control node EMN2, a first electrode of the thirteenth emission control transistor T13 is electrically connected to the second power supply terminal VGH, and a second electrode of the thirteenth emission control transistor T13 is electrically connected to the fifth emission control node EMN5. A first end of the third emission control capacitor C3 is electrically connected to the control electrode of the eleventh emission control transistor T11, and a second end of the third emission control capacitor C3 is electrically connected to the second electrode of the eleventh emission control transistor T11.

[0220] In the disclosed embodiment, the first light emission control output sub-circuit 661 includes a fourteenth light emission control transistor T14, a fifteenth light emission control transistor T15, and a fourth light emission control capacitor C4. The control electrode of the fourteenth light emission control transistor T14 is electrically connected to the fifth light emission control node EMN5, a first electrode of the fourteenth light emission control transistor T14 is electrically connected to the second power supply terminal VGH, and a second electrode of the fourteenth light emission control transistor T14 is electrically connected to the first light emission control output terminal EOUT_O. The control electrode of the fifteenth light emission control transistor T15 is electrically connected to the third light emission control node EMN3, a first electrode of the fifteenth light emission control transistor T15 is electrically connected to the first power supply terminal VGL, and a second electrode of the fifteenth light emission control transistor T15 is electrically connected to the first light emission control output terminal EOUT_O. The first end of the fourth light emission control capacitor C4 is electrically connected to the fifth light emission control node EMN5, and the second end of the fourth light emission control capacitor C4 is electrically connected to the second power supply terminal VGH.

[0221] In the disclosed embodiment, the second light-emission control output sub-circuit 662 includes a sixteenth light-emission control transistor T16, a seventeenth light-emission control transistor T17, and a fifth light-emission control capacitor C5. The control electrode of the sixteenth light-emission control transistor T16 is electrically connected to the fifth light-emission control node EMN5, a first electrode of the sixteenth light-emission control transistor T16 is electrically connected to the second power supply terminal VGH, and a second electrode of the sixteenth light-emission control transistor T16 is electrically connected to the second light-emission control output terminal EOUT_E. The control electrode of the seventeenth light-emission control transistor T17 is electrically connected to the fourth light-emission control node, a first electrode of the seventeenth light-emission control transistor T17 is electrically connected to the first power supply terminal VGL, and a second electrode of the seventeenth light-emission control transistor T17 is electrically connected to the second light-emission control output terminal EOUT_E. The first terminal of the fifth light-emission control capacitor C5 is electrically connected to the fifth light-emission control node EMN5, and the second terminal of the fifth light-emission control capacitor C5 is electrically connected to the second power supply terminal VGH.

[0222] In the disclosed embodiment, the third emission control output sub-circuit 663 includes an eighteenth emission control transistor T18, a nineteenth emission control transistor T19, a twentieth emission control transistor T20, and a sixth emission control capacitor C6. The control electrode of the eighteenth emission control transistor T18 is electrically connected to the fifth emission control node EMN5, a first electrode of the eighteenth emission control transistor T18 is electrically connected to the second power supply terminal VGH, and a second electrode of the eighteenth emission control transistor T18 is electrically connected to the third emission control output terminal EOUT_n. The control electrode of the nineteenth emission control transistor T19 is electrically connected to the first electrode of the twentieth emission control transistor T20, a first electrode of the nineteenth emission control transistor T19 is electrically connected to the first power supply terminal VGL, and a second electrode of the nineteenth emission control transistor T19 is electrically connected to the third emission control output terminal EOUT_n. The control electrode of the twentieth emission control transistor T20 is electrically connected to the first power supply terminal VGL, and a second electrode of the twentieth emission control transistor T20 is electrically connected to the second emission control node EMN2. A first terminal of the sixth light emitting control capacitor C6 is electrically connected to the control electrode of the nineteenth light emitting control transistor T19 , and a second terminal of the sixth light emitting control capacitor C6 is electrically connected to the second clock terminal ECB.

[0223] In the example of FIG6A , the first emission control transistor T1 to the twentieth emission control transistor T20 are all P-type transistors, such as thin-film transistors whose active layers are low-temperature doped polysilicon (LTPS). Those skilled in the art will appreciate that, according to the embodiments of the present disclosure, the first emission control transistor T1 to the twentieth emission control transistor T20 may also be N-type transistors, such as thin-film transistors whose active layers are indium gallium zinc oxide (IGZO), by changing the level of the gate turn-on signal of each transistor accordingly.

[0224] In addition, those skilled in the art will appreciate that the light-emitting control capacitor may be implemented as a single capacitor or multiple capacitor units connected in parallel or in series, as long as they can achieve their corresponding functions.

[0225] Figures 6B and 6C are signal timing diagrams for the light-emission control shift register in Figure 6A. Figures 6B and 6C illustrate the timing waveforms of the various signals in each phase. The following describes the operation of the light-emission control shift register provided by an embodiment of the present invention, using the structure of the light-emission control shift register shown in Figure 6A as an example, in conjunction with the signal timing diagrams shown in Figures 6B and 6C. The operation of the light-emission control shift register includes five phases.

[0226] For example, FIG6B shows the signal timings output by the first light emitting control output terminal EOUT_O, the second light emitting control output terminal EOUT_E and the third light emitting control output terminal EOUT_n when the first enable signal EN_O is low and the second enable pixel EN_E is high.

[0227] In the first phase S1 , the first light emitting control input signal EIN_n is low, the first clock signal ECK is low, the second clock signal ECB is high, the first enable signal EN_O is low, and the second enable signal EN_E is high.

[0228] Under the control of the first clock signal ECK, the first emission control transistor T1 and the second emission control transistor T2 are turned on. The first emission control input signal EIN_n is provided to the second emission control node EMN2 via the first emission control transistor T1. At this time, the potential of the second emission control node EMN2 is at a high level. The first power supply voltage VGL is provided to the first emission control node EMN1 via the second emission control transistor T2. At this time, the potential of the first emission control node EMN1 is at a low level.

[0229] Under the control of the first power supply voltage VGL, the tenth emission control transistor T10 is turned on. The potential of the first emission control node EMN1 is supplied to the control electrode of the eleventh emission control transistor T11 through the tenth emission control transistor T10, turning the eleventh emission control transistor T11 on. The potential of the first emission control node EMN1 charges the first terminal of the third emission control capacitor C3, which then stores a low level.

[0230] The twelfth light emitting control transistor T12 is turned off by the high level of the second clock signal ECB, and the first light emitting control node EMN1 is disconnected from the fifth light emitting control node EMN5.

[0231] Under the control of the first enable signal EN_O, the sixth emission control transistor T6 is turned on, and the high level of the second emission control node EMN2 is provided to the third emission control node EMN3. The high level of the third emission control node EMN3 turns off the seventh emission control transistor T7 and the fifteenth emission control transistor T15. The high level of the second emission control node EMN2 turns off the thirteenth emission control transistor T13.

[0232] The high level of the second light-emitting control node EMN2 charges the first end of the seventh light-emitting control capacitor C7 through the twentieth light-emitting control transistor T20, and the high level of the second light-emitting control node EMN2 charges the first end of the first light-emitting control capacitor C1 through the sixth light-emitting control transistor T6. The first ends of the first light-emitting control capacitor C1 and the seventh light-emitting control capacitor C7 are charged and store a high level.

[0233] The eighth light emitting control transistor T8 is turned off by the high level of the second enable signal EN_E. The second light emitting control node EMN2 is disconnected from the fourth light emitting control node EMN4.

[0234] Under the control of the first power supply voltage VGL, the twentieth light emitting control transistor T20 is turned on, and the high level of the second light emitting control node EMN2 is provided to the control electrode of the nineteenth light emitting control transistor T19 through the twentieth light emitting control transistor T20, and the nineteenth light emitting control transistor T19 is turned off.

[0235] The fifth light-emitting control node EMN5 remains at the high level of the previous stage. The potential of the fifth light-emitting control node EMN5 in the previous stage is the same as the potential of the fifth light-emitting control node EMN5 in the fifth stage S5. The fourteenth light-emitting control transistor T14, the sixteenth light-emitting control transistor T16, and the eighteenth light-emitting control transistor T18 are turned off by the fifth light-emitting control node EMN5 remaining at the high level of the previous stage.

[0236] When the fifteenth light-emitting control transistor T15 and the fourteenth light-emitting control transistor T14 are both turned off, the first light-emitting control signal EOUT_O output by the first light-emitting control output terminal EOUT_O is the same as that in the previous stage, and the first light-emitting control signal EOUT_O is at a low level. The previous stage can be considered as the fifth stage S5 of the previous frame refresh process.

[0237] When the nineteenth light emitting control transistor T19 and the eighteenth light emitting control transistor T18 are both turned off, the third light emitting control signal EOUT_n outputted by the third light emitting control output terminal EOUT_n is the same as that in the previous stage, and the third light emitting control signal EOUT_n is at a low level.

[0238] When the eighth light emitting control transistor T18 and the sixteenth light emitting control transistor T16 are both turned off, the second light emitting control signal EOUT_E outputted by the second light emitting control output terminal EOUT_E is the same as that in the previous stage, and the second light emitting control signal EOUT_E is at a high level.

[0239] In the second phase S2 , the first light emitting control input signal E1N_n is high, the first clock signal ECK is high, the second clock signal ECB is low, the first enable signal EN_O is low, and the second enable signal EN_E is high.

[0240] The first and second emission control transistors T1 and T2 are turned off when the first clock signal ECK is at a high level. Under the control of the first power supply voltage VGL, the tenth and twentieth emission control transistors T10 and T20 are turned on. Under the control of the first enable signal EN_O, the sixth emission control transistor T6 is turned on.

[0241] Under the control of the high level stored at the first ends of the first light emitting control capacitor C1 and the seventh light emitting control capacitor C7 , the third light emitting control transistor T3 , the fifteenth light emitting control transistor T15 , and the nineteenth light emitting control transistor T19 are turned off.

[0242] Under the control of the low level stored at the first terminal of the third emission control capacitor C3, the eleventh emission control transistor T11 is turned on. Under the control of the second clock signal ECB, the twelfth emission control transistor T12 is turned on. The second clock signal ECB is provided to the fifth emission control node EMN5 through the twelfth emission control transistor T12. At this time, the potential of the fifth emission control node EMN5 is at a low level.

[0243] Under the control of the low level of the fifth light-emitting control node EMN5, the fourteenth light-emitting control transistor T14, the sixteenth light-emitting control transistor T16, and the eighteenth light-emitting control transistor T18 are turned on, and the first ends of the fourth light-emitting control capacitor C4, the fifth light-emitting control capacitor C5, and the sixth light-emitting control capacitor C6 are charged by the low level of the fifth light-emitting control node EMN5. The first ends of the fourth light-emitting control capacitor C4, the fifth light-emitting control capacitor C5, and the sixth light-emitting control capacitor C6 store a low level. The eighth light-emitting control transistor T8 is turned off by the high level of the second enable signal EN_E.

[0244] When the fifteenth emission control transistor T15 is turned off and the fourteenth emission control transistor T14 is turned on, the second power supply voltage VGH is provided to the first emission control output terminal EOUT_O. At this time, the first emission control signal EOUT_O output by the first emission control output terminal EOUT_O is high.

[0245] When the nineteenth emission control transistor T19 is turned off and the eighteenth emission control transistor T18 is turned on, the second power supply voltage VGH is provided to the third emission control output terminal EOUT_n. At this time, the third emission control signal EOUT_n outputted by the third emission control output terminal EOUT_n is at a high level.

[0246] When the eighth light emitting control transistor T18 is turned off and the sixteenth light emitting control transistor T16 is turned on, the second power supply voltage VGH is provided to the second light emitting control output terminal EOUT_E. At this time, the second light emitting control signal EOUT_E output by the second light emitting control output terminal EOUT_E is at a high level.

[0247] In the third phase S3 , the first light emitting control input signal EIN_n is high, the first clock signal ECK is low, the second clock signal ECB is high, the first enable signal EN_O is low, and the second enable signal EN_E is high.

[0248] Under the control of the first clock signal ECK, the first emission control transistor T1 and the second emission control transistor T2 are turned on. The first emission control input signal EIN_n is provided to the second emission control node EMN2 via the first emission control transistor T1. At this time, the potential of the second emission control node EMN2 is at a high level. The first power supply voltage VGL is provided to the first emission control node EMN1 via the second emission control transistor T2. At this time, the potential of the first emission control node EMN1 is at a low level.

[0249] Under the control of the first power supply voltage VGL, the tenth emission control transistor T10 and the twentieth emission control transistor T20 are turned on. The potential of the first emission control node EMN1 is supplied to the control electrode of the eleventh emission control transistor T11 via the tenth emission control transistor T10, turning the eleventh emission control transistor T11 on. The potential of the first emission control node EMN1 charges the first terminal of the third emission control capacitor C3, which then stores a low level.

[0250] The twelfth light emitting control transistor T12 is turned off by the high level of the second clock signal ECB, and the first light emitting control node EMN1 is disconnected from the fifth light emitting control node EMN5.

[0251] Under the control of the low levels stored at the first ends of the fourth, fifth and sixth light emitting control capacitors C4, C5 and C6, the fourteenth, sixteenth and eighteenth light emitting control transistors T14, T16 and T18 are turned on.

[0252] Under the control of the first enable signal EN_O, the sixth emission control transistor T6 is turned on, and the high level of the second emission control node EMN2 is provided to the third emission control node EMN3. The high level of the third emission control node EMN3 turns off the seventh emission control transistor T7 and the fifteenth emission control transistor T15. The high level of the second emission control node EMN2 turns off the thirteenth emission control transistor T13.

[0253] The high level of the second light-emitting control node EMN2 is charged through the twentieth light-emitting control transistor T20 and the first end of the seventh light-emitting control capacitor C7. The high level of the second light-emitting control node EMN2 is charged to the first end of the first light-emitting control capacitor C1 through the sixth light-emitting control transistor T6. The first light-emitting control capacitor C1 and the first end of the seventh light-emitting control capacitor C7 are charged to store a high level.

[0254] The high level of the second light emitting control node EMN2 is provided to the control electrode of the nineteenth light emitting control transistor T19 via the twentieth light emitting control transistor T20, and the nineteenth light emitting control transistor T19 is turned off.

[0255] The eighth light emitting control transistor T8 is turned off by the high level of the second enable signal EN_E. The second light emitting control node EMN2 is disconnected from the fourth light emitting control node EMN4.

[0256] When the fifteenth emission control transistor T15 is turned off and the fourteenth emission control transistor T14 is turned on, the second power supply voltage VGH is provided to the first emission control output terminal EOUT_O. At this time, the first emission control signal EOUT_O output by the first emission control output terminal EOUT_O is high.

[0257] When the nineteenth emission control transistor T19 is turned off and the eighteenth emission control transistor T18 is turned on, the second power supply voltage VGH is provided to the third emission control output terminal EOUT_n. At this time, the third emission control signal EOUT_n outputted by the third emission control output terminal EOUT_n is at a high level.

[0258] When the eighth light emitting control transistor T8 is turned off and the sixteenth light emitting control transistor T16 is turned on, the second power supply voltage VGH is provided to the second light emitting control output terminal EOUT_E. At this time, the second light emitting control signal EOUT_E output by the second light emitting control output terminal EOUT_E is at a high level.

[0259] In the fourth stage S4 , the first light emitting control input signal EIN_n is low, the first clock signal ECK is high, the second clock signal ECB is low, the first enable signal EN_O is low, and the second enable signal EN_E is high.

[0260] The first and second emission control transistors T1 and T2 are turned off when the first clock signal ECK is at a high level. Under the control of the first power supply voltage VGL, the tenth and twentieth emission control transistors T10 and T20 are turned on. Under the control of the first enable signal EN_O, the sixth emission control transistor T6 is turned on.

[0261] Under the control of the low level stored at the first terminal of the third emission control capacitor C3, the eleventh emission control transistor T11 is turned on. The low level stored at the first terminal of the third emission control capacitor C3 is provided to the first emission control node EMN1 via the tenth emission control transistor T10. Under the control of the low level at the first emission control node EMN1, the fourth emission control transistor T4 is turned on.

[0262] Under the control of the second clock signal ECB, the fifth emission control transistor T5 and the twelfth emission control transistor T12 are turned on. The second clock signal ECB is supplied to the fifth emission control node EMN5 via the eleventh emission control transistor T11 and the twelfth emission control transistor T12. At this time, the potential of the fifth emission control node EMN5 is at a low level. The second power supply voltage VGH is supplied to the second emission control node EMN2 via the fourth emission control transistor T4 and the fifth emission control transistor T5.

[0263] The high level of the second light emitting control node EMN2 is provided to the control electrode of the nineteenth light emitting control transistor T19 via the twentieth light emitting control transistor T20. The high level of the second light emitting control node EMN2 is provided to the control electrode of the fifteenth light emitting control transistor T15 via the sixth light emitting control transistor T6, and the fifteenth light emitting control transistor T15 and the nineteenth light emitting control transistor T19 are turned off.

[0264] Under the control of the low level of the fifth light-emitting control node EMN5, the fourteenth light-emitting control transistor T14, the sixteenth light-emitting control transistor T16, and the eighteenth light-emitting control transistor T18 are turned on, and the first ends of the fourth light-emitting control capacitor C4, the fifth light-emitting control capacitor C5, and the sixth light-emitting control capacitor C6 are charged by the low level of the fifth light-emitting control node EMN5. The first ends of the fourth light-emitting control capacitor C4, the fifth light-emitting control capacitor C5, and the sixth light-emitting control capacitor C6 store a low level. The eighth light-emitting control transistor T8 is turned off by the high level of the second enable signal EN_E.

[0265] When the fifteenth emission control transistor T15 is turned off and the fourteenth emission control transistor T14 is turned on, the second power supply voltage VGH is provided to the first emission control output terminal EOUT_O. At this time, the first emission control signal EOUT_O output by the first emission control output terminal EOUT_O is high.

[0266] When the nineteenth emission control transistor T19 is turned off and the eighteenth emission control transistor T18 is turned on, the second power supply voltage VGH is provided to the third emission control output terminal EOUT_n. At this time, the third emission control signal EOUT_n outputted by the third emission control output terminal EOUT_n is at a high level.

[0267] When the eighth light emitting control transistor T8 is turned off and the sixteenth light emitting control transistor T16 is turned on, the second power supply voltage VGH is provided to the second light emitting control output terminal EOUT_E. At this time, the second light emitting control signal EOUT_E output by the second light emitting control output terminal EOUT_E is at a high level.

[0268] In the fifth stage S5 , the first light emitting control input signal EIN_n is low, the first clock signal ECK is low, the second clock signal ECB is high, the first enable signal EN_O is low, and the second enable signal EN_E is high.

[0269] Under the control of the first clock signal ECK, the first emission control transistor T1 and the second emission control transistor T2 are turned on. The first emission control input signal EIN_n is provided to the second emission control node EMN2 via the first emission control transistor T1. At this time, the potential of the second emission control node EMN2 is at a low level. The first power supply voltage VGL is provided to the first emission control node EMN1 via the second emission control transistor T2. At this time, the potential of the first emission control node EMN1 is at a low level.

[0270] Under the control of the first power supply voltage VGL, the tenth emission control transistor T10 and the twentieth emission control transistor T20 are turned on. The potential of the first emission control node EMN1 is supplied to the control electrode of the eleventh emission control transistor T11 via the tenth emission control transistor T10, turning the eleventh emission control transistor T11 on. The potential of the first emission control node EMN1 charges the first terminal of the third emission control capacitor C3, which then stores a low level.

[0271] The twelfth light emitting control transistor T12 is turned off by the high level of the second clock signal ECB, and the first light emitting control node EMN1 is disconnected from the fifth light emitting control node EMN5.

[0272] Under the control of the first enable signal EN_O, the sixth emission control transistor T6 is turned on, the low level of the second emission control node EMN2 is provided to the third emission control node EMN3, and the seventh emission control transistor T7 and the fifteenth emission control transistor T15 are turned on.

[0273] Under the control of the low level of the second emission control node EMN2, the thirteenth emission control transistor T13 is turned on, and the second power supply voltage VGH is provided to the fifth emission control node EMN5 through the thirteenth emission control transistor T13. The fourteenth emission control transistor T14, the sixteenth emission control transistor T16, and the eighteenth emission control transistor T18 are turned off by the high level of the fifth emission control node EMN5.

[0274] The high level of the second light emitting control node EMN2 is provided to the control electrode of the nineteenth light emitting control transistor T19 via the twentieth light emitting control transistor T20, and the nineteenth light emitting control transistor T19 is turned on.

[0275] The eighth light emitting control transistor T8 is turned off by the high level of the second enable signal EN_E. The second light emitting control node EMN2 is disconnected from the fourth light emitting control node EMN4.

[0276] When the fifteenth emission control transistor T15 is turned on and the fourteenth emission control transistor T14 is turned off, the first power supply voltage VGL is provided to the first emission control output terminal EOUT_O. At this time, the first emission control signal EOUT_O output by the first emission control output terminal EOUT_O is at a low level.

[0277] When the nineteenth emission control transistor T19 is turned on and the eighteenth emission control transistor T18 is turned off, the first power supply voltage VGL is provided to the third emission control output terminal EOUT_n. At this time, the third emission control signal EOUT_n outputted by the third emission control output terminal EOUT_n is at a low level.

[0278] When the eighth light emitting control transistor T8 and the sixteenth light emitting control transistor T16 are both turned off, the second light emitting control signal EOUT_E output by the second light emitting control output terminal EOUT_E is the same as that in the previous stage S4 , and the second light emitting control signal EOUT_E is at a high level.

[0279] In the disclosed embodiment, by controlling the first enable signal EN_O to be low and the second enable signal EN_E to be high, the first light-emitting control signal EOUT_O outputted by the first light-emitting control output terminal EOUT_O is a pulse waveform, and the second light-emitting control signal EOUT_E outputted by the second light-emitting control output terminal EOUT_E is a DC signal, with the second light-emitting control signal EOUT_E remaining at a high level. In this case, when the first light-emitting control signal EOUT_O is used to drive the anti-peeping sub-pixel, the anti-peeping sub-pixel operates, and the light-emitting element in the pixel circuit of the anti-peeping sub-pixel emits light. When the second light-emitting control signal EOUT_E is used to drive the display sub-pixel, the display sub-pixel does not operate under the drive of the DC second light-emitting control signal EOUT_E, and the light-emitting element in the pixel circuit of the display sub-pixel does not emit light.

[0280] By turning off a group of sub-pixels using an enable signal, the group of sub-pixels is not operational and no data voltage needs to be written to the group of sub-pixels, thereby reducing power consumption. Since the second light-emitting control signal EOUT_E is a DC signal, the logic power consumption generated by the voltage jump of the second light-emitting control signal EOUT_E can be reduced when the display sub-pixels are not operational.

[0281] For example, FIG6C shows the signal timings output by the first light emitting control output terminal EOUT_O, the second light emitting control output terminal EOUT_E, and the third light emitting control output terminal EOUT_n when the first enable signal EN_O is high and the second enable pixel EN_E is low.

[0282] FIG6C shows the operation process of the light emitting control shift register 600 shown in FIG6A under signal control, which is similar to the operation process of the light emitting control shift register 600 shown in FIG6A under signal control shown in FIG6B . For simplicity, similar parts are not repeated here.

[0283] In the first phase S1 , the first light emitting control input signal EIN_n is high, the first clock signal ECK is low, the second clock signal ECB is high, the first enable signal EN_O is high, and the second enable signal EN_E is low.

[0284] The first emission control transistor T1, the second emission control transistor T2, the fourth emission control transistor T4, the eighth emission control transistor T8, the tenth emission control transistor T10, the eleventh emission control transistor T11, and the twentieth emission control transistor T20 are turned on, while the third emission control transistor T3, the fifth emission control transistor T5 to the seventh emission control transistor T7, the ninth emission control transistor T9, and the twelfth emission control transistors T12 to the nineteenth emission control transistors T19 are turned off. The potential of the first emission control node EMN1 is low, the potential of the second emission control node EMN2 is high, the potential of the fourth emission control node EMN4 is high, and the potential of the fifth emission control node EMN5 is high.

[0285] The first light control signal EOUT_O outputted by the first light control output terminal EOUT_O is at a high level. The second light control signal EOUT_E outputted by the second light control output terminal EOUT_E is at a low level. The third light control signal EOUT_n outputted by the third light control output terminal EOUT_n is at a low level.

[0286] In the second phase S2 , the first light emitting control input signal EIN_n is high, the first clock signal ECK is high, the second clock signal ECB is low, the first enable signal EN_O is high, and the second enable signal EN_E is low.

[0287] The fourth emission control transistor T4, the fifth emission control transistor T5, the eighth emission control transistor T8, the tenth emission control transistors T10 to T12, the fourteenth emission control transistor T14, the sixteenth emission control transistor T16, the eighteenth emission control transistor T18, and the twentieth emission control transistor T20 are turned on, while the first emission control transistor T1 to T3, the sixth emission control transistor T6, the seventh emission control transistor T7, the ninth emission control transistor T9, the thirteenth emission control transistor T13, the fifteenth emission control transistor T15, the seventeenth emission control transistor T17, and the nineteenth emission control transistor T19 are turned off. The potential of the first emission control node EMN1 is low, the potential of the second emission control node EMN2 is high, the potential of the fourth emission control node EMN4 is high, and the potential of the fifth emission control node EMN5 is low.

[0288] The first light control signal EOUT_O outputted by the first light control output terminal EOUT_O is at a high level. The second light control signal EOUT_E outputted by the second light control output terminal EOUT_E is at a high level. The third light control signal EOUT_n outputted by the third light control output terminal EOUT_n is at a high level.

[0289] In the third phase S3 , the first light emitting control input signal EIN_n is high, the first clock signal ECK is low, the second clock signal ECB is high, the first enable signal EN_O is high, and the second enable signal EN_E is low.

[0290] The first emission control transistor T1, the second emission control transistor T2, the fourth emission control transistor T4, the eighth emission control transistor T8, the tenth emission control transistor T10, the eleventh emission control transistor T11, the fourteenth emission control transistor T14, the sixteenth emission control transistor T16, the eighteenth emission control transistor T18, and the twentieth emission control transistor T20 are turned on, while the third emission control transistor T3, the fifth emission control transistors T5 to T7, the ninth emission control transistor T9, the twelfth emission control transistor T12, the thirteenth emission control transistor T13, the fifteenth emission control transistor T15, the seventeenth emission control transistor T17, and the nineteenth emission control transistor T19 are turned off. The potential of the first emission control node EMN1 is low, the potential of the second emission control node EMN2 is high, the potential of the fourth emission control node EMN4 is high, and the potential of the fifth emission control node EMN5 is low.

[0291] The first light control signal EOUT_O outputted by the first light control output terminal EOUT_O is at a high level. The second light control signal EOUT_E outputted by the second light control output terminal EOUT_E is at a high level. The third light control signal EOUT_n outputted by the third light control output terminal EOUT_n is at a high level.

[0292] In the fourth stage S4 , the first light emitting control input signal EIN_n is low, the first clock signal ECK is high, the second clock signal ECB is low, the first enable signal EN_O is high, and the second enable signal EN_E is low.

[0293] The fourth emission control transistor T4, the fifth emission control transistor T5, the eighth emission control transistor T8, the tenth emission control transistor T10, the eleventh emission control transistor T11, the fourteenth emission control transistor T14, the sixteenth emission control transistor T16, the eighteenth emission control transistor T18, and the twentieth emission control transistor T20 are turned on, while the first emission control transistors T1 to T3, the sixth emission control transistor T6, the seventh emission control transistor T7, the ninth emission control transistor T9, the thirteenth emission control transistor T13, the fifteenth emission control transistor T15, the seventeenth emission control transistor T17, and the nineteenth emission control transistor T19 are turned off. The potential of the first emission control node EMN1 is low, the potential of the second emission control node EMN2 is high, the potential of the fourth emission control node EMN4 is high, and the potential of the fifth emission control node EMN5 is low.

[0294] The first light control signal EOUT_O outputted by the first light control output terminal EOUT_O is at a high level. The second light control signal EOUT_E outputted by the second light control output terminal EOUT_E is at a high level. The third light control signal EOUT_n outputted by the third light control output terminal EOUT_n is at a high level.

[0295] In the fifth stage S5 , the first light emitting control input signal EIN_n is low, the first clock signal ECK is low, the second clock signal ECB is high, the first enable signal EN_O is high, and the second enable signal EN_E is low.

[0296] The first to fourth emission control transistors T1 to T4, the eighth to eleventh emission control transistors T8 to T11, the thirteenth emission control transistor T13, the seventeenth emission control transistor T17, the nineteenth emission control transistor T190, and the twentieth emission control transistor T20 are turned on, while the fifth to seventh emission control transistors T5 to T7, the twelfth emission control transistor T12, the fourteenth to sixteenth emission control transistors T14 to T16, and the eighteenth emission control transistor T18 are turned off. The potential of the first emission control node EMN1 is low, the potential of the second emission control node EMN2 is low, the potential of the fourth emission control node EMN4 is high, and the potential of the fifth emission control node EMN5 is low.

[0297] The first light control signal EOUT_O outputted by the first light control output terminal EOUT_O is at a high level. The second light control signal EOUT_E outputted by the second light control output terminal EOUT_E is at a low level. The third light control signal EOUT_n outputted by the third light control output terminal EOUT_n is at a low level.

[0298] In the disclosed embodiment, by controlling the first enable signal EN_O to be high and the second enable signal EN_E to be low, the first light-emitting control signal EOUT_O outputted by the first light-emitting control output terminal EOUT_O is a direct current signal. The first light-emitting control signal EOUT_O remains high, while the second light-emitting control signal EOUT_E outputted by the second light-emitting control output terminal EOUT_E is a pulse waveform. In this case, when the first light-emitting control signal EOUT_O is used to drive the anti-peeping sub-pixel, the anti-peeping sub-pixel is not operated under the drive of the first direct current light-emitting control signal EOUT_O, and the light-emitting element in the pixel circuit of the anti-peeping sub-pixel does not emit light. When the second light-emitting control signal EOUT_E is used to drive the display sub-pixel, the display sub-pixel is operated, and the light-emitting element in the pixel circuit of the display sub-pixel emits light.

[0299] Since the first light emitting control signal EOUT_O is a direct current signal, the logic power consumption generated by the voltage jump of the first light emitting control signal EOUT_O can be reduced when the anti-peeping sub-pixel is not working.

[0300] When the first enable signal EN_O is low and the second enable signal EN_E is high, the timing of the first light control signal EOUT_O outputted by the first light control output terminal EOUT_O is the same as the timing of the third gate drive signal EOUT_n outputted by the third light control output terminal EOUT_n.

[0301] When the first enable signal EN_O is high and the second enable signal EN_E is low, the timing of the second light control signal EOUT_E outputted from the second light control output terminal EOUT_E is the same as the timing of the third light control signal EOUT_n outputted from the third light control output terminal EOUT_n.

[0302] In an embodiment of the present disclosure, the output of the first emission control signal EOUT_O is controlled based on the first enable signal EN_O, and the output of the second emission control signal EOUT_E is controlled based on the second enable signal EN_E. When the first emission control signal EOUT_O drives the anti-peeping sub-pixel and the second emission control signal EOUT_E drives the display sub-pixel, the operating state of the anti-peeping sub-pixel can be independently controlled by controlling the first enable signal EN_O, and the operating state of the display sub-pixel can be controlled by controlling the level of the second enable signal EN_E. Accordingly, when the first emission control signal EOUT_O drives the display sub-pixel and the second emission control signal EOUT_E drives the anti-peeping sub-pixel, the operating state of the display sub-pixel can be independently controlled by controlling the first enable signal EN_O, and the operating state of the anti-peeping sub-pixel can be controlled by controlling the level of the second enable signal EN_E.

[0303] For example, when the first light-emitting control signal EOUT_O drives the anti-peeping sub-pixel and the second light-emitting control signal EOUT_E drives the display sub-pixel, by controlling the level of the first enable signal EN_O to be low, the anti-peeping sub-pixel can be independently controlled to be in an active state. By controlling the level of the first enable signal EN_O to be high, the anti-peeping sub-pixel can be independently controlled to be in an inactive state. By controlling the level of the second enable signal EN_E to be low, the display sub-pixel can be independently controlled to be in an active state. By controlling the level of the second enable signal EN_E to be high, the display sub-pixel can be independently controlled to be in an inactive state.

[0304] In the embodiment of the present disclosure, the seventh emission control transistor T7 can prevent the control electrode of the fifteenth emission control transistor T15 from being in a floating state. The ninth emission control transistor T9 can prevent the control electrode of the seventeenth emission control transistor T17 from being in a floating state.

[0305] In the embodiment of the present disclosure, by providing a signal terminal to which the second electrodes of the seventh scanning transistor T7 and the ninth scanning transistor T9 are electrically connected, a partial refresh of the display image in the display panel can be achieved.

[0306] In some embodiments, the present disclosure further provides a shift register, which can be a scanning shift register or a light-emitting control shift register.

[0307] In the embodiment of the present disclosure, the scanning shift register may be the scanning shift register 300a, scanning shift register 400a and scanning shift register 500 described above. The light control shift register may be the light control shift register 300b, light control shift register 400b and light control shift register 600 described above.

[0308] In the embodiment of the present disclosure, a scanning shift register and a light emitting control shift register form a driving unit in a driving circuit, which can provide gate driving signals and light emitting control signals for a row of pixels in a pixel array.

[0309] FIG7A is a schematic structural diagram of a driving circuit according to an embodiment of the present disclosure.

[0310] As shown in Fig. 7A, the driving circuit 700a includes M cascaded shift registers, where M is a positive integer greater than 1. The M shift registers include a shift register 7101, a shift register 7102, ..., and a scanning shift register 710M.

[0311] In the embodiment of the present disclosure, the shift register may be the scanning shift register 300a, the scanning shift register 400a, and the scanning shift register 500 described above, and may also be the light-emitting control shift register 300b, the light-emitting control shift register 400b, and the light-emitting control shift register 600 described above. The shift register may also include any one of the scanning shift register 300a, the scanning shift register 400a, and the scanning shift register 500 described above, and any one of the light-emitting control shift register 300b, the light-emitting control shift register 400b, and the light-emitting control shift register 600 described above.

[0312] In the embodiment of the present disclosure, the input end of the m-th stage shift register is electrically connected to the output end of the m-1-th stage shift register, 1<m≤M.

[0313] In the embodiment of the present disclosure, the input terminal INPUT of the first-stage shift register 7101 is electrically connected to the trigger signal terminal STV.

[0314] In the embodiment of the present disclosure, each shift register of the driving circuit 700 a can provide a gate driving signal and a light emitting control signal for a row of pixels in the pixel array.

[0315] FIG7B is a schematic structural diagram of a gate driving circuit according to an embodiment of the present disclosure.

[0316] As shown in FIG7B , the gate driving circuit 700 b includes M cascaded scanning shift registers, where M is a positive integer greater than 1. The M scanning shift registers include a scanning shift register ST1 , a scanning shift register ST2 , . . . , and a scanning shift register STM.

[0317] In the embodiment of the present disclosure, the scanning shift register may be the scanning shift register 300 a , the scanning shift register 400 a , and the scanning shift register 500 mentioned above.

[0318] In the embodiment of the present disclosure, in the cascaded M scanning shift registers, the scanning input terminal INPUT of the m-th level scanning shift register is electrically connected to the third scanning output terminal OUTPUT3 of the m-1-th level scanning shift register, and the third scanning output terminal OUTPUT3 of the m-th level scanning shift register is electrically connected to the scanning input terminal INPUT of the m+1-th level scanning shift register, 1<m≤M-1.

[0319] For example, the scan input terminal INPUT of the second-level scan shift register ST2 is electrically connected to the third scan output terminal OUTPUT3 of the first-level scan shift register ST1, and the third gate drive signal GOUT(1) output by the third scan output terminal OUTPUT3 of the first-level scan shift register ST1 is the input signal of the scan input terminal INPUT of the second-level scan shift register ST2.

[0320] In the embodiment of the present disclosure, the scan input terminal INPUT of the first-stage scan shift register ST1 is electrically connected to the scan trigger signal terminal GSTV, and the third scan output terminal OUTPUT3 of the M-th-stage scan shift register STM is electrically connected to the anti-static terminal ESD.

[0321] In the embodiment of the present disclosure, the first power supply terminal VGL of the cascaded M scan shift registers is electrically connected to the power supply terminal Vgl, which provides a low-potential voltage. The second power supply terminal VGH of the cascaded M scan shift registers is electrically connected to the power supply terminal Vgh, which provides a high-potential voltage.

[0322] In the embodiment of the present disclosure, the first clock terminal GCK of the cascaded M scan shift registers is electrically connected to the clock signal terminal CK to receive the first clock signal GCK. The second clock terminal GCB of the cascaded M scan shift registers is electrically connected to the clock signal terminal CB to receive the second clock signal GCB.

[0323] In the embodiment of the present disclosure, the first enable terminal EN_O of the cascaded M scan shift registers is electrically connected to the enable terminal EN1 to receive the first enable signal EN_O, and the second enable terminal EN_E of the cascaded M scan shift registers is electrically connected to the enable terminal EN2 to receive the second enable signal EN_E.

[0324] FIG7C is a schematic structural diagram of a light emitting control driving circuit according to an embodiment of the present disclosure.

[0325] 7C , the light emission control driving circuit 700 c includes M cascaded light emission control shift registers, where M is a positive integer greater than 1. The M light emission control shift registers include a light emission control shift register ET1 , a light emission control shift register ET2 , . . . , and a light emission control shift register ETM.

[0326] In the embodiment of the present disclosure, the light emitting control shift register may be the light emitting control shift register 300 b , the light emitting control shift register 400 b and the light emitting control shift register 600 mentioned above.

[0327] In the embodiment of the present disclosure, in the cascaded M light-emitting control shift registers, the light-emitting control input terminal INPUT of the m-th light-emitting control shift register is electrically connected to the third light-emitting control output terminal OUTPUT3 of the m-1-th light-emitting control shift register, and the third light-emitting control output terminal OUTPUT3 of the m-th light-emitting control shift register is electrically connected to the light-emitting control input terminal INPUT of the m+1-th light-emitting control shift register, 1<m≤M-1.

[0328] For example, the light control input terminal INPUT of the second-level light control shift register ET2 is electrically connected to the third light control output terminal OUTPUT3 of the first-level light control shift register ET1, and the third light control signal EOUT(1) output by the third light control output terminal OUTPUT3 of the first-level light control shift register ET1 is the input signal of the light control input terminal INPUT of the second-level light control shift register ET2.

[0329] In the embodiment of the present disclosure, the light control input terminal INPUT of the first-stage light control shift register ET1 is electrically connected to the light control trigger signal terminal ESTV, and the third light control output terminal OUTPUT3 of the M-th-stage light control shift register ETM is electrically connected to the anti-static terminal ESD.

[0330] In the embodiment of the present disclosure, the first power supply terminal VGL of the cascaded M light-emitting control shift registers is electrically connected to the power supply terminal Vgl, which provides a low-potential voltage. The second power supply terminal VGH of the cascaded M light-emitting control shift registers is electrically connected to the power supply terminal Vgh, which provides a high-potential voltage.

[0331] In the embodiment of the present disclosure, the first clock terminal ECK of the cascaded M light-emitting control shift registers is electrically connected to the clock signal terminal CK to receive the first clock signal ECK. The second clock terminal ECB of the cascaded M light-emitting control shift registers is electrically connected to the clock signal terminal CB to receive the second clock signal ECB.

[0332] In the embodiment of the present disclosure, the first enable terminal EN_O of the cascaded M light-emitting control shift registers is electrically connected to the enable terminal EN1 to receive the first enable signal EN_O. The second enable terminal EN_E of the cascaded M light-emitting control shift registers is electrically connected to the enable terminal EN2 to receive the second enable signal EN_E.

[0333] FIG8A is a schematic structural diagram of a pixel unit according to an embodiment of the present disclosure.

[0334] As shown in FIG8A , the pixel unit P1 includes a first sub-pixel group Pixel O1 and a second sub-pixel group Pixel E1 .

[0335] In the embodiment of the present disclosure, the first sub-pixel group Pixel O1 may include the first sub-pixel Sub-Pixel O1_1, the first sub-pixel Sub-Pixel O1_2, and the first sub-pixel Sub-Pixel O1_3. The second sub-pixel group Pixel E1 may include the second sub-pixel Sub-Pixel E1_1, the second sub-pixel Sub-Pixel E1_2, and the second sub-pixel Sub-Pixel E1_3.

[0336] For example, the first sub-pixel Sub-Pixel O1_1, the first sub-pixel Sub-Pixel O1_2, and the first sub-pixel Sub-Pixel O1_3 may be privacy-prevention sub-pixels. The second sub-pixel Sub-Pixel E1_1, the second sub-pixel Sub-Pixel E1_2, and the second sub-pixel Sub-Pixel E1_3 may be display sub-pixels. When the first sub-pixel Sub-Pixel O1_1, the first sub-pixel Sub-Pixel O1_2, and the first sub-pixel Sub-Pixel O1_3 are in an operating state, and the second sub-pixel Sub-Pixel E1_1, the second sub-pixel Sub-Pixel E1_2, and the second sub-pixel Sub-Pixel E1_3 are in an inoperative state, the display device is in privacy-prevention mode. When the first sub-pixel Sub-Pixel O1_1, the first sub-pixel Sub-Pixel O1_2, and the first sub-pixel Sub-Pixel O1_3 are in an inoperative state, and the second sub-pixel Sub-Pixel E1_1, the second sub-pixel Sub-Pixel E1_2, and the second sub-pixel Sub-Pixel E1_3 are in an operating state, the display device is in normal display mode.

[0337] For example, the first sub-pixel Sub-Pixel O1_1, the first sub-pixel Sub-Pixel O1_2, and the first sub-pixel Sub-Pixel O1_3 may also be display sub-pixels, and the second sub-pixel Sub-Pixel E1_1, the second sub-pixel Sub-Pixel E1_2, and the second sub-pixel Sub-Pixel E1_3 may be anti-peep sub-pixels.

[0338] In the embodiment of the present disclosure, the first sub-pixel Sub-Pixel O1_1, the first sub-pixel Sub-Pixel O1_2, and the first sub-pixel Sub-Pixel O1_3 can be considered as sub-pixels in the same row. The second sub-pixels Sub-Pixel E1_1, the second sub-pixel Sub-Pixel E1_2, and the second sub-pixel Sub-Pixel E1_3 can be considered as sub-pixels in the same row.

[0339] For example, the first sub-pixel Sub-Pixel O1_1, the first sub-pixel Sub-Pixel O1_2, and the first sub-pixel Sub-Pixel O1_3 may be sub-pixels in the first row of the pixel array, and the second sub-pixel Sub-Pixel E1_1, the second sub-pixel Sub-Pixel E1_2, and the second sub-pixel Sub-Pixel E1_3 may be sub-pixels in the second row of the pixel array. Gate drive signals and light-emitting control signals are provided to the two rows of sub-pixels via a first-level shift register.

[0340] In the embodiment of the present disclosure, it is possible to configure that all sub-pixels in odd-numbered rows of a pixel array in a display panel are anti-peeping sub-pixels, and all sub-pixels in even-numbered rows are display sub-pixels.

[0341] FIG8B is a schematic structural diagram of a display device according to an embodiment of the present disclosure.

[0342] As shown in FIG. 8B , the display device 800 includes a display panel 810 and a driving circuit 820 .

[0343] In the embodiment of the present disclosure, the display panel 810 includes a plurality of pixel units. The structure of each pixel unit may be as shown in FIG8A .

[0344] For example, the pixel unit 810_1 includes a first sub-pixel group Pixel O1 and a second sub-pixel group Pixel E1. The first sub-pixel group Pixel O1 is electrically connected to the first scan output terminal GOUT(1)_O of the first-stage scan shift register ST1 of the shift register 820_1 in the driving circuit 820 and the first light-emitting control output terminal EOUT(1)_O of the first-stage light-emitting control shift register ET1, and the second sub-pixel group Pixel E1 is electrically connected to the second scan output terminal GOUT(1)_E of the first-stage scan shift register ST1 of the shift register 820_1 in the driving circuit 820 and the second light-emitting control output terminal EOUT(1)_E of the first-stage light-emitting control shift register ET1.

[0345] In the embodiment of the present disclosure, the light emission angles of the multiple first sub-pixels included in the first sub-pixel group Pixel O1 are smaller than the light emission angles of the multiple second sub-pixels included in the second sub-pixel group Pixel E1. The light emission angle is the angle between the emitted light and a direction perpendicular to the display panel. For example, the multiple first sub-pixels included in the first sub-pixel group Pixel O1 may be privacy-prevention sub-pixels, and the multiple second sub-pixels included in the second sub-pixel group Pixel E1 may be display sub-pixels.

[0346] FIG9A is a schematic structural diagram of a pixel unit according to another embodiment of the present disclosure.

[0347] As shown in FIG. 9A , the pixel unit P2 includes a first sub-pixel group Pixel O2 and a second sub-pixel group Pixel E2 .

[0348] In the embodiment of the present disclosure, the first sub-pixel group Pixel O2 may include the first sub-pixel Sub-Pixel O2_1, the first sub-pixel Sub-Pixel O2_2, and the first sub-pixel Sub-Pixel O2_3. The second sub-pixel group Pixel E2 may include the second sub-pixel Sub-Pixel E2_1, the second sub-pixel Sub-Pixel E2_2, and the second sub-pixel Sub-Pixel E2_3.

[0349] For example, the first sub-pixel Sub-Pixel O2_1, the first sub-pixel Sub-Pixel O2_2, and the first sub-pixel Sub-Pixel O2_3 may be privacy-prevention sub-pixels. The second sub-pixel Sub-Pixel E2_1, the second sub-pixel Sub-Pixel E2_2, and the second sub-pixel Sub-Pixel E2_3 may be display sub-pixels. When the first sub-pixel Sub-Pixel O2_1, the first sub-pixel Sub-Pixel O2_2, and the first sub-pixel Sub-Pixel O2_3 are in an operating state, and the second sub-pixel Sub-Pixel E2_1, the second sub-pixel Sub-Pixel E2_2, and the second sub-pixel Sub-Pixel E2_3 are in an inoperative state, the display device is in privacy-prevention mode. When the first sub-pixel Sub-Pixel O2_1, the first sub-pixel Sub-Pixel O2_2, and the first sub-pixel Sub-Pixel O2_3 are in an inoperative state, and the second sub-pixel Sub-Pixel E2_1, the second sub-pixel Sub-Pixel E2_2, and the second sub-pixel Sub-Pixel E2_3 are in an operating state, the display device is in a normal display mode.

[0350] For example, the first sub-pixel Sub-Pixel O2_1, the first sub-pixel Sub-Pixel O2_2, and the first sub-pixel Sub-Pixel O2_3 may also be display sub-pixels, while the second sub-pixel Sub-Pixel E2_1, the second sub-pixel Sub-Pixel E2_2, and the second sub-pixel Sub-Pixel E2_3 may be anti-peep sub-pixels.

[0351] In the embodiment of the present disclosure, the first sub-pixel Sub-Pixel O2_1, the first sub-pixel Sub-Pixel O2_2, the first sub-pixel Sub-Pixel O2_3, the second sub-pixel Sub-Pixel E2_1, the second sub-pixel Sub-Pixel E2_2, and the second sub-pixel Sub-Pixel E2_3 can be considered as sub-pixels in the same row. The first sub-pixel Sub-Pixel O2_1, the first sub-pixel Sub-Pixel O2_2, and the first sub-pixel Sub-Pixel O2_3 can be considered as sub-pixels in the same column. The second sub-pixel Sub-Pixel E2_1, the second sub-pixel Sub-Pixel E2_2, and the second sub-pixel Sub-Pixel E2_3 can be considered as sub-pixels in the same column.

[0352] For example, the first sub-pixel Sub-Pixel O2_1, the first sub-pixel Sub-Pixel O2_2, the first sub-pixel Sub-Pixel O2_3, the second sub-pixel Sub-Pixel E2_1, the second sub-pixel Sub-Pixel E2_2, and the second sub-pixel Sub-Pixel E2_3 are all sub-pixels in the first row, and the same shift register provides gate drive signals and light-emitting control signals for the sub-pixels in a row. The first sub-pixel Sub-Pixel O2_1, the first sub-pixel Sub-Pixel O2_2, and the first sub-pixel Sub-Pixel O2_3 may be sub-pixels in the first column of the pixel array, and the first sub-pixel Sub-Pixel E2_1, the second sub-pixel Sub-Pixel E2_2, and the third sub-pixel Sub-Pixel E2_3 may be sub-pixels in the second column of the pixel array.

[0353] In the embodiment of the present disclosure, it is possible to configure that all sub-pixels in odd-numbered columns of a pixel array in a display panel are anti-peeping sub-pixels, and all sub-pixels in even-numbered columns are display sub-pixels.

[0354] FIG9B is a schematic structural diagram of a display device according to another embodiment of the present disclosure.

[0355] As shown in FIG. 9B , the display device 900 includes a display panel 910 and a driving circuit 920 .

[0356] In the embodiment of the present disclosure, the display panel 910 includes a plurality of pixel units, and the structure of each pixel unit may be as shown in FIG9A .

[0357] For example, the pixel unit 910_1 includes a first sub-pixel group Pixel O2 and a second sub-pixel group Pixel E2. The first sub-pixel group Pixel O2 is electrically connected to the first scan output terminal GOUT(1)_O of the first-stage scan shift register ST1 of the shift register 920_1 in the driving circuit 920 and the first light-emitting control output terminal EOUT(1)_O of the first-stage light-emitting control shift register ET1, and the second sub-pixel group Pixel E2 is electrically connected to the second scan output terminal GOUT(1)_E of the first-stage scan shift register ST1 of the shift register 920_1 in the driving circuit 920 and the second light-emitting control output terminal EOUT(1)_E of the first-stage light-emitting control shift register ET1.

[0358] In the embodiment of the present disclosure, the light emission angles of the multiple first sub-pixels included in the first sub-pixel group Pixel O2 are smaller than the light emission angles of the multiple second sub-pixels included in the second sub-pixel group Pixel E2. The light emission angle is the angle between the emitted light and a direction perpendicular to the display panel. For example, the multiple first sub-pixels included in the first sub-pixel group Pixel O2 may be privacy-prevention sub-pixels, and the multiple second sub-pixels included in the second sub-pixel group Pixel E2 may be display sub-pixels.

[0359] FIG10 is a flowchart of a driving method according to an embodiment of the present disclosure.

[0360] As shown in FIG10 , the driving method can be applied to the scanning shift register 300 a, the scanning shift register 400 a, and the scanning shift register 500 described above. The driving method can also be applied to the light emission control shift register 300 b, the light emission control shift register 400 b, and the light emission control shift register 600 described above. The driving method can also be applied to any one of the scanning shift register 300 a, the scanning shift register 400 a, and the scanning shift register 500 described above, and any one of the light emission control shift register 300 b, the light emission control shift register 400 b, and the light emission control shift register 600 described above.

[0361] In an embodiment of the present disclosure, the driving method may include operations S1010 to S1030.

[0362] In operation S1010, the first enable signal from the first enable terminal is at a first level and the second enable signal from the second enable terminal is at a second level, and the first output terminal among the control input terminals outputs a pulse signal and the second output terminal among the input terminals outputs a DC signal.

[0363] In operation S1020 , the first enable signal is at the second level and the second enable signal is at the first level, and the first output terminal is controlled to output a direct current signal and the second output terminal is controlled to output a pulse signal.

[0364] In operation S1030 , the first enable signal and the second enable signal are both at the first level, and the first output terminal and the second output terminal are controlled to output pulse signals.

[0365] FIG. 11A is a flowchart of a driving method according to another embodiment of the present disclosure.

[0366] 11A , the driving method may be applied to the aforementioned scanning shift registers 300a, 400a, and 500. The driving method may include operations S1110a to S1130a.

[0367] In operation S1110a, the first enable signal from the first enable terminal is at a first level and the second enable signal from the second enable terminal is at a second level, controlling the first scan output terminal to output a pulse signal and the second scan output terminal to output a DC signal.

[0368] In operation S1120a, the first enable signal is at the second level and the second enable signal is at the first level, and the first scan output terminal is controlled to output a direct current signal and the second scan output terminal is controlled to output a pulse signal.

[0369] In operation S1130a, the first enable signal and the second enable signal are both at the first level, and the first scan output terminal and the second scan output terminal are controlled to output pulse signals.

[0370] In the embodiment of the present disclosure, operations S1110a to S1130a are similar to the operations performed by the scan shift register 500 described above, and are not described again herein.

[0371] In the embodiment of the present disclosure, the first level is a low level and the second level is a high level. Those skilled in the art may also set the first level to a high level and the second level to a low level according to the type of transistors in the shift register.

[0372] FIG. 11B is a flowchart of a driving method according to another embodiment of the present disclosure.

[0373] 11B , the driving method may be applied to the aforementioned light emission control shift registers 300b, 400b, and 600. The driving method may include operations S1110b to S1130b.

[0374] In operation S1110b, the first enable signal from the first enable terminal is at a first level and the second enable signal from the second enable terminal is at a second level, controlling the first light emitting control output terminal to output a pulse signal and the second light emitting control output terminal to output a DC signal.

[0375] In operation S1120b, the first enable signal is at the second level and the second enable signal is at the first level, and the first light-emitting control output terminal is controlled to output a direct current signal and the second light-emitting control output terminal is controlled to output a pulse signal.

[0376] In operation S1130b, the first enable signal and the second enable signal are both at the first level, and the first light-emitting control output terminal and the second light-emitting control output terminal are controlled to output pulse signals.

[0377] In the embodiment of the present disclosure, operations S1110b to S1130b are similar to the operations performed by the light emitting control shift register 600 described above, and are not described again herein.

[0378] In the embodiment of the present disclosure, the first level is a low level and the second level is a high level. Those skilled in the art may also set the first level to a high level and the second level to a low level according to the type of transistors in the shift register.

[0379] FIG12 is a schematic structural diagram of a scan shift register according to an embodiment of the present disclosure.

[0380] As shown in FIG. 12 , the shift register 1200 includes an input circuit 1210 , a control circuit 1220 , and an output circuit 1230 .

[0381] In the embodiment of the present disclosure, operations S1010 to S1030 included in the driving method described above may be applied to the shift register 1200 .

[0382] In the embodiment of the present disclosure, the input circuit 1210 is configured to, under the control of a first clock signal CK from a first clock terminal CK, provide a first power supply voltage VGL from a first power supply terminal VGL to a first node N1, and provide an input signal INPUT from an input terminal INPUT to a second node N. The control circuit 1220 is configured to, under the control of a first enable signal EN_O from a first enable terminal EN_O, provide a potential at a second node N2 to a third node N3, and under the control of a second enable signal EN_E from a second enable terminal EN_E, provide a potential at the second node N2 to a fourth node N4. The output circuit 1230 is configured to output a signal through an output terminal OUTPUT, under the control of the potentials of the first node N1, the second node N2, the third node N3, and the fourth node N4.

[0383] In the embodiment of the present disclosure, the shift register 1200 may be the scanning shift register 300a, the scanning shift register 400a, and the scanning shift register 500 described above. The shift register 1200 may also be the light-emission control shift register 300b, the light-emission control shift register 400b, and the light-emission control shift register 600 described above. The shift register 1200 may also include any one of the scanning shift register 300a, the scanning shift register 400a, and the scanning shift register 500 described above, and any one of the light-emission control shift register 300b, the light-emission control shift register 400b, and the light-emission control shift register 600 described above.

[0384] In the embodiment of the present disclosure, the input circuit 1210 may be the scan input circuit 310, the scan input circuit 410, and the scan input circuit 510 described above. The input circuit 1210 may also be the light emission control input circuit 340, the light emission control input circuit 440, and the light emission control input circuit 640. The input circuit 1210 may further include any one of the scan input circuit 310, the scan input circuit 410, and the scan input circuit 510 and any one of the light emission control input circuit 340, the light emission control input circuit 440, and the light emission control input circuit 640.

[0385] In the embodiment of the present disclosure, the control circuit 1220 may be the scan control circuit 320, the scan control circuit 420, and the scan control circuit 520 described above. The control circuit 1220 may also be the light-emission control circuit 350, the light-emission control circuit 450, and the light-emission control circuit 650. The control circuit 1220 may also include any one of the scan control circuit 320, the scan control circuit 420, and the scan control circuit 520 and any one of the light-emission control circuit 350, the light-emission control circuit 450, and the light-emission control circuit 650.

[0386] In the embodiment of the present disclosure, the output circuit 1230 may be the scan output circuit 330, the scan output circuit 430, and the scan output circuit 530 described above. The output circuit 1230 may also be the light emission control output circuit 360, the light emission control output circuit 460, and the light emission control output circuit 660. The output circuit 1230 may further include any one of the scan output circuit 330, the scan output circuit 430, and the scan output circuit 530 and any one of the light emission control output circuit 360, the light emission control output circuit 460, and the light emission control output circuit 660.

[0387] In the embodiment of the present disclosure, the first node N1 may be the first scanning node SN1 described above, or the first emission control node EMN1 described above. The first node N1 may further include the first scanning node SN1 and the first emission control node EMN1. The second node N2 may be the second scanning node SN2 described above, or the second emission control node EMN2 described above. The second node N2 may further include the second scanning node SN2 and the second emission control node EMN2. The third node N3 may be the third scanning node SN3 described above, or the third emission control node EMN3 described above. The third node N3 may further include the third scanning node SN3 and the third emission control node EMN3. The fourth node N4 may be the fourth scanning node SN4 described above, or the fourth emission control node EMN4 described above. The fourth node N4 may further include the first scanning node SN4 and the fourth emission control node EMN4.

[0388] In the embodiment of the present disclosure, the input terminal INPUT may be the scan input terminal GIN_n described above, or the light emitting control input terminal EIN_n described above. The input terminal INPUT may further include the scan input terminal GIN_n and the light emitting control input terminal EIN_n.

[0389] In the embodiment of the present disclosure, the output terminal OUTPUT may include the first scan output terminal GOUT_O, the second scan output terminal GOUT_E, and the third scan output terminal GOUT_n described above. The output terminal OUTPUT may include the first light emission control output terminal EOUT_O, the second light emission control output terminal EOUT_E, and the third light emission control output terminal EOUT_n described above.

[0390] The flowcharts and block diagrams in the accompanying drawings illustrate the possible implementation architecture, functions and operations of the systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each box in the flowchart or block diagram can represent a module, program segment, or a part of code, and the above-mentioned module, program segment, or a part of code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in an order different from that marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram or flowchart, and the combination of boxes in the block diagram or flowchart, can be implemented with a dedicated hardware-based system that performs the specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0391] Those skilled in the art will appreciate that various combinations and / or combinations of features described in the various embodiments and / or claims of this disclosure may be made, even if such combinations or combinations are not explicitly described in this disclosure. In particular, various combinations and / or combinations of features described in the various embodiments and / or claims of this disclosure may be made, without departing from the spirit and teachings of this disclosure. All such combinations and / or combinations fall within the scope of this disclosure.

[0392] The embodiments of the present disclosure are described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of the present disclosure. Although each embodiment has been described separately above, this does not mean that the measures in each embodiment cannot be used in combination to advantage. The scope of the present disclosure is defined by the appended claims and their equivalents. Without departing from the scope of the present disclosure, those skilled in the art may make various substitutions and modifications, which should all fall within the scope of the present disclosure.

Claims

1. A shift register, comprising: an input circuit configured to provide a first power supply voltage from a first power supply terminal to a first node and an input signal from an input terminal to a second node under control of a first clock signal from a first clock terminal; a control circuit configured to provide the potential of the second node to the third node under the control of a first enable signal from the first enable terminal, and to provide the potential of the second node to the fourth node under the control of a second enable signal from the second enable terminal; as well as The output circuit is configured to output a signal through an output terminal under the control of the potentials of the first node, the second node, the third node, and the fourth node.

2. The shift register according to claim 1, wherein: The input circuit includes a scan input circuit, the control circuit includes a scan control circuit, the output circuit includes a scan output circuit, the input terminal includes a scan input terminal, the first node includes a first scan node, the second node includes a second scan node, the third node includes a third scan node, the fourth node includes a fourth scan node, and the output terminal includes a first scan output terminal, a second scan output terminal, and a third scan output terminal; The scan input circuit is electrically connected to the scan input terminal, the first power terminal and the first clock terminal, and is configured to provide the first power supply voltage to the first scan node and provide the scan input signal from the scan input terminal to the second scan node under the control of the first clock signal; The scan control circuit is electrically connected to the first enable terminal, the second enable terminal and the second scan node, and is configured to provide the potential of the second scan node to the third scan node under the control of the first enable signal, and to provide the potential of the second scan node to the fourth scan node under the control of the second enable signal; and The scan output circuit is electrically connected to the second clock terminal, the first power supply terminal, the second power supply terminal, the first scan node, the second scan node, the third scan node and the fourth scan node, and is configured to provide the second power supply voltage of the second power supply terminal or the second clock signal from the second clock terminal to the first scan output terminal under the control of the potential of the first scan node and the potential of the third scan node, provide the second power supply voltage or the second clock signal to the second scan output terminal under the control of the potential of the first scan node and the potential of the fourth scan node, and provide the second power supply voltage or the second clock signal to the third scan output terminal under the control of the potential of the first scan node, the potential of the second scan node and the first power supply voltage.

3. The shift register according to claim 2, wherein: The scanning control circuit comprises: a first scan control subcircuit, electrically connected to the first enable terminal, the second scan node and the third scan node, and configured to provide a potential of the second scan node to the third scan node under the control of the first enable signal; and The second scan control subcircuit is electrically connected to the second enable terminal, the second scan node and the fourth scan node, and is configured to provide the potential of the second scan node to the fourth scan node under the control of the second enable signal.

4. The shift register according to claim 2, wherein: The scan output circuit comprises: A first scan output sub-circuit, electrically connected to the second clock terminal, the second power terminal, the first scan node and the third scan node, and configured to provide the second power supply voltage or the second clock signal to the first scan output terminal under the control of the potential of the first scan node and the potential of the third scan node; a second scan output sub-circuit, electrically connected to the second clock terminal, the second power terminal, the first scan node, and the fourth scan node, and configured to provide the second power supply voltage or the second clock signal to the second scan output terminal under the control of the potential of the first scan node and the potential of the fourth scan node; and The third scan output sub-circuit is electrically connected to the second clock terminal, the first power terminal, the second power terminal, the first scan node and the second scan node, and is configured to provide the second power supply voltage or the second clock signal to the third scan output terminal under the control of the potential of the first scan node, the potential of the second scan node and the first power supply voltage.

5. The shift register according to claim 2, wherein: The scan input circuit is also electrically connected to the second clock terminal and the second power supply terminal, and is configured to provide the second power supply voltage to the second scan node under the control of the potential of the first scan node and the second clock signal, and to provide the first clock signal to the first scan node under the control of the potential of the second scan node.

6. The shift register according to claim 5, wherein: The scan input circuit comprises: a first scanning transistor, a second scanning transistor, a third scanning transistor, a fourth scanning transistor, and a fifth scanning transistor; wherein the control electrode of the first scanning transistor is electrically connected to the first clock terminal, the first electrode of the first scanning transistor is electrically connected to the scanning input terminal, and the second electrode of the first scanning transistor is electrically connected to the second scanning node; The control electrode of the second scanning transistor is electrically connected to the first clock terminal, the first electrode of the second scanning transistor is electrically connected to the first power supply terminal, and the second electrode of the second scanning transistor is electrically connected to the first scanning node; The control electrode of the third scanning transistor is electrically connected to the second scanning node, the first electrode of the third scanning transistor is electrically connected to the first clock terminal, and the second electrode of the third scanning transistor is electrically connected to the first scanning node; The control electrode of the fourth scanning transistor is electrically connected to the first scanning node, the first electrode of the fourth scanning transistor is electrically connected to the second power supply terminal, and the second electrode of the fourth scanning transistor is electrically connected to the first electrode of the fifth scanning transistor; and A control electrode of the fifth scan transistor is electrically connected to the second clock terminal, and a second electrode of the fifth scan transistor is electrically connected to the second scan node.

7. The shift register according to claim 3, wherein: The first scan control subcircuit includes a sixth scan transistor and a seventh scan transistor; wherein the control electrode of the sixth scanning transistor is electrically connected to the first enabling terminal, the first electrode of the sixth scanning transistor is electrically connected to the second scanning node, and the second electrode of the sixth scanning transistor is electrically connected to the third scanning node; and The control electrode and the first electrode of the seventh scan transistor are both electrically connected to the third scan node, and the second electrode of the seventh scan transistor is electrically connected to the first enable terminal.

8. The shift register according to claim 2, wherein: The second scan control subcircuit includes an eighth scan transistor and a ninth scan transistor; wherein the control electrode of the eighth scanning transistor is electrically connected to the second enable terminal, the first electrode of the eighth scanning transistor is electrically connected to the second scanning node, and the second electrode of the eighth scanning transistor is electrically connected to the fourth scanning node; and The control electrode and the first electrode of the ninth scan transistor are both electrically connected to the fourth scan node, and the second electrode of the ninth scan transistor is electrically connected to the second enable terminal.

9. The shift register according to claim 4, wherein: The first scan output subcircuit includes a tenth scan transistor, an eleventh scan transistor, a first scan capacitor, and a second scan capacitor; wherein the control electrode of the tenth scanning transistor is electrically connected to the first scanning node, the first electrode of the tenth scanning transistor is electrically connected to the second power supply terminal, and the second electrode of the tenth scanning transistor is electrically connected to the first scanning output terminal; The control electrode of the eleventh scanning transistor is electrically connected to the third scanning node, the first electrode of the eleventh scanning transistor is electrically connected to the second clock terminal, and the second electrode of the eleventh scanning transistor is electrically connected to the first scanning output terminal; A first terminal of the first scan capacitor is electrically connected to the first scan node, and a second terminal of the first scan capacitor is electrically connected to the second power supply terminal; and A first terminal of the second scan capacitor is electrically connected to the third scan node, and a second terminal of the second scan capacitor is electrically connected to the first scan output terminal.

10. The shift register according to claim 4, wherein: The second scan output subcircuit includes a twelfth scan transistor, a thirteenth scan transistor, a third scan capacitor and a fourth scan capacitor; wherein the control electrode of the twelfth scanning transistor is electrically connected to the first scanning node, the first electrode of the twelfth scanning transistor is electrically connected to the second power supply terminal, and the second electrode of the twelfth scanning transistor is electrically connected to the second scanning output terminal; The control electrode of the thirteenth scanning transistor is electrically connected to the fourth scanning node, the first electrode of the thirteenth scanning transistor is electrically connected to the second clock terminal, and the second electrode of the thirteenth scanning transistor is electrically connected to the second scanning output terminal; A first terminal of the third scan capacitor is electrically connected to the first scan node, and a second terminal of the third scan capacitor is electrically connected to the second power supply terminal; and A first terminal of the fourth scan capacitor is electrically connected to the fourth scan node, and a second terminal of the fourth scan capacitor is electrically connected to the second scan output terminal.

11. The shift register according to claim 4, wherein: The third scan output sub-circuit includes a fourteenth scan transistor, a fifteenth scan transistor, a sixteenth scan transistor, a fifth scan capacitor and a sixth scan capacitor; wherein the control electrode of the fourteenth scanning transistor is electrically connected to the first scanning node, the first electrode of the fourteenth scanning transistor is electrically connected to the second power supply terminal, and the second electrode of the fourteenth scanning transistor is electrically connected to the third scanning output terminal; The control electrode of the fifteenth scanning transistor is electrically connected to the first electrode of the sixteenth scanning transistor, the first electrode of the fifteenth scanning transistor is electrically connected to the second clock terminal, and the second electrode of the fifteenth scanning transistor is electrically connected to the third scanning output terminal; The control electrode of the sixteenth scanning transistor is electrically connected to the first power supply terminal, and the second electrode of the sixteenth scanning transistor is electrically connected to the second scanning node; A first terminal of the fifth scan capacitor is electrically connected to the first scan node, and a second terminal of the fifth scan capacitor is electrically connected to the second power supply terminal; and A first terminal of the sixth scan capacitor is electrically connected to the first electrode of the sixteenth scan transistor, and a second terminal of the sixth scan capacitor is electrically connected to the third scan output terminal.

12. The shift register according to claim 1, wherein: The input circuit includes a light-emitting control input circuit, the control circuit includes a light-emitting control circuit, the output circuit includes a light-emitting control output circuit, the input end includes a light-emitting control input end, the first node includes a first light-emitting control node, the second node includes a second light-emitting control node, the third node includes a third light-emitting control node, the fourth node includes a fourth light-emitting control node, and the output end includes a first light-emitting control output end, a second light-emitting control output end, and a third light-emitting control output end; The light emitting control input circuit is electrically connected to the light emitting control input terminal, the first power terminal and the first clock terminal, and is configured to provide the first power supply voltage to the first light emitting control node and provide the light emitting control input signal from the light emitting control input terminal to the second light emitting control node under the control of the first clock signal; the light emitting control circuit being electrically connected to the first enable terminal, the second enable terminal, the first power terminal, the second power terminal, the second clock terminal, the first light emitting control node and the second light emitting control node, and being configured to provide the potential of the second light emitting control node to the third light emitting control node under the control of the first enable signal, provide the potential of the second light emitting control node to the fourth light emitting control node under the control of the second enable signal, and provide the second clock signal or the second power supply voltage to the fifth light emitting control node under the control of the first power supply voltage, the potential of the second light emitting control node, the potential of the first light emitting control node and the second clock signal; and The light-emitting control output circuit is electrically connected to the first power supply terminal, the second power supply terminal, the second light-emitting control node, the third light-emitting control node, the fourth light-emitting control node and the fifth light-emitting control node, and is configured to provide the first power supply voltage or the second power supply voltage to the first light-emitting control output terminal under the control of the potential of the third light-emitting control node and the potential of the fifth light-emitting control node, provide the first power supply voltage or the second power supply voltage to the second light-emitting control output terminal under the control of the potential of the fourth light-emitting control node and the potential of the fifth light-emitting control node, and provide the first power supply voltage or the second power supply voltage to the third light-emitting control output terminal under the control of the potential of the second light-emitting control node, the potential of the fifth light-emitting control node and the first power supply voltage.

13. The shift register according to claim 12, wherein: The light emitting control circuit comprises: a first light-emitting control subcircuit, electrically connected to the first enable terminal, the second clock terminal, the second light-emitting control node and the third light-emitting control node, and configured to provide a potential of the second light-emitting control node to the third light-emitting control node under the control of the first enable signal and the second clock signal; a second light-emitting control subcircuit, electrically connected to the second enable terminal, the second clock terminal, the second light-emitting control node, and the fourth light-emitting control node, and configured to provide a potential of the second light-emitting control node to the fourth light-emitting control node under the control of the second enable signal and the second clock signal; and The third light-emitting control subcircuit is electrically connected to the first power supply terminal, the second power supply terminal, the second clock terminal, the first light-emitting control node, the second light-emitting control node and the fifth light-emitting control node, and is configured to provide the second clock signal or the second power supply voltage to the fifth light-emitting control node under the control of the first power supply voltage, the potential of the second light-emitting control node, the potential of the first light-emitting control node and the second clock signal.

14. The shift register according to claim 12, wherein: The light emitting control output circuit comprises: a first light emission control output subcircuit, electrically connected to the first power supply terminal, the second power supply terminal, the third light emission control node and the fifth light emission control node, and configured to provide the first power supply voltage or the second power supply voltage to the first light emission control output terminal under the control of the potential of the third light emission control node and the potential of the fifth light emission control node; a second light emission control output subcircuit, electrically connected to the first power supply terminal, the second power supply terminal, the fourth light emission control node, and the fifth light emission control node, and configured to provide the first power supply voltage or the second power supply voltage to the second light emission control output terminal under the control of the potential of the fourth light emission control node and the potential of the fifth light emission control node; and The third light-emitting control output subcircuit is electrically connected to the first power supply terminal, the second power supply terminal, the second light-emitting control node and the fifth light-emitting control node, and is configured to provide the first power supply voltage or the second power supply voltage to the third light-emitting control output terminal under the control of the potential of the second light-emitting control node, the potential of the fifth light-emitting control node and the first power supply voltage.

15. The shift register according to claim 12, wherein: The light-emitting control input circuit is also electrically connected to the second clock terminal and the second power supply terminal, and is configured to provide the second power supply voltage to the second light-emitting control node under the control of the potential of the first light-emitting control node and the second clock signal, and to provide the first clock signal to the first light-emitting control node under the control of the potential of the second light-emitting control node.

16. The shift register according to claim 15, wherein: The light emitting control input circuit comprises: a first light emission control transistor, a second light emission control transistor, a third light emission control transistor, a fourth light emission control transistor, and a fifth light emission control transistor; Wherein, the control electrode of the first light-emitting control transistor is electrically connected to the first clock terminal, the first electrode of the first light-emitting control transistor is electrically connected to the light-emitting control input terminal, and the second electrode of the first light-emitting control transistor is electrically connected to the second light-emitting control node; The control electrode of the second light emission control transistor is electrically connected to the first clock terminal, the first electrode of the second light emission control transistor is electrically connected to the first power supply terminal, and the second electrode of the second light emission control transistor is electrically connected to the first light emission control node; The control electrode of the third light emitting control transistor is electrically connected to the second light emitting control node, the first electrode of the third light emitting control transistor is electrically connected to the first clock terminal, and the second electrode of the third light emitting control transistor is electrically connected to the first light emitting control node; a control electrode of the fourth light emission control transistor is electrically connected to the first light emission control node, a first electrode of the fourth light emission control transistor is electrically connected to the second power supply terminal, and a second electrode of the fourth light emission control transistor is electrically connected to the first electrode of the fifth light emission control transistor; and A control electrode of the fifth light emission control transistor is electrically connected to the second clock terminal, and a second electrode of the fifth light emission control transistor is electrically connected to the second light emission control node.

17. The shift register according to claim 13, wherein: The first light emission control subcircuit includes a sixth light emission control transistor, a seventh light emission control transistor and a first light emission control capacitor; Wherein, the control electrode of the sixth light-emitting control transistor is electrically connected to the first enable terminal, the first electrode of the sixth light-emitting control transistor is electrically connected to the second light-emitting control node, and the second electrode of the sixth light-emitting control transistor is electrically connected to the third light-emitting control node; The control electrode and the first electrode of the seventh light emitting control transistor are both electrically connected to the third light emitting control node, and the second electrode of the seventh light emitting control transistor is electrically connected to the first enable terminal; and A first terminal of the first light emission control capacitor is electrically connected to the third light emission control node, and a second terminal of the first light emission control capacitor is electrically connected to the second clock terminal.

18. The shift register according to claim 13, wherein: The second light emission control subcircuit includes an eighth light emission control transistor, a ninth light emission control transistor and a second light emission control capacitor; The control electrode of the eighth light-emitting control transistor is electrically connected to the second enable terminal, the first electrode of the eighth light-emitting control transistor is electrically connected to the second light-emitting control node, and the second electrode of the eighth light-emitting control transistor is electrically connected to the fourth light-emitting control node; The control electrode and the first electrode of the ninth light emitting control transistor are both electrically connected to the fourth light emitting control node, and the second electrode of the ninth light emitting control transistor is electrically connected to the second enable terminal; and A first terminal of the second light emission control capacitor is electrically connected to the fourth light emission control node, and a second terminal of the second light emission control capacitor is electrically connected to the second clock terminal.

19. The shift register according to claim 13, wherein: The third light emitting control subcircuit includes a tenth light emitting control transistor, an eleventh light emitting control transistor, a twelfth light emitting control transistor, a thirteenth light emitting control transistor and a third light emitting control capacitor; Wherein, the control electrode of the tenth light emitting control transistor is electrically connected to the first power supply terminal, the first electrode of the tenth light emitting control transistor is electrically connected to the first light emitting control node, and the second electrode of the tenth light emitting control transistor is electrically connected to the control electrode of the eleventh light emitting control transistor; The first electrode of the eleventh light emitting control transistor is electrically connected to the second clock terminal, and the second electrode of the eleventh light emitting control transistor is electrically connected to the first electrode of the twelfth light emitting control transistor; The control electrode of the twelfth light emitting control transistor is electrically connected to the second clock terminal, and the second electrode of the twelfth light emitting control transistor is electrically connected to the fifth light emitting control node; a control electrode of the thirteenth light emitting control transistor electrically connected to the second light emitting control node, a first electrode of the thirteenth light emitting control transistor electrically connected to the second power supply terminal, and a second electrode of the thirteenth light emitting control transistor electrically connected to the fifth light emitting control node; and A first end of the third light emission control capacitor is electrically connected to a control electrode of the eleventh light emission control transistor, and a second end of the third light emission control capacitor is electrically connected to a second electrode of the eleventh light emission control transistor.

20. The shift register according to claim 14, wherein: The first light emission control output subcircuit includes a fourteenth light emission control transistor, a fifteenth light emission control transistor and a fourth light emission control capacitor; Wherein, the control electrode of the fourteenth light-emitting control transistor is electrically connected to the fifth light-emitting control node, the first electrode of the fourteenth light-emitting control transistor is electrically connected to the second power supply terminal, and the second electrode of the fourteenth light-emitting control transistor is electrically connected to the first light-emitting control output terminal; The control electrode of the fifteenth light emitting control transistor is electrically connected to the third light emitting control node, the first electrode of the fifteenth light emitting control transistor is electrically connected to the first power supply terminal, and the second electrode of the fifteenth light emitting control transistor is electrically connected to the first light emitting control output terminal; and A first terminal of the fourth light emission control capacitor is electrically connected to the fifth light emission control node, and a second terminal of the fourth light emission control capacitor is electrically connected to the second power supply terminal.

21. The shift register according to claim 14, wherein: The second light emission control output subcircuit includes a sixteenth light emission control transistor, a seventeenth light emission control transistor and a fifth light emission control capacitor; The control electrode of the sixteenth light-emitting control transistor is electrically connected to the fifth light-emitting control node, the first electrode of the sixteenth light-emitting control transistor is electrically connected to the second power supply terminal, and the second electrode of the sixteenth light-emitting control transistor is electrically connected to the second light-emitting control output terminal; The control electrode of the seventeenth light emitting control transistor is electrically connected to the fourth light emitting control node, the first electrode of the seventeenth light emitting control transistor is electrically connected to the first power supply terminal, and the second electrode of the seventeenth light emitting control transistor is electrically connected to the second light emitting control output terminal; and A first terminal of the fifth light emitting control capacitor is electrically connected to the fifth light emitting control node, and a second terminal of the fifth light emitting control capacitor is electrically connected to the second power supply terminal.

22. The shift register according to claim 14, wherein: The third light emission control output sub-circuit includes an eighteenth light emission control transistor, a nineteenth light emission control transistor, a twentieth light emission control transistor and a sixth light emission control capacitor; The control electrode of the eighteenth light-emitting control transistor is electrically connected to the fifth light-emitting control node, the first electrode of the eighteenth light-emitting control transistor is electrically connected to the second power supply terminal, and the second electrode of the eighteenth light-emitting control transistor is electrically connected to the third light-emitting control output terminal; The control electrode of the nineteenth light emitting control transistor is electrically connected to the first electrode of the twentieth light emitting control transistor, the first electrode of the nineteenth light emitting control transistor is electrically connected to the first power supply terminal, and the second electrode of the nineteenth light emitting control transistor is electrically connected to the third light emitting control output terminal; A control electrode of the twentieth light emitting control transistor is electrically connected to the first power supply terminal, and a second electrode of the twentieth light emitting control transistor is electrically connected to the second light emitting control node; and A first terminal of the sixth light emitting control capacitor is electrically connected to the control electrode of the nineteenth light emitting control transistor, and a second terminal of the sixth light emitting control capacitor is electrically connected to the second clock terminal.

23. A driving circuit, comprising M cascaded shift registers according to any one of claims 1 to 22, wherein M is a positive integer greater than 1; The input end of the m-th shift register is electrically connected to the output end of the m-1-th shift register, 1<m≤M.

24. A display device comprising: Display panel; as well as The driving circuit as claimed in claim 23; Wherein, the display panel includes a plurality of pixel units, each of the pixel units includes a first sub-pixel group and a second sub-pixel group, the first sub-pixel group is electrically connected to the first scanning output terminal and the first light-emitting control output terminal in the driving circuit, and the second sub-pixel group is electrically connected to the second scanning output terminal and the second light-emitting control output terminal in the driving circuit, wherein the light emitting angles of the plurality of first sub-pixels included in the first sub-pixel group are smaller than the light emitting angles of the plurality of second sub-pixels included in the second sub-pixel group, and the light emitting angle is the angle between the emitted light and a direction perpendicular to the display panel.

25. A driving method, applied to the shift register according to any one of claims 1 to 22, comprising: The first enable signal from the first enable terminal is at a first level and the second enable signal from the second enable terminal is at a second level, controlling the first output terminal among the input terminals to output a pulse signal and the second output terminal among the input terminals to output a direct current signal; The first enable signal is at the second level and the second enable signal is at the first level, controlling the first output terminal to output a direct current signal and the second output terminal to output a pulse signal; as well as The first enable signal and the second enable signal are both at a first level, controlling the first output terminal and the second output terminal to output pulse signals.

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