Decoding method and apparatus, and device and medium

Abstract

Disclosed in the present application are a decoding method and apparatus, and a device and a medium. The method comprises: allocating one storage area to each coded block in M transport blocks corresponding to M HARQ processes; determining as a first HARQ process an HARQ process indicated by downlink control information; respectively performing decoding processing on N coded blocks in a transport block corresponding to the first HARQ process; when a coded block fails to be decoded, storing, in a storage area corresponding to the coded block in a physical layer, a soft bit corresponding to the coded block; when a coded block is correctly decoded, storing, in a storage area corresponding to the coded block in the physical layer, a hard bit corresponding to the coded block; and after the N coded blocks are all correctly decoded, submitting to a MAC layer N hard bits corresponding to the N coded blocks in the physical layer. On the basis of the embodiments of the present application, communication resources occupied when the physical layer submits hard bits of an HARQ process to a higher layer of a data plane can be effectively reduced, thereby reducing the resource consumption. Fig. 1

Description

Decoding method, device, equipment and medium

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application is based on the Chinese patent application with application number 202311755811.8 and application date of December 19, 2023, and claims the priority of the Chinese patent application. The entire content of the Chinese patent application is hereby introduced into this application as a reference. Technical Field

[0003] The present application relates to the field of communication technology, and in particular to a decoding method, apparatus, device, and medium. Background Art

[0004] Hybrid Automatic Repeat reQuest (HARQ) is a technology that combines Forward Error Correction (FEC) and Automatic Repeat Query (ARQ). The keywords of HARQ are storage, retransmission request, and combined demodulation.

[0005] In related technologies, the coding blocks corresponding to transport blocks in an HARQ process are stored in two ways: one storing the soft bits of the coding block and the other storing the hard bits of the coding block. When a coding block decoding error occurs in an HARQ process, the soft bits of the current coding block are stored and combined for decoding during the next retransmission. When the coding block is decoded correctly, the physical layer delivers the hard bits of the coding block to the higher layers of the data plane. However, delivering the hard bits of the HARQ process to the higher layers of the data plane consumes a lot of communication resources. Summary of the Invention

[0006] The purpose of the embodiments of the present application is to provide a decoding method and apparatus thereof, which can effectively reduce the communication resources occupied when the physical layer delivers the hard bits of the HARQ process to the higher layers of the data plane, thereby reducing resource consumption.

[0007] In a first aspect, an embodiment of the present application provides a decoding method, the method comprising: when M hybrid automatic repeat request HARQ processes are obtained, allocating a storage area for each coding block in M ​​transmission blocks corresponding to the M HARQ processes, wherein M is a positive integer; when downlink control information is obtained, determining that the HARQ process indicated by the downlink control information is the first HARQ process; performing decoding processing on the N coding blocks in the transmission block corresponding to the first HARQ process respectively, wherein N is a positive integer; when a coding block decoding error occurs, storing the soft bits corresponding to the coding block in the storage area corresponding to the coding block in the physical layer; when the coding block decoding is correct, storing the hard bits corresponding to the coding block in the storage area corresponding to the coding block in the physical layer; after the N coding blocks are all decoded correctly, submitting the N hard bits corresponding to the N coding blocks in the physical layer to the media access control MAC layer in the data plane.

[0008] In some implementations of the first aspect, hard bits corresponding to N coding blocks in a physical layer are delivered to a media access control (MAC) layer in a data plane, including: when the N coding blocks are decoded correctly, writing a first message in a target cache so that the MAC layer reads N storage areas of the N coding blocks based on the first message to obtain N hard bits, wherein the first message is used to indicate that the N coding blocks are decoded correctly.

[0009] In some implementation methods of the first aspect, after determining that the HARQ process indicated by the downlink control information is the first HARQ process, the method also includes: obtaining the first storage area starting address, first storage space capacity information, and index information of N coding blocks corresponding to the first HARQ process; based on the first storage area starting address, the first storage space capacity information and the index information of each coding block, determining the second storage area starting address of each coding block; wherein the first storage area starting address is the storage area starting address of the transmission block corresponding to the first HARQ process, the first storage space capacity information is used to characterize the storage capacity of the storage area of ​​the coding block in the transmission block corresponding to the first HARQ process, and the second storage area starting address is used to indicate that soft bits or hard bits are stored in the corresponding storage area.

[0010] In some implementation methods of the first aspect, the downlink control information includes a HARQ process identifier, and obtaining the first storage area starting address and first storage space capacity information corresponding to the first HARQ process includes: based on the HARQ process identifier, obtaining the storage starting address and storage space capacity information associated with the first HARQ process from the target cache, and obtaining the first storage area starting address and the first storage space capacity information; wherein, the target cache records M storage area starting addresses and M storage space capacity information associated with M HARQ processes.

[0011] In some implementations of the first aspect, a storage area is allocated to each coding block in M ​​transport blocks corresponding to M HARQ processes, including: for each transport block, obtaining the number of bits corresponding to the soft bits of each coding block in the transport block; based on the number of bits corresponding to the soft bits, determining the storage capacity of the storage area of ​​the coding block; and allocating a storage area to each coding block in the transport block based on the storage capacity.

[0012] In some implementations of the first aspect, after delivering N hard bits corresponding to N coding blocks in the physical layer to the media access control (MAC) layer in the data plane, the method further includes: delivering the N hard bits corresponding to the N coding blocks from the MAC layer to the packet data convergence protocol (PDCP) layer in the data plane; performing unified decryption processing on the N hard bits through the PDCP layer to obtain PDCP decrypted data; and storing the PDCP decrypted data in a double data rate memory (DDR).

[0013] In some implementations of the first aspect, after storing the soft bits corresponding to the coding block in the storage area corresponding to the coding block in the physical layer, the method also includes: re-decoding the soft bits corresponding to the coding block; and when the re-decoding is correct, replacing the soft bits stored in the storage area corresponding to the coding block with hard bits.

[0014] In a second aspect, an embodiment of the present application provides a decoding device, which includes: an allocation module for allocating a storage area for each coding block in M ​​transmission blocks corresponding to the M HARQ processes when M hybrid automatic repeat request HARQ processes are obtained, wherein M is a positive integer; a determination module for determining that the HARQ process indicated by the downlink control information is the first HARQ process when downlink control information is obtained; a decoding module for respectively decoding the N coding blocks in the transmission block corresponding to the first HARQ process, wherein N is a positive integer; a storage module for storing the soft bits corresponding to the coding blocks in the storage area corresponding to the coding blocks in the physical layer when a coding block decoding error occurs; the storage module is also used to store the hard bits corresponding to the coding blocks in the storage area corresponding to the coding blocks in the physical layer when the coding block decoding is correct; a submission module for submitting the N hard bits corresponding to the N coding blocks in the physical layer to the media access control MAC layer in the data plane after the N coding blocks are decoded correctly.

[0015] In some implementations of the second aspect, the delivery module includes: a writing unit, configured to write a first message in a target cache when all N coding blocks are decoded correctly, so that the MAC layer reads N storage areas of the N coding blocks based on the first message to obtain N hard bits, wherein the first message is used to indicate that the N coding blocks are decoded correctly.

[0016] In some implementation methods of the second aspect, the device also includes: an acquisition module, which is used to obtain the first storage area starting address, first storage space capacity information, and index information of N coding blocks corresponding to the first HARQ process after determining that the HARQ process indicated by the downlink control information is the first HARQ process; the determination module is also used to determine the second storage area starting address of each coding block based on the first storage area starting address, the first storage space capacity information and the index information of each coding block; wherein the first storage area starting address is the storage area starting address of the transmission block corresponding to the first HARQ process, the first storage space capacity information is used to characterize the storage capacity of the storage area of ​​the coding block in the transmission block corresponding to the first HARQ process, and the second storage area starting address is used to indicate that soft bits or hard bits are stored in the corresponding storage area.

[0017] In some implementation methods of the second aspect, the downlink control information includes a HARQ process identifier, and the acquisition module is specifically used to: based on the HARQ process identifier, obtain the storage start address and storage space capacity information associated with the first HARQ process from the target cache, and obtain the first storage area start address and the first storage space capacity information; wherein, the target cache records M storage area start addresses and M storage space capacity information associated with M HARQ processes.

[0018] In some implementations of the second aspect, the allocation module includes: an acquisition unit for obtaining, for each transmission block, the number of bits corresponding to the soft bits of each coding block in the transmission block; a determination unit for determining the storage capacity of the storage area of ​​the coding block based on the number of bits corresponding to the soft bits; and an allocation unit for allocating a storage area to each coding block in the transmission block based on the storage capacity.

[0019] In some implementations of the second aspect, the device also includes: a delivery module, which is further used to deliver the N hard bits corresponding to the N coding blocks in the physical layer to the media access control MAC layer in the data plane, and then deliver the N hard bits corresponding to the N coding blocks from the MAC layer to the packet data convergence protocol PDCP layer in the data plane; a decryption module, which is used to uniformly decrypt the N hard bits through the PDCP layer to obtain PDCP decrypted data; and a storage module, which is further used to store the PDCP decrypted data in a double data rate memory DDR.

[0020] In some implementations of the second aspect, the device also includes: a decoding module, which is used to re-decode the soft bits corresponding to the coding block after storing the soft bits corresponding to the coding block in the storage area corresponding to the coding block in the physical layer; and a replacement module, which is used to replace the soft bits stored in the storage area corresponding to the coding block with hard bits when the re-decoding is correct.

[0021] In a third aspect, an embodiment of the present application provides an electronic device, comprising: a processor and a memory storing computer program instructions; when the processor executes the computer program instructions, the steps of the decoding method of the first aspect are implemented.

[0022] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium having computer program instructions stored thereon. When the computer program instructions are executed by a processor, the steps of the decoding method of the first aspect are implemented.

[0023] In a fifth aspect, an embodiment of the present application provides a computer program product, which is stored in a non-volatile storage medium and is executed by at least one processor to implement the steps of the decoding method of the first aspect.

[0024] In a sixth aspect, an embodiment of the present application provides a chip, which includes a processor and a communication interface, the communication interface and the processor are coupled, and the processor is used to run programs or instructions to implement the steps of the decoding method of the first aspect.

[0025] The present application provides a decoding method, apparatus, device, and medium. When M hybrid automatic repeat request (HARQ) processes are obtained, a storage area is allocated to each coding block in M ​​transport blocks corresponding to the M HARQ processes. When downlink control information is obtained, the HARQ process indicated by the downlink control information is determined to be a first HARQ process. N coding blocks in the transport block corresponding to the first HARQ process are decoded separately. When a coding block is decoded incorrectly, soft bits corresponding to the coding block are stored in a storage area corresponding to the coding block in a physical layer. When the coding block is decoded correctly, hard bits corresponding to the coding block are stored in a storage area corresponding to the coding block in the physical layer. After all N coding blocks are decoded correctly, N hard bits corresponding to the N coding blocks in the physical layer are delivered to a media access control (MAC) layer in a data plane. Compared with the related art, in which the physical layer needs to submit the corresponding hard bits of the coding block to the MAC layer after each coding block is correctly decoded, the present application is that the physical layer will submit the hard bits of all coding blocks to the MAC layer together only after all coding blocks in the entire transmission block are correctly decoded. This can significantly reduce the number of information exchanges between the physical layer and the MAC layer, thereby reducing communication resource consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the technical solutions of the embodiments of the present application, a brief introduction to the drawings required for use in the embodiments of the present application is given below.

[0027] FIG1 is a schematic diagram of a decoding method according to an embodiment of the present application;

[0028] FIG2 is a schematic diagram of an example of a decoding process provided by an embodiment of the present application;

[0029] FIG3 is a schematic flow chart of a decoding method provided in another embodiment of the present application;

[0030] FIG4 is a flowchart of a decoding method provided in yet another embodiment of the present application;

[0031] FIG5 is a schematic structural diagram of a decoding device provided in an embodiment of the present application;

[0032] FIG6 is a schematic structural diagram of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0033] The features and exemplary embodiments of various aspects of the present application will be described in detail below. In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain the present application, rather than to limit the present application. For those skilled in the art, the present application can be implemented without the need for some of these specific details. The following description of the embodiments is merely to provide a better understanding of the present application by illustrating the examples of the present application.

[0034] In related technologies, when a coding block is decoded correctly, the physical layer immediately delivers the hard bits of the coding block to the MAC layer in the data plane, regardless of whether the coding block before it is correct. Therefore, for the N coding blocks of the HARQ process, the physical layer needs to interact with the MAC layer once each time the decoding of the coding block is completed. Therefore, the physical layer needs to interact with the MAC layer N times, resulting in a large number of information exchanges, occupying too many communication resources and causing waste of communication resources.

[0035] Furthermore, soft bits and hard bits are currently statically stored in separate memory areas. This means that two memory areas must be reserved for each coding block, one for hard bits and one for soft bits. However, for the same coding block, storing soft bits does not require storing hard bits, and storing hard bits does not require storing soft bits. Therefore, reserving two memory areas for each coding block significantly wastes memory space.

[0036] The decoding method provided in the embodiment of the present application is described in detail below through specific embodiments and their application scenarios in conjunction with the accompanying drawings.

[0037] FIG1 is a flow chart of a decoding method provided in an embodiment of the present application. The decoding method may be executed by a terminal. As an example, the terminal may be a Redcap terminal.

[0038] The decoding method of the present application is described below using a terminal as an example of an execution subject of the decoding method. It should be noted that the above execution subjects and application scenarios do not constitute a limitation of the present application.

[0039] As shown in FIG1 , the decoding method provided in the embodiment of the present application may include steps 110 to 160 .

[0040] Step 110: When M hybrid automatic repeat request (HARQ) processes are obtained, a storage area is allocated for each coding block in the M transport blocks corresponding to the M HARQ processes;

[0041] Step 120: When the downlink control information is obtained, determine that the HARQ process indicated by the downlink control information is the first HARQ process;

[0042] Step 130: Decode each of the N coding blocks in the transport block corresponding to the first HARQ process.

[0043] Step 140: In the event of a decoding error in a coding block, the soft bits corresponding to the coding block are stored in a storage area corresponding to the coding block in the physical layer;

[0044] Step 150: If the coded block is decoded correctly, the hard bits corresponding to the coded block are stored in a storage area corresponding to the coded block in the physical layer;

[0045] Step 160: After all N coding blocks are decoded correctly, N hard bits corresponding to the N coding blocks in the physical layer are delivered to the media access control (MAC) layer in the data plane.

[0046] The decoding method provided in the embodiment of the present application allocates a storage area for each coding block in the M transmission blocks corresponding to the M HARQ processes when M hybrid automatic repeat request HARQ processes are obtained; determines that the HARQ process indicated by the downlink control information is the first HARQ process when downlink control information is obtained; decodes the N coding blocks in the transmission block corresponding to the first HARQ process respectively; in the case of a decoding error of the coding block, stores the soft bits corresponding to the coding block in the storage area corresponding to the coding block in the physical layer; in the case of correct decoding of the coding block, stores the hard bits corresponding to the coding block in the storage area corresponding to the coding block in the physical layer; after all N coding blocks are decoded correctly, delivers the N hard bits corresponding to the N coding blocks in the physical layer to the media access control MAC layer in the data plane. Compared with the related art, in which the physical layer needs to submit the corresponding hard bits of the coding block to the MAC layer after each coding block is correctly decoded, the present application is that the physical layer will submit the hard bits of all coding blocks to the MAC layer together only after all coding blocks in the entire transmission block are correctly decoded. This can significantly reduce the number of information exchanges between the physical layer and the MAC layer, thereby reducing communication resource consumption.

[0047] The specific implementation of the above steps will be described in detail below with reference to specific embodiments.

[0048] In step 110, when M hybrid automatic repeat request HARQ processes are obtained, a storage area is allocated for each coding block in the M transport blocks corresponding to the M HARQ processes.

[0049] In step 110, M is a positive integer, each transport block corresponds to at least one coding block, and each coding block has a corresponding storage area. When the coding block is decoded correctly, the storage area is used to store the hard bits of the coding block; when the coding block is decoded incorrectly, the storage area is used to store the soft bits of the coding block.

[0050] For example, as shown in FIG2 , the related art solution sets up a storage area for soft bits and hard bits in the HARQ storage area. In the soft bit storage area, for each HARQ process from HARQ process 0 to HARQ process m, each corresponding n coding block has corresponding soft bit storage space; in the hard bit storage area, for each HARQ process from HARQ process 0 to HARQ process m, each corresponding n coding block has corresponding hard bit storage space. In contrast, in the present application, as shown in FIG3 , there is only one storage area in the HARQ storage area, which can be used to store both soft bits and hard bits. For each HARQ process from HARQ process 0 to HARQ process m, each corresponding n coding block has unique corresponding storage space.

[0051] In an embodiment of the present application, the present application can store soft bits and hard bits in the same storage area, and the soft bits and hard bits reuse the same storage space. When the coding block is decoded incorrectly, the storage area stores soft bits. When the coding block is decoded correctly but the time has not yet come to submit it to the MAC layer, the storage area stores hard bits. This can realize the multiplexing of storage space for soft bits and hard bits. Compared with the solution of allocating two storage spaces for each coding block, the present application can effectively reduce the storage space of soft bits and hard bits.

[0052] In some embodiments of the present application, allocating a storage area for each coding block in the M transport blocks corresponding to the M HARQ processes in step 110 may specifically include the following steps:

[0053] For each transport block, obtain the number of bits corresponding to the soft bits of each coding block in the transport block;

[0054] Determining a storage capacity of a storage area of ​​the coding block based on the number of bits corresponding to the soft bits;

[0055] A storage area is allocated for each coding block in the transport block based on the storage capacity.

[0056] In an embodiment of the present application, since the number of soft bits in each coding block is definitely greater than the number of hard bits, the storage capacity of the storage area of ​​the coding block is determined based on the number of bits corresponding to the soft bits. That is, the size of the storage space is reserved according to the number of soft bits in each coding block. The space reserved according to the number of soft bits can store both soft bits and hard bits, thereby ensuring that the storage capacity of the storage area can meet the storage requirements of soft bits and hard bits.

[0057] In step 120, when downlink control information is acquired, it is determined that the HARQ process indicated by the downlink control information is the first HARQ process.

[0058] In step 120, after receiving the downlink control information, the terminal can use the HARQ process identifier carried in the downlink control information to determine the first HARQ process among the M HARQ processes, and perform soft bit merging on the coding block in the transmission block corresponding to the first HARQ process to decode the merged soft bits.

[0059] The Physical Downlink Control Channel (PDCCH) carries Downlink Control Information (DCI). DCI carries various information sent by the base station to schedule terminals, such as the HARQ process identifier, resource blocks occupied in the frequency domain, monitoring location in the time domain, and modulation scheme selection. The HARQ process identifier indicates the HARQ process being processed in the current time slot.

[0060] In some embodiments of the present application, Figure 4 is a flow chart of a decoding method provided by another embodiment of the present application. After the above-mentioned step 140 determines that the HARQ process indicated by the downlink control information is the first HARQ process, the method may further include steps 410 and 420 as shown in Figure 4.

[0061] Step 410: Obtain a first storage area start address, first storage space capacity information, and index information of N coding blocks corresponding to a first HARQ process;

[0062] Step 420: Determine a starting address of a second storage area of ​​each coding block based on the starting address of the first storage area, the first storage space capacity information, and the index information of each coding block.

[0063] Among them, the starting address of the first storage area is the starting address of the storage area of ​​the transmission block corresponding to the first HARQ process, the first storage space capacity information is used to characterize the storage capacity of the storage area of ​​the coding block in the transmission block corresponding to the first HARQ process, and the starting address of the second storage area is used to indicate that the soft bits or hard bits are stored in the corresponding storage area.

[0064] In an embodiment of the present application, when processing the current coding block, the hardware can find the storage area starting address of the current coding block according to the storage area starting address of the current HARQ process, the storage area size of each coding block and the index of the current coding block, and store soft bits or hard bits.

[0065] Exemplarily, the starting address of the coding block storage area=the starting address of the storage area of ​​the HARQ process+the size of each coding block storage area*the coding block index.

[0066] In related technologies, because soft bits and hard bits are stored separately, a large amount of storage control information must be recorded, including the following: the starting address of the storage area for each HARQ process corresponding to the soft bits; the number of soft bits in each coding block; the starting address of the storage area for each HARQ process corresponding to the hard bits; and the number of hard bits in each coding block. This increased control information increases the complexity of software control and hardware implementation. Software configuration requires more registers, and hardware processing becomes correspondingly more complex.

[0067] In some embodiments of the present application, the downlink control information may include a HARQ process identifier, and the above 410 obtaining the first storage area start address and first storage space capacity information corresponding to the first HARQ process may specifically include:

[0068] Based on the HARQ process identifier, the storage start address and storage space capacity information associated with the first HARQ process are acquired from the target cache to obtain the first storage area start address and the first storage space capacity information.

[0069] The target cache may record M storage area start addresses and M storage space capacity information associated with M HARQ processes.

[0070] In an embodiment of the present application, the software in the terminal only needs to record the starting address of the storage space of each HARQ process and the storage space size of each coding block, without distinguishing between hard bits and soft bits. Therefore, it can effectively reduce the amount of control information that needs to be recorded by the physical layer software, further reduce the storage space occupancy, and reduce the complexity of software control and the complexity of hardware implementation.

[0071] In step 130, decoding is performed on the N coding blocks in the transport block corresponding to the first HARQ process respectively.

[0072] In step 130, after soft bits are combined for the coding block, the terminal can decode the combined soft bits using a decoder to obtain a decoding result for the coding block. Decoding the combined soft bits is equivalent to decoding the coding block. After decoding each coding block, the terminal can choose to store soft bits or hard bits in the corresponding storage area based on the decoding result of the coding block. Soft bits can include real signal values, unlike hard bits, which are interpreted as binary values.

[0073] In step 140 , when a coding block is decoded incorrectly, the soft bits corresponding to the coding block are stored in a storage area corresponding to the coding block in the physical layer.

[0074] In step 140, in the case of a decoding error in the coding block, the soft bits corresponding to the coding block are stored, and retransmission merging and decoding are performed during the next retransmission, so as to facilitate subsequent re-decoding of the soft bits, and to continue to determine whether to store soft bits or hard bits based on the decoding results of the re-decoding until the coding block is decoded correctly.

[0075] In some embodiments of the present application, after the soft bits corresponding to the coding block are stored in the storage area corresponding to the coding block in the physical layer in step 140, the method may further include the following steps:

[0076] Re-decode the soft bits corresponding to the coding block;

[0077] When the re-decoding is correct, the soft bits stored in the storage area corresponding to the coding block are replaced with hard bits.

[0078] In step 150 , when the coded block is decoded correctly, hard bits corresponding to the coded block are stored in a storage area corresponding to the coded block in the physical layer.

[0079] It should be noted that the present application does not specifically limit the order of step 140 and step 150. The present application can select step 140 or step 150 for execution based on the decoding result. Moreover, step 140 and step 150 are not executed after the N coding blocks are decoded separately in step 130. Instead, after each coding block is decoded, step 140 or step 150 will be selected for execution based on the decoding result of the coding block.

[0080] In step 160 , after all N coding blocks are decoded correctly, N hard bits corresponding to the N coding blocks in the physical layer are delivered to the Medium Access Control (MAC) layer in the data plane.

[0081] In step 160, N is a positive integer. The LTE wireless access protocol system is divided into three layers: Layer 1 is the physical layer (PHY); Layer 2 is the data plane upper layer, which includes the media access control layer (MAC), the radio link control sublayer (RLC), and the packet data convergence protocol sublayer (PDCP); and Layer 3 is the radio resource control layer (RRC). The physical layer is the lowest layer of the wireless access system, providing services to upper layers using the transport channel as an interface. Therefore, after all N code blocks are correctly decoded, the physical layer can deliver the N hard bits corresponding to the N code blocks to the MAC layer in the data plane.

[0082] In related technologies, hard bit transmission between the physical layer and the MAC layer is through data stream transmission, that is, a direct connection is required between the physical layer and the MAC layer, and the hardware connection and control logic are highly complex.

[0083] In some embodiments of the present application, to reduce hardware wiring complexity, the step 160 of delivering the hard bits corresponding to the N coding blocks in the physical layer to the media access control (MAC) layer in the data plane may include the following steps:

[0084] When all N coding blocks are decoded correctly, a first message is written into the target buffer, so that the MAC layer reads N storage areas of the N coding blocks based on the first message to obtain N hard bits.

[0085] The first message is used to indicate that the N coding blocks are decoded correctly.

[0086] In the embodiment of the present application, the MAC layer can obtain hard bits by accessing the storage area, and there is no need for a direct connection between the physical layer and the MAC, thereby reducing the complexity of hardware control.

[0087] In some embodiments of the present application, after delivering the N hard bits corresponding to the N coding blocks in the physical layer to the media access control (MAC) layer in the data plane in step 160, the method may further include the following steps:

[0088] Submitting N hard bits corresponding to N coding blocks from the MAC layer to the Packet Data Convergence Protocol (PDCP) layer in the data plane;

[0089] Performing unified decryption processing on the N hard bits through the PDCP layer to obtain PDCP decrypted data;

[0090] The PDCP decrypted data is stored in the double data rate memory DDR.

[0091] Specifically, after receiving N hard bits, the MAC layer submits them to the PDCP layer, which enables the PDCP layer to parse the header of the N hard bits, decrypt the payload, and store the decrypted data in the double data rate (DDR) memory.

[0092] It is understandable that the decoding method provided in the embodiment of the present application can be executed by a terminal or a control module in the terminal for executing the decoding method.

[0093] FIG5 is a schematic diagram of the structure of a decoding device provided in an embodiment of the present application. As shown in FIG5 , the decoding device 500 may include: an allocation module 510 , a determination module 520 , a decoding module 530 , a storage module 540 , and a submission module 550 .

[0094] Among them, the allocation module 510 is used to allocate a storage area for each coding block in M ​​transport blocks corresponding to the M HARQ processes when M hybrid automatic repeat request (HARQ) processes are obtained, where M is a positive integer; the determination module 520 is used to determine that the HARQ process indicated by the downlink control information is the first HARQ process when downlink control information is obtained; the decoding module 530 is used to respectively decode the N coding blocks in the transport block corresponding to the first HARQ process, where N is a positive integer; the storage module 540 is used to store the soft bits corresponding to the coding blocks in the storage area corresponding to the coding blocks in the physical layer when a decoding error occurs in the coding blocks; the storage module 540 is also used to store the hard bits corresponding to the coding blocks in the storage area corresponding to the coding blocks in the physical layer when the decoding of the coding blocks is correct; and the submission module 550 is used to submit the N hard bits corresponding to the N coding blocks in the physical layer to the media access control (MAC) layer in the data plane after all N coding blocks are decoded correctly.

[0095] The decoding device provided in the present application allocates a storage area for each coding block in the M transmission blocks corresponding to the M HARQ processes when M hybrid automatic repeat request HARQ processes are obtained; determines that the HARQ process indicated by the downlink control information is the first HARQ process when downlink control information is obtained; decodes the N coding blocks in the transmission block corresponding to the first HARQ process respectively; in the case of a decoding error of the coding block, stores the soft bits corresponding to the coding block in the storage area corresponding to the coding block in the physical layer; in the case of correct decoding of the coding block, stores the hard bits corresponding to the coding block in the storage area corresponding to the coding block in the physical layer; after all N coding blocks are decoded correctly, delivers the N hard bits corresponding to the N coding blocks in the physical layer to the media access control MAC layer in the data plane. Compared with the related art, in which the physical layer needs to submit the corresponding hard bits of the coding block to the MAC layer after each coding block is correctly decoded, the present application is that the physical layer will submit the hard bits of all coding blocks to the MAC layer together only after all coding blocks in the entire transmission block are correctly decoded. This can significantly reduce the number of information exchanges between the physical layer and the MAC layer, thereby reducing communication resource consumption.

[0096] In some embodiments of the present application, the delivery module 550 includes: a writing unit, configured to write a first message in a target cache when all N coding blocks are decoded correctly, so that the MAC layer reads N storage areas of the N coding blocks based on the first message to obtain N hard bits, wherein the first message is used to indicate that the N coding blocks are decoded correctly.

[0097] In some embodiments of the present application, the device also includes: an acquisition module, which is used to obtain the first storage area starting address, first storage space capacity information, and index information of N coding blocks corresponding to the first HARQ process after determining that the HARQ process indicated by the downlink control information is the first HARQ process; the determination module 520 is also used to determine the second storage area starting address of each coding block based on the first storage area starting address, the first storage space capacity information and the index information of each coding block; wherein the first storage area starting address is the storage area starting address of the transmission block corresponding to the first HARQ process, the first storage space capacity information is used to characterize the storage capacity of the storage area of ​​the coding block in the transmission block corresponding to the first HARQ process, and the second storage area starting address is used to indicate that soft bits or hard bits are stored in the corresponding storage area.

[0098] In some embodiments of the present application, the downlink control information includes a HARQ process identifier, and the acquisition module is specifically used to: based on the HARQ process identifier, obtain the storage start address and storage space capacity information associated with the first HARQ process from the target cache, and obtain the first storage area start address and the first storage space capacity information; wherein, the target cache records M storage area start addresses and M storage space capacity information associated with M HARQ processes.

[0099] In some embodiments of the present application, the allocation module 510 includes: an acquisition unit for obtaining, for each transmission block, the number of bits corresponding to the soft bits of each coding block in the transmission block; a determination unit for determining the storage capacity of the storage area of ​​the coding block based on the number of bits corresponding to the soft bits; and an allocation unit for allocating a storage area to each coding block in the transmission block based on the storage capacity.

[0100] In some embodiments of the present application, the delivery module 550 is further configured to, after delivering the N hard bits corresponding to the N coding blocks in the physical layer to the media access control (MAC) layer in the data plane, deliver the N hard bits corresponding to the N coding blocks from the MAC layer to the packet data convergence protocol (PDCP) layer in the data plane. The apparatus further includes a decryption module configured to perform a unified decryption process on the N hard bits at the PDCP layer to obtain PDCP decrypted data. The storage module 540 is further configured to store the PDCP decrypted data in a double data rate memory (DDR).

[0101] In some embodiments of the present application, the decoding module 530 is further configured to re-decode the soft bits corresponding to the coding block after storing the soft bits corresponding to the coding block in the storage area corresponding to the coding block in the physical layer. The apparatus further includes a replacement module configured to replace the soft bits stored in the storage area corresponding to the coding block with hard bits if the re-decoding is correct.

[0102] The decoding device provided in the embodiment of the present application can implement the various processes implemented by the electronic device in the method embodiments of Figures 1 to 4, and can achieve the same technical effects. To avoid repetition, they will not be described here.

[0103] FIG6 is a schematic diagram of the hardware structure of an electronic device provided in an embodiment of the present application.

[0104] As shown in FIG6 , the electronic device 600 includes a memory 601 , a processor 602 , and a computer program stored in the memory 601 and executable on the processor 602 .

[0105] In an example, the processor 602 may include a central processing unit (CPU), or an application specific integrated circuit (ASIC), or may be configured to implement one or more integrated circuits of the embodiments of the present application.

[0106] The memory 601 may include a read-only memory (ROM), a random access memory (RAM), a magnetic disk storage medium device, an optical storage medium device, a flash memory device, an electrical, optical, or other physical / tangible memory storage device. Therefore, typically, the memory includes one or more tangible (non-transitory) computer-readable storage media (e.g., a memory device) encoded with software including computer-executable instructions, and when the software is executed (e.g., by one or more processors), it is operable to perform the operations described with reference to the card activation method in the embodiment according to the first aspect of the present application.

[0107] The processor 602 runs a computer program corresponding to the executable program code by reading the executable program code stored in the memory 601, so as to implement the card activation method in the embodiment of the first aspect.

[0108] In some examples, the electronic device 600 may further include a communication interface 603 and a bus 604. As shown in FIG6, the memory 601, the processor 602, and the communication interface 603 are connected via the bus 604 and communicate with each other.

[0109] The communication interface 603 is mainly used to implement communication between the modules, devices, units and / or equipment in the embodiment of the present application. Input devices and / or output devices can also be connected through the communication interface 603.

[0110] The bus 604 includes hardware, software, or both that couples the components of the electronic device 600 to each other. By way of example, and not limitation, the bus 604 may include an Accelerated Graphics Port (AGP) or other graphics bus, an Enhanced Industry Standard Architecture (EISA) bus, a Front Side Bus (FSB), a HyperTransport (HT) interconnect, an Industry Standard Architecture (ISA) bus, an InfiniBand interconnect, a Low Pin Count (LPC) bus, a memory bus, a Micro Channel Architecture (MCA) bus, a Peripheral Component Interconnect (PCI) bus, a PCI-Express (PCI-E) bus, a Serial Advanced Technology Attachment (SATA) bus, a Video Electronics Standards Association Local Bus (VLB) bus, or other suitable buses, or a combination of two or more of the above. Where appropriate, the bus 604 may include one or more buses. Although embodiments herein describe and illustrate a particular bus, this application contemplates any suitable bus or interconnect.

[0111] The electronic device provided in the embodiment of the present application can implement the various processes implemented by the electronic device in the method embodiments of Figures 1 to 4, and can achieve the same technical effects. To avoid repetition, they will not be described here.

[0112] In conjunction with the decoding method in the above embodiments, the present application embodiment can provide a computer storage medium for implementation. The computer storage medium stores computer program instructions; when the computer program instructions are executed by a processor, the steps of any one of the decoding methods in the above embodiments are implemented.

[0113] In conjunction with the decoding method in the above embodiment, the present application embodiment can provide a computer program product for implementation. The (computer) program product is stored in a non-volatile storage medium, and when the program product is executed by at least one processor, it implements the steps of any one of the decoding methods in the above embodiment.

[0114] An embodiment of the present application further provides a chip, which includes a processor and a communication interface, the communication interface and the processor are coupled, and the processor is used to run programs or instructions to implement the various processes of the above-mentioned decoding method embodiment, and can achieve the same technical effect. To avoid repetition, it will not be repeated here.

[0115] It should be understood that the chip mentioned in the embodiments of the present application can also be called a system-level chip, a system chip, a chip system or a system-on-chip chip, etc.

[0116] It should be understood that the present application is not limited to the specific configurations and processes described above and illustrated in the figures. For the sake of brevity, a detailed description of known methods is omitted here. In the above embodiments, several specific steps are described and illustrated as examples. However, the method process of the present application is not limited to the specific steps described and illustrated. Those skilled in the art can make various changes, modifications, and additions, or change the order of the steps after understanding the spirit of the present application.

[0117] The functional blocks shown in the above-described block diagram can be implemented as hardware, software, firmware or a combination thereof. When implemented in hardware, it can be, for example, an electronic circuit, an application specific integrated circuit (ASIC), appropriate firmware, a plug-in, a function card, etc. When implemented in software, the elements of the present application are programs or code segments that are used to perform the required tasks. The program or code segment can be stored in a machine-readable medium, or transmitted on a transmission medium or a communication link by a data signal carried in a carrier wave. "Machine-readable medium" can include any medium that can store or transmit information. Examples of machine-readable media include electronic circuits, semiconductor memory devices, ROMs, flash memories, erasable ROMs (EROMs), floppy disks, CD-ROMs, optical disks, hard disks, optical fiber media, radio frequency (RF) links, etc. The code segment can be downloaded via a computer network such as the Internet, an intranet, etc.

[0118] It should also be noted that the exemplary embodiments mentioned in this application describe some methods or systems based on a series of steps or devices. However, this application is not limited to the order of the above steps. In other words, the steps can be performed in the order mentioned in the embodiments, or in a different order, or several steps can be performed simultaneously.

[0119] Aspects of the present disclosure have been described above with reference to the flowcharts and / or block diagrams of the methods, devices (systems) and computer program products according to the embodiments of the present disclosure. It should be understood that each box in the flowchart and / or block diagram and the combination of each box in the flowchart and / or block diagram can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer or other programmable data processing device to produce a machine so that these instructions executed by the processor of the computer or other programmable data processing device enable the implementation of the function / action specified in one or more boxes of the flowchart and / or block diagram. Such a processor can be, but is not limited to, a general-purpose processor, a special-purpose processor, a special application processor or a field programmable logic circuit. It is also understood that each box in the block diagram and / or flowchart and the combination of the boxes in the block diagram and / or flowchart can also be implemented by dedicated hardware that performs the specified function or action, or can be implemented by a combination of dedicated hardware and computer instructions.

[0120] The above description is only a specific embodiment of the present application. Those skilled in the art will clearly understand that for the convenience and brevity of description, the specific working processes of the systems, modules and units described above can refer to the corresponding processes in the aforementioned method embodiments, and will not be repeated here. It should be understood that the scope of protection of the present application is not limited thereto. Any person skilled in the art can easily think of various equivalent modifications or replacements within the technical scope disclosed in the present application, and these modifications or replacements should be included in the scope of protection of the present application.

Claims

1. A decoding method, characterized in that: The method comprises: In the case where M hybrid automatic repeat request HARQ processes are obtained, a storage area is allocated for each coding block in the M transport blocks corresponding to the M HARQ processes, where M is a positive integer; In a case where the downlink control information is acquired, determining that the HARQ process indicated by the downlink control information is the first HARQ process; Decoding N coding blocks in the transport block corresponding to the first HARQ process respectively, where N is a positive integer; In case of a decoding error of the coding block, storing the soft bits corresponding to the coding block in a storage area corresponding to the coding block in the physical layer; When the coding block is decoded correctly, storing the hard bits corresponding to the coding block in a storage area corresponding to the coding block in the physical layer; After the N coding blocks are all decoded correctly, the N hard bits corresponding to the N coding blocks in the physical layer are delivered to the media access control MAC layer in the data plane.

2. The method according to claim 1, characterized in that The delivering the hard bits corresponding to the N coding blocks in the physical layer to the media access control MAC layer in the data plane includes: When the N coding blocks are all decoded correctly, a first message is written into the target cache so that the MAC layer reads the N storage areas of the N coding blocks based on the first message to obtain the N hard bits, wherein the first message is used to indicate that the N coding blocks are decoded correctly.

3. The method according to claim 1 or 2, characterized in that: After determining that the HARQ process indicated by the downlink control information is the first HARQ process, the method further includes: Obtaining a starting address of a first storage area corresponding to the first HARQ process, first storage space capacity information, and index information of the N coding blocks; Determine a starting address of a second storage area of ​​each coding block based on the starting address of the first storage area, the capacity information of the first storage space, and the index information of each coding block; Among them, the starting address of the first storage area is the starting address of the storage area of ​​the transmission block corresponding to the first HARQ process, the first storage space capacity information is used to characterize the storage capacity of the storage area of ​​the coding block in the transmission block corresponding to the first HARQ process, and the starting address of the second storage area is used to indicate that the soft bit or the hard bit is stored in the corresponding storage area.

4. The method according to claim 3, characterized in that The downlink control information includes a HARQ process identifier, and the obtaining of a first storage area start address and first storage space capacity information corresponding to the first HARQ process includes: Based on the HARQ process identifier, acquiring the storage start address and storage space capacity information associated with the first HARQ process from the target cache to obtain the first storage area start address and the first storage space capacity information; The target cache records the M storage area start addresses and M storage space capacity information associated with the M HARQ processes.

5. The method according to any one of claims 1 to 4, characterized in that: The allocating a storage area for each coding block in the M transport blocks corresponding to the M HARQ processes includes: For each transport block, obtaining the number of bits corresponding to the soft bits of each coding block in the transport block; Determining a storage capacity of a storage area of ​​the coding block based on the number of bits corresponding to the soft bits; A storage area is allocated for each coding block in the transport block based on the storage amount.

6. The method according to any one of claims 1 to 5, characterized in that: After delivering the N hard bits corresponding to the N coding blocks in the physical layer to the media access control MAC layer in the data plane, the method further includes: Submitting N hard bits corresponding to the N coding blocks from the MAC layer to a Packet Data Convergence Protocol PDCP layer in the data plane; Performing a unified decryption process on the N hard bits through the PDCP layer to obtain PDCP decrypted data; The PDCP decrypted data is stored in a double data rate memory DDR.

7. The method according to any one of claims 1 to 6, characterized in that: After storing the soft bits corresponding to the coding block in the storage area corresponding to the coding block in the physical layer, the method further includes: Re-decoding the soft bits corresponding to the coding block; When the re-decoding is correct, the soft bits stored in the storage area corresponding to the coding block are replaced with hard bits.

8. A decoding device, characterized in that: The device comprises: An allocation module, configured to allocate a storage area for each coding block in M ​​transport blocks corresponding to the M HARQ processes when M hybrid automatic repeat request HARQ processes are acquired, wherein M is a positive integer; A determination module, configured to, when the downlink control information is acquired, determine that the HARQ process indicated by the downlink control information is the first HARQ process; A decoding module, configured to respectively decode N coding blocks in the transport block corresponding to the first HARQ process, where N is a positive integer; A storage module, configured to store the soft bits corresponding to the coding block in a storage area corresponding to the coding block in a physical layer when a decoding error occurs to the coding block; The storage module is further configured to store the hard bits corresponding to the coding block in a storage area corresponding to the coding block in the physical layer when the coding block is decoded correctly; The delivery module is used to deliver the N hard bits corresponding to the N coding blocks in the physical layer to the media access control MAC layer in the data plane after the N coding blocks are decoded correctly.

9. The device according to claim 8, characterized in that The submission module includes: A writing unit is used to write a first message in a target cache when the N coding blocks are all decoded correctly, so that the MAC layer reads the N storage areas of the N coding blocks based on the first message to obtain the N hard bits, wherein the first message is used to indicate that the N coding blocks are decoded correctly.

10. The device according to claim 8 or 9, characterized in that Also includes: an acquisition module, configured to, after determining that the HARQ process indicated by the downlink control information is the first HARQ process, acquire a first storage area start address, first storage space capacity information, and index information of the N coding blocks corresponding to the first HARQ process; The determining module is further configured to determine a starting address of a second storage area of ​​each coding block based on a starting address of the first storage area, the first storage space capacity information, and index information of each coding block; Among them, the starting address of the first storage area is the starting address of the storage area of ​​the transmission block corresponding to the first HARQ process, the first storage space capacity information is used to characterize the storage capacity of the storage area of ​​the coding block in the transmission block corresponding to the first HARQ process, and the starting address of the second storage area is used to indicate that the soft bit or the hard bit is stored in the corresponding storage area.

11. The device according to claim 10, characterized in that The acquisition module is specifically used for: Based on the HARQ process identifier, acquiring the storage start address and storage space capacity information associated with the first HARQ process from the target cache to obtain the first storage area start address and the first storage space capacity information; The target cache records the M storage area start addresses and M storage space capacity information associated with the M HARQ processes.

12. The device according to any one of claims 8 to 11, characterized in that: The allocation module comprises: An acquisition unit, configured to acquire, for each transport block, the number of bits corresponding to the soft bits of each coding block in the transport block; A determining unit, configured to determine a storage capacity of a storage area of ​​the coding block based on the number of bits corresponding to the soft bits; An allocating unit is used to allocate a storage area for each coding block in the transmission block based on the storage amount.

13. The device according to any one of claims 8 to 12, characterized in that: The delivery module is further configured to, after delivering the N hard bits corresponding to the N coding blocks in the physical layer to the media access control MAC layer in the data plane, deliver the N hard bits corresponding to the N coding blocks from the MAC layer to the packet data convergence protocol PDCP layer in the data plane; The device also includes: A decryption module, configured to perform a unified decryption process on the N hard bits through a PDCP layer to obtain PDCP decrypted data; The storage module is further used to store the PDCP decrypted data in a double data rate memory DDR.

14. The device according to any one of claims 8 to 13, characterized in that: The decoding module is further configured to re-decode the soft bits corresponding to the coding block after storing the soft bits corresponding to the coding block in the storage area corresponding to the coding block in the physical layer; The device also includes: The replacement module is used to replace the soft bits stored in the storage area corresponding to the coding block with hard bits when the re-decoding is correct.

15. An electronic device, characterized in that: The device comprises: a processor and a memory storing computer program instructions; When the processor executes the computer program instructions, the steps of the decoding method according to any one of claims 1 to 7 are implemented.

16. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer program instructions, and when the computer program instructions are executed by a processor, the steps of the decoding method according to any one of claims 1 to 7 are implemented.

17. A computer program product, characterized in that The computer program product is stored in a non-volatile storage medium, and the computer program product is executed by at least one processor to implement the steps of the decoding method according to any one of claims 1 to 7.

18. A chip, characterized in that: The method comprises a processor and a communication interface, wherein the communication interface and the processor are coupled, and the processor is used to run a program or an instruction to implement the steps of the decoding method according to any one of claims 1 to 7.

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