Small area current driver

Abstract

The present disclosure relates to a current driver circuit (200), including: an input branch (202) configured to receive an input current (IREF), a first transistor element (214), and a second transistor element (216); an output branch (204) comprising an output terminal (210), a third transistor element (218), and a fourth transistor element (220); and a bias branch (206) comprising a bias terminal (212) configured to receive a bias current (IB), and a fifth transistor element (222), wherein the second transistor element (216) and the fourth transistor element (220) define a current mirror to copy the input current (IREF) as output current (IOUT) at the output branch (204), wherein the third transistor element (218) is coupled with the input terminal (208) to allow a flow of current from the fourth transistor element (220) to the output terminal (210), wherein the fifth transistor element (222) is in a diode-connected configuration, and wherein the first transistor element (214) and the fifth transistor element (222) define a voltage level shift to provide a matching between a voltage at the first node (224b) of the second transistor element (214) and a voltage at the first node (224d) of the fourth transistor element (220).

Description

SMALL AREA CURRENT DRIVERTechnical Field

[0001] The present disclosure relates generally to a driver circuit having a reduced footprint.Background

[0002] In general, constant current drivers are an important building block in many circuit architectures. Simply put, a constant current driver is a circuit configured to deliver a regulated output current by maintaining the output current at a constant current value even in case of variations at an input of the driver or variations of a load coupled with the driver. A constant current driver is thus configured to adjust the voltage across the output to maintain a constant current flow. Constant current drivers have various applications for driving loads that should be fed with a constant current. A prominent example is the use of constant driver circuits for driving light emission, e.g. for driving light emitting diodes (LEDs). In this case, a constant current driver may be referred to as LED driver, or constant current LED driver. In this context, a constant current driver may ensure a uniform brightness of the emitted light, and may also reduce the risk of damaging the LEDs by ensuring that the LEDs do not draw more current than their nominal (rated) current. Thus, improvements in the capabilities of constant current drivers may be of particular relevance for the further advancements of several technologies, and in particular for driving light emitting devices (e.g., LED-based light emitting devices).Brief Description of the Drawings

[0003] In the drawings, like reference characters generally refer to the same parts throughout the different views. The drawings are not necessarily to scale, emphasis instead generally being placed upon illustrating the principles of the invention. In the following description, various aspects of the invention are described with reference to the following drawings, in which:FIG.1A and FIG. IB show possible configurations of a current driver circuit, in a schematic representation according to various aspects;FIG.1C and FIG. ID show possible configurations of an operational amplifier, in a schematic representation according to various aspects;FIG.2A shows a current driver circuit in a schematic representation according to various aspects;FIG.2B shows an implementation of the current driver circuit in a schematic representation according to various aspects;FIG.3 A shows the current driver circuit further including a voltage source, in a schematic representation according to various aspects;FIG.3B shows an implementation of the current driver circuit further including a voltage source, in a schematic representation according to various aspects;FIG.4A shows the current driver circuit further including an additional current source in the bias branch, in a schematic representation according to various aspects;FIG.4B shows an implementation of the current driver circuit further including an additional current source in the bias branch, in a schematic representation according to various aspects;FIG.5 A shows the current driver circuit further including additional current sources in the bias branch, in a schematic representation according to various aspects;FIG.5B shows an implementation of the current driver circuit further including additional current sources in the bias branch, in a schematic representation according to various aspects;FIG.6 shows a system including the current driver circuit and a load coupled with the current driver circuit, in a schematic representation according to various aspects; andFIG.7 A and FIG.7B show conventional circuit architectures in a schematic representation, to highlight a distinction with the configuration proposed herein.Description

[0004] The following detailed description refers to the accompanying drawings that show, by way of illustration, specific details and aspects in which the invention may be practiced. These aspects are described in sufficient detail to enable those skilled in the art to practice the invention. Other aspects may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the invention. The various aspects are not necessarily mutually exclusive, as some aspects may be combined with one or more other aspects to form new aspects.

[0005] In general, a constant current driver may be understood as a circuit configured to deliver a regulated output current. A current driver may receive an input (reference) current, and may provide at the output an output current having a stable current value. Considering LED applications, a constant current driver may be a constant current source capable of adapting to changes in forward voltage of a LED or string of LEDs. A constant current driver may thushave a range in which the output voltage may be varied to adapt to changes in the load and maintain a constant output current. The output DC voltage of a constant current driver may thus vary within the range according to the load, e.g. for an increasing load resistance the output voltage may increase, and for a decreasing load resistance the output voltage may decrease. A “constant current driver” may also be referred to herein simply as “current driver”.

[0006] In this regard, the design of a current driver combines large accuracy with severe dynamic range requirements. Accuracy may be required in several applications (for instance, in LED drivers the mismatch between the LED currents would alter the generated color) while dynamic range reduction is usually a strict requirement because it helps to keep the power dissipation inside the device at a small level. With this in mind, the usual approach for designing a constant current driver is not a simple cascoded current mirror, but it rather introduces an operational amplifier to obtain high output impedance, meet aggressive dynamic range demands and enable fast turn-on.

[0007] Various architectures have been developed to realize constant current drivers. In general, the basic concepts related to constant current drivers and their operation are well known in the art. A brief description is provided herein to introduce aspects relevant for the present disclosure. Some relevant design considerations will be discussed in relation to FIG.1A to FIG. ID, which show possible architectures of a current driver and of possible components of a current driver.

[0008] In the present disclosure particular reference may be made to the use of a current driver for driving a LED or a plurality of LEDs. Illustratively, particular reference may be made to the use of a current driver as LED driver, or as part of a LED driver. This application may be of particular interest because a current driver enables a precise control of the current delivered to the LED, thus allowing a precise control of the emitted light, e.g. in terms of color, brightness, and the like. Therefore, in the present disclosure terminology may be used that pertains to the particular context of LEDs and light emission. It is however understood that the aspects described in relation to a current driver for delivering current to a LED may apply in a corresponding manner to other applications of a current driver, e.g. for driving other types of circuits. For example, an output current of a current driver may be indicated or described as ILED, but it is understood that such current may be for use in any suitable application, and may be referred simply as “output current” (IOUT).

[0009] FIG.1A and FIG. IB show various configurations 100a, 100b of a current driver 100, in a schematic representation. The various configurations 100a, 100b are collectively referred to herein as current driver 100. In general, the current driver 100 may include an operationalamplifier and one or more transistors to receive a reference current IREF (e.g., by a reference current source 102) and deliver an output current ILED. In the exemplary configurations in FIG.1A and FIG. IB the transistors are represented as NMOS transistors, where NMOS stands for N-channel metal-oxide semiconductors (a type of Metal-Oxide-Semiconductor Field-Effect-Transistor, MOSFET). It is however understood that the aspects described herein may apply in a corresponding manner to other types of transistors, e.g. PMOS (P-channel metal- oxide semiconductors), or bipolar junction transistors (BJTs).

[0010] Furthermore, in the exemplary configuration in FIG.1 A and FIG. IB, a reference current source 102 is illustrated to provide the reference current IREF at the input of the current driver 100. In this configuration the current driver 100 acts a current sink at the output. The aspects described in relation to this configuration apply in a corresponding manner to the opposite case in which a current sink is present at the input, and the current driver 100 behaves as a current source at the output.

[0011] FIG.1A shows a first configuration 100a of a feedback-based current mirror, which represents a popular implementation of a LED driver. As an abridged overview, the feedbackbased current mirror 100a may receive a reference current IREF (e.g., from a reference current source 102), and may be configured to mirror the reference current IREF by means of a first transistor 104 (MD) and a second transistor 106 (MLED) into the output branch as output current ILED, e.g. to bias an external LED. The current mirror 100a may further include a third transistor 108 (Me) and a fourth transistor 110 (MOUT) as cascode elements to increase the output impedance. The current mirror 100a may further include an operational amplifier 114 that further increases the output impedance, as the requirement is usually severe. The virtual ground of the operational amplifier 114 is usually taken at a voltage VR that is obtained as the difference of the saturation voltages of two transistors (e.g., two NMOS). This optimizes the output dynamic range at the output terminal (e.g., at a LED pin).

[0012] By way of illustration, in the configuration in FIG.1A, the operational amplifier 114 works as a regulated cascode to increase the output impedance. The current mirror is defined by the first transistor 104 (MD) and the second transistor 106 (MLED). Illustratively, the drain current of the second transistor 106 (MLED) follows the reference current IREF. The third transistor 108 (Me) is a cascode element to maintain the voltage VR low. Illustratively, the third transistor 108 (Me) prevents the first transistor 104 (MD) to be in a triode configuration. The third transistor 108 (Me) may be seen as a shifting element to maintain the drain voltage of the first transistor 104 (MD) sufficiently low.

[0013] As shown, the current driver 100a may further include a “bias branch” at which the current driver 100a receives a bias current IB (e.g., from a bias current source 116), and further includes a fifth transistor 112 (MCASC) that has a source terminal coupled with the source terminal of the second transistor 106 (MLED).

[0014] In the configuration 100a there are thus a reference branch, where the reference current IREF is injected into a diode, the operational amplifier 114 and the output section. The reference branch has embedded a level shift transistor 108 (Me) to reduce the drain voltage of the first transistor (MD) that plays the role of the diode. The operational amplifier 114 brings the same voltage at the drain of the second transistor 106 (MLED) that acts as current generator.

[0015] The configuration 100a presents various drawbacks. For example, the voltage VR at the input of the operational amplifier 114 is close to ground, whereas the output of the operational amplifier 114 goes to the gate of the fourth transistor (MOUT), and thus should be close to the gate-source voltage (VGS) for activating that transistor. There may thus be some issues considering the dynamic range, and folding may be required to obtain a suitable dynamic range between the voltage VR at the input and the output of the operational amplifier 114. Furthermore, the configuration 100a is rather area consuming due to the presence of a relatively high number of transistors (considering also the architecture of the operational amplifier 114).

[0016] In many cases, the bias branch including the fifth transistor (MCASC) may be removed by shorting the gates of the third transistor 108 (Me) and first transistor 104 (MD), as shown in the configuration 100b in FIG. IB. This reduces the value of the output impedance because the second transistor 106 (MLED) is at a borderline condition for triode but the degradation is usually acceptable. In this scenario, the “cascoding branch” is removed by directly connecting the first transistor 104 (MD) to the reference current IREF, SO that the cascode is directly biased by the same branch used to provide the reference current IREF to the output mirror.

[0017] The configuration 100b of FIG. IB may have a comparable performance as the configuration 100a, with a tolerable degradation. There may be however still concerns regarding the operational amplifier 114. In general, the output current ILED is a replica of the reference current IREF, SO that they should share the same accuracy. The operational amplifier 114 should be suitably biased, thus introducing the need for another element of generator of bias to drive the operational amplifier 114.

[0018] The concerns regarding the operational amplifier 114 may be understood considering the configurations 150c, 150d of an exemplary operational amplifier 150 in FIG.1C and FIG.1D (illustratively, exemplary configurations of the operational amplifier 114). As mentioned, the relevant concern about the operational amplifier design is related to the fact thatthe input common mode is near ground, usually in the order of 200 mV or 300 mV, whereas the output should stay above the VGS of the transistor MOUT (e.g., NMOS). This requirement leads to the introduction in the operational amplifier 150 of an input stage with a PMOS differential pair (usually poorer than an NMOS in terms of matching), plus some folding to bring the signal from this stage to the output. Considering the configuration of FIG.1 A and FIG. IB, the output signal 170c, 170d (“out”) at the output of the operational amplifier 150 may drive the gate of the fourth transistor 110 (MOUT).

[0019] Considering the configuration 150c in FIG.1C, the operational amplifier 150 may include a differential pair formed by two PMOS transistors 152c, 154c, biased by a tail current ITAIL (from a tail current source 156c). At the output, the operational amplifier 150 may further include another pair of PMOS transistors 158c, 160c and a pair of NMOS transistors 162c, 164c, biased by bias current IB (from bias current source(s) 166c, 168c).

[0020] The configuration 150d in FIG. ID provides an alternative less straightforward implementation, in which level shifters are introduced. In the configuration 150d, the differential pair includes four transistors, i.e. a pair of a first series of NMOS transistor 162d and PMOS transistor 152d and a second series of NMOS transistor 164d and PMOS transistor 154d, biased by bias current IB (from bias current source(s) 166d, 168d). The configuration 150d further includes an output level shift (a further NMOS transistor 172d biased by a further bias current IB2 from a further bias current source 174d) to prevent the NMOS device 164d from operating in triode.

[0021] The configuration 150d provides thus an alternative implementation of an operational amplifier that may accept an input dynamic range down to ground voltage. However, also in this case, any requirements about the minimum supply voltage may become potentially critical. Furthermore, the presence of more branches and poles brings non-negligible concerns about the stability of the part and the offset of the amplifier 150. Usually large devices (having a larger area) and large power consumption are related to such design of the part.

[0022] Aspects of the present disclosure are related to an adapted architecture for a current driver that provides area savings compared to conventional driver architectures. Aspects of the present disclosure may be based on the realization how to design a current driver to implement its functionality with a reduced number of components. In particular, the architecture of the proposed current driver may include a smaller number of transistor elements compared to conventional architectures, and an adapted arrangement and coupling of the transistor elements may be provided to implement the current mirroring and op-amp functionalities while saving a significant amount of area, dissipation and even design effort.

[0023] According to various aspects, a current driver circuit may include: an input branch including an input terminal configured to receive an input current, a first transistor element coupled with the input terminal, and a second transistor element coupled with the first transistor element; an output branch including an output terminal configured to be coupled with a load, a third transistor element coupled with the output terminal, and a fourth transistor element coupled with the third transistor element; and a bias branch comprising a bias terminal configured to receive a bias current, and a fifth transistor element coupled with the bias terminal, wherein each transistor element comprises a first node, a second node, and a control node to allow controlling a current flow between the first node and the second node; wherein the second transistor element and the fourth transistor element are configured to define a current mirror to copy the input current from the input branch as output current at the output branch, wherein the third transistor element is disposed between the fourth transistor element and the output terminal, and the control node of the third transistor element is coupled with the input terminal to allow a flow of current from the fourth transistor element to the output terminal, wherein the fifth transistor element is in a diode connected configuration, wherein the control nodes of the first transistor element and the fifth transistor element are coupled with the bias terminal, and wherein the first transistor element and the fifth transistor element are configured to define a voltage level shift to provide a matching between a voltage at the first node of the second transistor element and a voltage at the first node of the fourth transistor element.

[0024] As mentioned, the proposed approach may be of particular relevance for implementation in an electronic circuit for driving light emitting elements, e.g. light emitting diodes. The proposed strategy allows providing the driving current to control the light emission while maintaining a small footprint of the current driver, thus facilitating its integration in many host devices (e.g., mobile communication devices, vehicles, and the like). Thus, in the following particular reference may be made to a configuration in which the proposed current driver is used to deliver driving current to one or more light emitting elements. It is however understood that the application of the proposed circuit architecture are not limited to light emitting elements, and the current driver may be for use in any suitable scenario.

[0025] FIG.2A shows a current driver circuit 200 in a schematic representation, according to various aspects. In general, the current driver circuit 200 may include an input branch 202 that includes an input terminal 208 configured to receive an input current IREF, and an output branch 204 that includes an output terminal 210 at which the current driver circuit 200 provides an output current IOUT. The input branch 202 may also be referred to herein as reference branch 202, the input terminal 208 may also be referred to herein as reference terminal 208, and theinput current IREF may also be referred to herein as reference current or input reference current. According to the proposed architecture, the current driver circuit 200 may further include a bias branch 206 that includes a bias terminal 212 configured to receive a bias current IB. The current driver circuit 200 may also be referred to herein as constant current driver circuit, as constant current driver, or simply as current driver or driver circuit.

[0026] According to various aspects, the current driver circuit 200 may be an integrated circuit. Illustratively the various components of the current driver circuit 200 may be integrated on the same substrate, e.g. on a printed circuit board (PCB) substrate.

[0027] As an exemplary configuration, the current driver circuit 200 may include a reference current source or may be coupled with a reference current source at the input terminal 208, and the reference current source may be configured to generate / supply the input current IREF. Considering a current source configured to supply the reference current IREF, the current driver circuit 200 may act as a current sink at the output side. As an exemplary implementation, the reference current source may include a digital-to-analog converter. As another exemplary configuration, the current driver circuit 200 may include a reference current sink or may be coupled with a reference current sink at the input terminal 208. Considering a current sink configured to sink the reference current IREF at the input terminal 208, the current driver circuit 200 may act as a current source at the output side.

[0028] In the present disclosure particular reference may be made to the scenario in which the input terminal 208 is coupled with a reference current source that supplies the input current IREF, as this may be the most relevant use case scenario considering an application of the current driver circuit 200 for driving light emission. It is however understood that the aspects described in relation to a configuration with a reference current source may apply in a corresponding manner to a configuration with a reference current sink, and vice versa.

[0029] In a corresponding manner, in some aspects the current driver circuit 200 may include a bias current source or may be coupled with a bias current source at the bias terminal 212, and the bias current source may be configured to generate / supply the bias current IB at the bias terminal 212. At the output branch 204, the output terminal 210 may be configured to be coupled with a load (see also FIG.6), e.g. the current driver circuit 200 may be configured to deliver the output current IOUT to the load, e.g. for driving an operation of the load such as a light emission.

[0030] The current driver circuit 200 may in general be configured to mirror the input current IREF as output current IOUT at the output terminal 210. Illustratively, the current driver circuit 200 may replicate the input current IREF at the output terminal 210. The configuration proposedherein and discussed in further detail below may apply to any suitable relationship between the input current IREF and the output current IOUT. AS an example, the current driver circuit 200 (e.g., the second and fourth transistor elements 216, 220) may be configured such that a current value of the output current IOUT is equal to a current value of the input current IREF. AS another example, the current driver circuit 200 (e.g., the second and fourth transistor elements 216, 220) may be configured such that a current value of the output current IOUT is a multiple of the current value of the input current IREF, e.g. the output current IOUT may be two times the input current IREF, or three times the input current IREF, or any other suitable multiple (e.g., integer multiple). As a further example, the current driver circuit 200 (e.g., the second and fourth transistor elements 216, 220) may be configured such that a current value of the output current IOUT is a fraction of the current value of the input current IREF, e.g. the output current IOUT may be half of the input current IREF, or one-third of the input current IREF, or any other suitable fraction.

[0031] In principle, the architecture proposed herein may be adapted to any suitable range for a current value of the input current IREF and output current IOUT. In a preferred configuration, the current driver circuit 200 may be configured to deliver an output current IOUT having a current value in the range from 50 pA (microampere) to 50 mA (milliampere), for example a current value in the range from 100 p A to 10 mA, for example a current value in the range from 1 mA to 2 mA.

[0032] The architecture proposed herein allows obtaining a circuit having a small footprint, by allowing a reduction of the overall number of circuit components. The current driver circuit 200 may thus be a “small footprint circuit”, or “small area circuit”. As a numerical example, the current driver circuit 200 may have a footprint in the range from 0.0005 mm2(square millimeters) to 1 mm2, for example a footprint in the range from 0.001 mm2to 0.5 mm2, for example a footprint in the range from 0.01 mm2to 0.05 mm2. In this regard, the term “footprint” may indicate the area occupied by the circuit (e.g., on a substrate).

[0033] The input branch 202, output branch 204, and bias branch 206 may each include one or more transistor elements. In various aspects, the input branch 202 may include a first transistor element 214 and a second transistor element 216, the output branch 204 may include a third transistor element 218 and a fourth transistor element 220, and the bias branch 206 may include a fifth transistor element 222. Possible variations of such configuration will be described in further detail in relation to FIG.3A to FIG.5B.

[0034] Each transistor element 214-222 may include a respective first node 224a-224e, second node 226a-226e, and control node 228a-228e. The control node 228a-228e may allow controlling an electrical behavior between the first node 224a-224e and the second node226a-226e (e.g., the behavior of a channel between the first node 224a-224e and the second node 226a-226e). Illustratively, the control node 228a-228e may allow controlling a current flow between the first node 224a-224e and the second node 226a-226e, e.g. a current flow from the second node 226a-226e towards the first node 224a-224e.

[0035] In principle, any suitable type of transistor may be used. In a preferred configuration, a transistor element 214-222 may include a MOSFET, in particular a NMOS transistor. NMOS transistors may be realized with smaller dimensions compared to other transistor types, thus contributing to the small footprint of the circuit 200. In other aspects, a transistor element 214-222 may include a PMOS transistor, or another type of transistor such as a BJT.

[0036] Considering the configuration in which a transistor element 214-222 includes an NMOS transistor, the control node 228a-228e may be a gate node, the first node 224a-224e may be a drain node, and the second node 226a-226e may be a source node. The NMOS transistor may include a gate structure defining a channel region (in a bulk material) between the source node and the drain node. In this case, the gate node may allow controlling a drain current from the source node towards the drain node.

[0037] Considering, as another example, the configuration in which a transistor element 214-222 includes a BJT, the control node 228a-228e may be a base node, the first node 224a-224e may be a collector node, and the second node 226a-226e may be an emitter node. It is understood that also other configurations with inverted arrangement of the source / drain node or collector / emitter node may be provided, depending on the type of transistor used. In general, the transistor elements 214-222 may be of the same transistor type or of different transistor types, as will be described in further detail below.

[0038] Before introducing the functions carried out by the transistor elements 214-222, it appears beneficial to describe in detail how the transistor elements 214-222 are coupled with one another and with the various terminals of the current driver circuit 200.

[0039] Turning to the input branch 202, the first transistor element 214 and the second transistor element 216 may be connected in series to one another. In this regard, the second node 226a of the first transistor element 214 may be coupled with the first node 224b of the second transistor element 216. The first transistor element 214 may be further coupled with the input terminal 208, e.g. the first node 224a of the first transistor element 214 may be coupled with the input terminal 208. The second transistor element 216 may be further coupled with the output branch 204, as will be discussed in further detail below. The input current IREF may thus bias the first transistor element 214 and the second transistor element 216.

[0040] Turning to the output branch 204, the third transistor element 218 and the fourth transistor element 220 may be connected in series to one another. In this regard, the second node 226c of the third transistor element 218 may be coupled with the first node 224d of the fourth transistor element 220. The third transistor element 218 may be further coupled with the output terminal 210, e.g. the first node 224c of the third transistor element 218 may be coupled with the output terminal 210. The fourth transistor element 220 may be further coupled with the input branch 202, as will be discussed in further detail below.

[0041] Turning to the bias branch 206, the fifth transistor element 222 may be coupled with the bias terminal 212, e.g. the first node 224e of the fifth transistor element 22may be coupled with the bias terminal 212. The fifth transistor element 222 may have a diode-connected configuration, e.g. the first node 224e and the control node 228e of the fifth transistor element 222 may be coupled with one another, so that a voltage at the first node 224e corresponds to a voltage at the control node 228e. In view of the diode-connected configuration, the fifth transistor element 222 may have a diode characteristic and may behave like a “two-terminal” device. Considering for example the case in which the fifth transistor element 222 is a NMOS transistor, the gate may be connected to the drain, so that the NMOS transistor may be in saturation.

[0042] Turning now to the functionalities implemented via the transistor elements 214-222, the second transistor element 216 and the fourth transistor element 220 may be configured to define a current mirror to copy the input current IREF from the input branch 202 as output current IOUT at the output branch 204. Illustratively, the second transistor element 216 and the fourth transistor element 220 may be coupled with one another in such a way that the input current IREF from the input branch 202 may be converted into a voltage to drive the fourth transistor element 220 and provide the output current IOUT at the output branch 204. In some aspects, the second transistor element 216 and the fourth transistor element 220 may be of the same transistor type (e.g., both NMOS).

[0043] As shown in FIG.2A, the control node 228b of the second transistor element 216 may be coupled with the control node 228d of the fourth transistor element 220. Furthermore, the second node 226b of the second transistor element 216 and the second node 226d of the fourth transistor element 220 may be at the same potential, for example the second nodes 226b, 226d may be coupled to one another and / or may both be coupled to a (same) reference potential (e.g., at a ground terminal 230).

[0044] The control node 228b of the second transistor element 216 may further be coupled with the control node 228a of the first transistor element 214. Thus, upon providing a suitable controlvoltage at the control node 228a of the first transistor element 214, the second transistor element 216 may be brought into a diode-connected configuration. The second transistor element 216 may thus be understood as the reference equivalent diode for the current mirror. In this case, the input current IREF may define a control voltage at the control node 228d of the fourth transistor element 220 (e.g., a gate source voltage VGS considering a NMOS configuration), thus causing a current flow from the fourth transistor element 220 (e.g., from the first terminal 224d towards the output terminal 210). As generally known in the art, a relationship between the input current IREF and the current output from the fourth transistor element 220 may be adapted by selecting the dimensions of the transistors. Considering for example the scenario in which the second transistor element 216 and the fourth transistor element 220 are NMOS devices, a current ID output from the fourth transistor element 220 may be expressed as ID=[(W / L) / (W / L)REF]*IREF where W / L is the ratio between the width and the length of the fourth transistor element 220 and (W / L)REF is ratio between the width and the length of the second transistor element 216. The fourth transistor element 220 may thus be understood as a current generator to generate the output current IOUT.

[0045] Compared to the configuration discussed in relation to FIG.1A and FIG. IB, the proposed circuit architecture may have at least two main differences.

[0046] As a first aspects, the third transistor element 218 disposed along the path between the fourth transistor element 220 and the output terminal 210 may further be coupled with the input terminal 208, as shown the control node 228c of the third transistor element 218 may be coupled with the input terminal 208. Thus, in the proposed configuration, the third transistor element 218 may act as a control gate for the current ID output from the fourth transistor element 220 (a copy of the input current IREF). The third transistor element 218 may thus allow enabling the flow of output current IOUT from the fourth transistor element 220 towards the output terminal 210, as controlled by the input current IREF via the coupling of the control node 228c and the input terminal 208. Having in mind the configuration of FIG.1 A and FIG. IB, the third transistor element 218 may illustratively behave as the transistor 110 (MOUT), and having the bias coming from the input terminal 208 makes the input branch 202 of the proposed configuration equivalent to the operational amplifier 114 of the configuration of FIG.1 A and FIG. IB. Thus, in the proposed architecture the “op-amp functionality” may be provided with a more compact arrangement compared to conventional circuit architectures.

[0047] As a further aspect, the first transistor element 214 and the fifth transistor element 222 may be configured to act as a level shifter to provide a matching between the voltage at the first node 224b of the second transistor element 216 and the voltage at the first node 224d of thefourth transistor element 220 (e.g., a matching between the drain voltages of the second and fourth transistor elements 216, 220). As shown, the second node 226e of the fifth transistor element 222 may be coupled with the first node 224d of the fourth transistor element 220 and, as discussed, the second node 226a of the first transistor element 214 may be coupled with the first node 224b of the third transistor element 216. The first transistor element 214 and the fifth transistor element 222 may thus be configured to define a voltage level shift to cause the voltage at the first node 224b of the second transistor element 216 to match (illustratively, be equal to) the voltage at the first node 224d of the fourth transistor element 220.

[0048] The function of the level shifter defined by the first transistor element 214 and fifth transistor element 222 may be better illustrated considering the case in which the transistor elements 214-220 are realized as NMOS transistors, but such considerations may apply also to other transistor types.

[0049] In general, the central component of the circuit 200 is the second transistor element 216, which receives (e.g., draws) the input current IREF. Considering the circuit architecture and the coupling among the transistor elements 214-220, the current at the second transistor element 216 (e.g., its drain current) matches the input current IREF, thus ensuring that the voltage at the input of the circuit 200 does not diverge.

[0050] The voltage across the second transistor element 216, e.g. the voltage between the control node 228b and the second node 226b (e.g., its gate-source voltage VGS), may thus be fixed, in view of the fixed current (IREF) delivered to the second transistor element 216. The difference between the voltage across the second transistor element 216 (a second gate-source voltage VGS) and the voltage across the fifth transistor element 222 (e.g., the voltage between the control node 228d and the second node 226d, e.g. a fifth gate-source voltage VGS) may define the voltage at the first node 224d of the fourth transistor element 220, e.g. its drain voltage, referred to herein as VR. By way of illustration, VR may be obtained by going up by the second gate-source voltage VGS and then down by the fifth gate-source voltage VGS.

[0051] At the input side, the voltage at the first node 224b of the second transistor element 216, e.g. its drain voltage, may be defined by the voltage across the first transistor element 214 (e.g., the voltage between the control node 228a and the second node 226a, e.g. a first gate-source voltage VGS). Illustratively, the voltage at the first node 224b of the second transistor element 216 may be defined by the difference between the voltage across the second transistor element 216 and the voltage across the first transistor element 214. By way of illustration, the drain voltage of the second transistor element 216 may be obtained by going down by the first gate-source voltage VGS.

[0052] By configuring the first transistor element 214 and the fifth transistor element 222 as matched transistors (e.g., as transistors of the same type, and with matched dimensions as discussed below), so that the voltage across the first transistor element 214 corresponds to the voltage across the fifth transistor element 222, it is ensured that the voltage at the first node 224b of the second transistor element 216 matches the voltage at the first node 224d of the fourth transistor element 220. The voltage matching improves the performance of the current mirror.

[0053] As mentioned, the control node 228a of the first transistor element 214 and the control node 228e of the fifth transistor element 222 may be coupled with one another, and may further be coupled with the bias terminal 212. The bias current IB may thus drive the behavior of the first transistor element 214 and fifth transistor element 222. In some aspects, the first transistor element 214 and the fifth transistor element 222 may be of the same transistor type (e.g., both NMOS), for example the same type as the second and fourth transistor elements 216, 220 or a different type with respect to the second and fourth transistor elements 216, 220.

[0054] By way of illustration, the proposed architecture may include a “single branch operational amplifier” (the first and second transistor elements 214, 216 biased by the input current IREF). The voltage at the control node 228b of the second transistor element 216 (e.g., at its gate) may set the value of the virtual ground of the operational amplifier, and such voltage may bias both the control node 228d and the first node 224d (e.g., the drain) of the fourth transistor element 220 (illustratively, the output current generator). The first achievement may be accomplished via the direct connection between the control nodes 228b, 228d of the second and fourth transistor elements 216, 220, so that the second and fourth transistor elements 216, 220 may act as a true current generator.

[0055] At the same time, to set the same voltage at the first node 224b, 224d (e.g., the drain) for both devices, two voltage shifters 214, 222 are added to the architecture. According to various aspects, the first and fifth transistor elements 214, 222 may be matched voltage shifters. In this regard, an aspect ratio of the first transistor element 214 (e.g., W / L considering a MOSFET, where W is the width and L is the length) may be proportional to the aspect ratio of the fifth transistor element 222 by a proportionality factor defined as the ratio of the input current IREF to the bias current IB. Considering that in general the input current IREF may be greater than the bias current IB, the aspect ratio of the first transistor element 214 may be greater than the aspect ratio of the fifth transistor element 222 by the factor IREF / IB. Illustratively, the fifth transistor element 222 may be considered as a simple diode, biased by the additional biascurrent IB, and the first transistor element 214 may be a matched transistor to satisfy the condition mentioned above.

[0056] The matching of the aspects ratios to the current values ensures the matching of the voltages at the first nodes 224b, 224d of the second and fourth transistor elements 216, 220. This allows fulfilling the tight demands regarding the dynamic range at the output side of the current driver circuit 200.

[0057] Having in mind the configurations discussed in relation to FIG.1A to FIG. ID, a straightforward comparison of their complexity with respect to the proposed architecture may be provided. Indeed, even though an input branch (with two series-connected transistors) and an output branch (with two series-connected transistors) are present in both architectures, the current driver circuit 200 includes a single (bias) branch 206 including the bias terminal 212 and the fifth transistor element 222 (and, in some aspects, a current bias generator) to complete the architecture. Compared to the configurations of FIG.1 A to FIG. ID where an operational amplifier having three or four branches and many transistors is adopted, the proposed configuration allows obtaining advantageous savings in power consumption and area.

[0058] In addition, thanks to the smaller number of internal nodes and devices, the feedback loop of the proposed architecture may provide a better stability so that also a smaller compensating cap may be needed. In a simple configuration (shown in FIG.2A), the current driver circuit 200 may include exactly five transistor elements 214-222. Finally, in case NMOS transistors are used at the input branch 202, having a NMOS input stage that replaces a PMOS one and the smaller number of devices, the offset affecting the accuracy at the first node 224d of the fourth transistor element 220 (VR node) may be smaller for the proposed architecture.

[0059] In the current driver circuit 200, the input current IREF may bias the second transistor element 216 providing the current mirror, and in addition the connection at the control node 228c of the third transistor element 218 at the output branch 204 comes directly from the branch driven by the input current IREF. Thus, in the current driver circuit 200, the input branch 202 plays the twofold role of amplifier and reference branch for the current mirror, thus providing such functionalities with fewer transistors compared to a conventional configuration. In the proposed architecture, the first transistor element 214 and second transistor element 216 may act as “operational amplifier”, in that the first node 224a (e.g., the drain) of the first transistor element 214 biases the control node 228c (e.g., the gate) of the third transistor element 218, while the control node 228b of the second transistor element 216 is coupled (via the fifth transistor element 222 acting as a diode) to the first node 224d (e.g., the drain) of the fourth transistor element 220. This is what the operational amplifier 114 in FIG.1A and FIG. IBaccomplishes, realized with fewer components. In a conventional configuration there are rather two separate components, whereas in the proposed architecture the function of the input current and operational amplifier are embedded in a single block that use fewer transistors.

[0060] In the proposed architecture, the first transistor element 214 may act a cascode element. In this regard, a “cascode” may be a device connected / configured to provide an impedance increase, e.g. an increase in output impedance. Further, the fifth transistor element 222 is biased by the voltage at the second transistor element 216 (e.g., its VGS voltage), and biases directly the voltage at the fourth transistor element 220. The first transistor element 214 and fifth transistor element 222 provide thus a shift that may reduce the voltage at the first node 224d of the fourth transistor element 220 to increase the dynamic range at the output. In this context, the first transistor element 214 is part of the architecture to bring the first node 224b of the first transistor element 216 to the same voltage (VR) as the first node 224d of the fourth transistor element 220 to have a better matching condition for the current mirror.

[0061] As mentioned above, the first and fifth transistor elements 214, 222 may be transistors of the same type with respect to one another, and the second and fourth transistor elements 216, 220 may be transistors of the same type with respect to one another. In this regard, the transistor type of the third transistor element 218 may be freely selected. For example, the third transistor element 218 may be of a different type with respect to the first / fifth transistor elements 214, 222 and may be of the same type as the second / fourth transistor elements 216 / 220, or vice versa. As another example, all transistors may be of the same transistor type (e.g., all NMOS). The free adaptation of the third transistor element 218 allows optimizing such transistor having area savings considerations in mind, without the need to provide a specific “matched” transistor type.

[0062] Before moving to further implementations and configurations of the current driver circuit 200, it is beneficial to discuss the role of the third transistor element 218. By way of illustration, the third transistor element 218 acts as control gate and allows to set the voltage at the first node 224d of the fourth transistor element 220. Further, the third transistor element 218 allows the first transistor element 216 to draw current by allowing to have VR at the suitable value, translated by the fifth transistor element 222 that sets the voltage at the control node 228b of the fourth transistor element 220 to draw the input current IREF. The third transistor element 218 receives the current that is output from the fourth transistor element 220 (as output current IOUT), and the voltage across the third transistor element 218 (e.g., the voltage between the control node 228c and the second node 226c, e.g., a third gate source voltage VGS) is defined by having the voltage VR at the second node 226c (e.g., the source), which is fixed, and thevoltage at the control node 228c is defined by the input current IREF. The third transistor element 218 allows thus the current flow from the fourth transistor element 220, and the presence of the third transistor element 218 illustratively closes the loop in the circuit architecture, thus providing suitable voltage values at the nodes of the second and fourth transistor elements 216, 220.

[0063] FIG.2B shows a current driver circuit 250 that shows an exemplary implementation of the current driver circuit 200. The configuration of FIG.2B may be a preferred realization of the current driver circuit 200, which implements the various functionalities with components that allow achieving a small footprint. It is however understood that also other implementations may be provided, e.g. with other types of transistors.

[0064] The current driver circuit 250 may include an input branch, an output branch, and a bias branch. At the input branch the current driver circuit 250 may include a reference current source 252 and an input terminal 258 (a reference terminal), coupled with the reference current source 252. The reference current source 252 may supply input current IREF to the input terminal 258. Further, at the input branch the current driver circuit 250 may include a first NMOS transistor 264 (Me) series with a second NMOS transistor 266 (MD). AS shown, the drain node of the first NMOS transistor 264 (Me) may be coupled with the input terminal 258, and the source node of the first NMOS transistor 264 (Me) may be coupled with the drain node of the second NMOS transistor 266 (MD).

[0065] At the output branch, the current driver circuit 250 may include an output terminal 260 at which the current driver circuit 250 provides an output current ILED. Further at the output branch the current driver circuit 250 may include a third NMOS transistor 268 (MOUT) series with a fourth NMOS transistor 270 (MLED). AS shown, the drain node of the third NMOS transistor 268 (MOUT) may be coupled with the output terminal 260, and the source node of the third NMOS transistor 268 (MOUT) may be coupled with the drain node of the fourth NMOS transistor 270 (MLED)

[0066] As discussed in relation to FIG.2A, the second NMOS transistor 266 (MD) and the fourth NMOS transistor 270 (MLED) may form a current mirror to “mirror” the input current IREF at the output branch as drain current of the fourth NMOS transistor 270 (MLED). In this regard, as shown, the gate nodes of the second NMOS transistor 266 (MD) and fourth NMOS transistor 270 (MLED) may be coupled with one another, and further the source nodes of the second NMOS transistor 266 (MD) and fourth NMOS transistor 270 (MLED) may be coupled with one another (and with a reference terminal 280, e.g. ground).

[0067] At the bias branch, the current driver circuit 250 may include a bias current source 256 and a bias terminal 262 coupled with the bias current source 256. The bias current source 256 may supply a bias current IB to the bias terminal 262. Further at the output branch the current driver circuit 250 may include a fifth NMOS transistor 272 (MLS) in a diode-connected configuration. Illustratively, the drain node and gate node of the fifth NMOS transistor 272 (MLS) may be coupled with one another. The drain node of the fifth NMOS transistor 272 (MLS) may be coupled with the bias terminal 262.

[0068] As discussed in relation to FIG.2A, the first NMOS transistor 264 (Me) and the fifth NMOS transistor 272 (MLS) may be configured as level shifters to cause the voltage at the drain node of the second NMOS transistor 266 (MD) to match (illustratively, to be equal or substantially equal) the voltage VR at the drain node of the fourth NMOS transistor 270 (MLED), thus improving the accuracy of the current mirroring. In this regard, the gate node of the first NMOS transistor 264 (Me) may be coupled with the gate node (and accordingly with the drain node) of the fifth NMOS transistor 272 (MLS). Accordingly, the gate node of the first NMOS transistor 264 (Me) may be coupled with bias terminal 262. Furthermore, the source node of the fifth NMOS transistor 272 (MLS) may be coupled with the drain node of the fourth NMOS transistor 270 (MLED).

[0069] Turning again to the output branch, as discussed in relation to FIG.2A, the gate node of the third NMOS transistor 268 (MOUT) may be coupled with the input terminal 258. This coupling allows the third NMOS transistor 268 (MOUT) to receive the input current IREF, and allows using the input current IREF to bias the “amplification stage” of the current driver circuit 250. Illustratively, the third transistor element 218 (MOUT) acts as control gate and is crossed by the mirrored replica of the input current IREF, whereas the amplification stage made by the first and second transistor elements 214, 216 is biased by the input current IREF directly, and this is possible thanks to the third transistor element 218 (MOUT) that closes the loop and allows this bias.

[0070] As discussed above, the comparison with other architectures (e.g., as shown in FIG.1A to FIG. ID) shows a relevant advantage in terms of complexity and power dissipation. In the following, in relation to FIG.3A to FIG.5B, possible modifications of the current driver circuit 200, 250 will be described. For the sake of clarity and brevity, the circuit components already described in relation to FIG.2A and FIG.2B are indicated in FIG.3A to FIG.5B with the same reference signs, and a repetition of the already described connections and configurations will be omitted. It is understood that the aspects discussed in relation to the current driver circuit200, 250 in FIG.2A and FIG.2B apply also to the current driver circuit 300, 350, 400, 450, 500, 550 in FIG.3A to FIG.5B, and vice versa.

[0071] A further improvement of the proposed configuration is related to limiting the effect of the bias current IB (and bias source), which may be a source of inaccuracy, and may subtract from the current IOUT supplied to the output load. Furthermore, in the proposed configuration the fourth transistor element (MLED) works at the triode boundaries.

[0072] Usually these potential issues are tolerable. The output impedance remains high enough even in case the fourth transistor element (MLED) is slightly in triode. Moreover, the increased sensitivity to the offset of the operational amplifier is mitigated by the already discussed superior accuracy at reference VR. AS a further consideration, the effect of the bias current IB (and bias source) is negligible any time the output current IOUT is much larger than the reference current IREF, as it normally is for any kind of current driver, and may play a role only in case the mirror ratio between MLED and MD is small.

[0073] Notwithstanding the above considerations, in some aspects a voltage source may be introduced in the circuit architecture to ensure that the fourth transistor element 220 (MLED) does not operate in the triode region. As shown in FIG.3A, in various aspects the current driver circuit 300 may further include a voltage source 302 (e.g., part of the bias branch 206). In this configuration, the voltage source 302 may be coupled between the control node 228e of the fifth transistor element 222 and the control node 228d of the fourth transistor element 220. Accordingly, considering the interconnections among the transistor elements, the voltage source 302 may be coupled with the control node 228a of the first transistor element 214 and the control node 228b of the second transistor element 216.

[0074] The voltage source 302 may be configured to generate a voltage and provide the generated voltage to the control node(s) 228a, 228e of the first transistor element 214 and fifth transistor element 222. The voltage provided by the voltage source 302 may shift upward the voltage at the control node(s) 228a, 228e, thus increasing the voltage VR and alleviating the dynamic range weakness at the first node 224d (e.g., the drain) of the fourth transistor element 220. A few millivolts are sufficient to adjust VR without causing potential issues for the dynamic range at the output. The voltage source 302 may thus be configured to generate a voltage in the range from 10 mV to 100 mV, for example a voltage in the range from 30 mV to 60 mV, for example a voltage of 50 mV. Illustratively, the voltage source 302 adds a voltage contribution to the voltage across the second transistor element 216 (the second gate-source voltage) before subtracting the voltage across the fifth transistor element 222 (the fifth gate-source voltage) to obtain a higher VR.

[0075] In principle, the voltage source 302 may be realized in any suitable manner. In general, as shown in FIG.3B for the current driver circuit 350, the voltage source 302 may be or include a battery 352. A battery 352 may provide a compact and space-efficient solution to obtain (starting from the gate voltage of the second NMOS transistor 266 MD) the desired upward shifts of the voltage at the gate nodes of the first NMOS transistor 264 (Me) and fifth NMOS transistor 272 (MLS), thus increasing VR and giving more room to the drains of the second and fourth NMOS transistor 266, 270 MD and MLED that leave the triode region definitively. The implementation of the battery is easy and just needs an additional branch.

[0076] A possible implementation of the configuration discussed in relation to FIG.3A and FIG.3B (illustratively, a possible implementation of the battery) is illustrated in FIG.4A and FIG.4B, which show a current driver circuit 400, 450 adapted to ensure that the fourth transistor element 220 (the output generator MLED) is in strong saturation and to remove any potential error due to the bias current at the fifth transistor element 222 (MLS).

[0077] With respect to the current driver circuit 200 of FIG.2A, the current driver circuit 400 may further include, at the bias branch, a sixth transistor element 406 (with respective first node 424f, second node 426f, and control node 428f), a (further) bias current source 402 (e.g., a current generator), and a seventh transistor element 408 (with respective first node 424g, second node 426g, and control node 428g). These components may illustratively define the “battery section” of the circuit 400. As shown, the seventh transistor element 408 may be disposed between the bias terminal 212 and the fifth transistor element 222, e.g. the first node 424g of the seventh transistor element 408 may be coupled with the bias terminal and the second node 426g of the seventh transistor element 408 may be coupled with the first node 224e of the fifth transistor element 222 (and accordingly with the control nodes 228a, 228f of the first and fifth transistor elements 214, 222).

[0078] The seventh transistor element 408 may have a diode-connected configuration, e.g. the first node 424e and the control node 428e of the seventh transistor element 408 may be coupled with one another, so that a voltage at the first node 424e corresponds to a voltage at the control node 428e. Further, the control node 428f of the sixth transistor element 406 may be coupled with the control node 428g (and accordingly the first node 424g) of the seventh transistor element 408. The second node 426f of the sixth transistor element 406 may be coupled with the control node(s) 228b, 228d of the second and fourth transistor elements 216, 220.

[0079] The proposed configuration is meant to have the sixth and seventh transistor elements 406, 408 with mismatched voltages at their respective control nodes 428f, 428g (e.g., mismatched VGS voltages). For example, this may be achieved by providing the sixth andseventh transistor elements 406, 408 with different dimensions). In turn, the mismatch causes the voltage at the second node(s) 226a, 226e of the first and fifth transistor elements 214, 222 to rise with respect to the voltage at the control node 228b of the second transistor element 216. With reference to the implementation of the current driver circuit 450 in FIG.4B, the sixth NMOS transistor 456 (MBI) and the seventh NMOS transistor 458 (MB?) have conveniently mismatched VGS to rise Me and MLS sources with respect to MD gate. Illustratively, in the configuration of FIG.4A and FIG.4B, the added transistor elements implement the functionality of the additional voltage source (the battery) of FIG.3A.

[0080] By way of illustration, the relationship between the control node 228b (e.g., the gate) of the first transistor element 216 and the first node 224d (e.g., the drain) of the fourth transistor element 220 is altered by the difference between the voltage across the sixth transistor element 406 (e.g., the voltage between the control node 228f and the second node 226f, e.g. a sixth gatesource voltage) and the voltage across the seventh transistor element 408 (e.g., the voltage between the control node 228g and the second node 226g, e.g. a seventh gate-source voltage). Considering the configuration in FIG.4B, the voltage VR may be defined as VGS of MD + VGS of Mb2 - VGS of Mbi - VGS of MLS. By way of illustration, the configuration in FIG.4A and FIG.4B may be understood as a “first up then down” configuration, in which the voltage at the control node 228b goes up by the voltage across the sixth transistor element 406 and then down by the voltage across the seventh transistor element 408.

[0081] The mismatch between the sixth and seventh transistor elements 406, 408 may be configured to cause an increase in VR. In this regard, the sixth transistor element 406 and the seventh transistor element 408 may be configured such that the voltage across the sixth transistor element 406 (a sixth gate-source voltage) is greater than the voltage across the seventh transistor element 406 (a seventh gate-source voltage).

[0082] According to various aspects, the sixth transistor element 406 and the seventh transistor element 408 may be of the same transistor type as the second and fourth transistor elements 216, 220 (e.g., may be all NMOS), to ensure a uniform transistor behavior, e.g. even in presence of variations due to temperature or processing.

[0083] According to various aspects, the current driver circuit 400 may further include (at the bias branch) a capacitor element 410 coupled between the second node 224d of the fourth transistor element 220 and the control node 228b of the first transistor element 216. The capacitor element 410 may enhance the stability of the circuit. With reference to the implementation of the current driver circuit 450 in FIG.4B the capacitor 460 may be coupled between the drain of the fourth NMOS transistor 270 (MLED) and the gate of the second NMOStransistor 266 (MD) to bypass any pole inserted by the “battery” section. The capacitance of the capacitor element 410, 460 may be relatively small, e.g. in the range from 100 fF (femtofarad) to 100 pF (picofarad), e.g. in the range from 1 pF to 10 pF.

[0084] Turning to implementing a correction for the bias current IB, this may be achieved in various ways. In a simple configuration, the size of the fourth transistor element 220 (MLED) may be increased. As another option, as shown in FIG.4A and FIG.4B in various aspects the current driver circuit 400 may further include a further (e.g., second) bias current source 402, 452, in addition to the bias current source providing bias current IB at the bias terminal 212. Illustratively, the bias current IB at the bias terminal (e.g., generated by a respective (first) bias current source 256) may flow along a certain path in the circuit. The second bias current source 402, 452 may be configured to generate a (second) bias current to bias the sixth transistor element 406. As an optional component, shown in FIG.4A and FIG.4B, the circuit 400 may further include a third bias current source 404, 454. The third bias current source 404 may be coupled with the fifth transistor element 222, e.g. with the second node 226e of the fifth transistor element 222 (the source node of the fifth NMOS transistor 272). A further terminal of the second bias current source 402 may be coupled with a reference potential of the circuit 400. The third bias current source 404 may be configured to generate a bias current (e.g., having the same current value IB as the second bias current source 402), and may act as a sink for the current from the first bias to avoid an error in the output current IOUT. Such error may however be small, so that the third bias current source 404, 454 may be dispensed with in some scenarios.

[0085] According to various aspects, the current driver circuit 400 may thus include a bias current source coupled with the bias terminal 212 (e.g., the bias current source 256 in FIG.4B) and configured to provide the bias current IB to the bias terminal 212, and may further include a second bias current source 402 disposed in the bias branch to bias the further voltage shifting elements defined by the sixth and seventh transistor elements 406, 408. The second bias current source 402 may be configured to generate a bias current IB having the same current value as the bias current IB from the (first) bias current source coupled with the bias terminal 212. The second bias current source 402 may be further coupled with the second and fourth transistor elements 216, 220, e.g. with the respective control node 228b, 228d. A further terminal of the second bias current source 402 may be coupled with a reference potential of the circuit 400.

[0086] Considering the configuration of FIG.4A and FIG.4B a possible reason for concern may come from the biasing of the common control node 428f, 428g of the sixth and seventh transistor elements 406, 408. Illustratively, considering the implementation of FIG.4B, thecommon gate of MBI and MB2 may be more than 2 VGS above the reference potential (GND). The configuration of the current driver circuit 500, 550 in FIG.5A and FIG.5B addresses this potential concern providing an implementation of the voltage source (the battery VLS) that leads to a solution capable of safely operating at lower supply voltages.

[0087] In the configuration of FIG.5 A and FIG.5B, the sixth and seventh transistor elements 406, 408 act in combination to shift first down and then up the voltage at the control node of the second transistor element 216 (e.g., the voltage at MD gate). By way of illustration, the configuration in FIG.5 A and FIG.5B may be understood as a “first down then up” configuration, in which the voltage at the control node 228b goes down by the voltage across the seventh transistor element 408 and then up by the voltage across the sixth transistor element 406. Although more complex than the basic architecture of FIG.2A, this configuration further enhances the accuracy of the circuit.

[0088] As shown in FIG.5 A, in this configuration the sixth transistor element 406 may be in a diode-connected configuration having the control node 428f coupled with the first node 424f. Further, the control node 428f and first node 424f of the sixth transistor element 406 may be coupled with the control node 228a of the first transistor element 214, and accordingly with the first node 224e and control node 228e of the diode-connected fifth transistor element 222.

[0089] In this configuration, also the seventh transistor element 408 may be in a diode- connected configuration having the control node 428g coupled with the first node 424g. The second node 426g of the seventh transistor element 408 may be coupled with the second node 426f of the sixth transistor element 406. Further, the control node 428g and first node 424g of the seventh transistor element 408 may be coupled with the control node 228b of the second transistor element 216, and accordingly with the control node 228d of the fourth transistor element 220.

[0090] In this scenario, the current driver circuit 500 may further include (at the bias branch) a plurality of bias current sources 502-508 to implement the desired voltage shifting. In the exemplary implementation of the current driver circuit 550 the current sources are indicated as 552-558.

[0091] The current driver circuit 500 may include a first bias current source 502 configured to provide (e.g., to generate) a first bias current IA. The first bias current source 502 may be coupled with the seventh transistor element 408, e.g. at the first node 424g (and accordingly may be coupled with the control node(s) 228b, 228d, 428g of the second, fourth, seventh transistor elements 216, 220, 408). The first bias current source 502 may thus deliver the first bias current IA to the seventh transistor element 408.

[0092] The current driver circuit 500 may further include a second bias current source 504 configured to provide (e.g., to generate) a second bias current IB. The second bias current source 504 may be coupled with the seventh transistor element 408, e.g. at the second node 426g. Another terminal of the second bias current source 504 may be coupled with the second node(s) 226b, 226d of the second and fourth transistor elements 216, 220, illustratively the other terminal of the second bias current source 504 and the second node(s) 226b, 226d may all be coupled to a reference potential of the circuit 500 (e.g., to ground).

[0093] The current driver circuit 500 may further include a third bias current source 506 configured to provide (e.g., to generate) a third bias current Ic. The third bias current source 506 may be coupled with the fifth transistor element 222, e.g. at the first node 224e. Accordingly, the third bias current source 506 may be coupled with the first node 424f of the sixth transistor element 406, and with the control node(s) 228a, 228e, 428f of the first, fifth, and sixth transistor elements 214, 222, 406.

[0094] As an optional component (analogously to the third bias current source 404 of FIG.4A), the current driver circuit 500 may further include a fourth bias current source 508 configured to provide (e.g., to generate) a fourth bias current lx, to reduce a possible error on the output current. The fourth bias current source 508 may be coupled with the fifth transistor element 222, e.g. at the second node 226e. Accordingly, the fourth bias current source 508 may be coupled with the first node 224d of the fourth transistor element 220, and with the second node 226c of the third transistor element 218.

[0095] According to various aspects, the current sources 502-508 may be configured to provide predefined current values for the respective current IA, IB, IC, IX to provide a convenient biasing of the “level shifting section”. In this regard, the second bias current IB may be greater (in other words, higher) than the first bias current IA, thus ensuring sufficient bias for the sixth transistor element 406 (MB2 in FIG.5B). In a corresponding manner, the third bias current Ic may be greater than a difference between the second bias current IB and the first bias current IA, i.e. IC>(IB-IA). Illustratively, the third bias current Ic may be greater than the current through the sixth transistor element 406 (MB2). AS a further consideration, if present, the fourth bias current Ix may be equal to a difference between the sum of the first and third bias currents IA, IC and the second bias current IB, i.e. IX=IA+IC-IB. AS mentioned, the addition of the current generator IA+IC-IB ensures that the output current IOUT is not affected by any systematic contribution of the current across the level shifting section.

[0096] FIG.6 shows a system 600 including a current driver circuit 610 and a load 620 coupled with the current driver circuit 610. The current driver circuit 610 may be configured as proposedherein, e.g. the current driver circuit 610 may have any configuration discussed in relation to the current driver circuit 200, 250, 300, 350, 400, 450, 500, 550 in FIG.2A to FIG.5B. For simplicity of representation the individual components of the current driver circuit 510 are not illustrated. In general, the current driver circuit 510 may receive an input current IREF at an input terminal 602 and may deliver an output current IOUT at an output terminal 604.

[0097] In some aspects, the system 600 may further include an input current source coupled with the input terminal 602. In the exemplary configuration in FIG.6, the load 620 may be coupled with the output terminal 604, and the current driver circuit 610 may act as a current sink at the output side. In other aspects, the system 600 may include an input current sink coupled with the input terminal 602, and the current driver circuit 610 may act as a current source at the output side.

[0098] It is understood that in general the current driver circuit 610 may include additional components with respect to those described in relation to FIG.2A to FIG.5B. As exemplary components, the current driver circuit 610 may include a control circuit, one or more filters, temperature protection elements, voltage surge protection elements, a memory, and the like.

[0099] In principle, the load 620 may be any suitable device (e.g., any suitable circuit) for which a current delivery exploiting the properties of the proposed current driver circuit 610 may be beneficial, e.g. in terms of small footprint.

[0100] In a preferred configuration, the load 620 may include a light emitting device having one or more light emitting elements, e.g. a plurality of light emitting elements. For example, the load 620 may include a light emitting device having one or more light emitting diodes (LEDs), e.g. a plurality of LEDs. In this scenario, the current driver circuit 610 may be a LED driver. For example, the load 620 may include a string of LED devices connected in series with one another, or a plurality of strings of LED devices.

[0101] The light emitting elements (e.g., the LEDs) may be configured to emit light having a predefined wavelength, for example in the visible range (e.g., from about 380 nm to about 700 nm), infrared and / or near-infrared range (e.g., in the range from about 700 nm to about 5000 nm), or ultraviolet range (e.g., from about 100 nm to about 400 nm). In some aspects, the light emitting elements may be configured to emit light in different wavelength ranges. For example a first light emitting element may be configured to emit light in a first wavelength range (e.g., a first color, for example blue), a second light emitting element may be configured to emit light in a second wavelength range (e.g., a second color, for example red), and a third light emitting element may be configured to emit light in a third wavelength range (e.g., a third color, for example green), etc.

[0102] As final remarks, it is beneficial to highlight a distinction between the architecture proposed herein (e.g., the basic configuration of FIG.2A) and two popular architectures, namely the Wilson mirror 700 (FIG.7A), and the regulated cascode stage 710 (FIG.7B), which may appear similar but behave in a rather different way.

[0103] With reference to FIG.7A, it may be seen that the Wilson mirror 700 lacks the level shift present in the architecture proposed herein, thus making the Wilson approach unfit for current drivers due to this weakness in the dynamic range. Illustratively, in the Wilson mirror 700 there is no bias branch with (fifth) transistor element to provide level shifting. In the current driver circuit of the present disclosure, the additional (fifth) transistor element allows bringing the voltage at the first node of the fourth transistor element (e.g., the drain of MLED) lower, thus saving a significant amount of voltage at the output of the dynamic range.

[0104] With reference to FIG.7B, it may be seen that the regulated cascode 710 takes the driver reference current IREF from a branch that is different from the one that builds up the operational amplifier that drives the (third) transistor element at the output (MOUT). In the regulated cascode 710, the bias current Iopmay be totally uncorrelated to the output current ILED and input current IREF. This may allow adapting the performance in terms of dynamic range and large output impedance achievement. Further, the channel length for the transistor Mopmay be either very large (to increase the amplifier gain and boost the output impedance more) or even at the minimum lithographic limit (to ensure a very fast response).

[0105] However, the regulated cascode 710 does not foresee a cascode Me at the input (illustratively, the first transistor element 214), or if such transistor is present, does not foresee that such transistor is biased with a voltage taken directly from the gate of MD. In fact, this would bring the operational amplifier stage in triode and would frustrate the output impedance enhancement. Furthermore, in usual applications the current of a regulated cascode 710 has a signal superimposed. In case it is used to bias the operational amplifier, severe problem for design would follow because the stability and the correct dynamic range of the part must be ensured in a wide spread of currents. This makes the approach not convenient, if not unfeasible, and this is another reason why the op-amp current Iopis uncorrelated to the one across the output branch.

[0106] By way of illustration, the architecture proposed herein may be seen as a combination of the advantageous properties of a Wilson mirror and regulated cascode, while not suffering from the respective drawbacks.

[0107] The terms “processor”, “processing circuit”, or “control circuit” as used herein may be understood as any kind of technological entity that allows handling of data. The data may behandled according to one or more specific functions that the processor / processing circuit / control circuit may execute. Further, a processor / processing circuit / control circuit as used herein may be understood as any kind of circuit, e.g., any kind of analog or digital circuit. A processor / processing circuit / control circuit may thus be or include an analog circuit, digital circuit, mixed-signal circuit, logic circuit (e.g., a hard-wired logic circuit or a programmable logic circuit), microprocessor, Central Processing Unit (CPU), Graphics Processing Unit (GPU), Digital Signal Processor (DSP), Field Programmable Gate Array (FPGA), integrated circuit, Application Specific Integrated Circuit (ASIC), etc., or any combination thereof. It is understood that any two (or more) of the processors / processing circuits / control circuits detailed herein may be realized as a single entity with equivalent functionality or the like, and conversely that any single processor / processing circuit / control circuit detailed herein may be realized as two (or more) separate entities with equivalent functionality or the like.

[0108] The term “connected” may be used herein with respect to terminals, integrated circuit elements, devices, and the like, to mean electrically connected, which may include a direct connection or an indirect connection, wherein an indirect connection may only include additional structures in the current path that do not influence the substantial functioning of the described circuit or device. The term “electrically conductively connected” that is used herein to describe an electrical connection between one or more terminals, devices, regions, contacts, etc., may be understood as an electrically conductive connection with, for example, ohmic behavior, e.g. provided by a metal or degenerate semiconductor in absence of p-n junctions in the current path. The term “electrically conductively connected” may be also referred to as “galvanically connected”. The term “coupled” may be used herein in the same manner as the term “connected”.

[0109] The term “terminal” may be used herein to describe a location (e.g., a point) or structure of a device or of an element of the device at which a signal (e.g., an analog signal, for example a current or a voltage) may be provided and / or to which another device or element may be connected. Illustratively, a terminal may be a location or a structure that is electrically conductively connected with the device or the element. A terminal may also be referred to herein as port, pin, contact, or contact point.

[0110] The term “reference voltage” or “reference potential” may be used herein to denote a base voltage for a circuit. In some aspects, the reference voltage may be also referred to as ground (GND) voltage, ground potential, virtual ground voltage, or zero volts (0 V). In an exemplary configuration the reference voltage may be 0 V, but the aspects described herein may apply in principle to any suitable value for the reference voltage.

[0111] The word “exemplary” is used herein to mean “serving as an example, instance, or illustration”. Any embodiment or design described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments or designs.

[0112] The phrase “at least one” and “one or more” may be understood to include a numerical quantity greater than or equal to one (e.g., one, two, three, four, [...], etc.). The phrase “at least one of’ with regard to a group of elements may be used herein to mean at least one element from the group consisting of the elements. For example, the phrase “at least one of’ with regard to a group of elements may be used herein to mean a selection of: one of the listed elements, a plurality of one of the listed elements, a plurality of individual listed elements, or a plurality of a multiple of individual listed elements.

[0113] All acronyms defined in the above description additionally hold in all claims included herein.

[0114] While the invention has been particularly shown and described with reference to specific aspects, it should be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. The scope of the invention is thus indicated by the appended claims and all changes, which come within the meaning and range of equivalency of the claims, are therefore intended to be embraced.List of reference signs 216 Second transistor element218 Third transistor element220 Fourth transistor element100 Current driver222 Fifth transistor element100a Configuration of current mirror224a First node100b Configuration of current mirror224b First node102 Reference current source224c First node104 First transistor224d First node106 Second transistor224e First node108 Third transistor226a Second node110 Fourth transistor226b Second node112 Fifth transistor226c Second node114 Operational amplifier226d Second node150 Operational amplifier226e Second node150c Configuration of operational228a Control node amplifier228b Control node150d Configuration of operational228c Control node amplifier228 d Control node152c PMOS transistor228 e Control node152d PMOS transistor230 Ground terminal154c PMOS transistor250 Current driver circuit154d PMOS transistor252 Reference current source156c Tail current source256 Bias current source158c PMOS transistor258 Input terminal160c PMOS transistor260 Output terminal162c NMOS transistor262 Bias terminal162d NMOS transistor 264 First NMOS transistor164c NMOS transistor266 Second NMOS transistor164d NMOS transistor268 Third NMOS transistor166c Bias current source270 F ourth NMO S transi stor166d Bias current source272 Fifth NMOS transistor168c Bias current source280 Ground terminal168d Bias current source 300 Current driver circuit170c Output signal302 Voltage source170d Output signal 350 Current driver circuit172d NMOS transistor352 Battery174d Bias current source400 Current driver circuit200 Current driver circuit402 Current source202 Input branch404 Current source204 Output branch 406 Sixth transistor element206 Bias branch 408 Seventh transistor element208 Input terminal 410 Capacitor element210 Output terminal424f First node212 Bias terminal424g First node214 First transistor element426f Second nodeg Second node f Control node g Control node Current driver circuit Current source Current source Sixth NMOS transistor Seventh NMOS transistor CapacitorCurrent driver circuit First current source Second current source Third current source Fourth current source Current driver circuit First current source Second current source Third current source Fourth current source System Input terminal Output terminal Current driver circuit LoadWilson mirror Regulated cascode stage

Claims

Claim1. A current driver circuit (200-500), comprising: an input branch (202) comprising an input terminal (208) configured to receive an input current (IREF), a first transistor element (214) coupled with the input terminal, and a second transistor element (216) coupled with the first transistor element (214); an output branch (204) comprising an output terminal (210) configured to be coupled with a load, a third transistor element (218) coupled with the output terminal (210), and a fourth transistor element (220) coupled with the third transistor element (218); and a bias branch (206) comprising a bias terminal (212) configured to receive a bias current (IB), and a fifth transistor element (222) coupled with the bias terminal (212), wherein each transistor element (214-222) comprises a first node (224a-224e), a second node (226a-226e), and a control node (228a-228e) to allow controlling a current flow between the first node (224a-224e) and the second node (226a-226e); wherein the second transistor element (216) and the fourth transistor element (220) are configured to define a current mirror to copy the input current (IREF) from the input branch (202) as output current (IOUT) at the output branch (204), wherein the third transistor element (218) is disposed between the fourth transistor element (220) and the output terminal (210), and the control node (228c) of the third transistor element (218) is coupled with the input terminal (208) to allow a flow of current from the fourth transistor element (220) to the output terminal (210), wherein the fifth transistor element (222) is in a diode-connected configuration, and wherein the control nodes (228a, 228e) of the first transistor element (214) and fifth transistor element (222) are coupled with the bias terminal (212), and wherein the first transistor element (214) and the fifth transistor element (222) are configured to define a voltage level shift to provide a matching between a voltage at the first node (224b) of the second transistor element (214) and a voltage at the first node (224d) of the fourth transistor element (220).

2. The current driver circuit (200-500) according to claim 1, wherein the second node (226a) of the first transistor element (214) is coupled with the first node (224b) of the second transistor element (216), and wherein the second node (226e) of the fifth transistor element (222) is coupled with the first node (224d) of the fourth transistor element (220).

3. The current driver circuit (200-500) according to claim 1 or 2, wherein the first transistor element (214) and the fifth transistor element (222) are of the same transistor type; and / or wherein the second transistor element (216) and the fourth transistor element (220) are of the same transistor type.

4. The current driver circuit (200-500) according to any one of claims 1 to 3, wherein an aspect ratio of the first transistor element (214) is proportional to an aspect ratio of the fifth transistor element (222) by a proportionality factor defined as the ratio of the input current (IREF) to the bias current (IB).

5. The current driver circuit (200-500) according to any one of claims 1 to 4, further comprising a voltage source (302) coupled between the control node (228e) of the fifth transistor element (222) and the control node (228d) of the fourth transistor element (220) and configured to generate a voltage to cause an upward shift of the voltage at the control nodes (228a, 228e) of the first transistor element (214) and fifth transistor element (222).

6. The current driver circuit (200-500) according to any one of claims 1 to 4, further comprising, at the bias branch (206), a sixth transistor element (406) and a seventh transistor element (408),wherein a second node (426f) of the sixth transistor element (406) is coupled with the control nodes (228b, 228d) of the second transistor element (216) and fourth transistor element (220), wherein the seventh transistor element (408) is in a diode-connected configuration and is disposed between the bias terminal (212) and the fifth transistor element (222), and wherein the sixth transistor element (406) and the seventh transistor element (408) are mismatched to cause a voltage across the sixth transistor element (406) to be greater than a voltage across the seventh transistor element (408).

7. The current driver circuit (200-500) according to claim 6, further including a capacitor element (410) coupled between the first node (224d) of the fourth transistor element (220) and the control node (228b) of the second transistor element (216).

8. The current driver circuit (200-500) according to claim 6 or 7, further comprising a first bias current source coupled with the bias terminal (212) and configured to provide the bias current (IB) to the bias terminal (212), and further comprising a second bias current source (402) coupled with the sixth transistor element (406) and configured to generate a second bias current having a matched current value with the bias current (IB) from the first bias current source to bias the sixth transistor element (406).

9. The current driver circuit (200-500) according to any one of claims 1 to 4, further comprising, at the bias branch (206), a sixth transistor element (406) and a seventh transistor element (408), wherein the sixth transistor element (406) is in a diode-connected configuration, the second node (426f) of the sixth transistor element (406) is coupled with the second node (426g) of the seventh transistor element (408), and the control node (428f) of thesixth transistor element (406) is coupled with the control nodes (228a, 228e) of the first transistor element (214) and fifth transistor element (222); and wherein the seventh transistor element (408) is in a diode-connected configuration, and the control node (428g) of the seventh transistor element (408) is coupled with the control nodes (228b, 228d) of the second transistor element (216) and fourth transistor element (220), and wherein the sixth transistor element (406) and the seventh transistor element (408) are mismatched to cause a voltage across the sixth transistor element (406) to be greater than a voltage across the seventh transistor element (408).

10. The current driver circuit (200-500) according to claim 9, further comprising: a first bias current source (502) coupled with the first node (424g) of the seventh transistor element (408) and configured to provide a first bias current (IA); a second bias current source (504) coupled with the second node (426g) of the seventh transistor element (408) and configured to provide a second bias current (IB); and a third bias current source (506) coupled with the first node (224e) of the fifth transistor element (222) and configured to provide a third bias current (Ic).

11. The current driver circuit (200-500) according to claim 10, wherein the second bias current (IB) is greater than the first bias current (IA); and / or the third bias current (Ic) is greater than a difference between the second bias current (IB) and the first bias current (IA).

12. The current driver circuit (200-500) according to claim 11, further comprising: a fourth bias current source (508) coupled with the second node (226e) of the fifth transistor element (222) and configured to provide a fourth bias current (lx),wherein preferably the fourth bias current (lx) is equal to a difference between the sum of the first and third bias currents (IA, IC) and the second bias current (IB).

13. The current driver circuit (200-500) according to any one of claims 1 to 12, wherein at least one of the first transistor element (214) and / or second transistor element (216) is a N-channel metal-oxide semiconductor (NMOS) transistor.

14. A system (600) comprising: a current driver circuit (610) configured according to any one of claims 1 to 13; and a load (620) coupled with the current driver circuit (610) at the output terminal (604) and configured to receive the output current (IOUT) from the current driver circuit (610) as driving current.

15. The system (600) according to claim 14, wherein the load (620) comprises one or more light emitting element, wherein preferably the load (620) comprises one or more light emitting diodes (LEDs).

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