Current mirror circuit

Abstract

The present disclosure relates to a current mirror circuit (200), including: a reference terminal (202); a mirror terminal (204); an operational amplifier (208) including a first input terminal (210), a second input terminal (212), and an output terminal (214); a plurality of output branches (220) coupled between the output terminal (214) and the mirror terminal (204), wherein each output branch (220) comprises: a transistor element (222a-222n) having a first node (224a-224n), a second node (226a-226n), and a control node (228a-228n), wherein the first node (224a-224n) is coupled with the mirror terminal (204) and the control node (228a-228n) is coupled with the output terminal (214) of the operational amplifier (208); a first resistive element (230a-230n) coupled between the second node (226a-226n) of the transistor element (222a-222n) and a reference potential of the current mirror circuit (200); and a second resistive element (232a-232n) coupled between the second node (226a-226n) of the transistor element (222a-222n) and the second input terminal (212) of the operational amplifier (208), wherein the current mirror circuit (200) further includes a switch arrangement (240) configured to selectively enable or disable a coupling of the transistor element (222a-222n) of at least one output branch (220) with a virtual ground of the operational amplifier (208).

Description

CURRENT MIRROR CIRCUITTechnical Field

[0001] The present disclosure relates generally to a current mirror circuit having a plurality of output branches.Background

[0002] In general, current mirrors are an important building block in many circuit architectures. Simply put, a current mirror is a circuit configured to “mirror” (illustratively, to copy) a reference current provided as input and deliver, as output, an output current that is a mirrored version of the input current. Current mirrors offer several advantageous properties. In particular, a current mirror may have a low input impedance and a relatively high output impedance, thus acting as a more ideal current source when delivering the output current to a load. Furthermore, a current mirror may maintain the output current substantially constant even in presence of variations in the load at the output, thus ensuring a robust and stable operation. Current mirrors have various applications, for example for providing a constant bias current to an active device, for imposing a level shift to a voltage signal, or for generating complex signal waveforms (e.g., having a sawtooth profile, as an example). Thus, improvements in the capabilities of current mirrors may be of particular relevance for the further advancements of several technologies.Brief Description of the Drawings

[0003] In the drawings, like reference characters generally refer to the same parts throughout the different views. The drawings are not necessarily to scale, emphasis instead generally being placed upon illustrating the principles of the invention. In the following description, various aspects of the invention are described with reference to the following drawings, in which:FIG.1A to FIG. IE show various configurations of a current mirror circuit, in a schematic representation according to various aspects;FIG.2 A to FIG.2C show a current mirror circuit having an adapted architecture, in a schematic representation according to various aspects;FIG.2D illustrates an offset compensation in the adapted current mirror circuit, in a schematic representation according to various aspects;FIG.2E shows a possible configuration of resistive elements of the current mirror circuit, in a schematic representation according to various aspectsFIG.3 shows an exemplary realization of the current mirror circuit, in a schematic representation according to various aspects;FIG.4 shows a system including the current mirror circuit and a load coupled with the current mirror circuit, in a schematic representation according to various aspects; andFIG.5A to FIG.5C illustrate simulation results for comparing a performance of the proposed circuit architecture of a current mirror circuit with a performance of a conventional circuit architecture of a current mirror circuit.Description

[0004] The following detailed description refers to the accompanying drawings that show, by way of illustration, specific details and aspects in which the invention may be practiced. These aspects are described in sufficient detail to enable those skilled in the art to practice the invention. Other aspects may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the invention. The various aspects are not necessarily mutually exclusive, as some aspects may be combined with one or more other aspects to form new aspects.

[0005] In general, a current mirror may be understood as a circuit configured to generate a copy of an input (reference) current and deliver the copy of the current at an output terminal. Various architectures have been developed to realize a current mirror. Two relevant examples are bipolar-based and MOSFET-based current mirrors, where MOSFET stands for Metal-Oxide- Semiconductor Field-Effect Transistor. Bipolar-based current mirrors include bipolar junction transistors (BJTs), and MOSFET-based current mirrors include MOSFETs to mirror the input current. Each architecture has its own advantages and disadvantages.

[0006] In general, the basic concepts related to current mirror circuits and their operation are well known in the art. A brief description is provided herein to introduce aspects relevant for the present disclosure.

[0007] While current mirrors have several attractive properties, there are various factors that influence their operation and may negatively affect the accuracy of the current mirroring. In particular, the behavior of the transistor(s) in a current mirror may be dependent on the temperature at which the current mirror operates, thus potentially limiting the accuracy in case of temperature variations. As another example, the relationship between the input current and the output current may be affected by variations in the input current that may cause a non-linear relationship and thus a less reliable operation. Some relevant design considerations will bediscussed in relation to FIG.1A to FIG. IE, which show possible architectures of a current mirror.

[0008] In the present disclosure particular reference may be made to the use of a current mirror as driver for a light emitting diode (LED). Illustratively, particular reference may be made to the use of a current mirror as LED driver, or as part of a LED driver. This application may be of particular interest because a current mirror enables a precise control of the current delivered to the LED, thus allowing a precise control of the emitted light, e.g. in terms of color, brightness, and the like. Therefore, in the present disclosure terminology may be used that pertains to the particular context of LEDs and light emission. It is however understood that the aspects described in relation to a current mirror for delivering current to a LED may apply in a corresponding manner to other applications of a current mirror, e.g. for driving other types of circuits. For example, an output current of a current mirror may be indicated or described as ILED, but it is understood that such current may be for use in any suitable application, and may be referred simply as “output current” (IOUT).

[0009] In general, it may be challenging to design a current mirror for applications in which relatively high currents are required. This may be the case, for example, for driving light emitting diodes (LEDs), which usually require tens of milliampere (mA). In this scenario, conventional designs based on switches are impractical, because LED driving would require large switches with low impedance, thus leading to excessively complex structures.

[0010] FIG.1A to FIG.1E show various configurations lOOa-lOOe of a current mirror circuit 100, in a schematic representation. The various configurations lOOa-lOOe are collectively referred to herein as current mirror 100. In general, the current mirror 100 may include an operational amplifier and one or more transistors to mirror a reference current IREF (e.g., by a reference current source 102) and deliver a mirrored version of the reference current IREF as output current ILED. In the exemplary configurations in FIG.1A to FIG. IE the transistors are represented as NMOS transistors, where NMOS stands for N-channel Metal-Oxide Semiconductors. It is however understood that the aspects described herein may apply in a corresponding manner to other types of transistors, e.g. PMOS, BJT.

[0011] Furthermore, in the exemplary configuration in FIG.1A to FIG. IE, a reference current source 102 is illustrated to provide the reference current IREF at the input of the current mirror 100. In this configuration the current mirror 100 produces a current sink at the output. The aspects described in relation to this configuration apply in a corresponding manner to the opposite case in which a current sink is present at the input, and the current mirror 100 reflects the current behaving as a current source at the output.

[0012] FIG.1A shows a first configuration 100a of a feedback-based current mirror, which represents a popular implementation of a LED driver. As an abridged overview, the feedbackbased current mirror 100a may receive a reference current IREF (e.g., from a reference current source 102), and may be configured to mirror the reference current IREF by means of a first transistor 104 (MD) and a second transistor 106 (MLED) into the output branch as output current ILED, e.g. to bias an external LED. The current mirror 100a may further include a third transistor 108 (Me) and a fourth transistor 110 (MOUT) as cascode elements to increase the output impedance. The current mirror 100a may further include an operational amplifier 114 that further increases the output impedance, as the requirement is usually severe. The virtual ground of the operational amplifier 114 is usually taken at a voltage VR that is obtained as the difference of the saturation voltages of two transistors (e.g., two NMOS). This optimizes the output dynamic range at the output terminal (e.g., at a LED pin).

[0013] By way of illustration, in the configuration in FIG.1A, the operational amplifier 114 works as a regulated cascode to increase the output impedance. The current mirror 100a is defined by the first transistor 104 (MD) and the second transistor 106 (MLED). Illustratively, the drain current of the second transistor 106 (MLED) follows the reference current IREF. The third transistor 108 (Me) is a cascode element to maintain the voltage VR low. Illustratively, the third transistor 108 (Me) prevents the first transistor 104 (MD) to be in a triode configuration. The third transistor 108 (Me) may be seen as a shifting element to maintain the drain voltage of the first transistor 104 (MD) sufficiently low.

[0014] As shown, the current mirror 100a may further include a “bias branch” at which the current mirror 100a receives a bias current IB (e.g., from a bias current source 116), and further including a fifth transistor 112 (MCASC) that has a source terminal coupled with the source terminal of the second transistor 106 (MLED).

[0015] The solution in FIG.1 A is attractive because it allows to easily change the current at the output (ILED) by means of two alternative ways. For example, the reference current IREF may be generated by a digital to analog converter (DAC), and the output current ILED tracks the reference current IREF with a precise multiplying factor. As another example, the reference current IREF may be constant and the width of the second transistor 106 (MLED) may be varied, thus implementing a classic current DAC solution

[0016] However, the problems affecting this solution are many, depending on the application and the adopted technology option. In particular, the current mirror 100a presents drawbacks in terms of accuracy, because the first transistor 104 (MD) and the second transistor 106 (MLED) are active components, so that the offset depends mainly on an offset of the threshold voltage(s),which leads to an offset in the output current ILED with respect to the input reference current IREF. The current offset may be modeled as a voltage generator coupled with the gate terminal of the second transistor 106 (MLED).

[0017] In the configuration 100a in FIG.1 A the offset associated to MLED gate, voff MLED, is a critical source of inaccuracy. Being multiplied by the device gain (gm_MLED), it causes an error that is a function both of the temperature and the value of the output current, ILED. This frustrates the attempts for an accurate trimming, as it is carried out at a single temperature and a single value for ILED to keep the cost of production small. Illustratively, the threshold voltage of a transistor may be sensitive to variations in temperature, so that even in case the current mirror 100a is calibrated to deliver a predefined (calibrated) output current ILED, the calibration relates only to one predefined temperature, and cannot be assumed to be valid at other temperatures, thus leading to a possible “error”, illustratively a mismatch between the reference current, IREF and the output current ILED.

[0018] As a further consideration, reducing the MLED offset leads to a large channel length. This implies a proportional increase in width to keep the saturation voltage unaltered. The area increase gets very relevant. Illustratively, a possible solution consists in increasing the dimensions of the first transistor 104 (MD) and the second transistor 106 (MLED), e.g. by increasing the channel length of such transistors. However, in view of the constant trend towards miniaturization of electronic components, this approach is not attractive. Considering for example the LED context, increasing the size of the LED driver is impractical for many applications that require a small footprint of an illumination module.

[0019] Thus, the configuration 100a in FIG.1A is sensitive to temperature variations. An additional consideration is related to the linearity of the current mirror. Ideally, the relationship between the input reference current IREF and the output current ILED should remain the same independently of the current value of the input reference current IREF. For many applications the required current is not constant over time, but rather varies to adapt to the operational needs of the load. For example, considering the LED context, for emission of different colors a different current may be required, or for varying the brightness of the emitted light, as examples. Considering the configuration in FIG.1 A, the impact of the current offset may vary for different input reference currents IREF, thus leading to a less robust and less reliable operation. Illustratively, in case IREF changes, it cannot be given for granted that the voltage VR ensures MLED saturation in all cases. A cumbersome optimization work is usually necessary.

[0020] In this regard, the possibility that VR brings MLED in triode may be a function of the temperature. It follows that the output current ILED depends on the offset of the operationalamplifier 114 only in a given temperature range, introducing an unexpected large random thermal drift. Furthermore, even if the operational amplifier 114 is very fast, at turn-on a dead time is met when charging the first transistor 104 (MD) up to the threshold level. This limits the performances for pulse width modulation (PWM) applications.

[0021] In view of the considerations above, a possible approach may consist in replacing the transistor-based mirror (e.g., the NMOS mirror) with a resistor pair, as shown in the configuration 100b in FIG. IB, which includes a first resistor 118 (RD) and a second (output) resistor 120 (RLED) to replace the first transistor 104 (MD) and second transistor 106 (MLED) of the configuration 100a in FIG.1A. This configuration may provide better accuracy and area occupation, because a resistor mismatch does not introduce any temperature drift, unlike the case in FIG.1 A, but merely introduces a scaling factor. Moreover, the large size of the resistors 118, 120 (to sustain large currents) ensures that the error is usually small.

[0022] The presence of a large variety of resistive layers gives some degree of freedom to optimize the overall area. Indeed, the replacement of transistors (e.g., MOSFETs) with resistors is often the right way to save area. Furthermore, no dead time is encountered when charging the node across the first resistor (RD) once the operational amplifier 114 is fast enough.

[0023] The resistors 118, 120 thus ensure a better matching, even in presence of temperature variations, or variations in the input reference current IREF. By eliminating the active transistors (illustratively, the first transistor 104 (MD) and second transistor 106 (MLED) of FIG.1 A), and using instead a resistor 118, 120 the potential issues related to saturation, triode connection, etc. are no longer present, thus providing higher accuracy while maintaining a relatively small occupied area. The configuration 100b in FIG. IB may thus be more attractive than the configuration 100a in FIG.1A for applications that involve relatively high current. The output impedance of the configuration 100b is relatively low(er) (e.g., considering about 1 Q (1 Ohm) for the second resistor 120 RLED), but it may be compensated by suitably configuring the operational amplifier 114.

[0024] However, also the configuration in FIG. IB presents some drawbacks, for example related to the offset of the operational amplifier 114 (voff opamp) that affects now the accuracy of the output current ILED. This issue was not present in the configuration 100a of FIG.1 A, because the offset of the operational amplifier was falling on the resistance of the second transistor 106 (MLED), which is about 10 or 20 times greater than the resistance of the resistor 120 RLED (e.g., 20 compared to 1 Q). Thus, in the configuration 100b the offset of the amplifier may become a relevant source of error. The offset is divided by the second resistor 120 (RLED) to produce the error. Comparing the errors gm_MLED*voff_MLED withvoff opamp / RLED, it is apparent that in the second case the thermal drift is smaller. This makes trimming more effective in the entire temperature range. In general, the offset of an operational amplifier 114 may be dependent on the area, so that the offset may be reduced by reducing the dimensions of the operational amplifier 114 (e.g., the dimensions of transistors included in the amplifier).

[0025] As a further consideration, the configuration 100b in FIG. IB presents drawbacks for what concerns the linearity of the mirroring operation. When the input reference current IREF varies, the offset of the operational amplifier 114 causes an error that is a function of the voltage at its terminals, so that by decreasing the input reference current IREF the error increases (in proportion). Any calibration is thus no longer valid when the input reference current IREF varies.

[0026] With the above considerations in mind, there may be various strategies to vary the output current ILED. In this regard, FIG.1C shows a possible configuration 100c in which the current mirror includes a variable second (output) resistor 122. This solution is however impractical and not realistic, because the required parallel / series switches for setting the variable resistor 122 would have an unpractical size because their on-resistance should be negligible compared to the resistor one, whose range is in the order of few Ohms.

[0027] Another possible configuration 150c in FIG.1C includes a variable reference current IREF (from a variable current source 124), for example the variable reference current IREF may be set by a suitable configuration of a DAC. The configuration 150c in FIG.1C refers to the case in which the input reference current IREF varies, thus varying the voltage at the terminal of the operational amplifier 114.

[0028] As a further option, as shown in the configuration lOOd in FIG. ID, the current mirror lOOd may include an output branch split into a plurality of parallel elements, e.g. a plurality of operational amplifiers 126a, 126b (AI, ... ,AN), a plurality of output transistors 128a, 128b (MOUT i, . . . ,MOUT N), and a plurality of output resistors 130a, 130b (RLi,..., RLN). Illustratively, the current mirror lOOd includes an output branch that is split in more units, each comprising a cascode (MOUT i, . . . ,MOUT N) and an operational amplifier 126a, 126b (Ai, . . . , AN). Rather than duplicating only the resistance, the number of amplifiers is duplicated. This configuration allows implementing the trimming using switches with smaller area, but it requires the presence of multiple amplifiers connected in parallel. Each amplifier contributes with its own offset, thus affecting the linearity of the current mirroring. In this configuration lOOd, the branches in parallel may be de-selected by switching off the amplifiers 126a, 126b and shorting their outputs at a reference potential (e.g., ground, GND).

[0029] An evolution of the configuration lOOd is illustrated in FIG. IE, in which the current mirror lOOe includes a single operational amplifier 114 that is shared among all the branches, and only the cascodes are split. The single operational amplifier 114 has in parallel the series connection of cascode elements 128a, 128b and resistors 130a, 130b. In this scenario, the single operational amplifier 114 biases the gate of a first cascode 128a (MOUT i) that is connected at any configuration. All the other cascode units have the gate biased with a multiplexer between the output of the operational amplifier 114 and the reference potential (e.g., ground).

[0030] The configurations 100c, 150c, lOOd, lOOe in FIG.1C to FIG. IE present however some limitations. For example, the configuration 150c in FIG.1C may have a simple implementation, as a very conventional current DAC may be used for IREF generation. Unfortunately, the linearity is very poor in case the range of the output current ILED is large. In fact, the accuracy depends on the ratio between the drop across the resistor 118 (RD) and the offset of the operational amplifier 114. Once IREF current changes in a wide range, the resulting current multiplication is strongly variable. Therefore, trimming gets troublesome if the accuracy target is tight. For those applications where the output current ILED changes at different operating modes, it may be necessary to evaluate and store in memory more than one trimming word and this increases the production costs. From the design point of view, the problem may be mitigated by making the offset of the operational amplifier 114 as small as possible. This asks for a large area but looks the only viable approach, because increasing the drop at the resistor 118 (RD) as an alternative makes the output dynamic range too poor at large currents.

[0031] The configuration lOOd in FIG. ID may be more a conceptual than a practical solution. As a strength point, the voltage at the input of the operational amplifier 114 is fixed. Hence, rejection to the offset of the operational amplifier 126a, 126b may be expected to be uniform in the overall setting range for the output current ILED and this is beneficial for linearity. However, there are evident drawbacks because it is unpractical to use an operational amplifier 126a, 126b for each selectable branch. Furthermore, although improved, linearity is not optimal because each operational amplifier 126a, 126b introduces an offset that is uncorrelated to the others and alters the desired relationship between the current levels of the output current ILED.

[0032] The configuration lOOe in FIG. IE may be more attractive. First of all, such configuration uses one operational amplifier 114 only. Then, all the cascodes 128a, 128b drive just a portion of the output current ILED. Hence, the sum of their areas may be made equal to the one of the (single) output transistor 110 in FIG.1C. This means that the area degradation is due only to few multiplexers in a low-power path. This is definitively negligible. Moreover, like in FIG. ID, the strength point of a fixed voltage at the input of the operational amplifier 114 isensured as well. A possible weak point of this configuration lOOe may be due to the fact that only one cascode 128a belongs to the feedback loop. In this way, the offset of each cascode unit replaces the offset of each operational amplifier 126a, 126b in FIG. ID to affect linearity. Luckily, the cascodes are so large to keep the associated offset comparable, if not better, to the one of the operational amplifier 126a, 126b. Unfortunately, the transfer function of the offset to output current ILED is different. If in FIG. ID it was given by the resistor RLj only, now also the cascode 1 / gm operates as a series element. This introduces a random thermal drift that, as usual, is troublesome for trimming effectiveness.

[0033] Aspects of the present disclosure are related to an adapted architecture for a current mirror circuit including an operational amplifier and a plurality of output branches, in which the contribution of a respective transistor element of an output branch to the virtual ground of the operational amplifier may be selectively enabled or disabled, thus allowing to adjust the output current (e.g., the LED current) in a widely variable range with improved accuracy. Illustratively, the present disclosure may be based on the realization that selectively coupling a transistor element with the virtual ground of the operational amplifier, allows obtaining a correlation between the offset on the transistor elements of different output branches, thus enabling a robust and reliable offset compensation. The proposed architecture may also be extended to any other application where a current should be generated in different values with a precise ratio.

[0034] By way of illustration, the proposed architecture may be based on the realization that by selectively coupling or decoupling a plurality of transistor elements with the virtual ground of the operational amplifier, an offset compensation may be obtained which reduces (or ideally eliminates) the effect of the offset between different transistors.

[0035] According to various aspects, a current mirror circuit may include: a reference terminal configured to receive a reference current; a mirror terminal, wherein the current mirror circuit is configured to provide a copy of the reference current as output current at the mirror terminal; an operational amplifier including a first input terminal, a second input terminal, and an output terminal; a plurality of output branches coupled between the output terminal of the operational amplifier and the mirror terminal, wherein the first input terminal of the operational amplifier is coupled with the reference terminal and the output terminal of the operational amplifier is feedback coupled with the second input terminal of the operational amplifier over the plurality of output branches, wherein each output branch of the plurality of output branches includes: a transistor element having a first node, a second node, and a control node to allow controlling an electrical behavior between the first node and the second node, wherein the first node iscoupled with the mirror terminal and the control node is coupled with the output terminal of the operational amplifier; a first resistive element coupled between the second node of the transistor element and a reference potential; and a second resistive element coupled between the second node of the transistor element and the second input terminal of the operational amplifier, wherein the current mirror circuit further includes a switch arrangement configured to selectively enable or disable a coupling of the transistor element of at least one output branch with a virtual ground of the operational amplifier.

[0036] As a further aspect, the resistive elements belonging to different output branches may be suitably dimensioned to correct the offset between the transistor elements of the different output branches. Aspects of the present disclosure may thus be based on the realization that a suitable selection of the resistance values of the resistive elements belonging to different output branches allows canceling the effect of the offset between the respective transistor elements. The proposed configuration including suitably dimensioned resistive elements may thus enable a current mirroring in which the effect of the transistor offsets is mitigated or eliminated, thus enhancing the accuracy and the reproducibility of the circuit operation. In this regard, in a preferred configuration wherein the plurality of output branches may include a first output branch and a second output branch, and a ratio of a resistance value of the second resistive element to a resistance value of the first resistive element of the first output branch may be equal to the ratio of a resistance value of the second resistive element to a resistance value of the first resistive element of the second output branch. Providing the same proportionality across the branches ensures cancellation of the offset, and thus a more robust and accurate operation of the current mirror.

[0037] As mentioned, the proposed approach may be of particular relevance for implementation in an electronic circuit for driving light emitting elements, e.g. light emitting diodes. The proposed strategy allows varying the driving current to tune the light emission in a wide dynamic range, thus providing a flexible and efficient operation of a light emitting device. Thus, in the following particular reference may be made to a configuration in which a driver circuit includes the proposed current mirror circuit to deliver driving current to one or more light emitting elements. It is however understood that the application of the proposed circuit architecture are not limited to light emitting elements, and the current mirror circuit may be for use in any suitable scenario.

[0038] FIG.2A shows a current mirror circuit 200 in a schematic representation, according to various aspects. In general, the current mirror circuit 200 may include a reference terminal 202 configured to receive a reference current IREF and a mirror terminal 204 at which the currentmirror circuit 200 delivers a copy of the reference current IREF as output current IOUT. A reference terminal (e.g., the reference terminal 202) may also be referred to herein as reference input terminal, or simply as input terminal of the current mirror circuit 200. A mirror terminal (e.g., the mirror terminal 204) may also be referred to herein as mirror output terminal, or simply as output terminal of the current mirror circuit 200. A current mirror circuit (e.g., the current mirror circuit 200) may also be referred to herein as current mirror device, or simply as current mirror. According to various aspects, the current mirror circuit 200 may be an integrated circuit. Illustratively the various components of the current mirror circuit 200 may be integrated on the same substrate, e.g. on a printed circuit board (PCB) substrate.

[0039] As an exemplary configuration, the current mirror circuit 200 may include a reference current source or may be coupled with a reference current source at the reference terminal 202. Considering a current source configured to supply the reference current IREF at the reference terminal 202, the current mirror circuit 200 may act as a current sink at the output side. As an exemplary implementation, the reference current source may include a digital to analog converter. As another exemplary configuration, the current mirror circuit 200 may include a reference current sink or may be coupled with a reference current sink at the reference terminal 202. Considering a current sink configured to sink the reference current IREF at the reference terminal 202, the current mirror circuit 200 may act as a current source at the output side. The current mirror circuit 200 may further include an input resistor 206 coupled with the reference terminal 202. The input resistor 206 may be further coupled with a reference potential of the circuit 200, e.g. the input resistor 206 may be coupled between the reference terminal 202 and a ground terminal 207.

[0040] In the present disclosure particular reference may be made to the scenario in which the reference terminal 202 is coupled with a reference current source that supplies the reference current IREF, as this may be the most relevant use case scenario considering an application of the current mirror circuit 200 for driving light emission. It is however understood that the aspects described in relation to a configuration with a reference current source may apply in a corresponding manner to a configuration with a reference current sink, and vice versa.

[0041] The current mirror circuit 200 may in general be configured to mirror the reference current IREF as output current IOUT at the output terminal 204. Illustratively, the current mirror circuit 200 may replicate the reference current IREF at the output terminal 204. The configuration proposed herein and discussed in further detail below may apply to any suitable relationship between the reference current IREF and the output current IOUT. AS an example, the current mirror circuit 200 may be configured such that a current value of the output current IOUT is equal to acurrent value of the reference current IREF. AS another example, the current mirror circuit 200 may be configured such that a current value of the output current IOUT is a multiple of the current value of the reference current IREF, e.g. the output current IOUT may be two times the reference current IREF, or three times the reference current IREF, or any other suitable multiple (e.g., integer multiple). As a further example, the current mirror circuit 200 may be configured such that a current value of the output current IOUT is a fraction of the current value of the reference current IREF, e.g. the output current IOUT may be half of the reference current IREF, or one-third of the reference current IREF, or any other suitable fraction. The relationship between the reference current IREF as output current IOUT may be adapted by suitably dimensioning the components of the current mirror circuit 200.

[0042] The current mirror circuit 200 may further include an operational amplifier 208. The operational amplifier 208 may include a first input terminal 210, a second input terminal 212, and an output terminal 214. Although not shown, the operational amplifier 208 may further include a positive power supply terminal at which the operational amplifier 208 receives a supply voltage (VDD), and a negative power supply terminal at which the operational amplifier 208 receives a reference voltage (Vss). For example, the positive power supply terminal may be coupled with a supply source configured to provide the supply voltage, and the negative power supply terminal may be coupled with a reference potential (e.g., ground).

[0043] In principle, the operational amplifier 208 may have any suitable configuration. For example, the operational amplifier 208 may provide low offset thermal drift, input range including ground, and output swing from a control voltage (e.g., NMOS VGS) to supply voltage (VDD).

[0044] As shown in FIG.2A, the first input terminal 210 may be coupled with the reference terminal 202 of the current mirror circuit 200 and may thus receive the reference current IREF from the reference terminal 202. The output terminal 214 may be coupled in a feedback configuration to the second input terminal 212, over a plurality of output branches 220 described in further detail below. Illustratively, the output terminal 214 may be feedback coupled with the second input terminal 212 over (in other words, via, or through) the plurality of output branches 220.

[0045] In a preferred configuration, the first input terminal 210 may be the non-inverting terminal (+) of the operational amplifier 208, and the second input terminal 212 may be the inverting terminal (-) of the operational amplifier 208. In this scenario, the feedback from the output terminal 214 may thus be coupled with the inverting terminal to provide a negative feedback configuration. In a preferred configuration, the current mirror circuit 200 may includea single operational amplifier 208, thus providing a space-efficient configuration. For the proposed circuit architecture, the operational amplifier 208 may have any suitable configuration, as generally known in the art.

[0046] As generally known in the art, an operational amplifier 208 may be a differential amplifier that amplifies and delivers at the output terminal 214 the voltage difference between a (first) voltage at the first input terminal 210 and a (second) voltage at the second input terminal 212. The differential voltage at the input (VD=V+-V) may be amplified by the gain (A) of the operational amplifier 208 to deliver an amplified output voltage.

[0047] A relevant concept in the context of operational amplifiers is the so-called “virtual ground”. As known, an operational amplifier may operate in a linear region in which the output voltage and the differential voltage at the input have a linear relationship, or in a saturation region in which a saturation occurs. Considering the usual high gain of an operational amplifier, saturation may occur even for relatively small differential voltage inputs. Only as a numerical example, considering an open loop gain A=106and a saturation voltage of 10 V (Volts), the operational amplifier may reach the saturation region for a differential voltage input of 10 pV. To operate in the linear region, the output voltage at the output terminal of the operational amplifier should be less than the saturation voltage, and thus the differential voltage input should be less than the corresponding differential voltage that would bring the operational amplifier in saturation.

[0048] Considering the numerical example above, the differential voltage input VD=V+-V should be less than 10 pV, and may thus be considered substantially negligible. Thus, the voltage difference between the non-inverting terminal and the inverting terminal of the operational amplifier may be considered substantially zero. There is thus a “virtual short” between the non-inverting terminal and the inverting terminal of the operational amplifier (e.g., between the first input terminal 210 and the second input terminal 212), so that the non-inverting terminal and the inverting terminal may be considered to be at the same potential. The voltage appearing at one of the non-inverting terminal or the inverting terminal will appear also at the other one of the non-inverting terminal or the inverting terminal. If, for example, the non-inverting terminal is grounded, then V+is at the reference potential (e.g., 0 V), and by virtue of the virtual ground also the inverting terminal is grounded and V' is at the reference potential.

[0049] According to various aspects, the current mirror circuit 200 may further include a plurality of output branches 220 coupled between the output terminal 214 of the operational amplifier and the mirror terminal 204. Illustratively, the current mirror circuit 200 may transferthe input reference current IREF as output current IOUT at the mirror terminal 204 over the plurality of output branches 220. In the exemplary configuration in FIG.2A, the current mirror circuit 200 may include a first output branch 220-1, a second output branch 220-2, and an N-th output branch 220-N. In general, the current mirror circuit 200 may include any suitable number of output branches 220, e.g. two, three, four, five, or more than five. In a preferred configuration, that provides the offset calibration with a compact arrangement while enabling an adjustment of the output current IOUT, the current mirror circuit 200 may include exactly two output branches 220-1, 220-2. The output branches 220-1, 220-2, 220-N are collectively referred to herein as output branches 220.

[0050] Each output branch 220 may include a respective transistor element 222a, 222b, 222n having a first node 224a, 224b, 224n, a second node 226a, 226b, 226n, and a control node 228a, 228b, 228n. In principle, any suitable type of transistor may be used. In a preferred configuration, the transistor element 222a, 222b, 222n may include a MOSFET, in particular a NMOS transistor. In other aspects, the transistor element 222a, 222b, 222n may include a PMOS transistor, or another type of transistor such as a BJT. In general, the control node 228a, 228b, 228n may allow controlling an electrical behavior between the first node 224a, 224b, 224n and the second node 226a, 226b, 226n, e.g. a current flow between the first node 224a, 224b, 224n and the second node 226a, 226b, 226n.

[0051] Considering the configuration in which the transistor element 222a, 222b, 222n includes an NMOS transistor, the control node 228a, 228b, 228b may be a gate node, the first node 224a, 224b, 224n may be a drain node, and the second node 226a, 226b, 226n may be a source node. The NMOS transistor may include a gate structure defining a channel region (in a bulk material) between the source node and the drain node. In this case, the gate node may allow controlling a drain current from the source node towards the drain node.

[0052] Considering, as another example, the configuration in which the transistor element 222a, 222b, 222n includes a BJT, the control node 228a, 228b, 228b may be a base node, the first node 224a, 224b, 224n may be a collector node, and the second node 226a, 226b, 226n may be an emitter node. It is understood that also other configurations with inverted arrangement of the source / drain node or collector / emitter node may be provided, depending on the type of transistor used. In general, the transistor elements 222a, 222b, 222n in different output branches 220 are of the same type. However, in principle the proposed architecture makes it possible to have transistor elements 222a, 222b, 222n in different output branches 220 that are of different types (e.g., the transistor element 222a may be of a first transistor type, e.g.a NMOS, and the transistor element 222b may be of a second (different) transistor type, e.g. a B JT, as an example). This design flexibility is not present in conventional circuit configurations.

[0053] As shown in FIG.2A, the first node 224a, 224b, 224n of the transistor element(s) 222a, 222b, 222n may be coupled with the mirror terminal 204 of the current mirror circuit 200. The current flowing from a transistor element 222a, 222b, 222n (e.g., the drain current) may thus contribute to the output current IOUT. Illustratively, the first node 224a, 224b, 224n of the transistor element(s) 222a, 222b, 222n may be coupled with an electrically conductive path leading to the mirror terminal 204, such that a sum of the currents from the transistor element(s) 222a, 222b, 222n defines the output current IOUT.

[0054] The control node 228a, 228b, 228n of the transistor element(s) 222a, 222b, 222n may be coupled with the output terminal 214 of the operational amplifier 208. The output voltage of the operational amplifier 208 may thus be delivered to the control node 228a, 228b, 228n as control voltage (e.g., as gate voltage) to control the current flow between the first node 224a, 224b, 224n and the second node 226a, 226b, 226n.

[0055] An output branch 220 may further include a (first) resistive element 230a, 230b, 230n coupled between the second node 226a, 226b, 226n of the transistor element 222a, 222b, 222n and a reference potential for the circuit 200. Illustratively, a (first) electrically conductive path may couple a reference potential (e.g., a ground terminal 207) with (each of) the second node 226a, 226b, 226n of the transistor element(s) 222a, 222b, 222n, and a respective (first) resistive element 230a, 230b, 230n may be disposed along the electrically conductive path for each output branch 220. The ground terminal 207 may be a single terminal, or may include a plurality of ground terminals each at the reference potential for the circuit 200. A “ground terminal” may also be referred to herein as “reference source”. Illustratively, the first resistive element 230a, 230b, 23 On may be coupled between the second node 226a, 226b, 226n and a source of reference potential (reference voltage, e.g. ground voltage) of the current mirror circuit 200. The (first) resistive element 230a, 230b, 230n may thus be coupled between the second node 226a, 226b, 226n and the reference source coupled to the input resistor 206. Illustratively, a (first) terminal of the input resistor 206 may be coupled with the reference terminal 202, and another (second) terminal of the input resistor 206 may be coupled with the first resistive elements 230a, 230b, 230n of the output branches 220.

[0056] An output branch 220 may further include a (second) resistive element 232a, 232b, 232n coupled between the second node 226a, 226b, 226n of the transistor element 222a, 222b, 222n and the second input terminal 212 of the operational amplifier 208. Illustratively, a (second) electrically conductive path may couple the second input terminal 212 with (each of) the secondnode 226a, 226b, 226n of the transistor element(s) 222a, 222b, 222n, and a respective (second) resistive element 232a, 232b, 232n may be disposed along the electrically conductive path for each output branch 220.

[0057] In a simple configuration, the resistive elements 230a, 230b, 230n, 232a, 232b, 232n may be realized as resistor, e.g. a respective first resistor and second resistor for each output branch 220. In other aspects, a resistive element 230a, 230b, 230n, 232a, 232b, 232n may be realized as a transistor, as will be described in further detail below in relation to FIG.2E. In general, a resistive element 230a, 230b, 230n, 232a, 232b, 232n may be any suitable component or plurality of components configured to provide a resistance along the electrically conductive path between the respective transistor element 222a, 222b, 222n and the operational amplifier 208.

[0058] In general, the second resistive element 232a, 232b, 232n may have a greater resistance compared to the first resistive element 230a, 230b, 230n. For example, a (second) resistance of the second resistive element 232a, 232b, 232n may be at least two times greater than a (first) resistance of the first resistive element 230a, 230b, 230n, for example at least five times greater, for example at least ten times greater, for example at least one hundred times greater. A greater resistance of the second resistive element 232a, 232b, 232n ensures that the current flowing through the second resistive element(s) 232a, 232b, 232n is negligible compared to the current flowing through the first resistive element(s) 230a, 230b, 230n so that substantially no current is taken away from the load. Only as a numerical example, the second resistive element 232a, 232b, 232n may have a resistance in the range from 10 (1 to 500 (1, for example in the range from 20 (1 to 200 (1, for example in the range from 50 (1 to 100 (1.

[0059] According to the proposed architecture, the current mirror circuit 200 may further include a switch arrangement 240 configured to selectively enable or disable a coupling of the transistor element 222a, 222b, 222n of at least one output branch 220 with the virtual ground of the operational amplifier 208. The switch arrangement 240 may thus be configured to selectively couple or decouple a transistor element 222a, 222b, 222n with the operational amplifier 208, e.g. with the second input terminal 212 of the operational amplifier 208. As will be described in further detail below, the switch arrangement 240 may be configured to selectively connect (close) or disconnect (open) the electrically conductive path between a transistor element 222a, 222b, 222n and the operational amplifier 208. In this regard, the switch arrangement 240 may be configured to selectively couple or decouple the control node 228a, 228b, 228n (e.g., the gate) of a transistor element 222a, 222b, 222n with the output terminal 214 of the operational amplifier 208, and may be configured to configured to selectively coupleor decouple the second node 226a, 226b, 226n (e.g., the source) of a transistor element 222a, 222b, 222n with the second input terminal 212 of the operational amplifier 208 (see also FIG.2C).

[0060] In the proposed configuration, the switch arrangement 240 allows selecting which output branches 220 contribute to the output current IOUT, and more importantly allows selecting which output branches 220 contribute to the virtual ground of the operational amplifier 208. This configuration enables an offset compensation, thus improving the linearity of the current mirroring. Assuming for example that the transistor element 222a of the first output branch 220-1 is coupled to the virtual ground, a further coupling of the transistor element 222b of the second output branch 220-2 will cause the virtual ground of the operational amplifier 208 to vary the voltage at the control node 228a of the transistor element 222a of the first output branch 220-1 to compensate an offset (if present) between the transistor elements 222a, 222b.

[0061] Illustratively, introducing in the current mirror circuit 200 the possibility for each of the output branches 220 (and the respective transistor element 222a, 222b, 222n and second resistor 232a, 232b, 232n) via a switch arrangement 240 to influence the virtual ground of the operational amplifier 208, introduces a correlation between the offset of the respective transistor elements 222a, 222b, 222n, thus enabling an offset compensation.

[0062] The proposed architecture provides thus two useful features. The output current IOUT (e.g., a LED current ILED) becomes insensitive to the offsets of the transistor elements 222a, 222b, 222n (illustratively, the cascode elements). Furthermore, a large linearity is achieved, as the ratios between the obtained values for the output current IOUT almost perfectly match the ideal case.

[0063] According to various aspects, as shown for the configuration 200b in FIG.2B, the current mirror circuit 200 may further include a control circuit 250 configured to control the switch arrangement 240. Illustratively, the control circuit 250 may be configured to select which output branches 220 contribute to the output current IOUT and virtual ground of the operational amplifier 208, and may control the switch arrangement 240 to selectively couple such output branches 220 to the operational amplifier 208. The control circuit 250 may thus control the switch arrangement 240 to selectively couple one or more of the transistor elements 222a, 222b, 222n with the operational amplifier 208 and to selectively decouple one or more other transistor elements 222a, 222b, 222n from the operational amplifier 208.

[0064] As an exemplary configuration, the control circuit 250 may control the switch arrangement 240 based on a target current level of the output current IOUT. For example, the control circuit 250 may receive an indication from a device coupled at the output terminal 204that a target current level is required to carry out a certain operation, and the control circuit 250 may control the switch arrangement 240 to couple transistor elements 222a, 222b, 222n with the operational amplifier 208 such that the combined current from the coupled transistor elements 222a, 222b, 222n delivers the target current level of the output current IOUT. AS another example, the control circuit 250 may control the switch arrangement 240 to deliver the target current level based on predefined information (e.g., stored in a memory of the current mirror circuit 200, not shown).

[0065] For example, a memory of the current mirror circuit 200 may store a plurality of trimming instructions (also referred to herein as trimming words), each corresponding to a respective target current level of the output current IOUT. Each trimming instruction may define a corresponding configuration for coupling / decoupling the transistor elements 222a, 222b, 222n with / from the operational amplifier 208 to define the respective target current level. The current mirror circuit 200 may retrieve a trimming instruction corresponding to the target current level to be provided and may control the switch arrangement 240 using the retrieved trimming instruction.

[0066] In principle, there may be various possible configurations for the switch arrangement 240. A preferred configuration 200c is illustrated in FIG.2C, which illustrates a realization of the switch arrangement 240 that has been found to provide an efficient implementation of the proposed architecture. According to various aspects, the switch arrangement 240 may include a plurality of switch elements, each associated with a respective output branch 220. In particular, the switch arrangement 240 may include a respective first switch element 242b, 242n and second switch element 244b, 244n associated with an output branch 220. As an exemplary realization, a switch element 242b, 242n, 244b, 244n may be or include a transistor (e.g., a MOSFET, a BJT, and the like). A “switch element” may also be referred to herein as “selection switch”.

[0067] The first switch element 242b, 242n may be configured (e.g., operable) to selectively couple or decouple the control node 228b, 228n of the respective transistor element 222b, 222n with the output terminal 214 of the operational amplifier 208. Illustratively, the first switch element 242b, 242n associated with an output branch 220 may be configured to selectively connect or disconnect the electrically conductive path between the respective transistor element 222b, 222n and the output terminal 214. For example, the first switch element 242b, 242n associated with an output branch 220 may be disposed between the control node 228b, 228n and the output terminal 214.

[0068] The second switch element 244b, 244n may be configured (e.g., operable) to selectively couple or decouple the second node 226b, 226n of the respective transistor element 222b, 222n with the second input terminal 212 of the operational amplifier 208. Illustratively, the second switch element 244b, 244n associated with an output branch 220 may be configured to selectively connect or disconnect the electrically conductive path between the respective transistor element 222b, 222n and the second input terminal 212. For example, the second switch element 244b, 244n associated with an output branch 220 may be disposed between the second node 226b, 226n and the second resistor element 232b, 232n.

[0069] According to various aspects, the first switch element 242b, 242n and the second switch element 244b, 244n associated with an output branch 220 may be controlled simultaneously such that the switch elements 242b, 242n, 244b, 244n are in the same state (e.g., both open or both closed). Stated in a different fashion, the pair of switch elements associated with the same output branch 220 may be in the same state. With reference to FIG.2C, the switch elements 242b and 244b corresponding to the second output branch 220-2 may be in the same state with respect to one another (e.g., both open or both closed), and the switch elements 242n and 244n corresponding to the N-th output branch 220-N may be in the same state with respect to one another (e.g., both open or both closed). The pair of switch elements belonging to different output branches 220 may be in the same state or in different states depending on the desired offset compensation and contribution to the output current IOUT. AS an example, with reference to FIG.2C, the switch elements 242b and 244b corresponding to the second output branch 220-2 may be both closed to connect the transistor element 222b to the virtual ground, and the switch elements 242n and 244n corresponding to the N-th output branch 220-N may be both open to disconnect the transistor element 222n from the virtual ground, or vice versa. As another example, with reference to FIG.2C, the switch elements 242b and 244b corresponding to the second output branch 220-2 and the switch elements 242n and 244n corresponding to the N-th output branch 220-N may all be closed to connect the transistor elements 222b, 222n to the virtual ground, or the switch elements 242b and 244b and the switch elements 242n and 244n may all be open to disconnect the transistor elements 222b, 222n from the virtual ground. For example, the control circuit 250 may be configured to deliver a control signal to the first switch element 242b, 242n of an output branch 220-2, 220-N to couple (or decouple) the transistor element 222b, 222n with the operational amplifier 208, and to deliver the same type of control signal to the second switch element 244b, 244n of that output branch 220-2, 220-N. For example, a trimming instruction used by the control circuit 250 may include the same type ofcontrol signal for each switch element 242b, 242n, 244b, 244n corresponding to a certain output branch 220.

[0070] In a preferred configuration, as shown in FIG.2C, at least one output branch 220-1 may have a non-switchable coupling with the operational amplifier 208. This configuration may define a “base level” for the output current IOUT, and in general a “default configuration” for the current mirror circuit 200, without the need to introduce and control additional switch elements. Thus, in some aspects, the transistor element 222a of at least one output branch 220-1 may have a non-switchable coupling with the operational amplifier 208, e.g. the control node 228a may have a non-switchable coupling with the output terminal 214, and the second node 226a may have a non-switchable coupling with the second input terminal 212. The at least one output branch 220-1 (illustratively, the corresponding transistor element 222a) may thus have a non-switchable coupling with the virtual ground of the amplifier 208.

[0071] The term “non-switchable coupling” may illustratively describe an uninterrupted connection between two entities, e.g. between the control node 228a and the output terminal 214 and / or between the second node 226a and the second input terminal 212. For example, the term “non-switchable coupling” may describe an ohmic contact between the two entities. In general, the term “non-switchable coupling” may describe an electrically conductive path between two entities that is free of a switchable element to open / close the path.

[0072] In the configuration in FIG.2C, the first output branch 220-1 may have the non-switchable coupling with the operational amplifier 208, e.g. the output branch 220 disposed closest to the operational amplifier 208 may have the uninterrupted coupling with the operational amplifier 208. It is however understood that in principle also another output branch 220 (e.g., the N-th output branch 220-N disposed farthest away from the operational amplifier 208, or an intermediate output branch 220 at an intermediate location) may have the non-switchable coupling with the operational amplifier 208. It is also understood that more than one output branch 220 may have the non-switchable coupling with the operational amplifier 208, while still having at least one other output branch 220 that may be selectively coupled / decoupled with the virtual ground of the operational amplifier 208.

[0073] According to various aspects, in addition to the selective coupling / decoupling of the transistor elements with the virtual ground of the operational amplifier 208, the resistive elements 230a, 230b, 230n, 232a, 232b, 232n may be dimensioned to correct the offset between different transistor elements 222a, 222b, 222n, as will be illustrated with reference to FIG.2D.

[0074] To better illustrate the effect of the proposed architecture, FIG.2D shows an exemplary configuration 200d including two output branches, e.g. including a transistor element 222a,222b MOUT i, MOUT 2 (e.g., a NMOS transistor), a first resistive element 230a RLI, 230b, RL2 and a second resistive element 232a RMI, 232b RM2. It is however understood that the aspects discussed in relation to FIG.2D may be extended in a corresponding manner to a configuration with more than two output branches.

[0075] FIG.2D illustrates why the offset at the control node of the second output branch 220-2 (i.e., an output branch that may be selectively coupled / decoupled with the virtual ground of the operational amplifier 208) is made ineffective by the proposed circuit design. The offset is represented in FIG.2D as a voltage source coupled with the control node of the transistor element 222b of the second output branch 220-2. The offsets of the first transistor element 222a MOUT i and second transistor element 222b MOUT 2 may be compensated by suitably dimensioning the first resistive element 230a RLI, 230b, RL2 and second resistive element 232a RMI, 232b RM2. Due to the offset, the voltage V 1 at the second node of the first transistor element 222a MOUT 1 may be different from the voltage V2 at the second node of the second transistor element 222b MOUT 2.

[0076] Applying the superposition of effects, as the system is assumed linear, the offset of the operational amplifier 208 may be assumed to be zero. To illustrate the effect achieved by the proposed architecture, let’s assume first that only the first output branch 220-1 contributes to the output current IOUT (e.g., the switch elements associated with the second output branch 220-2 are not active). In this case the output current IOUT may be expressed as VREF / RLI, where VREF=IREF*RD, with RD being the resistance of the input resistor 206.

[0077] Next, the transistor element 222b of the second output branch 220-2 is selected (by activating the corresponding switch elements). In this scenario, the offset at the control node of the second transistor element 222b MOUT 2 (e.g., at its gate) causes the second node of the second transistor element 222b MOUT 2 (e.g., its source) to shift an amount V2 from the virtual ground VG of the operational amplifier 208.

[0078] As mentioned above, the second resistor element 232a RMI of the first output branch 220-1 may be permanently connected, like the first transistor element 222a MOUT 1, whereas the second resistor element 232b RM2 of the second output branch 220-2 may be activated by the switch arrangement 240 (e.g., by the corresponding series switch 244b). When activated, the second resistive elements 232a RMI, 232b RM2 share a common connection at the virtual ground of the operational amplifier 208. In addition, the other terminal of the second resistor element 232a RMI is driven by the feedback loop that comprises the operational amplifier 208 itself. It follows that the combination of the second resistive elements 232a RMI, 232b RM2 and the operational amplifier 208 makes an inverting amplifier. This forces the second node of thefirst transistor element 222a MOUT i (e.g., its source) source to deviate from the ideal virtual ground of an amount Vi = -(RMI / RM2)*V2. It is however understood that the aspects discussed in relation to FIG.2D may apply also to the scenario in which all the output branches 220 have a switchable coupling with the amplifier 208.

[0079] Turning now to the output current IOUT, the contributions across the first transistor element 222a MOUT i and the second transistor element 222b MOUT 2 may be calculated. Neglecting the currents through the second resistive elements 232a RMI, 232b RM2 (as they are assumed much larger than the first resistive elements 230a RLI, 230b RL2, and the offset small enough) it results(1) IMOUT I = [VG-V2*(RMI / RM2)] / RLI(2) IMOUT_2 = [VG+V2] / RL2 thus leading to a value of the output current of(3) IOUT = IMOUT I + IMOUT_2 = [VG-V2*(RMI / RM2)] / RLI + [VG+V2] / RL2 == VG*(1 / RLI+1 / RL2) + V2*(RM2 / RL2-RM1 / RL1) / RM2

[0080] It follows that making the resistance value of the second resistor elements 232a RMI, 232b RM2 proportional to the resistance value of the first resistor elements 230a RLI, 230b RL2 cancels any dependence on V2, and the output current IOUT is exclusively due to the virtual ground and the parallel of RLI and RL2, as it should ideally be.

[0081] Thus, according to various aspects, a ratio of the resistance value of the second resistive element 232a to the resistance value of the first resistive element 230a of a first output branch 220-1 (e.g., the branch without a switchable coupling to the virtual ground), may be equal to the ratio of the resistance value of the second resistive element 232b to the resistance value of the first resistive element 230b of a second output branch 220-2 (e.g., a branch with a switchable coupling to the virtual ground). This ratio may provide that when both branches are coupled, the output current may be adjusted without suffering from the offset between the transistor elements 222a, 222b.

[0082] Stated in a different fashion, the resistance values of the resistive elements belonging to different output branches may be dimensioned such that subtracting the ratio of the resistance values of the resistive elements belonging to one output branch 220 from the ratio of the resistance values of the resistive elements belonging to another output branch 220 provides as a result zero (or substantially zero). For example, the resistance value of the second resistive element 232a of one output branch 220-1 may be greater than the resistance value of the first resistive element 230a of that output branch 220-1 by the same factor according to which thesecond resistive element 232b of another output branch 220-2 is greater than the resistance value of the first resistive element 230b of that other output branch 220-1.

[0083] Such ratio may be extended to a scenario with three (or more) output branches 220 considering a linear superposition of effects. Considering for example two output branches 220 in parallel which are both selected (as in FIG.2D) and assuming that a third output branch is added, the demonstration above indicates that the two branches in parallel give no offset. Moreover, their equivalent circuit is made by a single cascode (whose size is the sum of Mout i and Mout 2) a single resistance to the reference potential (given by the parallel of the resistors 230a and 230b) and a single resistance that couples the cascode (e.g., its source) to the input terminal 212 (e.g., the negative input) of the operational amplifier 208 (as it is given by the parallel of resistors 232a and 232b, its value is proportional to the resistors 230b and 230a in parallel). It follows that once the third element is connected the same demonstration above, applied to the equivalent circuit, shows that also in this case the associated offset is not harmful once the recommended relationship between resistor values is respected. This procedure may be made recursive, and three element in parallel may be considered as a single element so that adding the fourth no error arises, and so on.

[0084] Stated in a different fashion, a ratio of the resistance value of the first resistive element 230a of the first output branch 220-1 to the resistance value of the first resistive element 230b of the second output branch 220-2 may be equal to the ratio of the resistance value of the second resistive element 232a of the first output branch 220-1 to the resistance value of the second resistive element 232b of the second output branch 220-2. In this regard it is worth noting that the layer implementing the second resistive elements 232a, 232b RMJ may also be different with respect to the layer implementing the first resistive elements 230a, 230b RLJ. What is relevant is that the ratios between Rij / RLk and RMJ / RM match. This offers a degree of freedom in making RMJ large enough without spending in area. Furthermore, in a preferred configuration, the second resistive elements 232a, 232b RMJ may be implemented directly by the selection switches (see FIG.2E).

[0085] Thus, in the proposed architecture, the second transistor element 222b enters in the definition of the virtual ground of the operational amplifier, thus coupling the voltage at the second transistor element 222b with the virtual ground over the second resistive element 232b. Compared to conventional designs, in the proposed architecture the (second) cascode element 222b is brought in the feedback loop, thus allowing the regulation to correct a possible mismatch. The error due to the offset between the transistor elements 222a, 222b is canceled, thus improving the linearity of the current mirroring. A mismatch between the resistiveelements may still be present, but it may have a substantially negligible influence on the linearity of the circuit operation. The second resistive elements 232a, 232b allow a regulation providing error voltages that in combination have an effect on the output current IOUT that provides an error that is substantially zero.

[0086] By way of illustration, in the proposed configuration the (second) selection switches 244b, 244n may couple the second resistive element(s) 232b, 232n RMJ between the second node (e.g., source node) of each cascode element 222b, 222n and the input of the operational amplifier 208. The (second) selection switches 244b, 244n may share the same command Sj that turns the associated cascode on (illustratively, the same command as for the first selection switches 242b, 242n of the corresponding output branch). The value of the second resistive element(s) 232a, 232b, 232n RMJ may be selected to be proportional to the value of the first resistive element(s) 230a, 230b, 230n RLJ that loads the cascode. In addition, due to the very small value of RLJ, it may be possible to make the proportionality factor quite large.

[0087] It is possible to give a very intuitive view of the proposed architecture. Once an offset from the cascode affects the drop across the associated first resistive element 230b (the resistor RL2), the inverting operational amplifier built with the second resistive elements 232a, 232b (RMI and RM2) produces an error at the second node (e.g., the source) of the other cascode which has opposite sign and is proportional to the value of the associated first resistive element 230a (the resistor RLI). In this way, the errors affecting the generated currents will be equal in module and opposed in sign so that they will cancel each other when summed to give the output current IOUT. The above description can be extended to a larger number of selected devices by applying the superposition of the effects.

[0088] The proposed approach makes trimming very effective. It is sufficient to trim the value of the reference current IREF or input resistor 206 (RD) regardless of the value selected for the output current IOUT. This feature was not guaranteed by the considered solutions shown in FIG.1A to FIG. IE. Simulations (see FIG.5A to FIG.5C) report a degradation from the ideal condition once RMJ starts getting comparable with RLJ (the current through them can no longer be neglected like in the previous case). However, values in the order of a few hundreds Ohm for RMJ are already effective in practical implementations so that no degradation in loop stability or area occupation would come from the proposed solution.

[0089] As mentioned above, in a simple configuration the resistive elements 230a, 230b, 23 On, 232a, 232b, 232n may be realized simply as resistors. In some aspects, however, a more advanced configuration may be provided in which a switch element is implemented as second resistive element 232a, 232b, 232n. In this configuration, the functionality of providing aresistance and allowing a selective coupling / decoupling of the output branch may thus be combined in a single component, thus allowing to implement the proposed scheme in a more compact manner.

[0090] According to various aspects, the second resistive element 232a, 232b, 232n of at least one output branch 220, e.g. of each output branch 220 (as shown in FIG.2E), for example of each output branch 220-2, 220-N that has a switchable coupling with the operational amplifier 208, may be or include a switch element. In this configuration, the switch element acting as resistive element may be considered part of the switch arrangement 240. For example, a second switch element 244b, 244n may be configured (e.g., dimensioned) to act as second resistive element along the electrically conductive path between the second node 226b, 226n of the respective transistor element 222b, 222n and the second input terminal 212 of the operational amplifier 208. A switch element acting as resistive element may also be referred to herein as “resistive switch element” or “resistive selection switch”. The “resistive switch element” may thus be configured to selectively enable or disable a coupling of the second node 226b, 226n of the respective transistor element 222b, 222n with the second input terminal 212 of the operational amplifier 208, while also providing a sufficient resistance value for the proposed approach.

[0091] In a preferred configuration 200e, as shown in FIG.2E, the switch element 246a, 246b, 246n acting as (second) resistive element 232b, 232n may be realized by a further transistor element, e.g. a MOSFET (in particular a NMOS transistor), or any other suitable type of transistor (e.g., BJT). The switch element (e.g., the transistor) may thus be configured (e.g., dimensioned) to provide a greater resistance compared to the respective first resistive element 230b, 230n of the output branch 220-2, 220-N. A MOSFET (e.g., NMOS) may be a preferred configuration as it intrinsically provides a suitable resistance.

[0092] The configuration 200e in FIG.2E is illustrated with NMOS transistors as transistor elements 222a, 222b, 222n and as resistive switch elements 246b, 246n, it is however understood that the aspects described in relation to FIG.2E apply in a corresponding manner to a configuration with different types of transistors. Furthermore, the configuration 200e in FIG.2E may include three output branches (the N-th output branch 220-N may be a third branch), but it is understood that the aspects described in relation to FIG.2E apply in a corresponding manner to a configuration with more than three branches.

[0093] In a simple configuration, considering the configuration of the switch arrangement 240 including first and second switch elements 242b, 242n, 244b, 244n, and considering the case in which the second switch element(s) 244b, 244n are further implemented as (second) resistiveelements, the first switch elements 242b, 242n and the “resistive” second switch element(s) 244b, 244n may be realized by the same type of transistor (e.g., both MOSFETs, for example both NMOS). In other aspects, to provide a flexible tailoring of the circuit properties, the first switch elements 242b, 242n and the “resistive” second switch element(s) 244b, 244n may be realized by different types of transistors.

[0094] By way of illustration, in the arrangement of FIG.2C, a switch element 244b, 244n and a resistive element 232b, 232n are disposed in series to one another. Using a (second) switch element 244b, 244n having an associated resistance value suitable for the proposed architecture allows saving space and costs. According to various aspects, having the discussion in relation to FIG.2D in mind, the resistive (second) switch elements 244b, 244n belonging to different output branches may be configured to provide resistance values that ensure the offset cancellation.

[0095] Considering for example the first output branch 220-1 having the first resistive element 230a and a resistive second switch element 246a (e.g., NMOS), as shown in FIG.2E, and the second output branch 220-2 having the first resistive element 230b and a resistive second switch element 246b (e.g., a further NMOS), the following relationship may be provided. A ratio of the resistance value of the resistive second switch element 246a to the resistance value of the first resistive element 230a of the first output branch 220-1 (e.g., the branch without a switchable coupling to the virtual ground), may be equal to the ratio of the resistance value of the resistive second switch element 246b to the resistance value of the first resistive element 230b of a second output branch 220-2 (e.g., a branch with a switchable coupling to the virtual ground). This ratio may provide that when both branches are coupled, the output current may be adjusted without suffering from the offset between the transistor elements, as discussed above.

[0096] Stated in a different fashion, a ratio of the resistance value of the first resistive element 230a of the first output branch 220-1 to the resistance value of the first resistive element 230b of the second output branch 220-2 may be equal to the ratio of the resistance value of the resistive second switch element 246a of the first output branch 220-1 to the resistance value of the resistive second switch element 246b of the second output branch 220-2. In this regard it is worth noting that also the configuration may be provided, in which one branch (e.g., the first output branch 220-1) has the second resistive element implemented as a resistor and another branch (e.g., the second output branch 220-2) has the second resistive element implemented as a resistive switch element.

[0097] Thus, the second resistive elements (RMJ) may be directly implemented via selection switches. Considering a transistor, making the width (W) small enough and the length (L) sufficiently large ensures a suitable resistance value. Only as a numerical example, a transistor used as resistive switch element may have a length (L) in the range from 5 pm to 50 pm, for example in the range from 10 pm to 20 pm, and a width (W) in the range from 0.5 pm to 5 pm, for example in the range from 1 pm to 2 pm. Illustratively, the product W_Mswj*RLj may be kept constant (where W_Mswj is the width of the “j” resistive switch element and RLJ is the resistance of the corresponding first resistive element), keeping L equal for all of the switches. The width W_Mswmay thus be inversely proportional to the switch resistance RLJ.

[0098] According to various aspects, as shown in FIG.2E, the switch arrangement 240 may further include a (respective) third switch element 248b, 248n associated with at least one output branch 220, e.g. with each output branch 220, for example each output branch 220-2, 220-N that has a switchable coupling with the operational amplifier 208. The presence of third switch element(s) 248b, 248n is shown in the configuration 200e (e.g., in combination with resistive second switch elements), but it is understood that third switch element(s) 248b, 248n may be introduced even in absence of resistive second switch elements.

[0099] A third switch element(s) 248b, 248n may be configured to selectively couple or decouple the control node 228b, 228n of the transistor element 222b, 222n of the corresponding output branch 220 with a reference potential (e.g., with ground). In various aspects, the third switch element(s) 248b, 248n may have a behavior complementary to the behavior of the corresponding first switch element 242b, 242n, so that when the third switch element(s) 248b, 248n is active the first switch element 242b, 242n is inactive, and vice versa.

[0100] Illustratively, in this configuration the current mirror circuit 200 may further include a respective electrically conductive path between the control node 228b, 228n of the transistor elements 222b, 222n and the reference potential (e.g., the ground terminal 207), and the third switch element(s) 248b, 248n may be configured (e.g., operable) to connect or disconnect such electrically conductive path. The control circuit 250 may thus be configured to control the first switch element(s) 242b, 242n using a first control signal and the corresponding third switch element(s) 248b, 248n using a second control signal, and the second control signal may instruct a complementary operation compared to the first control signal. This configuration may provide a safe turn-off, in which the complementary selection switches 248b, 248n connect to the reference potential (e.g., ground) the control nodes of the de-selected cascode elements.

[0101] FIG.3 shows a current mirror circuit 300 in a schematic representation, according to various aspects. The current mirror circuit 300 may be an exemplary realization of the currentmirror circuit 200, e.g. with an exemplary number of output branches, an exemplary realization of transistor elements, etc. It is understood that the aspects discussed in relation to the current mirror circuit 200 apply in a corresponding manner to the current mirror circuit 300, and vice versa.

[0102] The current mirror circuit 300 may include a reference terminal 302 to receive a reference current IREF, and an input resistor 306 (RD) coupled with the reference terminal 302. The current mirror circuit 300 may further include a mirror terminal 304 at which the current mirror circuit 300 delivers a copy of the reference current IREF as output current ILED. The current mirror circuit 300 may further include an operational amplifier 308 (A) with a non-inverting terminal 310, an inverting terminal 312, and an output terminal 314.

[0103] The current mirror circuit 300 may further include three output branches. The first output branch may be directly (and non-switchable) coupled with the operational amplifier 308 and may include a first NMOS transistor 322a (MOUT i), a first resistive element 330a (RLI), and a second resistive element 332a (RMI). The second and third output branches may have a switchable coupling with the operational amplifier 308 and may include a respective NMOS transistor 322b, 322c (MOUT 2, MOUT 3), a respective first resistive element 330b, 330c (RL2, RLS), and a respective second resistive element 332b, 332c (RM2, RMS).

[0104] The current mirror circuit 300 may further include switch elements 342b, 342c, 344b, 344c (selection switches) to couple or decouple the second and / or third branch with the virtual ground of the operational amplifier. For example, the current mirror circuit 300 may include switch elements 342b, 344b associated with the second branch and controlled simultaneously, and may further include switch elements 342c, 344c associated with the third branch and controlled simultaneously (e.g., separately from the switch elements 342b, 344b associated with the second branch).

[0105] FIG.4 shows a system 400 including a current mirror circuit 410 and a load 420 coupled with the current mirror circuit 410. The current mirror circuit 410 may be configured as proposed herein, e.g. the current mirror circuit 410 may have any configuration discussed in relation to the current mirror circuit 200, 300 in FIG.2A to FIG.3. For simplicity of representation the individual components of the current mirror circuit 410 are not illustrated. In general, the current mirror circuit 410 may receive a reference current IREF at a reference terminal 402 and may deliver a copy of the reference current IREF as output current IOUT at a mirror terminal 404.

[0106] In some aspects, the system 400 may further include a reference current source coupled with the reference terminal 402. In the exemplary configuration in FIG.4, the load 420 may becoupled with the mirror terminal 404, and the current mirror circuit 410 may act as a current sink at the output side. In other aspects, the system 400 may include a reference current sink coupled with the reference terminal 402, and the current mirror circuit 410 may act as a current source at the output side.

[0107] In principle, the load 420 may be any suitable device (e.g., any suitable circuit) for which a current delivery exploiting the properties of the proposed current mirror circuit 410 may be beneficial, e.g. in terms of linearity and temperature drift.

[0108] In a preferred configuration, the load 420 may include a light emitting device having one or more light emitting elements, e.g. a plurality of light emitting elements. For example, the load 420 may include a light emitting device having one or more light emitting diodes (LEDs), e.g. a plurality of LEDs. In this scenario, the current mirror circuit 410 may be part of a driver circuit, e.g. of a LED driver. A light emitting device may have varying current requirements, e.g. to change color, to change intensity of the emitted light, and the like, and the proposed current mirror may allow adjusting the delivered output current IOUT with improved linearity and without suffering from offsets between different transistors, as discussed above.

[0109] The light emitting elements (e.g., the LEDs) may be configured to emit light having a predefined wavelength, for example in the visible range (e.g., from about 380 nm to about 700 nm), infrared and / or near-infrared range (e.g., in the range from about 700 nm to about 5000 nm), or ultraviolet range (e.g., from about 100 nm to about 400 nm). In some aspects, the light emitting elements may be configured to emit light in different wavelength ranges. For example a first light emitting element may be configured to emit light in a first wavelength range (e.g., a first color, for example blue), a second light emitting element may be configured to emit light in a second wavelength range (e.g., a second color, for example red), and a third light emitting element may be configured to emit light in a third wavelength range (e.g., a third color, for example green), etc.

[0110] As an example, considering the scenario in which the load 420 includes a plurality of light emitting elements, e.g. a plurality of LEDs, the control circuit 250 of the current mirror circuit 200, 410 may be configured to cause an activation of a number of output branches 220 (by controlling the switch arrangement to couple the corresponding transistor to the operational amplifier) as a function of a number and / or a type of light emitting elements that emit light (or should emit light). For example, the control circuit 250 may control the switch arrangement as a function of a color to be emitted, or of a light intensity to be emitted, e.g. to increase / decrease the output current IOUT accordingly by selecting more or less branches.

[0111] FIG.5A to FIG.5C illustrate graphs 500a, 500b, 500c showing results from simulations to compare the performance of the conventional configurations of the current mirror 150c in FIG.1C (506a, 506b) and FIG. IE (504a, 504b, 504c) with the performance of the proposed architecture (502a, 502b, 502c). The target refers to a practical application, where the output current of the current mirror varies in a range from 3 mA to 45 mA, so that a ratio 15 results. Regarding the dynamic range, the drop across the resistors does not exceed 200 mV and the saturation voltage of the cascodes is around 300 mV. Finally, the offset of the operational amplifier is made sufficiently small by choosing a large input transistor pair (W7L = 300 / 4) and a large channel length for the active load (20 pm). As it has already been evidenced, this parameter is not affecting the solution in FIG. IE and the proposed architecture but it has been tailored with an area trade-off not to degrade excessively the solution in FIG.1C.

[0112] The first histogram 500a takes into account the ratio between the maximum and the minimum current set across the load (e.g., the LED). Ideally it should result equal to 15. It looks immediate to verify that, despite the acceptable performance achieved by the solution of FIG. IE represented by the data points 504a (1% error at 6 sigma), the proposed architecture (data points 502a) offers, with a minimum cost, the almost perfect cancellation of any resulting error. On the contrary, the solution proposed in FIG.1C (data points 506a) suffers of a deviation that exceed 15% at 6 sigma. This means that the (already remarkable) area of the input stage of the operational amplifier would need a dramatic increase for the configuration of FIG.1C. Further analyses shows that, even when considering intermediate values of the generated current, the ratio is not affected by any spread with the proposed architecture.

[0113] As a next step, the current at the maximum level, 45 mA, is reported, as the input common mode is the same for the three configurations, a more uniform performance may be expected and this is confirmed by the graph 500b in FIG.5B. However, the solution of FIG. IE (data points 504b) appreciably performs worse, suffering a spread that is 35% larger. The reason why is clear because, unlike the other two solutions, only the smallest section of the output branch operates inside the regulation loop while the errors from the other cascodes cannot be corrected. Leaving the cascode outside the regulation loop introduces thus an additional error. Of course, the result of the circuit in FIG. IE depends on how many and which output branches out of the loop are activated or not.

[0114] Finally, the thermal drift of the resulting current is monitored (graph 500c in FIG.5C). The method is purely heuristic, as only the current difference between min and max temperature is evaluated. The comparison is limited between the configuration of FIG. IE (data points 504c) and the proposed architecture (data points 502c).

[0115] Moving from the configuration of FIG. IE to the proposed current mirror provides another winning point, as the influence from the cascode gm causes an additional thermal drift which adds to the one due to the offset of the operational amplifier (it gets nearly 3 times bigger). In addition, the simulation proves that in case of ideal operational amplifier (i.e. no offset) the error is null when the proposed architecture is adopted, while it is only slightly reduced with the configuration of FIG. IE. This means that, despite the reported one looks acceptable (drift as large as 0.3% for the configuration of FIG. IE at 6 sigma), different specifications (higher ratio between Imax and Imin, drop across Rl, area demands) or technology (offset of a NMOS transistor) might degrade at risky levels only the configuration of FIG. IE, not the proposed architecture.

[0116] The following examples pertain to aspects of the present disclosure.

[0117] Example 1 is a current mirror circuit including: a reference terminal configured to receive a reference current; a mirror terminal, wherein the current mirror circuit is configured to provide a copy of the reference current as output current at the mirror terminal; an operational amplifier including a first input terminal, a second input terminal, and an output terminal; a plurality of output branches coupled between the output terminal of the operational amplifier and the mirror terminal, wherein the first input terminal of the operational amplifier is coupled with the reference terminal and the output terminal of the operational amplifier is feedback coupled with the second input terminal of the operational amplifier over the plurality of output branches, wherein each output branch of the plurality of output branches includes: a transistor element having a first node, a second node, and a control node to allow controlling an electrical behavior between the first node and the second node, wherein the first node is coupled with the mirror terminal and the control node is coupled with the output terminal of the operational amplifier; a first resistive element coupled between the second node of the transistor element and a reference potential of the current mirror circuit; and a second resistive element coupled between the second node of the transistor element and the second input terminal of the operational amplifier, wherein the current mirror circuit further comprises a switch arrangement configured to selectively enable or disable a coupling of the transistor element of at least one output branch with a virtual ground of the operational amplifier.

[0118] In Example 2, the current mirror circuit according to example 1 may optionally further include that the switch arrangement includes a first switch element associated with the at least one output branch and configured to selectively couple or decouple the control node of the transistor element of the at least one branch with the output terminal of the operational amplifier.

[0119] In Example 3, the current mirror circuit according to example 1 or 2 may optionally further include that the switch arrangement includes a second switch element associated with the at least one output branch and configured to selectively couple or decouple the second node of the transistor element of the at least one branch with the second input terminal of the operational amplifier.

[0120] In Example 4, the current mirror circuit according to any one of examples 1 to 3 may optionally further include that the transistor element of at least one output branch has a non-switchable coupling with the virtual ground of the operational amplifier.

[0121] In Example 5, the current mirror circuit according to any one of examples 1 to 4 may optionally further include that the plurality of output branches includes a first output branch and a second output branch, wherein a ratio of a resistance value of the second resistive element to a resistance value of the first resistive element of the first output branch is equal to the ratio of a resistance value of the second resistive element to a resistance value of the first resistive element of the second output branch.

[0122] In Example 6, the current mirror circuit according to example 5 may optionally further include that the transistor element of the first output branch has a non-switchable coupling with the virtual ground of the operational amplifier; and that the transistor element of the second output branch has a switchable coupling with the virtual ground of the operational amplifier.

[0123] In Example 7, the current mirror circuit according to any one of examples 1 to 6 may optionally further include that a resistance value of the second resistive element is greater than a resistance value of the first resistive element.

[0124] In Example 8, the current mirror circuit according to any one of examples 1 to 7 may optionally further include a control circuit configured to control the switch arrangement to selectively enable or disable the coupling of the transistor element of the at least one output branch with the virtual ground of the operational amplifier.

[0125] In Example 9, the current mirror circuit according to any one of examples 1 to 8 may optionally further include that the second resistive element of the at least one output branch is realized by a switch element configured to selectively enable or disable a coupling of the second node of the respective transistor element with the second input terminal of the operational amplifier.

[0126] In Example 10, the current mirror circuit according to example 9 may optionally further include that the switch element is configured to provide a resistance having a resistance value greater than a resistance value of the first resistive element of the at least one output branch.

[0127] In Example 11, the current mirror circuit according to example 9 or 10 may optionally further include that the switch element is or comprises a Metal-Oxide-Semiconductor-Field- Effect-T ransi stor .

[0128] In Example 12, the current mirror circuit according to any one of examples 1 to 11 may optionally further include that the switch arrangement further includes a third switch element associated with the at least one output branch and configured to selectively couple or decouple the control node of the transistor element of the at least one output branch with a reference potential.

[0129] In Example 13, the current mirror circuit according to example 12 may optionally further include that the third switch element has a complementary behavior with respect to the first switch element associated with the at least one output branch.

[0130] Example 14 is a system including: a current mirror circuit configured according to any one of examples 1 to 13; and a load coupled with the current mirror circuit at the mirror terminal and configured to receive the output current from the current mirror circuit as driving current.

[0131] In Example 15, the system according to example 14 may optionally further include that the load includes one or more light emitting elements (e.g., LEDs).

[0132] The terms “processor”, “processing circuit”, or “control circuit” as used herein may be understood as any kind of technological entity that allows handling of data. The data may be handled according to one or more specific functions that the processor / processing circuit / control circuit may execute. Further, a processor / processing circuit / control circuit as used herein may be understood as any kind of circuit, e.g., any kind of analog or digital circuit. A processor / processing circuit / control circuit may thus be or include an analog circuit, digital circuit, mixed-signal circuit, logic circuit (e.g., a hard-wired logic circuit or a programmable logic circuit), microprocessor, Central Processing Unit (CPU), Graphics Processing Unit (GPU), Digital Signal Processor (DSP), Field Programmable Gate Array (FPGA), integrated circuit, Application Specific Integrated Circuit (ASIC), etc., or any combination thereof. It is understood that any two (or more) of the processors / processing circuits / control circuits detailed herein may be realized as a single entity with equivalent functionality or the like, and conversely that any single processor / processing circuit / control circuit detailed herein may be realized as two (or more) separate entities with equivalent functionality or the like.

[0133] The term “connected” may be used herein with respect to terminals, integrated circuit elements, devices, and the like, to mean electrically connected, which may include a direct connection or an indirect connection, wherein an indirect connection may only include additional structures in the current path that do not influence the substantial functioning of thedescribed circuit or device. The term “electrically conductively connected” that is used herein to describe an electrical connection between one or more terminals, devices, regions, contacts, etc., may be understood as an electrically conductive connection with, for example, ohmic behavior, e.g. provided by a metal or degenerate semiconductor in absence of p-n junctions in the current path. The term “electrically conductively connected” may be also referred to as “galvanically connected”. The term “coupled” may be used herein in the same manner as the term “connected”.

[0134] The term “terminal” may be used herein to describe a location (e.g., a point) or structure of a device or of an element of the device at which a signal (e.g., an analog signal, for example a current or a voltage) may be provided and / or to which another device or element may be connected. Illustratively, a terminal may be a location or a structure that is electrically conductively connected with the device or the element. A terminal may also be referred to herein as port, pin, contact, or contact point.

[0135] The term “reference voltage” or “reference potential” may be used herein to denote a base voltage for a circuit. In some aspects, the reference voltage may be also referred to as ground (GND) voltage, ground potential, virtual ground voltage, or zero volts (0 V). In an exemplary configuration the reference voltage may be 0 V, but the aspects described herein may apply in principle to any suitable value for the reference voltage.

[0136] The word “exemplary” is used herein to mean “serving as an example, instance, or illustration”. Any embodiment or design described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments or designs.

[0137] The phrase “at least one” and “one or more” may be understood to include a numerical quantity greater than or equal to one (e.g., one, two, three, four, [...], etc.). The phrase “at least one of’ with regard to a group of elements may be used herein to mean at least one element from the group consisting of the elements. For example, the phrase “at least one of’ with regard to a group of elements may be used herein to mean a selection of: one of the listed elements, a plurality of one of the listed elements, a plurality of individual listed elements, or a plurality of a multiple of individual listed elements.

[0138] All acronyms defined in the above description additionally hold in all claims included herein.

[0139] While the invention has been particularly shown and described with reference to specific aspects, it should be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. The scope of the invention is thus indicated by the appendedclaims and all changes, which come within the meaning and range of equivalency of the claims, are therefore intended to be embraced.List of reference signs 220-N N-th output branch222a Transistor element222b Transistor element100 Current mirror circuit222n Transistor element100a Configuration of current mirror224a First node100b Configuration of current mirror224b First node100c Configuration of current mirror224n First node lOOd Configuration of current mirror226a Second node lOOe Configuration of current mirror226b Second node102 Reference current source226n Second node104 First transistor228a Control node106 Second transistor228b Control node108 Third transistor228n Control node110 Fourth transistor230a First resistive element112 Fifth transistor230b First resistive element114 Operational amplifier230n First resistive element116 Bias current source232a Second resistive element118 First resistor232b Second resistive element120 Output resistor232n Second resistive element122 Variable resistor240 Switch arrangement124 Variable current source242b First switch element126a Operational amplifier242n First switch element126b Operational amplifier244b Second switch element128a Output transistor244n Second switch element128b Output transistor246a Resistive switch element130a Output resistor246b Resistive switch element130b Output re si stor246n Resistive switch element132 Switching arrangement248b Third switch element150c Configuration of current mirror248n Third switch element 200 Current mirror circuit250 Control circuit200b Configuration300 Current mirror circuit200c Configuration302 Reference terminal200d Configuration304 Mirror terminal200e Configuration306 Input resistor202 Reference terminal308 Operational amplifier204 Mirror terminal310 Non-inverting terminal206 Input resistor312 Inverting terminal207 Ground terminal314 Output terminal208 Operational amplifier322a First NMOS210 First input terminal322b Second NMOS212 Second input terminal322c Third NMOS214 Output terminal330a First resistive element220 Output branches330b First resistive element220-1 First output branch330c First resistive element220-2 Second output branch332a Second resistive elementb Second resistive element c Second resistive element b First switch element c First switch element b Second switch element c Second switch element System Reference terminal Mirror terminal Current mirror circuit Load a Graph b Graph c Graph a Data points for the proposed current mirror b Data points for the proposed current mirror c Data points for the proposed current mirror a Data points for current mirror of FIG IE b Data points for current mirror of FIG IE c Data points for current mirror of FIG IE a Data points for current mirror of FIG.1C b Data points for current mirror of FIG.1C

Claims

Claim1. A current mirror circuit (200), comprising: a reference terminal (202) configured to receive a reference current; a mirror terminal (204), wherein the current mirror circuit (200) is configured to provide a copy of the reference current as output current at the mirror terminal (204); an operational amplifier (208) including a first input terminal (210), a second input terminal (212), and an output terminal (214); a plurality of output branches (220) coupled between the output terminal (214) of the operational amplifier and the mirror terminal (204), wherein the first input terminal (210) of the operational amplifier (208) is coupled with the reference terminal (202) and the output terminal (214) of the operational amplifier (208) is feedback coupled with the second input terminal (212) of the operational amplifier (208) over the plurality of output branches (220), wherein each output branch (220) of the plurality of output branches (220) comprises: a transistor element (222a-222n) having a first node (224a-224n), a second node (226a-226n), and a control node (228a-228n) to allow controlling an electrical behavior between the first node (224a-224n) and the second node (226a-226n), wherein the first node (224a-224n) is coupled with the mirror terminal (204) and the control node (228a-228n) is coupled with the output terminal (214) of the operational amplifier (208); a first resistive element (230a-230n) coupled between the second node (226a-226n) of the transistor element (222a-222n) and a reference potential of the current mirror circuit (200); and a second resistive element (232a-232n) coupled between the second node (226a-226n) of the transistor element (222a-222n) and the second input terminal (212) of the operational amplifier (208), wherein the current mirror circuit (200) further comprises a switch arrangement (240) configured to selectively enable or disable a coupling of the transistor element(222a-222n) of at least one output branch (220) with a virtual ground of the operational amplifier (208), wherein the plurality of output branches (220) comprises a first output branch (220-1) and a second output branch (220-2), wherein a ratio of a resistance value of the second resistive element (232a) to a resistance value of the first resistive element (230a) of the first output branch (220-1) is equal to the ratio of a resistance value of the second resistive element (232b) to a resistance value of the first resistive element (230b) of the second output branch (220-2).

2. The current mirror circuit (200) according to claim 1, wherein the switch arrangement (240) comprises a first switch element (242b, 242n) associated with the at least one output branch (220) and configured to selectively couple or decouple the control node (228b, 228n) of the transistor element (222b, 222n) of the at least one branch (220) with the output terminal (214) of the operational amplifier (208).

3. The current mirror circuit (200) according to claim 1 or 2, wherein the switch arrangement (240) comprises a second switch element (244b, 244n) associated with the at least one output branch (220) and configured to selectively couple or decouple the second node (226b, 226n) of the transistor element (222b, 222n) of the at least one branch (220) with the second input terminal (212) of the operational amplifier (208).

4. The current mirror circuit (200) according to any one of claims 1 to 3, wherein the transistor element (222a) of at least one output branch (220-1) has a non-switchable coupling with the virtual ground of the operational amplifier (208).

5. The current mirror circuit (200) according to any one of claims 1 to 4,wherein the transistor element (222a) of the first output branch (220-1) has a non-switchable coupling with the virtual ground of the operational amplifier (208); and wherein the transistor element (222b) of the second output branch (220-2) has a switchable coupling with the virtual ground of the operational amplifier (208).

6. The current mirror circuit (200) according to any one of claims 1 to 5, wherein a resistance value of the second resistive element (232a-232n) is greater than a resistance value of the first resistive element (230a-230n).

7. The current mirror circuit (200) according to any one of claims 1 to 6, further comprising: a control circuit (250) configured to control the switch arrangement (240) to selectively enable or disable the coupling of the transistor element (222b, 222n) of the at least one output branch (220) with the virtual ground of the operational amplifier (208).

8. The current mirror circuit (200) according to any one of claims 1 to 7, wherein the second resistive element (232a-232n) of the at least one output branch (220) is realized by a switch element (246a-246n) configured to selectively enable or disable a coupling of the second node (226a-226n) of the respective transistor element (222a-222n) with the second input terminal (212) of the operational amplifier (208).

9. The current mirror circuit (200) according to claim 8, wherein the switch element (246a-246n) is configured to provide a resistance having a resistance value greater than a resistance value of the first resistive element (230a-230n) of the at least one output branch (220).

10. The current mirror circuit (200) according to claim 8 or 9,wherein the switch element (246a-246n) is or comprises a Metal-Oxide- Semiconductor-Field-Effect-Transistor.

11. The current mirror circuit (200) according to any one of claims 1 to 10, wherein the second resistive element (232a) of the first output branch (220-1) is realized by a switch element (246a) configured to selectively enable or disable a coupling of the second node (226a) of the respective transistor element (222a) with the second input terminal (212) of the operational amplifier (208), wherein the second resistive element (232b) of the second output branch (220-2) is realized by a switch element (246b) configured to selectively enable or disable a coupling of the second node (226b) of the respective transistor element (222b) with the second input terminal (212) of the operational amplifier (208), and wherein a ratio of the resistance value of the switch element (246a) to the resistance value of the first resistive element (230a) of the first output branch (220-1) is equal to the ratio of the resistance value of the switch element (246b) to the resistance value of the first resistive element (230b) of the second output branch (220-2).

12. The current mirror circuit (200) according to any one of claims 1 to 11, wherein the switch arrangement (240) further comprises a third switch element (248b, 248n) associated with the at least one output branch (220) and configured to selectively couple or decouple the control node (228b, 228n) of the transistor element (222b, 222n) of the at least one output branch (220) with a reference potential.

13. The current mirror circuit (200) according to claim 12 when dependent on claim 2, wherein the third switch element (248b, 248n) has a complementary behavior compared to the first switch element (242b, 242n) associated with the at least one output branch (220).

14. A system (400) comprising:a current mirror circuit (410) configured according to any one of claims 1 to 13; and a load (420) coupled with the current mirror circuit ( 10) at the mirror terminal (404) and configured to receive the output current from the current mirror circuit (410) as driving current.

15. The system (400) according to claim 14, wherein the load (420) comprises one or more light emitting elements.

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