Method and system for controlling a quantum device

Abstract

A signal generator is disclosed for generating analog signals for controlling a quantum device. The signal generator comprises a memory system that is configured to store a plurality of sequences of digital samples. The plurality of sequences comprises a first sequence and a second sequence. Each sequence out of the plurality of sequences represents an analog signal for controlling the quantum device. The signal generator also comprises a digital sample stream generator for generating a digital sample stream based on sequences of digital samples obtained from the memory system. The signal generator further comprises a digital-to-analog converter, DAC, for converting the digital sample stream into analog signals represented by the sequences of digital samples obtained from the memory system. The DAC is configured to operate at a clock frequency fDAC. The memory system comprises an auxiliary memory that is configured to store, of each sequence out of the plurality of sequences, a part of the sequence comprising the first digital sample of the sequence. The memory system comprises a main memory that is configured to store, of each sequence out of the plurality of sequences, a further part of the sequence comprising the last digital sample of the sequence.

Description

[0001] Method and system for controlling a quantum device

[0002] FIELD OF THE INVENTION

[0003] This disclosure relates to a signal generator for generating analog signals for controlling a quantum device, in particular to such signal generator comprising a main memory and an auxiliary memory. This disclosure further relates to a corresponding method for generating analog signals for controlling a quantum device.

[0004] BACKGROUND

[0005] Quantum experiments require a classical control system to control a quantum device. This control system is in its core a digital system but requires digital-to-analog (DAC) conversion to create control pulses. The control pulse-shapes are stored in digital memory connected to a Digital to Analog Converter (DAC) capable of converting the digital pulse shape into an analog pulse. To handle the stringent speed and accuracy requirements, the control system is typically implemented using a digital circuit such as a programmable gate array (FPGAs) or a complex programmable logic device (CPLD) that connects the DAC to an on-board Block RAM memory or an external SDRAM memory chip.

[0006] Most pulses are very short (tens of nanoseconds), have high-frequency content and therefore require high-speed DACs, e.g. 1 Giga samples per second (GSPS), to generate them. Often however, these short pulses need to be interleaved with much slower pulses (in the millisecond range). For example, Watson et al, described in their article a programmable two-qubit quantum device in silicon, Nature 555, p. 633-637 (2018) an example of controlling a programmable two spin-qubit processor. Electronics coupled to the qubits include programmable arbitrary waveform generators (AWGs) that can generate pulse sequences for initializing and manipulating qubits to perform certain operations and read-out electronics to measure the result of the operations. The control signals include both long pulses in the order of (tens of) milliseconds for initialization and read-out while the actual algorithm, the manipulation of the qubits, only includes pulses that are typically 10-100 nanoseconds.

[0007] Although the operations represented a very simple algorithm for only two qubits, the electronics needed to generate the pulse sequences and to readout the response of the qubits in response to the operations are very complex, non-scalable and inflexible. The pulse sequences are constructed in advance and stored as a whole in a relatively large memory. The disadvantage of such approach is that it only allows repetitive execution of the same sequences. Execution of operations that are for example conditional to the state of the quantum device so that the controller can dynamically adjust a pulse sequence is not possible as it requires a fast response of the control electronics to the readout of the quantum device.

[0008] CoIm et al described in their article {Hardware for dynamic quantum computing, Review of Scientific Instruments 88, 104703 (2017)} a pulse sequence generator for dynamic control of superconducting qubits that is capable of generating a sequence of short pulses on the fly. To enable dynamic construction of an arbitrary pulse sequence, the generator has access to a large number of digital pulse signals of different shapes that are stored in an SDRAM memory that is external to the FPGA. During execution, a digital pulse signal is loaded from the SDRAM to a fast-onboard FPGA block RAM that serves as a cache before the digital pulse signal is fed to a high-speed DAC to generate a desired signal shape. A caching strategy is used to prefetch a set of digital pulse shapes from the SDRAM and store it in the cache, while another set of digital pulse shapes in the cache is fed to the DAC.

[0009] A disadvantage of this technology is that difficulties may arise if the fast-onboard FPGA block RAM operates at a lower clock frequency than the high speed DAC(s) that is / are used to generate the analog control signals. If this is the case, then it may become impossible to, in all circumstances, dynamically generate analog signals that are immediately subsequent to each other.

[0010] Hence, there is a need in the art for a method and system that enable to dynamically generate analog control signals for controlling a quantum device, wherein the analog control signals directly follow each other, even though the memory and DAC operate at different clock frequencies.

[0011] SUMMARY

[0012] One aspect of this disclosure relates to a signal generator for generating analog signals for controlling a quantum device. The signal generator comprises a memory system that is configured to store a plurality of sequences of digital samples. The plurality of sequences comprises a first sequence and a second sequence. Each sequence out of the plurality of sequences represents an analog signal for controlling the quantum device. The signal generator also comprises a digital sample stream generator for generating a digital sample stream based on sequences of digital samples obtained from the memory system. The signal generator further comprises a digital-to-analog converter, DAC, for converting the digital sample stream into analog signals represented by the sequences of digital samples obtained from the memory system. The DAC is configured to operate at a clock frequency fDAc- The memory system comprises an auxiliary memory that is configured to store, of each sequence out of the plurality of sequences, a part of the sequence comprising the first digital sample of the sequence. The memory system comprises a main memory that is configured to store, of each sequence out of the plurality of sequences, a further part of the sequence comprising the last digital sample of the sequence. The main memory is configured to operate at a clock frequency fmain that is lower than the clock frequency fDAc and is configured to provide at most M digital samples per clock cycle to the digital sample stream generator, M being an integer number. The auxiliary memory is configured to operate at a clock frequency faUx that is lower than the clock frequency fDAc and is configured to provide at most N digital samples per clock cycle to the digital sample stream generator, N being an integer number. The digital sample stream generator is configured to, during a single clock cycle of the main memory, retrieve at most M digital samples from the main memory and at most N digital samples from the auxiliary memory. The retrieved M digital samples comprise a digital sample, preferably the last digital sample, of the first sequence and the retrieved N digital samples comprise the first digital sample of the second sequence.

[0013] One aspect of this disclosure relates to a method, preferably a computer-implemented method, for generating analog signals for controlling a quantum device. The method comprises a memory system storing a plurality of sequences of digital samples. The plurality of sequences comprises a first sequence and a second sequence. Each sequence out of the plurality of sequences represents an analog signal for controlling the quantum device. The step of the memory system storing the plurality of sequences comprises:

[0014] - an auxiliary memory of the memory system storing, of each sequence out of the plurality of sequences, a part of the sequence comprising the first digital sample of the sequence, and

[0015] - a main memory of the memory system storing, of each sequence out of the plurality of sequences, a further part of the sequence comprising the last digital sample of the sequence.

[0016] The method further comprises a digital sample stream generator obtaining digital samples from the memory system. This step comprises:

[0017] - the main memory providing at most M digital samples per clock cycle to the digital sample stream generator, M being an integer number, wherein the main memory operates at a clock frequency fmain, and

[0018] - the auxiliary memory providing at most N digital samples per clock cycle to the digital sample stream generator, N being an integer number, wherein the auxiliary memory operates at a clock frequency faux.

[0019] The method further comprises the digital sample stream generator generating a digital sample stream based on sequences of digital samples obtained from the memory system. The method also comprises a digital-to-analog converter, DAC, converting the digital sample stream into analog signals represented by the sequences of digital samples obtained from the memory system. The DAC operates at a clock frequency fDAc that is higher than the clock frequency fmain and higher than the clock frequency faux. The method further comprises, during a single clock cycle of the main memory, the digital sample stream generator retrieving at most M digital samples from the main memory and at most N digital samples from the auxiliary memory. The retrieved M digital samples comprise a digital sample, preferably the last digital sample, of the first sequence and the retrieved N digital samples comprise the first digital sample of the second sequence.

[0020] As indicated in the background section, difficulties may arise if a single memory is used for storing the digital samples that is slower than the DAC. This will be explained in more detail with reference to figure 1. As referred to herein, a memory being slower than a DAC may be understood as that the memory runs at a lower clock frequency than the DAC. As referred to herein, a DAC operating at some clock frequency fDAc (e.g. expressed in Hz) may be understood as that the DAC outputs an analog signal representing one digital sample every 1 1 fDAc (e.g. expressed in seconds). The clock frequency at which a DAC operates may also be referred to in the art as the sample rate of the DAC. The signal generator disclosed herein advantageously enables to dynamically generate control signals that are directly subsequent to each other irrespective of how many digital samples are in the involved sequences. This will be explained in more detail with reference to figure 3.

[0021] The auxiliary memory, main memory and digital sample stream generator typically all operate at the same clock frequency. Additionally or alternatively, the auxiliary memory, main memory and digital sample stream generator may be configured to output the same number of digital samples per clock cycle.

[0022] It should be appreciated that in the context of generating analog signals for quantum devices using a DAC, it is of the utmost importance that the analog signals are generated correctly and thus that the DAC receives the correct digital samples at the right time. To illustrate, if a digital sample would arrive at the DAC 1 ns too late, then that would already cause an incorrect analog signal to be provided to the quantum device.

[0023] The analog signals are typically pulse signals and the sequences may be said to represent a waveform which, in turn, represents an analog pulse signal.

[0024] The clock frequency of the DAC may be understood to indicate the number of digital samples per second that the DAC can process. The clock frequency of any of the memory, auxiliary memory and / or digital sample stream generator may be understood to indicate the number of times the memory, auxiliary memory and / or digital sample stream generator can output data. Note that these data may comprise more than one digital sample. The clock frequency fmain and the clock frequency faUx may be equal.

[0025] The main memory may be configured to output at most M digital samples per clock cycle to the digital sample stream generator in that the main memory has a memory width suitable for outputting at most M digital samples per memory port and is connected to the digital sample stream generator via only one memory port. Likewise, the auxiliary memory may be configured to output at most N digital samples per clock cycle to the digital sample stream generator in that the auxiliary memory has a memory width suitable for outputting at most N digital samples per memory port and is connected to the digital sample stream generator via only one memory port. Typically, M and N would be equal. Irrespective of this, both M and N would typically be greater than 1, such as four. A digital sample as referred to herein may for example have a number of bits ranging from 1 bit up to and including 32 bits, between 1 and 32 bits, such as 12 bits or 16 bits.

[0026] In an embodiment, the digital sample stream generator is configured to generate the digital sample stream such that the first digital sample of the second sequence directly follows the last digital sample of the first sequence.

[0027] In an embodiment of the method, the step of the digital stream generator generating the digital sample stream is performed such that the first digital sample of the second sequence directly follows the last digital sample of the first sequence.

[0028] These embodiments advantageously ensure that the analog signal as represented by the second sequence can arrive at the quantum device without delay .

[0029] As used herein, “directly follows” means that there is no idle time period in the digital sample stream between the last digital sample of the first sequence and the first digital sample of the second sequence, which idle time period is long enough for accommodating at least one digital sample.

[0030] In an embodiment, the digital sample stream generator is configured to generate the digital sample stream based on sequences of digital samples obtained from the memory system by concatenating the sequences of digital samples obtained from the memory system. More specifically, in this embodiment, the digital sample stream is configured to concatenate the first and second sequence.

[0031] In an embodiment of the method, the step of the digital stream generator generating the digital sample stream comprises concatenating the first and second sequence.

[0032] These embodiments provide a convenient way of determining the digital sample stream based on digital samples obtained from the memory.

[0033] The auxiliary memory preferably has a smaller memory size than the main memory. This eases the requirements for the auxiliary memory. Preferably, the auxiliary memory only stores, of each sequence, the first N digital samples of the sequence. If this is the case, the main memory preferably does not store the first N digital samples of the sequence and / or does store all other digital samples of the sequence in question. In an embodiment, the main memory is configured to, in each clock cycle, provide to the digital sample stream generator only digital samples belonging to a same sequence.

[0034] In an embodiment of the method, the main memory provides at most M digital samples belonging to a same sequence per clock cycle to the digital sample stream generator and / or the auxiliary memory provides at most N digital samples belonging to a same sequence per clock cycle to the digital sample stream generator.

[0035] These embodiments enables to dynamically select individual sequences to be converted into analog signals for controlling the quantum device.

[0036] The auxiliary memory is preferably also configured to, in each clock cycle, provide to the digital sample stream generator only digital samples that belong to a same sequence.

[0037] The main memory and / or auxiliary memory may be configured to provide to the digital sample stream generator only digital samples belonging to a same sequence in the sense that the main memory and / or auxiliary memory have stored, at each memory address, only digital samples belonging to the same sequence. Typically, with each read operation performed on a memory, data from only a single memory address can be retrieved.

[0038] In an embodiment, the signal generator comprises a field-programmable device, such as a field-programmable gate array, FPGA, and / or an application-specific integrated circuit, ASIC. The field-programmable device and / or, respectively, the ASIC comprises the main memory, the auxiliary memory and the digital sample stream generator. Implementing these components on a field-programmable device, such as an FPGA, and / or on an ASIC enables these components to operate at high speeds. In this embodiment, preferably no external memories, external to the field-programmable device and / or ASIC, are used for storing digital samples of any of the sequences, because accessing such external memory takes relatively long.

[0039] Preferably, M > ( fDAc I fmain ) and / or N > ( fDAc I faux ) . This enables the DAC to receive sufficient digital samples per unit of time for it to process digital samples at its clock frequency fDAc- Preferably, M = ( fDAc I fmain ) and / or N = ( fDAc I faux ).

[0040] In an embodiment fDAc= 1 GHZ, faUx= 250 MHZ, fmain = 250 MHZ and M = N = 4.

[0041] In an embodiment, the first sequence of digital samples contains P digital samples, P being an integer number, wherein (P - N) is not divisible by M.

[0042] In case N=M, then this is equal to stating that P is not divisible by M.

[0043] It should be appreciated that the signal generator disclosed herein would also be beneficial in cases where (P - N) is divisible by M, for example if the digital sample stream generator should start outputting the first sequence of digital samples somewhere in the middle of a clock cycle, e.g. with an offset of 1 ns if a clock cycle is 4 ns. In an embodiment, the plurality of sequences comprises a third sequence and a fourth sequence. In this embodiment, the signal generator comprises a further digital sample stream generator and a further DAC. The further digital sample stream generator is configured to generate a further digital sample stream based on sequences of digital samples obtained from the memory system. The further digital-to-analog converter, DAC, is configured to convert the further digital sample stream into further analog signals represented by the sequences of digital samples obtained by the further digital sample stream generator from the memory system. The further DAC is configured to operate at a clock frequency fDAc* which is typically equal to the clock frequency fDAc- In this embodiment, the main memory is configured to provide at most M digital samples per clock cycle to the further digital sample stream generator and the auxiliary memory is configured to provide at most N digital samples per clock cycle to the further digital sample stream generator. The further digital sample stream generator is configured to, during a single clock cycle of the main memory, retrieve at most M digital samples from the main memory and at most N digital samples from the auxiliary memory, the retrieved M digital samples comprising a digital sample, preferably the last digital sample, of the third sequence, the retrieved N digital samples comprising the first digital sample of the fourth sequence.

[0044] In an embodiment of the method, the plurality of sequences comprises a third sequence and a fourth sequence. In this embodiment, the method comprises a further digital sample stream generator generating a further digital sample stream based on sequences of digital samples obtained from the memory system and a further digital-to-analog converter, DAC, converting the further digital sample stream into further analog signals represented by the sequences of digital samples obtained by the further digital sample stream generator from the memory system, wherein the further DAC operates at a clock frequency fDAc*. The method comprises the further digital sample stream generator obtaining digital samples from the memory system, this step comprising

[0045] - the main memory providing at most M digital samples per clock cycle to the further digital sample stream generator, M being an integer number, wherein the main memory operates at a clock frequency fmain, and

[0046] - the auxiliary memory providing at most N digital samples per clock cycle to the further digital sample stream generator, N being an integer number, wherein the auxiliary memory operates at a clock frequency faux.

[0047] The method also comprises, during a single clock cycle of the main memory, the further digital sample stream generator retrieving at most M, preferably M, digital samples from the main memory and at most N, preferably N, digital samples from the auxiliary memory, the retrieved M digital samples comprising a digital sample, preferably the last digital sample, of the third sequence and the retrieved N digital samples comprising the first digital sample of the fourth sequence.

[0048] These embodiments advantageously allow to generate two digital sample streams in parallel. One digital sample stream may represent the in-phase (I) components of some control signal and the other digital sample stream may represent the quadrature (Q) components of that control signal.

[0049] Preferably, the main memory and / or auxiliary memory is configured to, in each clock cycle, provide to the further digital sample stream generator only digital samples belonging to a same sequence, for example in that the main memory and / or auxiliary memory has stored, at each memory address, only digital samples belonging to the same sequence.

[0050] The digital sample stream generator is preferably configured to generate the further digital sample stream such that the first digital sample of the fourth sequence directly follows the last digital sample of the third sequence.

[0051] The main memory may be configured to output at most M digital samples per clock cycle to the further digital sample stream generator in that the main memory has a memory width suitable for outputting at most M digital samples per memory port and is connected to the further digital sample stream generator via only one memory port. Likewise, the auxiliary memory may be configured to output at most N digital samples per clock cycle to the further digital sample stream generator in that the auxiliary memory has a memory width suitable for outputting at most N digital samples per memory port and is connected to the further digital sample stream generator via only one memory port.

[0052] In an embodiment, the auxiliary memory has stored, of each sequence out of the plurality of sequences, the part of the sequence comprising the first digital sample of the sequence, and the main memory has stored, of each sequence out of the plurality of sequences, the further part of the sequence comprising the last digital sample of the sequence.

[0053] In an embodiment, the auxiliary memory has stored, of each sequence out of the plurality of sequences, at most N digital samples. Preferably, these at most N digital samples of each sequence are stored at one memory location in the auxiliary memory.

[0054] This embodiment is advantageous in that it allows to use sequence indicators indicative of respective sequences to be used as address indicators indicative of respective locations in the auxiliary memory. To illustrate, if the digital sample stream generator receives a sequence indicator indicative of a sequence that has to be formed , then the digital sample stream generator can retrieve the at most N digital samples of that sequence from the auxiliary memory without having to first retrieve an address indicator (see below). After all, since the digital samples of that sequence are stored at one memory location, a one-to-one association can be presumed between sequence indicator and memory location.

[0055] In an embodiment, the signal generator comprises an address memory that is configured to store, for each sequence stored in the memory system, a sequence indicator of the sequence in association with an address indicator indicative of a location in the auxiliary memory and / or main memory of a sample of the sequence. In this embodiment, the digital sample stream generator is configured to perform steps of:

[0056] - receiving a sequence indicator, and

[0057] - based on the received sequence indicator, retrieving from the address memory the associated address indicator, and

[0058] - based on the retrieved address indicator, retrieving from the auxiliary memory and / or main memory the digital sample of the sequence indicated by the received sequence indicator.

[0059] Preferably the address memory has stored, for each sequence stored in the memory system, a sequence indicator in association with an address indicator.

[0060] In an embodiment, the method comprises an address memory of the signal generator storing, for each sequence stored in the memory system, a sequence indicator of the sequence in association with an address indicator indicative of a location in the auxiliary memory and / or main memory of a sample of the sequence. In this embodiment, the method comprises the digital sample stream generator performing steps of:

[0061] - receiving a sequence indicator, and

[0062] - based on the received sequence indicator, retrieving from the address memory the associated address indicator, and

[0063] - based on the retrieved address indicator, retrieving from the auxiliary memory and / or main memory the digital sample of the sequence indicated by the received sequence indicator.

[0064] These embodiments enable the digital sample stream generator to efficiently retrieve digital samples from the memory system.

[0065] In an embodiment, the address memory is configured to store, for each stored sequence indicator, a length indicator indicative of how many digital samples are in the sequence indicated by the sequence indicator. For each sequence stored in the memory system, the associated address indicator and length indicator together indicate the respective locations in the memory system of the digital samples of the sequence in question. In this embodiment, the digital sample stream generator is configured to perform steps of: - based on the received sequence indicator, retrieving from the address memory the associated length indicator, and

[0066] - based on the retrieved address indicator and length indicator, retrieving from the memory system digital samples of the sequence indicated by the received sequence indicator.

[0067] Preferably, the address memory has stored, for each stored sequence indicator, a length indicator indicative of how many digital samples are in the sequence indicated by the sequence indicator.

[0068] In an embodiment, the method comprises the address memory storing, for each stored sequence indicator, a length indicator indicative of how many digital samples are in the sequence indicated by the sequence indicator. For each sequence stored in the memory system, the associated address indicator and length indicator together indicate the respective locations in the memory system of the digital samples of the sequence in question. In this embodiment, the method comprises the digital sample stream generator performing steps of:

[0069] - based on the received sequence indicator, retrieving from the address memory the associated length indicator, and

[0070] - based on the retrieved address indicator and length indicator, retrieving from the memory system digital samples of the sequence indicated by the received sequence indicator.

[0071] These embodiments enable the digital sample stream generator to retrieve all digital samples of any sequence very efficiently. The digital sample stream generator may namely only retrieve the address indicator and length indicator for a sequence for it to be able to retrieve all digital samples of that sequence.

[0072] The digital sample stream generator may be configured to determine the memory locations in the main memory of the sequence’s digital samples based on the address indicator and the length indicator. The auxiliary memory and the main memory may have corresponding address structures such that the address indicator not only indicates the location of the sequence’s first sample in the auxiliary memory, but also a reference location in the main memory. The further part of the sequence may then occupy locations in the main memory that are next to this reference location.

[0073] To illustrate, the address indicator of some sequence may be “5” indicating that the first four digital samples of that sequence are stored at memory location “5” in the auxiliary memory and the length indicator may be “16” indicating that the sequence in total contains 16 digital samples. The address indicator “5” may then also be indicative of memory location “5” in the main memory, which then may serve as reference memory location. The digital sample stream generator may then determine by itself that, since the sequence contains 16 digital samples in total, the further part of the sequence, i.e. the last 12 digital samples of the sequence, are stored in memory locations “6”, “7”, “8” of the main memory. Note that in this example, it is assumed that four digital samples are stored at each memory location.

[0074] As will be appreciated by one skilled in the art, aspects of the present invention may be embodied as a system, method or computer program product. Accordingly, aspects of the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment (including firmware, resident software, micro-code, etc.) or an embodiment combining software and hardware aspects that may all generally be referred to herein as a "circuit," "module" or "system." Functions described in this disclosure may be implemented as an algorithm executed by a microprocessor of a computer. Furthermore, aspects of the present invention may take the form of a computer program product embodied in one or more computer readable medium(s) having computer readable program code embodied, e.g., stored, thereon.

[0075] The methods, systems, modules, functions and / or algorithms described with reference to the embodiments in this application may be realized in hardware, software, or a combination of hardware and software. The methods, systems, modules, functions and / or algorithms may be realized in a centralized fashion in at least one computing system, or in a distributed fashion where different elements are spread across several interconnected computing systems. Any kind of computing system or other apparatus adapted for carrying out the embodiments (or parts thereof) described in this application is suited. A typical implementation may comprise one or more digital circuits such as application specific integrated circuits (ASICs), one or more field programmable gate arrays (FPGAs), and / or one or more processors (e.g., x86, x64, ARM, PIC, and / or any other suitable processor architecture) and associated supporting circuitry (e.g., storage, DRAM, FLASH, bus interface circuits, etc.). Each discrete ASIC, FPGA, processor, or other circuit may be referred to as “chip,” and multiple such circuits may be referred to as a “chipset.” In an implementation, the programmable logic devices may be provided with fast RAM, in particular block RAM (BRAM). Another implementation may comprise a non-transitory machine-readable (e.g., computer readable) medium (e.g., FLASH drive, optical disk, magnetic storage disk, or the like) having stored thereon one or more lines of code that, when executed by a machine, cause the machine to perform processes as described in this disclosure.

[0076] The flowcharts and block diagrams in the figures may represent architecture, functionality, and operation of possible implementations of the methods, systems and / or modules to various embodiments of the present invention. In this regard, each block in a flowchart or a block diagram may represent a module, segment, or portion of code, which can be implemented as software, hardware or a combination of software and hardware.

[0077] It should also be noted that, in some alternative implementations, the functions noted in the blocks may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and / or flowchart illustrations, and combinations of blocks in the block diagrams and / or flowchart illustrations, can be implemented by special purpose hardware-based systems that perform the specified functions or acts, or combinations of special purpose hardware and computer instructions. The main insight of the embodiments in this disclosure revolves around dynamic control of the sampling rate during the formation of a digital pulse sequence for a quantum device and during the analysis of signals originating from the quantum device.

[0078] BRIEF DESCRIPTION OF THE DRAWINGS

[0079] Aspects of the invention will be explained in greater detail by reference to exemplary embodiments shown in the drawings, in which:

[0080] FIG. 1 shows timing diagrams of a signal generator without auxiliary memory as disclosed herein;

[0081] FIG. 2 schematically illustrates a signal generator according to an embodiment;

[0082] FIG. 3 shows a timing diagram of a signal generator according to an embodiment;

[0083] FIG. 4 shows a similar timing diagram as figure 3;

[0084] FIG. 5 is a timing diagram that shows in more detail the communication between the different components of a signal generator according to an embodiment;

[0085] FIG. 6 schematically illustrates a sequence processor 660 according to an embodiment;

[0086] FIG. 7 illustrates a data processing system according to an embodiment.

[0087] DETAILED DESCRIPTION OF THE DRAWINGS

[0088] In the figures, identical reference numbers indicate identical or similar elements. Further, reference numbers that differ by 100 indicate identical or similar elements.

[0089] Delivering instructions to a quantum processor is a complicated process. A quantum processor uses quantum elements, such as quantum bits (qubits), which are based on quantum systems such as trapped ions, trapped electrons, superconducting Josephson junctions, photons, quantum dots, etc. to process information based on quantum mechanical processes such as superposition and quantum entanglement. The information stored and processed by qubits is represented by the physical quantum states of the quantum bits. Typically, these quantum devices are located in a screened, cooled cryogenic environment to suppress the thermal noise that distorts the quantum state of the quantum bits.

[0090] In most implementations, a classical control system is used to translate instructions into physical pulses for controlling the quantum processor to perform quantum logic operations, and to measure quantum states of the quantum bits. In addition, a computer is used to upload the control program to the control system and after the execution of the control program, the measured states of the quantum bits are reported back in digital form back to this computer. To alter and readout quantum states digital-to-analog (DAC) and analog-to- digital converters (ADC) are used. In particular, physical signals referred to as control pulses with specific shapes need to be generated to change the state of a quantum element, such as a qubit. The quantum state is measured by sending a specifically shaped pulse to the quantum device and reading back its reflection or transmission. This measurement needs to be digitized and interpreted by the control system which then - in response - decides to generate further control pulses.

[0091] Each sequence of digital samples as referred to herein may represent a control pulse of particular shape and duration with which single or double qubit operation (gate operations) can be performed on a quantum device. Each gate operation represents a particular manipulation of the qubits of the quantum device. The generation of subsequent control pulses requires resources to store, compute, and generate such pulses of approx. 10 - 1000 ns. To this end, a large number of sequences representing different analog signals is digitally stored in a memory system.

[0092] Figure 1 shows timing diagrams of a signal generator in which no auxiliary memory as defined herein is implemented. Figure 1A shows a timing diagram indicating clock pulses (top), and indicating the digital samples as output by some memory storing all digital samples that collectively represent all signals that the generator signal can output (middle), and the digital sample stream that is provided to a DAC. Figure 1A indicates the duration 2 of a clock cycle for the memory. In figure 1A, a first sequence 4 of digital samples contains 16 digital samples [0; 1 ; ..; 14; 15] (indicated in white) and a second sequence 6 of digital samples also contains 16 digital samples [0; 1; ..; 14; 15] (indicated in grey). In practice, each sequence may contain many more, e.g. thousands of, digital samples. As can be seen, during each clock cycle, the memory outputs 4 digital samples, which in the next clock cycle are incorporated in the digital sample stream provided to the DAC. The memory in this example apparently can store four digital samples per memory address. As a result, per read operation only 4 digital samples can be retrieved from the memory. Hence, the DAC may operate at a clock frequency four times higher than the clock frequency of the memory. The DAC for example operates at a clock frequency of 1 GHz meaning that it can process a digital sample stream having a billion samples per second whereas the memory operates at a clock frequency of 250 MHz meaning that it can be read 250 million times per second.

[0093] In figure 1A, the second sequence 6 directly follows the first sequence 4. In other words, there is no idle time period in the digital sample stream between the first sequence 4 and second sequence 6, which is nice because such an idle time period would cause the desired control signal, represented by the second sequence of digital samples, to arrive at the quantum device later. Preferably, control signals are provided to a quantum device as fast as possible.

[0094] Figure 1B illustrates that using a single memory operating at a lower clock frequency than the DAC may yield an idle time period between the first sequence 4 and second sequence 6 in the digital sample stream. As in figure 1A, the second sequence shown in figure 1 B contains 16 digital samples. However, the first sequence 4 in figure 1B contains only 13 digital samples instead of 16. Again, the memory outputs 4 digital samples per clock cycle because it can store only four digital samples per memory address. However, this means that in clock cycle 8 only one digital sample, namely the last digital sample

[0012] , of the first sequence 4 is output by the memory simply because there are no more other digital samples left of the first sequence 4.

[0095] Storing digital samples of different sequences at the same memory address is preferably prevented as this would prevent dynamic control of the quantum device. Dynamic control of the quantum device may be understood as that the control signals provided to the quantum device are determined during an experiment, for example because they are conditional on a state of the quantum device. Hence, it is not known before an experiment which control signals are going to be provided to the quantum device. If for example the last digital sample

[0012] of the first sequence 4 would be stored at the same memory address as the first digital samples [0:2] of the second sequence 6, then all of these digital samples would always be output together by the memory and would end up together in the digital sample stream provided to the DAC. However, the second sequence 6 need not always follow the first sequence 4 given that the quantum device is dynamically controlled.

[0096] Thus, figure 1B shows that in clock cycle 8 the memory only outputs digital sample

[0012] of the first sequence 4. As a result, in the next clock cycle 10, only digital sample

[0012] is included in the digital sample stream. Because no digital samples of another sequence have been retrieved yet, there is an idle time period 12 in the digital sample stream containing no digital samples. This idle time period 12 constitutes a delay. In clock cycle 10, the memory can output digital samples of another sequence, in this example digital samples [0:3] of second sequence 6, which can be included in the digital sample stream during clock cycle 14.

[0097] Figure 2 schematically illustrates a signal generator 20 according to an embodiment. The signal generator may comprise a field-programmable device 22, such as a field- programmable gate array (FPGA), having programmed thereon several components of the signal generator 20. As known, a field-programmable device 22 may be configured using hardware description language and can achieve high processing speeds, which is very useful in the context of controlling quantum devices, especially if the quantum devices have relatively short coherence times. Additionally or alternatively, the signal generator 20 comprises an ASIC comprising at least part of the memory system.

[0098] In the embodiment of figure 2, the field-programmable device 22 comprises an address memory 24, an auxiliary memory 26, a main memory 28, a digital sample stream generator 30a, a further digital sample stream generator 30b, arbitrary waveform generator path 32, a DAC 34a and a DAC 34b. It should be appreciated that achieving the technical advantages of the signal generator disclosed herein does not necessarily require these components to be implemented on a field-programmable device. Further, although convenient, the address memory 24, further digital sample stream generator 30b, arbitrary waveform generator path 32 and further DAC 34b are optional elements and the advantages of the technology disclosed herein can be achieved without these optional elements.

[0099] The signal generator comprises a memory system that comprises auxiliary memory 26 and main memory 28. The memory system stores a plurality of sequences of digital samples. Each sequence represents an analog signal for controlling the quantum device. Preferably, the sequences that are to be converted into analog control signals are dynamically selected, for example in the sense that the selection depends on a current state of the quantum device. Hence, the memory system preferably stores many sequences in order to be able to appropriately control the quantum device as desired for any given state of the quantum device.

[0100] The auxiliary memory 26 stores, of each sequence out of the plurality of sequences, a part of the sequence comprising the first digital sample of the sequence. The main memory 28 stores, of each sequence out of the plurality of sequences, a further part of the sequence comprising the last digital sample of the sequence. The auxiliary memory 26 and main memory 28 would typically be similar memories in that they would operate at the same clock frequency and / or would have the same number of memory ports and / or would have the same memory width. The auxiliary memory 26 may require a smaller memory capacity than the main memory 28 if the auxiliary memory only stores the first few digital samples of each sequence and the main memory 28 stores the majority of digital samples of each sequence. Of course, if the auxiliary memory 26 would store the majority of digital samples of each sequence and the main memory 28 would store only the last few digital samples of each sequence, then the capacity of the main memory 28 may be much lower than the capacity of the auxiliary memory 26. Both the auxiliary memory 26 and the main memory 28 preferably store, at each memory location, only digital samples that belong to the same sequence. This allows that any sequence can be individually retrieved from the memory system, thus without also retrieving digital samples from other sequences. Such individual retrieval of sequences greatly eases dynamically controlling the quantum device.

[0101] The digital sample stream generators 30 are configured to generate respective digital sample streams based on sequences of digital samples obtained from the memory system. Each of the digital sample stream generators 30 may thus have to obtain digital samples from at least both the auxiliary memory 26 and the main memory 28 in order to obtain all digital samples of a sequence.

[0102] In order to correctly retrieve digital samples from the auxiliary memory and main memory, the digital sample stream generators 30 may make use of address memory 24. The address memory, if present, may namely store, for each sequence stored in the memory system, a sequence indicator of the sequence in association with an address indicator indicative of a location in the auxiliary memory of the first sample of the sequence. Preferably, the address memory would also store, for each stored sequence indicator, a length indicator indicative of how many digital samples are in the sequence indicated by the sequence indicator. As will be explained in more detail below, the digital sample stream generators, upon being instructed to incorporate a particular sequence of digital samples into the digital sample stream that it generates, can retrieve the address indicator and length indicator for that particular sequence from the address memory 24 and may be able to determine the memory locations of all digital samples of that particular sequence in the auxiliary memory 26 and the main memory 28.

[0103] In the embodiment of figure 2, the digital sample stream generators 30 provide their generated digital sample streams to an arbitrary waveform generator path 32. Arbitrary waveform generator path 32 is optional and may be configured to add features like a dynamically settable offset and gain as well as IQ mixing with a dynamically settable frequency and phase.

[0104] In turn, the arbitrary waveform generator path 32 provides the digital sample streams to respective DACs, each of which is configured to convert the digital sample stream into analog signals represented by the sequences of digital samples obtained from the memory system. The analog signals can then be provided to a quantum device for controlling the quantum device, for example for performing gate operations. The DAC 34a and the DAC 34b would typically be identical, but this is not strictly required.

[0105] Figure 3 shows a timing diagram of a signal generator according to an embodiment. The timing diagrams indicate, from top to bottom, clock pulses, the digital samples as output by an auxiliary memory according to an embodiment, the digital samples as output by a main memory according to an embodiment, and the digital sample stream output by a digital sample stream generator according to an embodiment.

[0106] In the embodiment of figure 3, the first sequence 4 contains 13 digital samples and the second sequence 6 contains 16 digital samples. Further, in the embodiment of figure 3, the DAC operates at a clock frequency that is four times higher than the clock frequency at which the memories and digital sample stream generator operate. Hence, in each clock cycle, the digital sample stream generator needs to output at least four digital samples in the digital sample stream. In the depicted embodiment, the main memory and auxiliary memory each can output digital samples in a single clock cycle. As a result, the digital sample stream generator can retrieve, during a single clock cycle, both digital samples from the auxiliary memory and from the main memory. Indeed, figure 3 shows that in clock cycle 342 the main memory outputs digital sample “12” belonging to the first sequence and the auxiliary memory outputs digital samples “0”, “1”, “2”, “3” belonging to the second sequence. Hence, the digital sample stream generator is able to, in next clock cycle 344, concatenate the sequences to each other and incorporate the digital samples “12”, “0”, “1”, “2” into the digital sample stream. In the generated digital sample stream, the digital sample “0” of the second sequence directly follows digital sample “12” of the first sequence meaning that there is no idle time. Thus, the analog signal represented by the second sequence is advantageously provided to the quantum device without delay.

[0107] As a side note, in the embodiment of figure 3, the digital sample stream is configured to always retrieve the first N digital samples of any sequence from the auxiliary memory and the other digital samples of the sequence from the main memory. Thus, if the digital sample stream recognizes that it has to retrieve the first N digital samples of some sequency, it will automatically attempt to retrieve these from the auxiliary memory. This is also the reason why in clock cycle 340 the first four digital samples “0”, “1”, “2”, “3” belonging to the first sequence 4 are retrieved from the auxiliary memory even though the main memory would have been able to output these digital samples as well because it is not outputting any other digital samples during clock cycle 340.

[0108] Figure 4 shows a similar timing diagram as figure 3. However, figure 4 also shows a “start” signal that is received by the digital sample stream generator. The start signal comprises a sequence indicator of the sequence that the digital sample stream generator has to include in the digital sample stream that it generates.

[0109] As shown, in clock cycle 446 the digital sample stream generator receives a start signal comprising the sequence indicator “0”. In the subsequent clock cycle 448, the auxiliary memory provides samples “0”, “1”, “2”, “3” belonging to sequence “0” to the digital sample stream generator. As before, the digital sample stream generator will retrieve the other digital samples of sequence “0” from the main memory and this happens in clock cycles 450, 452, 454.

[0110] Likewise, for sequence “1” the start signal is received by the digital sample stream generator in clock cycle 452 indicating that sequence “1” should be included in the digital sample stream after sequence “0”. The first sample “0”, “1”, “2”, “3” of sequence “1” are then retrieved by the digital sample stream generator from the auxiliary memory and the rest of the digital samples of sequence “1” from the main memory in clock cycles 456 and 458.

[0111] Figure 4 indicates that there is a delay of one clock cycle between reception of the start signal and the retrieval of the first samples of the sequence as indicated by the start signal, i.e. the first samples are retrieved in the clock cycle that is subsequent to the clock cycle in which the start signal is received. However, depending on the exact implementation, this delay may be any number of clock cycles.

[0112] The start signal may be sent by a sequence processor 560, which is shown in figure 5. Any of the signal generators disclosed herein may comprise a sequence processor 560. The sequence processor 560 may be configured to control the digital sample stream generator for example in that it is configured to send commands to the digital sample stream generator.

[0113] Figure 5 is a timing diagram that shows in more detail the communication between the different components of a signal generator according to an embodiment.

[0114] As can be seen on the left hand side, figure 5 spans five clock cycles 562, 564, 566, 568 and 570. In clock cycle 562, the sequence processor 560 sends a start signal 571 to the digital sample stream generator. The start signal 571 comprises sequence indicator “0” which is indicative of sequence “0”. The start signal 571 may be understood as an instruction for the digital sample stream generator to retrieve from the memory system the digital sample of sequence “0” and include them into the generated sample stream.

[0115] Upon reception of the start signal 571 in clock cycle 562, the digital sample stream generator retrieves an address indicator from an address memory by sending a request 572 to the address memory. The request 572 comprises the sequence indicator “0”. The address memory then returns a signal 573 comprising the address indicator of the sequence and, in this embodiment also the length of the sequence, which is typically indicative of a number of digital samples in the sequence. In the depicted embodiment, the address indicator is indicative of the location in the main memory of the samples of sequence “0

[0116] In clock cycle 564, the digital sample stream generator sends a request 574 to the auxiliary memory. The request 574 may specify the location in the auxiliary memory in that it comprises the sequence indicator “0”. The request 574 need not comprise the address indicator as retrieved from the address memory. Based on the sequence indicator, the auxiliary memory can namely return the correct data. After all, for the auxiliary memory, the sequence indicators may function as address indicators because the auxiliary memory has reserved, in this embodiment, one memory location per sequence. Indeed, the auxiliary memory returns a message 575 comprising the digital samples “0”, “1”, “2”, “3” belonging to sequence “0”. This allows the digital sample stream generator to include these digital samples into the digital sample stream in clock cycle 566. (The digital sample stream is not shown in figure 5.)

[0117] In clock cycle 566, the digital sample stream can send a request 576 to the main memory in order to retrieve the other digital samples of sequence “0” from the main memory. Request 576 would typically also specify a location in the main memory where the requested data is stored. Preferably, the digital sample stream generator can determine the location in the main memory of all digital samples of sequence “0” based on the address indicator, and optionally based on the length, received in step 573. This way, the digital sample stream generator only needs one address indicator for retrieving all digital samples of the sequence from the main memory. Indeed, the main memory returns in clock cycle 566 a signal 577 comprising the digital samples “4”, “5”, “6”, “7” of sequence “0” so that the digital sample stream generator can include these digital samples in the stream in clock cycle 568.

[0118] In a similar manner as in clock cycle 566, the digital sample stream generator retrieves samples “8”, “9”, “10”, “11” from the main memory in clock cycle 568 and digital sample “12” from the main memory in clock cycle 570.

[0119] However, in clock cycle 568, the sequence processor 560 sends a start signal 578 to the digital sample stream generator. The start signal 578 comprises sequence indicator “1”. The digital sample stream generator then sends a request 579 to the address memory for an address indicator of sequence “1”. Indeed, in signal 580, the address memory provides the address indicator and the length of sequence “1” to the digital sample stream generator.

[0120] In clock cycle 570, the digital sample stream generator can send request 583 to the auxiliary memory to retrieve digital samples “0”, “1”, “2”, “3” from the auxiliary memory (step 584). Request 583 may comprise the sequence indicator “1” as indication of the memory location in the auxiliary memory where digital samples “0”, “1”, “2”, “3” are stored and need not comprise the address indicator retrieved in step 580. The address indicator retrieved in step 580 may be used to retrieve further digital samples of sequence “1” from the main memory (not shown).

[0121] Thus, in clock cycle 570 the digital sample stream generator obtains both digital sample “12” of sequence “0” and digital samples “0”, “1”, “2”, “3” of sequence “1”. The digital sample stream generator can then concatenate these digital samples indicated by step 587 so that in the clock cycle subsequent to the clock cycle 570 the digital sample stream generator outputs the digital samples “12”, “0”, “1”, “2” as part of the generated sample stream.

[0122] Figure 6 schematically illustrates a sequence processor 660 according to an embodiment. The depicted sequence processor 660 comprises a classical processor 688 and a real-time co-processor 690. The classical processor may be configured to process instructions that define a quantum experiment and may provide similar functionality to other CPUs, such as branching, memory handling, arithmetic. Preferably, the classical processor is deterministic and low-latency. The classical processor 688 may for example be configured to process and / or determine instructions related to real-time waveform playback and measurement control. The classical processor may be configured to send and / or forward instructions, also referred to as commands, to real-time co-processor 690.

[0123] The real-time co-processor may be configured to, based on the instructions received from the classical processor, schedule real-time operations on the quantum system’s output and input paths for waveform playback and measurement control respectively. To illustrate, the real-time co-processor may output for a sequence a start time indication and a sequence index, and other information to a digital sample stream generator as disclosed herein, so that the digital sample stream generator can cause the digital samples of the correct sequence to appear in the digital sample stream at the correct time.

[0124] Fig. 7 depicts a block diagram illustrating a data processing system according to an embodiment. This data processing system may represent any of the data processing systems referred to herein, such as the sequence processor and / or classical processor and / or real-time co-processor and / or digital sample stream generator referred to herein.

[0125] As shown in Fig. 7, the data processing system 780 may include at least one processor 782 coupled to memory elements 788 through a system bus 797. As such, the data processing system may store program code within memory elements 788.

[0126] Further, the processor 780 may execute the program code accessed from the memory elements 788 via a system bus 797. In one aspect, the data processing system may be implemented as a computer that is suitable for storing and / or executing program code. It should be appreciated, however, that the data processing system 780 may be implemented in the form of any system including a processor and a memory that is capable of performing the functions described within this specification.

[0127] The memory elements 788 may include one or more physical memory devices such as, for example, local memory 789 and one or more bulk storage devices 792. The local memory may refer to random access memory or other non-persistent memory device (s) generally used during actual execution of the program code. A bulk storage device may be implemented as a hard drive or other persistent data storage device. The processing system 780 may also include one or more cache memories (not shown) that provide temporary storage of at least some program code in order to reduce the number of times program code must be retrieved from the bulk storage device 792 during execution.

[0128] Input / output (I / O) devices depicted as an input device 794 and an output device 795 optionally can be coupled to the data processing system. Examples of input devices may include, but are not limited to, a keyboard, a pointing device such as a mouse, any of the memories described herein, or the like. Examples of output devices may include, but are not limited to, a monitor or a display, speakers, DACs, or the like. Input and / or output devices may be coupled to the data processing system either directly or through intervening I / O controllers.

[0129] In an embodiment, the input and the output devices may be implemented as a combined input / output device (illustrated in Fig. 7 with a dashed line surrounding the input device 794 and the output device 795) . An example of such a combined device is a touch sensitive display, also sometimes referred to as a "touch screen display" or simply "touch screen". In such an embodiment, input to the device may be provided by a movement of a physical object, such as e.g. a stylus or a finger of a user, on or near the touch screen display.

[0130] A network adapter 796 may also be coupled to the data processing system to enable it to become coupled to other systems, computer systems, remote network devices, and / or remote storage devices through intervening private or public networks. The network adapter may comprise a data receiver for receiving data that is transmitted by said systems, devices and / or networks to the data processing system 780, and a data transmitter for transmitting data from the data processing system 780 to said systems, devices and / or networks. Modems, cable modems, and Ethernet cards are examples of different types of network adapter that may be used with the data processing system 780.

[0131] As pictured in Fig. 7, the memory elements 788 may store an application 790. In various embodiments, the application 790 may be stored in the local memory 789, the one or more bulk storage devices 792, or apart from the local memory and the bulk storage devices. It should be appreciated that the data processing system 780 may further execute an operating system (not shown in Fig. 7) that can facilitate execution of the application 790. The application 790, being implemented in the form of executable program code, can be executed by the data processing system 780, e.g., by the processor 780. Responsive to executing the application, the data processing system 780 may be configured to perform one or more operations or method steps described herein.

[0132] Various embodiments of the invention may be implemented as a program product for use with a computer system, where the program(s) of the program product define functions of the embodiments (including the methods described herein). In one embodiment, the program(s) can be contained on a variety of non-transitory computer-readable storage media, where, as used herein, the expression "non-transitory computer readable storage media" comprises all computer-readable media, with the sole exception being a transitory, propagating signal. In another embodiment, the program(s) can be contained on a variety of transitory computer-readable storage media.

[0133] Illustrative computer-readable storage media include, but are not limited to: (i) non- writable storage media (e.g., read only memory devices within a computer such as CD-ROM disks readable by a CD-ROM drive, ROM chips or any type of solid- state non-volatile semiconductor memory) on which information is permanently stored; and (ii) writable storage media (e.g., flash memory, floppy disks within a diskette drive or hard disk drive or any type of solid-state random-access semiconductor memory) on which alterable information is stored. The computer program may be run on the processor 782 described herein.

[0134] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0135] The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of the present invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the invention in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the invention. The embodiment was chosen and described in order to best explain the principles of the invention and the practical application, and to enable others of ordinary skill in the art to understand the invention for various embodiments.

Claims

CLAIMS1 . A signal generator for generating analog signals for controlling a quantum device, the signal generator comprising a memory system that is configured to store a plurality of sequences of digital samples, the plurality of sequences comprising a first sequence and a second sequence, wherein each sequence out of the plurality of sequences represents an analog signal for controlling the quantum device, and a digital sample stream generator for generating a digital sample stream based on sequences of digital samples obtained from the memory system, and a digital-to-analog converter, DAC, for converting the digital sample stream into analog signals represented by the sequences of digital samples obtained from the memory system, wherein the DAC is configured to operate at a clock frequency fDAc, wherein the memory system comprises an auxiliary memory that is configured to store, of each sequence out of the plurality of sequences, a part of the sequence comprising the first digital sample of the sequence, and wherein the memory system comprises a main memory that is configured to store, of each sequence out of the plurality of sequences, a further part of the sequence comprising the last digital sample of the sequence, wherein the main memory is configured to operate at a clock frequency fmain that is lower than the clock frequency fDAc and is configured to provide at most M digital samples per clock cycle to the digital sample stream generator, M being an integer number, and the auxiliary memory is configured to operate at a clock frequency faUx that is lower than the clock frequency fDAc and is configured to provide at most N digital samples per clock cycle to the digital sample stream generator, N being an integer number, wherein the digital sample stream generator is configured to, during a single clock cycle of the main memory, retrieve at most M digital samples from the main memory and at most N digital samples from the auxiliary memory, the retrieved M digital samples comprising a digital sample, preferably the last digital sample, of the first sequence and the retrieved N digital samples comprising the first digital sample of the second sequence.

2. The signal generator according to claim 1 , wherein the digital sample stream generator is configured to generate the digital sample stream such that the first digital sample of the second sequence directly follows the last digital sample of the first sequence.

3. The signal generator according to any of the preceding claims, wherein the digital sample stream generator is configured to generate the digital sample stream based on sequences of digital samples obtained from the memory system by concatenating the sequences of digital samples obtained from the memory system, wherein the digital sample stream is configured to concatenate the first and second sequence.

4. The signal generator according to any of the preceding claims, wherein the auxiliary memory has a smaller memory size than the main memory.

5. The signal generator according to any of the preceding claims, wherein the main memory is configured to, in each clock cycle, provide to the digital sample stream generator only digital samples belonging to a same sequence.

6. The signal generator according to any of the preceding claims, comprising a field-programmable device, such as a field-programmable gate array, and / or an application-specific integrated circuit, ASIC, wherein the field-programmable device and / or, respectively, the ASIC comprises the main memory, the auxiliary memory and the digital sample stream generator.

7. The signal generator according to any of the preceding claims, whereinM > ( fDAc I fmain ), and / orN > ( fDAC I faux )•8. The signal generator according to any of the preceding claims, wherein the first sequence of digital samples contains P digital samples, P being an integer number, wherein(P - N) is not divisible by M.

9. The signal generator according to any of the preceding claims, wherein the plurality of sequences comprises a third sequence and a fourth sequence, the signal generator comprising a further digital sample stream generator for generating a further digital sample stream based on sequences of digital samples obtained from the memory system, and a further digital-to-analog converter, DAC, for converting the further digital sample stream into further analog signals represented by the sequences of digital samples obtainedby the further digital sample stream generator from the memory system, wherein the further DAC is configured to operate at a clock frequency fDAc*, wherein the main memory is configured to provide at most M digital samples per clock cycle to the further digital sample stream generator, and the auxiliary memory is configured to provide at most N digital samples per clock cycle to the further digital sample stream generator, wherein the further digital sample stream generator is configured to, during a single clock cycle of the main memory, retrieve at most M digital samples from the main memory and at most N digital samples from the auxiliary memory, the retrieved M digital samples comprising a digital sample, preferably the last digital sample, of the third sequence, the retrieved N digital samples comprising the first digital sample of the fourth sequence.

10. The signal generator according to any of the preceding claims, wherein the auxiliary memory has stored, of each sequence out of the plurality of sequences, the part of the sequence comprising the first digital sample of the sequence, and wherein the main memory has stored, of each sequence out of the plurality of sequences, the further part of the sequence comprising the last digital sample of the sequence.

11. The signal generator according to any of the preceding claims, wherein the auxiliary memory has stored, of each sequence out of the plurality of sequences, at most N digital samples.

12. The signal generator according to any of the preceding claims, further comprising an address memory that is configured to store, for each sequence stored in the memory system, a sequence indicator of the sequence in association with an address indicator indicative of a location in the auxiliary memory and / or main memory of a sample of the sequence, wherein the digital sample stream generator is configured to perform steps of:- receiving a sequence indicator, and- based on the received sequence indicator, retrieving from the address memory the associated address indicator, and- based on the retrieved address indicator, retrieving from the auxiliary memory and / or main memory the digital sample of the sequence indicated by the received sequence indicator.

13. The signal generator according to the preceding claim, wherein the address memory is configured to store, for each stored sequence indicator, a length indicator indicative of how many digital samples are in the sequence indicated by the sequence indicator, wherein for each sequence stored in the memory system, the associated address indicator and length indicator together indicate the respective locations in the memory system of the digital samples of the sequence in question, wherein the digital sample stream generator is configured to perform steps of:- based on the received sequence indicator, retrieving from the address memory the associated length indicator, and- based on the retrieved address indicator and length indicator, retrieving from the memory system digital samples of the sequence indicated by the received sequence indicator.

14. A method for generating analog signals for controlling a quantum device, comprising a memory system storing a plurality of sequences of digital samples, the plurality of sequences comprising a first sequence and a second sequence, wherein each sequence out of the plurality of sequences represents an analog signal for controlling the quantum device, this step comprising- an auxiliary memory of the memory system storing, of each sequence out of the plurality of sequences, a part of the sequence comprising the first digital sample of the sequence, and- a main memory of the memory system storing, of each sequence out of the plurality of sequences, a further part of the sequence comprising the last digital sample of the sequence, the method further comprising a digital sample stream generator obtaining digital samples from the memory system, this step comprising- the main memory providing at most M digital samples per clock cycle to the digital sample stream generator, M being an integer number, wherein the main memory operates at a clock frequency fmain, and- the auxiliary memory providing at most N digital samples per clock cycle to the digital sample stream generator, N being an integer number, wherein the auxiliary memory operates at a clock frequency faux, the method further comprising the digital sample stream generator generating a digital sample stream based on sequences of digital samples obtained from the memory system, anda digital-to-analog converter, DAC, converting the digital sample stream into analog signals represented by the sequences of digital samples obtained from the memory system, wherein the DAC operates at a clock frequency fDAc that is higher than the clock frequency fmain and higher than the clock frequency faux, wherein the method comprises during a single clock cycle of the main memory, the digital sample stream generator retrieving at most M, preferably M, digital samples from the main memory and at most N, preferably N, digital samples from the auxiliary memory, the retrieved M digital samples comprising a digital sample, preferably the last digital sample, of the first sequence and the retrieved N digital samples comprising the first digital sample of the second sequence.

15. The method according to claim 14, wherein the step of the digital stream generator generating the digital sample stream is performed such that the first digital sample of the second sequence directly follows the last digital sample of the first sequence.

16. The method according to claim 14 or 15, wherein the step of the digital stream generator generating the digital sample stream comprises concatenating the first and second sequence.

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