Array substrate, display panel and display device

Abstract

Provided in the present invention are an array substrate, a display panel and a display device. The array substrate comprises a plurality of pixel driving circuits. Each pixel driving circuit comprises a first transistor and a driving transistor. The array substrate comprises: a substrate; a semiconductor layer disposed on one side of the substrate, the semiconductor layer comprising a first active layer pattern; and a first metal layer disposed on the side of the semiconductor layer away from the substrate, the first metal layer comprising a first gate layer pattern, wherein the first gate layer pattern overlaps the first active layer pattern, an overlapping portion is a first channel on the first active layer pattern, and the first transistor and the driving transistor share the first channel and the first gate layer pattern. The layout of the pixel driving circuits of the array substrate provided by the present invention is space-saving and suitable for use in a display panel with a high-density pixel arrangement.

Description

Array substrate, display panel and display device Technical Field

[0001] This invention relates to the field of display technology, and more specifically to an array substrate, a display panel, and a display device. Background Technology

[0002] Organic light-emitting display (OLED) devices have many advantages, including being all-solid-state, self-emissive, having a wide viewing angle, wide color gamut, fast response speed, high luminous efficiency, high brightness, high contrast, ultra-thinness, ultra-lightness, low power consumption, wide operating temperature range, the ability to manufacture large-size and flexible panels, and simple manufacturing processes. They can realize truly flexible displays and have broad development prospects, attracting increasing attention and importance from the market in recent years.

[0003] Organic light-emitting display devices (OLEDs) use pixel driving circuits to illuminate light-emitting pixels to achieve corresponding image display. Figure 1 shows an equivalent schematic diagram of a pixel driving circuit. In the prior art, the pixel driving circuit arranged on the display panel according to Figure 1 has a complex layout structure and requires a large layout space, which prevents the pixel density of the display panel from being further increased.

[0004] Summary of the Invention

[0005] In view of the problems in the prior art, the purpose of the present invention is to provide an array substrate, a display panel and a display device that saves the arrangement space of the pixel driving circuit and is suitable for display panels with high pixel density.

[0006] This invention provides an array substrate including multiple pixel driving circuits, each pixel driving circuit including a first transistor and a driving transistor; the array substrate includes:

[0007] Substrate;

[0008] A semiconductor layer is located on one side of the substrate, the semiconductor layer including a first active layer pattern;

[0009] A first metal layer is located on the side of the semiconductor layer away from the substrate. The first metal layer includes a first gate layer pattern, which overlaps with a first active layer pattern. The overlapping portion forms a first channel on the first active layer pattern.

[0010] The first transistor and the driving transistor share the first channel and the first gate layer pattern.

[0011] In some embodiments, the pattern of the first trench is a zigzag shape.

[0012] In some embodiments, the first gate layer pattern includes a first pattern and a second pattern connected along a first direction, wherein the area of ​​the first pattern is smaller than the area of ​​the second pattern.

[0013] Wherein, the second pattern overlaps with the middle part of the first active layer pattern, and the first pattern overlaps with the first end or the second end of the first active layer pattern.

[0014] In some embodiments, the pixel driving circuit further includes an initialization transistor, a data writing transistor, and a compensation transistor;

[0015] The semiconductor layer further includes a third active layer pattern of the initialization transistor, a fourth active layer pattern of the data writing transistor, and a fifth active layer pattern of the compensation transistor.

[0016] The first metal layer further includes a third gate layer pattern of the initialization transistor, a fourth gate layer pattern of the data writing transistor, and a fifth gate layer pattern of the compensation transistor;

[0017] The third gate layer pattern overlaps with the third active layer pattern, the fourth gate layer pattern overlaps with the fourth active layer pattern, and the fifth gate layer pattern overlaps with the fifth active layer pattern.

[0018] In some embodiments, the pixel driving circuit further includes a reset transistor, a first light-emitting control transistor, and a second light-emitting control transistor;

[0019] The semiconductor layer further includes a sixth active layer pattern of the reset transistor, a seventh active layer pattern of the first light-emitting control transistor, and an eighth active layer pattern of the second light-emitting control transistor.

[0020] The first metal layer further includes a sixth gate layer pattern of the reset transistor, a seventh gate layer pattern of the first light-emitting control transistor, and an eighth gate layer pattern of the second light-emitting control transistor.

[0021] The sixth active layer pattern overlaps with the sixth gate layer pattern, the seventh active layer pattern overlaps with the seventh gate layer pattern, and the eighth active layer pattern overlaps with the eighth gate layer pattern.

[0022] In some embodiments, the pixel driving circuit further includes a storage capacitor;

[0023] The array substrate further includes a second metal layer located on the side of the first metal layer away from the substrate; the second metal layer overlaps with the pattern of the first gate layer, and the overlapping portion of the vertical projection of the first gate layer pattern and the second metal layer on the substrate forms the storage capacitor.

[0024] In some embodiments, the area where the patterns of the second metal layer and the first gate layer overlap is 120 μm. 2 ~200μm 2 .

[0025] In some embodiments, a third metal layer disposed along a first direction is further included, located on the side of the second metal layer away from the substrate; the third metal layer includes a first scan signal line, a second scan signal line, and a third scan signal line;

[0026] The first scan signal line overlaps with the third gate layer pattern of the initialization transistor;

[0027] The second scan signal line overlaps with the fourth gate layer pattern of the write transistor and the fifth gate layer pattern of the compensation transistor;

[0028] The third scan signal line overlaps with the sixth gate layer pattern of the reset transistor.

[0029] In some embodiments, the third metal layer further includes an initialization voltage signal, a reset voltage signal line, and a first power supply voltage signal line; the third active layer pattern of the initialization transistor overlaps with the initialization voltage signal line;

[0030] The second metal layer overlaps with the first power supply voltage signal line;

[0031] The pattern of the sixth active layer of the reset transistor overlaps with the reset voltage signal line.

[0032] In some embodiments, a fourth metal layer disposed along a second direction is further included, located on the side of the third metal layer away from the substrate.

[0033] In some embodiments, the fourth metal layer includes a data line and the first power supply voltage signal line; the data line overlaps with the fourth active layer pattern on which the data is written; and the first power supply voltage signal line overlaps with the third metal layer.

[0034] This invention also provides a display panel, including the array substrate described above.

[0035] This invention also provides a display device, including a display substrate as described above.

[0036] The array substrate, display panel, and display device provided by this invention have the following advantages:

[0037] The pixel driving circuit arrangement space on the array substrate provided by this invention is small, making it suitable for use in high pixel density panels. Attached Figure Description

[0038] Other features, objects, and advantages of the invention will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings.

[0039] Figure 1 is an equivalent schematic diagram of a pixel driving circuit;

[0040] Figure 2 is a schematic diagram of the layout of an array substrate with a semiconductor layer and a first metal layer provided in an embodiment of the present invention;

[0041] Figure 3 is a schematic diagram of the layout of an array substrate with a semiconductor layer and a first metal layer provided in another embodiment of the present invention;

[0042] Figure 4 is a schematic diagram of the layout of an array substrate after a second metal layer is disposed in an embodiment of the present invention.

[0043] Figure 5 is a layout diagram of an array substrate after a second metal layer is disposed, according to another embodiment of the present invention.

[0044] Figure 6 is a partial enlarged view of the array substrate after the second metal layer is disposed in another embodiment of the present invention;

[0045] Figure 7 is a schematic diagram of the layout of an array substrate after contact holes are provided according to an embodiment of the present invention;

[0046] Figure 8 is a schematic diagram of the layout of an array substrate after a third metal layer is provided according to an embodiment of the present invention;

[0047] Figure 9 is a schematic diagram of the cross section cut along section line AA' in Figure 8;

[0048] Figure 10 is a schematic diagram of the cross section cut by section line BB' in Figure 8;

[0049] Figure 11 is a schematic diagram of the layout of an array substrate after a fourth metal layer is provided according to an embodiment of the present invention;

[0050] Figure 12 is a schematic cross-sectional view along the CC' direction in Figure 11;

[0051] Figure 13 is a schematic diagram of the cross section in the DD' direction of Figure 11;

[0052] Figure 14 is a schematic diagram of the cross section in the direction of section line EE' in Figure 11;

[0053] Figure 15 is a schematic diagram of the layout of the array substrate after the fourth metal layer is provided in another embodiment of the present invention;

[0054] Figure 16 is a schematic diagram of the layout of an array substrate after a fourth metal layer is provided according to another embodiment of the present invention.

[0055] Figure reference numerals: 10 Substrate; 73 Third insulating layer; 20 Buffer layer; 74 Fourth insulating layer; 30 Semiconductor layer; 75 Fifth insulating layer; 31 First active layer pattern; 80 Fourth metal layer; 40 First metal layer T1 First transistor; 41 First gate layer pattern T2 Driving transistor; 41a First pattern T3 Initialization transistor; 41b Second pattern T4 Data writing transistor; 43 Third gate layer pattern T5 Compensation transistor; 44 Fourth gate layer pattern T6 Reset transistor; 45 Fifth gate layer pattern T7 First light-emitting control transistor; 46 Sixth gate layer pattern T8 Second light-emitting control transistor; 47 Seventh gate layer pattern Sn-1 First scan signal line; 48 Eighth gate layer pattern Sn Second scan signal line; 50 Second metal layer Sn+1 Third scan signal line; 51 Via Vres Reference voltage signal line; 60 Third metal layer Data Data line; 71 First insulating layer ELVDD First power supply voltage signal line; 72 Second insulating layer Vint Initialization voltage signal line En Light-emitting control signal line Detailed Implementation

[0056] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that the invention will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore repeated descriptions of them will be omitted. The words “or” and “or” in the specification may mean “and” or “or”.

[0057] The following specific examples illustrate the implementation methods of this application. Those skilled in the art can easily understand the other advantages and effects of this application from the content disclosed herein. This application can also be implemented or applied through other different specific embodiments, and various details in this application can be modified or changed according to different viewpoints and application systems without departing from the spirit of this application. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this application can be combined with each other.

[0058] To address the problems in the prior art, embodiments of the present invention provide an array substrate. Figure 1 shows an equivalent schematic diagram of the pixel driving circuit in the array substrate provided by an embodiment of the present invention. This application designs the layout based on the equivalent schematic diagram of the pixel driving circuit shown in Figure 1. As shown in Figure 1, the pixel driving circuit includes a first transistor T1, a driving transistor T2, an initialization transistor T3, a data writing transistor T4, a compensation transistor T5, a reset transistor T6, a first light-emitting control transistor T7, and a second light-emitting control transistor T8.

[0059] The first transistor T1 and the driving transistor T2 respond to the potential of the second node n2 to turn on and off; the control terminals of the first transistor T1 and the driving transistor T2 are electrically connected to the second node n2.

[0060] Initialization transistor T3 responds to the first scan signal to transmit the initialization voltage to the second node n2. The first terminal of initialization transistor T3 is electrically connected to the initialization voltage signal line Vint, the second terminal of initialization transistor T3 is electrically connected to the second node n2, and the control terminal of initialization transistor T3 is electrically connected to the first scan signal line Sn-1.

[0061] Data writing transistor T4 and compensation transistor T5 respond to the second scan signal to transmit the data voltage and the threshold voltage Vth of the first transistor T1 to the second node n2 and store them in the storage capacitor Cs. The control terminal of data writing transistor T4 is electrically connected to the second scan signal line Sn, the first terminal of data writing transistor T4 is electrically connected to the data line Data, and the second terminal of data writing transistor T4 is electrically connected to the first terminal of the first transistor T1. The control terminal of compensation transistor T5 is electrically connected to the second scan signal line Sn, the first terminal of compensation transistor T5 is electrically connected to the second terminal of the first transistor T1, and the second terminal of compensation transistor T5 is electrically connected to the second node n2. Since the first transistor T1 and the driving transistor T2 are exactly the same size, the threshold voltage of the driving transistor T2 is the same as the threshold voltage of the first transistor T1. The first plate of the storage capacitor Cs is electrically connected to the second node n2, and the second plate of the storage capacitor Cs is electrically connected to the first power supply voltage signal line ELVDD.

[0062] Reset transistor T6 responds to the third scan signal by writing a reference voltage to the first terminal of the OLED element to reset its potential. The control terminal of reset transistor T6 is electrically connected to the third scan signal line Sn+1, the first terminal of reset transistor T6 is electrically connected to the reset voltage signal line Vres, and the second terminal of reset transistor T6 is electrically connected to the anode of the OLED element. Here, the anode of the OLED element is the same as the anode of the OLED.

[0063] The first light-emitting control transistor T7 and the second light-emitting control transistor T8 respond to the light-emitting control signal to drive the OLED light-emitting element to emit light. The control terminal of the first light-emitting control transistor T7 is electrically connected to the light-emitting control signal line En, the first terminal of the first light-emitting control transistor T7 is electrically connected to the first power supply voltage signal line ELVDD, and the second terminal of the first light-emitting control transistor T7 is electrically connected to the first terminal of the driving transistor T2. The control terminal of the second light-emitting control transistor T8 is electrically connected to the light-emitting control signal line En, the first terminal of the second light-emitting control transistor T8 is electrically connected to the second terminal of the driving transistor T2, and the second terminal of the second light-emitting control transistor T8 is electrically connected to the anode of the OLED light-emitting element.

[0064] It should be noted that in the circuits provided in the embodiments of this application, nodes do not represent actual existing components, but rather represent the junctions of related electrical connections in the circuit diagram. In other words, these nodes are equivalent to the junctions of related electrical connections in the circuit diagram. The control terminal of a transistor refers to the gate of the transistor, the first terminal of the transistor refers to either the source or drain of the transistor, and the second terminal of the transistor refers to the other of the source or drain. Transistors include P-type transistors and N-type transistors; this embodiment uses a P-type transistor as an example.

[0065] The array substrate provided in this embodiment of the invention includes multiple pixel driving circuits, but only the layout of one pixel driving circuit is used as an example to describe the invention in detail here. The layout of the other pixel driving circuits can be any of the layouts described in the following embodiments.

[0066] Figures 2 to 16 show the layout design of each layer of the pixel driving circuit in Figure 1 and cross-sectional structural diagrams of some locations. Referring to Figures 2 to 16, the array substrate provided in this embodiment of the invention includes a substrate 10, with the pixel driving circuit located on one side of the substrate 10; the pixel driving circuit includes a first transistor T1 and a driving transistor T2; the array substrate includes a semiconductor layer 30 located on one side of the substrate 10, the semiconductor layer 30 including a first active layer pattern 31; a first metal layer 40 located on the side of the semiconductor layer 30 away from the substrate 10, the first metal layer 40 including a first gate layer pattern 41; the first gate layer pattern 41 and the first active layer pattern 31 overlap in the vertical projection of the substrate 10, and the overlapping portion in the first active layer pattern 31 is the first channel; the first transistor T1 and the driving transistor T2 share the first channel and the first gate layer pattern 41.

[0067] By sharing the channel and gate between the first transistor T1 and the driving transistor T2, layout space for the pixel driving circuit is saved, which is beneficial for use in display panels with high pixel density.

[0068] It should be noted that the first metal layer 40 here forms the gate of the transistor in the pixel driving circuit, and the semiconductor layers located on both sides of the channel form the source or drain of the transistor in the pixel driving circuit.

[0069] For example, the material of the semiconductor layer 30 is low-temperature polycrystalline silicon, but it is not limited thereto. As shown in Figures 9, 10, 12 and 14, a buffer layer 20 is also provided between the substrate 10 and the semiconductor layer 30 to ensure good contact between the substrate 10 and the semiconductor layer 30.

[0070] In this embodiment, the first channel of the first transistor T1 and the driving transistor T2 has a U-shaped pattern, that is, the channel of the first transistor T1 and the driving transistor T2 is bent. Since the brightness of the light-emitting element in the pixel is related to the driving current generated by the driving transistor, and the driving current is controlled by the data signal transmitted by the data line, increasing the channel length of the driving transistor T2 can increase the data voltage range of the data signal, improve the control capability of the driving transistor T2 on the light-emitting element, and thus improve the display effect of the display panel. When the pixel layout space is narrow in some high PPI products, and it is not long enough to achieve a sufficiently long channel, the above-mentioned bent channel can be used to increase the channel length and meet the channel length requirements. Please refer to the white lines in Figures 1 and 2. The first channel is designed as bent, which further lengthens the charging path and the light-emitting path. As shown in Figures 1 and 2, the path from the data writing transistor T4, the first transistor T1, the compensation transistor T5 to the second node n2 is the charging path. The path from the first light-emitting control transistor T7, the driving transistor T2 to the second light-emitting control transistor T8 is the light-emitting path.

[0071] Please continue referring to Figure 2. The first gate layer pattern 41 includes a first pattern 41a and a second pattern 42b connected along a first direction. The area of ​​the first pattern 41a is smaller than the area of ​​the second pattern 41b. The orthographic projection shape of the first gate layer pattern 41 on the substrate 10 is a flag shape. In some embodiments, the first gate layer pattern 41 only includes the second pattern 41b. However, in this embodiment, the addition of the first pattern 41a extends the area of ​​the first gate layer pattern 41, which can increase the area of ​​the subsequently configured storage capacitor Cs, reduce the amount of gate potential change of the driving transistor T2 due to leakage, and improve the voltage regulation effect.

[0072] As shown in Figures 2 and 3, the second pattern 41b overlaps with the middle portion of the first active layer pattern 31, and the first pattern 41a overlaps with either the first or second end of the first active layer pattern 31. That is, the first gate layer pattern 41 is biased to the left or right of the first active layer pattern 31. In this case, the first transistor T1 and the driving transistor T2 can also be considered as a four-terminal device. For example, as shown in Figure 2, the four-terminal device includes a first terminal n1, a second terminal n2 (i.e., the second node), a third terminal n3, and a fourth terminal n4. The first terminal n1 and the fourth terminal n4 can be considered as the source of the four-terminal device, the second terminal n2 as the gate, and the third terminal n3 as the drain. In use, the gate, source, and one drain of the four-terminal device can be used, with the other drain suspended, to achieve the conduction function of the thin-film transistor.

[0073] As shown in Figure 3, in another embodiment, the first pattern 41a overlaps with the second end of the first active layer pattern 31. In this case, the first transistor T1 and the driving transistor T2 can also be regarded as a device with four terminals, including a first terminal n1, a second terminal n2, a third terminal n3 and a fourth terminal n4. The first terminal n1 and the fourth terminal n4 can be regarded as drains, the second terminal n2 can be regarded as gates, and the third terminal n3 can be regarded as sources.

[0074] Please refer to Figures 2 and 3. The pixel driving circuit also includes an initialization transistor T3, a data writing transistor T4, and a compensation transistor T5. The semiconductor layer 30 also includes a third active layer pattern of the initialization transistor T3, a fourth active layer pattern of the data writing transistor T4, and a fifth active layer pattern of the compensation transistor T5.

[0075] The first metal layer 40 also includes a third gate layer pattern 43 for initialization transistor T3, a fourth gate layer pattern 44 for data writing transistor T4, and a fifth gate layer pattern 45 for compensation transistor T5. The third gate layer pattern 43 and the third active layer pattern overlap in their vertical projection on the substrate 10, and the overlapping portion is the channel of the initialization transistor T3. The fourth gate layer pattern 44 and the fourth active layer pattern overlap in their vertical projection on the substrate 10, and the overlapping portion is the channel of the data writing transistor T4. The fifth active layer pattern and the fifth gate layer pattern 45 overlap in their vertical projection on the substrate 10, and the overlapping portion is the channel of the compensation transistor T5.

[0076] The third gate layer pattern 43 and the third active layer pattern of the initialization transistor T3 have two unconnected overlapping parts. The design of the third gate layer pattern 43 and the third active layer pattern of the initialization transistor T3 is equivalent to designing the initialization transistor T3 as a dual-gate transistor, that is, the initialization transistor T3 includes a first sub-transistor T3a and a second sub-transistor T3b.

[0077] The fifth gate layer pattern 45 and the fifth active layer pattern of the compensation transistor T5 have two unconnected overlapping parts. The design of the fifth gate layer pattern 45 and the fifth active layer pattern of the compensation transistor T5 is equivalent to designing the compensation transistor T5 as a dual-gate transistor, that is, the compensation transistor T5 includes a third sub-transistor T5a and a fourth sub-transistor T5b.

[0078] Furthermore, the pixel driving circuit also includes a reset transistor T6, a first light-emitting control transistor T7, and a second light-emitting control transistor T8; then the semiconductor layer 30 also includes a sixth active layer pattern of the reset transistor T6, a seventh active layer pattern of the first light-emitting control transistor T7, and an eighth active layer pattern of the second light-emitting control transistor T8.

[0079] The first metal layer 40 also includes a sixth gate layer pattern 46 of the reset transistor T6, a seventh gate layer pattern 47 of the first light-emitting control transistor T7, and an eighth gate layer pattern 48 of the second light-emitting control transistor T8.

[0080] Among them, the sixth active layer pattern and the sixth gate layer pattern 46 overlap in the vertical projection of the substrate 10, and the overlapping part is the channel of the reset transistor T6; the seventh active layer pattern and the seventh gate layer pattern 47 overlap in the vertical projection of the substrate 10, and the overlapping part is the channel of the first light-emitting control transistor T7; the eighth active layer pattern and the eighth gate layer pattern 48 overlap in the vertical projection of the substrate 10, and the overlapping part is the channel of the second light-emitting control transistor T8.

[0081] In this embodiment, the seventh gate layer pattern 47 and the eighth gate layer pattern 48 are connected, which is equivalent to the light emission control signal line En, and can realize the transmission of light emission control signal.

[0082] Please refer to Figure 2. The semiconductor layer 30, which connects the fifth active layer pattern of the compensation transistor T5, the first active layer patterns of the first transistor T1 and the driving transistor T2, and the eighth active layer pattern of the second light-emitting control transistor T8, is designed with a stepped structure (shown by the elliptical dashed box). This can reduce the parasitic capacitance of this section of semiconductor, reduce the difficulty of charging, reduce the area of ​​the semiconductor layer that can be exposed to light, reduce the influence of photogenerated carrier effects on the drain node of the compensation / or driving transistor, and weaken the current changes caused by potential fluctuations.

[0083] As shown in Figures 9 and 10, a first insulating layer 71 is provided between the semiconductor layer 30 and the first metal layer 40. The first insulating layer 71 can be made of silicon oxide (SiO2). The first insulating layer 71 is not shown in the layout design.

[0084] As shown in Figures 4 and 10, in one embodiment, the array substrate further includes a second metal layer 50 located on the side of the first metal layer 40 away from the substrate 10. The second metal layer 50 overlaps with the vertical projection of the first gate layer pattern 41 onto the substrate 10. The overlapping portion of the vertical projections of the second metal layer 50 and the first gate layer pattern 41 onto the substrate 10 forms a storage capacitor Cs, i.e., the first gate layer pattern 41 is the first electrode of the storage capacitor Cs, and the second metal layer 50 is the second electrode of the storage capacitor Cs. In some embodiments, the overlapping area of ​​the second metal layer 50 and the first gate layer pattern 41 is 120 μm. 2 ~200μm 2 .

[0085] Please refer to Figure 4. The area of ​​the second metal layer 50 is not limited to overlapping only with the first gate layer pattern 41 (see the dashed box in Figure 4). The second metal layer 50 also overlaps with the third active layer pattern of the initialization transistor T3, the fifth active layer pattern of the compensation transistor T5, the fourth active layer pattern of the data writing transistor T4, the seventh active layer pattern of the first light-emitting control transistor T7, and the eighth active layer pattern of the second light-emitting control transistor T8 in their vertical projection onto the substrate 10. The second metal layer 50 shields the semiconductor layer, preventing voltage changes at other nodes and voltage transitions of pulse signals from affecting the potential of the shielded semiconductor layer through capacitive coupling. On the other hand, it blocks light, preventing light incidence from causing changes in the carrier concentration of the semiconductor layer, thereby affecting the potential of that segment of the semiconductor layer.

[0086] As shown in Figure 5, in another embodiment, the second metal layer 50 also shields part of the semiconductor layer of other transistors, as indicated by the dashed box in Figure 5. The difference between the second metal layer 50 in Figure 5 and that in Figure 4 is that the area of ​​the second metal layer 50 is increased, covering a larger area of ​​the semiconductor layer. Compared to the second metal layer 50 shown in Figure 4, the area of ​​the second metal layer 50 in Figure 5 is further increased, i.e., the shielding area is increased. This can better weaken the impact of pulse signal voltage transitions and other node potential couplings on the lower electrode of the capacitor (i.e., the first gate layer pattern 41), reducing gate voltage and current fluctuations in the pixel driving circuit during the compensation and light-emitting phases.

[0087] The second metal layer 50 partially shields the semiconductor layer of the driving transistor T2. This shielding reduces the impact of other node voltage changes and pulse signal transitions on the source potentials of the driving transistor T2 and the compensation transistor T5. According to the MOSFET current formula, the transistor current I∝(Vgs-Vth). 2 According to the formula, shielding the source of the transistor is beneficial to the stability of the compensation current of the compensation transistor T5 and the stability of the light emission current of the driving transistor T2.

[0088] As shown in Figure 6, in another embodiment, the area of ​​the second metal layer 50 overlapping with the semiconductor layer 30 is relatively smaller than that in the design of Figure 5. The reduction in the area of ​​the second metal layer 50 reduces the parasitic capacitance of the second metal layer 50 to other signals, especially the parasitic capacitance of the scan lines and data lines, thereby reducing the delay of Tr (rise time) and Tf (fall time) in the signal transmission process and improving the display uniformity of the panel.

[0089] As shown in Figures 4, 5, 6 and 10, a through hole 51 is provided on the first electrode plate of the storage capacitor Cs. The through hole 51 is opposite to the first gate layer pattern 41. The length of the through hole 51 is denoted as m and the width is denoted as n, which satisfies: m≥1.5μm and n≥1.5μm, so as to reduce the potential fluctuation caused by the capacitive coupling effect on the second electrode plate of the storage capacitor Cs, i.e. the gate of the driving transistor T2.

[0090] As shown in Figure 10, a second insulating layer 72 is provided between the first metal layer 40 and the second metal layer 50. The overlapping portion of the projections of the first metal layer 40 and the second metal layer 50 onto the substrate 10 (shown by the dashed box in the figure) forms a storage capacitor Cs. The dielectric constant of the second insulating layer 72 is greater than that of the first insulating layer 71. Furthermore, referring to Figure 10, a third insulating layer 73 is also provided on the side of the second metal layer 50 away from the substrate 10. The second insulating layer 72 and the third insulating layer 73 are also not shown in the layout design.

[0091] As shown in Figure 7, the pixel driving circuit also includes multiple contact holes (shown in the dashed boxes in the figure), which are disposed on each insulating layer. By setting contact holes on each insulating layer, the semiconductor layer or each metal layer is exposed, and subsequently, the semiconductor layer, each metal layer, and signal lines are electrically connected to provide electrical signals to the semiconductor layer and the metal layer. It should be noted that the planar layout schematic diagram only shows the functional layers included in the array substrate, including the semiconductor layer, the first metal layer, the second metal layer, etc. In practice, adjacent functional layers need to be separated by insulating layers, therefore, an insulating film is provided between adjacent functional layers in practice.

[0092] As shown in Figures 8 to 10, the pixel driving circuit further includes a third metal layer 60 disposed along a first direction, and the third metal layer 60 is located on the side of the second metal layer 50 away from the substrate 10. In this embodiment, the first direction is the left-right direction as seen from the paper, i.e., the lateral direction. The resistivity of the third metal layer 60 is less than that of the first metal layer 40 and the second metal layer 50. Using the third metal layer 60 to transmit the lateral scanning signal can reduce the impedance of the scanning signal and reduce the delay in voltage rise and fall caused by RC loading (capacitive-resistive load) during signal transmission in the circuit.

[0093] As shown in Figure 8, the third metal layer 60 includes a first scan signal line Sn-1, a second scan signal line Sn, a third scan signal line Sn+1, the source and drain electrodes of the data writing transistor T4, the source and drain electrodes of the compensation transistor T5, the source and drain electrodes of the first light-emitting control transistor T7, the source and drain electrodes of the second light-emitting control transistor T8, the first power supply voltage signal line ELVDD, the initialization voltage signal line Vint, and the reset voltage signal line Vres. Specifically, the first scan signal line Sn-1 overlaps with the third gate layer pattern 43 of the initialization transistor T3, and is electrically connected to the third gate layer pattern 43 through a contact hole; the second scan signal line Sn overlaps with the fourth gate layer pattern 44 of the write transistor T4 and the fifth gate layer pattern 45 of the compensation transistor T5, and is electrically connected to the fourth gate layer pattern 44 and the fifth gate layer pattern 45 through a contact hole; the third scan signal line Sn+1 overlaps with the sixth gate layer pattern 46 of the reset transistor T6, and is electrically connected to the sixth gate layer pattern 46 through a contact hole; the third active layer pattern of the initialization transistor T3 overlaps with the initialization voltage signal line Vint, and the initialization voltage signal line Vint... The second metal layer 50 is electrically connected to the third active layer pattern through a contact hole; the second metal layer 50 overlaps with the first power supply voltage signal line ELVDD, and the first power supply voltage signal line is electrically connected to the second metal layer 50 and one end of the seventh active layer pattern of the first light-emitting control transistor T7 through a contact hole; the source and drain electrodes of the data writing transistor T4 overlap with the fourth active layer pattern of the data writing transistor T4; the source and drain electrodes of the compensation transistor T5 overlap with the fifth active layer pattern of the compensation transistor T5, and the source and drain electrodes of the compensation transistor T5 are electrically connected to the first gate layer pattern 41; the source and drain electrodes of the first light-emitting control transistor T7 overlap with the active layer pattern of the first light-emitting control transistor T7, and the source and drain electrodes of the first light-emitting control transistor T7 are electrically connected to one end of the active layer of the first light-emitting control transistor T7.

[0094] In other embodiments, the initialization voltage signal line Vint and the reset voltage signal line Vres can be semiconductor layers. When the initialization voltage signal line Vint and the reset voltage signal line Vres are semiconductor layers, as shown in Figures 2 and 3, they can be disposed on the same layer as the semiconductor layer 30. When the initialization voltage signal line Vint and the reset voltage signal line Vres are semiconductor layers, the semiconductor layer has a high resistance and good ESD resistance. During the fabrication process, static electricity is easily transmitted along the metal or semiconductor layer. The higher the resistance, the easier it is to eliminate the influence of static electricity. A longer propagation path makes it easier for static charge to be dispersed, preventing charge accumulation and breakdown.

[0095] The first power supply voltage signal line ELVDD is connected in parallel with the second metal layer 50 to transmit the first power supply voltage signal, which helps to reduce the voltage drop (IR Drop) that occurs during signal transmission and improve the uniformity of panel current.

[0096] Preferably, the thickness of the third insulating layer 73 is greater than the sum of the thicknesses of the first insulating layer 71 and the second insulating layer 72. Increasing the thickness of the third insulating layer 73 can reduce parasitic capacitance on the signal line and reduce the risk of electrostatic discharge (ESD) damage. This is because the signal line connects multiple transistors in series, forming a complete circuit except for the light-emitting element. With more layers stacked below, it avoids severe ESD damage during the manufacturing process due to insufficient thickness of the third insulating layer 73.

[0097] In another embodiment, the third insulating layer 73 can be a double insulating layer, comprising a first sub-insulating layer and a second sub-insulating layer. The first sub-insulating layer is made of the same material as the second insulating layer 72, thus preventing the second insulating layer 72 from being affected by lattice adaptation stress and thermal adaptation stress, which could affect the stability of the storage capacitor Cs. The first sub-insulating layer has a lower dielectric constant, which can relatively reduce the parasitic capacitance between the third metal layer 60, the second metal layer 50, and the semiconductor layer 30.

[0098] As shown in Figures 11 to 16, the pixel driving circuit further includes a fourth metal layer 80 and a fourth insulating layer 74. The fourth metal layer 80 is disposed along a second direction on the side of the substrate 10 away from the third insulating layer 73, and the fourth insulating layer 74 is disposed on the side of the fourth metal layer 80 away from the substrate 1. Here, the second direction is the vertical direction as seen from the paper, i.e., the longitudinal direction. As shown in Figure 11, the fourth metal layer 80 includes a data line Data and a first power supply voltage signal line ELVDD (longitudinal direction). Figure 12 shows a schematic cross-sectional view taken along section line CC' in Figure 11. As shown in Figure 12, in some embodiments, the size of the contact holes on the fourth insulating layer 74 is larger than the size of the contact holes on the third insulating layer 73. The fourth insulating layer 74 can be an organic layer, and the contact holes on the organic layer can be obtained through exposure and development. The larger size of the contact holes on the organic layer ensures that the openings are complete. The contact holes on the third insulating layer 73 are inorganic layers, and the third insulating layer 73 can be obtained through a process. The smaller size of the contact holes on the inorganic insulating layer saves space.

[0099] Please refer to Figure 11. The second metal layer 50 overlaps with the fourth active layer pattern on the data writing transistor T4 (see the dashed box). Here, the second metal layer 50 can shield the semiconductor layer on the data writing transistor T4, attracting more of the power on the data line Data and the second scan signal line Sn to the signal line of the fourth metal layer 80 that transmits the first power supply voltage signal (vertical). This enhances the shielding effect on the data line Data and the second scan signal line Sn, and reduces the impact of the two pulse signals on the potential of other nodes in the circuit.

[0100] Figure 13 shows a schematic cross-sectional view taken along section line DD' in Figure 11. As shown in Figure 13, a fifth insulating layer 75 is provided on the side away from the fourth metal layer 80. In some embodiments, the fifth insulating layer 75 can be an organic layer, which can serve a planarization function. A contact hole is formed in the fourth insulating layer 74, exposing the first power supply voltage signal line ELVDD (vertical direction) below the contact hole, so that the first power supply voltage signal line ELVDD (lateral direction) provided on the fourth insulating layer 74 forms contact with the source and drain electrodes of the first light-emitting control transistor T7 through the contact hole, thereby making the source and drain electrodes of the first light-emitting control transistor T7 electrically connected to the first power supply voltage signal line ELVDD.

[0101] The setting of the longitudinal signal transmission line can transmit the first power supply voltage signal in both the horizontal and vertical directions, improving the uniformity of the panel during the initialization process; the longitudinal signal line covers part or all of the left semiconductor, which can reduce the influence of light incident on the carrier concentration of the semiconductor layer in that area, and reduce the drain potential fluctuation caused by the photogenerated carrier effect.

[0102] As shown in Figures 11 and 14, the fourth metal layer 80 also includes an anode signal transmission layer, which is electrically connected to the source and drain electrodes of the second light-emitting control transistor T8 through contact holes. It should be noted that the contact holes on the anode signal transmission layer and the contact holes of the source and drain electrodes of the second light-emitting control transistor T8 are offset in the thickness direction of the substrate 10.

[0103] As shown in Figure 15, in another embodiment, the fourth metal layer 80 further includes an initialization voltage signal line Vint. The initialization voltage signal line Vint in the fourth metal layer 80 is arranged vertically and connected to the horizontally routed initialization voltage signal line Vint through contact holes formed on the fourth insulating layer 74. The initialization voltage signal line Vint is designed as a horizontal and vertical interlaced mesh structure to improve the uniformity of the panel during the anode reset process. In other embodiments, the reset voltage signal line Vres can also be designed as a horizontal and vertical interlaced mesh structure.

[0104] As shown in Figure 16, the fourth metal layer 80 also includes a second power supply voltage signal line ELVSS, which transmits a second power supply voltage signal. The second power supply voltage signal line ELVSS is not connected to any signal lines below it, and is used to reduce the IR drop (voltage drop) of the ELVSS signal, improving the current uniformity of the panel. In some other embodiments, the fourth metal layer 80 may also be other signal lines, not electrically connected to the signal lines below it; those skilled in the art can make specific settings according to actual needs.

[0105] A complete pixel includes any pixel circuit or a combination thereof shown in Figures 11, 15 and 16.

[0106] This invention also provides a display panel, including the array substrate described above, which can achieve all the technical effects of the array substrate described above, and will not be repeated here.

[0107] This invention also provides a display device, including the array substrate described above, which achieves all the technical effects of the array substrate described above, and will not be repeated here. The display device can be a mobile phone, computer, camera, watch, camcorder, projector, billboard, car display, etc.

[0108] The display panel and display device provided by the present invention have the following advantages:

[0109] The array substrate includes multiple pixel driving circuits, each including a first transistor and a driving transistor. The array substrate includes a substrate, a semiconductor layer, and a first metal layer. The semiconductor layer is located on one side of the substrate and includes a first active layer pattern. The first metal layer is located on the side of the semiconductor layer away from the substrate and includes a first gate layer pattern, which overlaps with the first active layer pattern. The overlapping portion forms a first channel in the first active layer pattern. The first transistor and the driving transistor share the first channel and the first gate layer pattern. The pixel driving circuit layout of the array substrate provided by this invention saves space and is suitable for display panels with high-density pixel arrangement.

[0110] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. An array substrate, characterized in that, It includes multiple pixel driving circuits, each pixel driving circuit including a first transistor and a driving transistor; The array substrate includes: Substrate; A semiconductor layer is located on one side of the substrate, the semiconductor layer including a first active layer pattern; A first metal layer is located on the side of the semiconductor layer away from the substrate. The first metal layer includes a first gate layer pattern, which overlaps with a first active layer pattern. The overlapping portion forms a first channel on the first active layer pattern. The first transistor and the driving transistor share the first channel and the first gate layer pattern.

2. The array substrate according to claim 1, characterized in that, The pattern of the first trench pipe is a zigzag shape.

3. The array substrate according to claim 2, characterized in that, The first gate layer pattern includes a first pattern and a second pattern connected along a first direction, wherein the area of ​​the first pattern is smaller than the area of ​​the second pattern. Wherein, the second pattern overlaps with the middle part of the first active layer pattern, and the first pattern overlaps with the first end or the second end of the first active layer pattern.

4. The array substrate according to claim 3, characterized in that, The pixel driving circuit also includes an initialization transistor, a data writing transistor, and a compensation transistor; The semiconductor layer further includes a third active layer pattern of the initialization transistor, a fourth active layer pattern of the data writing transistor, and a fifth active layer pattern of the compensation transistor. The first metal layer further includes a third gate layer pattern of the initialization transistor, a fourth gate layer pattern of the data writing transistor, and a fifth gate layer pattern of the compensation transistor; The third gate layer pattern overlaps with the third active layer pattern, the fourth gate layer pattern overlaps with the fourth active layer pattern, and the fifth gate layer pattern overlaps with the fifth active layer pattern.

5. The array substrate according to claim 4, characterized in that, The pixel driving circuit also includes a reset transistor, a first light-emitting control transistor, and a second light-emitting control transistor. The semiconductor layer further includes a sixth active layer pattern of the reset transistor, a seventh active layer pattern of the first light-emitting control transistor, and an eighth active layer pattern of the second light-emitting control transistor. The first metal layer further includes a sixth gate layer pattern of the reset transistor, a seventh gate layer pattern of the first light-emitting control transistor, and an eighth gate layer pattern of the second light-emitting control transistor. The sixth active layer pattern overlaps with the sixth gate layer pattern, the seventh active layer pattern overlaps with the seventh gate layer pattern, and the eighth active layer pattern overlaps with the eighth gate layer pattern.

6. The array substrate according to claim 5, characterized in that, The pixel driving circuit also includes a storage capacitor; The array substrate further includes a second metal layer located on the side of the first metal layer away from the substrate; the second metal layer overlaps with the pattern of the first gate layer, and the overlapping portion of the vertical projection of the first gate layer pattern and the second metal layer on the substrate forms the storage capacitor.

7. The array substrate according to claim 6, characterized in that, The area where the second metal layer and the first gate layer pattern intersect is 120 μm 2 ~ 200 μm 2 .

8. The array substrate according to claim 7, characterized in that, It also includes a third metal layer disposed along a first direction, located on the side of the second metal layer away from the substrate; the third metal layer includes a first scan signal line, a second scan signal line, and a third scan signal line; The first scan signal line overlaps with the third gate layer pattern of the initialization transistor; The second scan signal line overlaps with the fourth gate layer pattern of the write transistor and the fifth gate layer pattern of the compensation transistor; The third scan signal line overlaps with the sixth gate layer pattern of the reset transistor.

9. The array substrate according to claim 8, characterized in that, The third metal layer further includes an initialization voltage signal line, a reset voltage signal line, and a first power supply voltage signal line; The third active layer pattern of the initialization transistor overlaps with the initialization voltage signal line; The second metal layer overlaps with the first power supply voltage signal line; The pattern of the sixth active layer of the reset transistor overlaps with the reset voltage signal line.

10. The array substrate according to claim 9, characterized in that, It also includes a fourth metal layer disposed along the second direction, located on the side of the third metal layer away from the substrate.

11. The array substrate according to claim 10, characterized in that, The fourth metal layer includes a data line and the first power supply voltage signal line; the data line overlaps with the fourth active layer pattern of the data writing transistor; the first power supply voltage signal line overlaps with the third metal layer.

12. A display panel, characterized in that, Includes the array substrate as described in any one of claims 1 to 11.

13. A display device, characterized in that, Includes the array substrate as described in any one of claims 1 to 11.

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