Server, baseboard management controller, and management method for server

Abstract

The embodiments of the present application provide a server, a baseboard management controller (BMC), and a management method for a server. The server comprises a BMC and a plurality of server nodes, wherein the BMC comprises a plurality of input / output (IO) interface groups; each IO interface group comprises multiple communication interfaces; the server nodes are connected to communication interfaces of the corresponding IO interface groups; and the BMC is used for monitoring the server nodes connected to the IO interface groups. Thus, in the embodiments of the present application, a plurality of IO interface groups are integrated by means of a BMC, and multiple communication interfaces in each IO interface group are connected to corresponding server nodes, thereby achieving the aim of one BMC monitoring a plurality of server nodes on the basis of normal connection and communication between the BMC and the server nodes corresponding to the IO interface groups.

Description

Server, baseboard management controller, and server management method

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on December 29, 2023, with application number 202311871052.1 and application name “A server, baseboard management controller and server management method”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present invention relates to the technical field of servers, and in particular to a server, a baseboard management controller, and a server management method. Background Art

[0003] Current server architectures typically consist of multiple processors of the same model, interconnected by memory (also known as cache), such as two-way or four-way processors. These processors run the same operating system and share the server's memory and input / output (IO) resources. With advancements in manufacturing processes, the performance of individual processors has become increasingly powerful, allowing most applications to be handled by a single processor. Therefore, single-processor, single-socket servers have become a key trend in future development.

[0004] The server includes a baseboard management controller (BMC), which is used to monitor the operation of the server's processor, such as monitoring the processor's temperature, fan speed, power supply status, operating system status, etc.

[0005] Summary of the Invention

[0006] The embodiments of the present application provide a server, a baseboard management controller, and a server management method, which are used to enable one BMC to manage multiple server nodes.

[0007] In the first aspect, an embodiment of the present application provides a server, including a baseboard management controller and multiple server nodes, the baseboard management controller includes multiple input and output IO interface groups, each IO interface group includes multiple communication interfaces, the server node is connected to the communication interface of the corresponding IO interface group, and the baseboard management controller is used to monitor the server nodes connected to the IO interface group. Therefore, the embodiment of the present application integrates multiple IO interface groups through the baseboard management controller, each IO interface group includes multiple communication interfaces for connecting and communicating with the server node, and the multiple communication interfaces in each IO interface group are connected to the corresponding server node, thereby achieving the purpose of one BMC monitoring multiple server nodes on the basis of normal connection and communication between the BMC and the server node corresponding to the IO interface group. Moreover, since multiple server nodes share one BMC, the cost of the server is reduced.

[0008] In one possible implementation, the multiple communication interfaces include a first multiplexed high-speed interface, the baseboard management controller also includes a first processing unit and multiple controllers, the first processing unit is connected between the first multiplexed high-speed interface and the multiple controllers, the server node includes a second multiplexed high-speed interface and a second processing unit, the second multiplexed high-speed interface is connected to both the first multiplexed high-speed interface and the second processing unit; the first processing unit is used to encapsulate low-speed information from the multiple controllers into high-speed information and send it to the second processing unit via the first multiplexed high-speed interface and the second multiplexed high-speed interface, and the second processing unit is used to parse the high-speed information into multiple low-speed information. Thus, on the basis of realizing one BMC managing multiple server nodes, the number of pins provided by the BMC is reduced, and transmission efficiency is improved by replacing the low-speed interface with a high-speed interface.

[0009] In another possible implementation, multiple IO interface groups share a first multiplexed high-speed interface and a first processing unit. The various controllers corresponding to each IO interface group are all connected to the first processing unit. Multiple server nodes share a second multiplexed high-speed interface and a second processing unit. Each server node is connected to the second processing unit. This further reduces the number of BMC pins.

[0010] In another optional embodiment, the first processing unit is configured to encapsulate multiple low-speed messages and the target server node's identifier, intended for the target server node, into high-speed messages. The second processing unit then parses the high-speed messages to obtain multiple low-speed messages and the target server node's identifier, and then transmits the multiple low-speed messages to the corresponding information channels of the target server node based on the target server node's identifier. Thus, by including the target server node's identifier in the transmitted messages, the BMC can accurately control the corresponding server node.

[0011] Optionally, the multiple communication interfaces include: a high-speed serial computer expansion bus standard PCIe interface, an enhanced peripheral management interface eSPI, a low frame rate LPC interface, an integrated circuit bus I2C, an enhanced two-wire serial bus I3C interface, a serial peripheral interface SPI, a universal asynchronous receiver and transmitter UART interface general-purpose IO GPIO interface and a platform environment control interface PECI.

[0012] On the second aspect, an embodiment of the present application provides a baseboard management controller, including multiple input and output IO interface groups, each IO interface group includes multiple communication interfaces, the server node is connected to the communication interface of the corresponding IO interface group, and the management controller is used to monitor the server nodes connected to the IO interface group. The baseboard management controller integrates multiple IO interface groups, each IO interface group includes multiple communication interfaces for connecting and communicating with the server node, and the multiple communication interfaces in each IO interface group are connected to the corresponding server node, realizing the monitoring of multiple server nodes on the basis of normal connection and communication between a BMC and the server node corresponding to the IO interface group. Moreover, since multiple server nodes share one BMC, it helps to reduce server costs.

[0013] In one possible implementation, the multiple communication interfaces include a first multiplexed high-speed interface for connecting to corresponding server nodes. The baseboard management controller also includes a first processing unit and multiple controllers. The first processing unit is connected between the first multiplexed high-speed interface and the multiple controllers. The first processing unit is used to encapsulate low-speed information from the multiple controllers into high-speed information and send it to the server node through the first multiplexed high-speed interface. The transmission speed of the low-speed information is lower than the transmission speed of the high-speed information.

[0014] Optionally, the baseboard management controller further includes multiple graphics processors (GPUs). Each IO interface group includes a PCIe interface, and the PCIe interface of each IO interface group is connected to a corresponding graphics processor. Each GPU is configured to obtain image information from a server node connected via the corresponding IO interface group, or to send image information to a connected server node via the corresponding IO interface group. In this way, a single BMC can perform GPU processing on image information from multiple server nodes.

[0015] In another possible implementation, the baseboard management controller also includes a video graphics compression module, an Ethernet interface, a display interface and a switch switching circuit; one end of the video graphics compression module is connected to the first end of the switch switching circuit, and the other end of the video graphics compression module is connected to the remote display through the Ethernet interface; the second end of the switch switching circuit is connected to the local display through the display interface; the third end of the switch switching circuit is connected to N GPUs; the switch switching circuit is used to: obtain processed image information from one of the N GPUs; and send the obtained image information to the video graphics compression module for display on the remote display through the Ethernet interface, or send the obtained image information to the local display through the display interface for display.

[0016] Optionally, one GPU may be connected to the PCIe interface of each IO interface group, so as to enable one GPU to manage image displays of multiple server nodes.

[0017] In another possible implementation, the multiple communication interfaces include: a high-speed serial computer expansion bus standard PCIe interface, an enhanced peripheral management interface eSPI, a low frame rate LPC interface, an integrated circuit bus I2C, an enhanced two-wire serial bus I3C interface, a serial peripheral interface SPI, a universal asynchronous receiver and transmitter UART interface general-purpose IO GPIO interface and a platform environment control interface PECI.

[0018] In a third aspect, embodiments of the present application provide a server management method, which is applied to a baseboard management controller (BMC), wherein the BMC includes multiple input / output (IO) interface groups, each IO interface group being configured to connect to a corresponding server node, and each IO interface group including multiple communication interfaces connected to the corresponding server node. A target server node is managed via a target IO interface group, wherein the target IO interface group is any IO interface group from the multiple IO interface groups, and the target server node is a target server node connected to the target IO interface.

[0019] In one possible implementation, the multiple communication interfaces include a first multiplexed high-speed interface, the baseboard management controller also includes a first processing unit and multiple controllers, the first processing unit is connected between the first multiplexed high-speed interface and the multiple controllers, the server node includes a second multiplexed high-speed interface and a second processing unit, the second multiplexed high-speed interface is connected to both the first multiplexed high-speed interface and the second processing unit; the first processing unit encapsulates low-speed information from the multiple controllers into high-speed information and sends it to the second processing unit through the first multiplexed high-speed interface and the second multiplexed high-speed interface, and the second processing unit is used to parse the high-speed information into multiple low-speed information.

[0020] In another possible implementation, the baseboard management controller also includes multiple image processors, each IO interface group includes a PCIe interface, the PCIe interface of each IO interface group is connected to the corresponding image processor, and each GPU is used to obtain image information from the server node connected to the corresponding IO interface group, or to enable each GPU to send image information to the connected server node through the corresponding IO interface group.

[0021] In another possible implementation, the first processing unit is used to encapsulate multiple low-speed information and the identifier of the target server node sent to the target server node into high-speed information; the second processing unit parses the high-speed information to obtain multiple low-speed information and the identifier of the target server node, and sends the multiple low-speed information to the information channel corresponding to the target server node according to the identifier of the target server node.

[0022] In one possible implementation, the baseboard management controller further includes a video graphics compression module, an Ethernet interface, a display interface, and a switching circuit. One end of the video graphics compression module is connected to a first end of the switching circuit, and the other end of the video graphics compression module is connected to a remote display via the Ethernet interface. A second end of the switching circuit is connected to a local display via the display interface. A third end of the switching circuit is connected to N GPUs. The switching circuit is configured to: obtain processed image information from one of the N GPUs; and transmit the obtained image information to the video graphics compression module for display on the remote display via the Ethernet interface, or to transmit the obtained image information to the local display via the display interface for display. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 is a schematic diagram of the connection between the BMC and the server in a traditional solution;

[0024] FIG2 is a schematic diagram of the structure of a server provided in an embodiment of the present application;

[0025] FIG3 is a schematic diagram of the structure of another server provided in an embodiment of the present application;

[0026] FIG4 is a schematic diagram of the structure of another server provided in an embodiment of the present application;

[0027] FIG5 is a schematic diagram of TDM multiplexing;

[0028] FIG6 is a schematic diagram of a method for managing multiple server nodes by one BMC according to an embodiment of the present application;

[0029] FIG7 is a schematic diagram showing a structure of a GPU including multiple GPU virtual modules according to an embodiment of the present application;

[0030] Figure 8 is a schematic diagram of the structure of a BMC integrating multiple GPUs;

[0031] FIG9 is a schematic diagram after adding a switch switching circuit. DETAILED DESCRIPTION

[0032] A server is a type of computing device that runs faster and handles higher loads than regular computers. It provides computing or application services to other clients (such as PCs and smartphones) on a network. Servers feature high-speed processor computing power, long-term reliable operation, strong external data throughput, and excellent scalability. Servers are categorized by their physical form factor into rack-mount, blade, tower, and cabinet types.

[0033] Current server architectures typically consist of multiple processors of the same model, interconnected by memory (also known as cache) coherence. These processors run the same operating system and share the server's memory and input / output (IO) resources.

[0034] Currently, servers include a baseboard management (BMC), which monitors the health of the server's processor, such as temperature, fan speed, power supply status, and operating system status. The BMC can also perform operations such as firmware upgrades on the server's processor even when the server is not powered on, and can record critical logs when the server's processor crashes.

[0035] See Figure 1, which is a schematic diagram of the structure of the server in the relevant solution.

[0036] Figure 1 (a) shows a BMC connected to the server's main processor through various communication interfaces. The BMC can also manage other slave CPUs in the server through the main central processing unit (CPU).

[0037] Figure 1 (b) shows a BMC connected to the server's south bridge through various communication interfaces. The BMC manages the server's main CPU and other slave CPUs through the south bridge.

[0038] The various types of communication interfaces shown in Figure 1 include at least one of the following communication interfaces: a high-speed serial computer expansion bus standard Peripheral Component Interconnect Express (PCIe) interface, an enhanced serial peripheral interface (eSPI) and a low frame count (LPC) interface, an integrated circuit bus (I2C) interface / an enhanced two-wire serial bus (Improved Inter-Integrated Circuit, I3C) interface, a serial peripheral interface (SPI), a universal asynchronous receiver-transmitter (UART) interface, a general-purpose input and output (GPIO) interface, a system management bus (SMBus) interface, or a platform environment control interface (PECI).

[0039] Among the above communication interfaces, the PCIe interface can connect the graphics processing unit (GPU) and the processor. The eSPI / LPC interface is used for communication between the BMC and the BIOS. The PECI is a communication channel used to obtain processor temperature, internal management information, debug diagnostic information, etc. The I3C / I2C interface is a communication channel used to obtain processor temperature, internal management information, debug diagnostic information, etc. The SPI is used to trigger the processor BIOS to load the upgrade channel. The UART interface is a channel for obtaining log information of various components. The GPIO interface is used to obtain processor exception information and respond in a timely manner. The SMBus interface is used to manage the system and power management control bus.

[0040] Currently, a single BMC can only monitor the operating status of a single server's processor. However, with advancements in manufacturing processes, single processors are supporting more and more cores and achieving increasingly powerful performance. Most applications can be run on a single processor, making single-socket servers the future trend. Therefore, using a single BMC to monitor the processors of multiple single-socket servers can reduce the number of BMCs required when integrating multiple single-socket servers, saving costs.

[0041] In view of the above problems, an embodiment of the present application provides a server, which includes a baseboard management controller and multiple server nodes. The baseboard management controller integrates multiple IO interface groups, each IO interface group including multiple communication interfaces for connecting and communicating with the server nodes, and the multiple communication interfaces in each IO interface group are connected to the multiple communication interfaces of the corresponding server nodes. This achieves the purpose of a baseboard management controller (BMC) monitoring multiple server nodes on the basis of normal connection and communication between the baseboard management controller and the server nodes corresponding to the IO interface group. The server provided by the embodiment of the present application is described in detail below in conjunction with the accompanying drawings.

[0042] To better illustrate the server provided in the embodiments of the present application, the following example illustrates a BMC connected to two server nodes via two IO interface groups. However, a BMC does not have only two IO interface groups; it can also have three, four, or five IO interface groups, each of which can connect to a server node.

[0043] Referring to Figure 2, this figure is a schematic diagram of the structure of a server provided in an embodiment of the present application. The server includes a BMC and multiple server nodes.

[0044] A server node is a device that includes a processor, such as a single-socket server. In addition to the processor, a server node also includes a south bridge, a complex programmable logic device (CPLD), or a power supply unit (PSU) that resides on the same device as the processor.

[0045] In the embodiment of the present application, the BMC includes two IO interface groups, and the two IO interface groups are connected to two server nodes. Specifically, IO interface group 1 is connected to server node 1, and IO interface group 2 is connected to server node 2.

[0046] The embodiments of the present application do not specifically limit the objects to which the IO interface group connects to the server node. For example, the IO interface group may connect to the CPU of the server node, the south bridge of the server node, the CPLD of the server node, or the PSU of the server node. Furthermore, the IO interface group may connect to at least two of the CPU, south bridge, CPLD, and PSU of the server node.

[0047] The embodiment of the present application does not specifically limit the number of interfaces in each IO interface group. Each IO interface group includes multiple communication interfaces. For example, the multiple communication interfaces may include at least one of a PCIe interface, an eSPI, an LPC interface, a PECI, an I3C / I2C interface, an SPI, an SMBus interface, a UART interface, and a GPIO interface. And the number of each communication interface may be 1 or more. If each IO interface group includes the above content, it can be ensured that the BMC can communicate and connect with the server node corresponding to each IO interface group through each IO interface group. Figure 2 shows that each IO interface group includes all communication interfaces of a PCIe interface, an eSPI, an LPC interface, a PECI, an I3C / I2C interface, an SPI, an SMBus interface, a UART interface, and a GPIO interface. Among them, each communication interface is connected to the corresponding communication interface on the server node, for example, the GPIO interface of the IO interface group is connected to the GPIO interface of the server node, and the PCIe interface of the IO interface group is connected to the PCIe interface of the server node, etc.

[0048] Among them, the GPIO interface and UART interface in the server node are connected to the CPLD of the server node, the SMBUS interface is connected to the PSU, and other interfaces (such as PCIe interface, I3C / I2C interface, PECI, eSPI) are connected to the processor or south bridge.

[0049] In the BMC, the interface corresponding to each I / O interface group is connected to the corresponding controller. For example, the GPIO interface of I / O interface group 1 is connected to the corresponding GPIO controller, and the I2C / I3C interface of I / O interface group 1 is connected to the corresponding I2C / I3C controller. The specific connection method is shown in Figure 2. The controllers corresponding to all communication interfaces are connected to the BMC processor. In addition to connecting to the processor, the PCIe controller is also connected to the BMC's GPU. The BMC processor is used to exchange data with the corresponding server node through the controller of the corresponding communication interface. The GPU also exchanges data with the corresponding server node through the PCIe controller.

[0050] In an embodiment of the present application, the BMC monitors the server nodes connected to the IO interface group. Specifically, the BMC monitors the server nodes connected to the IO interface group, including: monitoring the status of the server nodes, including temperature, voltage, fan, and power supply, resetting the server nodes through reset and power cycle, and recording abnormal operation data or abnormality logs.

[0051] The embodiment of the present application does not specifically limit the manner in which the BMC monitors the server nodes connected to the IO interface group.

[0052] In one example, a polling method may be used to monitor multiple server nodes.

[0053] For example, at time T1, the BMC monitors server node 1 through I / O interface group 1. At time T2, it monitors server node 2 through I / O interface group 2. At time T3, it monitors server node 1. At time T4, it monitors server node 2. And so on, monitoring multiple server nodes in sequence.

[0054] The above T1, T2, T3, T4, etc. are used to represent multiple consecutive moments. The time intervals between the adjacent moments in T1, T2, T3, T4 can be the same or different, and this application does not specifically limit this.

[0055] In another example, the BMC can monitor multiple server nodes through manual control in the switching interface. Compared with polling and other methods, this method provides a better user experience.

[0056] For example, the web interface corresponding to the BMC includes a switching interface. A switching button is provided on the switching interface. Users can trigger the switching button to monitor multiple server nodes. This triggering method can be a single click, double click, or voice control, and is not specifically limited in this application.

[0057] Alternatively, the switching interface includes a server node list corresponding to multiple server nodes, and the user directly triggers a server node in the server node list to monitor the triggered server node.

[0058] In addition, the switch interface can also display input information. Users can enter the address of a specific server node in the switch interface, and the BMC will control the specified server node. For example, if a user enters the MAC address corresponding to server node 1 in the switch interface, the BMC will manage server node 1 based on the MAC address of server node 1.

[0059] In this way, the embodiment of the present application integrates multiple IO interface groups through BMC, each IO interface group includes multiple communication interfaces for connecting and communicating with server nodes, and the multiple communication interfaces in each IO interface group are connected to the multiple communication interfaces of the corresponding server nodes, thereby achieving the purpose of one BMC managing multiple server nodes on the basis of normal connection and communication between the BMC and the server nodes corresponding to the IO interface group.

[0060] Furthermore, considering the direct connection between the communication interfaces of the BMC's IO interface group and the server nodes shown in Figure 2, the BMC needs to provide a large number of pins to support the various types and quantities of interfaces. Excessive pin counts will increase the size of BMC-related devices, such as the BMC chip, thereby affecting the cost of the BMC chip. Furthermore, if the BMC were a separate plug-in or daughter card, each server node would require a set of IO interfaces to connect to the BMC. This would result in a large number of signals between the BMC and N server nodes, making it difficult to implement engineering solutions.

[0061] Based on this, an embodiment of the present application also provides a solution, which multiplexes multiple low-speed interfaces into a high-speed serial interface based on the above solution. In other words, one high-speed serial interface replaces multiple low-speed interfaces, thereby reducing the number of pins provided by the BMC.

[0062] The communication interface connecting the IO interface group to the server node includes a low-speed interface and a high-speed interface. The information transmission speed of the low-speed interface is lower than a preset speed threshold, and the information transmission speed of the high-speed interface is greater than the preset speed threshold. For example, among the various communication interfaces connected to the server node included in the above-mentioned IO interface group, the low-speed interface is an I2C / I3C interface, a UART interface, a GPIO interface, and an SMBUS interface. The high-speed interface is an interface such as PCIe, eSPI, LPC interface, PECI, etc. In the embodiment of the present application, one high-speed interface replaces multiple low-speed interfaces.

[0063] The embodiment of the present application does not specifically limit the size of the preset speed threshold. For example, the preset speed threshold can be 50 Mbps, 200 Kbps, 100 Kbps, etc.

[0064] The embodiments of the present application do not specifically limit the usage specifications of the high-speed interface. For example, the usage specification may be a low voltage differential signaling (LVDS) channel protocol or an LTPI protocol.

[0065] The following uses the example of multiplexing low-speed interfaces including I2C, I3C, UART, GPIO, and SMBUS into a high-speed interface to illustrate the multiplexing method. Other embodiments may also involve other customized low-speed interfaces, which can be multiplexed with existing low-speed interfaces into a high-speed interface. This will not be discussed here.

[0066] See FIG3 , which is a schematic diagram of the structure of another server provided in an embodiment of the present application.

[0067] In an embodiment of the present application, the multiple communication interfaces of each IO interface group in the BMC include a first multiplexed high-speed interface, and the first multiplexed high-speed interface is used to multiplex the low-speed information sent by the multiple low-speed interfaces in Figure 2. The multiple low-speed interfaces are, for example, an I2C / I3C interface, a UART interface, a GPIO interface, and an SMBUS interface. Specifically, the BMC also includes multiple controllers and a first processing unit, and the multiple controllers are, for example, an I2C / I3C controller, a UART controller, a GPIO controller, and an SMBUS controller. The first processing unit is connected between the first multiplexed high-speed interface and the multiple controllers, and the multiple controllers interact with the first processing unit. The first processing unit is connected to the server node through the first multiplexed high-speed interface.

[0068] In an embodiment of the present application, each IO interface group corresponds to a first processing unit, and the IO interface group is connected to the corresponding first processing unit. For example, IO interface group 1 is connected to one first processing unit, and IO interface group 2 is connected to another first processing unit.

[0069] In one example, the I2C / I3C controller, the UART controller, the GPIO controller, and the SMBUS controller respectively send the sent I2C / I3C information, UART information, GPIO information, and SMBUS information to the first processing unit. The first processing unit encapsulates the I2C / I3C information, UART information, GPIO information, and SMBUS information into first high-speed serial information (high-speed information) according to preset rules, and sends the first high-speed serial information to the corresponding server node through the first multiplexed high-speed interface of the IO interface group and the first multiplexed high-speed interface of the corresponding server node. The first high-speed serial information is used to represent the high-speed serial information sent by the first processing unit of the BMC.

[0070] For example, the first processing unit corresponding to IO interface group 1 obtains low-speed information sent by the corresponding multiple controllers, such as I2C / I3C information sent by the I2C / I3C controller, UART information sent by the UART controller, GPIO information sent by the GPIO controller, and SMBUS information sent by the SMBUS controller. Then, the first processing unit encapsulates the multiple low-speed information into first high-speed serial information according to preset rules, and sends the first high-speed serial information to server node 1 through the first multiplexed high-speed interface of IO interface group 1.

[0071] In another example, the first multiplexed high-speed interface of the IO interface group receives second high-speed serial information from the corresponding server node. The first processing unit corresponding to the IO interface group parses the second high-speed serial information according to preset rules to obtain multiple low-speed information, for example, parsing to obtain I2C / I3C information, UART information, GPIO information, and SMBUS information. Then, the first processing unit sends the multiple low-speed information to the corresponding controller, which then sends it to the processor or GPU through the controller. The second high-speed serial information is used to represent the high-speed serial information received by the first processing unit of the BMC.

[0072] For example, the first multiplexed high-speed interface corresponding to IO interface group 1 receives second high-speed serial information from server node 1 and sends it to the corresponding first processing unit. The first processing unit parses the second high-speed serial information based on preset rules to obtain I2C / I3C information, UART information, GPIO information, and SMBUS information. The first processing unit then sends the parsed I2C / I3C information to the corresponding I2C / I3C controller, the UART information to the corresponding UART controller, the GPIO information to the corresponding GPIO controller, and the SMBUS information to the corresponding SMBUS controller.

[0073] The embodiments of the present application do not specifically limit the content of the preset rules. For example, the preset rules may be time-decomposition multiplexing rules, and the preset rules may also be to encapsulate I2C / I3C information, UART information, GPIO information and SMBUS information in a fixed order, for example, the encapsulated high-speed serial information is {I2C / I3C information, UART information, GPIO information, SMBUS information}.

[0074] It should be noted that the server node corresponding to the IO interface group includes a second multiplexed high-speed interface, a second processing unit, and multiple information transmission channels, and the second processing unit is connected between the second multiplexed high-speed interface and the multiple information transmission channels. The second multiplexed high-speed interface is used to communicate with the first multiplexed high-speed interface of the IO interface group. The second multiplexed high-speed interface is used to multiplex the low-speed information sent by the multiple low-speed interfaces of the server node in Figure 2. The multiple low-speed interfaces are, for example, I2C / I3C interfaces, UART interfaces, GPIO interfaces, and SMBUS interfaces. The multiple information transmission channels include I2C / I3C information transmission channels, UART information transmission channels, GPIO information transmission channels, and SMBUS information transmission channels.

[0075] For example, IO interface group 1 communicates with the second multiplexed high-speed interface of server node 1 through the first multiplexed high-speed interface.

[0076] The server node also includes a second processing unit connected to the second multiplexed high-speed interface. To accurately transmit information between the BMC and the server node and avoid transmission errors and omissions, the second processing unit uses the same preset rules as the first processing unit but performs the opposite operation of the first processing unit.

[0077] Example 1: The I2C / I3C controller, UART controller, GPIO controller, and SMBUS controller in IO interface group 2 transmit I2C / I3C information, UART information, GPIO information, and SMBUS information to the first processing unit. The first processing unit corresponding to IO interface group 2 encapsulates the I2C / I3C information, UART information, GPIO information, and SMBUS information into first high-speed serial information using time-division multiplexing. For example, the first high-speed serial information is {I2C / I3C information, UART information, GPIO information, SMBUS information}. The BMC sends the first high-speed serial information to the second processing unit corresponding to server node 2 via the first multiplexed high-speed interface in IO interface group 2.

[0078] The second processing unit parses the first high-speed serial information {I2C / I3C information, UART information, GPIO information, SMBUS information} using the same time-division multiplexing method as the first processing unit to obtain I2C / I3C information, UART information, GPIO information, and SMBUS information. The second processing unit sends the I2C / I3C information, UART information, GPIO information, and SMBUS information to the I2C / I3C, UART, GPIO, and SMBUS information transmission channels in server node 2, respectively.

[0079] The I2C / I3C information transmission channel, also known as the I2C / I3C channel, is the I2C / I3C channel connecting the second processing unit and the CPU / southbridge of server node 2. The UART information transmission channel, also known as the URAT channel, is the URAT channel connecting the second processing unit and the CPLD of server node 2. The GPIO information transmission channel, also known as the GPIO channel, is the GPIO channel connecting the second processing unit and the CPLD of server node 2. The SMBUS information transmission channel, also known as the SMBUS channel, is the SMBUS channel connecting the second processing unit and the PSU of server node 2.

[0080] Example 2: The corresponding device in server node 2 transmits I2C / I3C information, UART information, GPIO information, and SMBUS information to the second processing unit via the I2C / I3C channel, UART channel, GPIO channel, and SMBUS channel, respectively. The second processing unit in server node 2 encapsulates the I2C / I3C information, UART information, GPIO information, and SMBUS information into second high-speed serial information {I2C / I3C information, UART information, GPIO information, SMBUS information} using a time-division multiplexing method. The second processing unit sends the second high-speed serial information via the second multiplexed high-speed interface in server node 2 to the first multiplexed high-speed interface of IO interface group 2, and then sends it via the first multiplexed high-speed interface to the first processing unit corresponding to IO interface group 2.

[0081] The first processing unit parses the second high-speed serial information {I2C / I3C information, UART information, GPIO information, SMBUS information} in the same multiplexing and demultiplexing manner as the second processing unit, obtaining the I2C / I3C information, UART information, GPIO information, and SMBUS information. The first processing unit sends the I2C / I3C information, UART information, GPIO information, and SMBUS information to the I2C / I3C controller, UART controller, GPIO controller, and SMBUS controller corresponding to I / O interface group 2.

[0082] Figure 3 also shows multiple non-multiplexed high-speed serial interfaces connected to multiple non-multiplexed high-speed serial interfaces of the server node. A non-multiplexed high-speed serial interface is a communication interface that does not multiplex other low-speed interfaces but has an information transmission speed greater than a preset transmission threshold, such as the PCIe interface, eSPI interface, and PECI.

[0083] It can be seen that compared with FIG2 , the number of BMC pins shown in FIG3 is reduced, that is, multiplexing multiple low-speed interfaces into one high-speed serial interface can reduce the number of pins provided by the BMC.

[0084] The embodiments of the present application do not specifically limit the form of the first processing unit. For example, the first processing unit may be a CPLD or an FPGA. The embodiments of the present application do not specifically limit the form of the second processing unit. For example, the second processing unit may be a CPLD or an FPGA.

[0085] The embodiments of the present application multiplex multiple low-speed interfaces through a single high-speed serial interface, reducing the number of pins required for the BMC connector, thereby helping to lower the cost of the BMC chip. They also help reduce the number of signals provided by the connectors of independent BMC plug-in cards or BMC daughter cards, thus reducing the difficulty of engineering implementation.

[0086] In addition, multiple IO interface groups in the BMC can share the first multiplexed high-speed interface and the first processing unit, and the multiple controllers corresponding to each of the IO interface groups are connected to the first processing unit, and the corresponding multiple server nodes share the second multiplexed high-speed interface and the second processing unit, and each server node is connected to the second processing unit, thereby further reducing the number of pins required by the BMC chip.

[0087] 4, which is a schematic diagram of the structure of another server provided by an embodiment of the present application, a BMC can only monitor one server node at a time.

[0088] In an embodiment of the present application, multiple IO interface groups in the BMC use the same first multiplexed high-speed interface. For example, IO interface group 1 and IO interface group 2 share the same first multiplexed high-speed interface. IO interface group 1 is connected to server node 1 through the first multiplexed high-speed interface, and IO interface group 2 is connected to server node 2 through the first multiplexed high-speed interface.

[0089] In an embodiment of the present application, the BMC includes a first processing unit for connecting to a first multiplexed high-speed interface. The first processing unit is connected to the low-speed interface controller corresponding to each IO interface group. For example, the I2C / I3C controller, UART controller, GPIO controller, and SMBUS controller corresponding to IO interface group 1 are connected to the first processing unit, and the I2C / I3C controller, UART controller, GPIO controller, and SMBUS controller corresponding to IO interface group 2 are connected to the first processing unit.

[0090] In one example, the first processing unit obtains high-speed serial reception information from the first multiplexed high-speed interface of the IO interface group, parses the high-speed serial reception information, obtains multiple low-speed information, and sends it to the processor through the low-speed interface controller.

[0091] In another example, the first processing unit obtains low-speed information from the low-speed interface controller corresponding to the IO interface group, encapsulates the low-speed information based on preset rules, obtains high-speed serial transmission information, and sends the high-speed serial transmission information through the first multiplexed high-speed interface.

[0092] For example, the first processing unit obtains I2C / I3C information, UART information, GPIO information, and SMBUS information from the I2C / I3C controller, UART controller, GPIO controller, and SMBUS controller corresponding to IO interface group 1. Based on preset rules, the first processing unit encapsulates the I2C / I3C information, UART information, GPIO information, and SMBUS information, obtains first high-speed serial information, and sends the first high-speed serial information through the first multiplexed high-speed interface.

[0093] In an embodiment of the present application, all server nodes connected to the BMC share a second processing unit and a second multiplexed high-speed interface. For example, server node 1 and server node 2 share a second processing unit and a second multiplexed high-speed interface. On the server node side, the second processing unit is connected to the second multiplexed high-speed interface. The second processing unit is configured to obtain first high-speed serial information from the second multiplexed high-speed interface, parse the first high-speed serial information based on preset rules, obtain multiple low-speed information, and send the multiple low-speed information to the server node.

[0094] The second multiplexed high-speed interface on the server node side is connected to the first high-speed serial interface on the IO interface group, so that one BMC can monitor the operation of multiple server nodes. For example, one BMC can monitor server node 1 and server node 2.

[0095] Because multiple I / O interface groups on the BMC side share a first multiplexed high-speed interface, and multiple server nodes on the server node side share a second multiplexed high-speed interface, when the first multiplexed high-speed interface on the BMC side communicates with the second multiplexed high-speed interface on the server node side, the BMC needs to know which I / O interface group the received information belongs to, and the server node needs to know which server node the received information belongs to.

[0096] In one example, the high-speed serial information exchanged between the BMC and the server node carries the identifier of the corresponding server node. The first processing unit or the second processing unit performs processing based on the carried server node identifier. In one example, the first processing unit is configured to encapsulate multiple low-speed messages and the identifier of the target server node to be sent to the target server node into high-speed information; the second processing unit parses the high-speed information to obtain multiple low-speed messages and the identifier of the target server node, and sends the multiple low-speed messages to the information channels corresponding to the target server node based on the identifier of the target server node.

[0097] For example, if the second processing unit obtains I2C / I3C information, UART information, GPIO information, and SMBUS information from the I2C / I3C, UART, GPIO, and SMBUS low-speed channels corresponding to server node 1, the I2C / I3C information, UART information, GPIO information, and SMBUS information may carry the identifier of server node 1, such as "Service1," indicating that the information originates from server node 1. Other identifiers representing server node 1 may also be used, and this is not specifically limited in this embodiment of the application.

[0098] The second processing unit encapsulates the low-speed information according to a preset rule to obtain a second high-speed serial information carrying the server node identifier. The second processing unit sends the second high-speed serial information to the first multiplexed high-speed interface on the BMC side through the second multiplexed high-speed interface, and then sends it to the first processing unit. The first processing unit parses the second high-speed serial information with the server node identifier to obtain the low-speed information carrying the server node identifier, and sends the low-speed information to the low-speed interface controller connected to the IO interface group corresponding to the server node. For example, if it carries the identifier of server node 1, the first processing unit sends the parsed low-speed information to the low-speed interface controller corresponding to IO interface group 1.

[0099] Exemplary description: If the first processing unit obtains multiple low-speed information from the low-speed interface controller corresponding to the IO interface group 1 in the BMC, for example, obtaining I2C / I3C information from the I2C / I3C controller and obtaining UART information from the UART controller. The low-speed information carries the identifier of the server node 1 corresponding to the IO interface group 1. The first processing unit encapsulates the information carrying the identifier of the server node 1 based on a preset rule to obtain the first high-speed serial information carrying the identifier of the server node 1, and sends the first high-speed serial information carrying the identifier of the server node 1 through the first multiplexed high-speed interface to the second multiplexed high-speed interface and the second processing unit of the server node test. The second processing unit sends the parsed low-speed information to the server node 1 according to the identifier of the server node 1.

[0100] In another example, the BMC can specify the active server node using a polling method or a designated method. In this case, the BMC needs to pre-store the correspondence between the server node and the IO interface group, and also needs to store the correspondence between the IO interface group and the low-speed interface controller. For example, if the designated server node is server node 1, server node 1 corresponds to IO interface group 1, and IO interface group 1 corresponds to a group of low-speed interface controllers. The first processing unit or the second processing unit parses the received information and sends it to the low-speed interface controller corresponding to the IO interface group corresponding to the designated server node, or sends it to the designated server node.

[0101] In summary, multiple IO interface groups share the same high-speed serial interface and processing unit, which helps to further reduce the pin count of the BMC connector.

[0102] The following description uses the preset rule of Time Division Multiplexing (TDM) as an example. TDM uses channel transmission time as the segmentation object and implements multiplexing by allocating non-overlapping time segments to multiple channels.

[0103] Refer to Figure 5, which is a schematic diagram of TDM multiplexing. Figure 5 uses information frames Frame T0 and Frame T-1 to represent information frames transmitted in adjacent time periods as an example. Among them, Frame T0 is the high-speed serial information of the T0 period, and Frame T-1 is the T -1 High-speed serial information in the time period. -1 , T0 are adjacent time periods, and multiple low-speed information is transmitted to the first processing unit or to the second processing unit once in each time period.

[0104] First, the implementation method of transmitting information from BMC to server nodes is introduced.

[0105] The BMC sends M channels of low-speed information to the first processing unit via the corresponding low-speed interface controller. The first processing unit converts the M channels of low-speed information into first high-speed serial information and sends the first high-speed serial information to the second processing unit via the high-speed serial bus. The second processing unit parses the first high-speed serial information to obtain M channels of low-speed information and sends the M channels of low-speed information to the corresponding low-speed interface channel. Low-speed interface channels are used to transmit low-speed information, and examples include GPIO channels, I2C / I3C channels, UART channels, and SMBUS channels.

[0106] Figure 5 shows that Frame T0 and Frame T-1 are first high-speed serial information {GPIO information, I2C / I3C information, UART information, SMBUS information}. That is, the BMC sends the GPIO information, I2C / I3C information, UART information, and SMBUS information to the first processing unit via the GPIO channel controlled by the GPIO controller, the I2C / I3C channel controlled by the I2C / I3C controller, the UART channel controlled by the UART controller, and the SMBUS channel controlled by the SMBUS controller, respectively. The first processing unit encapsulates the GPIO information, I2C / I3C information, UART information, and SMBUS information into high-speed serial transmission information {GPIO information, I2C / I3C information, UART information, SMBUS information}. The first processing unit communicates the high-speed serial transmission information {GPIO information, I2C / I3C information, UART information, SMBUS information} with the first multiplexed high-speed interface of the server node via the first multiplexed high-speed interface.

[0107] The second processing unit of the server node receives high-speed serial transmission information {GPIO information, I2C / I3C information, UART information, SMBUS information} through the second multiplexed high-speed interface of the server node, parses it based on preset rules, obtains low-speed information GPIO information, I2C / I3C information, UART information and SMBUS information, and sends the GPIO information, I2C / I3C information, UART information and SMBUS information to the GPIO channel, I2C / I3C channel, UART channel and SMBUS channel respectively.

[0108] FIG5 also shows that Frame T-1 is first sent to the server node, and then Frame T0 is sent to the server node.

[0109] (See the upper half of Figure 5).

[0110] The following describes how to transmit information from the server node to the BMC.

[0111] The server node sends the M-channel low-speed information to the second processing unit via the corresponding communication interface channel. The second processing unit encapsulates the M-channel low-speed information into second high-speed serial information based on preset rules and sends the high-speed serial received information to the first processing unit of the BMC via the high-speed serial bus. The first processing unit of the BMC parses the high-speed serial information based on preset rules to obtain the M-channel low-speed information and transmits the M-channel low-speed information via the corresponding communication interface channel.

[0112] Figure 5 shows that Frame T0 and Frame T-1 are second high-speed serial information {GPIO information, I2C / I3C information, UART information, SMBUS information}. That is, the server node sends the GPIO information, I2C / I3C information, UART information, and SMBUS information to the second processing unit via the GPIO channel, I2C / I3C channel, UART channel, and SMBUS channel, respectively. The second processing unit encapsulates the GPIO information, I2C / I3C information, UART information, and SMBUS information into the second high-speed serial information {GPIO information, I2C / I3C information, UART information, SMBUS information}. The second processing unit communicates the second high-speed serial information {GPIO information, I2C / I3C information, UART information, SMBUS information} with the first multiplexed high-speed interface of the IO interface group via the second multiplexed high-speed interface.

[0113] The first processing unit corresponding to the IO interface group receives the second high-speed serial information {GPIO information, I2C / I3C information, UART information, SMBUS information}, and parses it based on preset rules to obtain low-speed information GPIO information, I2C / I3C information, UART information and SMBUS information, and sends the GPIO information, I2C / I3C information, UART information and SMBUS information to the GPIO channel controlled by the GPIO controller, the I2C / I3C channel controlled by the I2C / I3C controller, the UART channel controlled by the UART controller and the SMBUS channel controlled by the SMBUS controller respectively.

[0114] FIG5 also shows that Frame T-1 is first sent to the IO interface group, and then Frame T-1 is sent to T0 to the IO interface group (see the lower half of FIG5).

[0115] The following uses image display as an example to describe in detail how one BMC monitors multiple server nodes.

[0116] See FIG6 , which is a schematic diagram of a method for managing multiple server nodes by a BMC according to an embodiment of the present application.

[0117] In the BMC, I / O interface group 1, I / O interface group 2, ..., and I / O interface group N are connected to a single GPU. Specifically, the PCIe interface of I / O interface group 1 is connected to the GPU via a PCIe controller, the PCIe interface of I / O interface group 2 is connected to the GPU via a PCIe controller, ..., and the PCIe interface of I / O interface group N is connected to the GPU via a PCIe controller. Furthermore, the PCIe interfaces of these I / O interface groups are also connected to the processor via a PCIe controller. N is an integer greater than or equal to 2.

[0118] The CPU on the server node sends configuration information to the CPU through the PCIe interface of the I / O interface group. The CPU then sends the configuration information to the GPU, which then configures itself based on the configuration information. GPU configuration includes loading kernel-mode drivers and initializing the GPU to ensure proper operation.

[0119] After the GPU configuration is completed, the CPU on the server node side first sends the image display information to the GPU. After obtaining the image display information, the GPU processes the image information. After the processing is completed, the obtained display data is sent to the local display through the display interface for local display, or the GPU completes the preprocessing and encoding process of the video encoding process through the video coding engine (VCE), and sends the encoded data to the remote display through the Ethernet interface for remote display.

[0120] In the embodiment of the present application, the VCE can be a chip responsible for encoding operations, or a dedicated hardware circuit integrated into the BMC. Compared with software encoding or GPU encoding, the VCE can increase processing speed and significantly reduce the power consumption caused by the GPU processing process.

[0121] It should be understood that the GPU configuration process takes a certain amount of time. If the GPU configuration time exceeds the time required to switch server nodes and send image display information to the GPU, the GPU configuration may not yet be complete, but image information sent by other server nodes may be received. For example, after server node 1 switches to server node 2, server node 2 sends image display information 2 to the GPU, but the GPU configuration is not yet complete. Using the parameters of the unconfigured GPU to process image display information 2 may result in processing errors or display data loss.

[0122] In view of the above problems, the embodiments of the present application provide two processing methods to avoid data loss caused by one GPU managing graphics information sent by multiple servers.

[0123] Refer to FIG7 , which is a schematic diagram of a structure in which a GPU includes multiple GPU virtual modules.

[0124] A GPU includes multiple GPU virtual modules, each corresponding to a PCIe interface in an I / O interface group. That is, GPU virtual module 1 connects to the PCIe interface in I / O interface group 1, GPU virtual module 2 connects to the PCIe interface in I / O interface group 2, and so on. GPU virtual module N connects to the PCIe interface in I / O interface group N.

[0125] The CPU of server node 1 can configure GPU virtual module 1 through IO interface group 1. GPU virtual module 1 obtains image display information from the CPU in server node 1 through the PCIe interface in IO interface group 1 for processing, and sends the obtained display data to the local display for local display, or sends it to the remote display for remote display through the video coding engine (VCE) and Ethernet interface.

[0126] The CPU of server node 2 can configure GPU virtual module 2 through IO interface group 2. GPU virtual module 2 obtains image display information from the CPU in server node 2 through the PCIe interface in IO interface group 2 for processing, and sends the obtained display data to the local display for local display, or sends it to the remote display for remote display through the video coding engine (VCE) and Ethernet interface.

[0127] By analogy, one BMC can manage N server nodes.

[0128] In the embodiment of the present application, multiple GPU virtual modules can be virtualized on the GPU, and each GPU virtual module controls a server node, thereby avoiding problems such as data loss.

[0129] See Figure 8, which is a schematic diagram of the structure of a BMC integrating multiple GPUs.

[0130] When there are N server nodes, the BMC includes N GPUs. Specifically, GPU1 connects to server node 1 via the PCIe interface of I / O interface group 1, GPU2 connects to server node 2 via the PCIe interface of I / O interface group 2, and so on. GPUN connects to server node N via the PCIe interface of I / O interface group N. Each VCE connects to each of the N GPUs.

[0131] The CPU of server node 1 can configure GPU 1 through IO interface group 1. GPU 1 obtains image display information from the CPU in server node 1 through the PCIe interface in IO interface group 1 for processing, and sends the obtained display data to the local display for local display, or sends it to the remote display for remote display through the video coding engine (VCE) and Ethernet interface.

[0132] The CPU of server node 2 can configure GPU2 through IO interface group 2. GPU2 can obtain image display information from the CPU in server node 2 through the PCIe interface in IO interface group 2 for processing, and send the obtained display data to the local display for local display, or send it to the remote display for remote display through the video coding engine (VCE) and Ethernet interface.

[0133] By analogy, one BMC can manage N server nodes.

[0134] Furthermore, considering the following issues with managing multiple server nodes with a single BMC: VCE and other components are complex to implement, and simultaneously supporting graphics processing for multiple GPUs would require significant space. Furthermore, BMC plug-in cards or daughter cards currently only support a single channel. In this embodiment, a switching circuit is added between multiple GPUs and the VCE or display interface module. This switching circuit ensures that only the CPU corresponding to a server node can interact with the BMC's VCE at any given time.

[0135] See FIG9 , which is a schematic diagram of FIG8 with a switch switching circuit added.

[0136] The first end of the switch switching circuit is connected to VCE, the third end is connected to N GPUs, and the second end is connected to the display interface.

[0137] The switch switching circuit realizes the connection between two ends. For example, it realizes the connection between GPUi and VCE, or realizes the connection between GPUi and the display interface. Here, 1 < i < N, and i is an integer.

[0138] In one example, the third end of the switch switching circuit is connected to GPU1, GPU2,..., GPUN, GPU1,... in turn based on the polling method. In this way, at a certain moment, only one GPU is connected to VCE. In this way, it is realized that at a certain moment, only the CPU corresponding to one server node interacts with the VCE of BMC.

[0139] In another example: the switch switching circuit always maintains a connection with a certain fixed GPU.

[0140] The embodiments of the present application do not specifically limit the switching method of the third end of the switch switching circuit. For example, through the preset polling method, the switch switching circuit can switch the connected server nodes in turn. It is also possible to switch the switch switching circuit to the specified server node and then not switch anymore by specifying the server. In addition, a switching interface can be designed on the BMC Web interface, a switching button can be designed on the BMC plug-in card / clip card, etc., for switching the server node that interacts with BMC.

[0141] The above are only the preferred embodiments of the present application, and do not impose any form of limitation on the present application. Although the present application has been disclosed above with preferred embodiments, it is not intended to limit the present application. Any person skilled in the art can make many possible changes and modifications to the technical solution of the present application, or modify it into an equivalent embodiment with equivalent changes, without departing from the scope of the technical solution of the present application. Therefore, any simple modification, equivalent change and modification made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application still fall within the scope of protection of the technical solution of the present application.

Claims

1. A server, characterized in that: It includes a baseboard management controller and multiple server nodes, the baseboard management controller includes multiple input and output IO interface groups, each of the IO interface groups includes multiple communication interfaces, the server nodes are connected to the communication interfaces of the corresponding IO interface groups, and the baseboard management controller is used to monitor the server nodes connected to the IO interface groups.

2. The server according to claim 1, characterized in that: The multiple communication interfaces include a first multiplexed high-speed interface, the baseboard management controller also includes a first processing unit and multiple controllers, the first processing unit is connected between the first multiplexed high-speed interface and the multiple controllers, the server node includes a second multiplexed high-speed interface and a second processing unit, the second multiplexed high-speed interface is connected to both the first multiplexed high-speed interface and the second processing unit; The first processing unit is used to encapsulate the low-speed information from the multiple controllers into high-speed information and send it to the second processing unit through the first multiplexed high-speed interface and the second multiplexed high-speed interface. The second processing unit is used to parse the high-speed information into multiple low-speed information, and the transmission speed of the low-speed information is lower than the transmission speed of the high-speed information.

3. The server according to claim 2, characterized in that: The multiple IO interface groups share the first multiplexed high-speed interface and the first processing unit, and the multiple controllers corresponding to each of the IO interface groups are connected to the first processing unit. The multiple server nodes share the second multiplexed high-speed interface and the second processing unit, and each server node is connected to the second processing unit.

4. The server according to claim 3, characterized in that: The first processing unit is used to encapsulate multiple low-speed information and the identifier of the target server node sent to the target server node into high-speed information; the second processing unit parses the high-speed information to obtain multiple low-speed information and the identifier of the target server node, and sends the multiple low-speed information to the information channel corresponding to the target server node according to the identifier of the target server node.

5. A baseboard management controller, characterized in that: It comprises a plurality of input and output IO interface groups, each of which comprises a plurality of communication interfaces, the server node is connected to the communication interface of the corresponding IO interface group, and the management controller is used to monitor the server node connected to the IO interface group.

6. The baseboard management controller according to claim 5, characterized in that: The multiple communication interfaces include a first multiplexed high-speed interface for connecting to corresponding server nodes. The management controller also includes a first processing unit and multiple controllers. The first processing unit is connected between the first multiplexed high-speed interface and the multiple controllers. The first processing unit is used to encapsulate low-speed information from the multiple controllers into high-speed information and send it to the server node via the first multiplexed high-speed interface. The transmission speed of the low-speed information is lower than the transmission speed of the high-speed information.

7. The baseboard management controller according to claim 5, characterized in that: The baseboard management controller also includes multiple image processors GPUs, each IO interface group includes a PCIe interface, the PCIe interface of each IO interface group is connected to the corresponding GPU, each GPU is used to obtain image information from the server node connected to the corresponding IO interface group, or each GPU is used to send image information to the connected server node through the corresponding IO interface group.

8. The baseboard management controller according to claim 7, characterized in that: The baseboard management controller also includes a video graphics compression module, an Ethernet interface, a display interface and a switch switching circuit; One end of the video graphics compression module is connected to the first end of the switch switching circuit, and the other end of the video graphics compression module is connected to the remote display through the Ethernet interface; the second end of the switch switching circuit is connected to the local display through the display interface; the third end of the switch switching circuit is connected to the N GPUs; The switch switching circuit is used to: obtain processed image information from one of the N GPUs; and send the obtained image information to the video graphics compression module to display it on the remote display through the Ethernet interface, or send the obtained image information to the local display through the display interface for display.

9. The baseboard management controller according to any one of claims 5 to 8, characterized in that: The multiple communication interfaces include: a high-speed serial computer expansion bus standard PCIe interface, an enhanced peripheral management interface eSPI, a low frame rate LPC interface, an integrated circuit bus I2C, an enhanced two-wire serial bus I3C interface, a serial peripheral interface SPI, a universal asynchronous receiver and transmitter UART interface general purpose IO GPIO interface and a platform environment control interface PECI.

10. A server management method, characterized in that: Applied to a baseboard management controller, the baseboard management controller includes a plurality of input and output IO interface groups, each IO interface group is used to connect to a corresponding server node, and each IO interface group includes a plurality of communication interfaces connected to the corresponding server node; The method comprises: The target server node is managed through the target IO interface group, wherein the target IO interface group is any IO interface group among multiple IO interface groups, and the target server node is the target server node connected to the target IO interface.

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