Display device

Abstract

A display device according to one embodiment of the present invention comprises: a display panel including a display area, which includes a transmission region and a plurality of pixel regions adjacent to the transmission region, and a non-display area adjacent to the display area; and an input sensor, which is arranged on the display panel and includes a plurality of conductive patterns. The plurality of conductive patterns include a plurality of sensing patterns provided in each of a first direction and a second direction that crosses the first direction. The sensing patterns include a plurality of mesh lines, and a transmission opening overlapping the transmission region and a pixel opening overlapping each of the plurality of pixel regions are defined in the plurality of mesh lines. In the display area, the ratio of the transmission region to the entire area of the transmission region and the plurality of pixel regions is 60% or more.

Description

display device

[0001] The present invention relates to a display device, and more particularly, to a display device having improved transmittance and improved sensing sensitivity of external input.

[0002] Multimedia devices such as televisions, mobile phones, tablets, navigation systems, and game consoles include display devices that display images to a user via a display screen. The display device may include a display panel that generates images and an input sensor that detects a user's touch.

[0003] Recent technological advancements have led to the development of transparent display devices with transparent areas within the display area. Meanwhile, input sensors may include conductors that detect external input, and the conductors of the input sensors positioned on the display panel may affect the display device's luminous efficiency or transmittance.

[0004] The present invention aims to provide a display device in which the transmittance of the display area is improved while the external input sensing sensitivity of the input sensor is improved.

[0005] According to one embodiment of the present invention, a display device includes a display panel including a display area including a transparent area and a non-display area adjacent to the display area, and an input sensor disposed on the display panel and including a plurality of conductive patterns. The plurality of conductive patterns include a first sensing electrode including a plurality of first sensing patterns provided along a first direction, and a plurality of bridge patterns connecting two adjacent ones of the plurality of first sensing patterns, a second sensing electrode including a plurality of second sensing patterns provided along a second direction intersecting the first direction and spaced apart from the first sensing electrode, and a transparent electrode electrically connected to at least a portion of the first sensing electrode and the second sensing electrode. Each of the plurality of first sensing patterns and the plurality of second sensing patterns includes a plurality of mesh lines defining a transmitting opening overlapping at least the transparent area. The transparent electrode overlaps at least a portion of the transparent area.

[0006] The display area may further include a plurality of pixel areas adjacent to the transmission area and emitting light.

[0007] In the above display area, the ratio of the transparent area to the total area of ​​the transparent area and the plurality of pixel areas may be 60% or more.

[0008] The input sensor may further include a cover insulating layer disposed between the first sensing electrode, the second sensing electrode, and the transparent electrode. The transparent electrode may be electrically connected to at least a portion of the first sensing electrode and the second sensing electrode through an upper contact hole penetrating the cover insulating layer.

[0009] The above transparent electrode can overlap at least a portion of each of the above transparent region and the plurality of pixel regions.

[0010] The above plurality of conductive patterns may be arranged on the same layer as the transparent electrode and may further include a dummy pattern insulated from the first sensing electrode and the second sensing electrode.

[0011] The plurality of pixel areas may include a first pixel area, a second pixel area, and a third pixel area arranged along the first direction. The transparent area may be adjacent to each of the first pixel area, the second pixel area, and the third pixel area along the second direction.

[0012] The above transparent electrode may include a transparent conductive oxide (TCO).

[0013] The display panel may include a light-emitting element that outputs source light and overlaps at least each of the plurality of pixel areas. The light-emitting element may include a first electrode, a first light-emitting stack disposed on the first electrode, a second light-emitting stack disposed on the first light-emitting stack, a third light-emitting stack disposed on the second light-emitting stack, a fourth light-emitting stack disposed on the third light-emitting stack, a second electrode disposed on the fourth light-emitting stack, and a charge generation layer disposed between each of the first light-emitting stack to the fourth light-emitting stack. Each of the first light-emitting stack to the fourth light-emitting stack may include at least one light-emitting layer.

[0014] A display device according to one embodiment of the present invention may further include a light control layer disposed on the light emitting element and transmitting the source light or converting the source light into light of a different wavelength.

[0015] The above optical control layer may include a bank including a plurality of bank openings, and a plurality of optical control patterns arranged inside each of the plurality of bank openings. The plurality of optical control patterns may not overlap the transmission area.

[0016] The at least one light-emitting layer included in each of the first to fourth light-emitting stacks may not overlap the transmission area.

[0017] The second sensing electrode may further include a connecting pattern disposed between two adjacent second sensing patterns among the plurality of second sensing patterns and having an integral shape with the plurality of second sensing patterns.

[0018] The input sensor may further include a sensing insulating layer disposed between the plurality of bridge patterns and the plurality of first sensing patterns. Each of the plurality of bridge patterns may be electrically connected to each of the plurality of first sensing patterns through a lower contact hole defined in the sensing insulating layer.

[0019] The above-mentioned transparent region may include a first transparent region that overlaps the transparent electrode on a plane, and a second transparent region that does not overlap the transparent electrode on a plane.

[0020] According to one embodiment of the present invention, a display device includes a display panel including a display area including a transparent area and a non-display area adjacent to the display area, and an input sensor disposed on the display panel and including a plurality of conductive patterns. The plurality of conductive patterns are provided along a first direction and a second direction intersecting the first direction, and each includes a plurality of unit sensing patterns insulated from each other, and a plurality of unit signal lines connected to at least some of the plurality of unit sensing patterns. Each of the plurality of unit sensing patterns includes a plurality of mesh lines defining a transparent opening overlapping at least the transparent area. Each of the plurality of unit signal lines is connected to a corresponding one of the plurality of unit sensing patterns, and each includes a plurality of sub-signal lines extending along the first direction.

[0021] The plurality of sub-signal lines may include a first sub-signal line connected to a first unit detection pattern, which is one of the unit detection patterns, and extending along the first direction, a second sub-signal line connected to the first unit detection pattern, extending along the first direction, and spaced apart from the first sub-signal line along the second direction, and a third sub-signal line connected to the first unit detection pattern, extending along the first direction, and spaced apart from each of the first sub-signal line and the second sub-signal line along the second direction.

[0022] The width of each of the plurality of sub-signal lines may be 1 micrometer or more and 5 micrometers or less. The spacing between each of the plurality of sub-signal lines may be 3 micrometers or more and 7 micrometers or less.

[0023] The plurality of conductive patterns may have an integral shape with some of the plurality of unit detection patterns, be electrically connected to some of the plurality of unit detection patterns, and further include an additional signal line overlapping the non-display area.

[0024] The input sensor may further include a sensing insulating layer disposed between the plurality of unit sensing patterns and the plurality of unit signal lines. Each of the plurality of unit signal lines may be electrically connected to each of the plurality of unit sensing patterns through a unit contact hole penetrating the sensing insulating layer.

[0025] The display area may further include a plurality of pixel areas adjacent to the transmission area and emitting light.

[0026] In the above display area, the ratio of the transparent area to the total area of ​​the transparent area and the plurality of pixel areas may be 60% or more.

[0027] The plurality of pixel areas may include a first pixel area, a second pixel area, and a third pixel area arranged along the first direction. The transparent area may be adjacent to each of the first pixel area, the second pixel area, and the third pixel area along the second direction.

[0028] The display panel may include a light-emitting element that outputs source light and overlaps at least each of the plurality of pixel areas. The light-emitting element may include a first electrode, a first light-emitting stack disposed on the first electrode, a second light-emitting stack disposed on the first light-emitting stack, a third light-emitting stack disposed on the second light-emitting stack, a fourth light-emitting stack disposed on the third light-emitting stack, a second electrode disposed on the fourth light-emitting stack, and a charge generation layer disposed between each of the first light-emitting stack to the fourth light-emitting stack. Each of the first light-emitting stack to the fourth light-emitting stack may include at least one light-emitting layer.

[0029] A display device according to one embodiment of the present invention may further include a light control layer disposed on the light emitting element and transmitting the source light or converting the source light into light of a different wavelength.

[0030] The above optical control layer may include a bank including a plurality of bank openings, and a plurality of optical control patterns arranged inside each of the plurality of bank openings. The plurality of optical control patterns may not overlap the transmission area.

[0031] The at least one light-emitting layer included in each of the first to fourth light-emitting stacks may not overlap the transmission area.

[0032] According to one embodiment of the present invention, a display device includes a display area including a transparent area and a plurality of pixel areas adjacent to the transparent area, and a display panel including a non-display area adjacent to the display area, and an input sensor disposed on the display panel and including a plurality of conductive patterns. The plurality of conductive patterns include a plurality of sensing patterns provided along a first direction and a second direction intersecting the first direction, respectively. The sensing patterns include a plurality of mesh lines, and a transmitting opening overlapping the transparent area and a pixel opening overlapping each of the plurality of pixel areas are defined in the plurality of mesh lines. In the display area, a ratio of the transparent area to a total area of ​​the transparent area and the plurality of pixel areas is 60% or more.

[0033] According to one embodiment of the present invention, the ratio of the transparent area in the display area increases, thereby improving the transmittance of the display device, and at the same time, the range of change in the electrostatic capacity of the input sensor can be secured to a large extent, thereby improving the sensing performance of the input sensor and the display device including the same.

[0034] FIG. 1A is a perspective view of an electronic device according to one embodiment of the present invention.

[0035] FIG. 1b is a perspective view of a curved electronic device according to one embodiment of the present invention.

[0036] Figure 2 is a cross-sectional view of a display device according to one embodiment of the present invention.

[0037] Figure 3a is a plan view of a display device according to one embodiment of the present invention.

[0038] FIG. 3b is an enlarged plan view of a portion of a display area of ​​a display device according to one embodiment of the present invention.

[0039] Figure 4 is an equivalent circuit diagram of a pixel according to one embodiment of the present invention.

[0040] FIGS. 5 and 6 are each cross-sectional views of a display device according to one embodiment of the present invention.

[0041] Figure 7 is a cross-sectional view of a light-emitting device according to one embodiment of the present invention.

[0042] Figure 8 is a plan view of an input sensor according to one embodiment of the present invention.

[0043] FIGS. 9A and 9B are each enlarged plan views of a portion of an input sensor according to one embodiment of the present invention.

[0044] FIG. 9c and FIG. 9c are each enlarged cross-sectional views of a portion of an input sensor according to one embodiment of the present invention.

[0045] FIGS. 10A to 10C are enlarged plan views of a portion of a display area of ​​a display device according to one embodiment of the present invention.

[0046] Fig. 11 is a plan view of an input sensor according to one embodiment of the present invention.

[0047] FIG. 12a is an enlarged plan view of a portion of an input sensor according to one embodiment of the present invention.

[0048] Figure 12b is an enlarged plan view of a portion of an input sensor according to one embodiment of the present invention.

[0049] FIG. 12c is an enlarged cross-sectional view of a portion of an input sensor according to one embodiment of the present invention.

[0050] Figure 13 is a plan view of an input sensor according to one embodiment of the present invention.

[0051] Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[0052] In this specification, when it is said that a component (or region, layer, portion, etc.) is “on,” “connected to,” or “coupled to” another component, it means that it can be directly connected / coupled to the other component, or a third component may be disposed between them.

[0053] Identical drawing numbers indicate identical components. Furthermore, in the drawings, the thicknesses, proportions, and dimensions of components are exaggerated for the purpose of effectively illustrating the technical content. "And / or" encompasses any combination of one or more of the associated components.

[0054] While terms such as "first" and "second" may be used to describe various components, these components should not be limited by these terms. These terms are used solely to distinguish one component from another. For example, without departing from the scope of the present invention, a first component may be referred to as a "second component," and similarly, a second component may also be referred to as a "first component." Singular expressions include plural expressions unless the context clearly indicates otherwise.

[0055] Additionally, terms such as "below," "lower," "above," and "upper" are used to describe the relationships between components depicted in the drawings. These terms are relative concepts and are described based on the directions indicated in the drawings.

[0056] Terms such as "include" or "have" should be understood to specify the presence of a feature, number, step, operation, component, part, or combination thereof described in the specification, but not to exclude in advance the possibility of the presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

[0057] In this specification, "directly disposed" may mean that there are no additional layers, films, regions, plates, etc., between a portion of a layer, film, region, plate, etc. and another portion. For example, "directly disposed" may mean disposed between two layers or two members without using an additional member, such as an adhesive member.

[0058] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which this invention pertains. Furthermore, terms defined in commonly used dictionaries should be interpreted to have a meaning consistent with their meaning in the relevant technical context, and should not be interpreted in an overly idealistic or overly formal sense unless explicitly defined herein.

[0059] Hereinafter, a display device according to one embodiment of the present invention will be described with reference to the drawings.

[0060] FIG. 1A is a perspective view of an electronic device according to an embodiment of the present invention. FIG. 1B is a perspective view of a curved electronic device according to an embodiment of the present invention. FIG. 2 is a cross-sectional view of a display device according to an embodiment of the present invention.

[0061] The electronic device (ED, ED-1) illustrated in FIGS. 1A and 1B may include a display device (DD) and a housing (HU) that accommodates at least a portion of the display device (DD). For example, a portion of the lower portion of the display device (DD) may be accommodated in the housing (HU).

[0062] Referring to FIG. 1A, the display device (DD) can display an image through the front surface (DU). The upper surface of a member positioned at the uppermost side of the display device (DD) can be defined as the front surface (DU) of the display device (DD). According to the present invention, the upper surface of the window (WD) illustrated in FIG. 2 can be defined as the front surface (DU) of the display device (DD).

[0063] In this embodiment, the front surface (DU) is parallel to the plane defined by the first direction (DR1) and the second direction (DR2). The normal direction of the front surface (DU), i.e., the thickness direction of the display device (DD), is indicated by the third direction (DR3). The front surface (or upper surface) and the back surface (or lower surface) of each layer or unit described below are distinguished by the third direction (DR3).

[0064] The display device (DD) according to the present invention may be a transparent display device (DD). The transparent display device (DD) can display information in a state where an object (PD) placed on the back surface (DB) of the display device (DD) is transparently reflected on the front surface (DU) of the display device (DD). Accordingly, a user can recognize an object placed on the back surface (DB) of the display device (DD) from the front surface (DU) of the display device (DD). The information is not limited to any one, such as an image, content, a playback screen, an application execution screen, a web browser screen, or various graphic objects. Although a vase is illustrated as an example of the object (PD) in Fig. 1b, it is not limited thereto, and the object (PD) has a specific shape and is not limited to any one thing.

[0065] The housing (HU) can protect the display device (DD) from external impact or the intrusion of foreign substances. The housing (HU) can be composed of a material such as plastic or metal. However, this is merely exemplary, and the housing is not limited thereto as long as it can protect the display device (DD) from external impact or the intrusion of foreign substances. In an electronic device (ED) according to one embodiment, the housing (HU) is omitted, but the display device (DD) can be rolled and placed inside the housing (HU) through a separate hinge member, and is not limited to any one embodiment.

[0066] Referring to FIG. 1B, an electronic device (ED-1) according to one embodiment may be curved along a second direction (DR2) based on an imaginary axis (AX) extending in a first direction (DR1). Accordingly, the display device (DD) may be curved with a predetermined curvature, and the housing (HU) may have a corresponding curvature. However, the present invention is not limited thereto, and the axis may extend in the second direction (DR2), or may be curved based on a plurality of axes extending in different directions.

[0067] Additionally, the display device (DD) may be a rollable display panel, a foldable display panel, or a slider display panel, and the entire display device (DD) may be disposed within the housing (HU) in an operational state. Accordingly, the display device (DD) may include a curved display surface or a three-dimensional display surface. The three-dimensional display surface may include a plurality of display areas pointing in different directions.

[0068] Referring to FIG. 2, a display device (DD) according to the present invention may include a display panel (DP), an input sensor (IS), an optical layer (OSL), and a window (WD). The display panel (DP) may include a base substrate (BS), a circuit element layer (DP-CL) disposed on the base substrate (BS), a display element layer (DP-OLED), and an encapsulation layer (TFE). The display device (DD) may further include functional layers such as an antireflection layer or a refractive index control layer.

[0069] The display panel (DP) is a light-emitting display panel, and may be any one of a liquid crystal display panel, an electrophoretic display panel, a microelectromechanical system display panel, an electrowetting display panel, an organic light-emitting display panel, an inorganic light-emitting display panel, and a quantum-dot display panel, without particular limitation.

[0070] The base substrate (BS) may include a synthetic resin film. The synthetic resin layer may include a thermosetting resin. In particular, the synthetic resin layer may be a polyimide-based resin layer, and the material thereof is not particularly limited. The synthetic resin layer may include at least one of an acrylic resin, a methacrylic resin, a polyisoprene, a vinyl resin, an epoxy resin, a urethane resin, a cellulose resin, a siloxane resin, a polyamide resin, and a perylene resin. In addition, the base layer may include a glass substrate, a metal substrate, or an organic / inorganic composite material substrate.

[0071] A circuit element layer (DP-CL) includes at least a plurality of insulating layers and circuit elements. The insulating layers described below may include organic layers and / or inorganic layers. The circuit element layer (DP-CL) forms an insulating layer, a semiconductor layer, and a conductive layer through processes such as coating and deposition. Thereafter, the insulating layer, the semiconductor layer, and the conductive layer can be selectively patterned through photolithography and etching processes. Through these processes, a semiconductor pattern, a conductive pattern, a signal line, etc. are formed. Patterns arranged on the same layer are formed through the same process.

[0072] The circuit element layer (DP-CL) includes driving circuits or signal lines that drive the pixels (PX). The display element layer (DP-OLED) may include a light-emitting element (OLED, see FIG. 5) and a pixel definition layer (PDL, see FIG. 5) included in the pixels (PX).

[0073] The encapsulation layer (TFE) can be disposed on the display element layer (DP-OLED) to protect the light-emitting element (OLED). The encapsulation layer (TFE) can include inorganic layers and an organic layer disposed between the inorganic layers. The inorganic layers can protect the light-emitting element (OLED) from moisture and oxygen, and the organic layer can protect the light-emitting element (OLED) from foreign substances such as dust particles.

[0074] The input sensor (IS) may be directly disposed on the display panel (DP). The input sensor (IS) may detect a user's input, for example, by electromagnetic induction and / or capacitive means. The display panel (DP) and the input sensor (IS) may be formed through a continuous process. Here, "directly disposed" may mean that no third component is disposed between the input sensor (IS) and the display panel (DP). For example, a separate adhesive layer may not be disposed between the input sensor (IS) and the display panel (DP).

[0075] The optical layer (OSL) may include light control patterns capable of changing the optical properties of source light generated from the light emitting device (OLED). In addition, the optical layer (OSL) may reduce the reflectivity of external light incident from the upper side of the window (WD). The light control patterns may include quantum dots, and the optical layer (OSL) may include color filters that selectively transmit light passing through the light control patterns. In one embodiment, the optical layer (OSL) may be omitted.

[0076] A window (WD) is positioned on top of a display panel (DP) and can transmit images provided from the display panel (DP) to the outside. The window (WD) may include a base layer and functional layers positioned on the base layer. The functional layers may include a protective layer, an anti-fingerprint layer, etc. The base layer of the window (WD) may be composed of glass, sapphire, plastic, etc.

[0077] Fig. 3a is a plan view of a display device according to one embodiment of the present invention. Fig. 3b is an enlarged plan view of a portion of a display area of ​​a display device according to one embodiment of the present invention.

[0078] Referring to FIGS. 3A and 3B, a display device (DD) according to one embodiment may include pixels arranged in a unit area (PU), a gate driving circuit (GDC) connected to the pixels, and signal lines.

[0079] A display device (DD) may include a display area (DA) and a non-display area (NDA). In the display area (DA), an emission layer (EML, see FIG. 5) of a pixel disposed in the unit area (PU) is disposed, and in the non-display area (NDA), the emission layer (EML) is not disposed. The non-display area (NDA) may surround the display area (DA). In one embodiment of the present invention, the non-display area (NDA) may be omitted or disposed only on one side of the display area (DA). Meanwhile, in FIG. 3A, the shapes of the display area (DA) and the non-display area (NDA) defined in the display device (DD) are exemplarily illustrated, and the display area (DA) and the non-display area (NDA) may be defined corresponding to a display panel (DP) included in the display device (DD).

[0080] A plurality of unit areas (PU) may be provided within the display area (DA). The unit areas (PU) may be arranged along a first direction (DR1) and a second direction (DR2). The unit areas (PU) may include light-emitting areas for the display panel (DP) to provide information to a user, a transparent area for increasing the transparency of the display panel (DP) so that an object (PD) arranged on the back surface (DB) of the display panel (DP) may be transparent to the user, and a wiring area in which signal lines connected to pixels are arranged.

[0081] FIG. 3b illustrates two first unit areas (PU1) and a second unit area (PU2) arranged along the second direction (DR2) among the unit areas (PU) of FIG. 3a.

[0082] The first unit area (PU1) may include pixel areas (PXA1-1, PXA2-1, PXA3-1) spaced apart along the first direction (DR1), and a transmission area (TA1) spaced apart from the pixel areas (PXA1-1, PXA2-1, PXA3-1) along the second direction (DR2).

[0083] The second unit area (PU2) may include pixel areas (PXA1-2, PXA2-2, PXA3-3) spaced apart along the first direction (DR1), and a transmission area (TA2) spaced apart from the pixel areas (PXA1-2, PXA2-2, PXA3-3) along the second direction (DR2).

[0084] Meanwhile, the non-pixel area (NPXA) may surround each of the pixel areas (PXA) and the transparent area (TA) adjacent to the pixel areas (PXA). Although not shown, the display area (DA) may further include a wiring area adjacent to the pixel areas (PXA) and the transparent area (TA). Wires such as sensing lines, power lines, and scan lines may be arranged in the wiring areas.

[0085] According to the present invention, the wavelengths of the source light provided in the pixel areas (PXAs) may be different from each other. Each of the pixel areas (PXAs) is defined by a light-emitting aperture (PDL-OP) included in a pixel defining layer (PDL, see FIG. 5), and the transmission areas (TA) may be defined by at least a transmission aperture (T-OP) formed in the pixel defining layer (PDL, see FIG. 5). This will be described later.

[0086] In a display area (DA) of a display device of one embodiment, the area of ​​each of the transparent areas (TA) is larger than the area of ​​each of the pixel areas (PXA). The area of ​​each of the transparent areas (TA) is larger than the sum of the planar areas of the pixel areas (PXA). In one embodiment, the planar area of ​​the transparent area (TA1) included in the first unit area (PU1) may be larger than the sum of the planar areas of the pixel areas (PXA1-1, PXA2-1, PXA3-1). The planar area of ​​the transparent area (TA2) included in the second unit area (PU2) may be larger than the sum of the planar areas of the pixel areas (PXA1-2, PXA2-2, PXA3-2). Based on the total area of ​​the transparent areas (TA) and the pixel areas (PXA), the planar area of ​​the transparent area (TA) may be 60% or more. In the first unit area (PU1), the planar area of ​​the transmissive area (TA1) may be 60% or more based on the total area of ​​the transmissive area (TA1) and the pixel areas (PXA1-1, PXA2-1, PXA3-1). In the second unit area (PU2), the planar area of ​​the transmissive area (TA2) may be 60% or more based on the total area of ​​the transmissive area (TA2) and the pixel areas (PXA1-2, PXA2-2, PXA3-2). The display device of one embodiment includes a transmissive area that is larger than the light-emitting areas, so that the transmittance of the display device is increased and can be used as a transparent display device.

[0087] Meanwhile, mesh lines (MSL) may overlap in the non-pixel area (NPXA) of the display area (DA). The mesh lines (MSL) may be included in the detection patterns (SP1, SP2, see FIG. 8) included in the detection electrodes (SE1, SE2, see FIG. 8) of the input sensor (IS, see FIG. 8) to be described later. The shape and arrangement of the mesh lines (MSL) will be described in more detail later.

[0088] Again, referring to FIG. 3A, the gate driver circuit (GDC) may be placed in the non-display area (NDA). The gate driver circuit (GDC) may be integrated into the display panel (DP) through an oxide silicon gate driver circuit (OSG) or amorphose silicon gate driver circuit (ASG) process.

[0089] Figure 4 is an equivalent circuit diagram of a pixel according to one embodiment of the present invention.

[0090] FIG. 4 illustrates an example circuit diagram of one pixel (PXij) among unit pixels (PU, see FIG. 3a).

[0091] Referring to FIG. 4, a pixel (PXij) may include a pixel circuit (PC) and a light-emitting element (OLED). The pixel circuit (PC) may include a plurality of transistors (T1-T3) and a capacitor (Cst).

[0092] A plurality of transistors (T1-T3) can be formed through a low temperature polycrystalline silicon (LTPS) process or a low temperature polycrystalline oxide (LTPO) process. Each of the first to third transistors (T1 to T3) can include either a silicon semiconductor or an oxide semiconductor. In this case, the oxide semiconductor can include a crystalline or amorphous oxide semiconductor, and the silicon semiconductor can include amorphous silicon, polycrystalline silicon, etc., and is not limited to any one embodiment.

[0093] Hereinafter, the first to third transistors (T1 to T3) are described as N type, but are not limited thereto, and each of the first to third transistors (T1 to T3) may be a P type transistor or an N type transistor depending on the applied signal. In this case, the source and drain of the P type transistor may correspond to the drain and source of the N type transistor, respectively.

[0094] FIG. 4 illustrates an example of a pixel (PXij) connected to the ith scan line (SCLi), the ith sensing line (SSLi), the jth data line (DLj), and the jth reference line (ILj).

[0095] The pixel (PXij) illustrated in FIG. 4 may correspond to any one of the pixels included in a unit pixel (PU, see FIG. 3a). The pixel circuit (PC) may include a first transistor (T1, a driving transistor), a second transistor (T2, a switching transistor), a third transistor (T3, a sensing transistor), and a capacitor (Cst). However, the pixel circuit (PC) may further include additional transistors and additional capacitors, and is not limited to any one embodiment.

[0096] Each of the first to third transistors (T1 to T3) may include a source (S1, S2, S3), a drain (D1, D2, D3), and a gate (G1, G2, G3).

[0097] The light-emitting device (OLED) may be an organic light-emitting device or an inorganic light-emitting device including an anode (a first electrode) and a cathode (a second electrode). The anode of the light-emitting device (OLED) may receive a first voltage (ELVDD) through a first transistor (T1), and the cathode of the light-emitting device (OLED) may receive a second voltage (ELVSS). The light-emitting device (OLED) may emit light by receiving the first voltage (ELVDD) and the second voltage (ELVSS).

[0098] A first transistor (T1) may include a drain (D1) receiving a first voltage (ELVDD), a source (S1) connected to the anode of the light-emitting element (OLED), and a gate (G1) connected to a capacitor (Cst). The first transistor (T1) may control a driving current flowing through the light-emitting element (OLED) from the first voltage (ELVDD) in response to a voltage value stored in the capacitor (Cst).

[0099] The second transistor (T2) may include a drain (D2) connected to the j-th data line (DLj), a source (S2) connected to a capacitor (Cst), and a gate (G2) receiving the ith write scan signal (SCi). The second transistor (T2) provides a data voltage (Vd) to the first transistor (T1) in response to the ith first scan signal (SCi).

[0100] A third transistor (T3) may include a source (S3) connected to the jth reference line (ILj), a drain (D3) connected to the anode of the light-emitting element (OLED), and a gate (G3) receiving the ith sampling scan signal (SSi). The jth reference line (ILj) may receive a reference voltage (Vr).

[0101] The capacitor (Cst) can store voltage differences of various values ​​depending on the input signal. For example, the capacitor (Cst) can store a voltage corresponding to the difference between the voltage received from the second transistor (T2) and the first voltage (ELVDD).

[0102] In the present invention, the equivalent circuit of the pixel (PXij) is not limited to the equivalent circuit illustrated in Fig. 4. In other embodiments of the present invention, the pixel (PXij) may be implemented in various forms for emitting light from the light-emitting element (OLED).

[0103] FIG. 5 and FIG. 6 are each cross-sectional views of a display device (DD) according to an embodiment of the present invention. FIG. 5 is a cross-sectional view taken along line I-I' of FIG. 3b. FIG. 6 is a cross-sectional view taken along line II-II' of FIG. 3b. FIG. 5 illustrates only a portion of the configuration of the display device (DD), and components such as a window (WD, see FIG. 2) are omitted.

[0104] Referring to FIG. 5, the display device (DD) may include a display panel (DP), an input sensor (IS) disposed on the display panel (DP), and an optical layer (OSL) disposed on the input sensor (IS).

[0105] A display panel (DP) may include a base substrate (BS), a circuit element layer (DP-CL) disposed on the base substrate (BS), a display element layer (DP-OLED), and an encapsulation layer (TFE).

[0106] The base substrate (BS) may include a synthetic resin film. The synthetic resin layer may include a thermosetting resin. In particular, the synthetic resin layer may include at least one of an acrylic resin, a methacrylic resin, a polyisoprene, a vinyl resin, an epoxy resin, a urethane resin, a cellulose resin, a siloxane resin, a polyamide resin, and a perylene resin. In addition, the base substrate (BS) may include a glass substrate, a metal substrate, or an organic / inorganic composite material substrate.

[0107] The circuit element layer (DP-CL) is formed by forming insulating, semiconductor, and conductive layers through processes such as coating and deposition. Subsequently, the insulating, semiconductor, and conductive layers can be selectively patterned using photolithography and etching processes. These processes form semiconductor patterns, conductive patterns, and signal lines. Patterns placed on the same layer are formed through the same process.

[0108] The circuit element layer (DP-CL) includes a driving circuit or signal line constituting a pixel. The display element layer (DP-OLED) may include a light-emitting element (OLED, see FIG. 4) included in the pixel and a pixel defining layer (PDL).

[0109] The circuit element layer (DP-CL) may include first to fifth insulating layers (10, 20, 30, 40, 50) and conductive patterns. According to one embodiment, the first insulating layer (10) to the fourth insulating layer (40) may be an inorganic layer including a single layer or multiple layers, and the fifth insulating layer (50) may be an organic layer.

[0110] A light-shielding pattern (BML) may be arranged on a base substrate (BS). In one embodiment, the light-shielding pattern (BML) is connected to a semiconductor pattern of an overlapping transistor (T1), and may receive a signal applied to the semiconductor pattern to form a sync structure under the semiconductor pattern. In one embodiment, the light-shielding pattern (BML) may include sequentially stacked metal layers. A first layer may include titanium, and a second layer may include copper.

[0111] The first insulating layer (10) may be disposed on a base substrate (BS) and may cover a light-shielding pattern (BML). According to one embodiment, the first insulating layer (10) may include sequentially laminated inorganic layers. The first layer may include silicon nitride, and the second layer may include silicon oxide.

[0112] A semiconductor pattern of a transistor (T1) may be disposed on a first insulating layer (10). The semiconductor pattern may include a source region (S1), a channel region (A1, or active region), and a drain region (D1). According to one embodiment, the semiconductor pattern may include IGZO (Indium Gallium Zinc Oxide).

[0113] The second insulating layer (20) may be disposed between the semiconductor pattern and the gate (G1). The second insulating layer (20) may expose an area of ​​the semiconductor pattern other than the active pattern (A1). The second insulating layer (20) may be patterned using the gate (G1) as a mask. According to one embodiment, the second insulating layer (20) may include silicon dioxide.

[0114] The gate (G1) may be disposed on the second insulating layer (20). According to one embodiment, the gate (G1) may include sequentially stacked metal layers. The first layer may include titanium, and the second layer may include copper.

[0115] The third insulating layer (30) may be disposed on the first insulating layer (10) and the second insulating layer (20) and may cover the gate (G1) and the semiconductor pattern exposed from the gate (G1). According to one embodiment, the third insulating layer (30) may include silicon oxynitride.

[0116] The first connection electrode (CNE1) may be disposed on the third insulating layer (30). The first connection electrode (CNE1) may be connected to the source region (S1) through a contact hole defined in the third insulating layer (30). According to one embodiment, the first connection electrode (CNE1) may include sequentially stacked metal layers. The first layer may include titanium, the second layer may include copper, and the third layer may include indium tin oxide (ITO).

[0117] The fourth insulating layer (40) may be disposed on the third insulating layer (30) and may cover the first connection electrode (CNE1). According to one embodiment, the fourth insulating layer (40) may include silicon nitride. A layer including silicon nitride has a higher film density than a layer including silicon oxide and / or silicon oxynitride, thereby reducing transmittance. Therefore, in order to increase transmittance in a transparent display panel (DP) such as the present invention, removal of silicon nitride in the transmission area (TA) is required.

[0118] The second connection electrode (CNE2) may be disposed on the fourth insulating layer (40). The second connection electrode (CNE2) may be connected to the first connection electrode (CNE1) through a contact hole defined in the fourth insulating layer (40). According to one embodiment, the second connection electrode (CNE2) may include the same material as the first connection electrode (CNE1). The display panel (DP) according to one embodiment may omit the second connection electrode (CNE2) and is not limited to any one embodiment.

[0119] The fifth insulating layer (50) may be disposed on the fourth insulating layer (40) and cover the second connection electrode (CNE2). According to one embodiment, the fifth insulating layer (50) may include an organic material. For example, the fifth insulating layer (50) may include photosensitive polyimide (PSPI).

[0120] The display element layer (DP-OLED) may be disposed on the fifth insulating layer (50). The display element layer (DP-OLED) may include a light-emitting element (OLED) and a pixel defining layer (PDL). The light-emitting element (OLED) may include a first electrode (AE), a functional layer (FNL), and a second electrode (CE). The functional layer (FNL) of the light-emitting element (OLED) according to one embodiment may include at least one light-emitting layer.

[0121] A pixel defining layer (PDL) may be disposed on the fifth insulating layer (50) and may cover the second connection electrode (CNE2). The pixel defining layer (PDL) may include an organic material. For example, the pixel defining layer (PDL) may include a photosensitive polyimide (PSPI). The pixel defining layer (PDL) may include a light-emitting opening (PDL-OP). The light-emitting openings (PDL-OP) of the pixel defining layer (PDL) are provided in plurality, and each of the light-emitting openings (PDL-OP) may be defined as light-emitting areas as described in FIG. 3b. An area where the pixel defining layer (PDL) is disposed may be defined as a non-light-emitting area.

[0122] A first electrode (AE) of a light-emitting element (OLED) is disposed on a fifth insulating layer (50). A light-emitting opening (PDL-OP) of a pixel defining layer (PDL) exposes at least a portion of the first electrode (AE). According to one embodiment, the first electrode (AE) may include sequentially stacked conductive material layers. For example, the first electrode (AE) may include a conductive material layer having a three-layer structure. A first layer of the first electrode (AE) may include indium tin oxide (ITO), a second layer may include silver, and a third layer may include indium tin oxide (ITO).

[0123] The functional layer (FNL) may include at least one organic material layer. The functional layer (FNL) may include at least one light-emitting layer. The light-emitting layer may generate light of a specific wavelength. The light-emitting layer may include an organic light-emitting material or an inorganic light-emitting material.

[0124] The functional layer (FNL) may further include a hole control layer and an electron control layer. At least one organic material layer included in the functional layer (FNL) may be commonly disposed in a light-emitting area and a non-light-emitting area. At least one organic material layer included in the functional layer (FNL) may be commonly disposed in pixels. In the present specification, layers formed as a common layer may be disposed across the entire display area (DA, see FIG. 3a) and the non-display area (NDA, see FIG. 3a). Layers formed as a common layer may be defined as a "common layer."

[0125] The encapsulation layer (TFE) can be disposed on the display element layer (DP-OLED) to protect the light-emitting element (OLED). The encapsulation layer (TFE) can include inorganic layers and an organic layer disposed between the inorganic layers. The inorganic layers can protect the light-emitting element (OLED) from moisture and oxygen, and the organic layer can protect the light-emitting element (OLED) from foreign substances such as dust particles.

[0126] Inorganic layers can prevent external moisture or oxygen from penetrating the functional layer (FNL) of an organic light-emitting device (OLED). The inorganic layers may include silicon nitride, silicon oxide, or a combination thereof. The inorganic layers can be formed through a deposition process.

[0127] The organic layer can provide a flat surface on the inorganic layer. Curves formed on the upper surface of the inorganic layer or particles present on the inorganic layer are covered by the organic layer, thereby preventing the surface state of the upper surface of the inorganic layer from affecting the components formed on the organic layer. The organic layer can include an organic material.

[0128] The input sensor (IS) includes a plurality of conductive patterns. The input sensor (IS) may include at least one conductive layer (or at least one sensor conductive layer) including a plurality of conductive patterns, and at least one insulating layer (or at least one sensor insulating layer). In the present embodiment, the input sensor (IS) may include a first insulating layer (IS-IL1, or first sensor insulating layer), a first conductive layer (IS-CL1, or first sensor conductive layer), a second insulating layer (IS-IL2, or second sensor insulating layer), a second conductive layer (IS-CL2, or second sensor conductive layer), and a third insulating layer (IS-IL3, or third sensor insulating layer). FIG. 5 briefly illustrates a plurality of conductive patterns included in each of the first conductive layer (IS-CL1) and the second conductive layer (IS-CL2).

[0129] The first insulating layer (IS-IL1) may be directly disposed on the display panel (DP). The first insulating layer (IS-IL1) may be an inorganic layer including at least one of silicon nitride, silicon oxynitride, and silicon oxide. Each of the first conductive layer (IS-CL1) and the second conductive layer (IS-CL2) may have a single-layer structure or a multi-layer structure laminated along a third direction (DR3). The first conductive layer (IS-CL1) and the second conductive layer (IS-CL2) may include conductive lines defining a mesh-shaped electrode. The conductive lines of the first conductive layer (IS-CL1) and the conductive lines of the second conductive layer (IS-CL2) may or may not be connected through a contact hole penetrating the second insulating layer (IS-IL2) depending on their positions.

[0130] The first conductive layer (IS-CL1) and the second conductive layer (IS-CL2) of the single-layer structure may include a metal layer or a transparent conductive layer. The metal layer may include molybdenum, silver, titanium, copper, aluminum, or an alloy thereof. The transparent conductive layer may include a transparent conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnOx), or indium zinc tin oxide (IZTO). In addition, the transparent conductive layer may include a conductive polymer such as PEDOT, metal nanowires, graphene, or the like.

[0131] The first conductive layer (IS-CL1) and the second conductive layer (IS-CL2) of the multilayer structure may include metal layers. The metal layers may have a three-layer structure of, for example, titanium / aluminum / titanium. The conductive layer of the multilayer structure may include at least one metal layer and at least one transparent conductive layer. The second insulating layer (IS-IL2) may be disposed between the first conductive layer (IS-CL1) and the second conductive layer (IS-CL2). The second insulating layer (IS-IL2) disposed between the first conductive layer (IS-CL1) and the second conductive layer (IS-CL2) may be described as a “sensing insulating layer” in this specification. The third insulating layer (IS-IL3) may cover the second conductive layer (IS-CL2). In one embodiment of the present invention, the third insulating layer (IS-IL3) may be omitted. The second insulating layer (IS-IL2) and the third insulating layer (IS-IL3) may include an inorganic layer or an organic layer.

[0132] An optical layer (OSL) can convert the color of light provided from a display element. The optical layer (OSL) can include a light control pattern and a structure for increasing the light conversion efficiency.

[0133] An optical layer (OSL) may be disposed on the input sensor (IS). The optical layer (OSL) may include a light control layer (CCL), a low refractive index layer (LR), a color filter layer (CFL), and a base layer (BL). In this specification, the optical layer (OSL) may be referred to as an upper panel.

[0134] A light control layer (CCL) can be disposed on a display element layer (DP-OLED) including a light emitting element (OLED). The light control layer (CCL) includes a bank (BMP), a first light control pattern (CCP-R), and a first barrier layer (CAP1).

[0135] A bank (BMP) may include a base resin and additives. The base resin may be composed of various resin compositions, which may be generally referred to as a binder. The additives may include a coupling agent and / or a photoinitiator. The additives may further include a dispersant.

[0136] The bank (BMP) may include a black coloring agent for light blocking. The bank (BMP) may include a black dye or pigment mixed into the base resin. In one embodiment, the black coloring agent may include carbon black, a metal such as chromium, or an oxide thereof.

[0137] The bank (BMP) may include a first bank opening (BOH1) corresponding to the light-emitting opening (PDL-OP). In a plan view, the first bank opening (BOH1) overlaps the light-emitting opening (PDL-OP) and has a larger area than the light-emitting opening (PDL-OP). That is, the first bank opening (BOH1) may have a larger area than the first light-emitting area (EA1) defined by the light-emitting opening (PDL-OP). Meanwhile, in the present specification, "corresponds" means that two configurations overlap when viewed in the thickness direction (DR3) of the display panel (DP), and is not limited to the same area.

[0138] A first optical control pattern (CCP-R) may be arranged inside the first bank opening (BOH1). The first optical control pattern (CCP-R) may change the optical properties of the source light.

[0139] The first light control pattern (CCP-R) may include quantum dots for changing the optical properties of the source light. The first light control pattern (CCP-R) may include first quantum dots for converting the source light into light of a different wavelength. In the first light control pattern (CCP-R) overlapping the first pixel area (PXA1), the first quantum dots may convert the source light into red light.

[0140] As used herein, "quantum dot" refers to a crystal of a semiconductor compound. Quantum dots can emit light of various emission wavelengths depending on the size of the crystal. Quantum dots can also emit light of various emission wavelengths by adjusting the element ratio within the quantum dot compound.

[0141] The diameter of the quantum dot may be, for example, about 1 nm to 10 nm.

[0142] The above quantum dots can be synthesized by a wet chemical process, an organometallic chemical vapor deposition process, a molecular beam epitaxy process, or a similar process.

[0143] The above wet chemical process is a method for growing quantum dot particle crystals by mixing an organic solvent and a precursor material. As the crystals grow, the organic solvent naturally acts as a dispersant coordinated to the quantum dot crystal surface, controlling the crystal growth. Therefore, the wet chemical process is easier and less expensive than vapor deposition methods such as metal-organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE), allowing for controlled growth of quantum dot particles.

[0144] The core of the quantum dot can be selected from a group II-VI compound, a group III-V compound, a group III-VI compound, a group I-III-VI compound, a group IV-VI compound, a group IV element, a group IV compound, and a combination thereof.

[0145] The group II-VI compound is a binary compound selected from the group consisting of CdSe, CdTe, CdS, ZnS, ZnSe, ZnTe, ZnO, HgS, HgSe, HgTe, MgSe, MgS and mixtures thereof; a ternary compound selected from the group consisting of CdSeS, CdSeTe, CdSTe, ZnSeS, ZnSeTe, ZnSTe, HgSeS, HgSeTe, HgSTe, CdZnS, CdZnSe, CdZnTe, CdHgS, CdHgSe, CdHgTe, HgZnS, HgZnSe, HgZnTe, MgZnSe, MgZnS and mixtures thereof; And it may be selected from the group consisting of a four-element compound selected from the group consisting of HgZnTeS, CdZnSeS, CdZnSeTe, CdZnSTe, CdHgSeS, CdHgSeTe, CdHgSTe, HgZnSeS, HgZnSeTe, HgZnSTe and mixtures thereof. Meanwhile, the II-VI group semiconductor compound may further include a Group I metal and / or a Group IV element. The Group I-II-VI compound may be selected from CuSnS or CuZnS, and the Group II-IV-VI compound may be selected from ZnSnS, etc. The Group I-II-IV-VI compound may be selected from a four-element compound selected from the group consisting of Cu2ZnSnS2, Cu2ZnSnS4, Cu2ZnSnSe4, Ag2ZnSnS2 and mixtures thereof.

[0146] The III-VI group compounds may include binary compounds such as In2S3, In2Se3, etc., ternary compounds such as InGaS3, InGaSe3, etc., or any combination thereof.

[0147] Group I-III-VI compounds are ternary compounds selected from the group consisting of AgInS, AgInS2, CuInS, CuInS2, AgGaS2, CuGaS2CuGaO2, AgGaO2, AgAlO2 and mixtures thereof, or AgInGaS2, It can be selected from four-element compounds such as CuInGaS2.

[0148] The group III-V compound may be selected from the group consisting of binary compounds selected from the group consisting of GaN, GaP, GaAs, GaSb, AlN, AlP, AlAs, AlSb, InN, InP, InAs, InSb, and mixtures thereof, ternary compounds selected from the group consisting of GaNP, GaNAs, GaNSb, GaPAs, GaPSb, AlNP, AlNAs, AlNSb, AlPAs, AlPSb, InGaP, InAlP, InNP, InNAs, InNSb, InPAs, InPSb, and mixtures thereof, and quaternary compounds selected from the group consisting of GaAlNP, GaAlNAs, GaAlNSb, GaAlPAs, GaAlPSb, GaInNP, GaInNAs, GaInNSb, GaInPAs, GaInPSb, InAlNP, InAlNAs, InAlNSb, InAlPAs, InAlPSb, and mixtures thereof. Meanwhile, the group III-V compound may further include a group II metal. For example, InZnP may be selected as the group III-II-V compound.

[0149] The group IV-VI compound may be selected from the group consisting of binary compounds selected from the group consisting of SnS, SnSe, SnTe, PbS, PbSe, PbTe and mixtures thereof; ternary compounds selected from the group consisting of SnSeS, SnSeTe, SnSTe, PbSeS, PbSeTe, PbSTe, SnPbS, SnPbSe, SnPbTe and mixtures thereof; and quaternary compounds selected from the group consisting of SnPbSSe, SnPbSeTe, SnPbSTe and mixtures thereof.

[0150] Examples of the above II-IV-V group semiconductor compounds may be ternary compounds selected from the group consisting of ZnSnP, ZnSnP2, ZnSnAs2, ZnGeP2, ZnGeAs2, CdSnP2, and CdGeP2 and mixtures thereof.

[0151] The group IV element may be selected from the group consisting of Si, Ge, and mixtures thereof. The group IV compound may be a binary compound selected from the group consisting of SiC, SiGe, and mixtures thereof.

[0152] Each element included in the multi-element compounds such as the above binary, ternary and quaternary compounds may exist in the particles in a uniform or non-uniform concentration. That is, the chemical formula indicates the type of elements included in the compound, and the element ratio within the compound may be different. For example, AgInGaS2 is AgIn x Ga 1-x It can mean S2 (where x is a real number between 0 and 1).

[0153] Here, binary, ternary, or quaternary compounds may exist within the particle at a uniform concentration, or may exist within the same particle with partially different concentration distributions. Furthermore, one quantum dot may have a core / shell structure, where one quantum dot surrounds another. In a core / shell structure, the concentration of the element present in the shell may have a concentration gradient, decreasing toward the core.

[0154] In some embodiments, the quantum dot may have a core-shell structure comprising a core comprising the aforementioned nanocrystals and a shell surrounding the core. The shell of the quantum dot may function as a protective layer to maintain semiconductor properties by preventing chemical modification of the core and / or as a charging layer to impart electrophoretic properties to the quantum dot. The shell may be a single layer or a multilayer. Examples of the shell of the quantum dot include a metal or non-metal oxide, a semiconductor compound, or a combination thereof.

[0155] For example, the oxide of the metal or non-metal may be a binary compound such as SiO2, Al2O3, TiO2, ZnO, MnO, Mn2O3, Mn3O4, CuO, FeO, Fe2O3, Fe3O4, CoO, Co3O4, NiO, or a ternary compound such as MgAl2O4, CoFe2O4, NiFe2O4, CoMn2O4, but the present invention is not limited thereto.

[0156] In addition, the semiconductor compound may be exemplified by CdS, CdSe, CdTe, ZnS, ZnSe, ZnTe, ZnSeS, ZnTeS, GaAs, GaP, GaSb, HgS, HgSe, HgTe, InAs, InP, InGaP, InSb, AlAs, AlP, AlSb, etc., but the present invention is not limited thereto.

[0157] Quantum dots can have a full width of half maximum (FWHM) of an emission wavelength spectrum of about 45 nm or less, preferably about 40 nm or less, and more preferably about 30 nm or less, and color purity and color reproducibility can be improved within this range. In addition, since light emitted by these quantum dots is emitted in all directions, a wide viewing angle can be improved.

[0158] In addition, the shape of the quantum dot is not particularly limited to a shape commonly used in the field, but more specifically, a shape such as a spherical, pyramidal, multi-arm, or cubic nanoparticle, nanotube, nanowire, nanofiber, or nanoplatelet particle can be used.

[0159] Since the energy band gap of quantum dots can be controlled by adjusting the size of the quantum dots or the element ratio within the quantum dot compound, light of various wavelengths can be obtained from the quantum dot light-emitting layer. Therefore, by using quantum dots as described above (using quantum dots of different sizes or varying the element ratio within the quantum dot compound), a light-emitting device that emits light of various wavelengths can be implemented. Specifically, the size of the quantum dots or the element ratio within the quantum dot compound can be selected to emit red, green, and / or blue light. In addition, the quantum dots can be configured to emit white light by combining light of various colors.

[0160] In one embodiment, a quantum dot included in a first light control pattern (CCP-R) overlapping a first pixel area (PXA1) may have a red emission color. The smaller the particle size of the quantum dot, the more it may emit light in a shorter wavelength range. For example, among quantum dots having the same core, the particle size of a quantum dot that emits green light may be smaller than the particle size of a quantum dot that emits red light. Additionally, among quantum dots having the same core, the particle size of a quantum dot that emits blue light may be smaller than the particle size of a quantum dot that emits green light. However, the embodiment is not limited thereto, and even among quantum dots having the same core, the particle size may be controlled depending on a shell forming material, shell thickness, etc.

[0161] Meanwhile, if quantum dots have various emission colors such as blue, red, and green, quantum dots with different emission colors may have different core materials.

[0162] The first light control pattern (CCP-R) may further include a scatterer. The first light control pattern (CCP-R) may include a first quantum dot that converts blue light into red light and a scatterer that scatters light.

[0163] The scatterer may be an inorganic particle. For example, the scatterer may comprise at least one of TiO2, ZnO, Al2O3, SiO2, and hollow silica. The scatterer may comprise any one of TiO2, ZnO, Al2O3, SiO2, and hollow silica, or may be a mixture of two or more materials selected from TiO2, ZnO, Al2O3, SiO2, and hollow silica.

[0164] The first light control pattern (CCP-R) may include a base resin in which the first quantum dots and scatterers are dispersed. The base resin, which is a medium in which the first quantum dots and scatterers are dispersed, may be composed of various resin compositions that may generally be referred to as binders. For example, the base resin may be an acrylic resin, a urethane resin, a silicone resin, an epoxy resin, etc. The base resin may be a transparent resin.

[0165] In this embodiment, the first light control pattern (CCP-R) can be formed by an inkjet process. A liquid composition can be provided within the bank opening (BOH). The composition, which is polymerized by a thermal or photo-curing process, reduces in volume after curing.

[0166] The light control layer (CCL) may include a first barrier layer (CAP1) disposed on one surface of the first light control pattern (CCP-R). The first barrier layer (CAP1) may serve to prevent the penetration of moisture and / or oxygen (hereinafter referred to as “moisture / oxygen”) and to improve the optical characteristics of the optical layer (OSL) by controlling the refractive index. The first barrier layer (CAP1) may be disposed on one upper surface or one lower surface of the first light control pattern (CCP-R) to block the first light control pattern (CCP-R) from being exposed to moisture / oxygen, and in particular, may block quantum dots included in the first light control pattern (CCP-R) from being exposed to moisture / oxygen. The first barrier layer (CAP1) may also protect the first light control pattern (CCP-R) from external impact.

[0167] In one embodiment, the first barrier layer (CAP1) may be disposed spaced apart from the display element layer (DP-OLED) with the first light control pattern (CCP-R) interposed therebetween. That is, the first barrier layer (CAP1) may be disposed on the upper surface of the first light control pattern (CCP-R). In one embodiment, the light control layer (CCL) may include a second barrier layer (CAP2) disposed between the first light control pattern (CCP-R) and the display element layer (DP-OLED). The first barrier layer (CAP1) may cover the upper surface of the first light control pattern (CCP-R) adjacent to the low-refractive-index layer (LR), and the second barrier layer (CAP2) may cover the lower surface of the first light control pattern (CCP-R) adjacent to the display element layer (DP-OLED). Meanwhile, in this specification, the “upper surface” may be a surface located above in the third direction (DR3), and the “lower surface” may be a surface located below in the third direction (DR3).

[0168] Additionally, the first barrier layer (CAP1) and the second barrier layer (CAP2) may cover one side of the bank (BMP) as well as the first light control pattern (CCP-R).

[0169] The first barrier layer (CAP1) may cover one side of the bank (BMP) adjacent to the low-refractive-index layer (LR) and the first light control pattern (CCP-R). The first barrier layer (CAP1) may be disposed directly under the low-refractive-index layer (LR). The second barrier layer (CAP2) may be disposed directly on the encapsulation layer (TFE). The light control layer (CCL) may be disposed on the display element layer (DP-OLED) and the encapsulation layer (TFE) with the second barrier layer (CAP2) interposed therebetween. The light control patterns (CCP-R, CCP-G, CCP-B) of the light control layer (CCL) may be formed on the second barrier layer (CAP2) disposed on the encapsulation layer (TFE) through a continuous process.

[0170] The first barrier layer (CAP1) and the second barrier layer (CAP2) may be formed of an inorganic material. In the display panel (DP) of one embodiment, the first barrier layer (CAP1) may include silicon oxynitride (SiON). The first barrier layer (CAP1) and the second barrier layer (CAP2) may both include silicon oxynitride. However, the present invention is not limited thereto, and each of the first barrier layer (CAP1) and the second barrier layer (CAP2) may include silicon oxide (SiO x ) or silicon nitride (SiN x ) may be included. In one embodiment, the first barrier layer (CAP1) disposed on the upper side of the first light control pattern (CCP-R) may include silicon oxynitride, and the second barrier layer (CAP2) disposed on the lower side of the first light control pattern (CCP-R) may include silicon oxide.

[0171] A color filter layer (CFL) may be disposed on the light control layer (CCL). The color filter layer (CFL) includes at least one color filter. The color filter transmits light within a specific wavelength range and blocks light outside the corresponding wavelength range. The first color filter (CF1) corresponding to the first pixel area (PXA1) may transmit red light and block green and blue light.

[0172] The first color filter (CF1) includes a base resin and a dye and / or pigment dispersed in the base resin. The base resin is a medium in which the dye and / or pigment is dispersed and may be composed of various resin compositions, which may generally be referred to as a binder.

[0173] The first color filter (CF1) may have a uniform thickness within the first pixel area (PXA1). Light converted from a blue source light to red light through the first light control pattern (CCP-R) may be provided to the outside with uniform brightness within the first pixel area (PXA1).

[0174] The optical layer (OSL) may further include a filling layer (FML) disposed between the light control layer (CCL) and the color filter layer (CFL). In one embodiment, the filling layer (FML) may fill a space between the light control layer (CCL) and the color filter layer (CFL). The filling layer (FML) may be disposed directly on the first barrier layer (CAP1), and the color filter layer (CFL) may be disposed directly on the filling layer (FML). A lower surface of the filling layer (FML) may be in contact with an upper surface of the first barrier layer (CAP1), and an upper surface of the filling layer (FML) may be in contact with lower surfaces of the color filters (CF1, CF2, CF3) of the color filter layer (CFL).

[0175] The filler layer (FML) can function as a buffer between the light control layer (CCL) and the color filter layer (CFL). In one embodiment, the filler layer (FML) can have a shock absorption function, etc., and can increase the strength of the display panel (DP). The filler layer (FML) can be formed from a filler resin including a polymer resin. For example, the filler layer (FML) can be formed from a filler resin including an acrylic resin or an epoxy resin.

[0176] Meanwhile, the filler layer (FML) may be positioned between the light control layer (CCL) and the color filter layer (CFL) to increase light extraction efficiency or may function as an optical functional layer, such as preventing reflected light from entering the light control layer (CCL). The filler layer (FML) may be a layer having a lower refractive index compared to adjacent layers.

[0177] In one embodiment, the display panel (DP) may further include a base layer (BL) disposed on a color filter layer (CFL). The base layer (BL) may be a member that provides a reference surface on which the color filter layer (CFL), the low-refractive layer (LR), and the light control layer (CCL) are disposed. The base layer (BL) may be a glass substrate, a metal substrate, a plastic substrate, or the like. However, the embodiment is not limited thereto, and the base layer (BL) may be an inorganic layer, an organic layer, or a composite material layer. In addition, unlike the embodiment illustrated, the base layer (BL) may be omitted in one embodiment.

[0178] Although not shown, an anti-reflection layer may be disposed on the base layer (BL). The anti-reflection layer may be a layer that reduces the reflectance of external light incident from the outside. The anti-reflection layer may be a layer that selectively transmits light emitted from the display panel (DP). In one embodiment, the anti-reflection layer may be a single layer comprising a dye and / or pigment dispersed in a base resin. The anti-reflection layer may be provided as a single continuous layer that overlaps the entire pixel areas (PXA, see FIG. 3b).

[0179] The anti-reflection layer may not include a polarizing layer. Accordingly, light passing through the anti-reflection layer and incident on the display element layer (DP-OLED) may be unpolarized light. The display element layer (DP-OLED) can receive unpolarized light from above the anti-reflection layer.

[0180] Referring to FIG. 6, the display panel (DP) may include a base substrate (BS) and a circuit element layer (DP-CL) disposed on the base substrate (BS). The circuit element layer (DP-CL) may be disposed on the base substrate (BS). The circuit element layer (DP-CL) may include an insulating layer, a semiconductor pattern, a conductive pattern, a signal line, and the like. The insulating layer, the semiconductor layer, and the conductive layer may be formed on the base substrate (BS) by a coating, deposition, or the like, and then the insulating layer, the semiconductor layer, and the conductive layer may be selectively patterned through multiple photolithography processes. Thereafter, the semiconductor pattern, the conductive pattern, and the signal line included in the circuit element layer (DP-CL) may be formed. In one embodiment, the circuit element layer (DP-CL) may include a transistor (T1), a buffer layer, and a plurality of insulating layers.

[0181] According to one embodiment, a light emitting device (OLED) may include a first electrode (AE), a second electrode (CE) facing the first electrode (AE), and a functional layer (FNL) disposed between the first electrode (AE) and the second electrode (CE). The functional layer (FNL) included in the light emitting device (OLED) may include at least an emission layer. The emission layer may include an organic emission material as an emission material, or may include quantum dots. The functional layer (FNL) may further include a hole control layer and an electron control layer. Meanwhile, although not illustrated, the light emitting device (OLED) may further include a capping layer (not illustrated) disposed on the second electrode (CE).

[0182] A pixel defining layer (PDL) is disposed on a circuit element layer (DP-CL) and can cover a portion of a first electrode (AE). A light-emitting opening (PDL-OP) is defined in the pixel defining layer (PDL). The light-emitting opening (PDL-OP) of the pixel defining layer (PDL) exposes at least a portion of the first electrode (AE). In the present embodiment, light-emitting areas (EA1, EA2, EA3) are defined to correspond to a portion of the first electrode (AE) exposed by the light-emitting opening (PDL-OP).

[0183] The display element layer (DP-OLED) may include a first light-emitting area (EA1), a second light-emitting area (EA2), and a third light-emitting area (EA3). The first light-emitting area (EA1), the second light-emitting area (EA2), and the third light-emitting area (EA3) may be regions defined by a pixel defining layer (PDL). The first light-emitting area (EA1), the second light-emitting area (EA2), and the third light-emitting area (EA3) may correspond to the first pixel area (PXA1), the second pixel area (PXA2), and the third pixel area (PXA3), respectively.

[0184] The light-emitting areas (EA1, EA2, EA3) may overlap with the pixel areas (PXA1, PXA2, PXA3). When viewed in a planar manner, the area of ​​the pixel areas (PXA1, PXA2, PXA3) defined by the color filters (CF1, CF2, CF3) may be larger than the area of ​​the light-emitting areas (EA1, EA2, EA3) defined by the pixel defining layer (PDL). However, the present invention is not limited thereto, and the area of ​​the pixel areas (PXA1, PXA2, PXA3) may be substantially the same as the area of ​​the light-emitting areas (EA1, EA2, EA3).

[0185] In a light-emitting device (OLED), a first electrode (AE) is disposed on a circuit element layer (DP-CL). The first electrode (AE) may be an anode or a cathode. Additionally, the first electrode (AE) may be a pixel electrode. The first electrode (AE) may be a transmissive electrode, a semi-transmissive electrode, or a reflective electrode.

[0186] Fig. 7 is a cross-sectional view of a light-emitting device according to one embodiment of the present invention. Fig. 7 illustrates the configuration of a functional layer (FNL) in the light-emitting device of one embodiment illustrated in Figs. 5 and 6. Fig. 7 exemplarily illustrates a light-emitting device (OLED) including a plurality of light-emitting stacks (ST1, ST2, ST3, ST4) arranged between a first electrode (AE) and a second electrode (CE).

[0187] Referring to FIG. 7, a light emitting device (OLED) of one embodiment may include a first electrode (AE), a second electrode (CE) facing the first electrode (AE), and first to fourth light emitting stacks (ST1, ST2, ST3, ST4) disposed between the first electrode (AE) and the second electrode (CE). Meanwhile, FIG. 5 exemplarily illustrates that the light emitting device (OLED) includes four light emitting stacks, but the number of light emitting stacks included in the light emitting device (OLED) may be less or more than this.

[0188] The light emitting device (OLED) may include first to third charge generation layers (CGL1, CGL2, CGL3) disposed between first to fourth light emitting stacks (ST1, ST2, ST3, ST4).

[0189] When voltage is applied, each of the first to third charge generation layers (CGL1, CGL2, CGL3) can generate charges (electrons and holes) by forming a complex through an oxidation-reduction reaction. Thereafter, the first to third charge generation layers (CGL1, CGL2, CGL3) can provide the generated charges to the adjacent stacks (ST1, ST2, ST3, ST4), respectively. The first to third charge generation layers (CGL1, CGL2, CGL3) can double the efficiency of current generated in the adjacent stacks (ST1, ST2, ST3, ST4) and can play a role in controlling the balance of charges between the adjacent stacks (ST1, ST2, ST3, ST4).

[0190] Each of the first to third charge generation layers (CGL1, CGL2, CGL3) may include an n-type layer and a p-type layer. The first to third charge generation layers (CGL1, CGL2, CGL3) may have a structure in which the n-type layer and the p-type layer are bonded to each other. However, the present invention is not limited thereto, and the first to third charge generation layers (CGL1, CGL2, CGL3) may include only one of the n-type layer and the p-type layer. The n-type layer may be a charge generation layer that provides electrons to an adjacent stack. The n-type layer may be a layer in which an n-dopant is doped into a base material. The p-type layer may be a charge generation layer that provides holes to an adjacent stack.

[0191] In one embodiment, the thickness of each of the first to third charge generation layers (CGL1, CGL2, CGL3) may be 1 angstrom (Å) or more and 150 angstroms (Å) or less. The concentration of the n-dopant doped in the first to third charge generation layers (CGL1, CGL2, CGL3) may be 0.1% or more and 3% or less, and specifically, 1% or less. When the concentration is less than 0.1%, the effect of the first to third charge generation layers (CGL1, CGL2, CGL3) controlling the balance of charges may hardly occur. When the concentration is greater than 3%, the light efficiency of the light-emitting element (OLED) may be reduced.

[0192] Each of the first to third charge generation layers (CGL1, CGL2, CGL3) may include a charge generation compound composed of an aryl amine organic compound, a metal, an oxide, carbide, fluoride of a metal, or a mixture thereof. For example, the aryl amine organic compound may include α-NPD, 2-TNATA, TDATA, MTDATA, sprio-TAD, or sprio-NPB. The metal may include cesium (Cs), molybdenum (Mo), vanadium (V), titanium (Ti), tungsten (W), barium (Ba), or lithium (Li). The oxide, carbide, and fluoride of the metal may include Re2O7, MoO3, V2O5, WO3, TiO2, Cs2CO3, BaF, LiF, or CsF. However, the materials of the first to third charge generation layers (CGL1, CGL2, CGL3) are not limited to the above examples.

[0193] Each of the first to fourth light-emitting stacks (ST1, ST2, ST3, and ST4) may include a light-emitting layer. The first light-emitting stack (ST1) may include a first light-emitting layer (BEML-1), the second light-emitting stack (ST2) may include a second light-emitting layer (BEML-2), the third light-emitting stack (ST3) may include a third light-emitting layer (BEML-3), and the fourth light-emitting stack (ST4) may include a fourth light-emitting layer (GEML). Some of the light-emitting layers included in the first to fourth light-emitting stacks (ST1, ST2, ST3, and ST4) may emit substantially the same color light, and some may emit different color light.

[0194] In one embodiment, the first to third light-emitting layers (BEML-1, BEML-2, BEML-3) of the first to third light-emitting stacks (ST1, ST2, ST3) can emit substantially the same first color light. For example, the first color light can be blue light, which is the source light described above. The wavelength range of the light emitted by the first to third light-emitting layers (BEML-1, BEML-2, BEML-3) can be about 420 nm or more and 480 nm or less.

[0195] The fourth light-emitting layer (GEML) of the fourth light-emitting stack (ST4) can emit a second color light different from the first color light. For example, the second color light can be green light. The wavelength range of the light emitted by the fourth light-emitting layer (GEML) can be about 520 nm or more and 600 nm or less.

[0196] The light emitting element (OLED) can emit light from the first electrode (AE) toward the second electrode (CE). In one embodiment of the light emitting element (OLED), each of the plurality of stacks (ST1, ST2, ST3, ST4) can include a hole transport region (HTR, MHTR1, MHTR2, MHTR3) and an electron transport region (METL1, METL2, METL3, ETR). The hole transport region (HTR, MHTR1, MHTR2, MHTR3) can transfer holes provided from the first electrode (AE) or the charge generation layer (CGL1, CGL2, CGL3) to the light emitting layer. The electron transport region (METL1, METL2, METL3, ETR) can transfer electrons provided from the second electrode (CE) or the charge generation layer (CGL1, CGL2, CGL3) to the light emitting layer.

[0197] An example of a light-emitting device (OLED) is a structure in which hole transport regions (HTR, MHTR1, MHTR2, MHTR3) are arranged below light-emitting layers (BEML-1, BEML-2, BEML-3, GEML) included in a plurality of stacks (ST1, ST2, ST3, ST4) based on the direction in which light is emitted, and electron transport regions (METL1, METL2, METL3, ETR) are arranged above light-emitting layers (BEML-1, BEML-2, BEML-3, GEML) included in a plurality of stacks (ST1, ST2, ST3, ST4). That is, the light emitting device (OLED) of one embodiment may have a forward device structure, but is not limited thereto, and may have an inverted device structure in which, based on the direction of emitting light, electron transport regions (METL1, METL2, METL3, ETR) are arranged below light emitting layers (BEML-1, BEML-2, BEML-3, GEML) included in a plurality of stacks (ST1, ST2, ST3, ST4) and hole transport regions (HTR, MHTR1, MHTR2, MHTR3) are arranged above light emitting layers (BEML-1, BEML-2, BEML-3, GEML) included in a plurality of stacks (ST1, ST2, ST3, ST4).

[0198] Each of the hole transport regions (HTR, MHTR1, MHTR2, MHTR3) may include a hole injection layer (HIL, MHIL1, MHIL2, MHIL3) and a hole transport layer (HTL, MHTL1, MHTL2, MHTL3) disposed on the hole injection layer (HIL, MHIL1, MHIL2, MHIL3). The hole transport layer (HTL, MHTL1, MHTL2, MHTL3) may contact a lower surface of the light emitting layer. However, the present invention is not limited thereto, and the hole transport regions (HTR, MHTR1, MHTR2, MHTR3) may further include a hole-side additional layer disposed on the hole transport layer (HTL, MHTL1, MHTL2, MHTL3). The hole-side additional layer may include at least one of a hole buffer layer, an emission auxiliary layer, and an electron blocking layer. The hole buffer layer may be a layer that increases light emission efficiency by compensating for the resonance distance according to the wavelength of light emitted from the light emitting layer. The electron blocking layer may be a layer that prevents electron injection from the electron transport region to the hole transport region.

[0199] The electron transport regions (METL1, METL2, METL3, ETR) may include an electron transport layer. The electron transport regions (METL1, METL2, METL3, ETR) may further include an electron injection layer disposed on the electron transport layer. For example, the fourth electron transport region (ETR) included in the fourth light-emitting stack (ST4) may further include a fourth electron injection layer (EIL) disposed on the fourth electron transport layer (ETL). The electron transport regions (METL1, METL2, METL3, ETR) may further include an electron-side additional layer disposed between the electron transport layer and the light-emitting layers. The electron-side additional layer may include at least one of an electron buffer layer and a hole blocking layer.

[0200] In a light-emitting device (OLED) according to one embodiment, the first electrode (AE) may be a reflective electrode. For example, the first electrode (AE) may include Ag, Mg, Cu, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, LiF / Ca, LiF / Al, Mo, Ti, W, In, Zn, Sn, or compounds or mixtures thereof (for example, a mixture of Ag and Mg) having high reflectivity. Alternatively, the first electrode (AE) may have a multi-layer structure including a reflective film formed of the above materials and a transparent conductive film formed of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium tin zinc oxide (ITZO), or the like. For example, the first electrode (AE) may have a two-layer structure of ITO / Ag and a three-layer structure of ITO / Ag / ITO, but is not limited thereto. In addition, the embodiment is not limited thereto, and the first electrode (AE) may include the above-described metal material, a combination of two or more metal materials selected from the above-described metal materials, or an oxide of the above-described metal materials. The thickness of the first electrode (AE) may be about 70 nm to about 1000 nm. For example, the thickness of the first electrode (AE) may be about 100 nm to about 300 nm.

[0201] In an OLED according to one embodiment, each of the hole transport regions (HTR, MHTR1, MHTR2, MHTR3) may have a multilayer structure having a single layer made of a single material, a single layer made of multiple different materials, or multiple layers made of multiple different materials.

[0202] Each of the hole transport regions (HTR, MHTR1, MHTR2, MHTR3) can be formed using various methods such as vacuum deposition, spin coating, casting, Langmuir-Blodgett (LB) method, inkjet printing, laser printing, and laser induced thermal imaging (LITI).

[0203] Each of the hole transport regions (HTR, MHTR1, MHTR2, MHTR3) contains a phthalocyanine compound such as copper phthalocyanine, DNTPD(N 1 ,N 1' -([1,1'-biphenyl]-4,4'-diyl)bis(N 1 -phenyl-N 4 ,N 4-di-m-tolylbenzene-1,4-diamine)), m-MTDATA(4,4',4"-[tris(3-methylphenyl)phenylamino] triphenylamine), TDATA(4,4'4"-Tris(N,N-diphenylamino)triphenylamine), 2-TNATA(4,4',4"-tris[N(2-naphthyl)-N-phenylamino]-triphenylamine), PEDOT / PSS(Poly(3,4-ethylenedioxythiophene) / Poly(4-styrenesulfonate)), PANI / DBSA(Polyaniline / Dodecylbenzenesulfonic acid), PANI / CSA(Polyaniline / Camphor sulfonicacid), PANI / PSS(Polyaniline / Poly(4-styrenesulfonate)), NPB(N,N'-di(naphthalene-l-yl)-N,N'-diphenyl-benzidine), 트리페닐아민을 포함하는 폴리에테르케톤(TPAPEK), 4-Isopropyl-4'-methyldiphenyliodonium [Tetrakis(pentafluorophenyl)borate], HATCN(dipyrazino[2,3-f: 2',3'-h] quinoxaline-2,3,6,7,10,11-hexacarbonitrile) 등을 포함할 수 있다.

[0204] Each of the hole transport regions (HTR, MHTR1, MHTR2, and MHTR3) is composed of carbazole derivatives such as N-phenylcarbazole and polyvinylcarbazole, fluorene derivatives, triphenylamine derivatives such as TPD (N,N'-bis(3-methylphenyl)-N,N'-diphenyl-[1,1'-biphenyl]-4,4'-diamine), TCTA (4,4',4"-tris(N-carbazolyl)triphenylamine), NPB (N,N'-di(naphthalene-l-yl)-N,N'-diphenyl-benzidine), TAPC (4,4'-Cyclohexylidene bis[N,N-bis(4-methylphenyl)benzenamine]), HMTPD (4,4'-Bis[N,N'-(3-tolyl)amino]-3,3'-dimethylbiphenyl), It may also contain mCP (1,3-Bis(N-carbazolyl)benzene).

[0205] Additionally, each of the hole transport regions (HTR, MHTR1, MHTR2, MHTR3) may include CzSi (9-(4-tert-Butylphenyl)-3,6-bis(triphenylsilyl)-9H-carbazole), CCP (9-phenyl-9H-3,9'-bicarbazole), or mDCP (1,3-bis(1,8-dimethyl-9H-carbazol-9-yl)benzene).

[0206] The hole transport region (HTR, MHTR1, MHTR2, MHTR3) may include the compounds of the above-described hole transport region in at least one of the hole injection layer (HIL, MHIL1, MHIL2, MHIL3), the hole transport layer (HTL, MHTL1, MHTL2, MHTL3), and the hole-side additional layer.

[0207] The thickness of each of the hole transport regions (HTR, MHTR1, MHTR2, MHTR3) may be from about 10 nm to about 1000 nm, for example, from about 10 nm to about 500 nm. The thickness of each of the hole injection layers (HIL, MHIL1, MHIL2, MHIL3) may be from about 5 nm to about 100 nm, for example. The thickness of each of the hole transport layers (HTL, MHTL1, MHTL2, MHTL3) may be from about 5 nm to about 100 nm. When the hole transport regions (HTR, MHTR1, MHTR2, MHTR3) include a hole-side additional layer, the thickness of the hole-side additional layer may be from about 1 nm to about 100 nm. When the hole transport regions (HTR, MHTR1, MHTR2, MHTR3) and the thickness of each layer included therein satisfy the ranges described above, satisfactory hole transport characteristics can be obtained without a substantial increase in driving voltage.

[0208] In addition to the aforementioned materials, each of the hole transport regions (HTR, MHTR1, MHTR2, and MHTR3) may further include a charge-generating material to enhance conductivity. The charge-generating material may be uniformly or non-uniformly dispersed within the hole transport regions (HTR, MHTR1, MHTR2, and MHTR3). The charge-generating material may be, for example, a p-type dopant. The p-type dopant may include, but is not limited to, at least one of a halogenated metal compound, a quinone derivative, a metal oxide, and a cyano group-containing compound. For example, p-type dopants may include, but are not limited to, halogenated metal compounds such as CuI and RbI, quinone derivatives such as TCNQ (Tetracyanoquinodimethane) and F4-TCNQ (2,3,5,6-tetrafluoro-7,7'8,8-tetracyanoquinodimethane), and metal oxides such as tungsten oxide and molybdenum oxide.

[0209] Each of the blue light-emitting layers (BEML-1, BEML-2, BEML-3) and the green light-emitting layer (GEML) may include a host material and a dopant material. Each of the blue light-emitting layers (BEML-1, BEML-2, BEML-3) and the green light-emitting layer (GEML) may include a material including a carbazole derivative moiety or an amine derivative moiety as a hole-transporting host material. Each of the blue light-emitting layers (BEML-1, BEML-2, BEML-3) and the green light-emitting layer (GEML) may include a material including a nitrogen-containing aromatic ring structure such as a pyridine derivative moiety, a pyridazine derivative moiety, a pyrimidine derivative moiety, a pyrazine derivative moiety, or a triazine derivative moiety as an electron-transporting host material.

[0210] Each of the blue light-emitting layers (BEML-1, BEML-2, BEML-3) and the green light-emitting layer (GEML) may include, as a host material, an anthracene derivative, a pyrene derivative, a fluoranthene derivative, a chrysene derivative, a dihydrobenzanthracene derivative, or a triphenylene derivative. In addition, each of the blue light-emitting layers (BEML-1, BEML-2, BEML-3) and the green light-emitting layer (GEML) may further include, as a host material, a general material known in the art. For example, each of the blue emitting layers (BEML-1, BEML-2, BEML-3) and the green emitting layer (GEML) may include at least one of DPEPO (Bis[2-(diphenylphosphino)phenyl] ether oxide), CBP (4,4'-Bis(carbazol-9-yl)biphenyl), mCP (1,3-Bis(carbazol-9-yl)benzene), PPF (2,8-Bis(diphenylphosphoryl)dibenzo[b,d]furan), TCTA (4,4',4''-Tris(carbazol-9-yl)-triphenylamine), and TPBi (1,3,5-tris(1-phenyl-1H-benzo[d]imidazole-2-yl)benzene) as a host material.However, it is not limited thereto, and for example, Alq3(tris(8-hydroxyquinolino)aluminum), PVK(poly(N-vinylcarbazole), ADN(9,10-di(naphthalene-2-yl)anthracene), TBADN(2-tert-butyl-9,10-di(naphth-2-yl)anthracene), DSA(distyrylarylene), CDBP(4,4'-bis(9-carbazolyl)-2,2'-dimethyl-biphenyl), MADN(2-Methyl-9,10-bis(naphthalen-2-yl)anthracene), CP1(Hexaphenyl cyclotriphosphazene), UGH2 (1,4-Bis(triphenylsilyl)benzene), DPSiO3(Hexaphenylcyclotrisiloxane), DPSiO4(Octaphenylcyclotetra siloxane), etc. can be used as the host material.

[0211] In one embodiment, the blue emitting layer (BEML-1, BEML-2, BEML-3) is a known fluorescent dopant material, such as a styryl derivative (e.g., 1, 4-bis[2-(3-N-ethylcarbazoryl)vinyl]benzene(BCzVB), 4-(di-p-tolylamino)-4'-[(di-p-tolylamino)styryl]stilbene(DPAVB), N-(4-((E)-2-(6-((E)-4-(diphenylamino)styryl)naphthalen-2-yl)vinyl)phenyl)-N-phenylbenzenamine(N-BDAVBi)), 4,4'-bis[2-(4-(N,N-diphenylamino)phenyl)vinyl]biphenyl(DPAVBi), perylene and its derivatives (e.g., 2, 5, 8, 11-Tetra-t-butylperylene (TBP)), pyrene and its derivatives (e.g., 1, 1-dipyrene, 1, 4-dipyrenylbenzene, 1, 4-Bis(N, N-Diphenylamino)pyrene), etc.

[0212] The green emitting layer (GEML) may include a known phosphorescent dopant material. For example, the phosphorescent dopant may be a metal complex including iridium (Ir), platinum (Pt), osmium (Os), gold (Au), titanium (Ti), zirconium (Zr), hafnium (Hf), europium (Eu), terbium (Tb), or thulium (Tm). Specifically, FIrpic (iridium(III) bis(4,6-difluorophenylpyridinato-N,C2')picolinate), Fir6 (Bis(2,4-difluorophenylpyridinato)-tetrakis(1-pyrazolyl)borate iridium(III)), or PtOEP (platinum octaethyl porphyrin) may be used as the phosphorescent dopant.

[0213] Each of the electron transport regions (METL1, METL2, METL3, ETR) may have a multilayer structure having a single layer made of a single material, a single layer made of multiple different materials, or multiple layers made of multiple different materials. For example, at least some of the electron transport regions (METL1, METL2, METL3, ETR) may include an electron transport layer (ETL4) and an electron injection layer (EIL4).

[0214] Each of the electron transport regions (METL1, METL2, METL3, ETR) can be formed using various methods such as vacuum deposition, spin coating, casting, Langmuir-Blodgett (LB) method, inkjet printing, laser printing, and laser induced thermal imaging (LITI).

[0215] The electron transport domains (METL1, METL2, METL3, ETR) may contain anthracene compounds. However, it is not limited thereto, and each of the electron transport domains (METL1, METL2, METL3, ETR) may be, for example, Alq3 (Tris(8-hydroxyquinolinato)aluminum), 1,3,5-tri[(3-pyridyl)-phen-3-yl]benzene, T2T (2,4,6-tris(3'-(pyridin-3-yl)biphenyl-3-yl)-1,3,5-triazine), 2-(4-(N-phenylbenzoimidazol-1-yl)phenyl)-9,10-dinaphthylanthracene, TPBi (1,3,5-Tri(1-phenyl-1H-benzo[d]imidazol-2-yl)benzene), BCP (2,9-Dimethyl-4,7-diphenyl-1,10-phenanthroline), Bphen (4,7-Diphenyl-1,10-phenanthroline), It may include TAZ(3-(4-Biphenylyl)-4-phenyl-5-tert-butylphenyl-1,2,4-triazole), NTAZ(4-(Naphthalen-1-yl)-3,5-diphenyl-4H-1,2,4-triazole), tBu-PBD(2-(4-Biphenylyl)-5-(4-tert-butylphenyl)-1,3,4-oxadiazole), BAlq(Bis(2-methyl-8-quinolinolato-N1,O8)-(1,1'-Biphenyl-4-olato)aluminum), Bebq2(berylliumbis(benzoquinolin-10-olate)), ADN(9,10-di(naphthalene-2-yl)anthracene), BmPyPhB(1,3-Bis[3,5-di(pyridin-3-yl)phenyl]benzene) and mixtures thereof.

[0216] In addition, each of the electron transport regions (METL1, METL2, METL3, ETR) may include a halogenated metal such as LiF, NaCl, CsF, RbCl, RbI, CuI, KI, a lanthanide metal such as Yb, and a co-deposition material of the halogenated metal and the lanthanide metal. For example, the electron transport regions (METL1, METL2, METL3, ETR) may include KI:Yb, RbI:Yb, etc. as the co-deposition material. The electron transport regions (METL1, METL2, METL3, ETR) may include two or more materials selected from Mg, Ag, Yb, and Al. For example, the electron transport regions (METL1, METL2, METL3, ETR) may include Mg and Yb.

[0217] Meanwhile, the electron transport regions (METL1, METL2, METL3, ETR) may use metal oxides such as Li2O, BaO, or Liq (8-hydroxyl-Lithium quinolate), but the examples are not limited thereto. Each of the electron transport regions (METL1, METL2, METL3, ETR) may also be formed of a material in which an electron transport material and an insulating organometal salt are mixed. The organometal salt may be a material having an energy band gap of approximately 4 eV or more. Specifically, for example, the organometal salt may include metal acetate, metal benzoate, metal acetoacetate, metal acetylacetonate, or metal stearate.

[0218] Each of the electron transport regions (METL1, METL2, METL3, ETR) may further include at least one of BCP (2,9-dimethyl-4,7-diphenyl-1,10-phenanthroline) and Bphen (4,7-diphenyl-1,10-phenanthroline) in addition to the aforementioned materials, but the embodiments are not limited thereto.

[0219] The electron transport region (METL1, METL2, METL3, ETR) may include the compounds of the electron transport region described above in the electron injection layer or the electron transport layer. When the electron transport region (METL1, METL2, METL3, ETR) includes an electron-side additional layer, the electron-side additional layer may include the above-described material. In one embodiment, the electron injection layer (EIL4) may be composed of two or more materials selected from Mg, Ag, Yb, and Al. The electron injection layer (EIL4) may be composed of a mixture of Mg and Yb, for example.

[0220] The thickness of each of the electron transport regions (METL1, METL2, METL3, ETR) may be, for example, about 10 nm to about 150 nm. The thickness of the electron transport layer may be, for example, about 0.1 nm to about 100 nm, for example, about 0.3 nm to about 50 nm. When the thickness of the electron transport layer satisfies the range described above, satisfactory electron transport characteristics can be obtained without a substantial increase in driving voltage.

[0221] The second electrode (CE) is provided on a plurality of light-emitting stacks (ST1, ST2, ST3, ST4). The second electrode (CE) may be a common electrode. The second electrode (CE) may be a cathode or an anode, but the embodiment is not limited thereto. For example, when the first electrode (AE) is an anode, the second electrode (CE) may be a cathode, and when the first electrode (AE) is a cathode, the second electrode (CE) may be an anode.

[0222] The second electrode (CE) may be a semi-transmissive electrode or a transmissive electrode. When the second electrode (CE) is a transmissive electrode, the second electrode (CE) may be made of a transparent metal oxide, for example, ITO (indium tin oxide), IZO (indium zinc oxide), ZnO (zinc oxide), ITZO (indium tin zinc oxide), etc.

[0223] When the second electrode (CE) is a semi-transmissive electrode or a reflective electrode, the second electrode (CE) may include Ag, Mg, Cu, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, LiF / Ca, LiF / Al, Mo, Ti, Yb, W, In, Zn, Sn, or a compound or mixture containing these (for example, AgMg, AgYb, or MgAg). Alternatively, the second electrode (CE) may have a multi-layer structure including a reflective film or a semi-transmissive film formed of the above material and a transparent conductive film formed of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium tin zinc oxide (ITZO), or the like. For example, the second electrode (CE) may include the above-described metal material, a combination of two or more metal materials selected from the above-described metal materials, or an oxide of the above-described metal materials.

[0224] Although not shown, the second electrode (CE) may be connected to an auxiliary electrode. When the second electrode (CE) is connected to the auxiliary electrode, the resistance of the second electrode (CE) may be reduced.

[0225] Meanwhile, a capping layer (CPL) may be further disposed on the second electrode (CE) of the light-emitting device (OLED) of one embodiment. The capping layer (CPL) may include a multilayer or a single layer.

[0226] In one embodiment, the capping layer (CPL) may be an organic layer or an inorganic layer. For example, when the capping layer (CPL) includes an inorganic material, the inorganic material may be an alkali metal compound such as LiF, an alkaline earth metal compound such as MgF2, SiON, SiN. X , SiOy, etc.

[0227] For example, when the capping layer (CPL) includes an organic material, the organic material may include α-NPD, NPB, TPD, m-MTDATA, Alq3, CuPc, TPD15 (N4,N4,N4',N4'-tetra (biphenyl-4-yl) biphenyl-4,4'-diamine), TCTA (4,4',4"- Tris (carbazol sol-9-yl) triphenylamine), etc., or may include an acrylate such as an epoxy resin or a methacrylate.

[0228] Meanwhile, the refractive index of the capping layer (CPL) may be 1.6 or greater. Specifically, the refractive index of the capping layer (CPL) may be 1.6 or greater for light in the wavelength range of 550 nm or greater and 660 nm or less.

[0229] Referring again to FIG. 6, in the light-emitting device (OLED) of one embodiment, the functional layer (FNL) may be disposed between the first electrode (AE) and the second electrode (CE). Referring to FIG. 6, the functional layer (FNL) may be disposed as a common layer so as to overlap the entirety of the light-emitting areas (EA1, EA2, EA3) and the pixel defining layer (PDL) that separates the light-emitting areas (EA1, EA2, EA3). However, the embodiment is not limited thereto, and the functional layer (FNL) may be patterned and provided so as to be separately disposed corresponding to each of the light-emitting areas (EA1, EA2, EA3). Alternatively, some of the plurality of organic layers included in the functional layer (FNL) may be patterned so as to be separately disposed corresponding to each of the light-emitting areas (EA1, EA2, EA3), and the remaining some may be disposed as a common layer so as to overlap the entirety of the light-emitting areas (EA1, EA2, EA3) and the pixel defining layer (PDL).

[0230] The second electrode (CE) is provided on the functional layer (FNL). The second electrode (CE) may be a common electrode. The second electrode (CE) may be a cathode or an anode, but the embodiment is not limited thereto. For example, when the first electrode (AE) is an anode, the second electrode (CE) may be a cathode, and when the first electrode (AE) is a cathode, the second electrode (CE) may be an anode. The second electrode (CE) may be a transmissive electrode, a semi-transmissive electrode, or a reflective electrode.

[0231] The encapsulation layer (TFE) may be disposed on the light-emitting element (OLED). For example, in one embodiment, the encapsulation layer (TFE) may be disposed on the second electrode (CE). In addition, when the light-emitting element (OLED) includes a capping layer (not shown), the encapsulation layer (TFE) may be disposed on the capping layer (not shown). As described above, the encapsulation layer (TFE) may include at least one organic film and at least one inorganic film, and the inorganic films and the organic films may be disposed alternately.

[0232] A display panel (DP) of one embodiment may include an optical layer (OSL) disposed on a display element layer (DP-OLED). The optical layer (OSL) may include a light control layer (CCL), a color filter layer (CFL), and a base layer (BL).

[0233] The light control layer (CCL) may include a light converter. The light converter may be a quantum dot or a phosphor, etc. The light converter may convert the wavelength of the light provided and emit it. That is, the light control layer (CCL) may be a layer including quantum dots at least in a portion or a layer including a phosphor.

[0234] The light control layer (CCL) may include a plurality of light control patterns (CCP-R, CCP-G, CCP-B). The light control patterns (CCP-R, CCP-G, CCP-B) may be spaced apart from each other. The light control patterns (CCP-R, CCP-G, CCP-B) may be arranged to be spaced apart from each other by a bank (BMP). The light control patterns (CCP-R, CCP-G, CCP-B) may be arranged within bank openings (BOH1, BOH2, BOH3) defined in the bank (BMP). However, the embodiment is not limited thereto. In Fig. 6, the bank (BMP) is illustrated as having a rectangular shape in cross-section and not overlapping with the light control patterns (CCP-R, CCP-G, CCP-B), but some edges of the light control patterns (CCP-R, CCP-G, CCP-B) may overlap at least partly with the bank (BMP). For example, the edge of the third light control pattern (CCP-B) may be arranged to overlap with the bank (BMP) in a plane. The bank (BMP) may have a trapezoidal shape in cross-section. The bank (BMP) may have a shape whose cross-sectional width increases as it approaches the display element layer (DP-OLED).

[0235] The light control pattern (CCP-R, CCP-G, CCP-B) may be a portion that converts the wavelength of light provided from the display element layer (DP-OLED) or transmits the provided light.

[0236] The light control layer (CCL) may include a first light control pattern (CCP-R) that provides red light as a first light, a second light control pattern (CCP-G) that provides green light as a second light, and a third light control pattern (CCP-B) that provides blue light as a third light. The light control layer (CCL) may include a first light control pattern (CCP-R) that converts source light provided from a light-emitting element (OLED) into first light, a second light control pattern (CCP-G) that converts the source light into second light, and a third light control pattern (CCP-B) that transmits the source light. At least some of the light control patterns (CCP-R, CCP-G, CCP-B) may include quantum dots that convert the source light into light of a specific wavelength.

[0237] At least some of the light control patterns (CCP-R, CCP-G, CCP-B) may be formed by an inkjet process. Alternatively, some of the light control patterns (CCP-R, CCP-G, CCP-B) may be formed by a photoresist process.

[0238] The light control layer (CCL) may further include scatterers. The first light control pattern (CCP-R) may include first quantum dots and scatterers, the second light control pattern (CCP-G) may include second quantum dots and scatterers, and the third light control pattern (CCP-B) may not include quantum dots but include scatterers. Each of the first light control pattern (CCP-R), the second light control pattern (CCP-G), and the third light control pattern (CCP-B) may further include a base resin that disperses quantum dots and scatterers. Meanwhile, since the third light control pattern (CCP-B) is formed through a photoresist process as described below, it may include a photosensitive resin.

[0239] The light control layer (CCL) may include a first barrier layer (CAP1) disposed on one surface of the first light control pattern (CCP-R). The light control layer (CCL) may include a first barrier layer (CAP1) spaced apart from the display element layer (DP-OLED) with the first light control pattern (CCP-R) interposed therebetween, and a second barrier layer (CAP2) adjacent to the display element layer (DP-OLED).

[0240] In a display panel (DP), an optical layer (OSL) includes a color filter layer (CFL) disposed on a light control layer (CCL). The color filter layer (CFL) may include color filters (CF1, CF2, CF3). The color filter layer (CFL) may include a first color filter (CF1) that transmits first light, a second color filter (CF2) that transmits second light, and a third color filter (CF3) that transmits source light. In one embodiment, the first color filter (CF1) may be a red filter, the second color filter (CF2) may be a green filter, and the third color filter (CF3) may be a blue filter.

[0241] Each of the color filters (CF1, CF2, CF3) includes a polymer photosensitive resin and a colorant. The first color filter (CF1) may include a red colorant, the second color filter (CF2) may include a green colorant, and the third color filter (CF3) may include a blue colorant. The first color filter (CF1) may include a red pigment or a red dye, the second color filter (CF2) may include a green pigment or a green dye, and the third color filter (CF3) may include a blue pigment or a blue dye.

[0242] Each of the first to third color filters (CF1, CF2, CF3) may be arranged to correspond to each of the first pixel area (PXA1), the second pixel area (PXA2), and the third pixel area (PXA3). In addition, each of the first to third color filters (CF1, CF2, CF3) may be arranged to correspond to each of the first to third light control patterns (CCP-R, CCP-G, CCP-B).

[0243] In addition, a plurality of color filters (CF1, CF2, CF3) that transmit different light may be overlapped and arranged in correspondence to the non-pixel area (NPXA) arranged between the pixel areas (PXA1, PXA2, PXA3). A plurality of color filters (CF1, CF2, CF3) may be overlapped and arranged in the third direction (DR3), which is the thickness direction, to distinguish the boundary between adjacent pixel areas (PXA1, PXA2, PXA3). Meanwhile, unlike the drawing, the color filter layer (CFL) may include a light-shielding portion (not shown) that distinguishes the boundary between adjacent color filters (CF1, CF2, CF3). The light-shielding portion (not shown) may be formed by including a blue filter, or an organic light-shielding material including a black pigment or a black dye, or an inorganic light-shielding material.

[0244] The optical layer (OSL) may include a filler layer (FML) disposed between the light control layer (CCL) and the color filter layer (CFL). The filler layer (FML) may be disposed between the light control patterns (CCP-R, CCP-G, CCP-B) and the color filters (CF1, CF2, CF3). The filler layer (FML) may be disposed on the light control layer (CCL) to block the light control patterns (CCP-R, CCP-G, CCP-B) from being exposed to moisture / oxygen. In addition, the filler layer (FML) may be disposed between the light control patterns (CCP-R, CCP-G, CCP-B) and the color filters (CF1, CF2, CF3) to increase light extraction efficiency or may function as an optical functional layer to prevent reflected light from entering the light control layer (CCL). The fill layer (FML) may be a layer with a lower refractive index compared to other adjacent layers.

[0245] In one embodiment, the optical layer (OSL) may further include a base layer (BL) disposed on the color filter layer (CFL). The base layer (BL) may be a member that provides a base surface on which the color filter layer (CFL) and the light control layer (CCL) are disposed. The base layer (BL) may be a glass substrate, a metal substrate, a plastic substrate, or the like. However, the embodiment is not limited thereto, and the base layer (BL) may be an inorganic layer, an organic layer, or a composite material layer. In addition, unlike the embodiment illustrated, the base layer (BL) may be omitted in one embodiment.

[0246] Meanwhile, the optical layer (OSL) may further include a filling pattern (FLP) overlapping the transmission area (TA). The portion of the optical layer (OSL) overlapping the transmission area (TA) does not overlap with the configurations of light control patterns (CCP-R, CCP-G, CCP-B), banks (BMP), color filters (CF1, CF2, CF3), etc., and an optically transparent filling pattern (FLP) may be arranged. The filling pattern (FLP) may be arranged to overlap the transmission area (TA) and may function as an optical functional layer, such as increasing light extraction efficiency or preventing reflected light from being incident downward. The filling pattern (FLP) may be a pattern having a lower refractive index compared to other adjacent layers.

[0247] Meanwhile, in order to improve the transmittance of the transmission area (TA) in the display panel (DP), at least some of the insulating layers arranged in the transmission area (TA) may be removed.

[0248] According to the present embodiment, the base substrate (BS), the first insulating layer (10), the second insulating layer (20), and the third insulating layer (30) may be arranged in the transmission area (TA). A transmission opening (T-OP) overlapping the transmission area (TA) may be defined in the fourth insulating layer (40), the fifth insulating layer (50), the pixel defining layer (PDL), and the light emitting element (OLED). The transmission opening (T-OP) may be defined by a side surface formed by penetrating a portion of each of the fourth insulating layer (40), the fifth insulating layer (50), the pixel defining layer (PDL), and the light emitting element (OLED) overlapping the transmission area (TA). The transmission opening (T-OP) may be formed by removing a portion of each of the fourth insulating layer (40), the fifth insulating layer (50), the pixel defining layer (PDL), and the light emitting element (OLED) by a dry etching process. Meanwhile, at least a part of a functional layer (FNL) included in a light-emitting element (OLED) may be removed through an etching process. As described above, the light-emitting element (OLED) includes a plurality of light-emitting stacks (ST1, ST2, ST3, ST4), each of which includes a light-emitting layer (BEML-1, BEML-2, BEML-3, GEML), and at least a part of the plurality of light-emitting stacks (ST1, ST2, ST3, ST4) may be removed in a transmission area (TA) corresponding to a transmission opening (T-OP). Accordingly, at least a part of the light-emitting layers (BEML-1, BEML-2, BEML-3, GEML) included in each of the plurality of light-emitting stacks (ST1, ST2, ST3, ST4) may not overlap the transmission area (TA).

[0249] In this embodiment, the upper surface of the third insulating layer (30) can be exposed from the fourth insulating layer (40), the fifth insulating layer (50), the pixel defining layer (PDL), and the light emitting element (OLED) through the transmission opening (T-OP). An inorganic layer, etc. included in the encapsulating layer (TFE) can be disposed on the upper surface of the third insulating layer (30).

[0250] The description of the above-described transmission area (TA) can be commonly applied to the unit areas (PU) described in Fig. 3a. Accordingly, a plurality of openings arranged spaced apart from each other along the first direction (DR1) and the second direction (DR2) can be defined in the fourth insulating layer (40), the fifth insulating layer (50), the pixel defining layer (PDL), and the light-emitting element (OLED) on a plane. The openings can be arranged along the first direction (DR1) and the second direction (DR2) on a plane.

[0251] According to the present invention, a fourth insulating layer (40) including silicon nitride may not be disposed in a transparent area (TA) of a display panel (DP) included in a transparent display device. Accordingly, the transmittance of the transparent area (TA) may be improved.

[0252] Meanwhile, in FIG. 6, the transmission opening (T-OP) corresponding to the transmission area (TA) is illustrated as being defined in each of the fourth insulating layer (40), the fifth insulating layer (50), the pixel defining layer (PDL), and the light emitting element (OLED), but this is not limited thereto, and the transmission opening (T-OP) may be additionally formed in another insulating layer included in the circuit element layer (DP-CL). Alternatively, the transmission opening (T-OP) may not be defined in some of the fourth insulating layer (40), the fifth insulating layer (50), the pixel defining layer (PDL), and the light emitting element (OLED). For example, some optically transparent layers of the functional layer (FNL) included in the light emitting element (OLED) may not be removed in a portion corresponding to the transmission opening (T-OP).

[0253] Figure 8 is a plan view of an input sensor (IS) according to one embodiment of the present invention.

[0254] As illustrated in Fig. 8, the input sensor (IS) includes a detection area (IS-DA) and a non-detection area (IS-NDA) adjacent to the detection area (IS-DA). The detection area (IS-DA) and the non-detection area (IS-NDA) correspond to the display area (DA) and the non-display area (NDA) illustrated in Fig. 3a, respectively.

[0255] The input sensor (IS) includes a plurality of conductive patterns as described above. The plurality of conductive patterns include first electrodes (SE1, or first sensing electrodes), second electrodes (SE2, or second sensing electrodes), first signal lines (SL1, or first sensor signal lines), and second signal lines (SL2, or second sensor signal lines).

[0256] First sensing electrodes (SE1) and second sensing electrodes (SE2) that are insulated from each other and intersect each other are arranged in a sensing area (IS-DA). First signal lines (SL1) connected to the first sensing electrodes (SE1) and second signal lines (SL2) electrically connected to the second sensing electrodes (SE2) are arranged in a non-sensing area (IS-NDA). One of the first signal lines (SL1) and the second signal lines (SL2) transmits a driving signal for detecting an external input from an external circuit to the corresponding electrodes, and the other one outputs a sensing signal. A change in mutual capacitance between the first sensing electrodes (SE1) and the second sensing electrodes (SE2) is measured based on the sensing signal. The input sensor illustrated in this embodiment may refer to an input sensor of a "mutual capacitance type."

[0257] The first sensing electrodes (SE1) may be provided in multiple rows. The first sensing electrodes (SE1) may include a first row sensing electrode (E1-1), a second row sensing electrode (E1-2), a third row sensing electrode (E1-3), and a fourth row sensing electrode (E1-4). Unlike as illustrated in FIG. 8, the first sensing electrodes (SE1) may include two or three row sensing electrodes, or may include five or more row sensing electrodes.

[0258] The second sensing electrodes (SE2) may be provided in multiple rows. The second sensing electrodes (SE2) may include a first thermal sensing electrode (E2-1), a second thermal sensing electrode (E2-2), a third thermal sensing electrode (E2-3), a fourth thermal sensing electrode (E2-4), a fifth thermal sensing electrode (E2-5), a sixth thermal sensing electrode (E2-6), and a seventh thermal sensing electrode (E2-7). Unlike as illustrated in FIG. 8, the second sensing electrodes (SE2) may include six or fewer thermal sensing electrodes, or may include eight or more thermal sensing electrodes.

[0259] The second sensing electrodes (SE2) may include second sensing patterns (SP2) and connection patterns (CP2). The second sensing patterns (SP2) may have a larger area than the connection patterns (CP2) and may have a diamond shape. Each of the connection patterns (CP2) is arranged between two adjacent second sensing patterns (SP2) among the second sensing patterns (SP2). The length of the connection patterns (CP2) may be relatively shorter than that of the second sensing patterns (SP2).

[0260] Each of the first sensing electrodes (SE1) may include first sensing patterns (SP1) and bridge patterns (CP1). Two adjacent first sensing patterns (SP1) may be connected by two bridge patterns (CP1), but the number of bridge patterns connecting each of the two adjacent first sensing patterns (SP1) is not limited.

[0261] In the present embodiment, each of the first signal lines (SL1) and the second signal lines (SL2) of FIG. 8 may be formed from the first conductive layer (IS-CL1) of FIG. 5. However, the present invention is not limited thereto, and each of the first signal lines (SL1) and the second signal lines (SL2) may also be formed from the second conductive layer (IS-CL2). Each of the first signal lines (SL1) and the second signal lines (SL2) may have a dual wiring structure including both a line formed from the first conductive layer (IS-CL1) and a line formed from the second conductive layer (IS-CL2).

[0262] The second sensing electrodes (SE2) and the first sensing patterns (SP1) may be arranged on the same layer. The bridge patterns (CP1) may be arranged on a different layer from the second sensing electrodes (SE2) and the first sensing patterns (SP1). In the input sensor (IS) of one embodiment, the bridge patterns (CP1) may be included in the first conductive layer (IS-CL1) described above in FIG. 5 and may be arranged on the first insulating layer (IS-IL1), and the second electrodes (SE2) and the first sensing patterns (SP1) may be included in the second conductive layer (IS-CL2) and may be arranged on the second insulating layer (IS-IL2). Alternatively, the bridge patterns (CP1) may be included in the second conductive layer (IS-CL2) and disposed on the second insulating layer (IS-IL2), and the second electrodes (SE2) and the first sensing patterns (SP1) may be included in the first conductive layer (IS-CL1) and disposed on the first insulating layer (IS-IL1).

[0263] As illustrated in FIG. 8, each of the first sensing electrodes (SE1) and the second sensing electrodes (SE2) may have a mesh shape in which a plurality of openings are defined. The plurality of openings may overlap, for example, corresponding light-emitting areas and transmission areas (TA) among the plurality of pixel areas (PXA) of FIG. 3B. The second sensing electrodes (SE2) intersect and insulate from the first sensing electrodes (SE1). The mesh shape of each of the first sensing electrodes (SE1) and the second sensing electrodes (SE2) will be described later in the description of FIG. 9A and the like.

[0264] Either of the first sensing electrodes (SE1) and the second sensing electrodes (SE2) may have an integral shape. In the present embodiment, the second sensing electrodes (SE2) having an integral shape are exemplified.

[0265] FIGS. 9A and 9B are enlarged plan views of a portion of an input sensor according to an embodiment of the present invention, respectively. FIGS. 9C and 9D are enlarged cross-sectional views of a portion of an input sensor according to an embodiment of the present invention, respectively. FIGS. 9A and 9B are enlarged views of a portion corresponding to area AA illustrated in FIG. 8, respectively. FIG. 9C illustrates a cross-section corresponding to line III-III' illustrated in FIG. 9A. FIG. 9D illustrates a cross-section corresponding to line IV-IV' illustrated in FIG. 9B.

[0266] Referring to FIGS. 9A and 9B together, a plurality of pixel apertures (POP) and transmission apertures (TOP) can be defined in each of the first detection patterns (SP1) and the second detection patterns (SP2).

[0267] The plurality of pixel apertures (POP) may include a first pixel aperture (POP1), a second pixel aperture (POP2), and a third pixel aperture (POP3) spaced apart from each other along a first direction (DR1). The transmission aperture (TOP) may be spaced apart from each of the first pixel aperture (POP1), the second pixel aperture (POP2), and the third pixel aperture (POP3) along the second direction (DR2).

[0268] Meanwhile, the plurality of pixel apertures (POP) may be apertures corresponding to the aforementioned pixel areas (PXAs). The transmission aperture (TOP) may be an aperture corresponding to the aforementioned transmission area (TA). In the present embodiment, a first pixel area (PXA1) may be arranged inside a first pixel opening (POP1), a second pixel area (PXA2) may be arranged inside a second pixel opening (POP2), and a third pixel area (PXA3) may be arranged inside a third pixel opening (POP3).

[0269] Each of the first sensing patterns (SP1) and the second sensing patterns (SP2) may include a plurality of mesh lines (MSL) defining a plurality of pixel openings (POP) and a plurality of transmission openings (TOP). The plurality of mesh lines (MSL) may include a plurality of mesh elements extending in each of the first direction (DR1) and the second direction (DR2). Meanwhile, the widths of the plurality of mesh elements included in the plurality of mesh lines (MSL) may be the same. However, the present invention is not limited thereto, and any one of the mesh elements included in the mesh lines (MSL) may be thicker than the other mesh elements. For example, a mesh element extending in one direction among the mesh lines (MSL) may have a thicker width than a mesh element extending in the other direction. The width of the mesh lines (MSL) may be, for example, 15 micrometers or more and 25 micrometers or less.

[0270] Each of the plurality of pixel apertures (POP) may have a planar area larger than the area of ​​the overlapping light-emitting areas. For example, the planar area of ​​the first pixel aperture (POP1) may be larger than the area of ​​the first pixel area (PXA1), the planar area of ​​the second pixel aperture (POP2) may be larger than the area of ​​the second pixel area (PXA2), and the planar area of ​​the third pixel aperture (POP3) may be larger than the area of ​​the third pixel area (PXA3). Therefore, the plurality of mesh lines (MSL) defining the plurality of pixel apertures (POP) may not reduce the light emission efficiency of light emitted through the pixel areas.

[0271] A top-of-the-panel (TOP) can have a planar area larger than that of the overlapping transmissive area (TA). The planar area of ​​the top-of-the-panel (TOP) can be larger than that of the transmissive area (TA). Therefore, the plurality of mesh lines (MSL) defining the top-of-the-panel (TOP) may not reduce the transmittance of the display device.

[0272] The arrangement and shape of the mesh lines (MSL) can be varied depending on the arrangement and planar area of ​​the plurality of pixel apertures (POP) and transmission apertures (TOP) defined in the mesh lines (MSL). In addition, the arrangement and planar area of ​​the plurality of pixel apertures (POP) and transmission apertures (TOP) can be varied depending on the arrangement and area of ​​the corresponding pixel areas (PXA) and transmission areas (TA).

[0273] Meanwhile, for convenience of explanation, a plurality of mesh lines (MSL) defining a plurality of pixel apertures (POP) and transmission apertures (TOP) may be connected to each other to form an integral shape. That is, a plurality of mesh lines (MSL) may be formed by patterning a plurality of pixel apertures (POP) and transmission apertures (TOP) on an integral conductive layer.

[0274] Referring to FIGS. 8 and 9A together, the input sensor (IS) includes a plurality of conductive patterns, and the plurality of conductive patterns include first sensing electrodes (SE1) and second sensing electrodes (SE2). The first sensing electrodes (SE1) include first sensing patterns (SP1) and bridge patterns (CP1). The second sensing electrodes (SE2) may include second sensing patterns (SP2) and connection patterns (CP2). FIG. 9A illustrates an enlarged planar shape of two first sensing patterns (SP1) included in the first sensing electrodes (SE1) and a bridge pattern (CP1) connecting them, and two second sensing patterns (SP2) included in the second sensing electrodes (SE2) and a connection pattern (CP2) connecting them.

[0275] In an input sensor (IS) of one embodiment, a boundary (CTL) may be defined between a first sensing pattern (SP1) and a second sensing electrode (SE2). The boundary (CTL) may be a portion from which at least some of the mesh lines (MSL) are removed. The boundary (CTL) may be provided to insulate the first sensing pattern (SP1) and the second sensing electrode (SE2) from each other. The boundary (CTL) may be provided to insulate the first sensing pattern (SP1) and the second sensing pattern (SP2) and to insulate the first sensing pattern (SP1) and the connection pattern (CP2).

[0276] Each of the second sensing patterns (SP2) and the connection pattern (CP2) included in the second sensing electrode (SE2) includes mesh lines (MSL) and may have an integral shape. The connection pattern (CP2) is arranged between two adjacent second sensing patterns (SP2) and may have an integral shape with each of the two second sensing patterns (SP2). Each of the plurality of second sensing patterns (SP2) and the connection pattern (CP2) illustrated in FIG. 9A includes mesh lines (MSL), and two adjacent second sensing patterns (SP2) and the connection pattern (CP2) among the plurality of second sensing patterns (SP2) may have an integral shape.

[0277] The bridge pattern (CP1) can electrically connect two adjacent first sensing patterns (SP1). The bridge pattern (CP1) overlaps the lower contact hole on a plane and can electrically connect two adjacent first sensing patterns (SP1) through the first contact hole (CH1).

[0278] The plurality of conductive patterns included in the input sensor (IS) further include at least one transparent electrode (TPE). The plurality of conductive patterns may include a plurality of transparent electrodes (TPE) spaced apart from each other on a plane. The transparent electrodes (TPE) are provided in multiple numbers and may be arranged throughout the detection area (IS-DA).

[0279] A transparent electrode (TPE) comprises an optically transparent material. The transparent electrode (TPE) may comprise, for example, a transparent conductive oxide (TCO). The transparent electrode (TPE) may comprise a transparent conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnOx), or indium zinc tin oxide (IZTO). For example, the transparent electrode (TPE) may comprise indium tin oxide (ITO).

[0280] The transparent electrode (TPE) may overlap at least a portion of the first sensing electrode (SE1) and the second sensing electrode (SE2) on a plane. The transparent electrode (TPE) may overlap at least a portion of the first sensing pattern (SP1), the second sensing pattern (SP2), and the connection pattern (CP2) on a plane. The transparent electrode (TPE) may be electrically connected to a portion of the first sensing pattern (SP1), the second sensing pattern (SP2), and the connection pattern (CP2) that overlap on a plane.

[0281] A transparent electrode (TPE) overlaps at least a portion of a transmission aperture (TOP) in a plane. The transparent electrode (TPE) may overlap at least a portion of a plurality of pixel apertures (POP) in a plane. The transparent electrode (TPE) overlaps the transmission aperture (TOP) and may overlap at least a portion of corresponding transmission areas (TA). The transmission areas (TA) may include a first transmission area (TA-1) that overlaps the transparent electrode (TPE) in a plane and a second transmission area (TA-2) that does not overlap the transparent electrode (TPE) in a plane. The transparent electrode (TPE) overlaps the pixel aperture (POP) and may overlap at least a portion of corresponding pixel areas (PXA).

[0282] Referring to FIGS. 9A and 9C, the transparent electrode (TPE) is disposed on a different layer from the first sensing electrode (SE1) and the second sensing electrode (SE2). As in one embodiment, the transparent electrode (TPE) may be disposed above the first sensing electrode (SE1) and the second sensing electrode (SE2). As illustrated in FIG. 9C, the transparent electrode (TPE) may be disposed on the third insulating layer (IS-IL3). The transparent electrode (TPE) may be spaced apart from the first sensing pattern (SP1), the second sensing pattern (SP2), and the connection pattern (CP2) with the third insulating layer (IS-IL3) interposed therebetween. The transparent electrode (TPE) can be electrically connected to a corresponding portion of the first sensing pattern (SP1), the second sensing pattern (SP2), and the connection pattern (CP2) disposed under the third insulating layer (IS-IL3) through an upper contact hole (CH-U) defined in the third insulating layer (IS-IL3). Meanwhile, in the present specification, the third insulating layer (IS-IL3) disposed between the transparent electrode (TPE) and the first sensing electrode (SE1) and the second sensing electrode (SE2) can be described as a “cover insulating layer.”

[0283] An input sensor (IS) of one embodiment includes a transparent electrode (TPE) electrically connected to each of the first sensing electrode (SE1) and the second sensing electrode (SE2) and overlapping at least a portion of the transmission area (TA) and the pixel area (PXA), thereby having high sensing sensitivity while maintaining high transmittance.

[0284] Specifically, a display device having a planar area of ​​the transmission area (TA) of 60% or more based on the total area of ​​the transmission area (TA) and pixel areas (PXA) has high transmittance and can be used as a transparent display device, but may have low sensing sensitivity due to low density of mesh lines (MSL). However, an input sensor and a display device including the same of one embodiment include a transparent electrode (TPE) electrically connected to the mesh lines (MSL) of each of the first sensing electrode (SE1) and the second sensing electrode (SE2), thereby increasing the area and density of a conductive pattern for external input sensing, thereby improving sensing sensitivity. Therefore, the sensing performance of a display device including the input sensor can be improved.

[0285] Referring to FIGS. 9b and 9d, the plurality of conductive patterns included in the input sensor (IS) may further include at least one dummy pattern (DPE). The plurality of conductive patterns may include a plurality of dummy patterns (DPE) spaced apart from each other on a plane. The dummy patterns (DPE) are provided in plurality and may be arranged throughout the detection area (IS-DA). The dummy patterns (DPE) may be spaced apart from the transparent electrodes (TPE) on a plane.

[0286] The dummy pattern (DPE) includes an optically transparent material. The dummy pattern (DPE) may include the same material as the transparent electrode (TPE). The dummy pattern (DPE) may include, for example, a transparent conductive oxide (TCO). The dummy pattern (DPE) may include a transparent conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnOx), or indium zinc tin oxide (IZTO). For example, the dummy pattern (DPE) may include indium tin oxide (ITO).

[0287] The dummy pattern (DPE) may overlap at least a portion of the first sensing electrode (SE1) and the second sensing electrode (SE2) on a plane. The dummy pattern (DPE) may overlap at least a portion of the first sensing pattern (SP1), the second sensing pattern (SP2), and the connection pattern (CP2) on a plane. The dummy pattern (DPE) may be an isolated floating electrode that is not electrically connected to other sensing electrodes (SE1, SE2) and transparent electrodes (TPE).

[0288] The dummy pattern (DPE) can overlap at least a portion of the transmission aperture (TOP) on a plane. The dummy pattern (DPE) can overlap at least a portion of a plurality of pixel apertures (POP) on a plane. The dummy pattern (DPE) can overlap the transmission aperture (TOP) and overlap at least a portion of the corresponding transmission areas (TA). The dummy pattern (DPE) can overlap the pixel aperture (POP) and overlap at least a portion of the corresponding pixel areas (PXA).

[0289] The dummy pattern (DPE) is disposed on a different layer from the first sensing electrode (SE1) and the second sensing electrode (SE2). As in one embodiment, the dummy pattern (DPE) may be disposed above the first sensing electrode (SE1) and the second sensing electrode (SE2). The dummy pattern (DPE) may be disposed on the same layer as the transparent electrode (TPE). The dummy pattern (DPE) may be disposed on the same layer as the transparent electrode (TPE) and may be formed through the same process. The dummy pattern (DPE) may include the same material as the transparent electrode (TPE). As illustrated in FIG. 9d, the dummy pattern (DPE) may be disposed on the third insulating layer (IS-IL3). The dummy pattern (DPE) may be spaced apart from the first sensing pattern (SP1), the second sensing pattern (SP2), and the connection pattern (CP2) with the third insulating layer (IS-IL3) interposed therebetween. In one embodiment, the transparent electrode (TPE) is electrically connected to a corresponding part of the first sensing pattern (SP1), the second sensing pattern (SP2), and the connection pattern (CP2) disposed under the third insulating layer (IS-IL3) through an upper contact hole (CH-U) defined in the third insulating layer (IS-IL3), but the dummy pattern (DPE) may not have a separate contact hole defined thereunder and may be insulated from the first sensing pattern (SP1), the second sensing pattern (SP2), and the connection pattern (CP2) disposed thereunder.

[0290] An input sensor of one embodiment further includes a dummy pattern (DPE) that is spaced apart from and floating on a plane from transparent electrodes (TPEs), thereby reducing the difference in transmittance between a portion where a transparent electrode (TPE) is disposed and a portion where a transparent electrode (TPE) is not disposed. Accordingly, the visibility of a display device including an input sensor can be improved.

[0291] FIGS. 10A to 10C are enlarged plan views of a portion of a display area of ​​a display device according to an embodiment of the present invention. FIGS. 10A to 10C illustrate in more detail the overlapping relationship between the aforementioned pixel areas (PXA), the transmission area (TA), and the transparent electrode (TPE).

[0292] Referring to FIG. 10A, the arrangement of the pixel areas (PXA) and the transparent area (TA) may be the same arrangement as the arrangement described above in FIG. 3B. The transparent electrode (TPE) of one embodiment may overlap a portion of the pixel areas (PXA) and a portion of the transparent area (TA). The transparent electrode (TPE) may overlap a portion of the transparent area (TA) and not overlap the remaining portion. The transparent electrode (TPE) may overlap a portion of the pixel areas (PXA) and not overlap the remaining portion.

[0293] Referring to FIG. 10b, unlike that illustrated in FIG. 3b, a portion of the transparent area (TA) may overlap with the pixel areas (PXA) in the first direction (DR1). A portion of the transparent area (TA) may be arranged parallel to the pixel areas (PXA) in the second direction (DR2), and the remaining portion may be extended to be arranged parallel to the pixel areas (PXA) in the first direction (DR1).

[0294] The transparent electrode (TPE') overlaps the pixel areas (PXA) and may overlap a part of the transmissive area (TA). The transparent electrode (TPE') may overlap a part of the transmissive area (TA) and may not overlap the remaining part. The transparent electrode (TPE') may overlap the entire pixel areas (PXA). The transparent electrode (TPE') may overlap a part of the transmissive area (TA) that is arranged parallel to the pixel areas (PXA) in the first direction (DR1).

[0295] Referring to FIG. 10c, unlike that illustrated in FIG. 3b, a portion of the transparent area (TA) may overlap with the pixel areas (PXA) in the first direction (DR1). A portion of the transparent area (TA) may be arranged parallel to the pixel areas (PXA) in the second direction (DR2), and the remaining portion may extend to be arranged parallel to the pixel areas (PXA) in the first direction (DR1).

[0296] Additionally, each of the first pixel area (PXA1), the second pixel area (PXA2), and the third pixel area (PXA3) may have an arrangement different from that illustrated in FIG. 3B. In one embodiment, the first pixel area (PXA1) and the second pixel area (PXA2) may be arranged side by side in the second direction (DR2), and the third pixel area (PXA3) may be arranged side by side in the first direction (DR1) with each of the first pixel area (PXA1) and the second pixel area (PXA2).

[0297] The display area (DA) of one embodiment may further include a spacer area (CSA). The spacer area (CSA) may be an area in which a spacer (not shown) is arranged. The spacer (not shown) may be included in the aforementioned display panel (DP, see FIG. 6) and configured to maintain a gap between the display panel (DP, see FIG. 6) and the input sensor (IS, see FIG. 6) and the optical layer (OSL, see FIG. 6) arranged thereon. The spacer area (CSA) may be arranged parallel to the third pixel area (PXA3) in the second direction (DR2).

[0298] The transparent electrode (TPE') overlaps the pixel areas (PXA) and may overlap a part of the transmissive area (TA). The transparent electrode (TPE') may overlap the spacer area (CSA). The transparent electrode (TPE') may overlap a part of the transmissive area (TA) and may not overlap the remaining part. The transparent electrode (TPE') may overlap the entire pixel areas (PXA) and the spacer area (CSA). The transparent electrode (TPE') may overlap a part of the transmissive area (TA) that is arranged parallel to the pixel areas (PXA) and the spacer area (CSA) in the first direction (DR1).

[0299] Fig. 11 is a plan view of an input sensor (IS) according to one embodiment of the present invention. Fig. 11 illustrates the plan shape of an input sensor of an embodiment different from the input sensor of the embodiment illustrated in Fig. 8.

[0300] As illustrated in Fig. 11, the input sensor (IS) includes a detection area (IS-DA) and a non-detection area (IS-NDA) adjacent to the detection area (IS-DA). The detection area (IS-DA) and the non-detection area (IS-NDA) correspond to the display area (DA) and the non-display area (NDA) illustrated in Fig. 3a, respectively.

[0301] The input sensor (IS) includes a plurality of conductive patterns as described above. The plurality of conductive patterns include detection patterns and signal lines. The detection patterns include a plurality of unit detection patterns (SP-U). The signal lines include a plurality of unit signal lines (SL-U).

[0302] A plurality of unit detection patterns (SP-U) that are insulated from each other are arranged in a detection area (IS-DA). Each of the plurality of unit detection patterns (SP-U) is provided in the form of a separate detection electrode, and each of the plurality of unit detection patterns (SP-U) can operate in a "self-capacitance manner" in which it senses an input. In one embodiment, the input sensor (IS) can detect an external input by detecting a self-capacitance voltage charged in each of the plurality of unit detection patterns (SP-U).

[0303] Each of the plurality of unit detection patterns (SP-U) can be electrically isolated from each other. Each of the plurality of unit detection patterns (SP-U) can be spaced apart from each other on a plane. In Fig. 11, each of the plurality of unit detection patterns (SP-U) is exemplarily illustrated as having a rectangular shape on a plane, but is not limited thereto, and each of the unit detection patterns (SP-U) can have a polygonal, circular, or elliptical plane shape other than a square.

[0304] Each of the plurality of unit detection patterns (SP-U) may be connected to a corresponding one of the plurality of unit signal lines (SL-U). Each of the plurality of unit signal lines (SL-U) is connected to a corresponding one of the plurality of unit detection patterns (SP-U) and extends along the first direction (DR1).

[0305] The plurality of unit detection patterns (SP-U) may be provided in multiple rows. The plurality of unit detection patterns (SP-U) may include a first row detection electrode (E1-1), a second row detection electrode (E1-2), a third row detection electrode (E1-3), a fourth row detection electrode (E1-4), and a fifth row detection electrode (E1-5). Unlike as illustrated in FIG. 11, the first detection electrodes (SE1) may include two to four row detection electrodes, or may include six or more row detection electrodes.

[0306] The plurality of unit sensing patterns (SP-U) may be provided in multiple columns. The plurality of unit sensing patterns (SP-U) may include a first heat sensing electrode (E2-1), a second heat sensing electrode (E2-2), a third heat sensing electrode (E2-3), a fourth heat sensing electrode (E2-4), a fifth heat sensing electrode (E2-5), a sixth heat sensing electrode (E2-6), a seventh heat sensing electrode (E2-7), and an eighth heat sensing electrode (E2-8). Unlike as illustrated in FIG. 11, the second sensing electrodes (SE2) may include seven or fewer heat sensing electrodes, or may include nine or more heat sensing electrodes.

[0307] In the present embodiment, each of the plurality of unit signal lines (SL-U) of FIG. 11 may be formed from the first conductive layer (IS-CL1) of FIG. 5. However, the present invention is not limited thereto, and each of the plurality of unit signal lines (SL-U) may also be formed from the second conductive layer (IS-CL2). Each of the plurality of unit signal lines (SL-U) may have a dual wiring structure including both a line formed from the first conductive layer (IS-CL1) and a line formed from the second conductive layer (IS-CL2).

[0308] Each of the plurality of unit detection patterns (SP-U) may be arranged on the same layer. In the input sensor (IS) of one embodiment, each of the plurality of unit detection patterns (SP-U) may be included in a second conductive layer (IS-CL2) and arranged on a second insulating layer (IS-IL2). Each of the plurality of unit detection patterns (SP-U) may be included in a first conductive layer (IS-CL1) and arranged on the first insulating layer (IS-IL1). Each of the plurality of unit detection patterns (SP-U) may be arranged on a different layer from each of the plurality of unit signal lines (SL-U).

[0309] As illustrated in FIG. 11, each of the plurality of unit detection patterns (SP-U) may have a mesh shape in which a plurality of aperture areas are defined. The plurality of aperture areas may, for example, overlap corresponding light-emitting areas and transmission areas (TA) among the plurality of pixel areas (PXA) of FIG. 3b.

[0310] Fig. 12a is an enlarged plan view of a portion of an input sensor according to an embodiment of the present invention. Fig. 12b is an enlarged plan view of a portion of a configuration of an input sensor according to an embodiment of the present invention. Fig. 12c are enlarged cross-sectional views of a portion of an input sensor according to an embodiment of the present invention. Fig. 12a shows an enlarged view of a portion corresponding to the BB area illustrated in Fig. 11. Fig. 12d briefly shows a planar shape of a unit signal line (SL-U) illustrated in Fig. 12a. Fig. 12c shows a cross-section corresponding to the line IV-IV' illustrated in Fig. 12a.

[0311] Referring to FIGS. 11 and 12A together, the input sensor (IS) includes a plurality of conductive patterns, and the plurality of conductive patterns include a plurality of unit detection patterns (SP-U) and a plurality of unit signal lines (SL-U). FIG. 12A illustrates an enlarged view of the shapes of nine unit detection patterns (SP-U) among the plurality of unit detection patterns (SP-U) and nine unit signal lines (SL-U) connected to each of them.

[0312] Each of the multiple unit detection patterns (SP-U) may have multiple pixel apertures (POP) and transmission apertures (TOP) defined.

[0313] The plurality of pixel apertures (POP) may include a first pixel aperture (POP1), a second pixel aperture (POP2), and a third pixel aperture (POP3) spaced apart from each other along a first direction (DR1). The transmission aperture (TOP) may be spaced apart from each of the first pixel aperture (POP1), the second pixel aperture (POP2), and the third pixel aperture (POP3) along the second direction (DR2).

[0314] Meanwhile, the plurality of pixel openings (POP) may be openings corresponding to the pixel areas (PXA) described above in FIG. 3B. The transmission opening (TOP) may be an opening corresponding to the transmission area (TA) described above in FIG. 3B. In the present embodiment, a first pixel area (PXA1) may be arranged inside a first pixel opening (POP1), a second pixel area (PXA2) may be arranged inside a second pixel opening (POP2), and a third pixel area (PXA3) may be arranged inside a third pixel opening (POP3).

[0315] Each of the first sensing patterns (SP1) and the second sensing patterns (SP2) may include a plurality of mesh lines (MSL) defining a plurality of pixel openings (POP) and a plurality of transmission openings (TOP). The plurality of mesh lines (MSL) may include a plurality of mesh elements extending in each of the first direction (DR1) and the second direction (DR2). Meanwhile, the thicknesses of the plurality of mesh elements included in the plurality of mesh lines (MSL) may be the same. However, the present invention is not limited thereto, and any one of the mesh elements included in the mesh line (MSL) may be thicker than the other mesh elements. For example, a mesh element extending in one direction among the mesh lines (MSL) may have a thicker thickness than a mesh element extending in the other direction.

[0316] Each of the plurality of pixel apertures (POP) may have a planar area larger than the area of ​​the overlapping light-emitting areas. For example, the planar area of ​​the first pixel aperture (POP1) may be larger than the area of ​​the first pixel area (PXA1), the planar area of ​​the second pixel aperture (POP2) may be larger than the area of ​​the second pixel area (PXA2), and the planar area of ​​the third pixel aperture (POP3) may be larger than the area of ​​the third pixel area (PXA3). Therefore, the plurality of mesh lines (MSL) defining the plurality of pixel apertures (POP) may not reduce the light emission efficiency of light emitted through the light-emitting areas.

[0317] A top-of-the-panel (TOP) can have a planar area larger than that of the overlapping transmissive area (TA). The planar area of ​​the top-of-the-panel (TOP) can be larger than that of the transmissive area (TA). Therefore, the plurality of mesh lines (MSL) defining the top-of-the-panel (TOP) may not reduce the transmittance of the display device.

[0318] The arrangement and shape of the mesh lines (MSL) can be varied depending on the arrangement and planar area of ​​the plurality of pixel apertures (POP) and transmission apertures (TOP) defined in the mesh lines (MSL). In addition, the arrangement and planar area of ​​the plurality of pixel apertures (POP) and transmission apertures (TOP) can be varied depending on the arrangement and area of ​​the corresponding pixel areas (PXA) and transmission areas (TA).

[0319] Meanwhile, for convenience of explanation, a plurality of mesh lines (MSL) defining a plurality of pixel apertures (POP) and transmission apertures (TOP) may be connected to each other to form an integral shape. That is, a plurality of mesh lines (MSL) may be formed by patterning a plurality of pixel apertures (POP) and transmission apertures (TOP) on an integral conductive layer.

[0320] The input sensor (IS) includes a plurality of conductive patterns, and the plurality of conductive patterns include a plurality of unit detection patterns (SP-U) and a plurality of unit signal lines (SL-U). Each of the plurality of unit signal lines (SL-U) is electrically connected to a corresponding unit detection pattern (SP-U). Each of the plurality of unit signal lines (SL-U) can be electrically connected to mesh lines (MSL) of the corresponding unit detection patterns (SP-U).

[0321] In Fig. 12b, the planar shape of one of the multiple unit signal lines (SL-U) is enlarged and illustrated.

[0322] Referring to FIGS. 12A and 12B, each of the plurality of unit signal lines (SL-U) includes a plurality of sub-signal lines (SL-S1, SL-S2, SL-S3). The plurality of sub-signal lines (SL-S1, SL-S2, SL-S3) extend along a first direction (DR1). Each of the plurality of sub-signal lines (SL-S1, SL-S2, SL-S3) is spaced apart from each other along a second direction (DR2).

[0323] Each of the plurality of unit signal lines (SL-U) may include, for example, three sub-signal lines (SL-S1, SL-S2, SL-S3). The plurality of unit signal lines (SL-U) may include a first sub-signal line (SL-S1), a second sub-signal line (SL-S2), and a third sub-signal line (SL-S3). Each of the first sub-signal line (SL-S1), the second sub-signal line (SL-S2), and the third sub-signal line (SL-S3) may extend along a first direction (DR1) and be spaced apart from each other along a second direction (DR2).

[0324] The width of each of the plurality of sub-signal lines (SL-S1, SL-S2, SL-S3) may be 1 micrometer or more and 5 micrometers. The width (W1) of the first sub-signal line (SL-S1), the width (W2) of the second sub-signal line (SL-S2), and the width (W3) of the third sub-signal line (SL-S3) may each be 1 micrometer or more and 5 micrometers. The width of each of the plurality of unit signal lines (SL-S1, SL-S2, SL-S3) may be smaller than the width of the mesh line (MSL).

[0325] The spacing between each of the plurality of sub-signal lines (SL-S1, SL-S2, SL-S3) may be 3 micrometers or more and 7 micrometers or less. The spacing between the first sub-signal line (SL-S1) and the second sub-signal line (SL-S2), and the spacing between the second sub-signal line (SL-S2) and the third sub-signal line (SL-S3), may each be 3 micrometers or more and 7 micrometers or less.

[0326] An input sensor (IS) of one embodiment includes a plurality of sub-signal lines (SL-S1, SL-S2, SL-S3) in which each of the unit signal lines (SL-U) electrically connected to the mesh lines (MSL) of the corresponding unit sensing patterns (SP-U) is configured to have excellent signal sensitivity while minimizing the area occupied by each of the unit signal lines (SL-U). Accordingly, an input sensor having excellent sensing sensitivity while minimizing dead space and a display device including the same can be provided.

[0327] Referring to FIGS. 12a to 12c, a plurality of sub-signal lines (SL-S1, SL-S2, SL-S3) included in each of a plurality of unit signal lines (SL-U) can be connected to a corresponding unit detection pattern (SP-U).

[0328] Each of the plurality of unit signal lines (SL-U) may be arranged on a different layer from the plurality of unit detection patterns (SP-U). In one embodiment, each of the plurality of unit signal lines (SL-U) may be arranged on a first insulating layer (IS-IL1), and the plurality of unit detection patterns (SP-U) may be arranged on a second insulating layer (IS-IL2). Each of the plurality of unit signal lines (SL-U) may be connected to a corresponding unit detection pattern (SP-U) through a unit contact hole (CH-N) formed in the second insulating layer (IS-IL2). Each of the plurality of sub-signal lines (SL-S1, SL-S2, SL-S3) may be connected to a corresponding unit detection pattern (SP-U) through a unit contact hole (CH-N) formed in the second insulating layer (IS-IL2). Each of the first sub-signal line (SL-S1), the second sub-signal line (SL-S2), and the third sub-signal line (SL-S3) can be connected to a corresponding unit sensing pattern (SP-U) through a unit contact hole (CH-N) formed in the second insulating layer (IS-IL2).

[0329] Fig. 13 is a plan view of an input sensor (IS) according to one embodiment of the present invention. Fig. 13 illustrates the planar shape of an input sensor of one embodiment illustrated in Fig. 11 and an input sensor of another embodiment.

[0330] Referring to FIG. 13, unlike the input sensor illustrated in FIG. 11, the input sensor of one embodiment may further include an additional signal line (SL-A).

[0331] The additional signal line (SL-A) may have an integral shape with some of the plurality of unit detection patterns (SP-U). The additional signal line (SL-A) may be electrically connected to some of the plurality of unit detection patterns (SP-U). In Fig. 13, it is exemplarily illustrated that the additional signal line (SL-A) has an integral shape with the eighth column detection electrode (E2-8) among the plurality of unit detection patterns (SP-U) and is electrically connected thereto, but the present invention is not limited thereto, and the additional signal line (SL-A) may have an integral shape with some of the plurality of unit detection patterns (SP-U) provided in a plurality of rows and columns and be electrically connected thereto.

[0332] Meanwhile, the additional signal line (SL-A) may be arranged on the same layer as the plurality of unit detection patterns (SP-U). In the input sensor (IS) of one embodiment, the plurality of unit detection patterns (SP-U) and the additional signal line (SL-A) may be included in the second conductive layer (IS-CL2) and arranged on the second insulating layer (IS-IL2). Alternatively, the plurality of unit detection patterns (SP-U) and the additional signal line (SL-A) may be included in the first conductive layer (IS-CL1) and arranged on the first insulating layer (IS-IL1). The additional signal line (SL-A) may be arranged on a different layer from each of the plurality of unit signal lines (SL-U).

[0333] In Fig. 13, it is exemplarily shown that the unit signal lines (SL-U) are not connected to the eighth thermal sensing electrodes (E2-8) to which the additional signal line (SL-A) is connected, but this is not limited thereto, and the unit signal lines (SL-U) may also be connected to each of the eighth thermal sensing electrodes (E2-8) to which the additional signal line (SL-A) is connected.

[0334] Hereinafter, the characteristics of an input sensor of an embodiment and an input sensor of a comparative example are compared and shown in Table 1 below. In Table 1 below, Example 1 has a mutual cap type input sensor structure as shown in FIG. 8, and shows the sensitivity of an input sensor including a transparent electrode as shown in FIG. 9a. Example 2 has a self-cap type input sensor structure as shown in FIG. 11, and shows the sensitivity of an input sensor in which unit signal lines are respectively connected to each unit detection pattern as shown in FIGS. 12a to 12c, and each of the unit signal lines includes three sub-signal lines. Comparative Example 1 has a mutual cap type input sensor structure as shown in FIG. 8, but shows the sensitivity of an input sensor that does not include a transparent electrode as shown in FIG. 9a.

[0335] Example 1 Example 2 Comparative Example 1 Mesh line width (μm) 18.9 18.9 18.9 Change in electrostatic capacity (fF) 40 41 517

[0336] Referring to the results in Table 1, it can be confirmed that the input sensors of the embodiment have a significantly increased capacitance change value compared to the capacitance change value of the comparative example, even though they have the same mesh line width as the comparative example 1. Through this, it can be confirmed that the input sensors of one embodiment can be applied to a transparent display device in which the planar area of ​​the transparent area is 60% or more based on the total area of ​​the transparent area and the pixel areas, and can have excellent sensing sensitivity. Although the present invention has been described above with reference to the preferred embodiments, it will be understood by those skilled in the art or having ordinary knowledge in the art that various modifications and changes can be made to the present invention without departing from the spirit and technical scope of the present invention as set forth in the claims to be described later. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

[0337] The display device of the present invention can improve the transmittance of the display device by increasing the ratio of the transparent area in the display area, while also ensuring a large range of change in the electrostatic capacity of the input sensor, thereby improving the sensing performance of the input sensor and the display device including the same. Therefore, the present invention, which provides the display device of the present invention, has high industrial applicability.

Claims

1. A display panel including a display area including a transparent area and a non-display area adjacent to the display area; and An input sensor disposed on the display panel and including a plurality of conductive patterns; The above multiple challenge patterns are A first sensing electrode including a plurality of first sensing patterns provided along a first direction, and a plurality of bridge patterns connecting two adjacent ones of the plurality of first sensing patterns; A second sensing electrode including a plurality of second sensing patterns provided along a second direction intersecting the first direction and spaced apart from the first sensing electrode; and A transparent electrode electrically connected to at least some of the first detection electrode and the second detection electrode; Each of the plurality of first detection patterns and the plurality of second detection patterns includes a plurality of mesh lines defining at least a transmission opening overlapping the transmission area, A display device in which the above transparent electrode overlaps at least a portion of the above transparent area.

2. In paragraph 1, A display device wherein the display area further includes a plurality of pixel areas adjacent to the transmission area and emitting light.

3. In paragraph 2, A display device wherein, in the above display area, the ratio of the transparent area to the total area of ​​the transparent area and the plurality of pixel areas is 60% or more.

4. In paragraph 1, The above input sensor Further comprising a cover insulating layer disposed between the first detection electrode, the second detection electrode, and the transparent electrode, A display device in which the transparent electrode is electrically connected to at least a portion of the first sensing electrode and the second sensing electrode through an upper contact hole penetrating the cover insulating layer.

5. In paragraph 2, A display device in which the transparent electrode overlaps at least a portion of the transparent area and each of the plurality of pixel areas.

6. In paragraph 1, The above multiple challenge patterns are A display device further comprising a dummy pattern disposed on the same layer as the transparent electrode and insulated from the first sensing electrode and the second sensing electrode.

7. In paragraph 2, The above multiple pixel areas are It comprises a first pixel area, a second pixel area, and a third pixel area arranged along the first direction, The above-mentioned transparent area is a display device adjacent to each of the first pixel area, the second pixel area, and the third pixel area along the second direction.

8. In paragraph 1, The above transparent electrode is a display device including a transparent conductive oxide (TCO).

9. In paragraph 2, The above display panel outputs source light and includes a light-emitting element overlapping at least each of the plurality of pixel areas, The above light emitting element First electrode; A first light-emitting stack disposed on the first electrode; A second light-emitting stack disposed on the first light-emitting stack; A third light-emitting stack disposed on the second light-emitting stack; A fourth light-emitting stack disposed on the third light-emitting stack; A second electrode disposed on the fourth light-emitting stack; and A charge generation layer disposed between each of the first to fourth light-emitting stacks; A display device, wherein each of the first to fourth light-emitting stacks includes at least one light-emitting layer.

10. In paragraph 9, A display device further comprising a light control layer disposed on the light-emitting element and transmitting the source light or converting the source light into light of a different wavelength.

11. In paragraph 10, The above optical control layer comprises a bank including a plurality of bank openings, and a plurality of optical control patterns arranged inside each of the plurality of bank openings, A display device in which the above plurality of light control patterns do not overlap the above transmission area.

12. In paragraph 9, A display device wherein at least one light-emitting layer included in each of the first light-emitting stack to the fourth light-emitting stack does not overlap the transparent area.

13. In paragraph 1, A display device wherein the second sensing electrode is positioned between two adjacent second sensing patterns among the plurality of second sensing patterns, and further includes a connecting pattern having an integral shape with the plurality of second sensing patterns.

14. In paragraph 1, The above input sensor further includes a detection insulating layer disposed between the plurality of bridge patterns and the plurality of first detection patterns, A display device in which each of the plurality of bridge patterns is electrically connected to each of the plurality of first sensing patterns through a lower contact hole defined in the sensing insulating layer.

15. In paragraph 1, The above penetration area is A first transparent region overlapping the transparent electrode on a plane; and A display device including a second transparent region that does not overlap with the transparent electrode on a plane.

16. A display panel including a display area including a transparent area and a non-display area adjacent to the display area; and An input sensor disposed on the display panel and including a plurality of conductive patterns; The above multiple challenge patterns are A plurality of unit detection patterns provided along each of a first direction and a second direction intersecting the first direction, each of which is insulated from each other; and A plurality of unit signal lines each connected to at least some of the plurality of unit detection patterns; Each of the above plurality of unit detection patterns includes a plurality of mesh lines defining at least a transmission opening overlapping the transmission area, Each of the above multiple unit signal lines A display device including a plurality of sub-signal lines, each of which extends along the first direction and is connected to a corresponding one of the plurality of unit detection patterns.

17. In paragraph 16, The above multiple sub signal lines A first sub-signal line connected to a first unit detection pattern, which is one of the above unit detection patterns, and extending along the first direction; A second sub-signal line connected to the first unit detection pattern, extending along the first direction, and spaced apart from the first sub-signal line along the second direction; and A display device including a third sub-signal line connected to the first unit detection pattern, extending along the first direction, and spaced apart from each of the first sub-signal line and the second sub-signal line along the second direction; 18. In paragraph 16, The width of each of the above multiple sub-signal lines is 1 micrometer or more and 5 micrometers or less, A display device wherein the spacing between each of the plurality of sub-signal lines is 3 micrometers or more and 7 micrometers or less.

19. In Article 16, The above multiple challenge patterns are A display device further comprising an additional signal line having an integral shape with some of the plurality of unit detection patterns, electrically connected to some of the plurality of unit detection patterns, and overlapping the non-display area.

20. In paragraph 16, The above input sensor Further comprising a detection insulating layer disposed between the plurality of unit detection patterns and the plurality of unit signal lines, A display device in which each of the plurality of unit signal lines is electrically connected to each of the plurality of unit detection patterns through a unit contact hole penetrating the detection insulating layer.

21. In paragraph 16, A display device wherein the display area further includes a plurality of pixel areas adjacent to the transmission area and emitting light.

22. In paragraph 21, A display device wherein, in the above display area, the ratio of the transparent area to the total area of ​​the transparent area and the plurality of pixel areas is 60% or more.

23. In paragraph 21, The above multiple pixel areas are It comprises a first pixel area, a second pixel area, and a third pixel area arranged along the first direction, The above-mentioned transparent area is a display device adjacent to each of the first pixel area, the second pixel area, and the third pixel area along the second direction.

24. In paragraph 21, The above display panel outputs source light and includes a light-emitting element overlapping at least each of the plurality of pixel areas, The above light emitting element First electrode; A first light-emitting stack disposed on the first electrode; A second light-emitting stack disposed on the first light-emitting stack; A third light-emitting stack disposed on the second light-emitting stack; A fourth light-emitting stack disposed on the third light-emitting stack; A second electrode disposed on the fourth light-emitting stack; and A charge generation layer disposed between each of the first to fourth light-emitting stacks; A display device, wherein each of the first to fourth light-emitting stacks includes at least one light-emitting layer.

25. In paragraph 24, A display device further comprising a light control layer disposed on the light-emitting element and transmitting the source light or converting the source light into light of a different wavelength.

26. In paragraph 25, The above optical control layer comprises a bank including a plurality of bank openings, and a plurality of optical control patterns arranged inside each of the plurality of bank openings, A display device in which the above plurality of light control patterns do not overlap the above transmission area.

27. In paragraph 24, A display device wherein at least one light-emitting layer included in each of the first light-emitting stack to the fourth light-emitting stack does not overlap the transparent area.

28. A display panel including a display area including a transparent area and a plurality of pixel areas adjacent to the transparent area, and a non-display area adjacent to the display area; and An input sensor disposed on the display panel and including a plurality of conductive patterns; The above multiple challenge patterns are comprising a plurality of detection patterns provided along each of a first direction and a second direction intersecting the first direction, The above detection patterns include multiple mesh lines, A transmission aperture overlapping the transmission area and a pixel aperture overlapping each of the plurality of pixel areas are defined in the plurality of mesh lines, A display device wherein, in the above display area, the ratio of the transparent area to the total area of ​​the transparent area and the plurality of pixel areas is 60% or more.

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