Shift register and display panel

Abstract

A shift register and a display panel, relating to the technical field of display. The shift register is applied to the display panel. The display panel has a full-screen display mode and a local display mode. The shift register comprises: a gate signal generation circuit configured to generate a gate drive signal; and an output selection circuit configured to, under the control of a control signal, output the gate drive signal in the full-screen display mode and output a non-operating level signal in the local display mode. The shift register also has good leakage resistance and low power consumption.

Description

Shift register and display panel Technical Field

[0001] The present disclosure belongs to the field of display technology, and particularly relates to a shift register and a display panel. Background Art

[0002] In existing technologies, pixel driver circuits typically use low-temperature polycrystalline oxide technology to achieve narrow bezels, low power consumption, and high reliability. However, oxide thin-film transistors (TFTs) have poor stability and their threshold voltage (Vth) is prone to negative bias, which can cause leakage current in the circuit, resulting in additional power consumption, reduced circuit reliability, and even circuit failure.

[0003] Summary of the Invention

[0004] The present invention aims to solve at least one of the technical problems existing in the prior art and provides a shift register applied to a display panel having a full-screen display mode and a partial display mode. The shift register comprises:

[0005] a gate signal generating circuit configured to generate a gate driving signal;

[0006] The output selection circuit is configured to output the gate drive signal in the full-screen display mode and output a non-working level signal in the partial display mode under the control of the control signal.

[0007] Preferably, the output selection circuit includes:

[0008] a first output selection subcircuit configured to, in response to the gate drive signal and the control signal, alternately output a second level signal and a third level signal in a full-screen mode, and output the second level signal in a partial display mode;

[0009] a first NOT gate configured to alternately output a first level signal and the third level signal in full-screen mode, and output the third level signal in partial mode; the first level signal being an operating level signal of the gate drive signal, and the third level signal being a non-operating level signal of the gate drive signal;

[0010] The first level signal is greater than the second level signal.

[0011] Preferably, the first output selection sub-circuit includes: a ninth transistor, a tenth transistor, an eleventh transistor and a twelfth transistor;

[0012] The control electrode of the ninth transistor is connected to the control signal terminal, the first electrode is connected to the signal output terminal of the first output selection sub-circuit, and the second electrode is connected to the second level signal terminal;

[0013] The control electrode of the tenth transistor is connected to the control signal terminal, the first electrode is connected to the third level signal terminal, and the second electrode is connected to the first electrode of the twelfth transistor;

[0014] The control electrode of the eleventh transistor is connected to the signal output terminal of the gate signal generating circuit, the first electrode is connected to the signal output terminal of the first output selection sub-circuit, and the second electrode is connected to the second level signal terminal;

[0015] The control electrode of the twelfth transistor is connected to the signal output end of the gate signal generating circuit, the first electrode is connected to the second electrode of the tenth transistor, and the second electrode is connected to the signal output end of the first output selection sub-circuit.

[0016] Preferably, the first NOT gate includes: a thirteenth transistor and a fourteenth transistor;

[0017] The connection node of the control electrode of the thirteenth transistor and the control electrode of the fourteenth transistor is multiplexed as the signal input terminal of the first NOT gate, connected to the signal output terminal of the first output selection sub-circuit; the first electrode of the thirteenth transistor and the second electrode of the fourteenth transistor are multiplexed as the signal output terminal of the first NOT gate;

[0018] The second electrode of the thirteenth transistor is connected to the first level signal terminal; the first electrode of the fourteenth transistor is connected to the third level signal terminal.

[0019] Preferably, the output selection circuit includes:

[0020] a second output selection subcircuit configured to, in response to the gate drive signal and the control signal, alternately output a first level signal and a third level signal in a full-screen mode, and output the first level signal in a partial display mode;

[0021] a second NOT gate configured to alternately output the first level signal and the third level signal in full-screen mode, and output the third level signal in partial display mode; the third level signal is an operating level signal of the gate drive signal, and the second level signal is a non-operating level signal of the gate drive signal;

[0022] The first level signal and the second level signal have the same positive and negative sign; the first level signal is greater than the second level signal.

[0023] Preferably, the second output selection sub-circuit includes: a 34th transistor, a 35th transistor, a 36th transistor and a 37th transistor; wherein,

[0024] The control electrode of the thirty-fourth transistor is connected to the signal output terminal of the gate signal generating circuit, the first electrode is connected to the third level signal terminal, and the second electrode is connected to the signal output terminal of the second output selection sub-circuit;

[0025] The control electrode of the thirty-fifth transistor is connected to the signal output terminal of the gating circuit, the first electrode is connected to the third level signal terminal, and the second electrode is connected to the signal output terminal of the second output selection sub-circuit;

[0026] The control electrode of the thirty-sixth transistor is connected to the signal output terminal of the gate signal generating circuit, the first electrode is connected to the signal output terminal of the second output selection sub-circuit, and the second electrode is connected to the first electrode of the thirty-seventh transistor;

[0027] The control electrode of the thirty-seventh transistor is connected to the signal output end of the gating circuit, and the second electrode is connected to the first level signal end.

[0028] Preferably, the second NOT gate includes: a thirty-eighth transistor and a thirty-ninth transistor;

[0029] The control electrode of the thirty-eighth transistor is connected to the signal output terminal of the second output selection sub-circuit, the first electrode is connected to the signal output terminal of the second NOT gate, and the second electrode is connected to the first level signal terminal;

[0030] The control electrode of the thirty-ninth transistor is connected to the signal output end of the second output selection sub-circuit, the first electrode is connected to the third level signal end, and the second electrode is connected to the signal output end of the second NOT gate.

[0031] Preferably, the first gate signal generating circuit includes a first input subcircuit, a second input subcircuit, a first control subcircuit, a second control subcircuit, a first voltage stabilizing subcircuit, a first output subcircuit and a second output subcircuit; wherein,

[0032] The first input subcircuit is configured to transmit an input signal to a second node in response to a first clock signal; the second node is a connection node between the first input subcircuit, the first control subcircuit, the second control subcircuit, and the first voltage stabilization subcircuit;

[0033] The second input sub-circuit is configured to transmit a second level signal to a first node in response to the first clock signal; the first node is a connection node between the second input sub-circuit, the first control sub-circuit, the second control sub-circuit, and the first output sub-circuit;

[0034] The first control subcircuit is configured to transmit the first clock signal to the first node in response to the voltage of the second node;

[0035] The second control sub-circuit is configured to transmit the third level signal to the second node in response to the voltage of the first node and a second clock signal;

[0036] The first voltage stabilizing sub-circuit is configured to transmit the voltage of the second node to the third node in response to the second level signal; the third node is a connection node between the voltage stabilizing sub-circuit and the second output sub-circuit;

[0037] The first output sub-circuit is configured to transmit the third level signal to the signal output terminal of the first gate signal generating circuit in response to the voltage of the first node;

[0038] The second output sub-circuit is configured to transmit the second clock signal to the signal output terminal of the first gate signal generating circuit in response to the voltage of the third node.

[0039] Preferably, the first input sub-circuit includes a first transistor; the control electrode of the first transistor is connected to the first clock signal terminal, the first electrode is connected to the input signal terminal, and the second electrode is connected to the second node.

[0040] Preferably, the second input sub-circuit includes a third transistor; the control electrode of the third transistor is connected to the first clock signal terminal, the first electrode is connected to the second level signal terminal, and the second electrode is connected to the first node.

[0041] Preferably, the first control subcircuit includes a second transistor; the control electrode of the second transistor is connected to the second node, the first electrode is connected to the first node, and the second electrode is connected to the first clock signal terminal.

[0042] Preferably, the second control subcircuit includes a sixth transistor and a seventh transistor; the sixth transistor has a control electrode connected to the second node, a first electrode connected to the third level signal terminal, and a second electrode connected to the first electrode of the seventh transistor; the seventh transistor has a control electrode connected to the second clock signal terminal, a first electrode connected to the second electrode of the sixth transistor, and a second electrode connected to the second node.

[0043] Preferably, the first voltage stabilizing sub-circuit includes an eighth transistor; the control electrode of the eighth transistor is connected to the second level signal terminal, the first electrode is connected to the second node, and the second electrode is connected to the third node.

[0044] Preferably, the first output sub-circuit includes a fourth transistor and a first capacitor; the control electrode of the fourth transistor is connected to the first node, the first electrode is connected to the third level signal end, and the second electrode is connected to the signal output end of the first gate signal generating circuit; one electrode of the first capacitor is connected to the first node, and the other electrode is connected to the third level signal end.

[0045] Preferably, the second output sub-circuit includes a fifth transistor and a second capacitor; the control electrode of the fifth transistor is connected to the third node, the first electrode is connected to the signal output end of the first gate drive circuit, and the second electrode is connected to the second clock signal end; one electrode of the second capacitor is connected to the third node, and the other electrode is connected to the signal output end of the first gate signal generating circuit.

[0046] Preferably, the second gate signal generating circuit includes a third input subcircuit, a fourth input subcircuit, a second voltage stabilizing subcircuit, a third control subcircuit, a fourth control subcircuit, a fifth control subcircuit, a sixth control subcircuit, a third output subcircuit and a fourth output subcircuit; wherein,

[0047] The third input sub-circuit is configured to transmit the second level signal to a fourth node in response to the first clock signal; the fourth node is a connection node between the third input sub-circuit, the third control sub-circuit, and the second voltage stabilization sub-circuit;

[0048] The fourth input sub-circuit is configured to transmit a first selection signal to a fifth node, a sixth node, and a seventh node in response to the first clock signal and the second level signal; the fifth node is a connection node between the third control sub-circuit and the fourth input sub-circuit; the sixth node is a connection node between the fourth input sub-circuit and the fourth control sub-circuit; and the seventh node is a connection node between the fourth input sub-circuit, the fourth control sub-circuit, and the fourth output sub-circuit;

[0049] The second voltage stabilizing sub-circuit is configured to transmit the voltage of the fourth node to an eighth node in response to the second level signal; the eighth node is a connection node between the second voltage stabilizing sub-circuit and the fifth control sub-circuit;

[0050] the third control subcircuit is configured to transmit the first clock signal to the fourth node in response to the voltage of the fifth node;

[0051] the fourth control subcircuit is configured to transmit the voltage of the sixth node to the seventh node in response to the voltage of the fourth node, the voltage of the sixth node, and the voltage of the seventh node;

[0052] the fifth control sub-circuit is configured to transmit the second clock signal to a ninth node in response to the voltage of the eighth node and the second clock signal terminal; the ninth node is a connection node between the fifth control sub-circuit and the third output sub-circuit;

[0053] the sixth control subcircuit is configured to transmit the third level signal to the fifth node and the ninth node in response to the voltage of the fifth node and the fourth level signal;

[0054] The third output sub-circuit is configured to transmit the third level signal to the signal output terminal of the second gate signal generating circuit in response to the voltage of the ninth node;

[0055] The fourth output sub-circuit is configured to transmit the second level signal to the signal output terminal of the second gate signal generating circuit in response to the voltage of the seventh node.

[0056] Preferably, the third input sub-circuit includes a fifteenth transistor; the control electrode of the fifteenth transistor is connected to the first clock signal terminal, the first electrode is connected to the second level signal terminal, and the second electrode is connected to the fourth node.

[0057] Preferably, the fourth input sub-circuit includes a sixteenth transistor, a seventeenth transistor, an eighteenth transistor and a nineteenth transistor;

[0058] The control electrode of the sixteenth transistor is connected to the first clock signal terminal, the first electrode is connected to the first selection signal terminal, and the second electrode is connected to the fifth node; the control electrode of the seventeenth transistor is connected to the second level signal terminal, the first electrode is connected to the fifth node, and the second electrode is connected to the seventh node; the first electrode of the eighteenth transistor is connected to the first clock signal terminal, the first electrode is connected to the first selection signal terminal, and the second electrode is connected to the first electrode of the nineteenth transistor; the control electrode of the nineteenth transistor is connected to the second level signal terminal, and the second electrode is connected to the sixth node.

[0059] Preferably, the second voltage stabilizing sub-circuit includes a twenty-third transistor; the control electrode of the twenty-third transistor is connected to the second level signal terminal, the first electrode is connected to the fourth node, and the second electrode is connected to the eighth node.

[0060] Preferably, the third control subcircuit includes a twentieth transistor; a control electrode of the twentieth transistor is connected to the fifth node, a first electrode is connected to the fourth node, and a second electrode is connected to the first clock signal terminal.

[0061] Preferably, the fourth control subcircuit includes a twenty-first transistor, a twenty-second transistor, a twenty-ninth transistor and a fifth capacitor;

[0062] The control electrode of the 21st transistor is connected to the fourth node, the first electrode is connected to the third level signal terminal, and the second electrode is connected to the first electrode of the 22nd transistor; the control electrode of the 22nd transistor is connected to the third node, and the second electrode is connected to the second clock signal terminal; the control electrode of the 29th transistor is connected to the sixth node, the first electrode is connected to the seventh node, and the second electrode is connected to the sixth node; one electrode of the fifth capacitor is connected to the second electrode of the 21st transistor, and the other electrode is connected to the sixth node.

[0063] Preferably, the fifth control subcircuit includes a twenty-fourth transistor, a twenty-fifth transistor and a third capacitor;

[0064] The control electrode of the 24th transistor is connected to the eighth node, the first electrode is connected to the second clock signal end, and the second electrode is connected to the first electrode of the 25th transistor; the control electrode of the 25th transistor is connected to the second clock signal end, and the second electrode is connected to the ninth node; one electrode of the third capacitor is connected to the eighth node, and the other electrode is connected to the second electrode of the 24th transistor.

[0065] Preferably, the sixth control subcircuit includes a twenty-seventh transistor and a twenty-eighth transistor;

[0066] The control electrode of the twenty-seventh transistor is connected to the fifth node, the first electrode is connected to the ninth node, and the second electrode is connected to the third level signal end; the control electrode of the twenty-eighth transistor is connected to the fourth level signal, the first electrode is connected to the third level signal end, and the second electrode is connected to the fifth node.

[0067] Preferably, the third output sub-circuit includes a twenty-sixth transistor and a fourth capacitor;

[0068] The control electrode of the twenty-sixth transistor is connected to the ninth node, the first electrode is connected to the third level signal terminal, and the second electrode is connected to the signal output terminal of the second gate signal generating circuit; one electrode of the fourth capacitor is connected to the third level signal terminal, and the other electrode is connected to the ninth node.

[0069] Preferably, the fourth output sub-circuit includes a thirtieth transistor and a seventh capacitor;

[0070] The control electrode of the 30th transistor is connected to the seventh node, the first electrode is connected to the signal output terminal of the second gate signal generating circuit, and the second electrode is connected to the second level signal terminal; one electrode of the seventh capacitor is connected to the second level signal terminal, and the other electrode is connected to the first electrode of the 30th transistor;

[0071] The signal output terminal of the second gate signal generating circuit outputs a second selection signal.

[0072] Preferably, it further comprises a gating circuit; the signal output terminal of the gating circuit is connected to the second output selection sub-circuit;

[0073] The gate circuit is configured to output the second level signal or the third level signal in response to a first gate signal and a second gate signal.

[0074] Preferably, the gating circuit includes a thirty-first transistor, a thirty-second transistor, a thirty-third transistor and a sixth capacitor;

[0075] The control electrode of the thirty-first transistor is connected to the fourth level signal, the first electrode is connected to the third level signal, and the second electrode is connected to the signal output end of the gating circuit;

[0076] The control electrode of the thirty-second transistor is connected to the first selection signal terminal, the first electrode is connected to the signal output terminal of the selection circuit, and the second electrode is connected to the first electrode of the thirty-third transistor;

[0077] The control electrode of the thirty-third transistor is connected to the second selection signal terminal, and the second electrode is connected to the control signal terminal;

[0078] One electrode of the sixth capacitor is connected to the second level signal, and the other electrode is connected to the signal output end of the gating circuit.

[0079] Preferably, it further comprises a plurality of pixel units; the pixel units are connected to the shift registers in a one-to-one correspondence.

[0080] In a second aspect, the present disclosure provides a display panel comprising the above-mentioned shift register. BRIEF DESCRIPTION OF THE DRAWINGS

[0081] FIG1 is a schematic structural diagram of a shift register according to a first embodiment of the present disclosure;

[0082] FIG2 is a structural block diagram of a shift register according to a first embodiment of the present disclosure;

[0083] FIG3 is a 0V leakage simulation result of the shift register according to the first embodiment of the present disclosure;

[0084] FIG4 is a schematic structural diagram of a shift register according to a second embodiment of the present disclosure;

[0085] FIG5 is a structural block diagram of a shift register according to a second embodiment of the present disclosure;

[0086] FIG6 is a diagram showing simulation results of the output signal of the shift register according to the second embodiment of the present disclosure. DETAILED DESCRIPTION

[0087] In order to enable those skilled in the art to better understand the technical solution of the present invention, the present invention is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0088] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by people with ordinary skills in the field to which this disclosure belongs. The words "first", "second" and similar words used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one", "an" or "the" do not indicate a quantity limitation, but rather indicate the existence of at least one. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0089] It should be noted that the transistors in the embodiments of the present disclosure are oxide transistors. Due to their structural characteristics, oxide transistors are susceptible to external environmental influences such as temperature, causing threshold voltage (Vth) drift, affecting the stability and reliability of the transistors and, in turn, the display quality of the display panel. Optionally, the switching characteristics of the transistors in the embodiments of the present disclosure can be N-type or P-type.

[0090] In the embodiments of the present disclosure, the source and drain of each transistor are structurally identical and interchangeable. To distinguish the two electrodes other than the gate, one electrode is referred to as the source and the other as the drain. The first electrode can be the source and the second electrode can be the drain.

[0091] In the embodiments of the present disclosure, the first level signal can be a high level signal or a low level signal, depending on the switching characteristics of the transistor. Accordingly, the second level signal has the same absolute value as the first level signal but an opposite sign. The input signal in the present disclosure can be an STV signal or the output signal of the previous stage circuit.

[0092] In a first aspect, the present disclosure provides a shift register for use in a display panel. Optionally, the display panel has a full-screen display mode and a partial display mode. The display panel includes a plurality of pixel units and a plurality of shift registers, and the pixel units and the shift registers are connected in a one-to-one correspondence. The shift register includes a gate signal generating circuit and an output selection circuit 30. The gate signal generating circuit is configured to generate a gate drive signal for driving the pixel unit. The output selection circuit 30 is configured to output a gate drive signal in full-screen display mode and output a non-working level signal in partial display mode under the control of a control signal MS, so as to update a partial screen of the display panel. The panel portion that does not need to be updated does not need to be charged and discharged multiple times, thereby reducing the power consumption of the display panel.

[0093] Preferably, the shift register disclosed in the present invention effectively solves the leakage problem of the shift register and improves the reliability of the circuit by setting different parts of the circuit to connect low-level signal terminals of different sizes.

[0094] The shift register disclosed in the present invention is described below with reference to specific embodiments.

[0095] First example: As shown in FIG. 1-2 , the shift register of the first example includes a first gate signal generating circuit 10 , a first output selecting sub-circuit 51 and a first NOT gate 61 .

[0096] 1 , the first gate signal generating circuit 10 includes a first input subcircuit 11 , a second output subcircuit 42 , a first control subcircuit 21 , a second control subcircuit 22 , a first voltage stabilizing subcircuit 31 , a first output subcircuit 41 , and a second output subcircuit 42 .

[0097] The first input sub-circuit 11 is configured to transmit an input signal STV to the second node N2 in response to the first clock signal CK. The second input sub-circuit 12 is configured to transmit a second level signal VGL2 to the first node N1 in response to the first clock signal CK. The first control sub-circuit 21 is configured to transmit the first clock signal CK to the first node N1 in response to the voltage of the second node N2. The second control sub-circuit 22 is configured to transmit a third level signal VGH to the second node N2 in response to the voltage of the first node N1 and the second clock signal CB. The first voltage regulation sub-circuit 31 is configured to transmit the voltage of the second node N2 to the third node N3 in response to the second level signal VGL2. The first output sub-circuit 41 is configured to transmit the third level signal VGH to the signal output terminal of the first gate signal generating circuit 10 in response to the voltage of the first node N1. The second output sub-circuit 42 is configured to transmit the second clock signal CB to the signal output terminal of the first gate signal generating circuit 10 in response to the voltage of the third node N3.

[0098] It should be noted that the first node N1 is a connection node between the second input sub-circuit 12, the first control sub-circuit 21, the second control sub-circuit 22, and the first output sub-circuit 41. The second node N2 is a connection node between the first input sub-circuit 11, the first control sub-circuit 21, the second control sub-circuit 22, and the first voltage stabilization sub-circuit 31. The third node N3 is a connection node between the first voltage stabilization sub-circuit 31 and the second output sub-circuit 42.

[0099] The shift register includes first to fourteenth transistors T1-T14. The first to eighth transistors T1-T8, the tenth transistor T10, the twelfth transistor T12, and the fourteenth transistor T14 are all P-type transistors. For a P-type transistor, when a low-level signal is input to the gate, the transistor is turned on; when a high-level signal is input to the gate, the transistor is turned off. The ninth transistor T9, the eleventh transistor T11, and the thirteenth transistor T13 are all N-type transistors. For an N-type transistor, when a high-level signal is input to the gate, the transistor is turned on; when a low-level signal is input to the gate, the transistor is turned off.

[0100] The first input sub-circuit 11 includes a first transistor T1. The control electrode of the first transistor T1 is connected to the first clock signal CK terminal, the first electrode is connected to the input signal STV terminal, and the second electrode is connected to the second node N2. When a low-level signal is written to the control electrode of the first transistor T1, the first transistor T1 turns on, and the input signal STV is written to the second node N2 through the first transistor T1.

[0101] The second input sub-circuit 12 includes a third transistor T3. The control electrode of the third transistor T3 is connected to the first clock signal CK terminal, the first electrode is connected to the second level signal VGL2 terminal, and the second electrode is connected to the first node N1. When a low-level signal is written to the control electrode of the third transistor T3, the third transistor T3 turns on, and the second level signal VGL2 is written to the first node N1 through the third transistor T3.

[0102] The first control subcircuit 21 includes a second transistor T2. The control electrode of the second transistor T2 is connected to the second node N2, the first electrode is connected to the first node N1, and the second electrode is connected to the first clock signal CK terminal. When a low-level signal is written to the control electrode of the second transistor T2, the second transistor T2 turns on, and the first clock signal CK is written to the first node N1 through the second transistor T2.

[0103] The second control subcircuit 22 includes a sixth transistor T6 and a seventh transistor T7. The control electrode of the sixth transistor T6 is connected to the first node N1, the first electrode is connected to the third level signal VGH terminal, and the second electrode is connected to the first electrode of the seventh transistor T7. The control electrode of the seventh transistor T7 is connected to the second clock signal CB terminal, and the second electrode is connected to the second node N2. When a low-level signal is written to the control electrodes of the sixth transistor T6 and the seventh transistor T7, the voltage of the first node N1 is transmitted to the second node N2 through the sixth transistor T6 and the seventh transistor T7.

[0104] The first voltage stabilization sub-circuit 31 includes an eighth transistor T8. The eighth transistor T8 has a control electrode connected to the second level signal VGL2 terminal, a first electrode connected to the second node N2, and a second electrode connected to the third node N3. When a low-level signal is written to the control electrode of the eighth transistor T8, the eighth transistor T8 turns on, and the voltage of the second node N2 is transmitted to the third node N3 through the eighth transistor T8.

[0105] The first output sub-circuit 41 includes a fourth transistor T4 and a first capacitor C1. The control electrode of the fourth transistor T4 is connected to the first node N1, the first electrode is connected to the terminal for the third level signal VGH, and the second electrode is connected to the signal output terminal of the first gate signal generating circuit 10. The two electrodes of the first capacitor C1 are connected to the control electrode and the first electrode of the fourth transistor T4, respectively. When a low-level signal is written to the control electrode of the fourth transistor T4, the fourth transistor T4 turns on, and the third level signal VGH is transmitted through the fourth transistor T4 to the signal output terminal of the first gate signal generating circuit 10.

[0106] The second output sub-circuit 42 includes a fifth transistor T5 and a second capacitor C2. The control electrode of the fifth transistor T5 is connected to the third node N3, the first electrode is connected to the signal output terminal of the first gate signal generating circuit 10, and the second electrode is connected to the second clock signal CB terminal. The two electrodes of the second capacitor C2 are connected to the control electrode and the first electrode of the fifth transistor T5, respectively. When a low-level signal is written to the control electrode of the fifth transistor T5, the fifth transistor T5 turns on, and the second clock signal CB is transmitted through the fifth transistor T5 to the signal output terminal of the first gate signal generating circuit 10 for output.

[0107] The first output selection sub-circuit 51 includes a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11, and a twelfth transistor T12. The connection node of the control electrodes of the eleventh transistor T11 and the twelfth transistor T12 serves as a first input terminal of the first output selection sub-circuit 51, connected to the signal output terminal of the gate drive signal first gate signal generating circuit 10. The connection node of the control electrodes of the ninth transistor T9 and the tenth transistor T10 serves as a second input terminal of the first output selection sub-circuit 51, connected to the control signal MS terminal. The connection node of the second electrode of the twelfth transistor T12, the first electrode of the eleventh transistor T11, and the first electrode of the ninth transistor T9 serves as a signal output terminal of the first output selection sub-circuit 51. Furthermore, the second electrode of the ninth transistor T9 is connected to the second level signal VGL2 terminal, the first electrode of the tenth transistor T10 is connected to the third level signal terminal, the second electrode of the tenth transistor T10 is connected to the first electrode of the twelfth transistor T12, and the second electrode of the eleventh transistor T11 is connected to the second level signal VGL2 terminal.

[0108] The first NOT gate 61 includes a thirteenth transistor T13 and a fourteenth transistor T14. The connection node of the control electrode of the thirteenth transistor T13 and the control electrode of the fourteenth transistor T14 is multiplexed as a signal input terminal of the first NOT gate 61. The connection node of the first electrode of the thirteenth transistor T13 and the second electrode of the fourteenth transistor T14 is multiplexed as a signal output terminal of the first NOT gate 61. The first electrode of the fourteenth transistor T14 is connected to the third level signal VGH terminal, and the second electrode of the thirteenth transistor T13 is connected to the first level signal VGL1 terminal.

[0109] The following is the working process of the first gate signal generating circuit 10 of the first example.

[0110] In the first phase, a low-level signal is written to the first clock signal CK, a high-level signal is written to the second clock signal CB, and a low-level signal is written to the input signal STV. The first transistor T1 and the third transistor T3 are both turned on, and the input signal STV is written to the second node N2 and the third node N3 via the first transistor T1. The second-level signal VGL2 is written to the first node N1 via the third transistor T3 and charges the first capacitor C1. The fourth transistor T4 and the fifth transistor T5 are both turned on, and the signal output terminal of the first gate signal generating circuit 10 is reset by the high-level third-level signal VGH and the high-level signal written to the second clock signal CB.

[0111] In the second phase, a high-level signal is written to the first clock signal CK, a low-level signal is written to the second clock signal CB, and a high-level signal is written to the input signal STV. The first transistor T1 and the third transistor T3 are both turned off. The low-level signal stored in the first capacitor C1 is slowly discharged to turn on the sixth transistor T6. The second clock signal CB turns on the seventh transistor T7 and the seventh transistor T7T6. The third-level signal VGH is transmitted to the second node N2 through the sixth transistor T6 and the seventh transistor T7 and the seventh transistor T7T6, turning on the eighth transistor T8. The low-level signal stored in the second capacitor C2 is slowly pulled down by the eighth transistor T8 to lower the voltage of the second node N2. The second transistor T2 is turned on. The high-level signal written by the first clock signal CK raises the voltage of the first node N1, turning off the fourth transistor T4. The voltage of the third node N3 continues to maintain a low-level signal under the action of the second capacitor C2. The fifth transistor T5 continues to be turned on. The low-level signal written by the second clock signal CB is transmitted to the signal output terminal of the first gate signal generating circuit 10 for output.

[0112] In the third phase, a low-level signal is written to the first clock signal CK, a high-level signal is written to the second clock signal CB, and a high-level signal is written to the input signal STV. The first transistor T1 and the third transistor T3 are both turned on. The input signal STV is transmitted to the second node N2, turning off the second transistor T2 and the fifth transistor T5. The second-level signal VGL2 is written to the first node N1, turning on the fourth transistor T4. The third-level signal VGH is transmitted through the fourth transistor T4 to the signal output terminal of the first gate signal generating circuit 10.

[0113] In summary, the gate driving signal generated by the first gate signal generating circuit 10 is an alternating second level signal VGL2 and a third level signal VGH, the second level signal VGL2 is a working level signal, and the third level signal VGH is a non-working level signal.

[0114] Furthermore, when the control signal MS is written as a high-level signal, the ninth transistor T9 is turned on and the tenth transistor T10 is turned off. Regardless of whether the gate drive signal is written as the first-level signal VGL1 or the third-level signal VGH, the first output selection sub-circuit 51 always outputs the second-level signal VGL2 flowing through the ninth transistor T9. After passing through the first NOT gate 61, this signal turns on the fourteenth transistor T14. The first NOT gate 61 then outputs the third-level signal VGH, i.e., the non-operating-level signal, indicating that the display is in partial display mode.

[0115] When the control signal MS is written as a low-level signal, the ninth transistor T9 is turned off and the tenth transistor T10 is turned on. When the gate drive signal is written as the third-level signal VGH, the eleventh transistor T11 is turned on, and the first output selection sub-circuit 51 outputs the second-level signal VGL2, which turns on the fourteenth transistor T14, and the first NOT gate 61 outputs the third-level signal VGH. When the gate drive signal is written as the first-level signal VGL1, the twelfth transistor T12 is turned on, and the third-level signal VGH is transmitted to the signal output terminal of the first output selection sub-circuit 51 through the tenth transistor T10 and the twelfth transistor T12. This signal turns on the thirteenth transistor T13, and the first NOT gate 61 outputs the first-level signal VGL1.

[0116] That is, when the control signal MS is written as a high-level signal, the display is in full-screen display mode, and when the control signal MS is written as a low-level signal, the display is in partial display mode. The first output selection sub-circuit 51 alternately outputs the second-level signal VGL2 and the third-level signal VGH in full-screen mode, and outputs the second-level signal VGL2 in partial display mode. The first NOT gate 61 alternately outputs the first-level signal VGL1 and the third-level signal VGH in full-screen display mode, and outputs the third-level signal VGH in partial display mode. In particular, when the display panel is in global display mode, the thirteenth transistor T13 is in an off state. However, at this time, the gate of the thirteenth transistor T13 is connected to the second-level signal VGL2 terminal and the drain is connected to the first-level signal VGL1 terminal. When the thirteenth transistor T13 experiences a negative bias, it may be mistakenly turned on, affecting the output of the first NOT gate 61. Therefore, in the present disclosure, the second-level signal VGL2 is set to be smaller than the first-level signal VGL1 to prevent the thirteenth transistor T13 from leaking and affecting the circuit output.

[0117] 3 , which shows a 0V leakage simulation result of the shift register, it can be seen that when the second level signal VGL2 is 2V lower than the first level signal VGL1 , the shift register has good leakage resistance and low power consumption.

[0118] Second example: As shown in FIG. 4-5 , the shift register of the second example includes a second gate signal output circuit 20 , a gating circuit 7 , a second output selection sub-circuit 52 and a second NOT gate 62 .

[0119] 4 , the second gate signal output circuit 20 includes a third input sub-circuit 13 , a fourth input sub-circuit 14 , a second voltage stabilizing sub-circuit 32 , a third control sub-circuit 23 , a fourth control sub-circuit 24 , a fifth control sub-circuit 25 , a sixth control sub-circuit 26 , a third output sub-circuit 43 and a fourth output sub-circuit 44 .

[0120] The third input sub-circuit 13 is configured to transmit the second level signal VGL2 to the fourth node N4 in response to the first clock signal CK. The fourth input sub-circuit 14 is configured to transmit the first selection signal Nscan[n-1] to the fifth node N5, the sixth node N6, and the seventh node N7 in response to the first clock signal CK and the second level signal VGL2. The second voltage stabilization sub-circuit 32 is configured to transmit the voltage of the fourth node N4 to the eighth node N8 in response to the second level voltage. The third control sub-circuit 23 is configured to transmit the first clock signal CK to the fourth node N4 in response to the voltage of the fifth node N5. The fourth control sub-circuit 24 is configured to transmit the voltage of the sixth node N6 to the seventh node N7 in response to the voltage of the fourth node N4, the voltage of the sixth node N6, and the voltage of the seventh node N7. The fifth control sub-circuit 25 is configured to transmit the second clock signal CB to the ninth node N9 in response to the voltage of the eighth node N8 and the second clock signal CB. The sixth control sub-circuit 26 and the fifth control sub-circuit 25 are configured to transmit the third level signal VGH to the fifth node N5 and the ninth node N9 in response to the voltage of the fifth node N5 and the fourth level signal. The third output sub-circuit 43 is configured to transmit the third level signal VGH to the signal output terminal of the second gate signal generating circuit 20 in response to the voltage of the ninth node N9. The fourth output sub-circuit 44 is configured to transmit the second level signal VGL2 to the signal output terminal of the second gate signal generating circuit 20 in response to the voltage of the seventh node N7.

[0121] It should be noted that the fourth node N4 is a connection node between the third input sub-circuit 13, the third control sub-circuit 23, and the second voltage stabilizing sub-circuit 32. The fifth node N5 is a connection node between the third control sub-circuit 23 and the fourth input sub-circuit 14. The sixth node N6 is a connection node between the fourth input sub-circuit 14 and the fourth control sub-circuit 24. The seventh node N7 is a connection node between the fourth input sub-circuit 14, the fourth control sub-circuit 24, and the fourth output sub-circuit 44. The eighth node N8 is a connection node between the second voltage stabilizing sub-circuit 32 and the fifth control sub-circuit 25. The ninth node N9 is a connection node between the fifth control sub-circuit 25 and the third output sub-circuit 43.

[0122] The shift register includes transistors 15 to 39, T15-T39. The 15-31 transistors T15-T31, the 33rd transistor T33, the 34th transistor T34, the 35th transistor T35, and the 39th transistor T39 are all P-type transistors, and the 32nd transistor T32, the 36th transistor T36, the 37th transistor T37, and the 38th transistor T38 are all N-type transistors. The third input sub-circuit 13 includes a 15th transistor T15. The control electrode of the 15th transistor T15 is connected to the first clock signal CK terminal, the first electrode is connected to the second level signal VGL2 terminal, and the second electrode is connected to the fourth node N4. When a low-level signal is written to the control electrode of the 15th transistor T15, the second transistor T2 writes to the fourth node N4 through the 15th transistor T15.

[0123] The fourth input sub-circuit 14 includes a sixteenth transistor T16, a seventeenth transistor T17, an eighteenth transistor T18, and a nineteenth transistor T19. The sixteenth transistor T16 has a control electrode connected to the first clock signal CK terminal, a first electrode connected to the first selection signal terminal, and a second electrode connected to the fifth node N5. The seventeenth transistor T17 has a control electrode connected to the second level signal VGL2 terminal, a first electrode connected to the fifth node N5, and a second electrode connected to the seventh node N7. The eighteenth transistor T18 has a first electrode connected to the first clock signal CK terminal, a first electrode connected to the first selection signal terminal, and a second electrode connected to the first electrode of the nineteenth transistor T19. The nineteenth transistor T19 has a control electrode connected to the second level signal VGL2 terminal, and a second electrode connected to the sixth node N6. When the control electrodes of the sixteenth transistor T16, the seventeenth transistor T17, the eighteenth transistor T18 and the nineteenth transistor T19 are all written with a low-level signal, the first selection signal Nscan[n-1] is transmitted to the fifth node N5, the sixth node N6 and the seventh node N7 through the sixteenth transistor T16, the seventeenth transistor T17, the eighteenth transistor T18 and the nineteenth transistor T19.

[0124] The second voltage stabilization sub-circuit 32 includes a twenty-third transistor T23. The twenty-third transistor T23 has a control electrode connected to the second level signal VGL2 terminal, a first electrode connected to the fourth node N4, and a second electrode connected to the eighth node N8. When a low-level signal is written to the control electrode of the twenty-third transistor T23, the voltage of the fourth node N4 is transmitted to the eighth node N8 through the twenty-third transistor T23.

[0125] The third control sub-circuit 23 includes a 20th transistor T20. The control electrode of the 20th transistor T20 is connected to the fifth node N5, the first electrode is connected to the fourth node N4, and the second electrode is connected to the first clock signal CK terminal. When a low-level signal is written to the control electrode of the 20th transistor T20, the first clock signal CK is written to the fourth node N4 via the 20th transistor T20. The fourth control sub-circuit 24 includes a 21st transistor T21, a 22nd transistor T22, a 29th transistor T29, and a fifth capacitor C5. The control electrode of the 21st transistor T21 is connected to the fourth node N4, the first electrode is connected to the third-level signal VGH terminal, and the second electrode is connected to the first electrode of the 22nd transistor T22. The control electrode of the 22nd transistor T22 is connected to the third node N3, and the second electrode is connected to the second clock signal CB terminal. The control electrode of the 29th transistor T29 is connected to the sixth node N6, the first electrode is connected to the seventh node N7, and the second electrode is connected to the sixth node N6. One electrode of the fifth capacitor C5 is connected to the second electrode of the 21st transistor T21, and the other electrode is connected to the sixth node N6. When low-level signals are written into the control electrodes of the twenty-first transistor T21 , the twenty-second transistor T22 , and the twenty-ninth transistor T29 , the voltage of the sixth node N6 is transmitted to the seventh node N7 through the fourth control sub-circuit 24 .

[0126] The fifth control sub-circuit 25 includes a twenty-fourth transistor T24, a twenty-fifth transistor T25, and a third capacitor C3. The control electrode of the twenty-fourth transistor T24 is connected to the eighth node N8, the first electrode is connected to the second clock signal CB terminal, and the second electrode is connected to the first electrode of the twenty-fifth transistor T25. The control electrode of the twenty-fifth transistor T25 is connected to the second clock signal CB terminal, and the second electrode is connected to the ninth node N9. One electrode of the third capacitor C3 is connected to the eighth node N8, and the other electrode is connected to the second electrode of the twenty-fourth transistor T24. When a low-level signal is written to the control electrodes of the twenty-fourth transistor T24 and the twenty-fifth transistor T25, the second clock signal CB is transmitted to the ninth node N9 through the fifth control sub-circuit 25.

[0127] The sixth control sub-circuit 26 and the fifth control sub-circuit 25 include a twenty-seventh transistor T27 and a twenty-eighth transistor T28. The twenty-seventh transistor T27 has a control electrode connected to the fifth node N5, a first electrode connected to the ninth node N9, and a second electrode connected to the third-level signal VGH terminal. The twenty-eighth transistor T28 has a control electrode connected to the fourth-level signal, a first electrode connected to the third-level signal VGH terminal, and a second electrode connected to the fifth node N5. When a low-level signal is written to the control electrodes of both the twenty-seventh transistor T27 and the twenty-eighth transistor T28, the third-level signal VGH is transmitted to the fifth node N5 and the ninth node N9 via the fifth control sub-circuit 25.

[0128] The third output sub-circuit 43 includes a twenty-sixth transistor T26 and a fourth capacitor C4. The control electrode of the twenty-sixth transistor T26 is connected to the ninth node N9, a first electrode is connected to the third level signal VGH terminal, and a second electrode is connected to the signal output terminal of the second gate signal generating circuit 20. One electrode of the fourth capacitor C4 is connected to the third level signal VGH terminal, and the other electrode is connected to the ninth node N9. When a low-level signal is written to the control electrode of the twenty-sixth transistor T26, the third level signal VGH is transmitted through the twenty-sixth transistor T26 to the signal output terminal of the second second gate signal generating circuit 20 for output.

[0129] The fourth output sub-circuit 44 includes a 30th transistor T30 and a seventh capacitor. The control electrode of the 30th transistor T30 is connected to the seventh node N7, a first electrode is connected to the signal output terminal of the second gate signal generating circuit 20, and a second electrode is connected to the second level signal terminal. One electrode of the seventh capacitor is connected to the second level signal terminal VGL2, and the other electrode is connected to the first electrode of the 30th transistor T30. When a low-level signal is written to the control electrode of the 30th transistor T30, the second level signal VGL2 is transmitted through the 30th transistor T30 to the signal output terminal of the second gate signal generating circuit 20 for output.

[0130] The gating circuit 7 is configured to output a second-level signal VGL2 or a third-level signal VGH in response to a first gating signal Nscan[n-1] and a second gating signal Nscan[n]. The gating circuit 7 includes a thirty-first transistor T31, a thirty-second transistor T32, a thirty-third transistor T33, and a sixth capacitor C6. The thirty-first transistor T31 has a control electrode connected to the fourth-level signal, a first electrode connected to the third-level signal VGH, and a second electrode connected to the signal output terminal of the gating circuit 7. The thirty-second transistor T32 has a control electrode connected to the first gating signal Nscan[n-1] terminal, a first electrode connected to the signal output terminal of the gating circuit 7, and a second electrode connected to the first electrode of the thirty-third transistor T33. The thirty-third transistor T33 has a control electrode connected to the second gating signal Nscan[n] terminal, and a second electrode connected to the control signal MS terminal. One electrode of the sixth capacitor C6 is connected to the second-level signal VGL2, and the other electrode is connected to the signal output terminal of the gating circuit 7. The first selection signal Nscan[n−1] is delayed by 1H compared to the second selection signal Nscan[n]. That is, the control signal MS can be transmitted to the second output selection sub-circuit 52 for only 1H.

[0131] The second output selection sub-circuit 52 includes a 34th transistor T34, a 35th transistor T35, a 36th transistor T36, and a 37th transistor T37. The 34th and 35th transistors T34 and T35 are both P-type transistors, while the 36th and 37th transistors T36 and T37 are both N-type transistors. The 34th transistor T34 has a control electrode connected to the signal output terminal of the second gate signal generating circuit 20, a first electrode connected to the third level signal VGH terminal, and a second electrode connected to the signal output terminal of the second output selection sub-circuit 52. The 35th transistor T35 has a control electrode connected to the signal output terminal of the strobe circuit 7, a first electrode connected to the third level signal VGH terminal, and a second electrode connected to the signal output terminal of the second output selection sub-circuit 52. The 36th transistor T36 has a control electrode connected to the signal output terminal of the second gate signal generating circuit 20, a first electrode connected to the signal output terminal of the second output selection sub-circuit 52, and a second electrode connected to the first electrode of the 37th transistor T37. The 37th transistor T37 has a control electrode connected to the signal output terminal of the strobe circuit 7, and a second electrode connected to the first level signal VGL1 terminal.

[0132] The second NOT gate 62 includes a 38th transistor T38 and a 39th transistor T39. The 38th transistor T38 has a control electrode connected to the signal output terminal of the second output selection sub-circuit 52, a first electrode connected to the signal output terminal of the second NOT gate 62, and a second electrode connected to the first level signal VGL1. The 39th transistor T39 has a control electrode connected to the signal output terminal of the second output selection sub-circuit 52, a first electrode connected to the third level signal VGH, and a second electrode connected to the signal output terminal of the second NOT gate 62.

[0133] The following is the working process of the second gate signal generating circuit 20 of the second embodiment.

[0134] In the first phase, a low-level signal is written into the first clock signal CK, a high-level signal is written into the second clock signal CB, a high-level signal is written into the input signal STV, and the second gate signal output circuit outputs a low-level signal.

[0135] In the second phase, a high level signal is written into the first clock signal CK, a low level signal is written into the second clock signal CB, a high level signal is written into the input signal STV, and the second gate signal output circuit outputs a high level signal.

[0136] In the third phase, a low-level signal is written into the first clock signal CK, a high-level signal is written into the second clock signal CB, a high-level signal is written into the input signal STV, and the second gate signal output circuit outputs a high-level signal.

[0137] In summary, the gate driving signal generated by the second gate signal generating circuit 20 is the second level signal VGL2 and the third level signal VGH alternately.

[0138] Furthermore, when the selection circuit 7 outputs the second-level signal VGL2, the 35th transistor T35 is turned on and the 37th transistor T37 is turned off. Regardless of whether the gate drive signal is the second-level signal VGL2 or the third-level signal VGH, the second output selection sub-circuit 52 always outputs the third-level signal VGH flowing through the 35th transistor T35. After passing through the second NOT gate 62, this signal turns on the 38th transistor T38. The second NOT gate 62 then outputs the first-level signal VGL1, i.e., the non-operating level signal, indicating that the display is in partial display mode.

[0139] When the gate circuit 7 outputs the third-level signal VGH, the 35th transistor T35 is turned off and the 37th transistor T37 is turned on. When the gate drive signal is written as the second-level signal VGL2, the 34th transistor T34 is turned on, the second output selection sub-circuit 52 outputs the third-level signal VGH, which turns on the 38th transistor T38, and the second NOT gate 62 outputs the first-level signal VGL1. When the gate drive signal is written as the third-level signal VGH, the 36th transistor T36 is turned on, the second output selection sub-circuit 52 outputs the first-level signal VGL1, which turns on the 39th transistor T39, and the second NOT gate 62 outputs the third-level signal VGH.

[0140] That is, when the gating circuit 7 outputs the second-level signal VGL2 to the second output selection sub-circuit 52, the display is in full-screen display mode. When the gating circuit 7 outputs the third-level signal VGH to the second output selection sub-circuit 52, the display is in partial display mode. The second output selection sub-circuit 52 alternately outputs the first-level signal VGL1 and the third-level signal VGH in full-screen mode, and outputs the first-level signal VGL1 in partial display mode. The second NOT gate 62 alternately outputs the first-level signal VGL1 and the third-level signal VGH in full-screen mode, and outputs the third-level signal VGH in partial display mode. The third-level signal VGH is the operating level signal of the gate drive signal, and the second-level signal VGL2 is the non-operating level signal of the gate drive signal.

[0141] In particular, when the display panel is in partial display mode, that is, when the gating circuit 7 outputs the third-level signal VGH, the thirty-seventh transistor T37 is turned on. When the gate drive signal is written with the second-level signal VGL2, the thirty-sixth transistor T36 should be turned off. However, when the threshold voltage of the thirty-sixth transistor T36 exhibits a negative bias, it may be mistakenly turned on, causing the first-level signal VGL1 to be transmitted to the second NOT gate 62, affecting the output. Therefore, in the second embodiment, the second-level signal VGL2 is set to be smaller than the first-level signal VGL1 to prevent leakage and affect circuit reliability.

[0142] 6 , which is a diagram showing simulation results of the shift register of the second example, it can be seen from the figure that the output of the shift register after improving the leakage condition has no horizontal stripes and has a lower step.

[0143] In a second aspect, the present disclosure provides a display panel comprising the shift register of any of the aforementioned embodiments. The display panel can be a display component of any display device with a display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigation system. Therefore, it has low power consumption and good leakage resistance.

[0144] It will be understood that the above embodiments are merely exemplary embodiments for illustrating the principles of the present invention, and the present invention is not limited thereto. Those skilled in the art will appreciate that various modifications and improvements can be made without departing from the spirit and substance of the present invention, and such modifications and improvements are also considered to be within the scope of protection of the present invention.

Claims

1. A shift register, which is applied to a display panel. The display panel has a full-screen display mode and a partial display mode. The shift register includes: A gate signal generation circuit configured to generate a gate driving signal; An output selection circuit configured to output the gate driving signal in the full-screen display mode and output a non-operating level signal in the partial display mode under the control of a control signal.

2. The shift register according to claim 1, wherein The output selection circuit includes: A first output selection sub-circuit configured to alternately output a second level signal and a third level signal in the full-screen mode in response to the gate driving signal and the control signal, and output the second level signal in the partial display mode; A first NOT gate configured to alternately output a first level signal and the third level signal in the full-screen mode and output the third level signal in the partial mode; the first level signal is the operating level signal of the gate driving signal, and the third level signal is the non-operating level signal of the gate driving signal; The first level signal is greater than the second level signal.

3. The shift register according to claim 2, wherein, The first output selection sub-circuit includes: a ninth transistor, a tenth transistor, an eleventh transistor, and a twelfth transistor; The control electrode of the ninth transistor is connected to the control signal terminal, the first electrode is connected to the signal output terminal of the first output selection sub-circuit, and the second electrode is connected to the second level signal terminal; The control electrode of the tenth transistor is connected to the control signal terminal, the first electrode is connected to the third level signal terminal, and the second electrode is connected to the first electrode of the twelfth transistor; The control electrode of the eleventh transistor is connected to the signal output terminal of the gate signal generation circuit, the first electrode is connected to the signal output terminal of the first output selection sub-circuit, and the second electrode is connected to the second level signal terminal; The control electrode of the twelfth transistor is connected to the signal output terminal of the gate signal generation circuit, the first electrode is connected to the second electrode of the tenth transistor, and the second electrode is connected to the signal output terminal of the first output selection sub-circuit.

4. The shift register according to claim 2, wherein The first NOT gate includes: a thirteenth transistor and a fourteenth transistor; The connection node of the control electrode of the thirteenth transistor and the control electrode of the fourteenth transistor is multiplexed as the signal input terminal of the first NOT gate and is connected to the signal output terminal of the first output selection sub-circuit; the first electrode of the thirteenth transistor and the second electrode of the fourteenth transistor are multiplexed as the signal output terminal of the first NOT gate; The second electrode of the thirteenth transistor is connected to the first level signal terminal; the first electrode of the fourteenth transistor is connected to the third level signal terminal.

5. The shift register according to claim 1, wherein, The output selection circuit includes: A second output selection sub-circuit configured to alternately output a first level signal and a third level signal in the full-screen mode in response to the gate driving signal and the control signal, and output the first level signal in the partial mode; A second NOT gate configured to alternately output the first level signal and the third level signal in the full-screen mode and output the third level signal in the partial mode; the third level signal is the operating level signal of the gate driving signal, and the second level signal is the non-operating level signal of the gate driving signal; The polarities of the first level signal and the second level signal are the same; the first level signal is greater than the second level signal.

6. The shift register according to claim 5, wherein, The second output selection sub-circuit includes: a thirty-fourth transistor, a thirty-fifth transistor, a thirty-sixth transistor, and a thirty-seventh transistor; where The control electrode of the thirty-fourth transistor is connected to the signal output terminal of the gate signal generation circuit, the first electrode is connected to the third level signal terminal, and the second electrode is connected to the signal output terminal of the second output selection sub-circuit; The control electrode of the thirty-fifth transistor is connected to the signal output terminal of the gating circuit, the first electrode is connected to the third level signal terminal, and the second electrode is connected to the signal output terminal of the second output selection sub-circuit; The control electrode of the thirty-sixth transistor is connected to the signal output terminal of the gate signal generation circuit, the first electrode is connected to the signal output terminal of the second output selection sub-circuit, and the second electrode is connected to the first electrode of the thirty-seventh transistor; The control electrode of the thirty-seventh transistor is connected to the signal output terminal of the gating circuit, and the second electrode is connected to the first level signal terminal.

7. The shift register according to claim 5, wherein, The second NOT gate includes: a thirty-eighth transistor and a thirty-ninth transistor; The control electrode of the thirty-eighth transistor is connected to the signal output terminal of the second output selection sub-circuit, the first electrode is connected to the signal output terminal of the second NOT gate, and the second electrode is connected to the first level signal terminal; The control electrode of the thirty-ninth transistor is connected to the signal output terminal of the second output selection sub-circuit, the first electrode is connected to the third level signal terminal, and the second electrode is connected to the signal output terminal of the second NOT gate.

8. The shift register according to any one of claims 2-4, wherein The first gate signal generation circuit includes a first input sub-circuit, a second input sub-circuit, a first control sub-circuit, a second control sub-circuit, a first voltage stabilization sub-circuit, a first output sub-circuit, and a second output sub-circuit; where The first input sub-circuit is configured to transmit an input signal to a second node in response to a first clock signal; the second node is the connection node of the first input sub-circuit, the first control sub-circuit, the second control sub-circuit, and the first voltage stabilization sub-circuit; The second input sub-circuit is configured to transmit a second level signal to a first node in response to the first clock signal; the first node is the connection node of the second input sub-circuit, the first control sub-circuit, the second control sub-circuit, and the first output sub-circuit; The first control sub-circuit is configured to transmit the first clock signal to the first node in response to the voltage of the second node; The second control sub-circuit is configured to transmit the third level signal to the second node in response to the voltage of the first node and a second clock signal; The first voltage stabilization sub-circuit is configured to transmit the voltage of the second node to a third node in response to the second level signal; the third node is the connection node of the voltage stabilization sub-circuit and the second output sub-circuit; The first output sub-circuit is configured to transmit the third level signal to the signal output terminal of the first gate signal generation circuit for output in response to the voltage of the first node; The second output sub - circuit is configured to transmit the second clock signal to the signal output terminal of the first gate signal generation circuit for output in response to the voltage of the third node.

9. The display panel according to claim 8, wherein, The first input sub - circuit includes a first transistor; the control electrode of the first transistor is connected to the first clock signal terminal, the first pole is connected to the input signal terminal, and the second pole is connected to the second node.

10. The display panel according to claim 8, wherein, The second input sub - circuit includes a third transistor; the control electrode of the third transistor is connected to the first clock signal terminal, the first pole is connected to the second - level signal terminal, and the second pole is connected to the first node.

11. The display panel according to claim 8, wherein, The first control sub - circuit includes a second transistor; the control electrode of the second transistor is connected to the second node, the first pole is connected to the first node, and the second pole is connected to the first clock signal terminal.

12. The display panel according to claim 8, wherein, The second control sub - circuit includes a sixth transistor and a seventh transistor; the control electrode of the sixth transistor is connected to the second node, the first pole is connected to the third - level signal terminal, and the second pole is connected to the first pole of the seventh transistor; the control electrode of the seventh transistor is connected to the second clock signal terminal, the first pole is connected to the second pole of the sixth transistor, and the second pole is connected to the second node.

13. The display panel according to claim 8, wherein, The first voltage - stabilizing sub - circuit includes an eighth transistor; the control electrode of the eighth transistor is connected to the second - level signal terminal, the first pole is connected to the second node, and the second pole is connected to the third node.

14. The display panel according to claim 8, wherein, The first output sub - circuit includes a fourth transistor and a first capacitor; the control electrode of the fourth transistor is connected to the first node, the first pole is connected to the third - level signal terminal, and the second pole is connected to the signal output terminal of the first gate signal generation circuit; one pole of the first capacitor is connected to the first node, and the other pole is connected to the third - level signal terminal.

15. The display panel according to claim 8, wherein, The second output sub - circuit includes a fifth transistor and a second capacitor; the control electrode of the fifth transistor is connected to the third node, the first pole is connected to the signal output terminal of the first gate driving circuit, and the second pole is connected to the second clock signal terminal; one pole of the second capacitor is connected to the third node, and the other pole is connected to the signal output terminal of the first gate signal generation circuit.

16. The shift register according to any one of claims 5-7, wherein, The second gate signal generation circuit includes a third input sub - circuit, a fourth input sub - circuit, a second voltage - stabilizing sub - circuit, a third control sub - circuit, a fourth control sub - circuit, a fifth control sub - circuit, a sixth control sub - circuit, a third output sub - circuit, and a fourth output sub - circuit; wherein, The third input sub - circuit is configured to transmit a second - level signal to a fourth node in response to a first clock signal; the fourth node is the connection node of the third input sub - circuit, the third control sub - circuit, and the second voltage - stabilizing sub - circuit. The fourth input sub - circuit is configured to transmit a first strobe signal to a fifth node, a sixth node, and a seventh node in response to the first clock signal and the second level signal; the fifth node is the connection node between the third control sub - circuit and the fourth input sub - circuit; the sixth node is the connection node between the fourth input sub - circuit and the fourth control sub - circuit; the seventh node is the connection node between the fourth input sub - circuit, the fourth control sub - circuit, and the fourth output sub - circuit; The second voltage - stabilizing sub - circuit is configured to transmit the voltage of the fourth node to an eighth node in response to the second level signal; the eighth node is the connection node between the second voltage - stabilizing sub - circuit and the fifth control sub - circuit; The third control sub - circuit is configured to transmit the first clock signal to the fourth node in response to the voltage of the fifth node; The fourth control sub - circuit is configured to transmit the voltage of the sixth node to the seventh node in response to the voltage of the fourth node, the voltage of the sixth node, and the voltage of the seventh node; The fifth control sub - circuit is configured to transmit the second clock signal to a ninth node in response to the voltage of the eighth node and the second clock signal terminal; the ninth node is the connection node between the fifth control sub - circuit and the third output sub - circuit; The sixth control sub - circuit is configured to transmit the third level signal to the fifth node and the ninth node in response to the voltage of the fifth node and the fourth level signal; The third output sub - circuit is configured to transmit the third level signal to the signal output terminal of the second gate signal generation circuit in response to the voltage of the ninth node; The fourth output sub - circuit is configured to transmit the second level signal to the signal output terminal of the second gate signal generation circuit in response to the voltage of the seventh node.

17. The display panel according to claim 16, wherein, The third input sub - circuit includes a fifteenth transistor; the control electrode of the fifteenth transistor is connected to the first clock signal terminal, the first electrode is connected to the second level signal terminal, and the second electrode is connected to the fourth node.

18. The display panel according to claim 16, wherein, The fourth input sub - circuit includes a sixteenth transistor, a seventeenth transistor, an eighteenth transistor, and a nineteenth transistor; The control electrode of the sixteenth transistor is connected to the first clock signal terminal, the first electrode is connected to the first strobe signal terminal, and the second electrode is connected to the fifth node; the control electrode of the seventeenth transistor is connected to the second level signal terminal, the first electrode is connected to the fifth node, and the second electrode is connected to the seventh node; The first electrode of the eighteenth transistor is connected to the first clock signal terminal, the first electrode is connected to the first strobe signal terminal, and the second electrode is connected to the first electrode of the nineteenth transistor; the control electrode of the nineteenth transistor is connected to the second level signal terminal, and the second electrode is connected to the sixth node.

19. The display panel according to claim 16, wherein, The second voltage - stabilizing sub - circuit includes a twenty - third transistor; the control electrode of the twenty - third transistor is connected to the second level signal terminal, the first electrode is connected to the fourth node, and the second electrode is connected to the eighth node.

20. The display panel according to claim 16, wherein, The third control sub-circuit includes a twentieth transistor; a control electrode of the twentieth transistor is connected to the fifth node, a first electrode is connected to the fourth node, and a second electrode is connected to the first clock signal terminal.

21. The display panel according to claim 16, wherein The fourth control sub-circuit includes a twenty-first transistor, a twenty-second transistor, a twenty-ninth transistor, and a fifth capacitor; The control electrode of the twenty-first transistor is connected to the fourth node, the first electrode is connected to the third-level signal terminal, and the second electrode is connected to the first electrode of the twenty-second transistor; the control electrode of the twenty-second transistor is connected to the third node, the second electrode is connected to the second clock signal terminal; the control electrode of the twenty-ninth transistor is connected to the sixth node, the first electrode is connected to the seventh node, and the second electrode is connected to the sixth node; one electrode of the fifth capacitor is connected to the second electrode of the twenty-first transistor, and the other electrode is connected to the sixth node.

22. The display panel according to claim 16, wherein, The fifth control sub-circuit includes a twenty-fourth transistor, a twenty-fifth transistor, and a third capacitor; The control electrode of the twenty-fourth transistor is connected to the eighth node, the first electrode is connected to the second clock signal terminal, and the second electrode is connected to the first electrode of the twenty-fifth transistor; the control electrode of the twenty-fifth transistor is connected to the second clock signal terminal, and the second electrode is connected to the ninth node; one electrode of the third capacitor is connected to the eighth node, and the other electrode is connected to the second electrode of the twenty-fourth transistor.

23. The display panel according to claim 16, wherein, The sixth control sub-circuit includes a twenty-seventh transistor and a twenty-eighth transistor; The control electrode of the twenty-seventh transistor is connected to the fifth node, the first electrode is connected to the ninth node, and the second electrode is connected to the third-level signal terminal; The control electrode of the twenty-eighth transistor is connected to the fourth-level signal, the first electrode is connected to the third-level signal terminal, and the second electrode is connected to the fifth node.

24. The display panel according to claim 16, wherein, The third output sub-circuit includes a twenty-sixth transistor and a fourth capacitor; The control electrode of the twenty-sixth transistor is connected to the ninth node, the first electrode is connected to the third-level signal terminal, and the second electrode is connected to the signal output terminal of the second gate signal generation circuit; one electrode of the fourth capacitor is connected to the third-level signal terminal, and the other electrode is connected to the ninth node.

25. The display panel according to claim 16, wherein, The fourth output sub-circuit includes a thirtieth transistor and a seventh capacitor; The control electrode of the thirtieth transistor is connected to the seventh node, the first electrode is connected to the signal output terminal of the second gate signal generation circuit, and the second electrode is connected to the second-level signal terminal; one electrode of the seventh capacitor is connected to the second-level signal terminal, and the other electrode is connected to the first electrode of the thirtieth transistor; The signal output terminal of the second gate signal generation circuit outputs a second gating signal.

26. The shift register according to claim 16, wherein, It further includes a gating circuit; the signal output terminal of the gating circuit is connected to the second output selection sub-circuit; The gating circuit is configured to output the second-level signal or the third-level signal in response to the first gating signal and the second gating signal.

27. [Corrected according to Rule 91 on 19.02.2024] The display panel according to claim 26, wherein, The gating circuit includes a thirty-first transistor, a thirty-second transistor, a thirty-third transistor, and a sixth capacitor; The control electrode of the thirty-first transistor is connected to the fourth-level signal, the first electrode is connected to the third-level signal, and the second electrode is connected to the signal output terminal of the strobe circuit; The control electrode of the thirty-second transistor is connected to the first strobe signal terminal, the first electrode is connected to the signal output terminal of the strobe circuit, and the second electrode is connected to the first electrode of the thirty-third transistor; The control electrode of the thirty-third transistor is connected to the second strobe signal terminal, and the second electrode is connected to the control signal terminal; One electrode of the sixth capacitor is connected to the second-level signal, and the other electrode is connected to the signal output terminal of the strobe circuit.

28. [Corrected according to Rule 91 on 19.02.2024] The shift register according to claim 1, wherein, It further includes a plurality of pixel units; the pixel units are connected to the shift registers in a one-to-one correspondence.

29. [Corrected according to Rule 91 on 19.02.2024] A display panel, which includes the shift register according to any one of claims 1-28.

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