Shift register unit and driving method therefor, and emission driving circuit and display apparatus

Abstract

Provided are a shift register unit and a driving method therefor, and an emission driving circuit and a display apparatus, which belong to the technical field of display. In the shift register unit, an input circuit can respectively control the potentials of two pull-up nodes under the control of signal terminals such as a first clock terminal, a second clock terminal, a first power supply terminal, a second power supply terminal, a start terminal and a pull-down terminal; a pull-down circuit can control the potential of a pull-down node under the control of the potentials of the two pull-up nodes and of signal terminals such as a third clock terminal, a first reset terminal and a second reset terminal; and under the control of the potentials of the two pull-up nodes, an output circuit can control a pull-up terminal to transmit a pull-up signal to an output terminal, and under the control of the potential of the pull-down node, the output circuit can control the pull-down terminal to transmit a pull-down signal to the output terminal. In this way, an output signal can be reliably adjusted by means of flexibly setting a signal provided by each signal terminal, thereby avoiding the problem of output stability being relatively poor due to a characteristic offset of transistors in each circuit.

Description

Shift register unit and driving method thereof, light emitting driving circuit, and display device

[0001] This disclosure claims priority to Chinese patent application number 202410009714.2, filed on January 2, 2024, entitled “Shift register unit and driving method thereof, light-emitting driving circuit, and display device,” the entire contents of which are incorporated by reference into this disclosure. Technical Field

[0002] The present disclosure relates to the field of display technology, and in particular to a shift register unit and a driving method thereof, a light-emitting driving circuit, and a display device. Background Art

[0003] The light-emitting driving circuit is coupled to a pixel circuit in a display panel and is used to provide a light-emitting control signal for the pixel circuit to drive the coupled light-emitting element to emit light.

[0004] In related technologies, gate drive on array (GOA) technology is often used to integrate emmission (EM) drive circuits on display panels to facilitate narrow-frame designs for display devices. Similar to gate drive circuits, current EM drive circuits typically include multiple cascaded EM GOA units, referred to as EOA units (also known as shift register units). Furthermore, the EOA units in the EM drive circuits typically include multiple N-type transistors made of oxide materials or multiple P-type transistors made of polysilicon (Poly-Si) materials.

[0005] Summary of the Invention

[0006] Provided are a shift register unit and a driving method thereof, a light-emitting driving circuit, and a display device. The technical solution is as follows:

[0007] In one aspect, a shift register unit is provided, comprising:

[0008] an input circuit, coupled to a first clock terminal, a second clock terminal, a first power terminal, a second power terminal, a starting terminal, a pull-down terminal, a first pull-up node, and a second pull-up node, respectively, for controlling the connection and disconnection between the starting terminal and the first pull-up node in response to a first clock signal provided by the first clock terminal, controlling the connection and disconnection between the pull-down terminal and the first pull-up node in response to a second power signal provided by the second power terminal, and adjusting the potential of the first pull-up node based on the first power signal provided by the first power terminal; and controlling the connection and disconnection between the starting terminal and the second pull-up node in response to a second clock signal provided by the second clock terminal, controlling the connection and disconnection between the pull-down terminal and the second pull-up node in response to the first power signal, and adjusting the potential of the second pull-up node based on the second power signal;

[0009] a pull-down circuit, coupled to a third clock terminal, the first pull-up node, the second pull-up node, the pull-down terminal, a first reset terminal, a second reset terminal, and the pull-down node, respectively, for controlling connection and disconnection between the third clock terminal and the pull-down node in response to a third clock signal provided by the third clock terminal, a first reset signal provided by the first reset terminal, and a second reset signal provided by the second reset terminal, controlling connection and disconnection between the pull-down terminal and the pull-down node in response to a potential of the first pull-up node, and controlling connection and disconnection between the pull-down terminal and the pull-down node in response to a potential of the second pull-up node;

[0010] The output circuit is coupled to the first pull-up node, the second pull-up node, the pull-down node, the pull-up end, the pull-down end and the output end, respectively, and is used to control the connection and disconnection between the pull-up end and the output end in response to the potential of the first pull-up node, control the connection and disconnection between the pull-up end and the output end in response to the potential of the second pull-up node, and control the connection and disconnection between the pull-down end and the output end in response to the potential of the pull-down node.

[0011] Optionally, the input circuit includes:

[0012] a first input sub-circuit, coupled to the first clock terminal, the first power terminal, the second power terminal, the starting terminal, the pull-down terminal, and the first pull-up node, respectively, for controlling the connection and disconnection between the starting terminal and the first pull-up node in response to the first clock signal, controlling the connection and disconnection between the pull-down terminal and the first pull-up node in response to the second power signal, and adjusting the potential of the first pull-up node based on the first power signal;

[0013] The second input sub-circuit is coupled to the second clock terminal, the first power terminal, the second power terminal, the starting terminal, the pull-down terminal and the second pull-up node, respectively, and is used to control the connection and disconnection between the starting terminal and the second pull-up node in response to the second clock signal, control the connection and disconnection between the pull-down terminal and the second pull-up node in response to the first power signal, and adjust the potential of the second pull-up node based on the second power signal.

[0014] Optionally, the first input sub-circuit includes: a first transistor, a second transistor and a first capacitor;

[0015] The gate of the first transistor is coupled to the first clock terminal, the first electrode of the first transistor is coupled to the starting terminal, and the second electrode of the first transistor is coupled to the first pull-up node;

[0016] The gate of the second transistor is coupled to the second power supply terminal, the first electrode of the second transistor is coupled to the pull-down terminal, and the second electrode of the second transistor is coupled to the first pull-up node;

[0017] A first terminal of the first capacitor is coupled to the first power supply terminal, and a second terminal of the first capacitor is coupled to the first pull-up node.

[0018] Optionally, the second input sub-circuit includes: a third transistor, a fourth transistor and a second capacitor;

[0019] The gate of the third transistor is coupled to the second clock terminal, the first electrode of the third transistor is coupled to the starting terminal, and the second electrode of the third transistor is coupled to the second pull-up node;

[0020] The gate of the fourth transistor is coupled to the first power supply terminal, the first electrode of the fourth transistor is coupled to the pull-down terminal, and the second electrode of the fourth transistor is coupled to the second pull-up node;

[0021] A first terminal of the second capacitor is coupled to the second power supply terminal, and a second terminal of the second capacitor is coupled to the second pull-up node.

[0022] Optionally, the pull-down circuit includes:

[0023] a pull-down control subcircuit, coupled to the third clock terminal, the first reset terminal, the second reset terminal, the pull-down terminal, and the pull-down control node, respectively, for controlling the connection between the pull-down terminal and the pull-down control node in response to the first reset signal and the second reset signal, and adjusting the potential of the pull-down control node based on the third clock signal;

[0024] The pull-down sub-circuit is coupled to the pull-down control node, the third clock terminal, the first pull-up node, the second pull-up node, the pull-down node and the pull-down terminal, respectively, and is used to control the connection and disconnection between the third clock terminal and the pull-down node in response to the potential of the pull-down control node, control the connection and disconnection between the pull-down terminal and the pull-down node in response to the potential of the first pull-up node, and control the connection and disconnection between the pull-down terminal and the pull-down node in response to the potential of the second pull-up node.

[0025] Optionally, the pull-down control subcircuit includes: a fifth transistor, a sixth transistor and a third capacitor;

[0026] The gate of the fifth transistor is coupled to the first reset terminal, the first electrode of the fifth transistor is coupled to the pull-down terminal, and the second electrode of the fifth transistor is coupled to the pull-down control node;

[0027] The gate of the sixth transistor is coupled to the second reset terminal, the first electrode of the sixth transistor is coupled to the pull-down terminal, and the second electrode of the sixth transistor is coupled to the pull-down control node;

[0028] A first terminal of the third capacitor is coupled to the third clock terminal, and a second terminal of the third capacitor is coupled to the pull-down control node.

[0029] Optionally, the pull-down sub-circuit includes: a seventh transistor, an eighth transistor and a ninth transistor;

[0030] The gate of the seventh transistor is coupled to the pull-down control node, the first electrode of the seventh transistor is coupled to the third clock terminal, and the second electrode of the seventh transistor is coupled to the pull-down node;

[0031] The gate of the eighth transistor is coupled to the first pull-up node, the first electrode of the eighth transistor is coupled to the pull-down terminal, and the second electrode of the eighth transistor is coupled to the pull-down node;

[0032] A gate of the ninth transistor is coupled to the second pull-up node, a first electrode of the ninth transistor is coupled to the pull-down terminal, and a second electrode of the ninth transistor is coupled to the pull-down node.

[0033] Optionally, the output circuit includes:

[0034] a first output sub-circuit, coupled to the first pull-up node, the pull-up terminal, and the output terminal, respectively, for controlling the connection and disconnection between the pull-up terminal and the output terminal in response to the potential of the first pull-up node;

[0035] a second output sub-circuit, coupled to the second pull-up node, the pull-up terminal, and the output terminal, respectively, for controlling the connection and disconnection between the pull-up terminal and the output terminal in response to the potential of the second pull-up node;

[0036] The third output sub-circuit is coupled to the pull-down node, the pull-down end and the output end respectively, and is used to control the connection and disconnection of the pull-down end and the output end in response to the potential of the pull-down node.

[0037] Optionally, the first output sub-circuit includes: a tenth transistor and a fourth capacitor;

[0038] The gate of the tenth transistor is coupled to the first pull-up node, the first electrode of the tenth transistor is coupled to the pull-up terminal, and the second electrode of the tenth transistor is coupled to the output terminal;

[0039] A first terminal of the fourth capacitor is coupled to the first pull-up node, and a second terminal of the fourth capacitor is coupled to the output terminal.

[0040] Optionally, the second output sub-circuit includes: an eleventh transistor and a fifth capacitor;

[0041] The gate of the eleventh transistor is coupled to the second pull-up node, the first electrode of the eleventh transistor is coupled to the pull-up terminal, and the second electrode of the eleventh transistor is coupled to the output terminal;

[0042] A first terminal of the fifth capacitor is coupled to the second pull-up node, and a second terminal of the fifth capacitor is coupled to the output terminal.

[0043] Optionally, the third output sub-circuit includes: a twelfth transistor and a sixth capacitor;

[0044] The gate of the twelfth transistor is coupled to the pull-down node, the first electrode of the twelfth transistor is coupled to the pull-down terminal, and the second electrode of the twelfth transistor is coupled to the output terminal;

[0045] A first terminal of the sixth capacitor is coupled to the pull-down node, and a second terminal of the sixth capacitor is coupled to the pull-down terminal.

[0046] Optionally, the twelfth transistor includes: two transistors connected in series between the output end and the pull-down end.

[0047] Optionally, the shift register unit further includes:

[0048] An anti-leakage circuit is coupled to the first pull-up node, the second pull-up node, the pull-up end, and the series node of two transistors connected in series among the twelfth transistor, respectively, and is used to control the on-off connection between the pull-up end and the series node in response to the potential of the first pull-up node, and to control the on-off connection between the pull-up end and the series node in response to the potential of the second pull-up node.

[0049] Optionally, the leakage prevention circuit includes: a thirteenth transistor and a fourteenth transistor;

[0050] The gate of the thirteenth transistor is coupled to the first pull-up node, the first electrode of the thirteenth transistor is coupled to the pull-up terminal, and the second electrode of the thirteenth transistor is coupled to the series node;

[0051] A gate of the fourteenth transistor is coupled to the second pull-up node, a first electrode of the fourteenth transistor is coupled to the pull-up terminal, and a second electrode of the fourteenth transistor is coupled to the series node.

[0052] Optionally, the output end is used to couple to a light emitting control end of a pixel circuit.

[0053] Optionally, each transistor in the shift register unit includes: an N-type transistor.

[0054] Optionally, the material of the N-type transistor includes: oxide material.

[0055] In another aspect, a method for driving a shift register unit is provided. The method is used to drive the shift register unit according to the above aspect, and the method includes:

[0056] In a first stage, the potential of the first power signal provided by the first power supply terminal and the potential of the first clock signal provided by the first clock terminal are both the first potential, and the potential of the second power signal provided by the second power supply terminal and the potential of the second clock signal provided by the second clock terminal are both the second potential; the input circuit controls the start terminal to be conductive with the first pull-up node in response to the first clock signal, and controls the pull-down terminal to be conductive with the second pull-up node in response to the first power signal, and the potential of the start signal provided by the start terminal is the first potential; the pull-down circuit controls the pull-down terminal to be conductive with the pull-down node in response to the potential of the first pull-up node; and the output circuit controls the pull-up terminal to be conductive with the output terminal in response to the potential of the first pull-up node;

[0057] In the second stage, the potential of the second power supply signal and the potential of the second clock signal are the first potential, and the potential of the first power supply signal and the potential of the first clock signal are the second potential; the input circuit controls the starting end to be connected to the second pull-up node in response to the second clock signal, and controls the pull-down end to be connected to the first pull-up node in response to the second power supply signal, and the potential of the starting signal is the second potential; the pull-down circuit controls the third clock end to be connected to the pull-down node in response to the third clock signal provided by the third clock end, and the potential of the third clock signal is the first potential; the output circuit controls the pull-down end to be connected to the output end in response to the potential of the pull-down node.

[0058] In yet another aspect, a light-emitting driving circuit is provided, comprising: at least two cascaded shift register units as described in the above aspect.

[0059] In another aspect, a display device is provided, comprising: a display panel, and the light-emitting driving circuit according to the above-mentioned aspect; the display panel comprises a plurality of pixels; the pixels comprise a pixel circuit and a light-emitting element;

[0060] The light-emitting driving circuit is coupled to the pixel circuit and is used to transmit a light-emitting driving signal to the pixel circuit;

[0061] The pixel circuit is further coupled to the light emitting element and is configured to drive the light emitting element to emit light in response to the light emitting control signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0062] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0063] FIG1 is a schematic structural diagram of a shift register unit provided by an embodiment of the present disclosure;

[0064] FIG2 is a schematic structural diagram of another shift register unit provided by an embodiment of the present disclosure;

[0065] FIG3 is a schematic structural diagram of another shift register unit provided by an embodiment of the present disclosure;

[0066] FIG4 is a schematic structural diagram of another shift register unit provided by an embodiment of the present disclosure;

[0067] FIG5 is a schematic diagram of a circuit structure of a shift register unit provided by an embodiment of the present disclosure;

[0068] FIG6 is a schematic diagram of the circuit structure of another shift register unit provided by an embodiment of the present disclosure;

[0069] FIG7 is a schematic structural diagram of a pixel circuit provided by an embodiment of the present disclosure;

[0070] FIG8 is a signal timing diagram of a pixel circuit provided by an embodiment of the present disclosure;

[0071] FIG9 is a flow chart of a driving method of a shift register unit provided in an embodiment of the present disclosure;

[0072] FIG10 is a schematic diagram of a signal timing sequence of a shift register unit provided by an embodiment of the present disclosure;

[0073] FIG11 is an equivalent circuit diagram of the shift register unit shown in FIG6 in the first stage;

[0074] FIG12 is an equivalent circuit diagram of the shift register unit shown in FIG6 in the second stage;

[0075] FIG13 is an equivalent circuit diagram of the shift register unit shown in FIG6 in the third stage;

[0076] FIG14 is an equivalent circuit diagram of the shift register unit shown in FIG6 in the fourth stage;

[0077] FIG15 is an equivalent circuit diagram of the shift register unit shown in FIG6 in the fifth stage;

[0078] FIG16 is an equivalent circuit diagram of the shift register unit shown in FIG6 in the sixth stage;

[0079] FIG17 is an equivalent circuit diagram of the shift register unit shown in FIG6 in the eleventh stage;

[0080] FIG18 is an equivalent circuit diagram of the shift register unit shown in FIG6 in the twelfth stage;

[0081] FIG19 is a schematic diagram of a signal timing simulation of a shift register unit provided by an embodiment of the present disclosure;

[0082] FIG20 is a schematic structural diagram of a light-emitting driving circuit provided in an embodiment of the present disclosure;

[0083] FIG21 is a schematic structural diagram of a display device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0084] In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings.

[0085] The transistors used in all embodiments of the present disclosure can be thin-film transistors, field-effect transistors, or other devices with similar characteristics. Based on their function in the circuit, the transistors used in the embodiments of the present disclosure are primarily switching transistors. Since the source and drain of the switching transistors used here are symmetrical, their source and drain are interchangeable. In the embodiments of the present disclosure, the source is referred to as the first electrode, and the drain is referred to as the second electrode. According to the configuration in the accompanying drawings, the middle end of the transistor is designated as the control electrode, which can also be referred to as the gate, the signal input end is designated as the source electrode, and the signal output end is designated as the drain electrode. Furthermore, the switching transistors used in the embodiments of the present disclosure can include either a P-type switching transistor or an N-type switching transistor. A P-type switching transistor is turned on when the gate is at a low level and turned off when the gate is at a high level, while an N-type switching transistor is turned on when the gate is at a high level and turned off when the gate is at a low level. Furthermore, multiple signals in each embodiment of the present disclosure correspond to a first potential and a second potential. The first potential and the second potential merely represent that the potential of the signal has two state variables and do not imply that the first potential or the second potential has a specific value throughout the text.

[0086] FIG1 is a schematic diagram of the structure of a shift register unit provided by an embodiment of the present disclosure. As shown in FIG1 , the shift register unit includes: an input circuit 01 , a pull-down circuit 02 , and an output circuit 03 .

[0087] The input circuit 01 is coupled to the first clock terminal P_ECK1, the second clock terminal P_ECK2, the first power terminal VDD1, the second power terminal VDD2, the starting terminal ESTV, the pull-down terminal VGL, the first pull-up node PU1, and the second pull-up node PU2, respectively. The input circuit 01 is configured to control the connection and disconnection between the starting terminal ESTV and the first pull-up node PU1 in response to a first clock signal provided by the first clock terminal P_ECK1, control the connection and disconnection between the pull-down terminal VGL and the first pull-up node PU1 in response to a second power signal provided by the second power terminal VDD2, and adjust the potential of the first pull-up node PU1 based on the first power signal provided by the first power terminal VDD1, and control the connection and disconnection between the starting terminal ESTV and the second pull-up node PU2 in response to a second clock signal provided by the second clock terminal P_ECK2, control the connection and disconnection between the pull-down terminal VGL and the second pull-up node PU2 in response to the first power signal, and adjust the potential of the second pull-up node PU2 based on the second power signal.

[0088] For example, when the potential of the first clock signal provided by the first clock terminal P_ECK1 is the first potential, the input circuit 01 can control the starting terminal ESTV to be connected to the first pull-up node PU1, so that the starting signal provided by the starting terminal ESTV is transmitted to the first pull-up node PU1. And, when the potential of the first clock signal is the second potential, the input circuit 01 can control the starting terminal ESTV to be disconnected from the first pull-up node PU1. Similarly, when the potential of the second power signal provided by the second power terminal VDD2 is the first potential, the input circuit 01 can control the pull-down terminal VGL to be connected to the first pull-up node PU1, so that the pull-down signal provided by the pull-down terminal VGL is transmitted to the first pull-up node PU1. And, when the potential of the second power signal is the second potential, the input circuit 01 can control the pull-down terminal VGL to be disconnected from the first pull-up node PU1. In addition, the input circuit 01 can also adjust the potential of the first pull-up node PU1 based on the first power signal provided by the first power terminal VDD1 through coupling.

[0089] For example, the input circuit 01 can control the start end ESTV to be turned on with the second pull-up node PU2 when the potential of the second clock signal provided by the second clock end P_ECK2 is the first potential, so that the start signal is transmitted to the second pull-up node PU2. And, the input circuit 01 can control the start end ESTV to be disconnected from the second pull-up node PU2 when the potential of the second clock signal is the second potential. Similarly, the input circuit 01 can control the pull-down end VGL to be turned on with the second pull-up node PU2 when the potential of the first power signal is the first potential, so that the pull-down signal is transmitted to the second pull-up node PU2. And, the input circuit 01 can control the pull-down end VGL to be disconnected from the second pull-up node PU2 when the potential of the first power signal is the second potential. In addition, the input circuit 01 can also adjust the potential of the second pull-up node PU2 based on the second power signal through coupling.

[0090] Optionally, in the embodiment of the present disclosure, the first potential may be an effective potential, and the second potential may be an ineffective potential. Furthermore, the first potential may be a high potential, and the second potential may be a low potential, i.e., the first potential is larger than the second potential. The transistor in the circuit corresponding to this potential may be an N-type transistor. If the transistor in the circuit is a P-type transistor, the first potential may be a low potential, and the second potential may be a high potential, i.e., the first potential is smaller than the second potential.

[0091] Continuing with Figure 1 , the pull-down circuit 02 is coupled to the third clock terminal ECK, the first pull-up node PU1, the second pull-up node PU2, the pull-down terminal VGL, the first reset terminal R1, the second reset terminal R2, and the pull-down node PD, respectively. The pull-down circuit 02 is configured to control the connection between the third clock terminal ECK and the pull-down node PD in response to a third clock signal provided by the third clock terminal ECK, a first reset signal provided by the first reset terminal R1, and a second reset signal provided by the second reset terminal R2. The pull-down circuit 02 is configured to control the connection between the third clock terminal ECK and the pull-down node PD in response to the potential of the first pull-up node PU1, and to control the connection between the pull-down terminal VGL and the pull-down node PD in response to the potential of the second pull-up node PU2.

[0092] For example, the pull-down circuit 02 can control the third clock terminal ECK to be conductive with the pull-down node PD when the potential of the third clock signal provided by the third clock terminal ECK is a first potential, the potential of the first reset signal provided by the first reset terminal R1, and the potential of the second reset signal provided by the second reset terminal R2 are a second potential, so that the third clock terminal ECK and the pull-down node PD are conductively connected. Furthermore, the pull-down circuit 02 can control the third clock terminal ECK to be decoupled from the pull-down node PD when the potential of the third clock signal is the second potential, and the potential of the first reset signal and / or the potential of the second reset signal is the first potential. Similarly, the pull-down circuit 02 can control the pull-down terminal VGL to be conductive with the pull-down node PD when the potential of the first pull-up node PU1 is a first potential, so that the pull-down signal is transmitted to the pull-down node PD. Furthermore, the pull-down circuit 02 can control the pull-down terminal VGL to be decoupled from the pull-down node PD when the potential of the first pull-up node PU1 is a second potential. Furthermore, the pull-down circuit 02 can control the pull-down terminal VGL to be conductive with the pull-down node PD when the potential of the second pull-up node PU2 is at a first potential, so that the pull-down signal is transmitted to the pull-down node PD. Furthermore, the pull-down circuit 02 can control the pull-down terminal VGL to be decoupled from the pull-down node PD when the potential of the second pull-up node PU2 is at a second potential.

[0093] Optionally, the display device includes N cascaded shift register units. The first reset terminal R1 can be coupled to the first pull-up node PU1(n-1) of the cascaded previous shift register unit; the second reset terminal R2 can be coupled to the second pull-up node PU2(n-1) of the cascaded previous shift register unit. Wherein, N is an integer greater than 1; n is greater than 0 and less than or equal to N.

[0094] Output circuit 03 is coupled to the first pull-up node PU1, the second pull-up node PU2, the pull-down node PD, the pull-up terminal VGH, the pull-down terminal VGL, and the output terminal Eout, respectively. Output circuit 03 is configured to control the connection and disconnection between the pull-up terminal VGH and the output terminal Eout in response to the potential of the first pull-up node PU1, control the connection and disconnection between the pull-up terminal VGH and the output terminal Eout in response to the potential of the second pull-up node PU2, and control the connection and disconnection between the pull-down terminal VGL and the output terminal Eout in response to the potential of the pull-down node PD.

[0095] For example, the output circuit 03 can control the pull-up terminal VGH and the output terminal Eout to be conductive when the potential of the first pull-up node PU1 is the first potential, so that the pull-up signal provided by the pull-up terminal VGH is transmitted to the output terminal Eout. And, the output circuit 03 can control the pull-up terminal VGH to be disconnected from the output terminal Eout when the potential of the first pull-up node PU1 is the second potential. Similarly, the output circuit 03 can control the pull-up terminal VGH to be conductive when the potential of the second pull-up node PU2 is the first potential, so that the pull-up signal is transmitted to the output terminal Eout. And, the output circuit 03 can control the pull-up terminal VGH to be disconnected from the output terminal Eout when the potential of the second pull-up node PU2 is the second potential. And, the output circuit 03 can control the pull-down terminal VGL to be conductive when the potential of the pull-down node PD is the first potential, so that the pull-down signal is transmitted to the output terminal Eout. Furthermore, the output circuit 03 can control the pull-down terminal VGL to be disconnected from the output terminal Eout when the potential of the pull-down node PD is the second potential.

[0096] In summary, an embodiment of the present disclosure provides a shift register unit. The shift register unit includes an input circuit, a pull-down circuit, and an output circuit. The input circuit can control the potentials of two pull-up nodes respectively under the control of signals provided by each signal terminal, such as a first clock terminal, a second clock terminal, a first power terminal, a second power terminal, a start terminal, and a pull-down terminal. The pull-down circuit can control the potential of the pull-down node under the control of the potential of the two pull-up nodes, as well as the signals provided by each signal terminal, such as a third clock terminal, a first reset terminal, and a second reset terminal. The output circuit can control the pull-up terminal to transmit a pull-up signal to the output terminal under the control of the potential of the two pull-up nodes, and can control the pull-down terminal to transmit a pull-down signal to the output terminal under the control of the potential of the pull-down node. In this way, the output signal can be reliably adjusted by flexibly setting the signals provided by each signal terminal, thereby avoiding the problem of poor output stability caused by the characteristic deviation of the transistors in each circuit.

[0097] Figure 2 is a schematic diagram of the structure of another shift register unit provided by an embodiment of the present disclosure. As shown in Figure 2, the input circuit 01 may include: a first input sub-circuit 011 and a second input sub-circuit 012. That is, the shift register unit provided by an embodiment of the present disclosure may have a dual-input structure.

[0098] The first input sub-circuit 011 can be coupled to the first clock terminal P_ECK1, the first power terminal VDD1, the second power terminal VDD2, the start terminal ESTV, the pull-down terminal VGL, and the first pull-up node PU1, respectively. The first input sub-circuit 011 can be used to control the connection between the start terminal ESTV and the first pull-up node PU1 in response to the first clock signal, control the connection between the pull-down terminal VGL and the first pull-up node PU1 in response to the second power signal, and adjust the potential of the first pull-up node PU1 based on the first power signal.

[0099] For example, the first input sub-circuit 011 can control the starting end ESTV to be connected to the first pull-up node PU1 when the potential of the first clock signal is the first potential, so that the starting signal is transmitted to the first pull-up node PU1. And, the first input sub-circuit 011 can control the starting end ESTV to be disconnected from the first pull-up node PU1 when the potential of the first clock signal is the second potential. Similarly, the first input sub-circuit 011 can control the pull-down end VGL to be connected to the first pull-up node PU1 when the potential of the second power signal is the first potential, so that the pull-down signal is transmitted to the first pull-up node PU1. And, the first input sub-circuit 011 can control the pull-down end VGL to be disconnected from the first pull-up node PU1 when the potential of the second power signal is the second potential. In addition, the first input sub-circuit 011 can also adjust the potential of the first pull-up node PU1 based on the first power signal through coupling.

[0100] The second input sub-circuit 012 can be coupled to the second clock terminal P_ECK2, the first power terminal VDD1, the second power terminal VDD2, the starting terminal ESTV, the pull-down terminal VGL, and the second pull-up node PU2, respectively. The second input sub-circuit 012 can be used to control the connection between the starting terminal ESTV and the second pull-up node PU2 in response to the second clock signal, control the connection between the pull-down terminal VGL and the second pull-up node PU2 in response to the first power signal, and adjust the potential of the second pull-up node PU2 based on the second power signal.

[0101] For example, the second input sub-circuit 012 can control the start end ESTV to be connected to the second pull-up node PU2 when the potential of the second clock signal is the first potential, so that the start signal is transmitted to the second pull-up node PU2. And, the second input sub-circuit 012 can control the start end ESTV to be disconnected from the second pull-up node PU2 when the potential of the second clock signal is the second potential. Similarly, the second input sub-circuit 012 can control the pull-down end VGL to be connected to the second pull-up node PU2 when the potential of the first power signal is the first potential, so that the pull-down signal is transmitted to the second pull-up node PU2. And, the second input sub-circuit 012 can control the pull-down end VGL to be disconnected from the second pull-up node PU2 when the potential of the first power signal is the second potential. In addition, the second input sub-circuit 012 can also adjust the potential of the second pull-up node PU2 based on the second power signal through coupling.

[0102] FIG3 is a schematic diagram of the structure of another shift register unit provided by an embodiment of the present disclosure. As shown in FIG3 , the pull-down circuit 02 may include: a pull-down control sub-circuit 021 and a pull-down sub-circuit 022 .

[0103] Pull-down control subcircuit 021 can be coupled to the third clock terminal ECK, the first reset terminal R1, the second reset terminal R2, the pull-down terminal VGL, and the pull-down control node PD_C. Pull-down control subcircuit 021 can be used to control the connection between the pull-down terminal VGL and the pull-down control node PD_C in response to the first reset signal and the second reset signal, and to adjust the potential of the pull-down control node PD_C based on the third clock signal.

[0104] For example, the pull-down control sub-circuit 021 can control the pull-down terminal VGL to be electrically connected to the pull-down control node PD_C when the potential of the first reset signal and / or the potential of the second reset signal is a first potential, so that the pull-down signal is transmitted to the pull-down control node PD_C. Furthermore, the pull-down control sub-circuit 021 can control the pull-down terminal VGL to be disconnected from the pull-down control node PD_C when the potential of the first reset signal and the potential of the second reset signal are both a second potential. Furthermore, the pull-down control sub-circuit 021 can also adjust the potential of the pull-down control node PD_C based on the third clock signal through coupling.

[0105] Pull-down sub-circuit 022 can be coupled to the pull-down control node PD_C, the third clock terminal ECK, the first pull-up node PU1, the second pull-up node PU2, the pull-down node PD, and the pull-down terminal VGL, respectively. Pull-down sub-circuit 022 can be used to control the connection and disconnection between the third clock terminal ECK and the pull-down node PD in response to the potential of the pull-down control node PD_C, control the connection and disconnection between the pull-down terminal VGL and the pull-down node PD in response to the potential of the first pull-up node PU1, and control the connection and disconnection between the pull-down terminal VGL and the pull-down node PD in response to the potential of the second pull-up node PU2.

[0106] For example, when the potential of the pull-down control node PD_C is at a first potential, the pull-down sub-circuit 022 can control the third clock terminal ECK to be conductive with the pull-down node PD, so that the third clock signal is transmitted to the pull-down node PD. Furthermore, when the potential of the pull-down control node PD_C is at a second potential, the pull-down sub-circuit 022 can control the third clock terminal ECK to be decoupled from the pull-down node PD. Similarly, when the potential of the first pull-up node PU1 is at a first potential, the pull-down sub-circuit 022 can control the pull-down terminal VGL to be conductive with the pull-down node PD, so that the pull-down signal is transmitted to the pull-down node PD. Furthermore, when the potential of the first pull-up node PU1 is at a second potential, the pull-down sub-circuit 022 can control the pull-down terminal VGL to be decoupled from the pull-down node PD. Furthermore, when the potential of the second pull-up node PU2 is at a first potential, the pull-down sub-circuit 022 can control the pull-down terminal VGL to be conductive with the pull-down node PD, so that the pull-down signal is transmitted to the pull-down node PD. Furthermore, the pull-down sub-circuit 022 may control the pull-down terminal VGL to be disconnected from the pull-down node PD when the potential of the second pull-up node PU2 is the second potential.

[0107] FIG4 is a schematic diagram of the structure of another shift register unit provided by an embodiment of the present disclosure. As shown in FIG4 , the output circuit 03 may include: a first output sub-circuit 031 , a second output sub-circuit 032 , and a third output sub-circuit 033 .

[0108] The first output sub-circuit 031 can be coupled to the first pull-up node PU1, the pull-up terminal VGH and the output terminal Eout respectively, and can be used to control the connection between the pull-up terminal VGH and the output terminal Eout in response to the potential of the first pull-up node PU1.

[0109] For example, the first output sub-circuit 031 can control the pull-up terminal VGH to be conductive with the output terminal Eout when the potential of the first pull-up node PU1 is a first potential, so that the pull-up signal is transmitted to the output terminal Eout. Furthermore, the first output sub-circuit 031 can control the pull-up terminal VGH to be decoupled from the output terminal Eout when the potential of the first pull-up node PU1 is a second potential.

[0110] The second output sub-circuit 032 can be coupled to the second pull-up node PU2, the pull-up terminal VGH and the output terminal Eout respectively, and can be used to control the connection between the pull-up terminal VGH and the output terminal Eout in response to the potential of the second pull-up node PU2.

[0111] For example, the second output sub-circuit 032 can control the pull-up terminal VGH to be conductive with the output terminal Eout when the potential of the second pull-up node PU2 is at a first potential, so that the pull-up signal is transmitted to the output terminal Eout. Furthermore, the second output sub-circuit 032 can control the pull-up terminal VGH to be decoupled from the output terminal Eout when the potential of the second pull-up node PU2 is at a second potential.

[0112] The third output sub-circuit 033 can be coupled to the pull-down node PD, the pull-down terminal VGL and the output terminal Eout respectively and can be used to control the connection between the pull-down terminal VGL and the output terminal Eout in response to the potential of the pull-down node PD.

[0113] For example, the third output sub-circuit 033 can control the pull-down terminal VGL to be conductive with the output terminal Eout when the potential of the pull-down node PD is at a first potential, so that the pull-down signal is transmitted to the output terminal Eout. Furthermore, the third output sub-circuit 033 can control the pull-down terminal VGL to be decoupled from the output terminal Eout when the potential of the pull-down node PD is at a second potential.

[0114] Based on Figure 4, Figure 5 shows a schematic diagram of the circuit structure of a shift register unit provided by an embodiment of the present disclosure. As shown in Figure 5, the first input sub-circuit 011 may include: a first transistor M1, a second transistor M2 and a first capacitor C1.

[0115] A gate of the first transistor M1 may be coupled to the first clock terminal P_ECK1 , a first electrode of the first transistor M1 may be coupled to the start terminal ESTV, and a second electrode of the first transistor M1 may be coupled to the first pull-up node PU1 .

[0116] A gate of the second transistor M2 may be coupled to the second power supply terminal VDD2 , a first electrode of the second transistor M2 may be coupled to the pull-down terminal VGL, and a second electrode of the second transistor M2 may be coupled to the first pull-up node PU1 .

[0117] A first terminal of the first capacitor C1 may be coupled to the first power supply terminal VDD1 , and a second terminal of the first capacitor C1 may be coupled to the first pull-up node PU1 .

[0118] Optionally, referring to FIG. 5 , it can be seen that the second input sub-circuit 012 may include: a third transistor M3 , a fourth transistor M4 , and a second capacitor C2 .

[0119] A gate of the third transistor M3 may be coupled to the second clock terminal P_ECK2 , a first electrode of the third transistor M3 may be coupled to the start terminal ESTV, and a second electrode of the third transistor M3 may be coupled to the second pull-up node PU2 .

[0120] A gate of the fourth transistor M4 may be coupled to the first power supply terminal VDD1 , a first electrode of the fourth transistor M4 may be coupled to the pull-down terminal VGL, and a second electrode of the fourth transistor M4 may be coupled to the second pull-up node PU2 .

[0121] A first terminal of the second capacitor C2 may be coupled to the second power supply terminal VDD2 , and a second terminal of the second capacitor C2 may be coupled to the second pull-up node PU2 .

[0122] Optionally, with continued reference to FIG. 5 , it can be seen that the pull-down control sub-circuit 021 may include: a fifth transistor M5 , a sixth transistor M6 , and a third capacitor C3 .

[0123] A gate of the fifth transistor M5 may be coupled to the first reset terminal R1 , a first electrode of the fifth transistor M5 may be coupled to the pull-down terminal VGL, and a second electrode of the fifth transistor M5 may be coupled to the pull-down control node PD_C.

[0124] A gate of the sixth transistor M6 may be coupled to the second reset terminal R2 , a first electrode of the sixth transistor M6 may be coupled to the pull-down terminal VGL, and a second electrode of the sixth transistor M6 may be coupled to the pull-down control node PD_C.

[0125] A first terminal of the third capacitor C3 may be coupled to the third clock terminal ECK, and a second terminal of the third capacitor C3 may be coupled to the pull-down control node PD_C.

[0126] Optionally, with continued reference to FIG. 5 , it can be seen that the pull-down sub-circuit 022 may include: a seventh transistor M7 , an eighth transistor M8 , and a ninth transistor M9 .

[0127] A gate of the seventh transistor M7 may be coupled to the pull-down control node PD_C, a first electrode of the seventh transistor M7 may be coupled to the third clock terminal ECK, and a second electrode of the seventh transistor M7 may be coupled to the pull-down node PD.

[0128] A gate of the eighth transistor M8 may be coupled to the first pull-up node PU1 , a first electrode of the eighth transistor M8 may be coupled to the pull-down terminal VGL, and a second electrode of the eighth transistor M8 may be coupled to the pull-down node PD.

[0129] A gate of the ninth transistor M9 may be coupled to the second pull-up node PU2 , a first electrode of the ninth transistor M9 may be coupled to the pull-down terminal VGL, and a second electrode of the ninth transistor M9 may be coupled to the pull-down node PD.

[0130] 5 , the first output sub-circuit 031 may include a tenth transistor M10 and a fourth capacitor C4, the second output sub-circuit 032 may include an eleventh transistor M11 and a fifth capacitor C5, and the third output sub-circuit 033 may include a twelfth transistor M12 and a sixth capacitor C6.

[0131] A gate of the tenth transistor M10 may be coupled to the first pull-up node PU1 , a first electrode of the tenth transistor M10 may be coupled to the pull-up terminal VGH, and a second electrode of the tenth transistor M10 may be coupled to the output terminal Eout.

[0132] A first terminal of the fourth capacitor C4 may be coupled to the first pull-up node PU1 , and a second terminal of the fourth capacitor C4 may be coupled to the output terminal Eout.

[0133] A gate of the eleventh transistor M11 may be coupled to the second pull-up node PU2 , a first electrode of the eleventh transistor M11 may be coupled to the pull-up terminal VGH, and a second electrode of the eleventh transistor M11 may be coupled to the output terminal Eout.

[0134] A first terminal of the fifth capacitor C5 may be coupled to the second pull-up node PU2 , and a second terminal of the fifth capacitor C5 may be coupled to the output terminal Eout.

[0135] A gate of the twelfth transistor M12 may be coupled to the pull-down node PD, a first electrode of the twelfth transistor M12 may be coupled to the pull-down terminal VGL, and a second electrode of the twelfth transistor M12 may be coupled to the output terminal Eout.

[0136] A first terminal of the sixth capacitor C6 may be coupled to the pull-down node PD, and a second terminal of the sixth capacitor C6 may be coupled to the pull-down terminal VGL.

[0137] Alternatively, referring to FIG. 5 , it can be seen that the twelfth transistor M12 includes two transistors M12a and M12b connected in series between the output terminal Eout and the pull-down terminal VGL, and is a dual-gate transistor. This reduces leakage current in the third output sub-circuit 033 and ensures reliable signal transmission to the output terminal Eout.

[0138] On the basis that the twelfth transistor M12 includes two transistors M12 a and M12 b connected in series, as shown in FIG5 , the shift register unit may further include: an anti-leakage circuit 04 .

[0139] The leakage prevention circuit 04 can be coupled to the first pull-up node PU1, the second pull-up node PU2, the pull-up terminal VGH, and the series node N1 of the two transistors in series in the twelfth transistor M12. The leakage prevention circuit 04 can be used to control the connection and disconnection between the pull-up terminal VGH and the series node N1 in response to the potential of the first pull-up node PU1, and to control the connection and disconnection between the pull-up terminal VGH and the series node N1 in response to the potential of the second pull-up node PU2.

[0140] For example, the anti-leakage circuit 04 can control the pull-up terminal VGH to be conductive with the series node N1 when the potential of the first pull-up node PU1 is the first potential, so that the pull-up signal is transmitted to the series node N1. Also, the anti-leakage circuit 04 can control the pull-up terminal VGH to be decoupled from the series node N1 when the potential of the first pull-up node PU1 is the second potential. Similarly, the anti-leakage circuit 04 can control the pull-up terminal VGH to be conductive with the series node N1 when the potential of the second pull-up node PU2 is the first potential, so that the pull-up signal is transmitted to the series node N1. Also, the anti-leakage circuit 04 can control the pull-up terminal VGH to be decoupled from the series node N1 when the potential of the second pull-up node PU2 is the second potential. In this way, leakage at the series node N1 can be avoided, thereby further ensuring reliable signal transmission to the output terminal Eout.

[0141] Based on FIG5 , further referring to FIG6 , which is a schematic diagram of a circuit structure of another shift register unit, it can be seen that the leakage protection circuit 04 may include: a thirteenth transistor M13 and a fourteenth transistor M14 .

[0142] A gate of the thirteenth transistor M13 may be coupled to the first pull-up node PU1 , a first electrode of the thirteenth transistor M13 may be coupled to the pull-up terminal VGH, and a second electrode of the thirteenth transistor M13 may be coupled to the series node N1 .

[0143] A gate of the fourteenth transistor M14 may be coupled to the second pull-up node PU2 , a first electrode of the fourteenth transistor M14 may be coupled to the pull-up terminal VGH, and a second electrode of the fourteenth transistor M14 may be coupled to the series node N1 .

[0144] Optionally, each transistor in the shift register unit provided in the embodiment of the present disclosure may include: an N-type transistor. And the material of the N-type transistor may include: an oxide material. That is, each transistor in the shift register unit may be an N-type transistor made of oxide material. The material here refers to the material of the active layer in the transistor. Correspondingly, as described above, the first potential may be a high potential, and the second potential may be a low potential. Of course, in some other embodiments, each transistor may also include: a P-type transistor. The material of the P-type transistor may include low temperature polysilicon (LTPS). Of course, the materials here are only schematic illustrations.

[0145] It is understood that the shift register unit shown in Figure 6 is a shift register unit with a 14T6C structure (ie, including 14 transistors and 6 capacitors). Of course, in some other embodiments, it is not limited to the 14T6C structure.

[0146] Optionally, the output terminal Eout of the shift register unit described in the embodiment of the present disclosure can be used to couple with the light emitting control terminal of the pixel circuit. Accordingly, the signal outputted through the output terminal Eout can be a light emitting control signal provided to the light emitting control terminal.

[0147] For example, FIG7 shows a schematic diagram of the structure of a pixel circuit. As shown in FIG7 , the pixel circuit can be a pixel circuit with a 7T1C structure (i.e., including 7 transistors T1 to T7 and 1 capacitor Cst). The 7 transistors T1 to T7 in the pixel circuit can be coupled to the following signal terminals, respectively: a reset signal terminal Rst(n), a light-emitting control terminal EM(n), an initial power supply terminal Vinit, a data signal terminal Data(n), a drive power supply terminal VDD, and gate signal terminals Gate(n) and Gate(n-1). In addition, the pixel circuit can also be coupled to the first electrode of the light-emitting element L1, and the second electrode of the light-emitting element L1 can also be coupled to the pull-down power supply terminal VSS. The pixel circuit can transmit a light-emitting drive signal to the first electrode of the light-emitting element L1 based on the signals provided by the coupled signal terminals, so that the light-emitting element L1 emits light under the voltage difference between the light-emitting drive signal and the pull-down power supply signal provided by the pull-down power supply terminal VSS. Of course, the pixel circuit is not limited to the 7T1C structure shown in FIG7 .

[0148] Optionally, the light-emitting element L1 may be an organic light-emitting diode (OLED). The first electrode of the light-emitting element L1 may be an anode, and the second electrode may be a cathode. Alternatively, in some other embodiments, the first electrode of the light-emitting element L1 may be a cathode, and the second electrode may be an anode. Each transistor in the pixel circuit may also be an N-type transistor. Alternatively, in some other embodiments, a P-type transistor may also be included.

[0149] It is understood that a structure including a pixel circuit and a light-emitting element can be referred to as a pixel. A display panel generally includes multiple rows and columns of pixels, and multiple cascaded shift register units can be coupled to the multiple rows of pixels in a one-to-one correspondence. In the embodiment of the present disclosure, the shift register unit can be coupled to the light-emitting control terminal EM(n) coupled to the pixel circuit and is used to provide a light-emitting control signal to the light-emitting control terminal EM(n).

[0150] For example, based on the structure shown in Figure 7, Figure 8 shows a timing diagram of the signal terminals coupled to a pixel circuit. Referring to Figure 8, it can be seen that driving the light-emitting element L1 to emit light can include a reset phase t01, a data writing phase t02, and a light-emitting phase t03 performed sequentially.

[0151] During the reset phase t01, the potential of the reset signal provided by the reset signal terminal Rst(n) and the potential of the gate drive signal provided by the gate signal terminal Gate(n-1) are both high, turning on transistors T6 and T7. This in turn causes the drive power signal provided by the drive power terminal VDD to be transmitted to the gate of transistor T3, and the initial power signal provided by the initial power terminal Vinit to be transmitted to the anode of light-emitting element L1. During the data writing phase t02, the potential of the gate drive signal provided by the gate signal terminal Gate(n) is high, turning on transistors T2 and T4. This in turn causes the data signal provided by the data signal terminal Data(n) to be transmitted to the gate of transistor T3. Furthermore, during the data writing phase t02, the potential of the reset signal provided by the reset signal terminal Rst(n) remains high, allowing the initial power signal to continue to be transmitted to the anode of light-emitting element L1. In the light-emitting stage t03, the potential of the light-emitting control signal provided by the light-emitting control terminal EM(n) is a high potential, so that the transistors T1 and T5 are turned on, thereby forming a path between the driving power supply terminal VDD and the pull-down power supply terminal VSS, thereby transmitting the light-emitting driving signal to the light-emitting element L1 to drive the light-emitting element L1 to emit light.

[0152] In summary, an embodiment of the present disclosure provides a shift register unit. The shift register unit includes an input circuit, a pull-down circuit, and an output circuit. The input circuit can control the potentials of two pull-up nodes respectively under the control of signals provided by each signal terminal, such as a first clock terminal, a second clock terminal, a first power terminal, a second power terminal, a start terminal, and a pull-down terminal. The pull-down circuit can control the potential of the pull-down node under the control of the potential of the two pull-up nodes, as well as the signals provided by each signal terminal, such as a third clock terminal, a first reset terminal, and a second reset terminal. The output circuit can control the pull-up terminal to transmit a pull-up signal to the output terminal under the control of the potential of the two pull-up nodes, and can control the pull-down terminal to transmit a pull-down signal to the output terminal under the control of the potential of the pull-down node. In this way, the output signal can be reliably adjusted by flexibly setting the signals provided by each signal terminal, thereby avoiding the problem of poor output stability caused by the characteristic deviation of the transistors in each circuit.

[0153] FIG9 is a flow chart of a method for driving a shift register unit according to an embodiment of the present disclosure. The method can be used to drive a shift register unit as shown in any one of FIG1 to FIG6 . As shown in FIG9 , the driving method includes:

[0154] Step 901, in the first stage, the potential of the first power signal provided by the first power supply terminal and the potential of the first clock signal provided by the first clock terminal are both the first potential, and the potential of the second power signal provided by the second power supply terminal and the potential of the second clock signal provided by the second clock terminal are both the second potential; the input circuit controls the start terminal to be connected to the first pull-up node in response to the first clock signal, and controls the pull-down terminal to be connected to the second pull-up node in response to the first power signal, and the potential of the start signal provided by the start terminal is the first potential; the pull-down circuit controls the pull-down terminal to be connected to the pull-down node in response to the potential of the first pull-up node; the output circuit controls the pull-up terminal to be connected to the output terminal in response to the potential of the first pull-up node.

[0155] Step 902, the second stage, the potential of the second power supply signal and the potential of the second clock signal are the first potential, and the potential of the first power supply signal and the potential of the first clock signal are the second potential; the input circuit controls the start end to be connected to the second pull-up node in response to the second clock signal, and controls the pull-down end to be connected to the first pull-up node in response to the second power supply signal, and the potential of the start signal is the second potential; the pull-down circuit controls the third clock end to be connected to the pull-down node in response to the third clock signal provided by the third clock end, and the potential of the third clock signal is the first potential; the output circuit controls the pull-down end to be connected to the output end in response to the potential of the pull-down node.

[0156] Optionally, taking the shift register unit shown in FIG6 , each transistor is an N-type transistor, and accordingly, the first potential (i.e., the effective potential) is a high potential, the second potential (i.e., the invalid potential) is a low potential, and the potential of the pull-up signal provided by the pull-up terminal VGH is a high potential, and the potential of the pull-down signal provided by the pull-down terminal VGL is a low potential as an example, the driving principle of the shift register unit recorded in the embodiment of the present disclosure is described in detail. For example, FIG10 is a timing diagram of each signal terminal in a shift register unit provided in an embodiment of the present disclosure. As shown in FIG10 , the driving process can be divided into at least 12 stages: (1) to (12).

[0157] In the first stage (1), the potential of the first power signal provided by the first power supply terminal VDD1, the potential of the start signal provided by the start terminal ESTV, the potential of the first clock signal provided by the first clock terminal P_ECK1, and the potential of the third clock signal provided by the third clock terminal ECK are all high potentials. The potential of the second power signal provided by the second power supply terminal VDD2 and the potential of the second clock signal provided by the second clock terminal P_ECK2 are all low potentials. Moreover, at this time, the potential of the first pull-up node PU1(n-1) of the cascaded previous stage shift register unit is high potential, that is, the potential of the first reset signal provided by the first reset terminal R1 is high potential. The potential of the second pull-up node PU2(n-1) of the cascaded previous stage shift register unit is low potential, that is, the potential of the second reset signal provided by the second reset terminal R2 is low potential. Accordingly, the first transistor M1, the fourth transistor M4 and the fifth transistor M5 can all be turned on, while the second transistor M2, the third transistor M3 and the sixth transistor M6 can all be turned off. Furthermore, the high-potential start signal can be transmitted to the first pull-up node PU1 via the turned-on first transistor M1 to charge the first pull-up node PU1. The low-potential pull-down signal can be transmitted to the second pull-up node PU2 via the turned-on fourth transistor M4 to discharge the second pull-up node PU2, and transmitted to the pull-down control node PD_C via the turned-on fifth transistor M5 to discharge the pull-down control node PD_C. Accordingly, the eighth transistor M8, the tenth transistor M10, and the thirteenth transistor M13 can be further turned on, while the seventh transistor M7, the ninth transistor M9, the eleventh transistor M11, and the fourteenth transistor M14 can be turned off. Furthermore, the low-potential pull-down signal can also be transmitted to the pull-down node PD via the turned-on eighth transistor M8 to discharge the pull-down node PD. Accordingly, the twelfth transistor M12 can be further turned off. Furthermore, the high-potential pull-up signal can be transmitted to the series node N1 via the turned-on thirteenth transistor M13, and transmitted to the output terminal Eout via the turned-on tenth transistor M10.

[0158] That is, in the first stage (1), a high-voltage signal can be output through the output terminal Eout. For example, a high-voltage light-emitting control signal, which will not be described in detail below. For example, FIG11 shows an equivalent circuit diagram of the shift register unit in the first stage (1).

[0159] In the second stage (2), the potential of the start signal provided by the start terminal ESTV is a high potential. The potential of the first power signal provided by the first power terminal VDD1, the potential of the second power signal provided by the second power terminal VDD2, the potential of the first clock signal provided by the first clock terminal P_ECK1, the potential of the second clock signal provided by the second clock terminal P_ECK2, and the potential of the third clock signal provided by the third clock terminal ECK are all low potentials. Moreover, at this time, the potential of the first pull-up node PU1 (n-1) of the cascaded previous stage shift register unit is a high potential, that is, the potential of the first reset signal is a high potential. The potential of the second pull-up node PU2 (n-1) of the cascaded previous stage shift register unit is a low potential, that is, the potential of the second reset signal is a low potential. Accordingly, the fifth transistor M5 can be turned on, while the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4 and the sixth transistor M6 are all turned off. Furthermore, the low-potential pull-down signal can be transmitted to the pull-down control node PD_C via the turned-on fifth transistor M5 to discharge the pull-down control node PD_C. In addition, under the action of the first capacitor C1, the potential of the first pull-up node PU1 can be maintained at the high potential of the first stage (1); under the action of the second capacitor C2, the potential of the second pull-up node PU2 can be maintained at the low potential of the first stage (1). Accordingly, the eighth transistor M8, the tenth transistor M10, and the thirteenth transistor M13 can be further turned on, while the seventh transistor M7, the ninth transistor M9, the eleventh transistor M11, and the fourteenth transistor M14 can be turned off. Furthermore, the low-potential pull-down signal can also be transmitted to the pull-down node PD via the turned-on eighth transistor M8 to discharge the pull-down node PD. Accordingly, the twelfth transistor M12 can be further turned off. Furthermore, the high-potential pull-up signal can be transmitted to the series node N1 via the turned-on thirteenth transistor M13, and transmitted to the output terminal Eout via the turned-on tenth transistor M10.

[0160] That is, in the second phase (2), the high potential signal can continue to be output through the output terminal Eout. For example, FIG12 shows an equivalent circuit diagram of the shift register unit in the second phase (2).

[0161] In the third stage (3), the potential of the start signal provided by the start terminal ESTV, the potential of the second clock signal provided by the second clock terminal P_ECK2, and the potential of the third clock signal provided by the third clock terminal ECK are all high potentials. The potential of the first power signal provided by the first power terminal VDD1, the potential of the second power signal provided by the second power terminal VDD2, and the potential of the first clock signal provided by the first clock terminal P_ECK1 are all low potentials. Moreover, at this time, the potential of the second pull-up node PU2(n-1) of the cascaded upper-stage shift register unit is high potential, that is, the potential of the second reset signal is high potential. The potential of the first pull-up node PU1(n-1) of the cascaded upper-stage shift register unit is low potential, that is, the potential of the first reset signal is low potential. Accordingly, the third transistor M3 and the sixth transistor M6 can be turned on, while the first transistor M1, the second transistor M2, the fourth transistor M4 and the fifth transistor M5 can be turned off. Furthermore, the low-potential pull-down signal can be transmitted to the pull-down control node PD_C via the turned-on sixth transistor M6 to discharge the pull-down control node PD_C. The high-potential start signal can be transmitted to the second pull-up node PU2 via the turned-on third transistor M3 to charge the second pull-up node PU2. However, because the high potential of the start signal is lower than the high potential of the pull-up signal, the potential of the second pull-up node PU2 is not fully charged to the required high potential at this time. In addition, under the action of the first capacitor C1, the potential of the first pull-up node PU1 can be maintained at the high potential of the second stage (2). Accordingly, the eighth transistor M8, the ninth transistor M9, the tenth transistor M10 and the thirteenth transistor M13 can be further turned on, while the seventh transistor M7, the eleventh transistor M11 and the fourteenth transistor M14 can be turned off. Furthermore, the low-potential pull-down signal can also be transmitted to the pull-down node PD via the turned-on eighth transistor M8 and the turned-on ninth transistor M9 to discharge the pull-down node PD. Accordingly, the twelfth transistor M12 can be further turned off. Furthermore, the high-level pull-up signal may be transmitted to the series node N1 via the turned-on thirteenth transistor M13 , and transmitted to the output terminal Eout via the turned-on tenth transistor M10 .

[0162] That is, in the third phase (3), the high potential signal can continue to be output through the output terminal Eout. For example, FIG13 shows an equivalent circuit diagram of the shift register unit in the third phase (3).

[0163] In the fourth stage (4), the potential of the second power supply signal provided by the second power supply terminal VDD2 is a high potential. The potential of the start signal provided by the start terminal ESTV, the potential of the first power supply signal provided by the first power supply terminal VDD1, the potential of the first clock signal provided by the first clock terminal P_ECK1, the potential of the second clock signal provided by the second clock terminal P_ECK2, and the potential of the third clock signal provided by the third clock terminal ECK are all low potentials. Moreover, at this time, the potential of the first pull-up node PU1 (n-1) and the potential of the second pull-up node PU2 (n-1) of the cascaded upper-level shift register unit are both low potentials, that is, the potential of the first reset signal and the potential of the second reset signal are both low potentials. Accordingly, the second transistor M2 can be turned on, and the first transistor M1, the third transistor M3, the fourth transistor M4, the fifth transistor M5 and the sixth transistor M6 are all turned off. Furthermore, the low-potential pull-down signal can be transmitted to the first pull-up node PU1 via the turned-on second transistor M2 to discharge the first pull-up node PU1. In addition, under the action of the third capacitor C3, the potential of the pull-down control node PD_C can be maintained at the low potential of the third stage (3). And, under the action of the second capacitor C2, the potential of the second pull-up node PU2 is further charged and pulled up to a higher potential. Accordingly, the ninth transistor M9, the eleventh transistor M11 and the fourteenth transistor M14 can be further turned on, while the seventh transistor M7, the eighth transistor M8, the tenth transistor M10 and the thirteenth transistor M13 can be turned off. Furthermore, the low-potential pull-down signal can also be transmitted to the pull-down node PD via the turned-on ninth transistor M9 to discharge the pull-down node PD. Accordingly, the twelfth transistor M12 can be further turned off. Furthermore, the high-potential pull-up signal can be transmitted to the series node N1 via the turned-on fourteenth transistor M14, and transmitted to the output terminal Eout via the turned-on eleventh transistor M11.

[0164] That is, in the fourth stage (4), a high-potential signal can continue to be output through the output terminal Eout. For example, FIG14 shows an equivalent circuit diagram of the shift register unit in the fourth stage (4). By providing the first capacitor C1 and the second capacitor C2, after the potential of the first power supply signal provided by the first power supply terminal VDD1 and the second power supply signal provided by the second power supply terminal VDD2 are switched, the output terminal Eout can be prevented from being in a floating state before being output to the output terminal Eout, thereby ensuring output stability.

[0165] In the fifth stage (5), the potential of the second power signal provided by the second power supply terminal VDD2, the potential of the second clock signal provided by the second clock terminal P_ECK2, and the potential of the third clock signal provided by the third clock terminal ECK are all high potentials. The potential of the start signal provided by the start terminal ESTV, the potential of the first power signal provided by the first power supply terminal VDD1, and the potential of the first clock signal provided by the first clock terminal P_ECK1 are all low potentials. Moreover, at this time, the potential of the first pull-up node PU1(n-1) and the potential of the second pull-up node PU2(n-1) of the cascaded upper-stage shift register unit are both low potentials, that is, the potential of the first reset signal and the potential of the second reset signal are both low potentials. Accordingly, the second transistor M2 and the third transistor M3 can be turned on, while the first transistor M1, the fourth transistor M4, the fifth transistor M5 and the sixth transistor M6 can be turned off. Furthermore, the low-potential pull-down signal can be transmitted to the first pull-up node PU1 via the turned-on second transistor M2 to discharge the first pull-up node PU1. The low potential start signal can be transmitted to the second pull-up node PU2 via the turned-on third transistor M3 to discharge the second pull-up node PU2. In addition, under the action of the third capacitor C3, the potential of the pull-down control node PD_C can jump to a high potential based on the high potential third clock signal. Accordingly, the seventh transistor M7 can be further turned on, and the eighth transistor M8, the ninth transistor M9, the tenth transistor M10, the eleventh transistor M11, the thirteenth transistor M13 and the fourteenth transistor M14 can all be turned off. Furthermore, the high potential third clock signal can be transmitted to the pull-down node PD via the turned-on seventh transistor M7 to charge the pull-down node PD. Accordingly, the twelfth transistor M12 can be further turned on. Furthermore, the low potential pull-down signal can be transmitted to the output terminal Eout via the turned-on twelfth transistor M12.

[0166] That is, in the fifth stage (5), a low-level signal can be output through the output terminal Eout. For example, a low-level light-emitting control signal, which will not be described in detail below. For example, FIG15 shows an equivalent circuit diagram of the shift register unit in the fifth stage (5).

[0167] In the sixth stage (6), the potential of the second power supply signal provided by the second power supply terminal VDD2 is a high potential. The potential of the start signal provided by the start terminal ESTV, the potential of the first power supply signal provided by the first power supply terminal VDD1, the potential of the first clock signal provided by the first clock terminal P_ECK1, the potential of the second clock signal provided by the second clock terminal P_ECK2, and the potential of the third clock signal provided by the third clock terminal ECK are all low potentials. Moreover, at this time, the potential of the first pull-up node PU1 (n-1) and the potential of the second pull-up node PU2 (n-1) of the cascaded upper-level shift register unit are both low potentials, that is, the potential of the first reset signal and the potential of the second reset signal are both low potentials. Accordingly, the second transistor M2 can be turned on, and the first transistor M1, the third transistor M3, the fourth transistor M4, the fifth transistor M5 and the sixth transistor M6 are all turned off. Furthermore, the low-potential pull-down signal can be transmitted to the first pull-up node PU1 through the turned-on second transistor M2 to discharge the first pull-up node PU1. In addition, under the action of the second capacitor C2, the potential of the second pull-up node PU2 can be maintained at the low potential of the fifth stage (5). Under the action of the third capacitor C3, the potential of the pull-down control node PD_C can jump to a low potential based on the low-potential third clock signal. And, under the action of the sixth capacitor C6, the potential of the pull-down node PD can be maintained at the high potential of the fifth stage (5). Accordingly, the twelfth transistor M12 can be further turned on, while the seventh transistor M7, the eighth transistor M8, the ninth transistor M9, the tenth transistor M10, the eleventh transistor M11, the thirteenth transistor M13 and the fourteenth transistor M14 are all turned off. Furthermore, the low-potential pull-down signal can be transmitted to the output terminal Eout via the turned-on twelfth transistor M12.

[0168] That is, in the sixth stage (6), a low potential signal can be outputted through the output terminal Eout. For example, FIG16 shows an equivalent circuit diagram of the shift register unit in the sixth stage (6).

[0169] In the seventh stage (7), the potential of the second power signal provided by the second power supply terminal VDD2, the potential of the second clock signal provided by the second clock terminal P_ECK2, and the potential of the third clock signal provided by the third clock terminal ECK are all high potentials. The potential of the start signal provided by the start terminal ESTV, the potential of the first power signal provided by the first power supply terminal VDD1, and the potential of the first clock signal provided by the first clock terminal P_ECK1 are all low potentials. Moreover, at this time, the potential of the first pull-up node PU1 (n-1) and the potential of the second pull-up node PU2 (n-1) of the cascaded upper-level shift register unit are both low potentials, that is, the potential of the first reset signal and the potential of the second reset signal are both low potentials. Since the signal timing is the same as that of the fifth stage (5), the driving principle of the shift register unit in the seventh stage (7) is also the same as that of the fifth stage (5), and will not be repeated. Accordingly, the equivalent circuit diagram of the seventh stage (7) can also refer to the equivalent circuit diagram 15 of the fifth stage (5) and will not be shown.

[0170] In the eighth stage (8), the potential of the second power supply signal provided by the second power supply terminal VDD2 is a high potential. The potential of the start signal provided by the start terminal ESTV, the potential of the first power supply signal provided by the first power supply terminal VDD1, the potential of the first clock signal provided by the first clock terminal P_ECK1, the potential of the second clock signal provided by the second clock terminal P_ECK2, and the potential of the third clock signal provided by the third clock terminal ECK are all low potentials. Moreover, at this time, the potential of the first pull-up node PU1 (n-1) and the potential of the second pull-up node PU2 (n-1) of the cascaded upper-level shift register unit are both low potentials, that is, the potential of the first reset signal and the potential of the second reset signal are both low potentials. Since the signal timing is the same as that of the sixth stage (6), the driving principle of the shift register unit in the eighth stage (8) is also the same as that of the sixth stage (6), and will not be repeated. Accordingly, the equivalent circuit diagram of the eighth stage (8) can also refer to the equivalent circuit diagram 16 of the sixth stage (6) and will not be shown.

[0171] In the ninth stage (9), the potential of the second power supply signal provided by the second power supply terminal VDD2, the potential of the second clock signal provided by the second clock terminal P_ECK2, and the potential of the third clock signal provided by the third clock terminal ECK are all high potentials. The potential of the start signal provided by the start terminal ESTV, the potential of the first power supply signal provided by the first power supply terminal VDD1, and the potential of the first clock signal provided by the first clock terminal P_ECK1 are all low potentials. Moreover, at this time, the potential of the first pull-up node PU1(n-1) and the potential of the second pull-up node PU2(n-1) of the cascaded upper-level shift register unit are both low potentials, that is, the potential of the first reset signal and the potential of the second reset signal are both low potentials. Since the signal timing is the same as that of the fifth stage (5), the driving principle of the shift register unit in the ninth stage (9) is also the same as that of the fifth stage (5), and will not be repeated. Accordingly, the equivalent circuit diagram of the ninth stage (9) can also refer to the equivalent circuit diagram 15 of the fifth stage (5) and will not be shown.

[0172] In the tenth stage (10), the potential of the second power supply signal provided by the second power supply terminal VDD2 is a high potential. The potential of the start signal provided by the start terminal ESTV, the potential of the first power supply signal provided by the first power supply terminal VDD1, the potential of the first clock signal provided by the first clock terminal P_ECK1, the potential of the second clock signal provided by the second clock terminal P_ECK2, and the potential of the third clock signal provided by the third clock terminal ECK are all low potentials. Moreover, at this time, the potential of the first pull-up node PU1 (n-1) and the potential of the second pull-up node PU2 (n-1) of the cascaded upper-level shift register unit are both low potentials, that is, the potential of the first reset signal and the potential of the second reset signal are both low potentials. Since the signal timing is the same as that of the sixth stage (6), the driving principle of the shift register unit in the tenth stage (10) is also the same as that of the sixth stage (6), and will not be repeated. Accordingly, the equivalent circuit diagram of the tenth stage (10) can also refer to the equivalent circuit diagram 16 of the sixth stage (6) and will not be shown.

[0173] In the eleventh stage (11), the potential of the second power signal provided by the second power supply terminal VDD2, the potential of the start signal provided by the start terminal STV, the potential of the second clock signal provided by the second clock terminal ECK2, and the potential of the third clock signal provided by the third clock terminal ECK are all high potentials. The potential of the first power signal provided by the first power supply terminal VDD1 and the potential of the first clock signal provided by the first clock terminal P_ECK1 are all low potentials. Moreover, at this time, the potential of the second pull-up node PU2(n-1) of the cascaded previous stage shift register unit is high potential, that is, the potential of the second reset signal is high potential. The potential of the first pull-up node PU1(n-1) of the cascaded previous stage shift register unit is low potential, that is, the potential of the first reset signal is low potential. Accordingly, the second transistor M2, the third transistor M3 and the sixth transistor M6 can all be turned on, while the first transistor M1, the fourth transistor M4 and the fifth transistor M5 can all be turned off. Furthermore, the low-potential pull-down signal can be transmitted to the first pull-up node PU1 via the turned-on second transistor M2 to discharge the first pull-up node PU1, and transmitted to the pull-down control node PD_C via the turned-on sixth transistor M6 to discharge the pull-down control node PD_C. The high-potential start signal can be transmitted to the second pull-up node PU2 via the turned-on third transistor M3 to charge the second pull-up node PU2. Accordingly, the ninth transistor M9, the eleventh transistor M11, and the fourteenth transistor M14 can all be turned on, while the seventh transistor M7, the eighth transistor M8, the tenth transistor M10, and the thirteenth transistor M13 can all be turned off. Furthermore, the low-potential pull-down signal can be transmitted to the pull-down node PD via the turned-on ninth transistor M9 to discharge the pull-down node PD. Accordingly, the twelfth transistor M12 can be further turned off. Furthermore, the high-potential pull-up signal can be transmitted to the series node N1 via the turned-on fourteenth transistor M14, and transmitted to the output terminal Eout via the turned-on eleventh transistor M11.

[0174] That is, in the eleventh stage (11), a high potential signal can be output through the output terminal Eout. For example, FIG17 shows an equivalent circuit diagram of the shift register unit in the eleventh stage (11). When the eleventh transistor M11 turns on and transmits a high potential pull-up signal to the output terminal Eout, the potential of the second pull-up node PU2 can be raised to a higher potential. Among them, the potential change ΔV of the first pull-up node PU1 is PU1 and the potential change ΔV of the second pull-up node PU2 PU2 Can satisfy: ΔV PU1 =C40 / (CgsM10+C40+C PU1 )*ΔEout; ΔV PU2 =C50 / (CgsM11+C50+C PU2)*ΔEout;

[0175] Wherein, C40 refers to the capacitance of the fourth capacitor C4; C50 refers to the capacitance of the fifth capacitor C5; CgsM10 refers to the parasitic capacitance of the tenth transistor M10; CgsM11 refers to the parasitic capacitance of the eleventh transistor M11; C PU1 Refers to the parasitic capacitance value of the first pull-up node PU1 except C40 and CgsM10; C PU2 It refers to the parasitic capacitance value of the second pull-up node PU2 except C50 and CgsM11; ΔEout refers to the change of the output signal of the output terminal Eout.

[0176] In the twelfth stage (12), the potential of the second power signal provided by the second power supply terminal VDD2 and the potential of the start signal provided by the start terminal STV are both high potentials. The potential of the first power signal provided by the first power supply terminal VDD1, the potential of the first clock signal provided by the first clock terminal P_ECK1, the potential of the second clock signal provided by the second clock terminal ECK2, and the potential of the third clock signal provided by the third clock terminal ECK are all low potentials. Moreover, at this time, the potential of the second pull-up node PU2(n-1) of the cascaded upper-stage shift register unit is high potential, that is, the potential of the second reset signal is high potential. The potential of the first pull-up node PU1(n-1) of the cascaded upper-stage shift register unit is low potential, that is, the potential of the first reset signal is low potential. Accordingly, the second transistor M2 and the sixth transistor M6 can be turned on, while the first transistor M1, the third transistor M3, the fourth transistor M4 and the fifth transistor M5 can be turned off. Furthermore, the low-potential pull-down signal can be transmitted to the first pull-up node PU1 via the turned-on second transistor M2 to discharge the first pull-up node PU1, and transmitted to the pull-down control node PD_C via the turned-on sixth transistor M6 to discharge the pull-down control node PD_C. In addition, under the action of the second capacitor C2, the potential of the second pull-up node PU2 can be maintained at the high potential of the eleventh stage (11). Accordingly, the ninth transistor M9, the eleventh transistor M11, and the fourteenth transistor M14 can be further turned on, while the seventh transistor M7, the eighth transistor M8, the tenth transistor M10, and the thirteenth transistor M13 can be turned off. Furthermore, the low-potential pull-down signal can be transmitted to the pull-down node PD via the turned-on ninth transistor M9 to discharge the pull-down node PD. Accordingly, the twelfth transistor M12 can be further turned off. Furthermore, the high-potential pull-up signal can be transmitted to the series node N1 via the turned-on fourteenth transistor M14, and transmitted to the output terminal Eout via the turned-on eleventh transistor M11.

[0177] That is, in the twelfth stage (12), the high potential signal can continue to be output through the output terminal Eout. For example, FIG18 shows an equivalent circuit diagram of the shift register unit in the twelfth stage (12).

[0178] Among them, in Figures 11 to 18, the "dashed line mark ×" is used to indicate that the transistor is turned off. In addition, Figures 11 to 18 also respectively identify the flow direction of high-voltage signals and low-voltage signals. Based on Figure 10 and in combination with Figures 11 to 18, Figure 19 shows a signal simulation diagram, and in this simulation diagram, the horizontal axis refers to time, the unit is microseconds (μs), and the vertical axis refers to voltage, the unit is volts (V). In addition, it should be noted that the first stage of step 901 may refer to the first stage 1 recorded in the above embodiment, and the second stage of step 902 may refer to the fifth stage 5 recorded in the above embodiment.

[0179] It should be noted that, since the driving method has substantially the same technical effects as the shift register unit described in the aforementioned embodiment, the technical effects of the driving method will not be repeatedly described here for the purpose of brevity.

[0180] FIG20 is a schematic diagram of the structure of a light-emitting drive circuit provided by an embodiment of the present disclosure. As shown in FIG20 , the light-emitting drive circuit includes: at least two cascaded shift register units EOA as shown in any one of FIG1 to FIG6 . For example, FIG20 schematically shows four cascaded EOAs (1) to EOAs (4).

[0181] As shown in Figure 20, the starting terminal ESTV of the first-stage shift register unit EOA can be externally connected to a terminal that provides a start signal. In the shift register units EOA of the other stages except the first-stage shift register unit EOA, the starting terminal ESTV of each stage shift register unit EOA can be coupled to the output terminal Eout of the cascaded previous stage shift register unit EOA. In addition, referring to Figure 20, it can be seen that the light-emitting drive circuit provided in the embodiment of the present disclosure can be driven by a two-phase clock. That is, at least two cascaded shift register units 00 can be coupled to two first clock terminals P_ECK1 and P_ECB1, two second clock terminals P_ECK2 and P_ECB2, and two third clock terminals ECK and ECB. Each two adjacent cascaded shift register units 00 are coupled to different first clock terminals, different second clock terminals, and different third clock terminals. Of course, this is merely a schematic illustration. For example, in some other embodiments, a four-phase clock drive can also be used. In addition, FIG20 also schematically shows the first power supply terminal VDD1, the second power supply terminal VDD2, the pull-up terminal VGH and the pull-down terminal VGL coupled to each level of the shift register unit.

[0182] FIG21 is a schematic diagram of the structure of a display device provided by an embodiment of the present disclosure. As shown in FIG21 , the display device includes: a display panel 100 and a light-emitting drive circuit 000 as shown in FIG20 . The display panel 100 includes a plurality of pixels. At least one pixel includes the pixel circuit and light-emitting element shown in FIG7 .

[0183] The light-emitting driver circuit 000 is coupled to the pixel circuit and is used to transmit a light-emitting drive signal to the pixel circuit. The pixel circuit is also coupled to the light-emitting element and is used to drive the light-emitting element to emit light in response to the light-emitting control signal. For example, the light-emitting drive signal provided by the light-emitting driver circuit 000 can be referred to in Figure 8.

[0184] Optionally, the display device may be any product or component with a display function, such as electronic paper, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, or a navigation device.

[0185] It should be understood that the terms used in the embodiments of the present disclosure are only used to explain the embodiments of the present disclosure and are not intended to limit the present disclosure. Unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present disclosure should have the common meanings understood by people with ordinary skills in the field to which the present disclosure belongs.

[0186] For example, the words "first", "second" or "third" and similar words used in the patent application specification and claims of this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components.

[0187] Likewise, the words “a” or “an” and the like do not denote a limitation of quantity, but rather denote the presence of at least one.

[0188] Words such as “include” or “comprising” mean that the elements or objects preceding “include” or “comprising” include the elements or objects listed after “include” or “comprising” and their equivalents, and do not exclude other elements or objects.

[0189] "Up," "down," "left," or "right" are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly. "Connected" or "coupled" refers to an electrical connection.

[0190] "And / or" indicates that three relationships can exist. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, and B exists alone. The character " / " generally indicates that the related objects are in an "or" relationship.

[0191] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working processes of the light-emitting driving circuit, shift register unit, each circuit and each sub-circuit described above can refer to the corresponding processes in the method embodiment and will not be repeated here.

[0192] The above description is merely an optional embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present disclosure shall be included in the scope of protection of the present disclosure.

Claims

1. A shift register unit, the shift register unit comprising: An input circuit, coupled to a first clock terminal, a second clock terminal, a first power terminal, a second power terminal, a start terminal, a pull - down terminal, a first pull - up node, and a second pull - up node respectively, for controlling the connection and disconnection between the start terminal and the first pull - up node in response to a first clock signal provided by the first clock terminal, controlling the connection and disconnection between the pull - down terminal and the first pull - up node in response to a second power signal provided by the second power terminal, adjusting the potential of the first pull - up node based on the first power signal provided by the first power terminal, and controlling the connection and disconnection between the start terminal and the second pull - up node in response to a second clock signal provided by the second clock terminal, controlling the connection and disconnection between the pull - down terminal and the second pull - up node in response to the first power signal, and adjusting the potential of the second pull - up node based on the second power signal; A pull - down circuit, coupled to a third clock terminal, the first pull - up node, the second pull - up node, the pull - down terminal, a first reset terminal, a second reset terminal, and a pull - down node respectively, for controlling the connection and disconnection between the third clock terminal and the pull - down node in response to a third clock signal provided by the third clock terminal, a first reset signal provided by the first reset terminal, and a second reset signal provided by the second reset terminal, controlling the connection and disconnection between the pull - down terminal and the pull - down node in response to the potential of the first pull - up node, and controlling the connection and disconnection between the pull - down terminal and the pull - down node in response to the potential of the second pull - up node; An output circuit, coupled to the first pull - up node, the second pull - up node, the pull - down node, a pull - up terminal, the pull - down terminal, and an output terminal respectively, for controlling the connection and disconnection between the pull - up terminal and the output terminal in response to the potential of the first pull - up node, controlling the connection and disconnection between the pull - up terminal and the output terminal in response to the potential of the second pull - up node, and controlling the connection and disconnection between the pull - down terminal and the output terminal in response to the potential of the pull - down node.

2. The shift register unit according to claim 1, wherein, The input circuit includes: A first input sub - circuit, coupled to the first clock terminal, the first power terminal, the second power terminal, the start terminal, the pull - down terminal, and the first pull - up node respectively, for controlling the connection and disconnection between the start terminal and the first pull - up node in response to the first clock signal, controlling the connection and disconnection between the pull - down terminal and the first pull - up node in response to the second power signal, and adjusting the potential of the first pull - up node based on the first power signal; A second input sub - circuit, coupled to the second clock terminal, the first power terminal, the second power terminal, the start terminal, the pull - down terminal, and the second pull - up node respectively, for controlling the connection and disconnection between the start terminal and the second pull - up node in response to the second clock signal, controlling the connection and disconnection between the pull - down terminal and the second pull - up node in response to the first power signal, and adjusting the potential of the second pull - up node based on the second power signal.

3. The shift register unit according to claim 2, wherein The first input sub - circuit includes: a first transistor, a second transistor, and a first capacitor; The gate of the first transistor is coupled to the first clock terminal, the first pole of the first transistor is coupled to the start terminal, and the second pole of the first transistor is coupled to the first pull-up node; The gate of the second transistor is coupled to the second power supply terminal, the first pole of the second transistor is coupled to the pull-down terminal, and the second pole of the second transistor is coupled to the first pull-up node; The first end of the first capacitor is coupled to the first power supply terminal, and the second end of the first capacitor is coupled to the first pull-up node.

4. The shift register unit according to claim 2 or 3, wherein, The second input sub-circuit includes: a third transistor, a fourth transistor, and a second capacitor; The gate of the third transistor is coupled to the second clock terminal, the first pole of the third transistor is coupled to the start terminal, and the second pole of the third transistor is coupled to the second pull-up node; The gate of the fourth transistor is coupled to the first power supply terminal, the first pole of the fourth transistor is coupled to the pull-down terminal, and the second pole of the fourth transistor is coupled to the second pull-up node; The first end of the second capacitor is coupled to the second power supply terminal, and the second end of the second capacitor is coupled to the second pull-up node.

5. The shift register unit according to any one of claims 1 to 4, wherein The pull-down circuit includes: A pull-down control sub-circuit, which is respectively coupled to the third clock terminal, the first reset terminal, the second reset terminal, the pull-down terminal, and the pull-down control node, and is used to control the on / off of the connection between the pull-down terminal and the pull-down control node in response to the first reset signal and the second reset signal, and adjust the potential of the pull-down control node based on the third clock signal; A pull-down sub-circuit, which is respectively coupled to the pull-down control node, the third clock terminal, the first pull-up node, the second pull-up node, the pull-down node, and the pull-down terminal, and is used to control the on / off of the connection between the third clock terminal and the pull-down node in response to the potential of the pull-down control node, control the on / off of the connection between the pull-down terminal and the pull-down node in response to the potential of the first pull-up node, and control the on / off of the connection between the pull-down terminal and the pull-down node in response to the potential of the second pull-up node.

6. The shift register unit according to claim 5, wherein, The pull-down control sub-circuit includes: a fifth transistor, a sixth transistor, and a third capacitor; The gate of the fifth transistor is coupled to the first reset terminal, the first pole of the fifth transistor is coupled to the pull-down terminal, and the second pole of the fifth transistor is coupled to the pull-down control node; The gate of the sixth transistor is coupled to the second reset terminal, the first pole of the sixth transistor is coupled to the pull-down terminal, and the second pole of the sixth transistor is coupled to the pull-down control node; The first end of the third capacitor is coupled to the third clock terminal, and the second end of the third capacitor is coupled to the pull-down control node.

7. The shift register unit according to claim 5 or 6, wherein, The pull-down sub-circuit includes: a seventh transistor, an eighth transistor, and a ninth transistor; The gate of the seventh transistor is coupled to the pull-down control node, the first pole of the seventh transistor is coupled to the third clock terminal, and the second pole of the seventh transistor is coupled to the pull-down node; The gate of the eighth transistor is coupled to the first pull-up node, the first pole of the eighth transistor is coupled to the pull-down end, and the second pole of the eighth transistor is coupled to the pull-down node; The gate of the ninth transistor is coupled to the second pull-up node, the first pole of the ninth transistor is coupled to the pull-down end, and the second pole of the ninth transistor is coupled to the pull-down node.

8. The shift register unit according to any one of claims 1 to 7, wherein, The output circuit includes: A first output sub-circuit, which is respectively coupled to the first pull-up node, the pull-up end and the output end, and is used to control the on / off between the pull-up end and the output end in response to the potential of the first pull-up node; A second output sub-circuit, which is respectively coupled to the second pull-up node, the pull-up end and the output end, and is used to control the on / off between the pull-up end and the output end in response to the potential of the second pull-up node; A third output sub-circuit, which is respectively coupled to the pull-down node, the pull-down end and the output end, and is used to control the on / off between the pull-down end and the output end in response to the potential of the pull-down node.

9. The shift register unit according to claim 8, wherein, The first output sub-circuit includes: a tenth transistor and a fourth capacitor; The gate of the tenth transistor is coupled to the first pull-up node, the first pole of the tenth transistor is coupled to the pull-up end, and the second pole of the tenth transistor is coupled to the output end; The first end of the fourth capacitor is coupled to the first pull-up node, and the second end of the fourth capacitor is coupled to the output end.

10. The shift register unit according to claim 8 or 9, wherein The second output sub-circuit includes: an eleventh transistor and a fifth capacitor; The gate of the eleventh transistor is coupled to the second pull-up node, the first pole of the eleventh transistor is coupled to the pull-up end, and the second pole of the eleventh transistor is coupled to the output end; The first end of the fifth capacitor is coupled to the second pull-up node, and the second end of the fifth capacitor is coupled to the output end.

11. The shift register unit according to any one of claims 8 to 10, wherein The third output sub-circuit includes: a twelfth transistor and a sixth capacitor; The gate of the twelfth transistor is coupled to the pull-down node, the first pole of the twelfth transistor is coupled to the pull-down end, and the second pole of the twelfth transistor is coupled to the output end; The first end of the sixth capacitor is coupled to the pull-down node, and the second end of the sixth capacitor is coupled to the pull-down end.

12. The shift register unit according to claim 11, wherein, The twelfth transistor includes: two transistors connected in series between the output end and the pull-down end.

13. The shift register unit according to claim 12, wherein, The shift register unit further includes: An anti-leakage circuit, which is respectively coupled to the first pull-up node, the second pull-up node, the pull-up end and the series node of the two transistors connected in series in the twelfth transistor, and is used to respond to the first potential of the pull-up node to control the on / off between the pull-up end and the series node, and to control the on / off between the pull-up end and the series node in response to the potential of the second pull-up node.

14. The shift register unit according to claim 13, wherein, The anti-leakage circuit includes: a thirteenth transistor and a fourteenth transistor; The gate of the thirteenth transistor is coupled to the first pull-up node, the first pole of the thirteenth transistor is coupled to the pull-up end, and the second pole of the thirteenth transistor is coupled to the series node; The gate of the fourteenth transistor is coupled to the second pull-up node, the first pole of the fourteenth transistor is coupled to the pull-up terminal, and the second pole of the fourteenth transistor is coupled to the series node.

15. The shift register unit according to any one of claims 1 to 14, wherein, The output terminal is used to be coupled to the light-emitting control terminal of the pixel circuit.

16. The shift register unit according to any one of claims 1 to 15, wherein Each transistor in the shift register unit includes: an N-type transistor.

17. The shift register unit according to claim 16, wherein, The material of the N-type transistor includes: an oxide material.

18. A driving method for a shift register unit, the method being used to drive the shift register unit according to any one of claims 1 to 17, the method comprising: In a first stage, the potential of the first power signal provided by the first power supply terminal and the potential of the first clock signal provided by the first clock terminal are both a first potential, and the potential of the second power signal provided by the second power supply terminal and the potential of the second clock signal provided by the second clock terminal are both a second potential; The input circuit controls the start terminal to conduct with the first pull-up node in response to the first clock signal, and controls the pull-down terminal to conduct with the second pull-up node in response to the first power signal, and the potential of the start signal provided by the start terminal is a first potential; the pull-down circuit controls the pull-down terminal to conduct with the pull-down node in response to the potential of the first pull-up node; The output circuit controls the pull-up terminal to conduct with the output terminal in response to the potential of the first pull-up node; In a second stage, the potential of the second power signal and the potential of the second clock signal are a first potential, and the potential of the first power signal and the potential of the first clock signal are a second potential; the input The circuit controls the start terminal to conduct with the second pull-up node in response to the second clock signal, and controls the pull-down terminal to conduct with the first pull-up node in response to the second power signal, and the potential of the start signal is a second potential; the pull-down circuit controls the third clock terminal to conduct with the pull-down node in response to the third clock signal provided by the third clock terminal, and the potential of the third clock signal is a first potential; The output circuit controls the pull-down terminal to conduct with the output terminal in response to the potential of the pull-down node.

19. A light-emitting driving circuit, the light-emitting driving circuit comprising: At least two cascaded shift register units according to any one of claims 1 to 17.

20. A display device, the display device comprising: A display panel, and a light-emitting driving circuit according to claim 19; The display panel includes a plurality of pixels; the pixels include pixel circuits and light-emitting elements; The light-emitting driving circuit is coupled to the pixel circuit and is used to transmit a light-emitting driving signal to the pixel circuit; The pixel circuit is further coupled to the light-emitting element and is used to drive the light-emitting element to emit light in response to the light-emitting control signal.

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