Shift register, display substrate and display panel

Abstract

A shift register, a display substrate and a display panel, belonging to the technical field of display. The shift register comprises: a first input sub-circuit (11), a second input sub-circuit (12), a first control sub-circuit (21), a second control sub-circuit (22), a first output sub-circuit (31), and a second output sub-circuit (32). The shift register further comprises a first anti-electric leakage sub-circuit (41), and / or a second anti-electric leakage sub-circuit (42). In response to a first clock signal (CK), the first anti-electric leakage sub-circuit (41) is configured to prevent a leakage current generated by the second input sub-circuit (12) from flowing into a second node (N2). In response to the voltage of the second node (N2), the second anti-electric leakage sub-circuit (42) is configured to prevent a leakage current generated by the first control sub-circuit (21) from flowing into a first node (N1). The shift register has good resistance to electric leakage and reliability.

Description

Shift register, display substrate, and display panel Technical Field

[0001] The present disclosure belongs to the field of display technology, and particularly relates to a shift register, a display substrate, and a display panel. Background Art

[0002] In existing technologies, pixel driver circuits typically use low-temperature polycrystalline oxide technology to achieve narrow bezels, low power consumption, and high reliability. However, oxide thin-film transistors (TFTs) have poor stability and their threshold voltage (Vth) is prone to negative bias, which can cause leakage current in the circuit, resulting in additional power consumption, reduced circuit reliability, and even circuit failure. Summary of the Invention

[0003] The present invention aims to solve at least one of the technical problems existing in the prior art and provides a shift register, a display substrate and a display panel with leakage resistance.

[0004] In a first aspect, the present disclosure provides a shift register, comprising: a first input subcircuit, a second input subcircuit, a first control subcircuit, a second control subcircuit, a first output subcircuit, and a second output subcircuit;

[0005] The first input sub-circuit is configured to transmit a first level signal to a first node in response to a first clock signal; the first node is a connection node between the first input sub-circuit, the first control sub-circuit, and the second control sub-circuit;

[0006] The second input sub-circuit is configured to transmit an input signal to a second node in response to the first clock signal; the second node is a connection node between the second input sub-circuit, the first control sub-circuit, and the second output sub-circuit;

[0007] The first control subcircuit is configured to transmit the first clock signal to the first node in response to the voltage of the second node;

[0008] The second control subcircuit is configured to transmit the second clock signal to a third node in response to the voltage of the first node and the second clock signal; the third node is a connection node among the second control subcircuit, the third control subcircuit, and the first output subcircuit;

[0009] The first output sub-circuit is configured to output the second level signal through the signal output terminal in response to the voltage of the third node;

[0010] The second output sub-circuit is configured to output the first level signal through the signal output terminal in response to the voltage of the second node;

[0011] The shift register further includes a first leakage prevention electronic circuit configured to prevent leakage current generated by the second input subcircuit from flowing into the second node in response to the first clock signal;

[0012] And / or, the shift register further includes a second leakage prevention electronic circuit; the second leakage prevention electronic circuit is configured to prevent leakage current generated by the first control subcircuit from flowing into the first node in response to the voltage of the second node.

[0013] Preferably, the second input subcircuit includes a third transistor; when the shift register includes the first anti-leakage electronic circuit, the first anti-leakage electronic circuit includes a first drain transistor and a second drain transistor; wherein,

[0014] The control electrode of the third transistor and the control electrode of the first drain transistor are both connected to the first clock signal terminal; the first electrode of the third transistor is connected to the input signal terminal, and the second electrode is connected to the first electrode of the first drain transistor; the second electrode of the first drain transistor is connected to the second node; the control electrode of the second drain transistor is connected to the second node, the first electrode is connected to the second electrode of the third transistor, and the second electrode is connected to the first level signal terminal.

[0015] Preferably, the second input subcircuit includes a third transistor; when the shift register includes a first anti-leakage electronic circuit, the first anti-leakage electronic circuit includes a first double-gate transistor; wherein,

[0016] The control electrode of the third transistor and the first gate of the first dual-gate transistor are both connected to the first clock signal terminal; the first electrode of the third transistor is connected to the input signal terminal, and the second electrode is connected to the first electrode and the second gate of the first dual-gate transistor; the second electrode of the first dual-gate transistor is connected to the second node.

[0017] Preferably, the first control subcircuit includes a second transistor; when the shift register includes the second anti-leakage electronic circuit, the second anti-leakage electronic circuit includes a third drain transistor and a fourth drain transistor; wherein,

[0018] The control electrode of the second transistor and the control electrode of the third drain transistor are both connected to the second node; the first electrode of the second transistor is connected to the first clock signal end, and the second electrode is connected to the second electrode of the third drain transistor and the second electrode of the fourth drain transistor; the first electrode of the third drain transistor is connected to the first node; the control electrode of the fourth drain transistor is connected to the first node, and the first electrode is connected to the first level signal end.

[0019] Preferably, the first control subcircuit includes a second transistor; when the shift register includes the second anti-leakage electronic circuit, the second anti-leakage electronic circuit includes a second dual-gate transistor; wherein,

[0020] The control electrode of the second transistor and the first gate of the second dual-gate transistor are both connected to the second node; the first electrode of the second transistor is connected to the second electrode and the second gate of the second dual-gate transistor, and the second electrode is connected to the first clock signal terminal; the first electrode of the second dual-gate transistor is connected to the first node.

[0021] Preferably, the width-to-length ratios of the third transistor and the first drain transistor are both smaller than the width-to-length ratio of the second drain transistor;

[0022] The width-to-length ratios of the second transistor and the third drain transistor are both smaller than the width-to-length ratio of the fourth drain transistor.

[0023] Preferably, it further includes a third control subcircuit;

[0024] The third control sub-circuit is configured to transmit a second level signal to the third node in response to the voltage of the second node.

[0025] Preferably, it further includes a fourth control subcircuit;

[0026] The fourth control sub-circuit is configured to transmit the second-level signal to the second node in response to the voltage of the first node, the second clock signal, and the voltage of the third node.

[0027] Preferably, the first input sub-circuit comprises a first transistor;

[0028] The control electrode of the first transistor is connected to the first clock signal terminal, the first electrode is connected to the first level signal terminal, and the second electrode is connected to the first node.

[0029] Preferably, the second control subcircuit includes a fourth transistor, a fifth transistor and a first capacitor;

[0030] The control electrode of the fourth transistor is connected to the first node, the first electrode is connected to the second clock signal terminal, and the second electrode is connected to the first electrode of the fifth transistor;

[0031] The control electrode of the fifth transistor is connected to the second clock signal terminal, the first electrode is connected to the second electrode of the fourth transistor, and the second electrode is connected to the third node;

[0032] One electrode of the first capacitor is connected to the first level signal terminal, and the other electrode is connected to the first node.

[0033] Preferably, the first output sub-circuit includes a seventh transistor and a second capacitor;

[0034] The control electrode of the seventh transistor is connected to the third node, the first electrode is connected to the second level signal terminal, and the second electrode is connected to the signal output terminal of the shift register;

[0035] One electrode of the second capacitor is connected to the third node, and the other electrode is connected to the second level signal terminal.

[0036] Preferably, the second output sub-circuit includes an eighth transistor and a third capacitor;

[0037] The control electrode of the eighth transistor is connected to the second node, a first electrode is connected to the signal output end of the shift register, and the other electrode is connected to the first level signal end;

[0038] One electrode of the third capacitor is connected to the second node, and the other electrode is connected to the first electrode of the eighth transistor.

[0039] Preferably, the second output sub-circuit includes a third dual-gate transistor and a third capacitor;

[0040] The first gate of the third dual-gate transistor is connected to the second node, the first electrode and the second gate are both connected to the signal output terminal, and the second electrode is connected to the first level signal terminal;

[0041] One electrode of the third capacitor is connected to the second node, and the other electrode is connected to the signal output end.

[0042] Preferably, the third control subcircuit includes a sixth transistor;

[0043] The control electrode of the sixth transistor is connected to the second node, the first electrode is connected to the third node, and the second electrode is connected to the second level signal terminal.

[0044] Preferably, the fourth control subcircuit includes a ninth transistor, a tenth transistor and an eleventh transistor;

[0045] The control electrode of the ninth transistor is connected to the first node, the first electrode is connected to the second level signal terminal, and the second electrode is connected to the first electrode of the tenth transistor;

[0046] The control electrode of the tenth transistor is connected to the second clock signal terminal, and the second electrode is connected to the fourth node; the fourth node is the connection node between the tenth transistor and the eleventh transistor;

[0047] The control electrode of the eleventh transistor is connected to the third node, the first electrode is connected to the fourth node, and the second electrode is connected to the second node.

[0048] Preferably, the shift register further comprises a third anti-leakage electronic circuit;

[0049] The third leakage prevention circuit is configured to prevent leakage current at the first node from flowing into the fourth node.

[0050] Preferably, the third anti-leakage electronic circuit comprises a fifth drain transistor and a sixth drain transistor; wherein,

[0051] The control electrode of the fifth drain transistor and the control electrode of the eleventh transistor are both connected to the third node; the first electrode of the eleventh transistor is connected to the second electrode of the fifth drain transistor and the second electrode of the sixth drain transistor, and the second electrode is connected to the second node; the first electrode of the fifth drain transistor is connected to the fourth node; the control electrode of the sixth drain transistor is connected to the fourth node, and the first electrode is connected to the first level signal terminal.

[0052] Preferably, the third anti-leakage electronic circuit comprises a fourth dual-gate transistor; wherein,

[0053] The first gate of the fourth dual-gate transistor and the control electrode of the eleventh transistor are both connected to the third node; the first electrode of the fourth dual-gate transistor is connected to the fourth node, and the second electrode and the second gate are both connected to the first electrode of the eleventh transistor; the second electrode of the eleventh transistor is connected to the second node.

[0054] Preferably, the width-to-length ratios of the eleventh transistor and the fifth drain transistor are both smaller than the width-to-length ratio of the sixth drain transistor.

[0055] Preferably, the first input sub-circuit, the second input sub-circuit, the first control sub-circuit, the second control sub-circuit, the first output sub-circuit and the second output sub-circuit all include transistors, and all of the transistors are oxide transistors.

[0056] In a second aspect, the present disclosure provides a display substrate, comprising: a substrate, and a plurality of the above-mentioned shift registers cascaded on the substrate.

[0057] In a third aspect, the present disclosure provides a display panel comprising the above-mentioned display substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] FIG1 is a schematic structural diagram of an existing shift register;

[0059] FIG2 is a diagram showing simulation results of an existing shift register;

[0060] FIG3 is another simulation result diagram of the existing shift register;

[0061] FIG4 is a schematic structural diagram of a shift register according to a first example of the present disclosure;

[0062] FIG5 is a block diagram of the structure of the shift register in FIG4 ;

[0063] FIG6 is a schematic structural diagram of a second example shift register of the present disclosure;

[0064] FIG7 is a schematic structural diagram of a shift register according to a third example of the present disclosure;

[0065] FIG8 is a schematic structural diagram of a shift register according to a fourth example of the present disclosure;

[0066] FIG9 is a diagram showing simulation results of the shift register according to the fourth example of the present disclosure. DETAILED DESCRIPTION

[0067] In order to enable those skilled in the art to better understand the technical solution of the present invention, the present invention is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0068] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by people with ordinary skills in the field to which this disclosure belongs. The words "first", "second" and similar words used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one", "an" or "the" do not indicate a quantity limitation, but rather indicate the existence of at least one. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0069] It should be noted that the transistors in the embodiments of the present disclosure are oxide transistors. Due to their structural characteristics, oxide transistors are easily affected by external environments such as temperature, resulting in a drift in the threshold voltage (Vth), which affects the stability and reliability of the transistors and, in turn, the display effect of the display panel. Optionally, the switching characteristics of the transistors in the embodiments of the present disclosure can be N-type or P-type. For ease of description, the following description only assumes that the transistors are N-type.

[0070] In the embodiments of the present disclosure, the source and drain of each transistor are structurally indistinguishable and can be interchanged. Here, in order to distinguish the two poles other than the gate, one of the poles is referred to as the source and the other as the drain. The first pole can be the source and the second pole can be the drain. For an N-type transistor, when a high-level signal is input to the gate, the transistor is turned on, and when a low-level signal is input to the gate, the transistor is turned off. For a P-type transistor, when a low-level signal is input to the gate, the transistor is turned on, and when a high-level signal is input to the gate, the transistor is turned off. The dual-gate transistor has a first gate, a second gate, a first pole and a second pole. The first gate and the second gate are structurally indistinguishable, and one of them can be a top gate and the other a bottom gate.

[0071] In the embodiments of the present disclosure, the first level signal can be a high level signal or a low level signal, depending on the switching characteristics of the transistor. Accordingly, the second level signal has the same absolute value as the first level signal but an opposite sign. The input signal in the present disclosure can be an STV signal or the output signal of the previous stage circuit.

[0072] FIG1 shows an existing shift register. As shown in FIG1 , the shift register includes a first input subcircuit 11 , a second input subcircuit 12 , a first control subcircuit 21 , a second control subcircuit 22 , a first output subcircuit 31 , and a second output subcircuit 32 .

[0073] The first input sub-circuit 11 is configured to transmit a first-level signal VGH to a first node N1 in response to a first clock signal CK. The second input sub-circuit 12 is configured to transmit an input signal STV to a second node N2 in response to the first clock signal CK. The first control sub-circuit 21 is configured to transmit the first clock signal CK to the first node N1 in response to a voltage at the second node N2. The second control sub-circuit 22 is configured to transmit a second clock signal CB to a third node N3 in response to a voltage at the first node N1 and a second clock signal CB. The first output sub-circuit 31 is configured to output a second-level signal VGL through a signal output terminal OUT in response to a voltage at the third node N3. The second output sub-circuit 32 is configured to output a first-level signal VGH through a signal output terminal OUT in response to a voltage at the second node N2.

[0074] It should be noted here that the first node N1 is the connection node of the first input sub-circuit 11, the first control sub-circuit 21 and the second control sub-circuit 22, the second node N2 is the connection node of the second input sub-circuit 12, the first control sub-circuit 21 and the second output sub-circuit 32, and the third node N3 is the connection node of the second control sub-circuit 22 and the first output sub-circuit 31.

[0075] In some examples, the first input sub-circuit 11 includes a first transistor T1; the control electrode of the first transistor T1 is connected to the first clock signal CK terminal, the first electrode is connected to the first level signal VGH terminal, and the second electrode is connected to the first node N1. When a high-level signal is written to the control electrode of the first transistor T1, the first transistor is turned on, and the first level signal VGH is written to the first node N1 through the first transistor T1.

[0076] In some examples, the second input sub-circuit 12 includes a third transistor T3. The third transistor T3 has a control electrode connected to the first clock signal CK terminal, a first electrode connected to the input signal STV terminal, and a second electrode connected to the second node N2. When a high-level signal is written to the control electrode of the third transistor T3, the third transistor turns on, and the input signal STV is written to the second node N2 through the third transistor T3.

[0077] In some examples, the first control subcircuit 21 includes a second transistor T2. The control electrode of the second transistor T2 is connected to the second node N2, the first electrode is connected to the first node N1, and the second electrode is connected to the first clock signal CK terminal. When a high-level signal is written to the control electrode of the second transistor T2, the second transistor turns on, and the first clock signal CK is written to the first node N1 through the second transistor T2.

[0078] In some examples, the second control subcircuit 22 includes a fourth transistor T4, a fifth transistor T5, and a first capacitor. The control electrode of the fourth transistor T4 is connected to the first node N1, the first electrode is connected to the second clock signal CB terminal, and the second electrode is connected to the first electrode of the fifth transistor T5. The control electrode of the fifth transistor T5 is connected to the second clock signal CB terminal, the first electrode is connected to the second electrode of the fourth transistor T4, and the second electrode is connected to the third node N3. One electrode of the first capacitor is connected to the first level signal VGH terminal, and the other electrode is connected to the first node N1. When a high-level signal is written to the control electrode of the fourth transistor T4 and the control electrode of the fifth transistor T5, both the fourth transistor T4 and the fifth transistor T5 are turned on, and the second clock signal CB is written to the third node N3 through the fourth transistor T4 and the fifth transistor T5.

[0079] In some examples, the first output sub-circuit 31 includes a seventh transistor T7 and a second capacitor. The seventh transistor T7 has a control electrode connected to the third node N3, a first electrode connected to the second level signal VGL terminal, and a second electrode connected to the signal output terminal OUT of the shift register. One electrode of the second capacitor is connected to the third node N3, and the other electrode is connected to the second level signal VGL terminal. When a high-level signal is written to the control electrode of the seventh transistor T7, the seventh transistor T7 turns on, and the second level signal VGL is transmitted through the seventh transistor T7 to the signal output terminal OUT.

[0080] In some examples, the second output sub-circuit 32 includes an eighth transistor T8 and a third capacitor. The eighth transistor T8 has a control electrode connected to the second node N2, a first electrode connected to the signal output terminal OUT of the shift register, and another electrode connected to the first level signal VGH terminal. One electrode of the third capacitor is connected to the second node N2, and the other electrode is connected to the first electrode of the eighth transistor T8. When a high-level signal is written to the control electrode of the eighth transistor T8, the eighth transistor T8 turns on, and the first level signal VGH is transmitted through the eighth transistor T8 to the signal output terminal OUT for output.

[0081] Following is the working process of the above shift register.

[0082] In the first phase, a high-level signal is written to the first clock signal CK, and a low-level signal is written to the second clock signal CB. Both the first transistor T1 and the third transistor T3 are turned on, and the first-level signal VGH is written to the first node N1. At this time, the input signal STV is a low-level signal, written to the second node N2, and turns off the second transistor T2. The high-level signal at the first node N1 turns on the fourth transistor T4, and the low-level signal input at the second clock signal CB turns off the fifth transistor T5, resulting in no output from the circuit.

[0083] In the second stage, the first clock signal CK is written into a low-level signal, the second clock signal CB is written into a high-level signal, the fourth transistor T4 and the fifth transistor T5 are both turned on, the second clock signal CB is written into the third node N3 to turn on the seventh transistor T7, and the second-level signal VGL is output to the signal output terminal OUT through the seventh transistor T7.

[0084] In the third stage, the first clock signal CK is written as a high-level signal, the second clock signal CB is written as a low-level signal, the first transistor T1 and the third transistor T3 are turned on, the input signal STV is written as a high-level signal and transmitted to the second node N2, the high-level signal turns on the eighth transistor T8, and the first-level signal VGH is output to the signal output terminal OUT through the eighth transistor T8.

[0085] In the fourth stage, the first clock signal CK is written as a low-level signal, the second clock signal CB is written as a high-level signal, the fourth transistor T4 and the fifth transistor T5 are turned on, the high-level signal is transmitted to the third node N3 to turn on the seventh transistor T7, and the second-level signal VGL is transmitted to the signal output terminal OUT through the seventh transistor T7.

[0086] FIG2 and FIG3 are simulation results of the shift register in FIG1 . As can be seen from the figures, the process window of the existing shift register is [-1V, 3V]. The process window is small and easily causes circuit failure when the transistor is negatively biased.

[0087] Based on this, the present disclosure proposes a shift register with leakage resistance, which not only includes the first input sub-circuit 11, the second input sub-circuit 12, the first control sub-circuit 21, the second control sub-circuit 22, the first output sub-circuit 31, and the second output sub-circuit 32 described above, but also specifically includes a first leakage prevention electronic circuit 41 and / or a second leakage prevention electronic circuit 42. The first leakage prevention electronic circuit 41 is configured to prevent leakage current generated by the second input sub-circuit 12 from flowing into the second node N2 in response to a first clock signal CK. The second leakage prevention electronic circuit 42 is configured to prevent leakage current generated by the first control sub-circuit 21 from flowing into the first node N1 in response to a voltage at the second node N2.

[0088] By adding a first anti-leakage electronic circuit 41 to the shift register of the present embodiment, when the shift register is in the fourth stage, the third transistor T3 can be prevented from being mistakenly turned on due to a negative threshold voltage bias, causing the input signal STV to be written to a high level and mistakenly turning on the eighth transistor T8. In other words, when leakage current flows into the third transistor T3 when it is mistakenly turned on, the leakage current is consumed by the second drain transistor Y2, thereby preventing the leakage current from affecting the eighth transistor T8 and reducing the reliability of the circuit. Similarly, the shift register of the present embodiment also adds a second anti-leakage electronic circuit 42. When the shift register is in the fourth stage, the leakage current generated by the second input sub-circuit 12 is prevented from turning on the second transistor T2 and causing the first clock signal CK to be written to the first node N1. In other words, when the second transistor T2 is mistakenly turned on and a leakage current is generated, the leakage current is consumed by the fourth drain transistor Y4, thereby preventing it from affecting the voltage of the first node N1.

[0089] In order to make the shift register in the embodiment of the present disclosure clearer, the shift register in the embodiment of the present disclosure is described in detail below with reference to specific examples.

[0090] First Example: Figure 4 is a schematic diagram of the structure of the first example shift register provided by the present disclosure, and Figure 5 is a block diagram of its structure. As shown in Figure 4, in addition to the first input subcircuit 11, the second input subcircuit 12, the first control subcircuit 21, the second control subcircuit 22, the first output subcircuit 31, and the second output subcircuit 32 described above, the shift register also includes a first leakage prevention electronic circuit 41 and a second leakage prevention electronic circuit 42. The first leakage prevention electronic circuit 41 is connected to the second input subcircuit 12, and the second leakage prevention electronic circuit 42 is connected to the first control subcircuit 21.

[0091] The structure of a shift register according to a first embodiment is described below. The first input subcircuit 11 includes a first transistor T1. The control electrode of the first transistor T1 is connected to the first clock signal CK, the first electrode is connected to the first level signal VGH, and the second electrode is connected to the first node N1. The second input subcircuit 12 includes a third transistor T3. The control electrode of the third transistor T3 is connected to the first clock signal CK, the first electrode is connected to the input signal STV, and the second electrode is connected to the second node N2. The first control subcircuit 21 includes a second transistor T2. The control electrode of the second transistor T2 is connected to the second node N2, the first electrode is connected to the first node N1, and the second electrode is connected to the first clock signal CK. The second control subcircuit 22 includes a fourth transistor T4, a fifth transistor T5, and a first capacitor. The control electrode of the fourth transistor T4 is connected to the first node N1, the first electrode is connected to the second clock signal CB, and the second electrode is connected to the first electrode of the fifth transistor T5. The control electrode of the fifth transistor T5 is connected to the second clock signal CB, the first electrode is connected to the second electrode of the fourth transistor T4, and the second electrode is connected to the third node N3. One electrode of the first capacitor is connected to the first level signal VGH, and the other electrode is connected to the first node N1. The first output sub-circuit 31 includes a seventh transistor T7 and a second capacitor. The control electrode of the seventh transistor T7 is connected to the third node N3, the first electrode is connected to the second level signal VGL, and the second electrode is connected to the signal output terminal OUT of the shift register. One electrode of the second capacitor is connected to the third node N3, and the other electrode is connected to the second level signal VGL. The second output sub-circuit 32 includes a fourth dual-gate transistor and a third capacitor. The first gate of the fourth dual-gate transistor is connected to the second node N2, the first and second gates are both connected to the signal output terminal OUT, and the second electrode is connected to the first level signal VGH. One electrode of the third capacitor is connected to the second node N2, and the other electrode is connected to the signal output terminal OUT. The first leakage prevention electronic circuit 41 includes a first drain transistor Y1 and a second drain transistor Y2. The control electrode of the first drain transistor Y1 is connected to the first clock signal CK, the first electrode is connected to the second electrode of the third transistor T3, and the second electrode is connected to the second node N2. The control electrode of the second drain transistor Y2 is connected to the second node N2, the first electrode is connected to the second electrode of the third transistor T3, and the second electrode is connected to the first level signal VGH.

[0092] The second leakage prevention circuit 42 includes a third draining transistor Y3 and a fourth draining transistor Y4. The third draining transistor Y3 has a control electrode connected to the second node N2, a first electrode connected to the first node N1, and a second electrode connected to the first electrode of the second transistor T2. The fourth draining transistor Y4 has a control electrode connected to the first node N1, a first electrode connected to the second level signal VGL terminal, and a second electrode connected to the first electrode of the second transistor T2.

[0093] Specifically, the width-to-length ratios of the third transistor T3 and the first draining transistor Y1 are both smaller than the width-to-length ratio of the second draining transistor Y2; and the width-to-length ratios of the second transistor T2 and the third draining transistor Y3 are both smaller than the width-to-length ratio of the fourth draining transistor Y4. Thus, when leakage current is generated by the third transistor T3, the second draining transistor Y2 acts as a large resistor, dissipating the leakage current and preventing it from flowing into the second node N2 and impacting subsequent circuits. The operating principles of the second leakage prevention electronic circuit 42 are similar to those of the first leakage prevention electronic circuit 41 and are not further described here.

[0094] It should be noted that a dual-gate transistor has two gates, namely a first gate and a second gate. The first gate and the second gate are separated by an insulating layer, and a PN junction is formed between the first gate and the source, and between the second gate and the drain. When a certain voltage is applied to the first gate, a reverse bias is formed at the PN junction, thereby controlling the current between the source and the drain. When a certain voltage is applied to the second gate, a forward bias is formed at the PN junction, thereby increasing the current between the source and the drain. Dual-gate transistors have higher reliability and longer lifespan, and can reduce current leakage and charge accumulation.

[0095] 4 , the following is a working process of the shift register of the first embodiment.

[0096] In the first phase, a high-level signal is written to the first clock signal CK, and a low-level signal is written to the second clock signal CB. The first transistor T1 and the third transistor T3 are both turned on, and the first-level signal VGH is written to the first node N1. At this time, the input signal STV is a low-level signal, which is written to the second node N2 and turns off the second transistor T2 and the eighth transistor T8. The high-level signal at the first node N1 turns on the fourth transistor T4, and the low-level signal input at the second clock signal CB turns off the fifth transistor T5, resulting in no output from the circuit.

[0097] In the second stage, the first clock signal CK is written into a low-level signal, the first to third transistors are all turned off, the second clock signal CB is written into a high-level signal, the fourth transistor T4 and the fifth transistor T5 are both turned on, the second clock signal CB is written into the third node N3 to turn on the seventh transistor T7, and the second-level signal VGL is output to the signal output terminal OUT through the seventh transistor T7.

[0098] In the third stage, the first clock signal CK is written as a high-level signal, the second clock signal CB is written as a low-level signal, the first transistor T1 and the third transistor T3 are turned on, the input signal STV is written as a high-level signal and transmitted to the second node N2, the high-level signal turns on the eighth transistor T8, and the first-level signal VGH is output to the signal output terminal OUT through the eighth transistor T8.

[0099] In the fourth stage, a low-level signal is written to the first clock signal CK, and the first to third transistors are all turned off. A high-level signal is written to the second clock signal CB, turning on the fourth transistor T4 and the fifth transistor T5. This high-level signal is transmitted to the third node N3, turning on the seventh transistor T7. The second-level signal VGL is transmitted to the signal output terminal OUT through the seventh transistor T7. During this stage, the third transistor T3 is in the off state, but due to its negative bias, it can be mistakenly turned on, causing the input signal STV, which is written to the high-level signal at this time, to be mistakenly turned on, i.e., leakage current to be transmitted to the second node N2, mistakenly turning on the eighth transistor T8, affecting the output. After connecting the first anti-leakage electronic circuit 41, the leakage current will be consumed by the second drain transistor Y2 and will not be transmitted to the second node N2, affecting subsequent circuits. Optionally, the first control subcircuit 21 of the present disclosure is also connected to the second anti-leakage electronic circuit 42. When the first control subcircuit 21 generates leakage current, it is consumed by the fourth drain transistor Y4, preventing the leakage current from affecting the voltage of the first node N1. Second example: As shown in FIG6 , the difference between the second example and the first example is that the first anti-leakage electronic circuit 41 includes a first dual-gate transistor YY1 , and the second anti-leakage electronic circuit 42 includes a second dual-gate transistor YY2 .

[0100] The structure of a shift register according to a second embodiment is described below. The first input subcircuit 11 includes a first transistor T1. The control electrode of the first transistor T1 is connected to the first clock signal CK, the first electrode is connected to the first level signal VGH, and the second electrode is connected to the first node N1. The second input subcircuit 12 includes a third transistor T3. The control electrode of the third transistor T3 is connected to the first clock signal CK, the first electrode is connected to the input signal STV, and the second electrode is connected to the second node N2. The first control subcircuit 21 includes a second transistor T2. The control electrode of the second transistor T2 is connected to the second node N2, the first electrode is connected to the first node N1, and the second electrode is connected to the first clock signal CK. The second control subcircuit 22 includes a fourth transistor T4, a fifth transistor T5, and a first capacitor. The control electrode of the fourth transistor T4 is connected to the first node N1, the first electrode is connected to the second clock signal CB, and the second electrode is connected to the first electrode of the fifth transistor T5. The control electrode of the fifth transistor T5 is connected to the second clock signal CB, the first electrode is connected to the second electrode of the fourth transistor T4, and the second electrode is connected to the third node N3. One electrode of the first capacitor is connected to the first level signal VGH, and the other electrode is connected to the first node N1. The first output sub-circuit 31 includes a seventh transistor T7 and a second capacitor. The control electrode of the seventh transistor T7 is connected to the third node N3, the first electrode is connected to the second level signal VGL, and the second electrode is connected to the signal output terminal OUT of the shift register. One electrode of the second capacitor is connected to the third node N3, and the other electrode is connected to the second level signal VGL. The second output sub-circuit 32 includes a fourth dual-gate transistor and a third capacitor. The first gate of the fourth dual-gate transistor is connected to the second node N2, the first and second gates are both connected to the signal output terminal OUT, and the second electrode is connected to the first level signal VGH. One electrode of the third capacitor is connected to the second node N2, and the other electrode is connected to the signal output terminal OUT. The first anti-leakage electronic circuit 41 includes a first dual-gate transistor YY1. The first gate of the first dual-gate transistor YY1 is connected to the first clock signal CK, the first and second gates are both connected to the second electrode of the third transistor T3, and the second electrode is connected to the second node N2.

[0101] The second anti-leakage electronic circuit 42 includes a second dual-gate transistor YY2 , wherein the first gate of the second dual-gate transistor YY2 is connected to the second node N2 , the first electrode is connected to the first node N1 , and the second electrode and the second gate are both connected to the first clock signal CK terminal.

[0102] 6 , the following is an operating process of the shift register according to the second embodiment.

[0103] In the first phase, a high-level signal is written to the first clock signal CK, and a low-level signal is written to the second clock signal CB. The first transistor T1 and the third transistor T3 are both turned on, and the first-level signal VGH is written to the first node N1. At this time, the input signal STV is a low-level signal, which is written to the second node N2 and turns off the second transistor T2 and the eighth transistor T8. The high-level signal at the first node N1 turns on the fourth transistor T4, and the low-level signal input at the second clock signal CB turns off the fifth transistor T5, resulting in no output from the circuit.

[0104] In the second stage, the first clock signal CK is written into a low-level signal, the first to third transistors are all turned off, the second clock signal CB is written into a high-level signal, the fourth transistor T4 and the fifth transistor T5 are both turned on, the second clock signal CB is written into the third node N3 to turn on the seventh transistor T7, and the second-level signal VGL is output to the signal output terminal OUT through the seventh transistor T7.

[0105] In the third stage, the first clock signal CK is written as a high-level signal, the second clock signal CB is written as a low-level signal, the first transistor T1 and the third transistor T3 are turned on, the input signal STV is written as a high-level signal and transmitted to the second node N2, the high-level signal turns on the eighth transistor T8, and the first-level signal VGH is output to the signal output terminal OUT through the eighth transistor T8.

[0106] In the fourth stage, a low-level signal is written to the first clock signal CK, and the first to third transistors are all turned off. A high-level signal is written to the second clock signal CB, turning on the fourth transistor T4 and the fifth transistor T5. This high-level signal is transmitted to the third node N3, turning on the seventh transistor T7. The second-level signal VGL is transmitted to the signal output terminal OUT through the seventh transistor T7. During this stage, the third transistor T3 is in the off state, but due to its negative bias, it can be mistakenly turned on, causing the input signal STV, which is written to the high-level signal at this time, to be mistakenly turned on, i.e., leakage current to be transmitted to the second node N2, mistakenly turning on the eighth transistor T8, affecting the output. After connecting the first anti-leakage electronic circuit 41, the leakage current will be consumed by the first dual-gate transistor YY1 and will not be transmitted to the second node N2, affecting subsequent circuits. Optionally, the first control subcircuit 21 of the present disclosure is also connected to the second anti-leakage electronic circuit 42. When the first control subcircuit 21 generates leakage current, it is consumed by the second dual-gate transistor YY2, preventing the leakage current from affecting the voltage of the first node N1.

[0107] Third Example: As shown in Figure 7, the third embodiment differs from the first embodiment in that the shift register further includes a third control subcircuit 23, a fourth control subcircuit 24, and a third leakage prevention electronic circuit. The third control subcircuit 23 is configured to transmit the second level signal VGL to the third node N3 in response to the voltage at the second node N2. The fourth control subcircuit 24 is configured to transmit the second level signal VGL to the second node N2 in response to the voltage at the first node N1, the second clock signal CB, and the voltage at the third node N3. The third leakage prevention electronic circuit is configured to prevent leakage current from the first node N1 from flowing into the fourth node N4. The third leakage prevention electronic circuit is connected to the fourth control subcircuit 24, and the fourth node N4 is the connection node between the third leakage prevention electronic circuit and the fourth control subcircuit 24.

[0108] The structure of a shift register according to a third embodiment is described below. The first input subcircuit 11 includes a first transistor T1. The control electrode of the first transistor T1 is connected to the first clock signal CK, the first electrode is connected to the first level signal VGH, and the second electrode is connected to the first node N1. The second input subcircuit 12 includes a third transistor T3. The control electrode of the third transistor T3 is connected to the first clock signal CK, the first electrode is connected to the input signal STV, and the second electrode is connected to the second node N2. The first control subcircuit 21 includes a second transistor T2. The control electrode of the second transistor T2 is connected to the second node N2, the first electrode is connected to the first node N1, and the second electrode is connected to the first clock signal CK. The second control subcircuit 22 includes a fourth transistor T4, a fifth transistor T5, and a first capacitor. The control electrode of the fourth transistor T4 is connected to the first node N1, the first electrode is connected to the second clock signal CB, and the second electrode is connected to the first electrode of the fifth transistor T5. The control electrode of the fifth transistor T5 is connected to the second clock signal CB, the first electrode is connected to the second electrode of the fourth transistor T4, and the second electrode is connected to the third node N3. One electrode of the first capacitor is connected to the first level signal VGH, and the other electrode is connected to the first node N1. The first output sub-circuit 31 includes a seventh transistor T7 and a second capacitor. The seventh transistor T7 has a control electrode connected to the third node N3, a first electrode connected to the second level signal VGL terminal, and a second electrode connected to the signal output terminal OUT of the shift register. One electrode of the second capacitor is connected to the third node N3, and the other electrode is connected to the second level signal VGL terminal. The second output sub-circuit 32 includes a fourth dual-gate transistor and a third capacitor. The fourth dual-gate transistor has a first gate connected to the second node N2, a first electrode and a second gate both connected to the signal output terminal OUT, and a second electrode connected to the first level signal VGH terminal. One electrode of the third capacitor is connected to the second node N2, and the other electrode is connected to the signal output terminal OUT.

[0109] The first leakage prevention circuit 41 includes a first drain transistor Y1 and a second drain transistor Y2. The first drain transistor Y1 has a control electrode connected to the first clock signal CK terminal, a first electrode connected to the second electrode of the third transistor T3, and a second electrode connected to the second node N2. The second drain transistor Y2 has a control electrode connected to the second node N2, a first electrode connected to the second electrode of the third transistor T3, and a second electrode connected to the first level signal VGH terminal.

[0110] The second leakage prevention circuit 42 includes a third draining transistor Y3 and a fourth draining transistor Y4. The third draining transistor Y3 has a control electrode connected to the second node N2, a first electrode connected to the first node N1, and a second electrode connected to the first electrode of the second transistor T2. The fourth draining transistor Y4 has a control electrode connected to the first node N1, a first electrode connected to the second level signal VGL terminal, and a second electrode connected to the first electrode of the second transistor T2.

[0111] The third control sub-circuit 23 includes a sixth transistor T6 , wherein the control electrode of the sixth transistor T6 is connected to the second node N2 , the first electrode is connected to the third node N3 , and the second electrode is connected to the second level signal VGL terminal.

[0112] The fourth control subcircuit 24 includes a ninth transistor T9, a tenth transistor T10, and an eleventh transistor T11. The ninth transistor T9 has a control electrode connected to the first node N1, a first electrode connected to the second level signal VGL terminal, and a second electrode connected to the first electrode of the tenth transistor T10. The tenth transistor T10 has a control electrode connected to the second clock signal CB terminal, and a second electrode connected to the fourth node N4. The fourth node N4 is the connection node between the tenth transistor T10 and the eleventh transistor T11. The eleventh transistor T11 has a control electrode connected to the third node N3, a first electrode connected to the fourth node N4, and a second electrode connected to the second node N2.

[0113] The third leakage prevention circuit includes a fifth drain transistor Y5 and a sixth drain transistor Y6. The fifth drain transistor Y5 has a control electrode connected to the third node N3, a first electrode connected to the fourth node N4, and a second electrode connected to the first electrode of the eleventh transistor T11. The sixth drain transistor Y6 has a control electrode connected to the fourth node N4, a first electrode connected to the first level signal VGH terminal, and a second electrode connected to the first electrode of the eleventh transistor T11.

[0114] In particular, the width-to-length ratios of the eleventh transistor T11 and the fifth drain transistor Y5 are both smaller than the width-to-length ratio of the sixth drain transistor Y6. Thus, when leakage current is generated in the eleventh transistor T11, the sixth drain transistor Y6 acts as a large resistor, dissipating the leakage current and preventing it from flowing into the fourth node N4 and affecting other circuits.

[0115] 7 , the following is an operating process of the shift register according to the third embodiment.

[0116] In the first phase, a high-level signal is written to the first clock signal CK, and a low-level signal is written to the second clock signal CB. The first transistor T1 and the third transistor T3 are both turned on, the first-level signal VGH is written to the first node N1, and the tenth transistor T10 is turned off. At this time, the input signal STV is a low-level signal, which is written to the second node N2 and turns off the second transistor T2, the sixth transistor T6, and the eighth transistor T8. The high-level signal at the first node N1 turns on the fourth transistor T4, and the low-level signal input at the second clock signal CB turns off the fifth transistor T5, resulting in no output from the circuit.

[0117] In the second stage, the first clock signal CK is written into a low-level signal, the first to third transistors are all turned off, the second clock signal CB is written into a high-level signal, the fourth transistor T4 and the fifth transistor T5 are both turned on, the second clock signal CB is written into the third node N3 to turn on the seventh transistor T7, and the second-level signal VGL is output to the signal output terminal OUT through the seventh transistor T7.

[0118] In the third stage, a high-level signal is written into the first clock signal CK, a low-level signal is written into the second clock signal CB, the first transistor T1 and the third transistor T3 are turned on, the tenth transistor T10 is turned off, the input signal STV is written into a high-level signal and transmitted to the second node N2, the high-level signal turns on the eighth transistor T8, and the first-level signal VGH is output to the signal output terminal OUT through the eighth transistor T8.

[0119] In the fourth stage, a low-level signal is written to the first clock signal CK, and the first to third transistors are all turned off. A high-level signal is written to the second clock signal CB, turning on the fourth transistor T4 and the fifth transistor T5. This high-level signal is transmitted to the third node N3, turning on the seventh transistor T7. The second-level signal VGL is transmitted to the signal output terminal OUT through the seventh transistor T7. During this stage, the third transistor T3 is in the off state, but due to its negative bias, it can be mistakenly turned on, causing the input signal STV, which is written to the high-level signal at this time, to be mistakenly turned on, i.e., leakage current to be transmitted to the second node N2, mistakenly turning on the eighth transistor T8, affecting the output. After connecting the first anti-leakage electronic circuit 41, the leakage current will be consumed by the second drain transistor Y2 and will not be transmitted to the second node N2, affecting subsequent circuits. Optionally, the first control subcircuit 21 of the present disclosure is also connected to the second anti-leakage electronic circuit 42. When the first control subcircuit 21 generates leakage current, it is consumed by the fourth drain transistor Y4, preventing the leakage current from affecting the voltage of the first node N1. Optionally, the fourth control subcircuit 24 of the present disclosure is further connected to a third anti-leakage electronic circuit. When the fourth control subcircuit 24 generates leakage current, the leakage current is consumed by the sixth drain transistor Y6 to prevent the leakage current from affecting the voltage of the fourth node N4.

[0120] Fourth example: As shown in FIG8 , the fourth example differs from the third example in that the first leakage-proof electronic circuit 41 includes a first dual-gate transistor YY1 , the second leakage-proof electronic circuit 42 includes a second dual-gate transistor YY2 , and the third leakage-proof electronic circuit includes a fourth dual-gate transistor.

[0121] The structure of a shift register according to a fourth embodiment is described below. The first input subcircuit 11 includes a first transistor T1. The control electrode of the first transistor T1 is connected to the first clock signal CK, the first electrode is connected to the first level signal VGH, and the second electrode is connected to the first node N1. The second input subcircuit 12 includes a third transistor T3. The control electrode of the third transistor T3 is connected to the first clock signal CK, the first electrode is connected to the input signal STV, and the second electrode is connected to the second node N2. The first control subcircuit 21 includes a second transistor T2. The control electrode of the second transistor T2 is connected to the second node N2, the first electrode is connected to the first node N1, and the second electrode is connected to the first clock signal CK. The second control subcircuit 22 includes a fourth transistor T4, a fifth transistor T5, and a first capacitor. The control electrode of the fourth transistor T4 is connected to the first node N1, the first electrode is connected to the second clock signal CB, and the second electrode is connected to the first electrode of the fifth transistor T5. The control electrode of the fifth transistor T5 is connected to the second clock signal CB, the first electrode is connected to the second electrode of the fourth transistor T4, and the second electrode is connected to the third node N3. One electrode of the first capacitor is connected to the first level signal VGH, and the other electrode is connected to the first node N1. The first output sub-circuit 31 includes a seventh transistor T7 and a second capacitor. The seventh transistor T7 has a control electrode connected to the third node N3, a first electrode connected to the second level signal VGL terminal, and a second electrode connected to the signal output terminal OUT of the shift register. One electrode of the second capacitor is connected to the third node N3, and the other electrode is connected to the second level signal VGL terminal. The second output sub-circuit 32 includes a fourth dual-gate transistor and a third capacitor. The fourth dual-gate transistor has a first gate connected to the second node N2, a first electrode and a second gate both connected to the signal output terminal OUT, and a second electrode connected to the first level signal VGH terminal. One electrode of the third capacitor is connected to the second node N2, and the other electrode is connected to the signal output terminal OUT.

[0122] The first anti-leakage circuit 41 includes a first dual-gate transistor YY1 , wherein the first gate of the first dual-gate transistor YY1 is connected to the first clock signal CK terminal, the first electrode and the second gate are both connected to the second electrode of the third transistor T3 , and the second electrode is connected to the second node N2 .

[0123] The second anti-leakage electron circuit 42 includes a second dual-gate transistor YY2 having a first gate connected to the second node N2, a first electrode connected to the first node N1, and a second electrode and a second gate both connected to the first electrode of the second transistor T2.

[0124] The third control sub-circuit 23 includes a sixth transistor T6 , wherein the control electrode of the sixth transistor T6 is connected to the second node N2 , the first electrode is connected to the third node N3 , and the second electrode is connected to the second level signal VGL terminal.

[0125] The fourth control subcircuit 24 includes a ninth transistor T9, a tenth transistor T10, and an eleventh transistor T11. The ninth transistor T9 has a control electrode connected to the first node N1, a first electrode connected to the second level signal VGL terminal, and a second electrode connected to the first electrode of the tenth transistor T10. The tenth transistor T10 has a control electrode connected to the second clock signal CB terminal, and a second electrode connected to the fourth node N4. The fourth node N4 is the connection node between the tenth transistor T10 and the eleventh transistor T11. The eleventh transistor T11 has a control electrode connected to the third node N3, a first electrode connected to the fourth node N4, and a second electrode connected to the second node N2.

[0126] The third anti-leakage electronic circuit includes a third dual-gate transistor YY3 , wherein the first gate of the third dual-gate transistor YY3 is connected to the third node N3 , the first electrode is connected to the fourth node N4 , and the second electrode and the second gate are both connected to the first electrode of the eleventh transistor T11 .

[0127] 8 , the following is a working process of the shift register according to the third embodiment.

[0128] In the first phase, a high-level signal is written to the first clock signal CK, and a low-level signal is written to the second clock signal CB. The first transistor T1 and the third transistor T3 are both turned on, the first-level signal VGH is written to the first node N1, and the tenth transistor T10 is turned off. At this time, the input signal STV is a low-level signal, which is written to the second node N2 and turns off the second transistor T2, the sixth transistor T6, and the eighth transistor T8. The high-level signal at the first node N1 turns on the fourth transistor T4, and the low-level signal input at the second clock signal CB turns off the fifth transistor T5, resulting in no output from the circuit.

[0129] In the second stage, the first clock signal CK is written into a low-level signal, the first to third transistors are all turned off, the second clock signal CB is written into a high-level signal, the fourth transistor T4 and the fifth transistor T5 are both turned on, the second clock signal CB is written into the third node N3 to turn on the seventh transistor T7, and the second-level signal VGL is output to the signal output terminal OUT through the seventh transistor T7.

[0130] In the third stage, a high-level signal is written into the first clock signal CK, a low-level signal is written into the second clock signal CB, the first transistor T1 and the third transistor T3 are turned on, the tenth transistor T10 is turned off, the input signal STV is written into a high-level signal and transmitted to the second node N2, the high-level signal turns on the eighth transistor T8, and the first-level signal VGH is output to the signal output terminal OUT through the eighth transistor T8.

[0131] In the fourth stage, a low-level signal is written to the first clock signal CK, and the first to third transistors are all turned off. A high-level signal is written to the second clock signal CB, turning on the fourth transistor T4 and the fifth transistor T5. This high-level signal is transmitted to the third node N3, turning on the seventh transistor T7. The second-level signal VGL is transmitted to the signal output terminal OUT through the seventh transistor T7. During this stage, the third transistor T3 is in the off state, but due to its negative bias, it can be mistakenly turned on, causing the input signal STV, which is written to the high-level signal at this time, to be mistakenly turned on, i.e., leakage current to be transmitted to the second node N2, mistakenly turning on the eighth transistor T8, affecting the output. After connecting the first anti-leakage electronic circuit 41, the leakage current will be consumed by the first dual-gate transistor YY1 and will not be transmitted to the second node N2, affecting subsequent circuits. Optionally, the first control subcircuit 21 of the present disclosure is also connected to the second anti-leakage electronic circuit 42. When the first control subcircuit 21 generates leakage current, it is consumed by the second dual-gate transistor YY2, preventing the leakage current from affecting the voltage of the first node N1. Optionally, the fourth control subcircuit 24 of the present disclosure is further connected to a third anti-leakage electronic circuit. When the fourth control subcircuit 24 generates leakage current, the leakage current is consumed by the third dual-gate transistor YY3 to prevent the leakage current from affecting the voltage of the fourth node N4.

[0132] In addition, the embodiment of the present disclosure also provides a simulation result diagram of the shift register after adding the leakage prevention electronic circuit, as shown in FIG9 . It can be seen that the process window of the shift register is [-4V, 3V], which is significantly improved.

[0133] In a second aspect, this embodiment provides a display substrate comprising the shift register according to any of the above embodiments, so that the display substrate has low power consumption, a large process window, and good leakage resistance.

[0134] In a third aspect, embodiments of the present disclosure provide a display panel comprising the above-mentioned display substrate, wherein the display panel can be a display component of any display device having a display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigation system.

[0135] It will be understood that the above embodiments are merely exemplary embodiments for illustrating the principles of the present invention, and the present invention is not limited thereto. Those skilled in the art will appreciate that various modifications and improvements can be made without departing from the spirit and substance of the present invention, and such modifications and improvements are also considered to be within the scope of protection of the present invention.

Claims

1. A shift register, comprising: The first input sub - circuit, the second input sub - circuit, the first control sub - circuit, the second control sub - circuit, the first output sub - circuit and the second output sub - circuit; The first input sub - circuit is configured to transmit a first - level signal to a first node in response to a first clock signal; The first node is a connection node of the first input sub - circuit, the first control sub - circuit and the second control sub - circuit; The second input sub - circuit is configured to transmit an input signal to a second node in response to the first clock signal; The second node is a connection node of the second input sub - circuit, the first control sub - circuit and the second output sub - circuit; The first control sub - circuit is configured to transmit the first clock signal to the first node in response to the voltage of the second node; The second control sub - circuit is configured to transmit the second clock signal to a third node in response to the voltage of the first node and a second clock signal; The third node is a connection node of the second control sub - circuit, the third control sub - circuit and the first output sub - circuit; The first output sub - circuit is configured to output the second - level signal through a signal output terminal in response to the voltage of the third node; The second output sub - circuit is configured to output the first - level signal through the signal output terminal in response to the voltage of the second node; The shift register further includes a first anti - leakage electronic circuit, and the first anti - leakage electronic circuit is configured to prevent the leakage current generated by the second input sub - circuit from flowing into the second node in response to the first clock signal; And / or, the shift register further includes a second anti - leakage electronic circuit; the second anti - leakage electronic circuit is configured to prevent the leakage current generated by the first control sub - circuit from flowing into the first node in response to the voltage of the second node.

2. The shift register according to claim 1, wherein, The second input sub - circuit includes a third transistor; when the shift register includes the first anti - leakage electronic circuit, the first anti - leakage electronic circuit includes a first current - guiding transistor and a second current - guiding transistor; wherein, The control electrode of the third transistor and the control electrode of the first current - guiding transistor are both connected to the first clock signal terminal; the first electrode of the third transistor is connected to the input signal terminal, the second electrode is connected to the first electrode of the first current - guiding transistor; the second electrode of the first current - guiding transistor is connected to the second node; the control electrode of the second current - guiding transistor is connected to the second node, the first electrode is connected to the second electrode of the third transistor, and the second electrode is connected to the first - level signal terminal.

3. The shift register according to claim 1, wherein The second input sub - circuit includes a third transistor; when the shift register includes a first anti - leakage electronic circuit, the first anti - leakage electronic circuit includes a first double - gate transistor; wherein, The control electrode of the third transistor and the first gate of the first double - gate transistor are both connected to the first clock signal terminal; the first electrode of the third transistor is connected to the input signal terminal, the second electrode is connected to the first and second gates of the first double - gate transistor; the second electrode of the first double - gate transistor is connected to the second node.

4. The shift register according to claim 1, wherein, The first control sub - circuit includes a second transistor; when the shift register includes the second anti - leakage electronic circuit, the second anti - leakage electronic circuit includes a third drain transistor and a fourth drain transistor; wherein, The control electrode of the second transistor and the control electrode of the third drain transistor are both connected to the second node; the first electrode of the second transistor is connected to the first clock signal terminal, and the second electrode is connected to the second electrode of the third drain transistor and the second electrode of the fourth drain transistor; the first electrode of the third drain transistor is connected to the first node; the control electrode of the fourth drain transistor is connected to the first node, and the first electrode is connected to the first level signal terminal.

5. The shift register according to claim 1, wherein, The first control sub - circuit includes a second transistor; when the shift register includes the second anti - leakage electronic circuit, the second anti - leakage electronic circuit includes a second double - gate transistor; wherein, The control electrode of the second transistor and the first gate of the second double - gate transistor are both connected to the second node; the first electrode of the second transistor is connected to the second electrode and the second gate of the second double - gate transistor, and the second electrode is connected to the first clock signal terminal; the first electrode of the second double - gate transistor is connected to the first node.

6. The shift register according to claim 2 or 4, wherein, The width - to - length ratios of the third transistor and the first drain transistor are both smaller than the width - to - length ratio of the second drain transistor; The width - to - length ratios of the second transistor and the third drain transistor are both smaller than the width - to - length ratio of the fourth drain transistor.

7. The shift register according to claim 1, wherein, It further includes a third control sub - circuit; The third control sub - circuit is configured to transmit a second level signal to the third node in response to the voltage of the second node.

8. The shift register according to claim 7, wherein, It further includes a fourth control sub - circuit; The fourth control sub - circuit is configured to transmit the second level signal to the second node in response to the voltage of the first node, the second clock signal, and the voltage of the third node.

9. The shift register according to claim 1, wherein, The first input sub - circuit includes a first transistor; The control electrode of the first transistor is connected to the first clock signal terminal, the first electrode is connected to the first level signal terminal, and the second electrode is connected to the first node.

10. The shift register according to claim 1, wherein, The second control sub - circuit includes a fourth transistor, a fifth transistor, and a first capacitor; The control electrode of the fourth transistor is connected to the first node, the first electrode is connected to the second clock signal terminal, and the second electrode is connected to the first electrode of the fifth transistor; The control electrode of the fifth transistor is connected to the second clock signal terminal, the first electrode is connected to the second electrode of the fourth transistor, and the second electrode is connected to the third node; One electrode of the first capacitor is connected to the first level signal terminal, and the other electrode is connected to the first node.

11. The shift register according to claim 1, wherein, The first output sub - circuit includes a seventh transistor and a second capacitor; The control electrode of the seventh transistor is connected to the third node, the first electrode is connected to the second level signal terminal, and the second electrode is connected to the signal output terminal of the shift register; One electrode of the second capacitor is connected to the third node, and the other electrode is connected to the second level signal terminal.

12. The shift register according to claim 1, wherein The second output sub - circuit includes an eighth transistor and a third capacitor; The control electrode of the eighth transistor is connected to the second node, the first electrode is connected to the signal output terminal of the shift register, and the other electrode is connected to the first level signal terminal; One electrode of the third capacitor is connected to the second node, and the other electrode is connected to the first electrode of the eighth transistor.

13. The shift register according to claim 1, wherein, The second output sub-circuit includes a third double-gate transistor and a third capacitor; The first gate of the third double-gate transistor is connected to the second node, the first electrode and the second gate are both connected to the signal output terminal, and the second electrode is connected to the first level signal terminal; One electrode of the third capacitor is connected to the second node, and the other electrode is connected to the signal output terminal.

14. The shift register according to claim 7, wherein, The third control sub-circuit includes a sixth transistor; The control electrode of the sixth transistor is connected to the second node, the first electrode is connected to the third node, and the second electrode is connected to the second level signal terminal.

15. The shift register according to claim 8, wherein, The fourth control sub-circuit includes a ninth transistor, a tenth transistor, and an eleventh transistor; The control electrode of the ninth transistor is connected to the first node, the first electrode is connected to the second level signal terminal, and the second electrode is connected to the first electrode of the tenth transistor; The control electrode of the tenth transistor is connected to the second clock signal terminal, and the second electrode is connected to the fourth node; the fourth node is the connection node of the tenth transistor and the eleventh transistor; The control electrode of the eleventh transistor is connected to the third node, the first electrode is connected to the fourth node, and the second electrode is connected to the second node.

16. The shift register according to claim 1, wherein, The shift register further includes a third anti-leakage electronic circuit; The third anti-leakage electronic circuit is configured to prevent the leakage current of the first node from flowing into the fourth node.

17. The shift register according to claim 15 or 16, wherein, The third anti-leakage electronic circuit includes a fifth drainage transistor and a sixth drainage transistor; wherein, The control electrode of the fifth drainage transistor and the control electrode of the eleventh transistor are both connected to the third node; the first electrode of the eleventh transistor is connected to the second electrode of the fifth drainage transistor and the second electrode of the sixth drainage transistor, and the second electrode is connected to the second node; the first electrode of the fifth drainage transistor is connected to the fourth node; the control electrode of the sixth drainage transistor is connected to the fourth node, and the first electrode is connected to the first level signal terminal.

18. The shift register according to claim 15 or 16, wherein The third anti-leakage electronic circuit includes a fourth double-gate transistor; wherein, The first gate of the fourth double-gate transistor and the control electrode of the eleventh transistor are both connected to the third node; the first electrode of the fourth double-gate transistor is connected to the fourth node, and the second electrode and the second gate are both connected to the first electrode of the eleventh transistor; the second electrode of the eleventh transistor is connected to the second node.

19. The shift register according to claim 17, wherein The aspect ratios of the width to length of the eleventh transistor and the fifth drainage transistor are both smaller than the aspect ratio of the width to length of the sixth drainage transistor.

20. The shift register according to claim 1, wherein, The first input sub-circuit, the second input sub-circuit, the first control sub-circuit, the second control sub-circuit, the first output sub-circuit, and the second output sub-circuit all include transistors, and all the transistors are oxide transistors.

21. A display substrate, comprising: A substrate, and a plurality of shift registers as described in any one of claims 1 to 20 cascaded on the substrate.

22. A display panel, which includes the display substrate as described in claim 21.

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