Display panel and display device

Abstract

A display panel (1100), comprising a plurality of rows of pixel circuits (100) and a first gate driving circuit (110). The plurality of rows of pixel circuits (100) are arranged in a first direction, each of the plurality of rows of pixel circuits (100) comprises a plurality of pixel circuits (100) arranged in a second direction, and the first direction intersects with the second direction. The first gate driving circuit (110) comprises a plurality of first shift registers (G1) arranged in cascade, one first shift register (G1) is configured to be electrically connected to at least two rows of pixel circuits (100), and at least two first shift registers (G1) are connected to the same row of pixel circuits (100).

Description

Display panel and display device

[0001] This application claims priority to Chinese patent application No. 202410010113.3, filed on January 3, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The present disclosure relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0003] With the continuous development of display technology, organic light-emitting diode (OLED) display panels have gradually become one of the mainstream products in the display field due to their excellent performance, such as self-luminescence, no need for backlight, high contrast, thin thickness, wide viewing angle, fast response speed, flexibility, wide operating temperature range, and simple structure and process. OLED display panels can be widely used in terminal products such as smartphones, tablets, TVs, and wearable devices (such as watches). Among them, narrow bezels are an important development direction for display devices. How to reduce the bezel width of display panels is a technical problem that needs to be solved urgently. Summary of the Invention

[0004] In one aspect, a display panel is provided. The display panel comprises multiple rows of pixel circuits and a first gate driver circuit. The multiple rows of pixel circuits are arranged along a first direction, and each of the multiple rows of pixel circuits includes multiple pixel circuits arranged along a second direction, where the first direction intersects the second direction. The first gate driver circuit includes multiple first shift registers arranged in cascade connection, wherein one first shift register is configured to be electrically connected to at least two rows of pixel circuits, and at least two first shift registers are connected to the same row of pixel circuits.

[0005] In some embodiments, the pixel circuit includes a driving transistor, a first reset transistor, a voltage-stabilizing transistor, a first capacitor, and a second capacitor. The control electrode of the driving transistor is electrically connected to the first node, the first electrode is electrically connected to the second node, and the second electrode is electrically connected to the third node. The control electrode of the first reset transistor is electrically connected to the first scan signal line, the first electrode is electrically connected to the first voltage signal line, and the second electrode is electrically connected to the first node. The control electrode of the voltage-stabilizing transistor is electrically connected to the second scan signal line, the first electrode is electrically connected to the second voltage signal line, and the second electrode is electrically connected to one plate of the first capacitor; the other plate of the first capacitor is electrically connected to the second node. One plate of the second capacitor is electrically connected to the first node, and the other plate is electrically connected to the second node. The first scan signal line and the second scan signal line are electrically connected to two first shift registers, respectively.

[0006] In some embodiments, the first scan signal line electrically connected to the pixel circuits in the Nth row is electrically connected to the first shift register in the Nth stage. The second scan signal line electrically connected to the pixel circuits in the Nth row is electrically connected to the first shift register in the (N+K)th stage, where N and K are both positive integers.

[0007] In some embodiments, the first scan signal line electrically connected to the pixel circuits in the Nth row is electrically connected to the first shift register in the (N-M)th stage. The second scan signal line electrically connected to the pixel circuits in the Nth row is electrically connected to the first shift register in the Nth stage. Wherein, N and M are both positive integers.

[0008] In some embodiments, the pixel circuit further includes a first light-emitting control transistor and a second reset transistor. The control electrode of the first light-emitting control transistor is electrically connected to the first light-emitting control signal line, the first electrode is electrically connected to the second node, and the second electrode is electrically connected to the fourth node. The control electrode of the second reset transistor is electrically connected to the third scan signal line, the first electrode is electrically connected to the third voltage signal line, and the second electrode is electrically connected to the fourth node. The display panel further includes a second gate drive circuit, the second gate drive circuit includes a plurality of second shift registers arranged in cascade, and one first light-emitting control signal line is electrically connected to one second shift register. The third scan signal line is electrically connected to one first shift register, and the third scan signal line electrically connected to the pixel circuit in the Nth row is electrically connected to the first shift register in the (N+J)th stage; wherein N and J are both positive integers.

[0009] In some embodiments, when the second scanning signal line electrically connected to the pixel circuit in the Nth row is electrically connected to the first shift register at the (N+K)th stage, the value of J is greater than the value of K.

[0010] In some embodiments, the pixel circuit further includes a first light-emitting control transistor and a second reset transistor. The control electrode of the first light-emitting control transistor is electrically connected to the first light-emitting control signal line, the first electrode is electrically connected to the second node, and the second electrode is electrically connected to the fourth node. The control electrode of the second reset transistor is electrically connected to the third scan signal line, the first electrode is electrically connected to the third voltage signal line, and the second electrode is electrically connected to the fourth node. The display panel further includes a second gate drive circuit and a third gate drive circuit. The second gate drive circuit includes a plurality of second shift registers arranged in cascade, and one first light-emitting control signal line is electrically connected to one second shift register. The third gate drive circuit includes a plurality of third shift registers arranged in cascade, and one third scan signal line is electrically connected to one third shift register.

[0011] In some embodiments, the second voltage signal line and the third voltage signal line are configured to transmit the same voltage signal, and the second voltage signal line and the third voltage signal line are the same signal line. The first electrode of the voltage stabilizing transistor is electrically connected to the fourth node and is electrically connected to the second voltage signal line through the second reset transistor.

[0012] In some embodiments, the second voltage signal line and the third voltage signal line are configured to transmit the same voltage signal, and the second voltage signal line and the third voltage signal line are the same signal line.

[0013] In some embodiments, the second voltage signal line and the third voltage signal line are configured to transmit different voltage signals, and the second voltage signal line and the third voltage signal line are different voltage signal lines.

[0014] In some embodiments, the pixel circuit includes a driving transistor, a first reset transistor, a voltage regulator transistor, a first emission control transistor, a second reset transistor, a first capacitor, and a second capacitor. The driving transistor has a control electrode electrically connected to the first node, a first electrode electrically connected to the second node, and a second electrode electrically connected to the third node. The first reset transistor has a control electrode electrically connected to the first scan signal line, a first electrode electrically connected to the first voltage signal line, and a second electrode electrically connected to the first node. The voltage regulator transistor has a control electrode electrically connected to the second scan signal line, a first electrode electrically connected to the second voltage signal line, and a second electrode electrically connected to one plate of the first capacitor; the other plate of the first capacitor is electrically connected to the second node. One plate of the second capacitor is electrically connected to the first node, and the other plate is electrically connected to the second node. The first emission control transistor has a control electrode electrically connected to the first emission control signal line, a first electrode electrically connected to the second node, and a second electrode electrically connected to a fourth node. The second reset transistor has a control electrode electrically connected to the third scan signal line, a first electrode electrically connected to the third voltage signal line, and a second electrode electrically connected to the fourth node. The first scan signal line and the third scan signal line are electrically connected to two first shift registers, respectively.

[0015] In some embodiments, the pixel circuit includes a driving transistor, a first reset transistor, a voltage-stabilizing transistor, a first light-emitting control transistor, a second reset transistor, a first capacitor, and a second capacitor. The control electrode of the driving transistor is electrically connected to the first node, the first electrode is electrically connected to the second node, and the second electrode is electrically connected to the third node. The control electrode of the first reset transistor is electrically connected to the first scanning signal line, the first electrode is electrically connected to the first voltage signal line, and the second electrode is electrically connected to the first node. The control electrode of the voltage-stabilizing transistor is electrically connected to the second scanning signal line, the first electrode is electrically connected to the second voltage signal line, and the second electrode is electrically connected to one plate of the first capacitor; the other plate of the first capacitor is electrically connected to the second node. One plate of the second capacitor is electrically connected to the first node, and the other plate is electrically connected to the second node. The control electrode of the first light-emitting control transistor is electrically connected to the first light-emitting control signal line, the first electrode is electrically connected to the second node, and the second electrode is electrically connected to the fourth node. The control electrode of the second reset transistor is electrically connected to the third scanning signal line, the first electrode is electrically connected to the third voltage signal line, and the second electrode is electrically connected to the fourth node. The second scanning signal line and the third scanning signal line are electrically connected to two first shift registers respectively.

[0016] In some embodiments, a frame period of the display panel includes a first reset phase and a data write phase. During the first reset phase, the first shift register transmits a first scan signal to the first scan signal line, and the first voltage signal line transmits a first voltage signal. The first reset transistor is configured to transmit the first voltage signal to the first node under the control of the first scan signal. During the data write phase, the first shift register transmits the first scan signal to the first scan signal line, and the first voltage signal line transmits a data signal. The first reset transistor is configured to transmit the data signal to the first node under the control of the first scan signal.

[0017] In some embodiments, the pixel circuit further includes a data write transistor, wherein a control electrode of the data write transistor is electrically connected to the fourth scan signal line, a first electrode is electrically connected to the data line, and a second electrode is electrically connected to the first node. The display panel further includes a fourth gate drive circuit, wherein the fourth gate drive circuit includes a plurality of fourth shift registers arranged in cascade, and each fourth scan signal line is electrically connected to one fourth shift register.

[0018] In some embodiments, a frame period of the display panel includes a first reset phase and a data write phase. During the first reset phase, the first shift register transmits a first scan signal to the first scan signal line, and the first voltage signal line transmits a first voltage signal. The first reset transistor is configured to transmit the first voltage signal to the first node under the control of the first scan signal. During the data write phase, the fourth shift register transmits a fourth scan signal to the fourth scan signal line, and the data line transmits a data signal. The data write transistor is configured to transmit the data signal to the first node under the control of the fourth scan signal.

[0019] In some embodiments, the pixel circuit further includes a second light emission control transistor, wherein a control electrode of the second light emission control transistor is electrically connected to the second light emission control signal line, a first electrode is electrically connected to the fourth voltage signal line, and a second electrode is electrically connected to the third node. The display panel further includes a fifth gate drive circuit, wherein the fifth gate drive circuit includes a plurality of fifth shift registers arranged in cascade connection, wherein one fifth shift register is electrically connected to at least one second light emission control signal line, and a row of pixel circuits is electrically connected to one fifth shift register.

[0020] In another aspect, a display device is provided, comprising the display panel according to any one of the above embodiments.

[0021] The above display device has the same structure and beneficial effects as the display panels provided in some of the above embodiments, which will not be described in detail here. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] To more clearly illustrate the technical solutions of the present disclosure, the following briefly introduces the drawings required for use in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure, and those skilled in the art can also derive other drawings based on these drawings. Furthermore, the drawings described below are schematic diagrams and are not intended to limit the actual dimensions of the products, actual processes of the methods, actual timing of signals, and the like involved in the embodiments of the present disclosure.

[0023] FIG1 is a schematic diagram of a display device according to some embodiments;

[0024] FIG2 is a structural block diagram of a display device according to some embodiments;

[0025] FIG3 is an equivalent circuit diagram of a pixel circuit according to some embodiments;

[0026] FIG4 is a control timing diagram of a pixel circuit according to some embodiments;

[0027] FIG5 is a diagram illustrating a connection relationship between a pixel circuit and a gate driving circuit according to some embodiments;

[0028] FIG6 is another connection diagram of a pixel circuit and a gate driving circuit according to some embodiments;

[0029] FIG7 is a diagram illustrating another connection relationship between a pixel circuit and a gate driving circuit according to some embodiments;

[0030] FIG8 is a diagram illustrating another connection relationship between a pixel circuit and a gate driving circuit according to some embodiments;

[0031] FIG9 is a diagram illustrating another connection relationship between a pixel circuit and a gate driving circuit according to some embodiments;

[0032] FIG10 is another control timing diagram of a pixel circuit according to some embodiments;

[0033] FIG11 is a diagram illustrating another connection relationship between a pixel circuit and a gate driving circuit according to some embodiments;

[0034] FIG12 is a diagram illustrating another connection relationship between a pixel circuit and a gate driving circuit according to some embodiments;

[0035] FIG13 is another control timing diagram of a pixel circuit according to some embodiments;

[0036] FIG14 is a diagram illustrating another connection relationship between a pixel circuit and a gate driving circuit according to some embodiments;

[0037] FIG. 15 is a diagram illustrating another connection relationship between a pixel circuit and a gate driving circuit according to some embodiments. DETAILED DESCRIPTION

[0038] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the embodiments described are only some embodiments of the present disclosure, not all embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of the present disclosure.

[0039] Unless the context requires otherwise, throughout the specification and claims, the term "comprise" and its other forms, such as the third person singular form "comprises" and the present participle form "comprising", are to be interpreted as open and inclusive, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" or "some examples" are intended to indicate that the particular features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the particular features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0040] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0041] When describing some embodiments, the terms "electrically connected" and "connected," and their derivatives, may be used. The term "connected" should be broadly interpreted. For example, "connected" can mean a fixed connection, a removable connection, or an integral connection; it can be directly connected or indirectly connected through an intermediary. The term "electrically connected" indicates, for example, that two or more components are in direct physical or electrical contact, or that they are indirectly connected through other electronic components or structures.

[0042] “At least one of A, B and C” has the same meaning as “at least one of A, B or C” and both include the following combinations of A, B and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B and C.

[0043] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0044] The use of "adapted to" or "configured to" herein is intended to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0045] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0046] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0047] As used herein, "parallel", "perpendicular", and "equal" include the situations described and situations similar to the situations described, and the range of the similar situations is within an acceptable deviation range, wherein the acceptable deviation range is as determined by a person of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the specific quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range of approximate parallelism can be, for example, a deviation within 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range of approximate perpendicularity can also be, for example, a deviation within 5°. "Equal" includes absolute equality and approximate equality, wherein the acceptable deviation range of approximate equality can be, for example, that the difference between the two equals is less than or equal to 5% of either one.

[0048] It will be understood that when a layer or element is referred to as being on another layer or plate, it can be directly on the other layer or plate, or intervening layers may be present between the layer or element and the other layer or plate.

[0049] Exemplary embodiments are described herein with reference to cross-sectional and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0050] The transistors used in the pixel circuits provided in the embodiments of the present disclosure may be thin film transistors (TFT), field effect transistors (MOS) or other switching devices with the same characteristics, wherein the embodiments of the present disclosure are described by taking thin film transistors as an example. The thin film transistor may be a P-type transistor or an N-type transistor, wherein the P-type transistor is turned on under the action of a low potential and is cut off under the action of a high potential; the N-type transistor is turned on under the action of a high potential and is cut off under the action of a low potential. The embodiments of the present disclosure are described by taking N-type transistors as an example, but the type of transistor is not limited thereto, and any transistor may be considered to be set as a P-type transistor or an N-type transistor.

[0051] The control electrode of each thin-film transistor used in the pixel circuit is the gate of the thin-film transistor, the first electrode is one of the source and drain of the thin-film transistor, and the second electrode is the other of the source and drain of the thin-film transistor. Since the source and drain of the thin-film transistor can be structurally symmetrical, their source and drain can be structurally the same. In other words, the first electrode and the second electrode of the thin-film transistor in the embodiments of the present disclosure can be structurally the same. For example, the first electrode of the thin-film transistor is the source, and the second electrode is the drain.

[0052] The first node, second node, etc. in the pixel circuit do not represent actual components, but represent the junction points of related electrical connections in the circuit diagram. That is, these nodes are nodes formed by the junction points of related electrical connections in the circuit diagram.

[0053] 1 , an embodiment of the present disclosure provides a display device 1000 , which is a product having an image display function. For example, the display device 1000 can be any device that displays either moving (e.g., video) or fixed (e.g., still images), and whether text or images.

[0054] For example, the display device 1000 may be a mobile phone, a wireless device, a personal digital assistant (PDA), a wearable device, an augmented reality (AR) device, a virtual reality (VR) device, a handheld or portable computer, a GPS receiver / navigator, a camera, an MP4 video player, a video camera, a game console, a watch, a clock, a calculator, a television monitor, a flat-panel display, a computer monitor, an automotive display (e.g., an odometer display), a cockpit controller and / or display, a display of a camera view (e.g., a display of a rearview camera in a vehicle), an electronic photo, an electronic billboard or sign, a projector, packaging, and an aesthetic structure (e.g., a display of an image of a piece of jewelry), etc. For example, as shown in FIG1 , the display device 1000 may be a mobile phone.

[0055] From the perspective of the light-emitting type of the display device 1000, the display device 1000 may be an organic light-emitting diode display device or a quantum dot electroluminescent display device (Quantum Dot Light Emitting Diodes; abbreviated as: QLED), etc. From the perspective of the form of the display device 1000, the display device 1000 may be a flat display device, a curved display device, or a foldable display device, etc. From the perspective of the shape of the display device 1000, the display device 1000 may be rectangular or circular, etc. The following takes an organic light-emitting diode display device that is rectangular and flat as an example to schematically illustrate some embodiments of the present disclosure, but the embodiments of the present disclosure are not limited thereto, and any other display devices may also be considered as long as the same technical ideas are applied.

[0056] Referring to Figure 2, in some embodiments, the display device 1000 includes a display panel 1100 and a driving circuit board 1200. The driving circuit board 1200 may include, for example, a timing controller (TCON), a power management chip DC / DC, and an adjustable resistor voltage divider circuit (generating Vcom) and other driving circuits. The driving circuit board 1200 may also include other circuit structures, which are not listed here one by one. The driving circuit board 1200 is electrically connected to the display panel 1100 and is used to transmit a control signal to the display panel 1100, thereby driving the display panel 1100 to realize image display. In addition, the display device 1000 may also include a touch structure, an under-screen camera, and an under-screen fingerprint recognition sensor, so that the display device 1000 can realize a variety of different functions such as touch, photo taking, video recording or fingerprint recognition, which are not specifically limited here.

[0057] Continuing with FIG. 2 , the display panel 1100 includes a display area AA and a peripheral area BB. The peripheral area BB is located on at least one side of the display area AA. For example, the peripheral area BB surrounds the display area AA. The display area AA is the area on the display panel 1100 used to display images. The display area AA is provided with a plurality of sub-pixels P, which are the smallest light-emitting units on the display panel 1100 and are used to display images. The peripheral area BB can be used, for example, to configure a gate driver on array (GOA) circuit and control signal lines (such as clock signal lines and power supply voltage signal lines). Of course, the functions of the peripheral area BB are not limited thereto, and non-disclosed embodiments will not be described in detail here.

[0058] The multiple sub-pixels P can emit light of different colors. For example, the multiple sub-pixels P include red sub-pixels that emit red light, green sub-pixels that emit green light, and blue sub-pixels that emit blue light, so that the display panel can achieve color display. Of course, the embodiments of the present disclosure are not limited to this, as long as the same technical concept is adopted.

[0059] Each sub-pixel P includes a pixel circuit 100 and a light-emitting device 200. The multiple pixel circuits 100 included in the multiple sub-pixels P can be arranged into multiple rows and columns. The multiple rows of pixel circuits 100 are arranged along a first direction Y, and the multiple rows of pixel circuits 100 each include multiple pixel circuits 100 arranged along a second direction X. The first direction Y intersects with the second direction X. The multiple columns of pixel circuits 100 are arranged along the second direction X, and the multiple columns of pixel circuits 100 each include multiple pixel circuits 100 arranged along the first direction Y. A row of pixel circuits 100 may include multiple pixel circuits 100 arranged along the second direction X, and a column of pixel circuits 100 may include multiple pixel circuits arranged along the first direction Y. The first direction Y intersects with the second direction X. Exemplarily, the first direction Y is perpendicular to the second direction X.

[0060] The pixel circuit 100 includes a plurality of thin film transistors (TFTs) and at least one capacitor Cst. The pixel circuit 100 is used to drive the light-emitting device 200 to emit light. For example, the pixel circuit 100 can be a "7T2C" circuit, a "7T1C" circuit, or an "8T1C" circuit, etc. The embodiments of the present disclosure are not limited thereto, and any other pixel circuits can also be considered as long as the same technical ideas are applied. Among them, "T" refers to TFT, and the number before "T" refers to the number of TFTs; "C" refers to the capacitor Cst, and the number before "C" refers to the number of capacitors Cst.

[0061] In some embodiments, with the development of display technology, display panels with variable refresh rates and display panels with local high refresh rates have received increasing attention. Pixel circuits using metal oxide (Oxide) thin film transistors are widely used in display panels. Furthermore, pixel circuits using internal compensation are also widely used in display panels due to their advantages such as simple and reliable algorithms and low display panel manufacturing costs. Based on this, referring to FIG3 , an embodiment of the present disclosure provides a "7T2C" pixel circuit 100, i.e., the pixel circuit 100 includes 7 thin film transistors and 2 capacitors.

[0062] As shown in FIG3 , the pixel circuit 100 may include a driving transistor DT, a first reset transistor T1 , a voltage stabilizing transistor T2 , a second reset transistor T3 , a data writing transistor T4 , a first emission control transistor T5 , a second emission control transistor T6 , a first capacitor C1 , and a second capacitor C2 .

[0063] The control electrode of the driving transistor DT is electrically connected to the first node N1, the first electrode (e.g., the source electrode) is electrically connected to the second node N2, and the second electrode (e.g., the drain electrode) is electrically connected to the third node N3. The driving transistor DT is configured to generate a driving current under the control of a voltage difference Vgs between the gate and source electrodes of the driving transistor DT. As shown in FIG3 , when the driving transistor DT is an N-type transistor, the voltage difference Vgs between the gate and source electrodes of the driving transistor DT is equal to the voltage of the first node N1 minus the voltage of the second node N2. In this case, the driving transistor DT generates a driving current under the control of the voltage difference (Vgs) between the first node N1 and the second node N2, and drives the light-emitting device 200 to emit light according to the driving current. Of course, when the driving transistor DT is a P-type transistor, the voltage difference Vgs between the gate and source electrodes of the driving transistor DT is equal to the voltage of the first node N1 minus the voltage of the third node N3. In other words, the driving transistor DT generates a driving current under the control of the voltage difference (Vgs) between the first node N1 and the third node N3, and drives the light-emitting device 200 to emit light according to the driving current.

[0064] The control electrode of the first reset transistor T1 is electrically connected to the first scanning signal line GL1, the first electrode is electrically connected to the first voltage signal line Vref, and the second electrode is electrically connected to the first node N1. The first reset transistor T1 is configured to transmit the first voltage signal from the first voltage signal line Vref to the first node N1 under the control of the first scanning signal from the first scanning signal line GL1, so as to reset (initialize) the voltage of the first node N1.

[0065] The control electrode of the voltage-stabilizing transistor T2 is electrically connected to the second scan signal line GL2, the first electrode is electrically connected to the fourth node N4, and is electrically connected to the second voltage signal line VX via the second reset transistor T3. The second electrode is electrically connected to one plate of the first capacitor C1. The other plate of the first capacitor C1 is electrically connected to the second node N2. The voltage-stabilizing transistor T2 and the first capacitor C1 are configured to maintain the voltage of the second node N2. In one implementation, as shown in FIG3 , the second voltage signal line VX and the third voltage signal line Vinit can be the same signal line. In this case, the first electrode of the voltage-stabilizing transistor T2 can be electrically connected to the second voltage signal line VX via the second reset transistor T3.

[0066] The control electrode of the second reset transistor T3 is electrically connected to the third scan signal line GL3, the first electrode is electrically connected to the third voltage signal line Vinit, and the second electrode is electrically connected to the fourth node N4. The second reset transistor T3 is configured to transmit the third voltage signal from the third voltage signal line Vinit to the fourth node N4 under the control of the third scan signal from the third scan signal line GL3, thereby resetting the voltage of the fourth node N4.

[0067] The control electrode of the data write transistor T4 is electrically connected to the fourth scan signal line GL4, the first electrode is electrically connected to the data line DL, and the second electrode is electrically connected to the first node N1. The data write transistor T4 is configured to transmit the data signal from the data line DL to the first node N1 under the control of the fourth scan signal from the fourth scan signal line GL4.

[0068] The first emission control transistor T5 has a control electrode electrically connected to the first emission control signal line EML1, a first electrode electrically connected to the second node N2, and a second electrode electrically connected to the fourth node N4. The fourth node N4 is also electrically connected to the light-emitting device 200. The second emission control transistor T6 has a control electrode electrically connected to the second emission control signal line EML2, a first electrode electrically connected to the fourth voltage signal line VDD, and a second electrode electrically connected to the third node N3. The first emission control transistor T5 and the second emission control transistor T6 are configured to be turned on (on) during the display phase to transmit a drive current to the light-emitting device 200, thereby driving the light-emitting device 200 to emit light. The functions of the first emission control transistor T5 and the second emission control transistor T6 are not limited to this. The first emission control transistor T5 and the second emission control transistor T6 can also be turned on during other phases to cooperate with other transistors to achieve different functions, as described below.

[0069] One plate of the second capacitor C2 is electrically connected to the first node N1 , and the other plate is electrically connected to the second node N2 . The second capacitor C2 is configured to maintain the voltage of the first node N1 .

[0070] In which, the display panel 1100 may include multiple first scan signal lines GL1, multiple second scan signal lines GL2, multiple third scan signal lines GL3, multiple fourth scan signal lines GL4, multiple first light-emitting control signal lines EML1 and multiple second light-emitting control signal lines EML2, and the multiple first scan signal lines GL1, multiple second scan signal lines GL2, multiple third scan signal lines GL3, multiple fourth scan signal lines GL4, multiple first light-emitting control signal lines EML1 and multiple second light-emitting control signal lines EML2 are all arranged at intervals along the first direction Y, and a row of pixel circuits 100 is electrically connected to one first scan signal line GL1, one second scan signal line GL2, one third scan signal line GL3, one fourth scan signal line GL4, one first light-emitting control signal line EML1 and one second light-emitting control signal line EML2. Hereinafter, in some embodiments, for the convenience of description, the above-mentioned "first scanning signal line GL1, second scanning signal line GL2, third scanning signal line GL3, fourth scanning signal line GL4, first light-emitting control signal line EML1 and second light-emitting control signal line EML2" are all referred to as "scanning signal lines".

[0071] 4 , some embodiments of the present disclosure further provide a method for controlling a pixel circuit 100, which is used to drive the pixel circuit 100 shown in FIG3 . A display frame period may include a first reset phase D1, a compensation phase D2, a data writing phase D3, a second reset phase D4, and a display phase D5, which are sequentially arranged.

[0072] In the first reset stage D1, the first scan signal line GL1 transmits the first scan signal, the first reset transistor T1 is turned on under the control of the first scan signal, and the first reset transistor T1 transmits the voltage of the first voltage signal line Vref (marked as Vref) to the first node N1, initializing (resetting) the voltage of the N1 node.

[0073] The third scan signal line GL3 transmits a third scan signal, the second reset transistor T3 is turned on under the control of the third scan signal, and the second reset transistor T3 transmits the voltage of the third voltage signal line Vinit (labeled as Vinit) to the fourth node N4, initializing the voltage of the fourth node N4.

[0074] The first light emitting control signal line EML1 transmits a first light emitting control signal, the first light emitting control transistor T5 is turned on under the control of the first light emitting control signal, and the first light emitting control transistor T5 transmits the voltage (Vinit) of the fourth node N4 to the second node N2 to initialize the voltage of the second node N2.

[0075] Moreover, the second scanning signal line GL2 starts to transmit the second scanning signal after a period of time in the first reset stage D1. Under the control of the second scanning signal, the voltage-stabilizing transistor T2 transmits the voltage (Vinit) of the fourth node N4 to the plate of the first capacitor C1 connected to the voltage-stabilizing transistor T2, thereby resetting the voltage of the plate of the first capacitor C1.

[0076] The voltage-stabilizing transistor T2 is turned on later than the second reset transistor T3 and the first emission control transistor T5. Thus, the second reset transistor T3 and the first emission control transistor T5 can first reset the voltage of the second node N2 (one plate of the first capacitor C1), and then the voltage-stabilizing transistor T2 resets the voltage of the other plate of the first capacitor C1. This prevents excessive fluctuations in the voltage of the second node N2, prevents the voltage difference (Vgs) between the first node N1 and the second node N2 from suddenly increasing at the start of the first reset phase D1, and prevents the driving transistor DT from generating a transient high current, thereby improving the safety of the pixel circuit 100.

[0077] During compensation phase D2, the first scan signal line GL1 continues to transmit the first scan signal, the first reset transistor T1 remains on, and the voltage at the first node N1 remains at Vref. The second scan signal line GL2 continues to transmit the second scan signal, and the third scan signal line continues to transmit the third scan signal. The second reset transistor T3 and the voltage-stabilizing transistor T2 both remain on, and the voltage at the fourth node N4 and the plate voltage of the first capacitor C1 connected to the voltage-stabilizing transistor T2 remain at Vinit. The first emission control signal line EML1 transmits a cutoff voltage (a voltage that turns off the corresponding transistor), turning off the first emission control transistor T5.

[0078] The second emission control signal line EML2 transmits a second emission control signal, turning on the second emission control transistor T6 under the control of the second emission control signal. The second emission control transistor T6 then transmits a fourth voltage signal (labeled as Vdd) from the fourth voltage signal terminal VDD to the third node N3. At this point, the voltage at the first node N1 is Vref, the voltage at the second node N2 is Vinit, and the voltage at the third node N3 is Vdd. Based on this, the voltage difference Vgs between the gate (first node N1) and the source (second node N2) of the driving transistor DT is calculated as follows: Vgs = Vref - Vinit, the voltage at the first node N1 - Vinit = Vref - Vinit, i.e., Vgs = Vref - Vinit. At this point, Vgs is greater than the threshold voltage Vth of the driving transistor DT, i.e., Vgs - Vth > 0. The driving transistor DT is turned on, and discharges the current from the driving transistor DT to the second node N2 through the third node N3 until the voltage at the second node N2 changes to (Vref - Vth). This achieves compensation of the threshold voltage of the driving transistor DT.

[0079] During the data write phase D3, the first scan signal line GL1 stops transmitting the first scan signal and instead transmits a cutoff voltage signal. The first reset transistor T1 is turned off under the control of the cutoff voltage. The third scan signal line GL3 continues transmitting the third scan signal, the second reset transistor T3 remains on, and the voltage at the fourth node N4 remains at Vinit. The second scan signal line GL2 continues transmitting the second scan signal, the voltage-stabilizing transistor T2 remains on, and the voltage at the plate of the first capacitor C1 connected to the voltage-stabilizing transistor T2 remains at Vinit. The second emission control signal line EML2 transmits a cutoff voltage, and the second emission control transistor T6 is turned off. The data line DL transmits the data signal Vdata, and the fourth scan signal line GL4 transmits the fourth scan signal. The data write transistor T4 is turned on and transmits the data signal Vdata to the first node N1, causing the voltage at the first node N1 to change to Vdata. Due to the bootstrap effect of the first capacitor C1 and the second capacitor C2, the voltage at the second node N2 changes by [(Vref - Vth) + C1 / (C1 + C2) × (Vdata - Vref)].

[0080] During the second reset phase D4, the second scan signal line GL2 stops transmitting the second scan signal and begins transmitting the cutoff voltage signal, turning off the voltage-stabilizing transistor T2. The first light-emission control signal line EML1 first transmits the cutoff voltage signal, then the first light-emission control signal, and finally transmits the first light-emission control signal before the end of the second reset phase D4. In other words, assuming the first light-emission control signal line EML1 is an N-type transistor, the first light-emission control signal line EML1 transitions from a low level to a high level during the second reset phase D4, causing the first light-emission control transistor T5 to be first turned off and then turned on. The third scan signal line GL3 transmits the third scan signal, while the second reset transistor T3 remains on. The voltage at the fourth node N4 is maintained at Vinit. This reduces the issue of uneven display on the display panel 1100 caused by voltage differences across the light-emitting device 200.

[0081] In the display stage D5, the first scanning signal line GL1, the second scanning signal line GL2, the third scanning signal line GL3, and the fourth scanning signal line GL4 all transmit a cutoff voltage. Correspondingly, the first reset transistor T1, the second reset transistor T3, the voltage-stabilizing transistor T2, and the data writing transistor T4 are all in the off state. The first light-emitting control signal line EML1 and the second light-emitting control signal line EML2 transmit the first light-emitting control signal and the second light-emitting control signal, respectively. The first light-emitting control transistor T5 and the second light-emitting control transistor T6 are both turned on. At this time, the voltage difference between the gate and source of the driving transistor DT is Vgs = Vdata - [(Vref - Vth) + C1 / (C1 + C2) × (Vdata - Vref)], and the driving current I generated by the driving transistor DT is I = K × (Vgs - Vth). 2 , that is, the driving current I=K×[(Vdata-Vref)×C2 / (C1+C2)] 2 , the influence of the threshold voltage Vth of the driving transistor DT on the driving current can be eliminated. The light emitting device 200 emits light under the driving current.

[0082] As shown in FIG2 , the peripheral area BB of the display panel 1100 can be used to set a gate driver circuit (Gate Driver on Array; GOA for short), and control signal lines (such as clock signal lines, power supply voltage signal lines, etc.). For example, the display panel 1100 may include multiple gate driver circuits, and each of the multiple gate driver circuits includes multiple shift registers arranged in cascade. Each gate driver circuit in the multiple gate driver circuits is configured to be connected to a scan signal line (such as the first scan signal line GL1), and each shift register of the gate driver circuit is connected to at least one scan signal line. The shift register is configured to transmit a turn-on signal of a transistor (such as a first reset transistor), and transmit the turn-on signal to the control electrode of the corresponding transistor of at least one row of pixel circuits through the at least one scan signal line, thereby driving the corresponding transistor to be turned on, thereby realizing the function of driving the transistor to be turned on.

[0083] In the display panel provided by the related art, each scanning signal line electrically connected to the pixel circuit is connected to a different gate drive circuit. Thus, the number of gate drive circuits required for the display panel is equal to the number of transistors included in the pixel circuit minus one (the gate of the driving transistor DT is not connected to a scanning signal line). Taking the pixel circuit shown in FIG3 as an example, the display panel requires six gate drive circuits, which is a relatively large number of gate drive circuits. Furthermore, the multiple gate drive circuits can be arranged in the width direction (the second direction X) of the peripheral region. Thus, the greater the number of gate drive circuits, the greater the width occupied by the gate drive circuits in the peripheral region, which is less conducive to reducing the width of the peripheral region of the display panel, i.e., less conducive to achieving a narrow frame of the display panel.

[0084] In order to solve the above technical problems, referring to Figure 5, the display panel 1100 provided by some embodiments of the present disclosure further includes a first gate driving circuit 110, and the first gate driving circuit 110 includes a plurality of first shift registers G1 arranged in cascade, and at least two first shift registers G1 are connected to the same row of pixel circuits 100. In this way, a row of pixel circuits 100 is electrically connected to at least two first shift registers G1, and the control electrodes of at least two different transistors included in the pixel circuit 100 are driven by the first gate driving circuit 110. That is, at least two different transistors share the first gate driving circuit 110. This is conducive to reducing the number of gate driving circuits included in the display panel 1100, and is conducive to reducing the width of the peripheral area BB occupied by the gate driving circuit, thereby reducing the border width of the display panel, and is conducive to achieving a narrow border for the display panel 1100.

[0085] For example, a row of pixel circuits 100 can be connected to two first shift registers G1 (as shown in FIG5 ), or a row of pixel circuits 100 can be connected to three first shift registers G1. Moreover, a row of pixel circuits 100 can be connected to two (or more) first shift registers G1 cascaded with each other (as shown in FIG5 ), or can be connected to two (or more) first shift registers G1 spaced apart from each other. Of course, the embodiments of the present disclosure are not limited thereto, and can be connected in any other suitable manner, as long as the same technical ideas are adopted. In the following embodiments of the present disclosure, the pixel circuit 100 shown in FIG3 is taken as an example to exemplarily describe the present disclosure.

[0086] For the convenience of description, the multiple rows of pixel circuits 100 included in the display panel 1100 can be numbered in sequence as the first row of pixel circuits 100 (1), the second row of pixel circuits 100 (2), ..., the Nth row of pixel circuits 100 (N), etc., and the first scanning signal line GL1 connected to the first row of pixel circuits 100 (1) is marked as GL1 (1), the first scanning signal line GL1 connected to the second row of pixel circuits 100 (2) is marked as GL1 (2), ...., the first scanning signal line GL1 connected to the Nth row of pixel circuits 100 (N) is marked as GL1 (N), etc. In some embodiments of the present disclosure, other scanning signal lines (such as the second scanning signal line or the first light-emitting control signal line, etc.) also use similar names and labels, and the embodiments of the present disclosure will not list them one by one. In addition, the multiple first shift registers arranged in cascade are marked in sequence as the first-stage first shift register G1 (1), the second-stage first shift register G1 (2), ..., the Nth-stage first shift register G1 (N), etc. in the cascade order.

[0087] The waveform of the first scanning signal transmitted by the first scanning signal line GL1 is similar to the waveform of the second scanning signal transmitted by the second scanning signal line GL2, and the start and end times (on time and off time) of the second scanning signal are respectively delayed (latter) than the start and end times of the first scanning signal. In this way, the first shift register G1 connected to the first scanning signal line GL1 can be the first shift register G1 of the previous stage (upper stage) of the first shift register G1 connected to the second scanning signal line GL2. In other words, the first shift register G1 connected to the first scanning signal line GL1 first transmits the first scanning signal to the first scanning signal line GL1, and then the first shift register G1 connected to the second scanning signal line GL2 transmits the second scanning signal to the second scanning signal line GL2. In this way, the influence on the control method of the pixel circuit 100 can be minimized while reducing one gate driving circuit, or even without changing the control method of the pixel circuit 100.

[0088] It can be understood that in the embodiments of the present disclosure, the signals transmitted from the first shift register G1 to the first scanning signal line GL1 and the second scanning signal line GL2 are respectively referred to as the first scanning signal and the second scanning signal. The first scanning signal and the second scanning signal can be essentially the same. For the first scanning signal line GL1 and the second scanning signal line GL2 respectively electrically connected to the two rows of pixel circuits 100 connected to the same first shift register G1, the first scanning signal and the second scanning signal can be exactly the same. For the first scanning signal line GL1 and the second scanning signal line GL2 electrically connected to the same row of pixel circuits 100, the start and end times of the first scanning signal and the second scanning signal respectively have a certain time difference.

[0089] For the reasons described above, in some embodiments, referring to FIG6 , the first scan signal line GL1 and the second scan signal line GL2 electrically connected to the same row of pixel circuits 100 are respectively electrically connected to two first shift registers G1. In other words, the first reset transistor T1 and the voltage regulator transistor T2 share the first gate driver circuit 110. This eliminates one gate driver circuit, facilitating a reduction in the width of the peripheral area BB and, consequently, the bezel width of the display panel.

[0090] It can be understood that, as shown in Figure 6, in the drawings of the present disclosure, multiple gate drive circuits (such as the first gate drive circuit 110, the second gate drive circuit 120, the third gate drive circuit 130, etc.) are arranged in the vertical direction. This arrangement is only schematically represented to simplify the drawings. Multiple gate drive circuits can be arranged along the second direction X in the peripheral area.

[0091] In some embodiments, as shown in FIG6 , the first scanning signal line GL1(N) electrically connected to the pixel circuit 100(N) in the Nth row is electrically connected to the first shift register G1(N) in the Nth stage. The second scanning signal line GL2(N) electrically connected to the pixel circuit 100(N) in the Nth row is electrically connected to the first shift register G1(N+K) in the (N+K)th stage. Wherein, N and K are both positive integers.

[0092] For example, the value of K can be 1, 2, 3, 4, etc., which are not listed here one by one. The value of K is generally not very large. For example, the value of K can be less than or equal to 10. This facilitates the electrical connection between the (N+K)-th stage first shift register G1(N+K) and the second scan signal line GL2(N) in the peripheral area, reducing the span of the connection line between the (N+K)-th stage first shift register G1(N+K) and the second scan signal line GL2(N). Furthermore, it can facilitate reducing the number of first shift registers G1 included in the first gate driver circuit 110, reducing the space occupied by the first gate driver circuit 110 in the first direction Y, and further reducing the width of the lower side frame occupied by the first gate driver circuit 110.

[0093] For example, after the first shift register G1 connected to the first scanning signal line GL1 of the last row of pixel circuits 100, at least K first shift registers G1 can be cascaded so that the second scanning signal lines GL2 electrically connected to the last K rows of pixel circuits 100 can all be electrically connected to one first shift register G1.

[0094] In other embodiments, referring to FIG. 7 , the first scanning signal line GL1(N) electrically connected to the N-th row of pixel circuits 100(N) is electrically connected to the (N-M)-th stage shift register; the second scanning signal line electrically connected to the N-th row of pixel circuits is electrically connected to the N-th stage shift register; wherein N and M are both positive integers.

[0095] For example, the value of N is greater than M, and the value of M can be 1, 2, 3, 4, etc., which are not listed here one by one. The value of M is usually not very large. For example, the value of M can be less than or equal to 10. This is conducive to the electrical connection between the (NM)-th stage first shift register G1 (NM) and the first scan signal line GL1 (N) in the peripheral area, and the span of the connection line between the (NM)-th stage first shift register G1 (NM) and the first scan signal line GL1 (N) is reduced. In addition, it can be helpful to reduce the number of first shift registers G1 included in the first gate driver circuit 110, reduce the space of the first gate driver circuit 110 in the first direction Y, and further reduce the width of the lower side frame occupied by the first gate driver circuit 110.

[0096] For example, at least M first shift registers G1 can be cascaded before the first-stage first shift register G1 connected to the second scanning signal line GL2 of the first row of pixel circuits 100, so that the first scanning signal lines GL1 electrically connected to the first M rows of pixel circuits 100 can all be electrically connected to one first shift register G1.

[0097] In some embodiments, when the pixel circuit 100 is connected to the first gate driving circuit 110 in the manner shown in Figure 6 or Figure 7, the control method of the pixel circuit 100 is the same as the control method of the pixel circuit shown in Figure 4 above, and will not be repeated here.

[0098] In some embodiments, referring to Figures 6 and 7, the second voltage signal line VX and the third voltage signal line Vinit are configured to transmit the same voltage signal, and the first voltage signal line VX and the third voltage signal line Vinit are the same signal line. This helps to simplify the connection relationship of the pixel circuit 100 and reduce the difficulty of arranging the signal lines of the display panel 1100. In addition, the first electrode of the voltage-stabilizing transistor T2 is electrically connected to the fourth node N4 and is electrically connected to the third voltage signal line Vinit through the second reset transistor T3. As shown above, in this way, the second reset transistor T3 can be turned on first in the first reset phase D1 to reset the voltages of the fourth node N4 and the second node N2, and then the voltage-stabilizing transistor T2 can be turned on to transmit the third voltage signal to a plate of the first capacitor C1 connected to the voltage-stabilizing transistor T2, thereby preventing the driving transistor DT from generating a transient large current.

[0099] Referring to Figures 6 and 7 , the display panel 1100 may further include a second gate driver circuit 120, a third gate driver circuit 130, a fourth gate driver circuit 140, and a fifth gate driver circuit 150. The second gate driver circuit 120 includes a plurality of second shift registers EM1 arranged in cascade connection, with a first emission control signal line EML1 electrically connected to each second shift register EM1. The third gate driver circuit 130 includes a plurality of third shift registers G3 arranged in cascade connection, with a third scan signal line GL3 electrically connected to each third shift register G3. The fourth gate driver circuit 140 includes a plurality of fourth shift registers G4 arranged in cascade connection, with a fourth scan signal line GL4 electrically connected to each fourth shift register G4. The fifth gate driver circuit 150 includes a plurality of fifth shift registers EM2 arranged in cascade connection, with a second emission control signal line EML2 electrically connected to each fifth shift register EM2. In other words, the second reset transistor T3, the data write transistor T4, the first emission control transistor T5, and the second emission control transistor T6 are each driven by a gate driver circuit. 6 and 7 only exemplarily show a second shift register EM1(N), a third shift register G3(N), a fourth shift register G4(N) and a fifth shift register EM2(N) electrically connected to the Nth row of pixel circuits 100(N).

[0100] As shown in FIG4 , the start time of the first scan signal transmitted by the first scan signal line GL1 is the same as the start time of the third scan signal transmitted by the third scan signal line GL3. That is, the start time of the pixel circuit 100 transmitting the first voltage signal to the first node N1 through the first reset transistor T1 (the voltage initialization time for the first node N1) is the same as the start time of the second reset transistor T3 transmitting the third voltage signal to the fourth node N4 (the voltage initialization time for the fourth node N4). Moreover, the cut-off time of the second reset transistor T3 transmitting the third voltage signal to the fourth node N4 is later (further back) than the cut-off time of the first reset transistor T1 transmitting the first voltage signal to the first node N1. Research has found that delaying the start time of the second reset transistor T3 transmitting the third voltage signal to the fourth node N4 does not significantly affect the pixel circuit 100 and does not reduce the voltage reset effect on the fourth node N4.

[0101] Based on the above reasons, referring to Figure 8, when the first scanning signal line GL1 is electrically connected to a first shift register G1, the third scanning signal line GL3 can also be electrically connected to a first shift register G1, that is, the first reset transistor T1 and the second reset transistor T3 share the first gate driving circuit 110. In this way, the number of gate driving circuits included in the display panel 1100 can also be reduced, thereby reducing the width of the peripheral area occupied by the gate driving circuit, which is conducive to achieving a narrow frame for the display panel 1100.

[0102] Furthermore, the third scan signal line GL3(N), electrically connected to the Nth row of pixel circuits 100(N), is electrically connected to the (N+J)th stage of the first shift register G1(N+J). Here, N and J are both positive integers. In this way, the start and end times of the third scan signal on the third scan signal line GL3 can be made later than the start and end times of the first scan signal on the first scan signal line GL1. In other words, the turn-on time of the second reset transistor T3 can be made later than the turn-on time of the first reset transistor T1, and the turn-off time of the second reset transistor T3 can be made later than the turn-off time of the first reset transistor T1. This can greatly reduce the impact of the control method of the pixel circuit 100.

[0103] For example, the value of J can be 1, 2, 3, 4, etc., which are not listed here one by one. The value of J is generally not very large. For example, the value of J can be less than or equal to 10. This is conducive to the electrical connection between the (N+J)-th stage first shift register G1(N+J) and the third scan signal line GL3(N) in the peripheral area BB, reducing the span of the connection line between the (N+J)-th stage first shift register G1(N+J) and the third scan signal line GL3(N). In addition, it can be helpful to reduce the number of first shift registers G1 included in the first gate drive circuit 110, reduce the space of the first gate drive circuit 110 in the first direction Y, and further reduce the width of the lower side frame occupied by the first gate drive circuit 110.

[0104] Continuing with FIG8 , in some embodiments, the second voltage signal line VX and the third voltage signal line Vinit are configured to transmit the same voltage signal. The first voltage signal line VX and the third voltage signal line Vinit are the same signal line, and the first electrode of the voltage-stabilizing transistor T2 is directly electrically connected to the second voltage signal line VX. This simplifies the connection relationship of the pixel circuit 100 and reduces the difficulty of signal line arrangement of the display panel. Moreover, the first electrode of the voltage-stabilizing transistor T2 can be directly electrically connected to the third voltage signal line Vinit. In this way, the voltage-stabilizing transistor T2 can be independently controlled independently of the second reset transistor T3. In other words, the third voltage signal on the third voltage signal line Vinit can be transmitted to one plate of the first capacitor C1 without the second reset transistor T3 being turned on, which helps to improve the control accuracy of the voltage-stabilizing transistor T2.

[0105] Referring to FIG8 , the display panel 1100 may further include a second gate driver circuit 120, a fourth gate driver circuit 140, a fifth gate driver circuit 150, and a sixth gate driver circuit 160. The second gate driver circuit 120 includes a plurality of second shift registers EM1 arranged in cascade connection, with a first emission control signal line EML1 electrically connected to each second shift register EM1. The fourth gate driver circuit 140 includes a plurality of fourth shift registers G4 arranged in cascade connection, with a fourth scan signal line GL4 electrically connected to each fourth shift register G4. The fifth gate driver circuit 150 includes a plurality of fifth shift registers EM2 arranged in cascade connection, with a second emission control signal line EML2 electrically connected to each fifth shift register EM2. The sixth gate driver circuit 160 includes a plurality of sixth shift registers G6 arranged in cascade connection, with a second scan signal line GL2 electrically connected to each sixth shift register G6. That is, the first reset transistor T1 and the second reset transistor T3 share the first gate drive circuit 110, and the voltage regulator transistor T2, the data writing transistor T4, the first emission control transistor T5, and the second emission control transistor T6 are each driven by a gate drive circuit. FIG8 exemplarily illustrates a second shift register EM1(N), a fourth shift register G4(N), a fifth shift register EM2(N), and a sixth shift register G6(N) electrically connected to the Nth row of pixel circuits 100(N).

[0106] In other embodiments, referring to FIG9 , the first scan signal line GL1, the second scan signal line GL2, and the third scan signal line GL3 are each electrically connected to a first shift register G1. In other words, the first reset transistor T1, the voltage regulator transistor T2, and the second reset transistor T3 share the first gate driver circuit 110. This can further reduce the number of gate driver circuits included in the display panel 1100 (by two gate driver circuits), further reducing the width of the peripheral area occupied by the gate driver circuits, thereby further reducing the width of the peripheral area and achieving a narrow frame for the display panel 1100.

[0107] When the second scan signal line GL2(N) electrically connected to the Nth row of pixel circuits 100 is electrically connected to the (N+K)th stage first shift register G1(N+K), the value of J is greater than the value of K. In other words, the (N+K)th stage first shift register G1(N+K) is the previous first shift register G1 of the (N+J)th stage first shift register G1(N+J). In this way, the cutoff time of the third scan signal of the third scan signal line GL3 can be later than the cutoff time of the second scan signal of the second scan signal line GL2, that is, the start and end times of the conduction of the second reset transistor T3 are both later than the start and end times of the conduction of the voltage-stabilizing transistor T2. In this way, the impact on the control method of the pixel circuit 100 can be greatly reduced while reducing two gate drive circuits.

[0108] For example, the value of K is 1 and the value of J is 2; or the value of K is 1 and the value of J is 3; or the value of K is 2 and the value of J is 4, etc. Of course, the embodiments of the present disclosure are not limited thereto, and the values ​​of K and J can be designed as needed, as long as the same technical ideas are adopted. Among them, the values ​​of K and J can both be less than or equal to 10, which is conducive to the electrical connection between the (N+K)-th stage first shift register G1(N+K) and the second scan signal line GL2(N), and the (N+J)-th stage first shift register G1(N+J) and the third scan signal line GL3(N) in the peripheral area, reducing the span of the connecting lines between the (N+K)-th stage first shift register G1(N+K) and the second scan signal line GL2(N), and between the (N+J)-th stage first shift register G1(N+J) and the third scan signal line GL3(N). Furthermore, it can be beneficial to reduce the number of first shift registers G1 included in the first gate driving circuit 110 , reduce the space of the first gate driving circuit 110 in the first direction Y, and further reduce the width of the lower side frame occupied by the first gate driving circuit 110 .

[0109] For example, after the first shift register G1 connected to the first scan signal line GL1 of the last row of pixel circuits 100, at least J first shift registers G1 can be cascaded so that the third scan signal lines GL3 electrically connected to the last J rows of pixel circuits 100 can all be electrically connected to one first shift register G1.

[0110] As shown in FIG9 , in some embodiments, the second voltage signal line VX and the third voltage signal line Vinit may also be configured to transmit different voltage signals. In this case, the second voltage signal line VX and the third voltage signal line Vinit are different voltage signal lines.

[0111] Of course, in some other embodiments, the second voltage signal line VX may be different from the first voltage signal line Vref and the fourth voltage signal line VDD, or may be the same as one of the first voltage signal line Vref and the fourth voltage signal line VDD. The embodiments of the present disclosure do not make specific limitations on this, as long as the same technical ideas are adopted.

[0112] Continuing with FIG9 , the display panel 1100 may further include a second gate driver circuit 120, a fourth gate driver circuit 140, and a fifth gate driver circuit 150. The second gate driver circuit 120 includes a plurality of second shift registers EM1 arranged in cascade connection, with a first emission control signal line EML1 electrically connected to each second shift register EM1. The fourth gate driver circuit 140 includes a plurality of fourth shift registers G4 arranged in cascade connection, with a fourth scan signal line GL4 electrically connected to each fourth shift register G4. The fifth gate driver circuit 150 includes a plurality of fifth shift registers EM2 arranged in cascade connection, with a second emission control signal line EML2 electrically connected to each fifth shift register EM2. In other words, the first reset transistor T1, the second reset transistor T3, and the voltage regulator transistor T2 share the first gate driver circuit 110, while the data write transistor T4, the first emission control transistor T5, and the second emission control transistor T6 are each driven by a gate driver circuit. Based on this, the display panel may be provided with only four gate driving circuits, thus greatly reducing the number of gate driving circuits, greatly reducing the width of the peripheral area BB, and further reducing the border width of the display panel.

[0113] Based on the connection relationship between the pixel circuit and the first gate driving circuit shown in FIG9 , some embodiments of the present disclosure further provide a method for driving a pixel circuit, for driving the gate driving circuit shown in FIG9 . Referring to FIG10 , a display frame period may include a first reset phase D1, a compensation phase D2, a data writing phase D3, a second reset phase D4, and a display phase D5, which are sequentially arranged.

[0114] In the first reset stage D1, the first scan signal line GL1 transmits the first scan signal, the first reset transistor T1 is turned on under the control of the first scan signal, and the first reset transistor T1 transmits the voltage of the first voltage signal line Vref to the first node N1 to initialize the voltage of the N1 node.

[0115] Some time after the first scan signal line GL1 begins transmitting the first scan signal, the second scan signal line GL2 begins transmitting the second scan signal. The voltage-stabilizing transistor T2 is turned on under the control of the second scan signal. That is, the turn-on time of the voltage-stabilizing transistor T2 is later than the turn-on time of the first reset transistor T1. The voltage-stabilizing transistor T2 transmits the second voltage signal at the second voltage signal terminal V2 to a plate of the first capacitor C1 connected to the voltage-stabilizing transistor T2.

[0116] Some time after the second scan signal line GL2 begins transmitting the second scan signal, the third scan signal line GL3 begins transmitting the third scan signal. The second reset transistor T3 is turned on under the control of the third scan signal. In other words, the turn-on time of the second reset transistor T3 is later than the turn-on time of the voltage-stabilizing transistor T2. The second reset transistor T3 transmits the third voltage signal from the third voltage signal terminal Vinit to the fourth node N4, thereby initializing the voltage of the fourth node N4.

[0117] The first light-emission control signal line EML1 transmits a first light-emission control signal, turning on the first light-emission control transistor T5. The second light-emission control signal line EML2 transmits a cutoff voltage, turning off the second light-emission control transistor T6. The pixel circuit 100 no longer transmits a driving current to the light-emitting device 200, and the light-emitting device 200 stops emitting light. Furthermore, the first light-emission control transistor T5 turns on before the second reset transistor T3. After the second reset transistor T3 turns on, the voltage at the fourth node N4 is transmitted to the second node N2, thereby initializing the voltage at the second node N2.

[0118] 4 and 10 , the control method of the pixel circuit 100 in the compensation phase D2 , the data writing phase D3 , the second reset phase D4 , and the display phase D5 is the same as that in the above embodiment and will not be described again.

[0119] In other embodiments, referring to FIG. 11 , the second scan signal line GL2 and the third scan signal line GL3 electrically connected to the same row of pixel circuits 100 are electrically connected to two first shift registers G1, respectively. This saves one gate drive circuit, helps reduce the width of the peripheral area BB, and further reduces the bezel width of the display panel, thereby achieving a narrow bezel on the display panel.

[0120] For example, as shown in FIG11 , the second scanning signal line GL2(N) electrically connected to the pixel circuit 100(N) in the Nth row is electrically connected to the first shift register G1(N) in the Nth stage. The third scanning signal line GL3(N) electrically connected to the pixel circuit 100(N) in the Nth row is electrically connected to the first shift register G1(N+K) in the (N+Q)th stage. Wherein, N and Q are both positive integers.

[0121] For example, the value of Q can be 1, 2, 3, 4, etc., which are not listed here one by one. The value of Q is generally not very large. For example, the value of Q can be less than or equal to 10. This facilitates the electrical connection between the (N+Q)-th stage first shift register G1(N+Q) and the third scan signal line GL3(N) in the peripheral area, reducing the span of the connection line between the (N+Q)-th stage first shift register G1(N+Q) and the third scan signal line GL3(N). Furthermore, it can be beneficial to reduce the number of first shift registers G1 included in the first gate drive circuit 110, reduce the space of the first gate drive circuit 110 in the first direction Y, and further reduce the width of the lower side frame occupied by the first gate drive circuit 110.

[0122] For example, after the first shift register G1 connected to the second scanning signal line GL2 of the last row of pixel circuits 100, at least Q first shift registers G1 can be cascaded so that the third scanning signal lines GL3 electrically connected to the last Q rows of pixel circuits 100 can all be electrically connected to one first shift register G1.

[0123] Referring to FIG. 11 , the display panel 1100 may further include a second gate driver circuit 120, a fourth gate driver circuit 140, a fifth gate driver circuit 150, and a seventh gate driver circuit 170. The second gate driver circuit 120 includes a plurality of second shift registers EM1 arranged in cascade connection, with a first emission control signal line EML1 electrically connected to a second shift register EM1(N). The fourth gate driver circuit 140 includes a plurality of fourth shift registers G4(N) arranged in cascade connection, with a fourth scan signal line GL4(N) electrically connected to a fourth shift register G4(N). The fifth gate driver circuit 150 includes a plurality of fifth shift registers EM2 arranged in cascade connection, with a second emission control signal line EML2(N) electrically connected to a fifth shift register EM2(N). The seventh gate driver circuit 170 includes a plurality of seventh shift registers G7 arranged in cascade connection, with a first scan signal line GL1 electrically connected to a seventh shift register G7(N). That is, the voltage-stabilizing transistor T2 and the second reset transistor T3 share the first gate drive circuit 110, and the first reset transistor T1, the data-writing transistor T4, the first light-emission control transistor T5, and the second light-emission control transistor T6 are each driven by a gate drive circuit. FIG11 exemplarily illustrates a second shift register EM1(N), a fourth shift register G4(N), a fifth shift register EM2(N), and a seventh shift register G7(N) electrically connected to the Nth row of pixel circuits 100(N).

[0124] In some embodiments, when the pixel circuit 100 is connected to the first gate driving circuit 110 in the manner shown in FIG11 , the control method of the pixel circuit 100 may be substantially the same as the control method of the pixel circuit shown in FIG10 , and will not be repeated here.

[0125] In other embodiments, referring to Figures 12 and 13 , the pixel circuit 100 may not include the data write transistor T4, and the pixel circuit 100 may transmit a data signal to the first node N1 via the first reset transistor T1. In this case, the first voltage signal line Vref may transmit different signals at different stages to facilitate transmitting different voltage signals to the first node N1 at different stages. This allows the display panel to save one gate drive circuit, thereby reducing the width of the peripheral area BB and facilitating a narrow bezel design for the display panel.

[0126] As shown in FIG. 13 , one display frame period may include a first reset phase D1 , a compensation phase D2 , a data writing phase D3 , a second reset phase D4 and a display phase D5 , which are arranged in sequence.

[0127] During a first reset phase D1, the first shift register G1 transmits a first scan signal to the first scan signal line GL1, and the first voltage signal line Vref transmits a first voltage signal. The first reset transistor T1 is configured to transmit the first voltage signal to the first node N1 under the control of the first scan signal, thereby resetting the voltage of the first node N1.

[0128] In the data writing phase D3, the first shift register G1 transmits a first scan signal to the first scan signal line GL1, and the first voltage signal line Vref transmits a data signal Vdata. The first reset transistor T1 is configured to transmit the data signal Vdata to the first node N1 under the control of the first scan signal.

[0129] Furthermore, in the second compensation stage D2 , the second reset stage D4 and the display stage, the control method of the pixel circuit 100 may be substantially the same as the control method of the pixel circuit in the aforementioned embodiment, and will not be described in detail here.

[0130] As shown in FIG12 , the display panel 1100 may further include a second gate driver circuit 120, a third gate driver circuit 130, a fifth gate driver circuit 150, and a sixth gate driver circuit 160. The second gate driver circuit 120 includes a plurality of second shift registers EM1 arranged in cascade connection, with a first emission control signal line EML1 electrically connected to each second shift register EM1. The third gate driver circuit 130 includes a plurality of third shift registers G3 arranged in cascade connection, with a third scan signal line GL3 electrically connected to each third shift register G3. The fifth gate driver circuit 150 includes a plurality of fifth shift registers EM2 arranged in cascade connection, with a second emission control signal line EML2 electrically connected to each fifth shift register EM2. The sixth gate driver circuit 160 includes a plurality of sixth shift registers G6 arranged in cascade connection, with a second scan signal line GL2 electrically connected to each sixth shift register G6. In other words, the first reset transistor T1, the second reset transistor T3, the voltage regulator transistor T2, the first emission control transistor T5, and the second emission control transistor T6 are each driven by a gate driver circuit. The embodiments of the present disclosure simplify the structure of the pixel circuit 100, reduce the number of gate drive circuits included in the display panel 1100, and thereby reduce the width of the peripheral area BB of the display panel, which is conducive to achieving a narrow bezel for the display panel 1100. FIG. 12 exemplarily illustrates a second shift register EM1(N), a third shift register G3(N), a fifth shift register EM2(N), and a sixth shift register G6(N) electrically connected to the Nth row of pixel circuits 100(N).

[0131] Of course, the above-mentioned multiple embodiments can be implemented separately or in combination, as long as the same technical concept is adopted. The following only lists two embodiments as examples. It is understood that the embodiments of the present disclosure are not limited to these, and other different combinations of embodiments can also be considered. The embodiments of the present disclosure will not be listed one by one.

[0132] For example, referring to FIG. 14 , the pixel circuit 100 does not include a data write transistor, and transmits different voltage signals to the first node N1 via the first reset transistor T1 during the first reset phase D1 and the data write phase D3. Furthermore, the first scan signal line GL1 and the second scan signal line GL2 are each electrically connected to a first shift register G1 of the first gate driver circuit 110. For example, the first scan signal line GL1(N) electrically connected to the pixel circuits 100(N) in the Nth row is electrically connected to the first shift register G1 of the Nth stage, and the second scan signal line GL2(N) is electrically connected to the first shift register G1 of the (N+K)th stage. Where N and K are both positive integers.

[0133] Alternatively, referring to FIG15 , the pixel circuit 100 does not include a data write transistor, and transmits different voltage signals to the first node N1 via the first reset transistor T1 during the first reset phase D1 and the data write phase D3. Furthermore, the first scan signal line GL1, the second scan signal line GL2, and the third scan signal line GL3 are each electrically connected to a first shift register G1 of the first gate driver circuit 110. For example, the first scan signal line GL1(N) electrically connected to the Nth row of pixel circuits 100(N) is electrically connected to the Nth stage of the first shift register G1, the second scan signal line GL2(N) is electrically connected to the (N+K)th stage of the first shift register G1(N+K), and the third scan signal line GL3 is electrically connected to the (N+J)th stage of the first shift register G1(N+J). N, K, and J are all positive integers, and the value of J is greater than the value of K.

[0134] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that a person skilled in the art can conceive within the technical scope disclosed in the present disclosure should be included within the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A display panel, comprising: A plurality of rows of pixel circuits, which are arranged along a first direction and each include a plurality of pixel circuits arranged along a second direction, the first direction intersecting the second direction; A first gate driving circuit, including a plurality of first shift registers arranged in cascade, and at least two first shift registers are connected to the same row of pixel circuits.

2. The display panel according to claim 1, wherein, The pixel circuit includes a driving transistor, a first reset transistor, a voltage stabilizing transistor, a first capacitor and a second capacitor; the control electrode of the driving transistor is electrically connected to a first node, the first electrode is electrically connected to a second node, and the second electrode is electrically connected to a third node; the control electrode of the first reset transistor is electrically connected to a first scan signal line, the first electrode is electrically connected to a first voltage signal line, and the second electrode is electrically connected to the first node; the control electrode of the voltage stabilizing transistor is electrically connected to a second scan signal line, the first electrode is electrically connected to a second voltage signal line, and the second electrode is electrically connected to one plate of the first capacitor; the other plate of the first capacitor is electrically connected to the second node; one plate of the second capacitor is electrically connected to the first node, and the other plate is electrically connected to the second node; Wherein, the first scan signal line and the second scan signal line are respectively electrically connected to two first shift registers.

3. The display panel according to claim 2, wherein, The first scan signal line electrically connected to the Nth row of pixel circuits is electrically connected to the Nth stage of the first shift register; the second scan signal line electrically connected to the Nth row of pixel circuits is electrically connected to the (N+K)th stage of the first shift register; wherein, both N and K are positive integers.

4. The display panel according to claim 2, wherein, The first scan signal line electrically connected to the Nth row of pixel circuits is electrically connected to the (N−M)th stage of the first shift register; the second scan signal line electrically connected to the Nth row of pixel circuits is electrically connected to the Nth stage of the first shift register; wherein, both N and M are positive integers.

5. The display panel according to any one of claims 2 to 4, wherein, The pixel circuit further includes a first light-emitting control transistor and a second reset transistor; the control electrode of the first light-emitting control transistor is electrically connected to a first light-emitting control signal line, the first electrode is electrically connected to the second node, and the second electrode is electrically connected to a fourth node; the control electrode of the second reset transistor is electrically connected to a third scan signal line, the first electrode is electrically connected to a third voltage signal line, and the second electrode is electrically connected to the fourth node; The display panel further includes a second gate driving circuit, the second gate driving circuit includes a plurality of second shift registers arranged in cascade, and a first light-emitting control signal line is electrically connected to one second shift register; Wherein, the third scan signal line is electrically connected to one first shift register, and the third scan signal line electrically connected to the Nth row of pixel circuits is electrically connected to the (N+J)th stage of the first shift register; wherein, both N and J are positive integers.

6. The display panel according to claim 5, wherein, When the second scan signal line electrically connected to the pixel circuit of the Nth row is electrically connected to the (N+K)th stage of the first shift register, the value of J is greater than the value of K.

7. The display panel according to any one of claims 2 to 4, wherein the pixel circuit further includes a first light-emitting control transistor and a second reset transistor; a control electrode of the first light-emitting control transistor is electrically connected to a first light-emitting control signal line, a first pole is electrically connected to the second node, and a second pole is electrically connected to a fourth node; a control electrode of the second reset transistor is electrically connected to a third scan signal line, a first pole is electrically connected to a third voltage signal line, and a second pole is electrically connected to the fourth node; the display panel further includes: a second gate driving circuit including a plurality of second shift registers cascaded, and a first light-emitting control signal line is electrically connected to one second shift register; a third gate driving circuit including a plurality of third shift registers cascaded, and a third scan signal line is electrically connected to one third shift register.

8. The display panel according to any one of claims 5 to 7, wherein the second voltage signal line and the third voltage signal line are configured to transmit the same voltage signal, and the second voltage signal line and the third voltage signal line are the same signal line; a first pole of the voltage stabilizing transistor is electrically connected to the fourth node and is electrically connected to the third voltage signal line through the second reset transistor.

9. The display panel according to any one of claims 5 to 7, wherein the second voltage signal line and the third voltage signal line are configured to transmit the same voltage signal, and the second voltage signal line and the third voltage signal line are the same signal line.

10. The display panel according to any one of claims 5 to 7, wherein the second voltage signal line and the third voltage signal line are configured to transmit different voltage signals, and the second voltage signal line and the third voltage signal line are different voltage signal lines.

11. The display panel according to claim 1, wherein The pixel circuit includes a driving transistor, a first reset transistor, a voltage stabilizing transistor, a first light-emitting control transistor, a second reset transistor, a first capacitor, and a second capacitor. The control electrode of the driving transistor is electrically connected to a first node, the first electrode is electrically connected to a second node, and the second electrode is electrically connected to a third node. The control electrode of the first reset transistor is electrically connected to a first scan signal line, the first electrode is electrically connected to a first voltage signal line, and the second electrode is electrically connected to the first node. The control electrode of the voltage stabilizing transistor is electrically connected to a second scan signal line, the first electrode is electrically connected to a second voltage signal line, and the second electrode is electrically connected to one plate of the first capacitor. The other plate of the first capacitor is electrically connected to the second node. One plate of the second capacitor is electrically connected to the first node, and the other plate is electrically connected to the second node. The control electrode of the first light-emitting control transistor is electrically connected to a first light-emitting control signal line, the first electrode is electrically connected to the second node, and the second electrode is electrically connected to a fourth node. The control electrode of the second reset transistor is electrically connected to a third scan signal line, the first electrode is electrically connected to a third voltage signal line, and the second electrode is electrically connected to the fourth node. Wherein, the first scan signal line and the third scan signal line are respectively electrically connected to two first shift registers.

12. The display panel according to claim 1, wherein, The pixel circuit includes a driving transistor, a first reset transistor, a voltage stabilizing transistor, a first light-emitting control transistor, a second reset transistor, a first capacitor, and a second capacitor. The control electrode of the driving transistor is electrically connected to a first node, the first electrode is electrically connected to a second node, and the second electrode is electrically connected to a third node. The control electrode of the first reset transistor is electrically connected to a first scan signal line, the first electrode is electrically connected to a first voltage signal line, and the second electrode is electrically connected to the first node. The control electrode of the voltage stabilizing transistor is electrically connected to a second scan signal line, the first electrode is electrically connected to a second voltage signal line, and the second electrode is electrically connected to one plate of the first capacitor. The other plate of the first capacitor is electrically connected to the second node. One plate of the second capacitor is electrically connected to the first node, and the other plate is electrically connected to the second node. The control electrode of the first light-emitting control transistor is electrically connected to a first light-emitting control signal line, the first electrode is electrically connected to the second node, and the second electrode is electrically connected to a fourth node. The control electrode of the second reset transistor is electrically connected to a third scan signal line, the first electrode is electrically connected to a third voltage signal line, and the second electrode is electrically connected to the fourth node. Wherein, the second scan signal line and the third scan signal line are respectively electrically connected to two first shift registers.

13. The display panel according to any one of claims 2 to 12, wherein, One frame period of the display panel includes a first reset stage and a data writing stage; In the first reset stage, the first shift register transmits a first scan signal to the first scan signal line, and the first voltage signal line transmits a first voltage signal; The first reset transistor is configured to transfer the first voltage signal to the first node under the control of the first scan signal; In the data writing stage, the first shift register transfers a first scan signal to the first scan signal line, and the first voltage signal line transfers a data signal; The first reset transistor is configured to transfer the data signal to the first node under the control of the first scan signal.

14. The display panel according to any one of claims 2 to 12, wherein The pixel circuit further includes a data writing transistor, the control electrode of the data writing transistor is electrically connected to a fourth scan signal line, the first electrode is electrically connected to a data line, and the second electrode is electrically connected to the first node; The display panel further includes a fourth gate driving circuit, the fourth gate driving circuit includes a plurality of fourth shift registers arranged in cascade, and a fourth scan signal line is electrically connected to one fourth shift register.

15. The display panel according to claim 14, wherein, One frame period of the display panel includes a first reset stage and a data writing stage; In the first reset stage, the first shift register transfers a first scan signal to the first scan signal line, and the first voltage signal line transfers a first voltage signal; The first reset transistor is configured to transfer the first voltage signal to the first node under the control of the first scan signal; In the data writing stage, the fourth shift register transfers a fourth scan signal to the fourth scan signal line, and the data line transfers a data signal; the data writing transistor is configured to transfer the data signal to the first node under the control of the fourth scan signal.

16. The display panel according to any one of claims 2 to 15, wherein The pixel circuit further includes a second light-emitting control transistor, the control electrode of the second light-emitting control transistor is electrically connected to a second light-emitting control signal line, the first electrode is electrically connected to a fourth voltage signal line, and the second electrode is electrically connected to the third node; The display panel further includes a fifth gate driving circuit, the fifth gate driving circuit includes a plurality of fifth shift registers arranged in cascade, one fifth shift register is electrically connected to at least one second light-emitting control signal line, and one row of pixel circuits is electrically connected to one fifth shift register.

17. A display device, wherein, Comprising: The display panel according to any one of claims 1 to 16; A driving circuit board, electrically connected to the display panel, and configured to transfer control signals to the display panel.

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