CMOS sensor pixel and CMOS sensor

Abstract

A CMOS sensor pixel (10) comprises a photosensitive element (100), a reset transistor (105), and a source follower (110). A terminal of the photosensitive element (100), a gate terminal (111) of the source follower (110) and a terminal of the reset transistor (105) are electrically coupled to a node (102). The CMOS sensor pixel (10) further comprises a cascode transistor (114) arranged between the photosensitive element (100) and the node (102), and a biasing circuit (118) configured to change, during a startup time of the CMOS sensor pixel (10), a gate voltage to be applied to a gate terminal (115) of the cascode transistor (114).

Description

[0001] CMOS SENSOR PIXEL AND CMOS SENSOR

[0002] Active-pixel sensors (APS ) are increasingly being used in a variety of applications such as X-ray imaging or in consumer electronics . An active-pixel sensor comprises a plurality of pixel sensor unit cells comprising a photodetector such as a photodiode and an ampli fier circuit . Generally, attempts are made to improve the performance of CMOS sensor pixels .

[0003] It is an obj ect of the present invention to provide an improved CMOS sensor pixel and an improved CMOS sensor .

[0004] SUMMARY

[0005] According to embodiments , the above obj ect is achieved by the claimed matter according to the independent claims . Further developments are defined in the dependent claims .

[0006] According to embodiments , a CMOS sensor pixel comprises a photosensitive element , a reset transistor, and a source follower . A terminal of the photosensitive element , a gate terminal of the source follower and a terminal of the reset transistor are electrically coupled to a node . The CMOS sensor pixel further comprises a cascode transistor arranged between the photosensitive element and the node , and a biasing circuit configured to change , during a startup time of the CMOS sensor pixel , a gate voltage to be applied to a gate terminal of the cascode transistor .

[0007] For example , the biasing circuit is configured to change the gate voltage to be applied to the gate terminal of the cascode transistor in dependence of a reset voltage signal applied to the gate terminal of the reset transistor . By way of example , the biasing circuit is configured to apply a larger gate voltage when the reset voltage signal is at a high level in comparison to a stage in which the reset voltage signal is at a low level .

[0008] According to embodiments , the biasing circuit comprises a startup voltage terminal and a cascode voltage terminal . A node connected to the startup voltage terminal and to the cascode voltage terminal is configured to be connected to a gate terminal of the cascode transistor .

[0009] For example , the biasing circuit comprises a bias ing transistor, and a gate terminal of the biasing transistor is connectable to a voltage signal derived from the reset voltage signal .

[0010] For example , the biasing circuit may further comprise a startup transistor . A terminal of the startup transistor and a terminal of the biasing transistor may be connected to a node connected to a gate terminal of the cascode transistor, a gate terminal of the startup transistor being connectable to the reset voltage signal .

[0011] According to further embodiments , the biasing circuit may further comprise a startup trans istor . A terminal of the startup transistor may be connected to a node connected to a terminal of the cascode transistor and to a terminal of the photosensitive element . A gate terminal of the startup transistor may be connectable to the reset voltage signal .

[0012] According to embodiments , a CMOS sensor comprising a plurality of CMOS sensor pixels as described above . According to embodiments , the startup voltage terminals of the plurality of pixels may be connected to a common startup voltage terminal .

[0013] In addition, the cascode voltage terminals of the plurality of pixels may be connected to a common cascode voltage terminal .

[0014] According to embodiments , an electronic device comprises the CMOS sensor as described above . For example , the electronic device may be selected from a smart phone , a camera, and an X- ray image sensor .

[0015] BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The accompanying drawings are included to provide a further understanding of embodiments of the invention and are incorporated in and constitute a part of this speci fication . The drawings illustrate the embodiments of the present invention and together with the description serve to explain the principles . Other embodiments of the invention and many of the intended advantages will be readily appreciated, as they become better understood by reference to the following detailed description . The elements of the drawings are not necessarily to scale relative to each other . Like reference numbers designate corresponding similar parts .

[0017] Fig . 1A is a schematic drawing of a CMOS sensor pixel according to embodiments .

[0018] Fig . IB is a diagram showing a voltage-time diagram .

[0019] Fig . 2A is an equivalent circuit diagram of a CMOS sensor pixel according to further embodiments . Fig. 2B is a voltage-time diagram of the CMOS sensor pixel illustrated in Fig. 2A.

[0020] Fig. 2C is an equivalent circuit diagram of a CMOS sensor pixel according to further embodiments.

[0021] Fig. 3 shows a CMOS sensor according to embodiments.

[0022] Fig. 4 shows an electronic device according to embodiments.

[0023] DETAILED DESCRIPTION

[0024] In the following detailed description reference is made to the accompanying drawings, which form a part hereof and in which are illustrated by way of illustration specific embodiments in which the invention may be practiced. In this regard, directional terminology such as "top", "bottom", "front", "back", "over", "on", "above", "leading", "trailing" etc. is used with reference to the orientation of the Figures being described. Since components of embodiments of the invention can be positioned in a number of different orientations, the directional terminology is used for purposes of illustration and is in no way limiting. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope defined by the claims .

[0025] The description of the embodiments is not limiting. In particular, elements of the embodiments described hereinafter may be combined with elements of different embodiments.

[0026] As employed in this specification, the terms "coupled" and / or "electrically coupled" are not meant to mean that the elements must be directly coupled together - intervening elements may be provided between the "coupled" or "electrically coupled" elements . The term "electrically connected" may describe a low-ohmic electric connection between the elements electrically connected together .

[0027] Fig . 1A is an equivalent circuit diagram of a CMOS sensor pixel 10 according to embodiments . As is shown in Fig . 1A, a CMOS sensor pixel 10 comprises a photosensitive element 100 such as e . g . a photodiode . The CMOS sensor pixel 10 further comprises a reset transistor 105 and a source follower 110 . A terminal of the photosensitive element 100 , a gate terminal 111 of the source follower 110 and a terminal of the reset transistor 105 are electrically coupled to a node 102 . The CMOS sensor pixel 10 further comprises a cascode transistor 114 that is arranged between the photosensitive element 100 and the node 102 .

[0028] The CMOS sensor pixel 10 further comprises a biasing circuit 118 which is configured to change , during a startup time of the CMOS sensor pixel 10 , a gate voltage to be applied to the gate terminal 115 of the cascode transistor 114 . The output of the source follower 110 may be connected to a column output 16 , e . g . via a selection transistor 121 .

[0029] Fig . IB shows a voltage-time diagram of a voltage at node 102 , i . e . a voltage that is appl ied to the gate terminal 111 of the source follower 110 and bias voltage Vpd between the terminals of the photodetector 100 .

[0030] When a reset voltage signal is appl ied to a gate terminal 107 of the reset transi stor 105 , the node 102 is set to a high level corresponding to a voltage level supplied by the reset voltage terminal 108 . The high voltage level is discharged due to a photocurrent generated by the photodetector 100 . Generally, leakage and dark current increase with increasing bias voltage Vpd of the photodetector . Accordingly, by decreasing a bias voltage Vpd across the photodetector during the discharge of the node 102 , leakage and dark current may be reduced . According to embodiments , due to the presence of the biasing circuit 118 , the bias voltage Vpd across the photodetector 100 may be decreased .

[0031] Fig . 2A shows an example of a CMOS sensor pixel 10 according to further embodiments .

[0032] Di f fering from embodiments illustrated in Fig . 1A, the biasing circuit 118 may comprise a biasing transistor 119 . A source or drain terminal of the biasing transistor may be connected to a cascode voltage terminal 116 . A signal which may be derived from the reset s ignal may be appl ied to a gate terminal of the biasing transistor 119 . For example , when the type of transistor of the biasing transistor 119 is identical to the transistor type of the reset transistor 105 , a signal having a waveform which is inverse to the waveform of the reset signal may be applied to the gate electrode of the biasing transistor 119 . I f the transistor type of the biasing transistor 119 is di f ferent from the transistor type of the reset transistor 105 , a signal having the same waveform as the reset signal may be applied to the gate electrode of the biasing transistor 119 .

[0033] The biasing circuit 118 may further comprise a startup transistor 112 . The reset signal terminal 113 is connected to the gate electrode of the startup transistor 112 . Moreover, a terminal , e . g . the source or the drain terminal of the startup transistor 112 is connected to a startup voltage terminal 109 . Accordingly, when the reset signal is applied to the reset transistor 105 , the same signal is applied to the startup transistor 112 . Moreover, a signal which is inverse to the reset signal may be applied to the biasing transistor 119 .

[0034] A node which is connected to a terminal of the startup transistor 112 and to a terminal of the biasing transistor 119 is connected to the gate terminal 115 of the cascode transistor 114 . As a result , during startup, a voltage corresponding to a di f ference between the startup voltage and the cascode voltage is applied to the gate terminal 115 of the cascode transistor 114 . As a result , the bias voltage at the photodetector 100 rises at a steep rate . As a consequence , a voltage at the node 102 linearly decreases from the reset level .

[0035] The image sensor pixel 10 illustrated in Fig . 2A may further comprise capacitors 122 for performing correlated double sampling ( CDS ) .

[0036] Fig . 2B shows an example of a voltage at the node 102 and a biasing voltage Vpd at the photosensitive element 100 in dependence from time . The upper portion of Fig . 2B shows the behavior of the reset signal 113 with time . As is shown, when the reset signal 113 is at a high level , the node 102 i s charged . At the same time , the bias voltage Vpd at the photosensitive element 100 is raised to an upper level and then gradually decreases . In a corresponding manner, the voltage at node 102 linearly decreases with time .

[0037] Fig . 2C shows an example of a CMOS sensor pixel 10 according to further embodiments .

[0038] Di f fering from embodiments illustrated in Fig . 1A, the biasing circuit 118 may further comprise a startup transistor 112 . The reset signal terminal 113 is connected to the gate electrode of the startup transistor 112 . Moreover, a terminal , e . g . the source or the drain terminal of the startup transistor 112 is connected to a startup voltage terminal 109 . Accordingly, when the reset signal is applied to the reset transistor 105 , the same signal is applied to the startup transistor 112 .

[0039] A node which is connected to a terminal of the startup transistor 112 is connected to a terminal of the photosensitive element 100 and further to a terminal , e . g . source or drain terminal of the cascode transistor 114 . As a result , during startup, a voltage corresponding to the startup voltage is added to the voltage at the terminal of the photodetector 100 . As a result , the bias voltage at the photodetector 100 rises at a steep rate . As a consequence , a voltage at the node 102 linearly decreases from the reset level .

[0040] Fig . 3 shows an example of a CMOS sensor 15 according to embodiments . The CMOS sensor 15 comprises a plurality of CMOS sensor pixels 10 which have been described above . For example , a column output 16 may be assigned to a column of CMOS sensor pixels 10 . The CMOS sensor 15 may further comprise a row selection line driver 150 for driving selection of lines of CMOS sensor pixels . Further, the CMOS sensor 15 may comprise a column processing device 152 for processing signals output by the column output 16 . The CMOS sensor 15 further comprises a controller 151 which may be e . g . configured to generate the voltage signals such as reset signal . The CMOS sensor 15 further comprises a pixel data processing device 153 which may be configured to process image signals into output image data For example , the image sensor 15 may further comprise a biasing line 123 which may be connected to the cascode voltage terminals 116 of the single sensor pixels 10 . Moreover, the CMOS sensor 15 may comprise a startup line 124 which may be connected to the startup voltage terminals 109 of the single pixels 10 . In this way, it is easy to implement a stitched sensor . In more detail , two extra common lines may be stitched for the whole sensor 15 . Accordingly, a large area sensor may be easily manufactured .

[0041] Fig . 4 shows an example of an electronic device 20 comprising the CMOS sensor 15 that has been explained above . The electronic device 20 may be e . g . a smartphone , or a camera or an x-ray image sensor .

[0042] As has been described above , according to embodiments , leakage and dark currents may be reduced using a standard CMOS technology using a regulating or biasing circuit having a reduced power consumption . The concept may be easi ly extended to stitched CMOS image sensors .

[0043] While embodiments of the invention have been described above , it is obvious that further embodiments may be implemented . For example , further embodiments may comprise any subcombination of features recited in the claims or any subcombination of elements described in the examples given above . Accordingly, this spirit and scope of the appended claims should not be limited to the description of the embodiments contained herein . LIST OF REFERENCES

[0044] 10 CMOS sensor pixel

[0045] 11 electromagnetic radiation

[0046] 15 CMOS sensor

[0047] 16 column output

[0048] 17 image data

[0049] 20 electronic device

[0050] 100 photosensitive element

[0051] 102 node

[0052] 105 reset transistor

[0053] 107 gate terminal of reset transistor

[0054] 108 reset voltage terminal

[0055] 109 startup voltage terminal

[0056] 110 source follower

[0057] 111 gate terminal of source follower

[0058] 112 startup transistor

[0059] 113 reset signal terminal

[0060] 114 cascode transistor

[0061] 115 gate terminal of cascode transistor

[0062] 116 cascode voltage terminal

[0063] 118 biasing circuit

[0064] 119 biasing transistor

[0065] 121 selection transistor

[0066] 122 storage capacitor

[0067] 123 biasing line

[0068] 124 startup line

[0069] 125 common startup voltage terminal

[0070] 126 common cascode voltage terminal

[0071] 150 row selection line drive

[0072] 151 controller

[0073] 152 column processing device

[0074] 153 pixel data processing device

Claims

CLAIMS1. A CMOS sensor pixel (10) comprising: a photosensitive element (100) ; a reset transistor (105) ; and a source follower (110) , a terminal of the photosensitive element (100) , a gate terminal (111) of the source follower (110) and a terminal of the reset transistor (105) being electrically coupled to a node (102) , the CMOS sensor pixel (10) further comprising a cascode transistor (114) arranged between the photosensitive element (100) and the node (102) , and a biasing circuit (118) configured to change, during a startup time of the CMOS sensor pixel (10) , a gate voltage to be applied to a gate terminal (115) of the cascode transistor (114) .

2. The CMOS sensor pixel (10) according to claim 1, wherein the biasing circuit (118) is configured to change the gate voltage to be applied to the gate terminal (115) of the cascode transistor (114) in dependence of a reset voltage signal applied to the gate terminal (107) of the reset transistor (105) .

3. The CMOS sensor pixel (10) according to claim 1 or 2, wherein the biasing circuit (118) is configured to apply a larger gate voltage when the reset voltage signal is at a high level in comparison to a stage in which the reset voltage signal is at a low level.

4. The CMOS sensor pixel (10) according to any of the preceding claims, wherein the biasing circuit (118) comprises a startup voltage terminal (109) and a cascode voltage terminal (116) , a node connected to the startup voltageterminal (109) and to the cascode voltage terminal (116) being configured to be connected to a gate terminal (115) of the cascode transistor (114) .

5. The CMOS sensor pixel (10) according to claim 4, wherein the biasing circuit (118) comprises a biasing transistor (119) , a gate terminal of the biasing transistor (119) being connectable to a voltage signal derived from a reset voltage signal.

6. The CMOS sensor pixel (10) according to claim 5, wherein the biasing circuit (118) further comprises a startup transistor (112) , a terminal of the startup transistor (112) and a terminal of the biasing transistor ( 119) being connected to a node connected to a gate terminal (115) of the cascode transistor (114) , a gate terminal of the startup transistor (112) being connectable to the reset voltage signal.

7. The CMOS sensor pixel (10) according to claim 1, wherein the biasing circuit (118) further comprises a startup transistor (112) , a terminal of the startup transistor (112) being connected to a node connected to a terminal of the cascode transistor (114) and to a terminal of the photosensitive element (100) , a gate terminal of the startup transistor (112) being connectable to the reset voltage signal .A CMOS sensor (15) comprising a plurality of CMOS sensor pixels (10) according to any of claims 1 to 3.

9. A CMOS sensor (15) comprising a plurality of CMOS sensor pixels (10) according to any of claims 4 to 7.

10. The CMOS sensor (15) according to claim 9, wherein the startup voltage terminals of the plurality of pixels are connected to a common startup voltage terminal (125) .

11. The CMOS sensor according to claim 9 or 10, wherein the cascode voltage terminals (109) of the plurality of pixels (10) are connected to a common cascode voltage terminal (126) .

12. An electronic device (20) comprising the CMOS sensor (10) according to any of claims 8 to 11.

13. The electronic device (20) according to claim 12, being selected from a smart phone, a camera, and an X-ray image sensor .

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