Gate drive circuit and operating method therefor, display substrate, and display apparatus

Abstract

Disclosed are a gate drive circuit and an operating method therefor, a display substrate, and a display apparatus. The gate drive circuit comprises multiple stages of shift register circuits (100), and multiple stages of logic operation circuits (200) respectively connected to the multiple stages of shift register circuits, wherein the multiple stages of shift register circuits (100) are connected in a cascaded manner; among at least one stage of shift register circuit (100), each stage of shift register circuit (100) is configured to receive a first clock signal (CKV1), and output a first input signal (A_Q n_) to a corresponding logic operation circuit (200) under the control of the first clock signal (CKV1); and among at least one stage of logic operation circuit (200), each stage of logic operation circuit (200) is configured to output a write-in switch signal (WSn) under the control of the first input signal (A_Q n_), the write-in switch signal (WSn) comprises two valid signals, and the sum of pulse widths of the two valid signals is less than or equal to the period (T1) of the first clock signal (CKV1).

Description

Gate drive circuit and operating method thereof, display substrate, and display device

[0001] This application claims priority to PCT international applications No. PCT / CN2024 / 071143, No. PCT / CN2024 / 071152, and No. PCT / CN2024 / 071147, filed on January 8, 2024, and priority to Chinese patent applications No. 202410129327.2, No. 202410130614.5, and No. 202410130058.1, filed on January 30, 2024. The contents of the above-mentioned PCT international applications and Chinese patent applications should be understood as being incorporated into this application by reference. Technical Field

[0002] The embodiments of the present disclosure relate to, but are not limited to, the field of display technology, and specifically to a gate driving circuit and a working method thereof, a display substrate, and a display device. Background Art

[0003] Micro-OLEDs (Micro Organic Light-Emitting Diodes) are a type of microdisplay that has been developed in recent years, with silicon-based OLEDs being one of them. Silicon-based OLEDs are a novel display technology that combines semiconductor manufacturing processes with OLED display technology, using wafers as substrates to manufacture OLED devices. By combining the advantages of both semiconductor manufacturing processes and OLED display technology, silicon-based OLEDs not only offer a high pixel density (PPI), but also high brightness, low power consumption, fast response time, a wide color gamut, and excellent thermal stability.

[0004] Summary of the Invention

[0005] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0006] In a first aspect, an embodiment of the present disclosure provides a gate driving circuit, comprising a multi-stage shift register circuit and a multi-stage logic operation circuit respectively connected to the multi-stage shift register circuit, wherein the multi-stage shift register circuit is cascade-connected;

[0007] In the at least one stage of shift register circuit, each stage of the shift register circuit is configured to receive a first clock signal and output a first input signal to a corresponding logic operation circuit under the control of the first clock signal;

[0008] In at least one level of logic operation circuit, each level of logic operation circuit is configured to output a write switch signal under the control of the first input signal, and the write switch signal includes two valid signals, and the sum of the pulse widths of the two valid signals is less than or equal to the period of the first clock signal.

[0009] In an exemplary embodiment, in the at least one stage of the shift register circuit, each stage of the shift register circuit includes a first signal input terminal, a first clock signal terminal, and a first shift signal output terminal, and is configured to receive the first signal through the first signal input terminal and the first clock signal through the first clock signal terminal, shift the first signal under control of the first clock signal to obtain the first input signal, and provide the first input signal to the corresponding logic operation circuit through the first shift signal output terminal;

[0010] The pulse width of the effective signal in the first input signal is S periods of the first clock signal, where S is a positive integer.

[0011] In an exemplary embodiment, the shift register circuit is configured to control a pulse width of a valid signal in the first input signal by a pulse width of a valid signal in the first signal.

[0012] In an exemplary embodiment, the end time of the valid signal in the first input signal output by the n-th stage shift register circuit is synchronized with the start time of the valid signal in the first input signal output by the n+S-th stage shift register circuit, where n is a positive integer; the start time of the valid signal in the first input signal output by the n+S-th stage shift register circuit is no earlier than the end time of the valid signal in the first input signal output by the n-th stage shift register circuit.

[0013] In an exemplary embodiment, in the at least one level of logic operation circuit, each level of logic operation circuit includes a first input terminal and a write switch signal terminal, and is configured to receive the first input signal through the first input terminal, generate the write switch signal under the control of the first input signal, and output the write switch signal through the write switch signal terminal;

[0014] In the at least one level of logic operation circuit, each level of logic operation circuit, under the control of the first input signal received at the first input end of this level, generates a start time of the first valid signal in the write switch signal, which is synchronized with the start time of the valid signal in the first input signal received at the first input end of this level; and generates an end time of the second valid signal in the write switch signal, which is synchronized with the end time of the valid signal in the first input signal received at the first input end of this level.

[0015] In an exemplary embodiment, in the at least one stage of the shift register circuit, a phase relationship between the first signal received by each stage of the shift register circuit in one light-emitting cycle and the first clock signal includes:

[0016] The rising edge time of the first signal is no later than the first rising edge time of the first clock signal;

[0017] The falling edge time of the first signal is no earlier than the time of the Sth rising edge of the first clock signal and no earlier than the time of the S+1th rising edge of the first clock signal.

[0018] In an exemplary embodiment, in the at least one stage of the shift register circuit, each stage of the shift register circuit further includes a second signal input terminal, a second clock signal terminal, and a second shift signal output terminal. The shift register circuit is configured to receive a second signal through the second signal input terminal and a second clock signal through the second clock signal terminal, and shift the second signal under control of the second clock signal to obtain a second input signal, and provide the second input signal to the corresponding logic operation circuit through the second shift signal output terminal. In the at least one stage of the logic operation circuit, each stage of the logic operation circuit further includes a second input terminal, configured to receive the second input signal through the second input terminal, and generate the write switch signal under control of the first input signal and the second input signal.

[0019] In the at least one level of logic operation circuit, the end time of the first valid signal in the write switch signal generated by each level of logic operation circuit under the control of the second input signal received at the second input end of this level is synchronized with the start time of the valid signal in the second input signal received at the second input end of this level.

[0020] In an exemplary embodiment, in the at least one level of logic operation circuit, the start time of the valid signal in the first input signal received by the first input terminal of each level of logic operation circuit is earlier than the start time of the valid signal in the second input signal received by the second input terminal of the current level.

[0021] In an exemplary embodiment, in the at least one level of logic operation circuit, each level of logic operation circuit is configured to control the pulse width of the first valid signal in the write switch signal by the difference between the start time of the valid signal in the second input signal and the start time of the valid signal in the first input signal.

[0022] In an exemplary embodiment, the shift register circuit is configured to control a pulse width of a valid signal in the second input signal by a pulse width of a valid signal in the second signal.

[0023] In an exemplary embodiment, the cycle duration of the second clock signal is consistent with the cycle duration of the first clock signal. In the at least one stage of the shift register circuit, the phase relationship between the second signal received by each stage of the shift register circuit in one light-emitting cycle and the second clock signal includes:

[0024] The rising edge time of the second signal is no later than the first rising edge time of the second clock signal;

[0025] The falling edge time of the second signal is no earlier than the time of the Sth rising edge of the second clock signal and no earlier than the time of the S+1th rising edge of the second clock signal.

[0026] In an exemplary embodiment, in the at least one stage of the shift register circuit, each stage of the shift register circuit further includes a third signal input terminal, a third clock signal terminal, and a third shift signal output terminal, and is configured to receive a third signal through the third signal receiving terminal and a third clock signal through the third clock signal terminal, and shift the third signal under control of the third clock signal to obtain a third input signal, and provide the third input signal to the corresponding logic operation circuit through the third shift signal output terminal; in the at least one stage of the logic operation circuit, each stage of the logic operation circuit further includes a third input terminal, and is configured to receive the third input signal through the third input terminal, and generate the write switch signal under control of the first input signal, the second input signal, and the third input signal;

[0027] In the at least one level of logic operation circuit, the start time of the second valid signal in the write switch signal generated by each level of logic operation circuit under the control of the third input signal received at the third input terminal of this level is synchronized with the end time of the valid signal in the third input signal received at the third input terminal of this level.

[0028] In an exemplary embodiment, in the at least one level of logic operation circuit, the end time of the valid signal in the first input signal received by the first input terminal of each level of logic operation circuit is later than the end time of the valid signal in the third input signal received by the third receiving terminal of the current level.

[0029] In an exemplary embodiment, in the at least one level of logic operation circuit, each level of logic operation circuit is configured to control the pulse width of the second valid signal in the write switch signal by the difference between the end time of the valid signal in the first input signal and the end time of the valid signal in the third input signal.

[0030] In an exemplary embodiment, the shift register circuit is configured to control a pulse width of a valid signal in the third input signal by a pulse width of a valid signal in the third signal.

[0031] In an exemplary embodiment, the cycle length of the third clock signal is consistent with the cycle length of the first clock signal. In the at least one stage of the shift register circuit, the phase relationship between the third signal received by each stage of the shift register circuit in one light-emitting cycle and the third clock signal includes:

[0032] The rising edge time of the third signal is no later than the first rising edge time of the third clock signal;

[0033] The falling edge time of the third signal is no earlier than the time of the Sth rising edge of the third clock signal and no earlier than the time of the S+1th rising edge of the third clock signal.

[0034] In an exemplary embodiment, the end time of the valid signal in the first input signal output by the n-th stage shift register circuit differs from the start time of the valid signal in the first input signal output by the (n+m)-th stage shift register circuit by mS cycles of the first clock signal, where m is a positive integer; the start time of the valid signal in the first input signal output by the n-th stage shift register circuit differs from the start time of the valid signal in the first input signal output by the (n+m)-th stage shift register circuit by m cycles of the first clock signal.

[0035] In an exemplary embodiment, the n-th stage shift register circuit is connected to the n-th stage logic operation circuit and is configured to provide a first input signal to the n-th stage logic operation circuit; the n+m-th stage shift register circuit is connected to the n+m-th stage logic operation circuit and is configured to provide a first input signal to the n+m-th stage logic operation circuit;

[0036] The n-th level logic operation circuit is configured to generate a write switch signal under the control of the first input signal output by the n-th level shift register circuit, and the n+m-th level logic operation circuit is configured to generate a write switch signal under the control of the first input signal output by the n+m-th level shift register circuit; the end time of the second valid signal in the write switch signal generated by the n-th level logic operation circuit differs from the start time of the first valid signal in the write switch signal generated by the n+m-th level logic operation circuit by mS cycles of the first clock signal; the start time of the first valid signal in the write switch signal generated by the n-th level logic operation circuit differs from the start time of the first valid signal in the write switch signal generated by the n+m-th level logic operation circuit by m cycles of the first clock signal.

[0037] In an exemplary embodiment, at least one level of logic operation circuit includes a fourth clock signal terminal, the fourth clock signal terminal being configured to receive a fourth clock signal, the cycle duration of the fourth clock signal being consistent with the cycle duration of the first clock signal;

[0038] Under the control of the fourth clock signal, the end time of the second valid signal in the write switch signal output by the n-th level logic operation circuit is different from the start time of the first valid signal in the write switch signal output by the n+S-th level logic operation circuit by a first time interval, and the length of the first time interval is the length of the valid signal in one cycle of the fourth clock signal.

[0039] In an exemplary embodiment, one light-emitting cycle includes S cycles of the fourth clock signal. In a light-emitting cycle corresponding to the n-th level logic operation circuit, the end time of the second valid signal in the write switch signal output by the n-th level logic operation circuit is synchronized with the S-th rising edge of the fourth clock signal received by the n-th level logic operation circuit, and the start time of the first valid signal in the write switch signal output by the n+S-th level logic operation circuit is synchronized with the S-th falling edge of the fourth clock signal received by the n+S-th level logic operation circuit.

[0040] In an exemplary embodiment, the difference between the start time of the first valid signal in the write switch signal output by the n-th level logic operation circuit and the start time of the first valid signal in the write switch signal output by the n+1-th level logic operation circuit is greater than or equal to the pulse width of the second valid signal, and n is a positive integer;

[0041] In a second aspect, the present disclosure provides a gate driving method, which is applied to the gate driving circuit described in any of the above embodiments, wherein the gate driving circuit includes a multi-stage shift register circuit and a multi-stage logic operation circuit respectively connected to the multi-stage shift register circuit, and the multi-stage shift register circuit is cascade-connected; the working method includes:

[0042] Each shift register circuit in at least one stage of the shift register circuit receives a first clock signal and outputs a first input signal to a corresponding logic operation circuit under the control of the first clock signal;

[0043] Each level of logic operation circuit in at least one level of logic operation circuit outputs a write switch signal under the control of the first input signal, and the write switch signal includes two valid signals, and the sum of the pulse widths of the two valid signals is less than or equal to the period of the first clock signal.

[0044] In a third aspect, the present disclosure provides a display substrate comprising a display area and a non-display area; the display area comprises a plurality of sub-pixels, at least one sub-pixel comprises a pixel driving circuit and at least one scanning signal line, and the scanning signal line is configured to provide a scanning signal to the connected pixel driving circuit; the non-display area comprises a plurality of cascaded gate driving circuits, at least one gate driving circuit is connected to the scanning signal line in the display area, and at least one gate driving circuit comprises the gate driving circuit described in any of the above embodiments.

[0045] In a fourth aspect, the present disclosure provides a display device comprising the display substrate described in any of the above embodiments.

[0046] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] The accompanying drawings are intended to facilitate understanding of the technical solutions of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solutions of the present disclosure and do not constitute a limitation of the technical solutions of the present disclosure. The shapes and sizes of each component in the drawings do not reflect the actual scale and are intended only to illustrate the contents of the present disclosure.

[0048] FIG1 is a schematic structural diagram of a silicon-based OLED display device;

[0049] FIG2 is a schematic diagram of a planar structure of a display area in a silicon-based OLED display device;

[0050] FIG3 is a schematic diagram of the cross-sectional structure of a display area in a silicon-based OLED display device;

[0051] FIG4 a is an equivalent circuit diagram of a pixel driving circuit;

[0052] FIG4 b is an equivalent circuit diagram of a pixel driving circuit;

[0053] FIG5a is a driving timing diagram of the pixel driving circuit shown in FIG4b;

[0054] FIG5b is a driving timing diagram of the pixel driving circuit shown in FIG4b;

[0055] FIG6 a is a schematic structural diagram of a gate driving circuit according to an exemplary embodiment of the present disclosure;

[0056] FIG6 b is a junction operation timing diagram of a gate driving circuit according to an exemplary embodiment of the present disclosure;

[0057] FIG6 c is a junction operation timing diagram of a gate driving circuit according to an exemplary embodiment of the present disclosure;

[0058] FIG6 d is a schematic structural diagram of a gate driving circuit according to an exemplary embodiment of the present disclosure;

[0059] FIG6e is a schematic structural diagram of a gate driving circuit according to an exemplary embodiment of the present disclosure;

[0060] FIG7 is a working principle diagram of a first operation circuit according to an exemplary embodiment of the present disclosure;

[0061] FIG8 is an equivalent circuit diagram of a first operation circuit according to an exemplary embodiment of the present disclosure;

[0062] FIG9 a is a working principle diagram of a second operation circuit according to an exemplary embodiment of the present disclosure;

[0063] FIG9b is a working principle diagram of the latch in FIG9a provided by an exemplary embodiment of the present disclosure;

[0064] FIG9c is a timing diagram of an operation of a latch provided by an exemplary embodiment of the present disclosure;

[0065] FIG10 is an equivalent circuit diagram of a second operation circuit according to an exemplary embodiment of the present disclosure;

[0066] FIG11 is a working principle diagram of a third operation circuit according to an exemplary embodiment of the present disclosure;

[0067] FIG12 is an equivalent circuit diagram of a third operation circuit according to an exemplary embodiment of the present disclosure;

[0068] FIG13 is a working principle diagram of a level converter according to an exemplary embodiment of the present disclosure;

[0069] FIG14 is a working principle diagram of a row drive enhancer according to an exemplary embodiment of the present disclosure;

[0070] FIG15 is an equivalent circuit diagram of a level converter according to an exemplary embodiment of the present disclosure;

[0071] FIG16 is an equivalent circuit diagram of a row driver booster according to an exemplary embodiment of the present disclosure;

[0072] FIG17 is an equivalent circuit diagram of an output circuit according to an exemplary embodiment of the present disclosure;

[0073] FIG18 is a schematic structural diagram of a shift register circuit according to an exemplary embodiment of the present disclosure;

[0074] FIG19 is a diagram showing the working principle of a trigger according to an exemplary embodiment of the present disclosure;

[0075] FIG20 is a timing diagram of an operation of a trigger according to an exemplary embodiment of the present disclosure;

[0076] FIG21 is an equivalent circuit diagram of a trigger according to an exemplary embodiment of the present disclosure;

[0077] FIG22 is a timing diagram of an operation of a trigger according to an exemplary embodiment of the present disclosure;

[0078] FIG23 is a timing diagram of an operation of a trigger according to an exemplary embodiment of the present disclosure;

[0079] FIG24 is a timing diagram of an operation of a trigger according to an exemplary embodiment of the present disclosure;

[0080] FIG25 is a timing diagram of an operation of a trigger according to an exemplary embodiment of the present disclosure;

[0081] FIG26 is an operation timing diagram of a shift register circuit according to an exemplary embodiment of the present disclosure;

[0082] FIG27 a is an operation timing diagram of a shift register circuit according to an exemplary embodiment of the present disclosure;

[0083] FIG27 b is an operation timing diagram of a shift register circuit according to an exemplary embodiment of the present disclosure;

[0084] FIG27c is an operation timing diagram of a shift register circuit according to an exemplary embodiment of the present disclosure;

[0085] FIG27 d is an operation timing diagram of a shift register circuit according to an exemplary embodiment of the present disclosure;

[0086] FIG28 is a working principle diagram of a first test circuit according to an exemplary embodiment of the present disclosure;

[0087] FIG29 is a working principle diagram of a second test circuit according to an exemplary embodiment of the present disclosure;

[0088] FIG30 is a working principle diagram of a third test circuit according to an exemplary embodiment of the present disclosure;

[0089] FIG31 is a schematic structural diagram of a display substrate according to an exemplary embodiment of the present disclosure;

[0090] FIG32 is a schematic structural diagram of a display device according to an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION

[0091] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. The embodiments can be implemented in a number of different forms. A person of ordinary skill in the art can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. Unless there is a conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other. In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits detailed descriptions of some known functions and known components. The drawings of the embodiments of the present disclosure only relate to the structures involved in the embodiments of the present disclosure, and other structures can refer to the general design.

[0092] The scales of the figures in this disclosure can be used as a reference for actual processes, but are not limited to such. For example, the width-to-length ratio of the channel, the thickness and spacing of the various film layers, and the width and spacing of the various signal lines can be adjusted according to actual needs. The number of pixels in the display device and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures. The figures described in this disclosure are merely schematic structural diagrams, and one embodiment of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0093] In this specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0094] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limiting the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the direction in which each constituent element is described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced according to the circumstances.

[0095] In this specification, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the specific meanings of these terms in this disclosure.

[0096] In this specification, a transistor refers to a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0097] In this specification, in order to distinguish the two electrodes of a transistor other than the gate electrode, one of the electrodes is directly described as the first electrode and the other as the second electrode. The first electrode can be the drain electrode and the second electrode can be the source electrode, or the first electrode can be the source electrode and the second electrode can be the drain electrode. In cases where transistors with opposite polarity are used or where the direction of current changes during circuit operation, the functions of the "source electrode" and "drain electrode" are sometimes interchangeable. Therefore, in this specification, the terms "source electrode" and "drain electrode" can be interchanged.

[0098] In this specification, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables the transfer of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0099] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state where the angle is greater than 85° and less than 95°.

[0100] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film." Similarly, "insulating film" may be replaced with "insulating layer."

[0101] In this specification, the term "same-layer arrangement" refers to a structure formed by patterning two (or more) structures using the same patterning process. The materials of these structures can be the same or different. For example, the precursor materials for forming the multiple structures arranged in the same layer can be the same, and the materials of the final structures can be the same or different.

[0102] The triangles, rectangles, trapezoids, pentagons or hexagons in this specification are not in the strict sense, but may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.

[0103] The term "about" in the present disclosure refers to a numerical value that is not strictly defined and allows for process and measurement errors.

[0104] FIG1 is a schematic diagram of the structure of a silicon-based OLED display device. As shown in FIG1 , the silicon-based OLED display device may include a display area and a non-display area. The display area may include multiple scan signal lines, multiple data signal lines, and multiple sub-pixels Pxij forming multiple pixel rows and multiple pixel columns. The multiple scan signal lines are respectively arranged in the multiple pixel rows, and the multiple data signal lines are respectively arranged in the multiple pixel columns. Each sub-pixel Pxij may include at least a pixel driving circuit and a light-emitting device. The pixel driving circuit is configured to provide the current required for light emission to the connected light-emitting device. The pixel driving circuit of each sub-pixel Pxij may be connected to the scan signal line of the corresponding pixel row and the data signal line of the corresponding pixel column. The sub-pixel Pxij may refer to the sub-pixel in the i-th pixel row and the j-th pixel column. The pixel driving circuit of the sub-pixel Pxij is respectively connected to the i-th scan signal line and the j-th data signal line, where i and j may be natural numbers. The non-display area may include a display driver integrated circuit (DDIC), a gate driver (GD), and a data driver (SD). The display driver circuit may include at least a timing controller (TCON). The timing controller is configured to generate timing signals required by the gate driver, such as a start signal (STV) and a clock signal (CKV), and send the timing signals to the gate driver. The gate driver is respectively connected to a plurality of scan signal lines in the display area, and the gate driver is configured to provide the required timing signals (timing) to the connected pixel driver circuit to realize the display progressive scanning function. The data driver is respectively connected to a plurality of data signal lines in the display area, and the data driver is configured to provide the required data signals (data) to the connected pixel driver circuit to realize the switching and control of the display screen.

[0105] In one exemplary embodiment, a silicon-based OLED display device may utilize a single-chip display architecture ("One Chip"), integrating a gate driver, data driver, clock control unit, image processing unit, and storage unit on a single chip. A chip with a One Chip architecture includes both digital and analog components, making it a mixed-signal chip.

[0106] In another exemplary embodiment, the silicon-based OLED display device can be a dual-chip display architecture (Two Chip), in which the gate driving device and the data driving device are integrated in the display substrate, and the clock control unit, the image processing unit, the mobile industry processor interface (MIPI) and the storage unit are integrated in one chip, which is bonded to the display substrate through the COC process.

[0107] Figure 2 is a schematic diagram of the planar structure of a display area in a silicon-based OLED display device. As shown in Figure 2, the display area may include multiple pixel units P arranged in a matrix on a plane parallel to the display device. At least one pixel unit P may include a first sub-pixel P1 that emits a first color light, a second sub-pixel P2 that emits a second color light, and a third sub-pixel P3 that emits a third color light. Each of the three sub-pixels may include a pixel driving circuit and a light-emitting device. The pixel driving circuit in the sub-pixel is respectively connected to a scan signal line and a data signal line. The pixel driving circuit is configured to receive a data voltage transmitted by the data signal line under the control of the scan signal line and output a corresponding current to the display light-emitting device. The light-emitting device in the sub-pixel is connected to the pixel driving circuit of the sub-pixel in which it is located. The light-emitting device is configured to emit light of corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel in which it is located.

[0108] In an exemplary embodiment, the first subpixel P1 may be a red (R) subpixel emitting red light, the second subpixel P2 may be a blue (B) subpixel emitting blue light, and the third subpixel P3 may be a green (G) subpixel emitting green light.

[0109] In an exemplary embodiment, the shape of the sub-pixels can be any one or more of a triangle, square, rectangle, rhombus, trapezoid, parallelogram, pentagon, hexagon, and other polygons. The three sub-pixels can be arranged in a horizontal parallel arrangement, a vertical parallel arrangement, a herringbone arrangement, etc., which is not limited in this disclosure. In other possible embodiments, the pixel unit can include four sub-pixels, which is not limited in this disclosure.

[0110] FIG3 is a schematic diagram of the cross-sectional structure of the display area in a silicon-based OLED display device, illustrating a structure that uses white light + color filter to achieve full color. As shown in FIG3 , in a direction perpendicular to the display device, the silicon-based OLED display device may include: a silicon substrate 101, a driving circuit layer 102 disposed on the silicon substrate 101, a light-emitting structure layer 103 disposed on the side of the driving circuit layer 102 away from the silicon substrate 101, a first encapsulation layer 104 disposed on the side of the light-emitting structure layer 103 away from the silicon substrate 101, a color filter structure layer 105 disposed on the side of the first encapsulation layer 104 away from the silicon substrate 101, a second encapsulation layer 106 disposed on the side of the color filter structure layer 105 away from the silicon substrate 101, and a cover layer 107 disposed on the side of the second encapsulation layer 106 away from the silicon substrate 101. In some possible implementations, the silicon-based OLED display device may include other film layers, which are not limited in this disclosure.

[0111] In an exemplary embodiment, the silicon substrate 101 may be a bulk silicon substrate or a silicon-on-insulator (SOI) substrate. The driving circuit layer 102 may be prepared on the silicon substrate 101 by a silicon semiconductor process. The driving circuit layer 102 may include a plurality of circuit units. The circuit units may include at least a pixel driving circuit. The pixel driving circuit is connected to a scanning signal line and a data signal line, respectively. The pixel driving circuit may include a plurality of transistors and a storage capacitor. FIG3 shows only one transistor as an example. The transistor may include a gate electrode G, a first electrode S, and a second electrode D. The gate electrode G, the first electrode S, and the second electrode D may be connected to corresponding connection electrodes through tungsten metal-filled vias (i.e., tungsten vias, W-vias), and may be connected to other electrical structures (such as traces, etc.) through the connection electrodes.

[0112] In an exemplary embodiment, the light-emitting structure layer 103 may include a plurality of light-emitting devices, each of which may include at least an anode, an organic light-emitting layer, and a cathode. The anode may be connected to the second pole D of the transistor via a connecting electrode, the organic light-emitting layer is connected to the anode, the cathode is connected to the organic light-emitting layer, and the cathode is connected to the second power line. The organic light-emitting layer emits light under the drive of the anode and the cathode. In an exemplary embodiment, the organic light-emitting layer may include a light-emitting layer (EML for short), and any one or more of the following: a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). In an exemplary embodiment, for a light-emitting device that emits white light, the organic light-emitting layers of all sub-pixels may be a common layer connected together.

[0113] In an exemplary embodiment, the first encapsulation layer 104 and the second encapsulation layer 106 can be encapsulated using a thin film encapsulation (TFE) method to ensure that external moisture cannot enter the light-emitting structure layer. The color filter structure layer 105 can include at least a red filter unit, a blue filter unit, and a green filter unit. The red filter unit is set in the red sub-pixel to filter the white light emitted by the light-emitting device into red light. The blue filter unit is set in the blue sub-pixel to filter the white light emitted by the light-emitting device into blue light. The green filter unit is set in the green sub-pixel to filter the white light emitted by the light-emitting device into green light. The cover layer 107 can be made of glass or a flexible plastic material such as colorless polyimide.

[0114] Figure 4a is an equivalent circuit diagram of a pixel driving circuit. As shown in Figure 4a, the pixel driving circuit has a 4T2C structure, which can include four transistors (a first transistor T1, a second transistor T2, a third transistor T3, and a fourth transistor T4) and two storage capacitors (a first capacitor C1 and a second capacitor C2). The pixel driving circuit is connected to six signal lines (a first scan signal line S1, a second scan signal line S2, a third scan signal line S3, a data signal line DATA, a first power line VDD, and a second power line VSS).

[0115] In an exemplary embodiment, the pixel driving circuit may include a first node N1, a second node N2, and a third node N3. The first node N1 is connected to the second electrode of the first transistor T1, the gate electrode of the third transistor T3, and the first end of the first capacitor C1, respectively. The second node N2 is connected to the second electrode of the second transistor T2, the first electrode of the third transistor T3, the second end of the first capacitor C1, and the first end of the second capacitor C2, respectively. The third node N3 is connected to the second electrode of the third transistor T3 and the second electrode of the fourth transistor T4, respectively.

[0116] In an exemplary embodiment, the first transistor T1 can be referred to as a write switch transistor, a gate electrode of the first transistor T1 is connected to the first scan signal line S1, a first electrode of the first transistor T1 is connected to the data signal line DATA, and a second electrode of the first transistor T1 is connected to the first node N1.

[0117] In an exemplary embodiment, the second transistor T2 is called a display switch transistor, a gate electrode of the second transistor T2 is connected to the second scan signal line S2, a first electrode of the second transistor T2 is connected to the first power line VDD, and a second electrode of the second transistor T2 is connected to the second node N2.

[0118] In an exemplary embodiment, the third transistor T3 may be referred to as a driver transistor, a gate electrode of the third transistor T3 is connected to the first node N1, a first electrode of the third transistor T3 is connected to the second node N2, and a second electrode of the third transistor T3 is connected to the third node N3.

[0119] In an exemplary embodiment, the fourth transistor T4 can be called an auto zero transistor, a gate electrode of the fourth transistor T4 is connected to the third scan signal line S3, a first electrode of the fourth transistor T4 is connected to the second power line VSS, and a second electrode of the fourth transistor T4 is connected to the third node N3.

[0120] In an exemplary embodiment, a first end of the first capacitor C1 is connected to the first node N1, a second end of the first capacitor C1 is connected to the second node N2, a first end of the second capacitor C2 is connected to the second node N2, and a second end of the second capacitor C2 is connected to the first power line VDD.

[0121] In an exemplary embodiment, the light emitting device EL may be an organic electroluminescent diode (OLED) including a stacked first electrode (anode), an organic light emitting layer, and a second electrode (cathode). The first electrode of the light emitting device XL is connected to the third node N3, and the second electrode of the light emitting device EL is connected to the common voltage line VCOM.

[0122] In an exemplary embodiment, the signal of the first power line VDD may be a continuously provided high level signal, and the signals of the second power line VSS and the common voltage line VCOM may be continuously provided low level signals.

[0123] In an exemplary embodiment, the first to fourth transistors T1 to T4 may be P-type transistors (PMOS) or N-type transistors (NMOS). For example, the first to fourth transistors T1 to T4 are all P-type transistors. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the difficulty of manufacturing the display substrate, and improve the product yield.

[0124] In an exemplary embodiment, the first to fourth transistors T1 to T4 may include P-type transistors and N-type transistors. For example, the first to third transistors T1 to T3 may be P-type transistors, and the fourth transistor T4 may be an N-type transistor, as shown in FIG4a. In an exemplary embodiment, the first to fourth transistors T1 to T4 are all P-type transistors. For example, the first to fourth transistors T1 to T4 may all be P-type transistors, as shown in FIG4b.

[0125] FIG5a is a driving timing diagram of the pixel driving circuit shown in FIG4a. As shown in FIG5a, in an exemplary embodiment, the operation process of the pixel driving circuit may include:

[0126] The first phase A1 (from the first moment t1 to the second moment t2) can be called the initialization phase. The signals of the first scan signal line S1 and the second scan signal line S2 are low-level signals, and the signal of the third scan signal line S3 is a high-level signal, so that the first transistor T1, the second transistor T2 and the fourth transistor T4 are turned on. The first transistor T1 is turned on so that the bias voltage Vofs output by the data signal line DATA is written into the first capacitor C1, and the potential Vs of the first node N1 (i.e., the gate electrode of the third transistor T3) is Vofs. The second transistor T2 is turned on so that the first power supply voltage ELVDD output by the first power line VDD is written into the second node N2, and the potential Vg of the second node N2 (i.e., the first electrode of the third transistor T3) is ELVDD. At this time, the gate-source voltage Vgs of the third transistor T3 is ELVDD-Vofs, and the storage voltage V of the first capacitor C1 is V cs =ELVDD-Vofs, the potential Vd of the third node N3 (ie, the second electrode of the third transistor T3) = Vg+Vth, preparing for the next stage of discharge. ofs >|Vth|, where Vth is the threshold voltage of the third transistor T3.

[0127] The second stage A2 (from the second moment t2 to the third moment t3) can be called the self-discharge stage. The signal of the third scanning signal line S3 is a high-level signal, and the fourth transistor T4 is continuously turned on. The signal of the first scanning signal line S1 changes from a low-level signal to a high-level signal, causing the first transistor T1 to be disconnected first, and the first node N1 to float. Subsequently, the signal of the second scanning signal line S2 changes from a low-level signal to a high-level signal, causing the second transistor T2 to be disconnected, and the second node N2 forms a loop through the turned-on third transistor T3, the third node N3 and the turned-on fourth transistor T4, and begins to discharge, and the potential of the second node N2 drops. Because the first node N1 is floating, the voltage difference across the first capacitor C1 remains unchanged, and thus the potential of the first node N1 drops as the potential of the second node N2 drops. Due to the back gate effect of the third transistor T3, the gate-source voltage Vgs of the third transistor T3 remains unchanged, and thus the equivalent threshold voltage |V th_EF |As the potential of the second node N2 decreases, the equivalent threshold voltage of the third transistor T3 gradually increases. th_EF |=α(ELVDD-Vs)+|Vth|, α is the back gate coefficient. When the equivalent threshold voltage of the third transistor T3 |V th_EF When Vgs increases to the gate-source voltage Vgs of the third transistor T3, the third transistor T3 is turned off and the second node N2 stops discharging.

[0128] The third stage A3 (from the third moment t3 to the fourth moment t4) can be called the data writing stage and the threshold compensation stage. The signal of the second scan signal line S2 is a high-level signal, and the second transistor T2 is continuously disconnected. The signal of the third scan signal line S3 is a high-level signal, and the fourth transistor T4 is continuously turned on. The signal of the first scan signal line S1 changes from a high-level signal to a low-level signal, turning on the first transistor T1. The first transistor T1 is turned on so that the data voltage Vdata output by the data signal line DATA is written to the first node N1, and the potential of the first node N1 changes from Vofs to Vdata. Since the second node N2 is floating, threshold compensation can be achieved in this stage.

[0129] The fourth phase A4 (after the fifth moment t5) can be called the light-emitting phase. The signals on the second scan signal line S2 and the third scan signal line S3 are low-level signals, and the signal on the first scan signal line S1 is high-level signal, turning on the second transistor T2 and turning off the first transistor T1 and the fourth transistor T4. Turning on the second transistor T2 causes the power supply voltage output from the first power line VDD to provide a driving voltage to the first electrode of the light-emitting device EL through the turned-on second transistor T2 and third transistor T3, driving the light-emitting device EL to emit light.

[0130] The fourth moment t4 is the moment when the signal of the first scanning signal line S1 changes from a low level to a high level, that is, the end time of the second valid signal in the signal of the first scanning signal line S1.

[0131] In the light-emitting stage, the driving current of the third transistor T3 is not affected by the threshold voltage of the third transistor T3, eliminating the influence of the threshold voltage of the third transistor T3 on the driving current, ensuring uniform display brightness of the display product and improving the display effect of the entire display product.

[0132] FIG5 b is a driving timing diagram of the pixel driving circuit shown in FIG4 b . As shown in FIG5 b , the operation process of the pixel driving circuit in FIG4 b may include a first stage A1 to a fourth stage A4. FIG5 b differs from FIG5 a in that the timing of the third scanning signal line S3 is different. In FIG4 a and FIG5 a , the fourth transistor T4 is an N-type transistor (high level turns on, low level turns off), while in FIG4 b and FIG5 b , the fourth transistor T4 is a P-type transistor (high level turns off, low level turns on).

[0133] As can be seen from Figures 5a and 5b, during a light-emitting cycle, the write switch signal WS (i.e., the signal written to the first scanning signal line S1) has two pulse widths. The first pulse width is used to read the threshold voltage, while the second pulse width is used to write the grayscale voltage and compensate for the threshold voltage. These two pulse widths of the write switch signal WS are crucial for the pixel driver circuit to properly drive the light-emitting device EL to emit light. In the case of progressive scanning, the pulse widths of the valid signals in the write switch signal WS for multiple rows may overlap at the same time, causing the first transistors T1 in the pixel driver circuits for multiple rows to be turned on at the same time, leading to the technical problem of data signals being written to the wrong row.

[0134] An embodiment of the present disclosure provides a gate driving circuit, which may include a multi-stage shift register circuit and a multi-stage logic operation circuit respectively connected to the multi-stage shift register circuit, wherein the multi-stage shift register circuit is cascade-connected;

[0135] In the at least one stage of shift register circuit, each stage of the shift register circuit is configured to receive a first clock signal and output a first input signal to a corresponding logic operation circuit under the control of the first clock signal;

[0136] In at least one level of logic operation circuit, each level of logic operation circuit is configured to output a write switch signal under the control of a first input signal, and the write switch signal includes two valid signals, and the sum of the pulse widths of the two valid signals is less than or equal to the period of the first clock signal.

[0137] In the gate drive circuit provided by the embodiment of the present disclosure, in at least one level of shift register circuit, each level of shift register circuit is configured to receive a first clock signal and output a first input signal to the corresponding logic operation circuit under the control of the first clock signal; in at least one level of logic operation circuit, each level of logic operation circuit is configured to output a write switch signal under the control of the first input signal, and the write switch signal includes two valid signals, and the sum of the pulse widths of the two valid signals is less than or equal to the period of the first clock signal. This can avoid the situation where the pulse widths of the valid signals in the write switch signals of multiple rows output by the multiple levels of logic operation circuits at the same time overlap, and further avoid the phenomenon that the first transistors in the pixel drive circuits of multiple rows are turned on at the same time, and can overcome the technical problem of data signals being written to the wrong row due to the overlap of valid signals in the write switch signals of multiple rows at the same time.

[0138] As shown in FIG6a and FIG6c, a structural diagram of a gate driving circuit provided by an embodiment of the present disclosure is shown. The gate driving circuit may include a multi-stage shift register circuit 100 and a multi-stage logic operation circuit 200 respectively connected to the multi-stage shift register circuit 100. The multi-stage shift register circuit is cascade-connected.

[0139] In at least one stage of the shift register circuit 100 , each stage of the shift register circuit 100 may be configured to receive a first clock signal CKV1 and output a first input signal A_Qn_ to a corresponding logic operation circuit 200 under the control of the first clock signal CKV1 ;

[0140] In at least one level of logic operation circuit 200, each level of logic operation circuit 200 is configured to output a write switch signal WSn under the control of a first input signal A_Qn_, wherein the write switch signal WSn includes two valid signals, and the sum of the pulse widths of the two valid signals is less than or equal to the period T1 of the first clock signal CKV1.

[0141] As shown in FIG6 c , in the write switch signal WSn output by the n-th stage logic operation circuit 200 , the sum of the pulse width tw1 of the first valid signal and the pulse width tw2 of the second valid signal is less than or equal to the period T1 of the first clock signal CKV1 .

[0142] In an exemplary embodiment, as shown in FIG. 6 c , in one light emitting period, two valid signals written into the switching signal WSn may alternately drive the first transistor T1 in the pixel driving circuit.

[0143] In an exemplary embodiment, as shown in FIG6c , the valid signal in the write switch signal WSn may be a low level. The embodiments of the present disclosure are not limited thereto. The valid signal in the write switch signal WSn may be set based on the circuit structure of the pixel driving circuit. For example, the valid signal in the write switch signal WSn may be a high level.

[0144] In an exemplary embodiment, as shown in FIG6a , in at least one stage of the shift register circuit 100, each stage of the shift register circuit 100 may include a first signal input terminal IN_A_Dn, a first clock signal terminal IN_CKV1, and a first shift signal output terminal OUT_A_Qn_. The shift register circuit 100 is configured to receive a first signal A_Dn through the first signal input terminal IN_A_Dn and a first clock signal CKV1 through the first clock signal terminal IN_CKV1. Under the control of the first clock signal CKV1, the shift register circuit 100 shifts the first signal A_Dn to obtain a first input signal A_Qn_. The shift register circuit 100 provides the first input signal A_Qn_ to the corresponding logic operation circuit 200 through the first shift signal output terminal OUT_A_Qn.

[0145] The pulse width of the valid signal in the first input signal A_Qn can be S periods T1 of the first clock signal, where S is a positive integer. For example, as shown in FIG6b , S can be 3, that is, the pulse width of the valid signal in the first input signal A_Qn_ can be three periods T1 of the first clock signal.

[0146] In an exemplary embodiment, the shift register circuit 100 can be configured to control the pulse width of the valid signal in the first input signal A_Qn_ by adjusting the pulse width of the first signal A_Dn, thereby adjusting the pulse width of the valid signal in the first input signal A_Qn_. In an exemplary embodiment, the pulse width of the valid signal can be understood as the duration of the valid signal. In an exemplary embodiment, the valid signal in the first signal A_Dn can be a high-level signal, but the embodiments of the present disclosure are not limited thereto. For example, the valid signal in the first signal A_Dn can be a low-level signal, as long as the pulse width of the valid signal in the first input signal A_Qn_ can be controlled.

[0147] In an exemplary embodiment, as shown in FIG6b , the end time of the valid signal in the first input signal A_Qn_ output by the n-th stage shift register circuit 100 is synchronized with the start time of the valid signal in the first input signal A_Qn+S_ output by the n+S-th stage shift register circuit 100, where n is a positive integer and S is the number of periods T1 of the first clock signal included in the pulse width of the valid signal in the first input signal A_Qn.

[0148] In an exemplary embodiment, since the first input signal A_Qn+S_ output by the n+S-th stage shift register circuit 100 is obtained by shifting the first input signal A_Qn_ output by the n-th stage shift register circuit 100 through S-stage shift register circuits 100 (i.e., shifting through S shift register circuits 100), the start time of the valid signal in the first input signal A_Qn+S_ output by the n+S-th stage shift register circuit 100 may be delayed compared to the end time of the valid signal in the first input signal A_Qn_ output by the n-th stage shift register circuit 100. Therefore, the end time of the valid signal in the first input signal A_Qn_ output by the n+S-th stage shift register circuit 100 may be delayed compared to the end time of the valid signal in the first input signal A_Qn_ output by the n-th stage shift register circuit 100. The start time synchronization of the valid signal in the first input signal A_Qn+S_ output by the register circuit 100 can be that the end time of the valid signal in the first input signal A_Qn_ output by the n-th stage shift register circuit 100 is a certain time interval with the start time of the valid signal in the first input signal A_Qn+S_ output by the n+S-th stage shift register circuit 100. Since the time interval is small, it can be considered as synchronization. Under normal circumstances, the start time of the valid signal in the first input signal A_Qn+S_ output by the n+S-th stage shift register circuit 100 is slightly later than the end time of the valid signal in the first input signal A_Qn_ output by the n-th stage shift register circuit 100 (but the time interval is not large, which can be considered as synchronization). That is, "synchronization" in the embodiments of the present disclosure can be understood as two times completely coinciding, or two times having a certain time interval.

[0149] As shown in Figure 6b, the value of S can be 3, that is, the end time t4n of the valid signal in the first input signal A_Qn_ output by the n-th stage shift register circuit 100 is synchronized with the start time t2(n+3) of the valid signal in the first input signal A_Qn+3_ output by the n+3-th stage shift register circuit 100; the end time t4(n+1) of the valid signal in the first input signal A_Qn+1_ output by the n+1-th stage shift register circuit 100 is synchronized with the start time t2(n+4) of the valid signal in the first input signal A_Qn+4_ output by the n+4-th stage shift register circuit 100.

[0150] In an exemplary embodiment, at least one level of logic operation circuit 200 can be configured to generate a write switch signal WSn based on the first input signal A_Qn_, and output the write switch signal WSn to at least one pixel driving circuit, for example, output the write switch signal WSn to a row of pixel driving circuits. The first input signal A_Qn+1_ for generating the write switch signal WSn+1 of the n+1th row is obtained by shifting the first input signal A_Qn_ for generating the write switch signal WSn of the nth row. Therefore, the phase difference (i.e., the time difference of the valid signals) between the write switch signal WSn+1 of the n+1th row and the write switch signal WSn of the nth row is the time for displaying one row. Since the write switch signal WSn includes the pulse widths of two valid signals, during the shifting process, there may be an overlap of the valid signals in the write switch signals WS of the two rows, thereby causing the data signal to be written to the wrong row. In the embodiment of the present disclosure, the end time of the valid signal in the first input signal A_Qn_ output by the n-th stage shift register circuit 100 is designed to be synchronized with the start time of the valid signal in the first input signal A_Qn+S_ output by the n+S-th stage shift register circuit 100, thereby avoiding the phenomenon of the valid signals in the write switch signals WS of the two rows overlapping, thereby avoiding the technical problem of the data signal being written to the wrong row.

[0151] In an exemplary embodiment, the valid signal in the first input signal A_Qn_ can be a low-level signal. The embodiments of the present disclosure are not limited to this. The valid signal of the first input signal A_Qn_ can be set according to the working timing of the shift register circuit, the logic operation circuit and the gate drive circuit. For example, the valid signal in the first input signal can be a high level.

[0152] In an exemplary embodiment, as shown in FIG6 a and FIG6 b , in at least one stage of logic operation circuit 200, each stage of logic operation circuit 200 may include a first input terminal IN_A_Qn_ and a write switch signal terminal OUT_WSn, and is configured to receive a first input signal A_Dn through the first input terminal IN_A_Qn_, generate a write switch signal WSn under the control of the first input signal A_Dn, and output the write switch signal WSn through the write switch signal terminal OUT_WSn;

[0153] In at least one level of logic operation circuit 200, each level of logic operation circuit 200, under the control of the first input signal A_Qn_ received by the first input terminal IN_A_Qn_ of the current level, generates a write switch signal WSn whose start time t1 is synchronized with the start time t1 of the valid signal in the first input signal A_Qn_ received by the first input terminal IN_A_Qn_ of the current level; and generates a write switch signal WSn whose end time t4 is synchronized with the end time t4 of the valid signal in the first input signal A_Qn_ received by the first input terminal IN_A_Qn_ of the current level.

[0154] In an exemplary embodiment, as shown in FIG6a and FIG6c, in at least one stage of the shift register circuit 100, each stage of the shift register circuit 100 may further include a second signal input terminal IN_B_Dn, a second clock signal terminal IN_CKV2, and a second shift signal output terminal OUT_B_Qn, configured to receive the second signal B_Dn through the second signal input terminal IN_B_Dn and the second clock signal CKV2 through the second clock signal terminal IN_CKV2, shift the second signal B_Dn under the control of the second clock signal CKV2 to obtain a second input signal B_Qn, and provide the second input signal B_Qn to the corresponding logic operation circuit 200 through the second shift signal output terminal OUT_B_Qn; in at least one stage of the logic operation circuit 200, each stage of the logic operation circuit 200 may further include a second input terminal IN_B_Qn, configured to receive the second input signal B_Qn through the second input terminal IN_B_Qn, and generate a write switch signal WSn under the control of the first input signal A_Qn and the second input signal B_Qn;

[0155] In at least one level of logic operation circuit 200, under the control of the second input signal B_Qn received at the second input terminal IN_B_Qn of this level, the end time t2 of the first valid signal in the write switch signal WSn generated by each level of logic operation circuit 200 is synchronized with the start time t2 of the valid signal in the second input signal B_Qn received at the second input terminal IN_B_Qn of this level.

[0156] In an exemplary embodiment, as shown in FIG6c , the valid signal in the second input signal B_Qn may be a high level. The embodiments of the present disclosure are not limited thereto. The valid signal in the second input signal B_Qn may be set based on the circuit structure and working mode of the gate driving circuit. For example, the valid signal in the second input signal B_Qn may be a low level.

[0157] In an exemplary embodiment, as shown in FIG6c , in at least one stage of logic operation circuit 200, a start time t1 of a valid signal in the first input signal A_Qn received by the first input terminal IN_A_Qn of each stage of logic operation circuit 200 is earlier than a start time t2 of a valid signal in the second input signal B_Qn received by the second input terminal IN_B_Qn of the same stage.

[0158] In an exemplary embodiment, as shown in FIG6c , in at least one level of logic operation circuit 200, each level of logic operation circuit 200 is configured to control the pulse width tw1 of the first valid signal in the write switch signal WSn based on the difference between the start time t2 of the valid signal in the second input signal B_Qn and the start time t1 of the valid signal in the first input signal A_Qn (i.e., t2-t1). Thus, the pulse width tw1 of the first valid signal in the write switch signal WSn can be adjusted by adjusting the difference between the start time t1 of the valid signal in the first input signal A_Qn and the start time t2 of the valid signal in the second input signal B_Qn. This allows for flexible adjustment of the pulse width tw1 of the first valid signal in the write switch signal WSn. When tw1+tw2<T1, the valid signals in multiple rows of the write switch signals WSn output by the multi-level logic operation circuit 200 will not overlap at the same time, thereby avoiding the technical problem of data signals being written to the wrong row.

[0159] In an exemplary embodiment, the shift register circuit 100 can be configured to control the pulse width of the valid signal in the second input signal B_Qn by adjusting the pulse width of the valid signal in the second signal B_Dn. Thus, the pulse width of the valid signal in the second input signal B_Qn can be adjusted by adjusting the pulse width of the valid signal in the second signal B_Dn. In an exemplary embodiment, the valid signal in the second signal B_Dn can be a high-level signal, but the embodiments of the present disclosure are not limited thereto. For example, the valid signal in the second signal B_Dn can be a low-level signal, as long as the pulse width of the valid signal in the second input signal B_Qn can be controlled.

[0160] In an exemplary embodiment, as shown in FIG6a and FIG6c, in at least one stage of the shift register circuit 100, each stage of the shift register circuit 100 may further include a third signal input terminal IN_C_Dn, a third clock signal terminal IN_CKV3, and a third shift signal output terminal OUT_C_Qn, configured to receive the third signal C_Dn through the third signal receiving terminal IN_C_Dn and receive the third clock signal CKV3 through the third clock signal terminal IN_CKV3, and under the control of the third clock signal CKV3, the third signal C_Dn is shifted. Shifting is performed to obtain a third input signal C_Qn, and the third input signal C_Qn is provided to the corresponding logic operation circuit 200 through the third shifted signal output terminal OUT_C_Qn. In the at least one level of logic operation circuit 200, each level of logic operation circuit 200 may further include a third input terminal IN_C_Qn, configured to receive the third input signal C_Qn through the third input terminal IN_C_Qn, and generate a write switch signal WSn under the control of the first input signal A_Qn_, the second input signal B_Qn, and the third input signal C_Qn.

[0161] In at least one level of logic operation circuit 200, each level of logic operation circuit 200, under the control of the third input signal C_Qn received by the third input terminal IN_C_Qn of this level, generates a start time t3 of the second valid signal in the write switch signal WSn, which is synchronized with the end time of the valid signal in the third input signal C_Qn received by the third input terminal IN_C_Qn of this level.

[0162] In an exemplary embodiment, the “synchronization” mentioned in the embodiment of the present disclosure may mean that two times coincide with each other, or there may be a certain time interval.

[0163] In an exemplary embodiment, as shown in FIG6c , the valid signal in the third input signal C_Qn may be a high level. The embodiments of the present disclosure are not limited thereto. The valid signal in the third input signal C_Qn may be set based on the circuit structure and working mode of the gate driving circuit. For example, the valid signal in the third input signal C_Qn may be a low level.

[0164] In an exemplary embodiment, in at least one stage of logic operation circuit 200, the end time t4 of the valid signal in the first input signal A_Qn_ received by the first input terminal IN_A_Qn_ of each stage of logic operation circuit 200 is later than the end time t3 of the valid signal in the third input signal C_Qn received by the third receiving terminal IN_C_Qn of this stage.

[0165] In an exemplary embodiment, in at least one level of logic operation circuit 200, each level of logic operation circuit 200 is configured to control the pulse width tw2 of the second valid signal in the write switch signal WSn based on the difference between the end time t4 of the valid signal in the first input signal A_Qn_ and the end time t3 of the valid signal in the third input signal C_Qn (i.e., t4-t3). Thus, the pulse width tw2 of the second valid signal in the write switch signal WSn can be adjusted by adjusting the difference between the end time t4 of the valid signal in the first input signal A_Qn_ and the end time t3 of the valid signal in the third input signal C_Qn. This allows for flexible adjustment of the pulse width tw2 of the second valid signal in the write switch signal WSn. When tw1+tw2<T1, valid signals in multiple rows of write switch signals WSn output by the multi-level logic operation circuit 200 will not overlap at the same time, thereby preventing the technical problem of data signals being written to the wrong row.

[0166] In an exemplary embodiment, the pulse width tw1 of the first valid signal in the write switch signal WSn can be adjusted by adjusting the difference between the start time t1 of the valid signal in the first input A_Qn_ and the start time t2 of the valid signal in the second input signal B_Qn, and the pulse width tw2 of the second valid signal in the write switch signal WSn can be adjusted by adjusting the difference between the end time t4 of the valid signal in the first input A_Qn_ and the end time t3 of the valid signal in the third input signal C_Qn. In this way, the pulse width tw1 of the first valid signal and the pulse width tw2 of the second valid signal in the write switch signal WSn can be flexibly adjusted. When tw1+tw2<T1, the valid signals in the multiple rows of write switch signals WSn output by the multi-stage logic operation circuit 200 will not overlap at the same time, thereby avoiding the technical problem of data signals being written to the wrong row.

[0167] In an exemplary embodiment, the shift register circuit 100 can be configured to control the pulse width of the valid signal in the third input signal C_Qn by adjusting the pulse width of the valid signal in the third signal C_Dn. Thus, the pulse width of the valid signal in the third input signal C_Qn can be adjusted by adjusting the pulse width of the valid signal in the third signal C_Dn. In an exemplary embodiment, the valid signal in the third signal C_Dn can be a high-level signal, but the present disclosure is not limited thereto. For example, the valid signal in the third signal C_Dn can be a low-level signal, as long as the pulse width of the valid signal in the third input signal C_Qn_ can be controlled.

[0168] The technical solution of the gate driving circuit disclosed in the present invention is described below through exemplary embodiments.

[0169] As shown in FIG6d, it is a structural diagram of a multi-stage cascade gate drive circuit. Each gate drive circuit may include two parts: a logic control circuit 10 and a target signal generating circuit 20. The logic control circuit 10 may include a logic control unit (for example, it may include at least one of a transmission gate, a logic control transistor, a NAND gate, and an inverter), which is mainly used for addressing, forward and reverse scanning control, etc. (10-3 is a reset control subcircuit, which is configured to reset the row drive enhancer 400). Among them, Z0 to Zn+1 and Z0_ to Zn+1_ are scan start row control signal terminals, IN_S TV is the input terminal for the start signal STV (set to input the first signal A_D1, the second signal B_D1, and the third signal C_D1), the signals input by the first forward and reverse scan control terminal GSD_FW and the second forward and reverse scan control terminal GSD_BW are mutually inverse signals (for example, the signals input by the first forward and reverse scan control terminal GSD_FW and the second forward and reverse scan control terminal GSD_BW are one high level 1 and the other low level 0), T0 to Tn+1 are reset signal control terminals; the target signal generation circuit 20 may include a shift register circuit 100, a logical operation circuit (Logical Transition Unit) 200, a level conversion circuit (Level shifter) 300 and a line driver enhancement circuit (Line Driver) 400, mainly used to generate the line drive timing signal as shown in Figure 5a or Figure 5b. In an exemplary embodiment, the gate drive circuit can be arranged in the non-display area of ​​the display substrate, can be located on one side of the pixel row direction of the display area in the display substrate, or can be located on both sides of the pixel row direction of the display area in the display substrate. The gate drive device may include multiple cascaded gate drive circuits, at least one of which is connected to a scan signal line in a pixel row in the display area, providing a scan signal to the connected scan signal line. When the gate drive device is positioned on both sides of the pixel row in the display area, the scan signal lines in the pixel row are driven by two gate drive circuits, forming a bilateral drive structure. This ensures high pixel density drive capability and prevents drive signal distortion.

[0170] Figure 6e is a schematic diagram of the structure of a target signal generating circuit 20 in a gate driver circuit according to an exemplary embodiment of the present disclosure. As shown in Figure 6e, the target signal generating circuit in the gate driver circuit may include a shift register circuit 100, a logical operation circuit (Logical Transition Unit) 200, a level shifter circuit (Level Shifter) 300, and a line driver enhancement circuit (Line Driver) 400.

[0171] In an exemplary embodiment, the shift register circuit 100 may be a shift register circuit composed of a D flip-flop (D Flip Flop, abbreviated as DFF). The shift register circuit 100 is connected to the display driver circuit and receives a timing signal generated by the display driver circuit. The timing signal may include a start signal STV and a clock signal CKV. The D flip-flop is configured to shift and register the received timing signal to initially generate a timing sequence that can be shifted row by row. The logic operation circuit 200 is connected to the shift register circuit 100 and is configured to perform a logic operation on the shifted signal to generate a plurality of target timing sequences with different waveforms. The level conversion circuit 300 is connected to the logic operation circuit 200 and is configured to perform voltage domain conversion on the target timing sequence. The row drive enhancement circuit 400 is connected to the level conversion circuit 300 and is configured to enhance the converted signal, thereby enhancing the output capability and outputting the scan signal to the display area.

[0172] In an exemplary embodiment, the pixel driving circuit in the display area includes a first scan signal line S1, a second scan signal line S2, and a third scan signal line S3. The level conversion circuit 300 and the row drive enhancement circuit 400 constitute an output circuit. The output circuit may include three output sub-circuits. Each sub-output circuit may include a level converter and a row drive enhancer. One output sub-circuit is connected to the first scan signal line S1 of a pixel row in the display area and is configured to output a first scan signal to the display area. Another output sub-circuit is connected to the second scan signal line S2 of a pixel row in the display area and is configured to output a second scan signal to the display area. Still another output sub-circuit is connected to the third scan signal line S3 of a pixel row in the display area and is configured to output a third scan signal to the display area.

[0173] In an exemplary embodiment, the first scan signal may be referred to as a write switch (WS) signal, configured to control the on / off switching of a first transistor T1 in a pixel driving circuit. The second scan signal may be referred to as a display switch (DS) signal, configured to control the on / off switching of a second transistor T2 in the pixel driving circuit. The third scan signal may be referred to as a display reset signal (Auto Zero, AZ) signal, configured to control the on / off switching of a fourth transistor T4 in the pixel driving circuit.

[0174] In an exemplary embodiment, since signals such as the start signal and the clock signal are output by the display driver circuit, their voltage domains are inconsistent with the voltage domain of the pixel driver circuit. By converting the level converter in the level conversion circuit 300, the required voltage (0V to -2V & -5V) is introduced, thereby ensuring that the voltage of the output gate drive signal matches that of the pixel driver circuit.

[0175] In an exemplary embodiment, the start signal STV may be referred to as a frame start signal, with a period of one frame, and the clock signal CKV may be referred to as a row driving clock signal, with a period of one row.

[0176] In an exemplary embodiment, the logic operation circuit 200 may include at least a first operation circuit, a second operation circuit, and a third operation circuit, the first operation circuit being configured to generate a write switch signal WS, the second operation circuit being configured to generate a display switch signal DS, and the third operation circuit being configured to generate a display reset signal AZ.

[0177] FIG7 is a diagram illustrating the working principle of a first arithmetic circuit according to an exemplary embodiment of the present disclosure. The first arithmetic circuit may include nine components, namely four inverters (INVX), three NOR gates (NOR), one NAND gate (NAND), and one two-way selector (MUX2). As shown in FIG7 , the first arithmetic circuit may include a first NAND gate 301, a first inverter 401, a second inverter 402, a third inverter 403, a fourth inverter 404, a first NOR gate 501, a second NOR gate 502, a third NOR gate 503, and a two-way selector 510.

[0178] In an exemplary embodiment, a first input terminal of the first NAND gate 301 is connected to the second input terminal B_Qn of the logic operation circuit, a second input terminal of the first NAND gate 30 is connected to the third input terminal C_Qn of the logic operation circuit, an output terminal of the first NAND gate 301 is connected to the input terminal of the first inverter 401, an output terminal of the first inverter 401 is connected to the first input terminal of the first NOR gate 501, a second input terminal of the first NOR gate 501 is connected to the first input terminal IN_A_Qn_ of the logic operation circuit, an output terminal of the first NOR gate 501 is connected to the input terminal of the second inverter 402, an output terminal of the second inverter 402 is connected to the first input terminal of the second NOR gate 502, a second input terminal of the second NOR gate 502 is connected to the clock signal terminal CKV4 of the logic operation circuit, an output terminal of the second NOR gate 502 is connected to the input terminal of the fourth inverter 404, and an output terminal of the fourth inverter 404 is connected to the second input terminal of the two-way selector 510. The input of the third inverter 403 is connected to the second reset terminal IN_LF_pulse2 of the logic operation circuit. The output of the third inverter 403 is connected to the second input terminal of the third NOR gate 503. The first input of the third NOR gate 503 is connected to the first reset terminal IN_LF_pulse1 of the logic operation circuit. The output of the third NOR gate 503 is connected to the control terminal of the two-way selector 510. The first input of the two-way selector 510 is connected to the input terminal IN_A_Qn of the inverted first input signal of the logic operation circuit. The output of the two-way selector 510 serves as the output terminal of the first operation circuit (which can serve as the write switch signal terminal WSn of the logic operation circuit) and is connected to the input terminal of a level shifter (e.g., the first level shifter) to output the write switch signal WSn to the level shifter.

[0179] In an exemplary embodiment, the first operation circuit operates as follows: the first NAND gate 301 and the first inverter 401 perform an AND operation on the second input signal B_Qn at the second input terminal IN_B_Qn and the third input signal C_Qn at the third input terminal IN_C_Qn. The first NOR gate 501 and the second inverter 402 perform an OR operation on the AND operation result and the first input signal A_Qn_ at the first input terminal IN_A_Qn_. The second NOR gate 502 and the fourth inverter 404 perform an OR operation on the OR operation result and the fourth clock signal CKV4 at the fourth clock signal terminal IN_CKV4, i.e., F1 = B_Qn & C_Qn + A_Qn_ + CKV4. The third inverter 403 inverts the second reset signal at the second reset terminal LF_pulse2. The third NOR gate 503 performs a NOR operation on the inverted result and the first reset signal at the first reset terminal LF_pulse1, i.e., F2 serves as a control signal of the two-way selector 510. When F2=1, the output end of the two-way selector 510 outputs A_Qn (ie, the inverted signal of the first input signal A_Qn_); when F2=0, the output end of the two-way selector 510 outputs F1.

[0180] FIG8 is an equivalent circuit diagram of a first operation circuit of an exemplary embodiment of the present disclosure. As shown in FIG8 , in the gate drive circuit of the embodiment of the present disclosure, the first operation circuit of the logic operation circuit may include 30 transistors. Among them, the first inverter 401, the second inverter 402, the third inverter 403, and the fourth inverter 404 each include 1 P-type transistor and 1 N-type transistor, the first NAND gate 301, the first NOR gate 501, the second NOR gate 502, and the third NOR gate 503 each include 2 P-type transistors and 2 N-type transistors, and the two-way selector 510 includes 3 P-type transistors and 3 N-type transistors.

[0181] In an exemplary embodiment, the first NAND gate 301, the first inverter 401, the first NOR gate 501, the second inverter 402, the second NOR gate 502, the fourth inverter 404, the third inverter 403, the third NOR gate 503 and the two-way selector 510 can be arranged in sequence along the first direction X (the direction close to the display area).

[0182] In an exemplary embodiment, a first P-type transistor P1, a first N-type transistor N1, a second P-type transistor P2, and a second N-type transistor N2 form a first NAND gate 301. The gate electrode of the first P-type transistor P1 and the gate electrode of the first N-type transistor N1 are connected to each other and to the third input terminal IN_C_Qn of the logic operation circuit. The gate electrode of the second P-type transistor P2 and the gate electrode of the second N-type transistor N2 are connected to each other and to the second input terminal IN_B_Qn of the logic operation circuit. The first electrode of the first P-type transistor P1 and the first electrode of the second P-type transistor P2 are both connected to the first power supply line VDD. The second electrode of the first P-type transistor P1 and the second electrode of the second P-type transistor P2 are connected to each other and to the second electrode of the second N-type transistor N2, the gate electrode of the third P-type transistor P3, and the gate electrode of the third N-type transistor N3, respectively. The first electrode of the first N-type transistor N1 is connected to the ground line GND, and the second electrode of the first N-type transistor N1 is connected to the first electrode of the second N-type transistor N2.

[0183] In an exemplary embodiment, a third P-type transistor P3 and a third N-type transistor N3 form a first inverter 401. A gate electrode of the third P-type transistor P3 and a gate electrode of the third N-type transistor N3 are connected to each other and are connected to the second electrode of the first P-type transistor P1, the second electrode of the second P-type transistor P2, and the second electrode of the second N-type transistor N2, respectively. A first electrode of the third P-type transistor P3 is connected to a first power supply line VDD, a first electrode of the third N-type transistor N3 is connected to a ground line GND, and a second electrode of the third P-type transistor P3 and a second electrode of the third N-type transistor N3 are connected to each other and are connected to the gate electrode of the fifth P-type transistor P5 and the gate electrode of the fifth N-type transistor N5, respectively.

[0184] In an exemplary embodiment, a fourth P-type transistor P4, a fourth N-type transistor N4, a fifth P-type transistor P5, and a fifth N-type transistor N5 form a first NOR gate 501. The gate electrode of the fourth P-type transistor P4 and the gate electrode of the fourth N-type transistor N4 are connected to each other and to the first input terminal IN_A_Qn of the logic operation circuit. The gate electrode of the fifth P-type transistor P5 and the gate electrode of the fifth N-type transistor N5 are connected to each other and to the second electrode of the third P-type transistor P3 and the second electrode of the third N-type transistor N3, respectively. A first electrode of the fourth P-type transistor P4 is connected to the first power supply line VDD. A second electrode of the fourth P-type transistor P4 is connected to the first electrode of the fifth P-type transistor P5. A first electrode of the fourth N-type transistor N4 and a first electrode of the fifth N-type transistor N5 are both connected to the ground line GND. A second electrode of the fourth N-type transistor N4 and a second electrode of the fifth N-type transistor N5 are connected to each other and to the second electrode of the fifth P-type transistor P5, the gate electrode of the sixth P-type transistor P6, and the gate electrode of the sixth N-type transistor N6, respectively.

[0185] In an exemplary embodiment, a sixth P-type transistor P6 and a sixth N-type transistor N6 form a second inverter 402. A gate electrode of the sixth P-type transistor P6 and a gate electrode of the sixth N-type transistor N6 are connected to each other and are respectively connected to the second electrode of the fifth P-type transistor P5, the second electrode of the fourth N-type transistor N4, and the second electrode of the fifth N-type transistor N5. A first electrode of the sixth P-type transistor P6 is connected to the first power supply line VDD, a first electrode of the sixth N-type transistor N6 is connected to the ground line GND, and a second electrode of the sixth P-type transistor P6 and a second electrode of the sixth N-type transistor N6 are connected to each other and are respectively connected to the gate electrode of the eighth P-type transistor P8 and the gate electrode of the eighth N-type transistor N8.

[0186] In an exemplary embodiment, a seventh P-type transistor P7, a seventh N-type transistor N7, an eighth P-type transistor P8, and an eighth N-type transistor N8 form a second NOR gate 502. The gate electrode of the seventh P-type transistor P7 and the gate electrode of the seventh N-type transistor N7 are connected to each other and to the clock signal terminal CKV4 of the logic operation circuit. The gate electrode of the eighth P-type transistor P8 and the gate electrode of the eighth N-type transistor N8 are connected to each other and to the second electrode of the sixth P-type transistor P6 and the second electrode of the sixth N-type transistor N6, respectively. A first electrode of the seventh P-type transistor P7 is connected to the first power supply line VDD. A second electrode of the seventh P-type transistor P7 is connected to the first electrode of the eighth P-type transistor P8. A first electrode of the seventh N-type transistor N7 and a first electrode of the eighth N-type transistor N8 are both connected to the ground line GND. A second electrode of the seventh N-type transistor N7 and a second electrode of the eighth N-type transistor N8 are connected to each other and to the second electrode of the eighth P-type transistor P8, the gate electrode of the ninth P-type transistor P9, and the gate electrode of the ninth N-type transistor N9, respectively.

[0187] In an exemplary embodiment, a ninth P-type transistor P9 and a ninth N-type transistor N9 form a fourth inverter 404. The gate electrode of the ninth P-type transistor P9 and the gate electrode of the ninth N-type transistor N9 are connected to each other and are connected to the second electrode of the seventh N-type transistor N7, the second electrode of the eighth N-type transistor N8, and the second electrode of the eighth P-type transistor P8, respectively. A first electrode of the ninth P-type transistor P9 is connected to the first power supply line VDD, a first electrode of the ninth N-type transistor N9 is connected to the ground line GND, and a second electrode of the ninth P-type transistor P9 and the second electrode of the ninth N-type transistor N9 are connected to each other and are connected to the first electrode of the fifteenth P-type transistor P15 and the first electrode of the fifteenth N-type transistor N15, respectively.

[0188] In an exemplary embodiment, the tenth P-type transistor P10 and the tenth N-type transistor N10 form a third inverter 403. The gate electrode of the tenth P-type transistor P10 and the gate electrode of the tenth N-type transistor N10 are connected to each other and to the second reset terminal IN_LF_pulse2 of the logic operation circuit. The first electrode of the tenth P-type transistor P10 is connected to the first power supply line VDD, the first electrode of the tenth N-type transistor N10 is connected to the ground line GND, and the second electrode of the tenth P-type transistor P10 and the second electrode of the tenth N-type transistor N10 are connected to each other and to the gate electrode of the eleventh P-type transistor P11 and the gate electrode of the eleventh N-type transistor N11, respectively.

[0189] In the exemplary embodiment, the eleventh P-type transistor P11, the eleventh N-type transistor N11, the twelfth P-type transistor P12, and the twelfth N-type transistor N12 constitute a third NOR gate 503. The gate electrode of the eleventh P-type transistor P11 and the gate electrode of the eleventh N-type transistor N11 are connected to each other and to the second electrode of the tenth P-type transistor P10 and the second electrode of the tenth N-type transistor N10, respectively. The gate electrode of the twelfth P-type transistor P12 and the gate electrode of the twelfth N-type transistor N12 are connected to each other and to the first reset terminal IN_LF_pulse1 of the logic operation circuit. The first electrode of the N-type transistor P11 is connected to the first power supply line VDD, the second electrode of the eleventh P-type transistor P11 is connected to the first electrode of the twelfth P-type transistor P12, the first electrode of the eleventh N-type transistor N11 and the first electrode of the twelfth N-type transistor N12 are both connected to the ground line GND, the second electrode of the eleventh N-type transistor N11 and the second electrode of the twelfth N-type transistor N12 are connected to each other, and are respectively connected to the second electrode of the twelfth P-type transistor P12, the gate electrode of the thirteenth P-type transistor P13, the gate electrode of the thirteenth N-type transistor N13, the gate electrode of the fourteenth N-type transistor N14 and the gate electrode of the fifteenth P-type transistor P15.

[0190] In an exemplary embodiment, the thirteenth P-type transistor P13, the thirteenth N-type transistor N13, the fourteenth P-type transistor P14, the fourteenth N-type transistor N14, the fifteenth P-type transistor P15, and the fifteenth N-type transistor N15 constitute a two-way selector 510. The gate electrode of the thirteenth P-type transistor P13 and the gate electrode of the thirteenth N-type transistor N13 are connected to each other, and are respectively connected to the second electrode of the eleventh N-type transistor N11, the second electrode of the twelfth N-type transistor N12, the second electrode of the twelfth P-type transistor P12, the gate electrode of the fourteenth N-type transistor N14, and the gate electrode of the fifteenth P-type transistor P15. A first electrode of the thirteenth P-type transistor P13 is connected to the first power supply line VDD, a first electrode of the thirteenth N-type transistor N13 is connected to the ground line GND, a second electrode of the thirteenth P-type transistor P13 and the second electrode of the thirteenth N-type transistor N13 are connected to each other, and are respectively connected to the gate electrode of the fourteenth P-type transistor P14 and the gate electrode of the fifteenth N-type transistor N15. The first electrode of the fourth N-type transistor N14 is connected to the first electrode of the fourth N-type transistor N14, and is connected to the first input terminal A_Qn of the logic operation circuit. The first electrode of the fifteenth P-type transistor P15 and the first electrode of the fifteenth N-type transistor N15 are connected to each other, and are respectively connected to the second electrode of the ninth P-type transistor P9 and the second electrode of the ninth N-type transistor N9. The second electrode of the fourteenth P-type transistor P14, the second electrode of the fourteenth N-type transistor N14, the second electrode of the fifteenth P-type transistor P15, and the second electrode of the fifteenth P-type transistor P15 are connected to each other and serve as the output terminal OUT_WS of the first operation circuit (that is, the output terminal of the output write switch signal OUT_WSn in Figure 7, which can be used as the write switch signal terminal OUT_WSn of the logic operation circuit).

[0191] Figure 9a is a schematic diagram of the working principle of a second arithmetic circuit according to an exemplary embodiment of the present disclosure. The second arithmetic circuit may include nine parts, namely six inverters, one NOR gate, one NAND gate, and one latch (D-Latch). As shown in Figure 9, the second arithmetic circuit may include a second NAND gate 302, a fifth inverter 405, a sixth inverter 406, a seventh inverter 407, an eighth inverter 408, a ninth inverter 409, a tenth inverter 410, a fourth NOR gate 504, and a latch 520.

[0192] In an exemplary embodiment, an input terminal of the fifth inverter 405 is connected to a write switch signal terminal WSn of the logic operation circuit, an output terminal of the fifth inverter 405 is connected to an input terminal of the sixth inverter 406, an output terminal of the sixth inverter 406 is connected to an input terminal of the seventh inverter 407, an output terminal of the seventh inverter 407 is connected to an input terminal of the eighth inverter 408, an output terminal of the eighth inverter 408 is connected to an input terminal of the ninth inverter 409, an output terminal of the ninth inverter 409 is connected to an input terminal of the tenth inverter 410, an output terminal of the tenth inverter 410 is connected to an enable signal terminal EN of a latch 520, and an input terminal of the latch 520 is connected to a second input terminal IN_B_Q of the logic operation circuit. n, the output of the latch 520 is connected to the second input of the fourth NOR gate 504, the first input of the fourth NOR gate 504 is connected to the duty control terminal IN_D_Qn of the logic operation circuit, the output of the fourth NOR gate 504 is connected to the first input of the second NAND gate 302, the second input of the second NAND gate 302 is connected to the second reset terminal LF_pulse2 of the logic operation circuit, and the output of the second NAND gate 302 serves as the output terminal OUT_DS of the second operation circuit and the display switch signal terminal OUT_DSn, and is connected to the display switch control terminal DS of the at least one pixel driving circuit, outputting the display switch signal to the display switch control terminal DS of the at least one pixel driving circuit. In an exemplary embodiment, the output of the second NAND gate 302 can be connected to the input of another level shifter (e.g., a second level shifter), outputting the display switch signal DSn to the level shifter. The level shifter performs level shifting on the display switch signal DSn and outputs it to the corresponding row driver booster (e.g., the second row driver booster). After the row driver booster performs signal amplification, the signal is output to the display switch control terminal of the corresponding pixel driving circuit.

[0193] In an exemplary embodiment, the operating principle of the second operation circuit is as follows: the fifth inverter 405 to the tenth inverter 410 delay the signal written to the switch signal terminal OUT_WSn and then input it to the enable signal terminal EN of the latch 520, which serves as the enable signal of the latch 520. The second input signal of the second input terminal B_Qn of the logic operation circuit serves as the input signal of the latch 520. When the enable signal at the enable signal terminal EN is low, the output of the latch 520 remains unchanged. When the enable signal at the enable signal terminal EN is high, the output of the latch 520 changes with the second input signal. Subsequently, the fourth NOR gate 504 performs a NOR operation on the duty control signal D_Qn at the duty control terminal IN_D_Qn and the signal at the first output terminal OUT_Q of the latch 520. The second NAND gate 302 performs a NAND operation on the NOR operation result and the second reset signal at the second reset terminal LF_pulse2. The logical expression is: Where Q is the output signal of latch 520 (when the enable signal EN input to the enable signal terminal of latch 520 is high, Q = B_Qn; when the enable signal EN input to the enable signal terminal of latch 520 is low, the signal output from output terminal Q remains the original output signal; under normal operation, the enable signal EN input to the enable signal terminal of latch 520 is high, Q = B_Qn). LF_pulse2 is the reset signal. Under normal operation, LF_pulse2 = 1, and DSn = D_Qn + Q. When a global reset is required, LF_pulse2 = 0, and the output signal DSn of the second arithmetic circuit is high (i.e., DSn = 1). D_Qn is the emission duty control signal. When the emission duty is 100%, D_Qn remains low, and DSn = Q. To adjust the emission duty, the duty cycle of D_Qn can be adjusted.

[0194] As shown in FIG9b, a working principle diagram of a latch 520 according to an exemplary embodiment of the present disclosure is shown. The latch 520 includes one inverter and four NAND gates. As shown in FIG9b, the latch 520 includes a twenty-first NAND gate 521, a twenty-second NAND gate 522, a twenty-third NAND gate 523, a twenty-fourth NAND gate 524, and a twenty-fifth inverter 525. The first input terminal of the twenty-first NAND gate 521 is connected to the second input terminal B_Qn of the logic operation circuit, the second input terminal of the twenty-first NAND gate 521 is connected to the enable signal terminal EN, the output terminal of the twenty-first NAND gate 521 is connected to the first input terminal of the twenty-second NAND gate 522, and the second input terminal of the twenty-second NAND gate 522 is connected to the second input terminal of the latch 520. The output terminal OUT_Q_ is connected, and the output terminal of the twenty-second NAND gate 522 serves as the first output terminal Q of the latch 520; the input terminal of the twenty-fifth inverter 525 is connected to the second input terminal IN_B_Qn of the logic operation circuit, the output terminal of the twenty-fifth inverter 525 is connected to the first input terminal of the twenty-third NAND gate 523, the second input terminal of the twenty-third NAND gate 523 is connected to the enable signal terminal EN, the output terminal of the twenty-third NAND gate 523 is connected to the second input terminal of the twenty-fourth NAND gate 524, the first input terminal of the twenty-fourth NAND gate 524 is connected to the first output terminal OUT_Q of the latch 520, and the output terminal of the twenty-fourth NAND gate 524 serves as the second output terminal OUT_Q_ of the latch 520. As shown in Figure 9c, it is a working timing diagram of the latch provided in an embodiment of the present disclosure (the horizontal axis in Figure 9c is time, the unit is microseconds; the vertical axis is voltage, the unit is volt V); in Figure 9b, the signal of the first node B1 is the result of the NAND operation obtained by performing a NAND operation on the second input signal B_Qn and the enable signal EN, the signal of the second node B2 is the result of the NAND operation obtained by performing a NAND operation on the second input signal B_Qn after being inverted by the inverter and the enable signal EN, the output signal Q is the result of the NAND operation obtained by performing a NAND operation on the signal of the first node B1 and the signal of the output terminal OUT_Q_, and the output signal Q_ is the result of the NAND operation obtained by performing a NAND operation on the signal of the second node B2 and the signal of the output terminal Q.

[0195] As shown in FIG9c , in the first stage t1, the enable signal EN is a high-level signal, the second input signal B_Qn is a low-level signal, the signal of the first node B1 obtained by performing a NAND operation on the enable signal EN and the second input signal B_Qn is a high-level signal, the signal of the second node B2 obtained by performing a NAND operation on the second input signal B_Qn after inversion operation and the enable signal EN is a low-level signal, the signal of the second node B2 obtained by performing a NAND operation on the signal of the first output terminal OUT_Q and the second output terminal OUT_Q is a high-level signal, and since the signals of the first node B1 and the second output terminal OUT_Q_ are both high-level, the signal of the first node B1 obtained by performing a NAND operation on the signal of the second output terminal OUT_Q_ and the signal of the first output terminal OUT_Q_ is a low-level signal; in the second stage t2, the enable signal EN is a high-level signal, and the signal of the second node B2 is a low-level signal. The signal EN is a low-level signal, and the second input signal B_Qn changes from a low-level signal to a high-level signal. Since the enable signal EN is a low-level signal, the first node B1 and the second node B2 are both high-level signals, the first output terminal OUT_Q maintains the low level of the previous stage, and the second output terminal OUT_Q_ maintains the high-level signal of the previous stage; in the third stage t3, the enable signal EN and the second input signal B_Qn are both high-level signals, the first node B1 obtained by performing a NAND operation on the enable signal EN and the second input signal B_Qn is a low-level signal, the first output terminal OUT_Q is a high-level signal after the signal of the first node B1 and the signal of the second output terminal OUT_Q_ are performed a NAND operation, and the second node B2 obtained by performing a NAND operation on the second input signal B_Qn after the inversion operation is performed on the enable signal EN The timing of the fourth stage t4 and the sixth stage t6 is the same as that of the second stage t2, the timing of the fifth stage t5 and the seventh stage t7 is the same as that of the third stage t3, and the timing of the eighth stage t8 and the tenth stage t10 is the same as that of the first stage t1; in the ninth stage t9 and the eleventh stage t11, the second input signal B_Qn changes from a high level to a low level signal, and the timing of other signals is the same as that of the second stage t2.

[0196] As can be seen from FIG9b and FIG9c, the latch 520 has the following three states in total. The first state: the enable signal EN is at a high level (1), the second input signal B_Qn is a low level signal (0), the signal of the first node B1 is at a high level, the signal of the second node B2 is at a low level, the signal of the second output terminal Q_ is a high level signal, and the signal of the first output terminal OUT_Q is a low level signal (called a latch set 0 operation); the second state: the enable signal EN is at a low level (0), the second input signal B_Qn is any signal (high level or low level), the first node B 1 and the signals of the second node B2 are both high level, the second output terminal OUT_Q_ and the first output terminal Q maintain the original output signal and do not change with the change of the second input signal B_Qn (called the holding stage, the stage of latching 1-bit binary number); the third state: the enable signal EN is high level (1), the second input signal B_Qn is a high level signal (1), the signal of the first node B1 is low level, the signal of the second node B2 is high level, the signal of the first output terminal Q is a high level signal (latch set 1 stage), and the signal of the second output terminal OUT_Q_ is a low level signal.

[0197] The D latch 520 in FIG9a primarily functions to prevent the high level of the display switch signal DSn from enclosing the first low level of the write switch signal WSn (i.e., the first low level of the write switch signal WSn at least partially overlaps with the high level of the display switch signal DSn). If the high level of the display switch signal DSn shifts forward to enclose the first low level of the write switch signal WSn, the time for writing the first power supply voltage at the second node N2 of the pixel driver circuit and the time for writing the bias voltage Vofs at the first node N1 of the pixel driver circuit will be shortened, resulting in incomplete initialization. If the first low level of the write switch signal WSn shifts backward to enclose the high level of the display switch signal DSn, the self-discharge time of the pixel driver circuit will be shortened, resulting in inaccurate threshold voltage readings. The D latch 520 operates normally only when the enable signal EN input to the enable signal terminal EN of the latch 520 is at a high level (i.e., EN=1). If the enable signal at the enable signal terminal EN is not at a high level (e.g., EN=0), the latch state is indeterminate, and the signal output from the first output terminal Q of the latch 520 is indeterminate.

[0198] FIG10 is an equivalent circuit diagram of a second operation circuit of an exemplary embodiment of the present disclosure. As shown in FIG10 , in the gate drive circuit of the embodiment of the present disclosure, the second operation circuit of the logic operation circuit may include 38 transistors. Among them, the second NAND gate 302 includes 2 P-type transistors and 2 N-type transistors, the fifth inverter 405, the sixth inverter 406, the seventh inverter 407, the eighth inverter 408, the ninth inverter 409, and the tenth inverter 410 each include 1 P-type transistor and 1 N-type transistor, the fourth NOR gate 504 includes 2 P-type transistors and 2 N-type transistors, and the latch 520 includes 9 P-type transistors and 9 N-type transistors.

[0199] In an exemplary embodiment, the fifth inverter 405, the sixth inverter 406, the seventh inverter 407, the eighth inverter 408, the ninth inverter 409, the tenth inverter 410, the latch 520, the fourth NOR gate 504 and the second NAND gate 302 can be arranged in sequence along the first direction X (the direction close to the display area in the display substrate).

[0200] In the exemplary embodiment, the twenty-first P-type transistor P21 and the twenty-first N-type transistor N21 constitute a fifth inverter 405. The gate electrode of the twenty-first P-type transistor P21 and the gate electrode of the twenty-first N-type transistor N21 are connected to each other and to the write switch signal terminal OUT_WSn of the logic operation circuit. A first electrode of the twenty-first P-type transistor P21 is connected to the first power supply line VDD, a first electrode of the twenty-first N-type transistor N21 is connected to the ground line GND, and a second electrode of the twenty-first P-type transistor P21 and the second electrode of the twenty-first N-type transistor N21 are connected to each other and to the gate electrode of the twenty-second P-type transistor P22 and the gate electrode of the twenty-second N-type transistor N22, respectively.

[0201] In the exemplary embodiment, the twenty-second P-type transistor P22 and the twenty-second N-type transistor N22 constitute the sixth inverter 406. The gate electrode of the twenty-second P-type transistor P22 and the gate electrode of the twenty-second N-type transistor N22 are connected to each other and to the second electrode of the twenty-first P-type transistor P21 and the second electrode of the twenty-first N-type transistor N21, respectively. The first electrode of the twenty-second P-type transistor P22 is connected to the first power supply line VDD, the first electrode of the twenty-second N-type transistor N22 is connected to the ground line GND, the second electrode of the twenty-second P-type transistor P22 and the second electrode of the twenty-second N-type transistor N22 are connected to each other and to the gate electrode of the twenty-third P-type transistor P23 and the gate electrode of the twenty-third N-type transistor N23, respectively.

[0202] In the exemplary embodiment, the twenty-third P-type transistor P23 and the twenty-third N-type transistor N23 constitute the seventh inverter 407. The gate electrode of the twenty-third P-type transistor P23 and the gate electrode of the twenty-third N-type transistor N23 are connected to each other and to the second electrode of the twenty-second P-type transistor P22 and the second electrode of the twenty-second N-type transistor N22, respectively. A first electrode of the twenty-third P-type transistor P23 is connected to the first power supply line VDD, a first electrode of the twenty-third N-type transistor N23 is connected to the ground line GND, and a second electrode of the twenty-third P-type transistor P23 and the second electrode of the twenty-third N-type transistor N23 are connected to each other and to the gate electrode of the twenty-fourth P-type transistor P24 and the gate electrode of the twenty-fourth N-type transistor N24, respectively.

[0203] In the exemplary embodiment, the twenty-fourth P-type transistor P24 and the twenty-fourth N-type transistor N24 constitute the eighth inverter 408. The gate electrode of the twenty-fourth P-type transistor P24 and the gate electrode of the twenty-fourth N-type transistor N24 are connected to each other and to the second electrode of the twenty-third P-type transistor P23 and the second electrode of the twenty-third N-type transistor N23, respectively. The first electrode of the twenty-fourth P-type transistor P24 is connected to the first power supply line VDD, the first electrode of the twenty-fourth N-type transistor N24 is connected to the ground line GND, the second electrode of the twenty-fourth P-type transistor P24 and the second electrode of the twenty-fourth N-type transistor N24 are connected to each other and to the gate electrode of the twenty-fifth P-type transistor P25 and the gate electrode of the twenty-fifth N-type transistor N25, respectively.

[0204] In the exemplary embodiment, the twenty-fifth P-type transistor P25 and the twenty-fifth N-type transistor N25 constitute a ninth inverter 409. The gate electrode of the twenty-fifth P-type transistor P25 and the gate electrode of the twenty-fifth N-type transistor N25 are connected to each other and to the second electrode of the twenty-fourth P-type transistor P24 and the second electrode of the twenty-fourth N-type transistor N24, respectively. A first electrode of the twenty-fifth P-type transistor P25 is connected to the first power supply line VDD, a first electrode of the twenty-fifth N-type transistor N25 is connected to the ground line GND, and a second electrode of the twenty-fifth P-type transistor P25 and the second electrode of the twenty-fifth N-type transistor N25 are connected to each other and to the gate electrode of the twenty-sixth P-type transistor P26 and the gate electrode of the twenty-sixth N-type transistor N26, respectively.

[0205] In the exemplary embodiment, the twenty-sixth P-type transistor P26 and the twenty-sixth N-type transistor N26 constitute the tenth inverter 410. The gate electrode of the twenty-sixth P-type transistor P26 and the gate electrode of the twenty-sixth N-type transistor N26 are connected to each other and to the second electrode of the twenty-fifth P-type transistor P25 and the second electrode of the twenty-fifth N-type transistor N25, respectively. The first electrode of the twenty-sixth P-type transistor P26 is connected to the first power supply line VDD, the first electrode of the twenty-sixth N-type transistor N26 is connected to the ground line GND, and the second electrode of the twenty-sixth P-type transistor P26 and the second electrode of the twenty-sixth N-type transistor N26 are connected to each other and to the gate electrode of the twenty-ninth P-type transistor P29, the gate electrode of the twenty-ninth N-type transistor N29, the gate electrode of the thirty-second P-type transistor P32, and the gate electrode of the thirty-second N-type transistor N32, respectively.

[0206] In an exemplary embodiment, the twenty-seventh to thirty-fifth P-type transistors P27 to P35 and the twenty-seventh to thirty-fifth N-type transistors N27 to N35 constitute the latch 520 .

[0207] In an exemplary embodiment, the gate electrode of the twenty-seventh P-type transistor P27 and the gate electrode of the twenty-seventh N-type transistor N27 are interconnected and respectively connected to the second input terminal B_Qn of the logic operation circuit, the gate electrode of the thirty-third P-type transistor P33 and the gate electrode of the thirty-third N-type transistor N33, the first electrode of the twenty-seventh P-type transistor P27 is connected to the first power supply line VDD, the first electrode of the twenty-seventh N-type transistor N27 is connected to the ground line GND, the second electrode of the twenty-seventh P-type transistor P27 and the second electrode of the twenty-seventh N-type transistor N27 are interconnected and respectively connected to the gate electrode of the twenty-eighth P-type transistor P28 and the gate electrode of the twenty-eighth N-type transistor N28.

[0208] In the exemplary embodiment, the gate electrode of the twenty-eighth P-type transistor P28 and the gate electrode of the twenty-eighth N-type transistor N28 are connected to each other and are respectively connected to the second electrode of the twenty-seventh P-type transistor P27 and the second electrode of the twenty-seventh N-type transistor N27. The gate electrode of the twenty-ninth P-type transistor P29 and the gate electrode of the twenty-ninth N-type transistor N29 are connected to each other and are respectively connected to the second electrode of the twenty-sixth P-type transistor P26, the second electrode of the twenty-sixth N-type transistor N26, the gate electrode 232P of the thirty-second P-type transistor P32, and the gate electrode of the thirty-second N-type transistor N32. In addition, the first electrode of the twenty-eighth P-type transistor P28 and the first electrode of the twenty-ninth P-type transistor P29 are both connected to the first power supply line VDD, the second electrode of the twenty-eighth P-type transistor P28 and the second electrode of the twenty-ninth P-type transistor P29 are connected to each other, and are respectively connected to the second electrode of the twenty-eighth N-type transistor N28, the gate electrode of the thirtieth P-type transistor P30 and the gate electrode of the thirtieth N-type transistor N30, the first electrode of the twenty-ninth N-type transistor N29 is connected to the ground line GND, and the second electrode of the twenty-ninth N-type transistor N29 is connected to the first electrode of the twenty-eighth N-type transistor N28.

[0209] In the exemplary embodiment, the gate electrode of the 30th P-type transistor P30 and the gate electrode of the 30th N-type transistor N30 are connected to each other and are respectively connected to the second electrode of the 28th P-type transistor P28, the second electrode of the 28th N-type transistor N28, and the second electrode of the 29th P-type transistor P29. The gate electrode of the 31st P-type transistor P31 and the gate electrode of the 31st N-type transistor N31 are connected to each other and are respectively connected to the second electrode of the 34th P-type transistor P34, the second electrode of the 34th N-type transistor N34, the second electrode of the 35th P-type transistor P35, the gate electrode of the 36th P-type transistor P36, and the gate electrode of the 37th P-type transistor P37. The gate electrode of the sixteenth N-type transistor N36 is connected, the first electrode of the thirtieth P-type transistor P30 and the first electrode of the thirty-first P-type transistor P31 are both connected to the first power supply line VDD, the second electrode of the thirtieth P-type transistor P30 and the second electrode of the thirty-first P-type transistor P31 are connected to each other, and are respectively connected to the second electrode of the thirty-first N-type transistor N31, the gate electrode of the thirty-fifth P-type transistor P35 and the gate electrode of the thirty-fifth N-type transistor N35, the first electrode of the thirtieth N-type transistor N30 is connected to the ground line GND, and the second electrode of the thirtieth N-type transistor N30 is connected to the first electrode of the thirty-first N-type transistor N30.

[0210] In an exemplary embodiment, the gate electrode of the thirty-second P-type transistor P32 and the gate electrode of the thirty-second N-type transistor N32 are connected to each other, and are respectively connected to the second electrode of the twenty-sixth P-type transistor P26, the second electrode of the twenty-sixth N-type transistor N26, the gate electrode of the twenty-ninth P-type transistor P29, and the gate electrode of the twenty-ninth N-type transistor N29. The gate electrode of the thirty-third P-type transistor P33 and the gate electrode of the thirty-third N-type transistor N33 are connected to each other, and are respectively connected to the second input terminal B_Qn of the logic operation circuit, the gate electrode of the twenty-seventh P-type transistor P27, and the gate electrode of the twenty-seventh N-type transistor N27. The first electrode of the thirty-second P-type transistor P32 and the first electrode of the thirty-third P-type transistor P33 are both connected to the first power supply line VDD, the second electrode of the thirty-second P-type transistor P32 and the second electrode of the thirty-third P-type transistor P33 are connected to each other, and are respectively connected to the second electrode of the thirty-third N-type transistor N33, the gate electrode of the thirty-fourth P-type transistor P34 and the gate electrode of the thirty-fourth N-type transistor N34, the first electrode of the thirty-second N-type transistor N32 is connected to the ground line GND, and the second electrode of the thirty-second N-type transistor N32 is connected to the first electrode of the thirty-third N-type transistor N33.

[0211] In the exemplary embodiment, the gate electrode of the thirty-fourth P-type transistor P34 and the gate electrode of the thirty-fourth N-type transistor N34 are connected to each other and are respectively connected to the second electrode of the thirty-second P-type transistor P32, the second electrode of the thirty-third P-type transistor P33, and the second electrode of the thirty-third N-type transistor N33. The gate electrode of the thirty-fifth P-type transistor P35 and the gate electrode of the thirty-fifth N-type transistor N35 are connected to each other and are respectively connected to the second electrode of the thirtieth P-type transistor P30, the second electrode of the thirty-first P-type transistor P31, and the second electrode of the thirty-first N-type transistor N31. The first electrode of the thirty-fourth P-type transistor P34 and the first electrode of the thirty-fifth P-type transistor P35 are both connected to the first electrode. The source line VDD is connected, the second electrode of the thirty-fourth P-type transistor P34 and the second electrode of the thirty-fifth P-type transistor P35 are connected to each other, and are respectively connected to the second electrode of the thirty-fourth N-type transistor N34, the gate electrode of the thirty-first P-type transistor P31, the gate electrode of the thirty-first N-type transistor N31, the gate electrode of the thirty-sixth P-type transistor P36 and the gate electrode of the thirty-sixth N-type transistor N36, the first electrode of the thirty-fifth N-type transistor N35 is connected to the ground line GND, and the second electrode of the thirty-fifth N-type transistor N35 is connected to the first electrode of the thirty-fourth N-type transistor N34.

[0212] In the exemplary embodiment, the thirty-sixth P-type transistor P36, the thirty-sixth N-type transistor N36, the thirty-seventh P-type transistor P37, and the thirty-seventh N-type transistor N37 constitute a fourth NOR gate 504. The gate electrode of the thirty-sixth P-type transistor P36 and the gate electrode of the thirty-sixth N-type transistor N36 are connected to each other, and are respectively connected to the second electrode of the thirty-fourth P-type transistor P34, the second electrode of the thirty-fourth N-type transistor N34, the second electrode of the thirty-fifth P-type transistor P35, the gate electrode of the thirty-first P-type transistor P31, and the gate electrode of the thirty-first N-type transistor N31. The gate electrode of the thirty-seventh P-type transistor P37 and the gate electrode of the thirty-seventh N-type transistor N37 are connected to each other and are connected to the ratio control terminal D_Qn of the logic operation circuit. The thirty-sixth P-type transistor P36 and the gate electrode of the thirty-sixth N-type transistor N36 are connected to each other, and are respectively connected to the second electrode of the thirty-fourth P-type transistor P34, the second electrode of the thirty-fourth N-type transistor N34, the second electrode of the thirty-fifth P-type transistor P35, the gate electrode of the thirty-first P-type transistor P31, and the gate electrode of the thirty-first N-type transistor N31. The gate electrode of the thirty-seventh P-type transistor P37 and the gate electrode of the thirty-seventh N-type transistor N37 are connected to each other, and are connected to the ratio control terminal D_Qn of the logic operation circuit. The first electrode of the thirty-sixth P-type transistor P36 is connected to the first power supply line VDD, the second electrode of the thirty-sixth P-type transistor P36 is connected to the first electrode of the thirty-seventh P-type transistor P37, the first electrode of the thirty-sixth N-type transistor N36 and the first electrode of the thirty-seventh N-type transistor N37 are both connected to the ground line GND, the second electrode of the thirty-sixth N-type transistor N36 and the second electrode of the thirty-seventh N-type transistor N37 are connected to each other, and are respectively connected to the second electrode of the thirty-seventh P-type transistor P37, the gate electrode of the thirty-ninth P-type transistor P39 and the gate electrode of the thirty-ninth N-type transistor N39.

[0213] In the exemplary embodiment, the thirty-eighth P-type transistor P38, the thirty-eighth N-type transistor N38, the thirty-ninth P-type transistor P39, and the thirty-ninth N-type transistor N39 constitute a second NAND gate 302. The gate electrode of the thirty-eighth P-type transistor P38 and the gate electrode of the thirty-eighth N-type transistor N38 are connected to each other and to the second reset terminal LF_pulse2 of the logic operation circuit. The gate electrode of the thirty-ninth P-type transistor P39 and the gate electrode of the thirty-ninth N-type transistor N39 are connected to each other and to the second electrode of the thirty-sixth N-type transistor N36, the second electrode of the thirty-seventh P-type transistor P37, and the second electrode of the thirty-seventh N-type transistor N37, respectively. The first electrode of the thirty-eighth P-type transistor P38 and the first electrode of the thirty-ninth P-type transistor P39 are both connected to the first power line VDD. The thirty-ninth N-type transistor N39 The first electrode of the thirty-ninth N-type transistor N39 is connected to the ground line GND, the second electrode of the thirty-ninth N-type transistor N39 is connected to the first electrode of the thirty-eighth N-type transistor N38, the second electrode of the thirty-eighth P-type transistor P38, the second electrode of the thirty-eighth N-type transistor N38 and the second electrode of the thirty-ninth P-type transistor P39 are connected to each other and serve as the output terminal OUT_DS of the second operation circuit (that is, the output terminal of the output display switch signal DSn in Figure 9, which can be used as the display switch signal terminal DSn of the logic operation circuit).

[0214] Figure 11 is a schematic diagram illustrating the operation of a third arithmetic circuit according to an exemplary embodiment of the present disclosure. The third arithmetic circuit may include two components: a NOR gate and a NAND gate. As shown in Figure 9 , the third arithmetic circuit may include a fifth NOR gate 505 and a third NAND gate 303.

[0215] In an exemplary embodiment, a first input terminal of the fifth NOR gate 505 is connected to the third input terminal C_Qn of the logic operation circuit, a second input terminal of the fifth NOR gate 505 is connected to the second input terminal B_Qn of the logic operation circuit, a third input terminal of the fifth NOR gate 505 is connected to the duty control terminal D_Qn of the logic operation circuit, an output terminal of the fifth NOR gate 505 is connected to the first input terminal of the third NAND gate 303, a second input terminal of the third NAND gate 303 is connected to the second reset terminal LF_pulse2 of the logic operation circuit, and an output terminal of the third NAND gate 303 serves as the output terminal OUT_AZ of the third operation circuit and as the display reset signal terminal AZn of the logic operation circuit, and is connected to the display reset control terminal AZ in at least one pixel driving circuit, and outputs a display reset signal to the display reset control terminal AZ in the at least one pixel driving circuit. In an exemplary embodiment, the output end of the third NAND gate 303 can be connected to the input end of another level converter (e.g., a third level converter), and a display reset signal is output to the level converter. The level converter converts the display reset signal into a voltage domain and outputs the signal to a corresponding row driver enhancer (e.g., a third row driver enhancer). The row driver enhancer enhances the converted signal and outputs the signal to a display reset control terminal AZ in a corresponding pixel driver circuit.

[0216] In an exemplary embodiment, the operating principle of the third operation circuit is as follows: the fifth NOR gate 505 performs a NOR operation on the third input signal of the third input terminal IN_C_Qn, the second input signal of the second input terminal IN_B_Qn, and the duty control signal of the duty control terminal IN_D_Qn, and the third NAND gate 303 performs a NAND operation on the NOR operation result and the second reset signal of the second reset terminal IN_LF_pulse2. The logical expression thereof is: Among them, LF_pulse2 is the initialization signal, which maintains a high level under normal working conditions (i.e., LF_pulse2=1), then AZn=B_Qn+C_Qn+D_Qn. When LF_pulse2 is a low level (i.e., LF_pulse2=0), then AZn=1, and AZn outputs a high level. When the luminous time accounts for 100%, D_Qn remains at a low level, then AZn=B_Qn+C_Qn. When it is necessary to adjust the luminous time proportion, it can be done by adjusting the duty cycle of D_Qn. That is, the duty cycle control signal of the duty cycle control terminal D_Qn can simultaneously affect the write switch signal DSn and the display reset signal AZn, and the write switch signal DSn and the display reset signal AZn can be simultaneously controlled by the duty cycle control signal of the duty cycle control terminal D_Qn, thereby adjusting and controlling the luminous time proportion of the luminous stage.

[0217] Figure 12 is an equivalent circuit diagram of a third arithmetic circuit according to an exemplary embodiment of the present disclosure. As shown in Figure 12, the third arithmetic circuit of the logic arithmetic circuit of the gate driver circuit in the display substrate of the present embodiment may include 10 transistors. The fifth NOR gate 505 includes three P-type transistors and three N-type transistors, and the third NAND gate 303 includes two P-type transistors and two N-type transistors.

[0218] In an exemplary embodiment, the fifth NOR gate 505 and the third NAND gate 303 may be sequentially disposed along the first direction X (a direction approaching the display area).

[0219] In the exemplary embodiment, the forty-first P-type transistor P41, the forty-first N-type transistor N41, the forty-second P-type transistor P42, the forty-second N-type transistor N42, the forty-third P-type transistor P43, and the forty-third N-type transistor N43 form a fifth NOR gate 505. The gate electrode of the forty-first P-type transistor P41 and the gate electrode of the forty-first N-type transistor N41 are connected to each other and to the duty control terminal IN_D_Qn of the logic operation circuit. The gate electrode of the forty-second P-type transistor P42 and the gate electrode of the forty-second N-type transistor N42 are connected to each other and to the second input terminal B_Qn of the logic operation circuit. The gate electrode of the forty-third P-type transistor P43 and the gate electrode of the forty-third N-type transistor N43 are connected to each other and to the third input terminal IN_C_Qn of the logic operation circuit. The first electrode of the forty-first P-type transistor P41 is connected to the first power supply line VDD, and the second electrode of the forty-first P-type transistor P41 is connected to the first power supply line VDD. The first electrode of the forty-second P-type transistor P42 is connected, the second electrode of the forty-second P-type transistor P42 is connected to the first electrode of the forty-third P-type transistor P43, the first electrode of the forty-first N-type transistor N41, the first electrode of the forty-second N-type transistor N42 and the first electrode of the forty-third N-type transistor N43 are all connected to the ground line GND, the second electrode of the forty-first N-type transistor N41, the second electrode of the forty-second N-type transistor N42 and the second electrode of the forty-third N-type transistor N43 are connected to each other, and are respectively connected to the second electrode of the forty-third P-type transistor P43, the gate electrode of the forty-fifth P-type transistor P45 and the gate electrode of the forty-fifth N-type transistor N45.

[0220] In the exemplary embodiment, the forty-fourth P-type transistor P44, the forty-fourth N-type transistor N44, the forty-fifth P-type transistor P45, and the forty-fifth N-type transistor N45 constitute a third NAND gate 303. The gate electrode of the forty-fourth P-type transistor P44 and the gate electrode of the forty-fourth N-type transistor N44 are connected to each other and to the second reset terminal LF_pulse2 of the logic operation circuit. The gate electrode of the forty-fifth P-type transistor P45 and the gate electrode of the forty-fifth N-type transistor N45 are connected to each other and to the second electrode of the forty-first N-type transistor N41, the second electrode of the forty-second N-type transistor N42, the second electrode of the forty-third N-type transistor N43, and the second electrode of the forty-third P-type transistor P43, respectively. The first electrode of the forty-fourth P-type transistor P44 and the first electrode of the forty-fifth P-type transistor P45 are both connected to the first power supply line VDD. The first electrode of the forty-fourth N-type transistor N44 is connected to the ground line GND. The forty-fourth N-type transistor N44 is connected to the ground line GND. The second electrode of the forty-fifth N-type transistor N45 is connected to the first electrode of the forty-fourth P-type transistor P44, the second electrode of the forty-fifth P-type transistor P45 and the second electrode of the forty-fifth N-type transistor N45 are connected to each other and serve as the output terminal OUT_AZ of the third operation circuit (that is, the output terminal of the output display reset signal AZn in Figure 11, which can be used as the display reset signal terminal OUT_AZn of the logic operation circuit).

[0221] FIG13 is a diagram illustrating the working principle of a level converter according to an exemplary embodiment of the present disclosure. As shown in FIG13 , the level converter may include an eleventh inverter 411 , a first P-type field effect transistor 501P, a second P-type field effect transistor 502P, a first N-type field effect transistor 501N, and a second N-type field effect transistor 502N.

[0222] In an exemplary embodiment, the input terminal IN_shifter of the level converter is respectively connected to the input terminal of the eleventh inverter 411 and the gate electrode of the first P-type field effect transistor 501P (wherein, the input terminal of the second level converter is electrically connected to the display switch signal terminal OUT_DSn in the logic operation circuit, and the input terminal of the third level converter is electrically connected to the display reset signal terminal AZ in the path operation circuit), the output terminal of the eleventh inverter 411 is connected to the gate electrode of the second P-type field effect transistor 502P, and the first electrode of the first P-type field effect transistor 501P and the first electrode of the second P-type field effect transistor 502P are both connected to the first power supply The first power supply line VDD is connected to the first P-type field effect transistor 501P. The second electrode of the first P-type field effect transistor 501N is connected to the second electrode of the first N-type field effect transistor 501N, the gate electrode of the second N-type field effect transistor 502N, and the second output terminal OUT_B_shifter of the level shifter. The second electrode of the second P-type field effect transistor 502P is connected to the gate electrode of the first N-type field effect transistor 501N, the second electrode of the second N-type field effect transistor 502N, and the first output terminal OUT_shifter of the level shifter. The first electrode of the first N-type field effect transistor 501N and the first electrode of the second N-type field effect transistor 502N are both connected to the second power supply line VSS. The first output terminal of the second level shifter is electrically connected to the first input terminal of the second row driver booster; the second output terminal of the second level shifter is electrically connected to the second input terminal of the second row driver booster; the first output terminal of the third level shifter is electrically connected to the first input terminal of the third row driver booster; and the second output terminal of the third level shifter is electrically connected to the second input terminal of the third row driver booster.

[0223] In an exemplary embodiment, the operating principle of the level shifter is as follows: when the input signal at the input terminal IN_shifter of the level shifter is low, the first P-type field-effect transistor 501P is turned on, the second P-type field-effect transistor 502P is turned off, the output signal at the second output terminal OUT_B_shifter of the level shifter is the signal of the first power line VDD, the second N-type field-effect transistor 502N is turned on, the output signal at the first output terminal OUT_shifter of the level shifter is the signal of the second power line VSS, and the first N-type field-effect transistor 501N is turned off. When the input signal at the input terminal IN_shifter of the level shifter is high, the first P-type field-effect transistor 501P is turned off, the second P-type field-effect transistor 502P is turned on, the output signal at the first output terminal OUT_shifter of the level shifter is the signal of the first power line VDD, the first N-type field-effect transistor 501N is turned on, the output signal at the second output terminal OUT_B_shifter of the level shifter is the signal of the second power line VSS, and the second N-type field-effect transistor 502N is turned off.

[0224] FIG14 is a schematic diagram illustrating the operating principle of a row driver enhancer according to an exemplary embodiment of the present disclosure. As shown in FIG14 , the row driver enhancer may include a fourth NAND gate 304, a fifth NAND gate 305, a first transmission gate 201, a twelfth inverter 412, a third P-type field effect transistor 503P, and a third N-type field effect transistor 503N. The third P-type field effect transistor 503P and the third N-type field effect transistor 503N have a relatively large width-to-length ratio to improve driving capability. The row driver enhancer can enhance the driving capability of a signal. The signal enhanced by the row driver enhancer can enhance the driving capability and can be suitable for driving an entire row of pixel driver circuits. In an exemplary embodiment, the enable signal input terminal IN_EN in FIG14 can be electrically connected to the reset control subcircuit 10-3 in FIG6 d and configured to receive the reset control signal from the reset control subcircuit 10-3. The reset control subcircuit 10-3 may include a NAND gate and an inverter, wherein the two input terminals of the NAND gate are respectively connected to the reset control terminal and the reset terminal, the output terminal of the NAND gate is connected to the input terminal of the inverter, and the output terminal of the inverter is connected to the enable signal input terminal IN_EN in the row driver enhancer.

[0225] In an exemplary embodiment, a first input terminal IN_driver of the row driver booster is connected to a first input terminal of a fourth NAND gate 304, an enable signal terminal EN of the row driver booster is connected to a second input terminal of the fourth NAND gate 304, an output terminal of the fourth NAND gate 304 is connected to an input terminal of the first transmission gate 201, an output terminal of the first transmission gate 201 is connected to a gate electrode of a third P-type field effect transistor 503P, and a first electrode of the third P-type field effect transistor 503P is connected to a first power supply line VDD. A second input terminal IN_B_driver of the row driver booster is connected to a first input terminal of a fifth NAND gate 305, an enable signal EN of the row driver booster is connected to a second input terminal of the fifth NAND gate 305, an output terminal of the fifth NAND gate 305 is connected to an input terminal of a twelfth inverter 412, an output terminal of the twelfth inverter 412 is connected to a gate electrode of a third N-type field effect transistor 503N, and a first electrode of the third N-type field effect transistor 503N is connected to a second power supply line VSS. The second electrode of the third P-type field-effect transistor 503P and the second electrode of the third N-type field-effect transistor 503N are connected to the output terminal OUT_driver of the row driver booster. The first transmission gate 201 and the twelfth inverter 412 have active-high enable terminals connected to the first power line VDD, and active-low enable terminals connected to the second power line VSS. The fourth NAND gate 304 and the fifth NAND gate 305 have active-high enable terminals connected to the first power line VDD, and active-low enable terminals connected to the ground line GND. In an exemplary embodiment, the output terminal of the second row driver booster is electrically connected to the display switch control terminal DS of the corresponding pixel driver circuit, and the output terminal of the third row driver booster is electrically connected to the display reset control terminal AZ of the corresponding pixel driver circuit.

[0226] In an exemplary embodiment, when the enable signal input to the enable signal terminal IN_EN of the row driver booster is a first level signal, the row driver booster is in a high-impedance state. This satisfies the requirement that, when the gate driver circuit is bilaterally driven (i.e., the gate driver circuit is located on both sides of the display area of ​​the display substrate), the enable signal input to the enable signal terminal of the row driver booster located on one side of the display area is set to the first level, so that the modified row driver booster is in a high-impedance state, thereby achieving unilateral driving of the gate driver circuit. That is, when gate driver circuits are provided on both sides of the display area, the high-impedance state of the row driver booster can achieve unilateral driving of the gate driver circuit (the row driver booster on one side of the display area is in a high-impedance state) or bilateral driving (the row driver boosters on both sides of the display area are not in a high-impedance state).

[0227] In an exemplary embodiment, the first level of the enable signal input to the enable signal terminal EN of the row driver booster may be a low level, that is, the enable signal is a low level. The embodiments of the present disclosure are not limited thereto. The row driver booster can be configured according to the circuit structure of the row driver booster so that the row driver booster is in a high-impedance state when the enable signal is at the first level.

[0228] In an exemplary embodiment, the row driver booster operates as follows:

[0229] When the enable signal at the enable signal terminal EN is 0, the fourth NAND gate 304 and the fifth NAND gate 305 output 1 (high level). The output of the fourth NAND gate 304 outputs 1 (high level) after passing through the first transmission gate 201, the third P-type field effect transistor 503P is turned off, and the output of the fifth NAND gate 305 outputs 0 (low level) after passing through the twelfth inverter 412, the third N-type field effect transistor 503N is turned off, and the entire circuit is in a high-impedance state.

[0230] When the enable signal at the enable signal terminal EN is 1, the circuit output is determined by the input signals at the first input terminal IN_driver and the second input terminal IN_B_driver of the row driver enhancer. The input signal at the first input terminal IN_driver and the input signal at the second input terminal IN_B_driver of the row driver enhancer are opposite direction signals. The opposite direction signals mean that the input signal at the first input terminal IN_driver is a high level signal 1, and the input signal at the second input terminal IN_B_driver is a low level signal 0; the input signal at the first input terminal IN_driver is a low level signal 0, and the input signal at the second input terminal IN_B_driver is a high level signal 1.

[0231] When the input signal at the first input terminal IN_driver of the row driver booster is 1 and the input signal at the second input terminal IN_B_driver is 0, the fourth NAND gate 304 outputs 0. The output of the fourth NAND gate 304 is output as 0 after passing through the first transmission gate 201, and the third P-type field effect transistor 503P is turned on. The fifth NAND gate 305 outputs 1. The output of the fifth NAND gate 305 is output as 0 after passing through the twelfth inverter 412, and the third N-type field effect transistor 503N is turned off. The output signal at the output terminal OUT_driver of the row driver booster is the signal of the first power line VDD (high level).

[0232] When the input signal at the first input terminal IN_driver of the row driver booster is 0 and the input signal at the second input terminal IN_B_driver is 1, the fourth NAND gate 304 outputs 1. The output of the fourth NAND gate 304 outputs 1 after passing through the first transmission gate 201, and the third P-type field effect transistor 503P is turned off. The fifth NAND gate 305 outputs 0. The output of the fifth NAND gate 305 outputs 1 after passing through the twelfth inverter 412, and the third N-type field effect transistor 503N is turned on. The output signal at the output terminal OUT_driver of the row driver booster is the signal of the second power line VSS (low level).

[0233] In an exemplary embodiment, when the enable signal at the enable signal terminal EN is 0, the circuit output is in a high-impedance state. When the enable signal at the enable signal terminal EN is 1, the circuit output does not change the logical relationship between the high and low inputs and outputs; the enable signal at the enable signal terminal EN is a high-configuration control signal. In principle, the row driver booster is a buffer with a large width-to-length ratio, resulting in high output current and high drive capability. Furthermore, the row driver booster has low output impedance and strong drive capability.

[0234] In an exemplary embodiment, the input terminal IN_shifter of the level converter can be connected to the output terminal of the logic operation circuit 200, the first output terminal OUT_shifter of the level converter can be connected to the first input terminal IN_driver of the row driver enhancer, the second output terminal OUT_B_shifter of the level converter can be connected to the second input terminal IN_B_driver of the row driver enhancer, and the output terminal OUT_driver of the row driver enhancer can be connected to the scan signal line of the display area.

[0235] Figure 15 is an equivalent circuit diagram of a level shifter according to an exemplary embodiment of the present disclosure. As shown in Figure 15 , the level shifter of the gate drive circuit in the display substrate according to the present embodiment may include 16 transistors. The eleventh inverter 411 includes one P-type transistor and one N-type transistor, the first P-type field-effect transistor 501P includes six P-type transistors, the second P-type field-effect transistor 502P includes six P-type transistors, the first N-type field-effect transistor 501N includes one N-type transistor, and the second N-type field-effect transistor 502N includes one N-type transistor.

[0236] In the exemplary embodiment, the fifty-first P-type transistor P1 and the fifty-first N-type transistor N1 form the eleventh inverter 411. The gate electrode of the fifty-first P-type transistor P1 and the gate electrode of the fifty-first N-type transistor N1 are both connected to the converter input terminal IN_shifter, a first electrode of the fifty-first P-type transistor P1 is connected to the first power supply line VDD, a first electrode of the fifty-first N-type transistor N1 is connected to the ground line GND, a second electrode of the fifty-first P-type transistor P1 is connected to the second electrode of the fifty-first N-type transistor N1, and is connected to the gate electrodes of the six P-type transistors in the second P-type field-effect transistor 502P.

[0237] In an exemplary embodiment, the fifty-second P-type transistor P52, the fifty-third P-type transistor P53, the fifty-fourth P-type transistor P54, the fifty-fifth P-type transistor P55, the fifty-sixth P-type transistor P56 and the fifty-seventh P-type transistor P57 connected in parallel constitute a first P-type field effect transistor 501P, the gate electrodes of the fifty-second P-type transistor P52 to the fifty-seventh P-type transistor P57 are all connected to the converter input terminal IN_shifter, the first electrodes of the fifty-second P-type transistor P52 to the fifty-seventh P-type transistor P57 are all connected to the first power line VDD, and the second electrodes of the fifty-second P-type transistor P52 to the fifty-seventh P-type transistor P57 are respectively connected to the gate electrode of the fifty-third N-type transistor N53, the second electrode of the fifty-second N-type transistor N52 and the second output terminal OUT_B_shifter of the converter.

[0238] In an exemplary embodiment, the fifty-eighth P-type transistor P58, the fifty-ninth P-type transistor P59, the sixtieth P-type transistor P60, the sixty-first P-type transistor P61, the sixty-second P-type transistor P62 and the sixty-third P-type transistor P63 connected in parallel constitute a second P-type field effect transistor 502P, the gate electrodes of the fifty-eighth P-type transistor P58 to the sixty-third P-type transistor P63 are all connected to the second electrode of the fifty-first P-type transistor P51 and the second electrode of the fifty-first N-type transistor N51, the first electrodes of the fifty-eighth P-type transistor P58 to the sixty-third P-type transistor P63 are all connected to the first power line VDD, and the second electrodes of the fifty-eighth P-type transistor P58 to the sixty-third P-type transistor P63 are respectively connected to the gate electrode of the fifty-second N-type transistor N52, the second electrode of the fifty-third N-type transistor N53 and the first output terminal OUT_shifter of the converter.

[0239] In the exemplary embodiment, a fifty-second N-type transistor N52 serves as the first N-type field-effect transistor 501N. A gate electrode of the fifty-second N-type transistor N52 is connected to the first output terminal OUT_shifter of the converter and second electrodes of the fifty-eighth through sixty-third P-type transistors P58 through P63, respectively. A first electrode of the fifty-second N-type transistor N52 is connected to the second power supply line VSS, and a second electrode of the fifty-second N-type transistor N52 is connected to the second output terminal OUT_B_shifter of the converter and second electrodes of the fifty-second through fifty-seventh P-type transistors P52 through P57, respectively.

[0240] In an exemplary embodiment, the fifty-third N-type transistor N53 serves as the second N-type field-effect transistor 502N, the gate electrode of the fifty-third N-type transistor N53 is respectively connected to the second output terminal OUT_B_shifter of the converter and the second electrodes of the fifty-second P-type transistor P52 to the fifty-seventh P-type transistor P57, the first electrode of the fifty-third N-type transistor N53 is connected to the second power line VSS, and the second electrode of the fifty-third N-type transistor N53 is respectively connected to the first output terminal OUT_shifter of the converter and the second electrodes of the fifty-eighth P-type transistor P58 to the sixty-third P-type transistor P63.

[0241] Figure 16 is an equivalent circuit diagram of a row driver booster according to an exemplary embodiment of the present disclosure. As shown in Figure 16, the row driver booster of the gate driver circuit in the display substrate according to the embodiment of the present disclosure may include 20 transistors. Among them, the fourth NAND gate 304 includes two P-type transistors and two N-type transistors, the fifth NAND gate 305 includes two P-type transistors and two N-type transistors, the first transmission gate 201 includes one P-type transistor and one N-type transistor, the twelfth inverter 412 includes one P-type transistor and one N-type transistor, the third P-type field-effect transistor 503P includes four P-type transistors, and the third N-type field-effect transistor 503N includes four N-type transistors.

[0242] In an exemplary embodiment, the fourth NAND gate 304, the first transmission gate 201, the fifth NAND gate 305 and the twelfth inverter 412 can be arranged in sequence along the first direction X (the direction close to the display area), the third P-type field effect transistor 503P and the third N-type field effect transistor 503N can be arranged on one side of the twelfth inverter 412 in the first direction X, and the third N-type field effect transistor 503N can be arranged on one side of the third P-type field effect transistor 503P in the second direction Y.

[0243] In an exemplary embodiment, the seventy-first P-type transistor P71 , the seventy-second P-type transistor P72 , the seventy-first N-type transistor N71 , and the seventy-second N-type transistor N72 constitute a fourth NAND gate 304 . The gate electrode of the seventy-first P-type transistor P71 and the gate electrode of the seventy-first N-type transistor N71 are connected to each other and to the first input terminal IN_driver of the enhancer, the gate electrode of the seventy-second P-type transistor P72 and the gate electrode of the seventy-second N-type transistor N72 are connected to each other and to the enable signal terminal EN, the first electrode of the seventy-first P-type transistor P71 and the first electrode of the seventy-second P-type transistor P72 are both connected to the first power line VDD, the first electrode of the seventy-second N-type transistor N72 is connected to the second power line VSS, the second electrode of the seventy-second N-type transistor N72 is connected to the first electrode of the seventy-first N-type transistor N71, the second electrode of the seventy-first P-type transistor P71 and the second electrode of the seventy-second P-type transistor P72 are connected to each other and are respectively connected to the second electrode of the seventy-first N-type transistor N71, the first electrode of the seventy-third P-type transistor P73 and the first electrode of the seventy-third N-type transistor N73.

[0244] In the exemplary embodiment, the seventy-third P-type transistor P73 and the seventy-third N-type transistor N73 constitute the first transmission gate 201. The gate electrode of the seventy-third P-type transistor P73 is connected to the second power supply line VSS, the gate electrode of the seventy-third N-type transistor N73 is connected to the first power supply line VDD, the first electrode of the seventy-third P-type transistor P73 and the first electrode of the seventy-third N-type transistor N73 are connected to each other and are respectively connected to the second electrode of the seventy-first P-type transistor P71, the second electrode of the seventy-first N-type transistor N71, and the second electrode of the seventy-second P-type transistor P72, the second electrode of the seventy-third P-type transistor P73 and the second electrode of the seventy-third N-type transistor N73 are connected to each other and are respectively connected to the gate electrodes of the seventy-seventh P-type transistor P77 to the eightieth P-type transistor P80.

[0245] In an exemplary embodiment, the seventy-fourth P-type transistor P74 , the seventy-fifth P-type transistor P75 , the seventy-fourth N-type transistor N74 , and the seventy-fifth N-type transistor N75 constitute a fifth NAND gate 305 . The gate electrode of the seventy-fourth P-type transistor P74 and the gate electrode of the seventy-twenty-fourth N-type transistor N74 are connected to each other and to the second input terminal IN_B_driver of the enhancer, the gate electrode of the seventy-fifth P-type transistor P75 and the gate electrode of the seventy-fifth N-type transistor N75 are connected to each other and to the enable signal terminal EN, the first electrode of the seventy-fourth P-type transistor P74 and the first electrode of the seventy-fifth P-type transistor P75 are both connected to the first power line VDD, the first electrode of the seventy-fifth N-type transistor N75 is connected to the second power line VSS, the second electrode of the seventy-fifth N-type transistor N75 is connected to the first electrode of the seventy-fourth N-type transistor N74, the second electrode of the seventy-fourth P-type transistor P74 and the second electrode of the seventy-fifth P-type transistor P75 are connected to each other and are respectively connected to the second electrode of the seventy-fourth N-type transistor N74, the gate electrode of the seventy-sixth P-type transistor P76 and the gate electrode of the seventy-sixth N-type transistor N76.

[0246] In the exemplary embodiment, the seventy-sixth P-type transistor P76 and the seventy-sixth N-type transistor N76 constitute the twelfth inverter 412. The gate electrode of the seventy-sixth P-type transistor P76 and the gate electrode of the seventy-sixth N-type transistor N76 are connected to each other and are respectively connected to the second electrode of the seventy-fourth P-type transistor P74, the second electrode of the seventy-fourth N-type transistor N74, and the second electrode of the seventy-fifth P-type transistor P75. A first electrode of the seventy-sixth P-type transistor P76 is connected to the first power supply line VDD, a first electrode of the seventy-sixth N-type transistor N76 is connected to the second power supply line VSS, a second electrode of the seventy-sixth P-type transistor P76 and the second electrode of the seventy-sixth N-type transistor N27 are connected to each other and are respectively connected to the gate electrodes of the seventy-seventh N-type transistor N77 to the eightieth N-type transistor N80.

[0247] In the exemplary embodiment, a seventy-seventh P-type transistor P77, a seventy-eighth P-type transistor P78, a seventy-ninth P-type transistor P79, and an eightieth P-type transistor P80 connected in parallel form a third P-type field effect transistor 503P. Gate electrodes of the seventy-seventh P-type transistor P77 through the eightieth P-type transistor P80 are connected to one another and to the second electrode of the seventy-third P-type transistor P73 and the second electrode of the seventy-third N-type transistor N73, respectively. First electrodes of the seventy-seventh P-type transistor P77 through the eightieth P-type transistor P80 are all connected to the first power supply line VDD, and second electrodes of the seventy-seventh P-type transistor P77 through the eightieth P-type transistor P80 are all connected to the booster output terminal OUT_driver.

[0248] In the exemplary embodiment, a seventy-seventh N-type transistor N77, a seventy-eighth N-type transistor N78, a seventy-ninth N-type transistor N79, and an eightieth N-type transistor N80, which are connected in parallel, form a third N-type field effect transistor 503N. Gate electrodes of the seventy-seventh N-type transistor N77 through the eightieth N-type transistor N80 are connected to each other and to the second electrode of the seventy-sixth P-type transistor P76 and the second electrode of the seventy-sixth N-type transistor N76, respectively. First electrodes of the seventy-seventh N-type transistor N77 through the eightieth N-type transistor N80 are all connected to the second power supply line VSS, and second electrodes of the seventy-seventh N-type transistor N77 through the eightieth N-type transistor N80 are all connected to the booster output terminal OUT_driver.

[0249] Figure 17 is an equivalent circuit diagram of an output circuit (including a level shifter and a row driver booster) according to an exemplary embodiment of the present disclosure. As shown in Figures 15, 16, and 17, the output circuit includes the level shifter shown in Figure 15 and the row driver booster shown in Figure 16. The first output terminal OUT_shifter of the shifter is connected to the first input terminal IN_driver of the booster, and the second output terminal OUT_B_shifter of the shifter is connected to the second input terminal IN_B_driver of the booster.

[0250] In an exemplary embodiment, as shown in Figure 18, which is a circuit schematic diagram of a shift register circuit provided in an exemplary embodiment of the present disclosure, each gate drive circuit may include four triggers (DFF1 to DFF4), and the shift registers in multiple rows of gate drive circuits are cascaded. For example, the first output terminal OUT_A_Qn (which can be used as the output terminal of the first shift signal A_Qn_inverted signal A_Qn, and the second output terminal OUT_A_Qn_ can be used as the above-mentioned first shift signal output terminal) of the first trigger DFF1 of the n-th row gate drive circuit is connected to the input terminal IN_A_Dn+1 (which can be used as the above-mentioned first signal input terminal) of the first trigger DFF1 of the n+1-th row gate drive circuit; the first output terminal OUT_A_Qn+1 of the first trigger DFF1 of the n+1-th row gate drive circuit is connected to the input terminal IN_A_Dn (which can be used as the above-mentioned first signal input terminal) of the first trigger DFF1 of the n-th row gate drive circuit. Similarly, the first output terminal OUT_B_Qn (which can be used as the above-mentioned second shift signal output terminal) of the second trigger DFF2 of the gate drive circuit of the nth row is connected to the input terminal IN_B_Dn+1 (which can be used as the above-mentioned second signal input terminal) of the second trigger DFF2 of the gate drive circuit of the n+1th row; the first output terminal OUT_B_Qn+1 of the second trigger DFF2 of the gate drive circuit of the n+1th row is connected to the input terminal IN_B_Dn (which can be used as the above-mentioned second signal input terminal) of the second trigger DFF2 of the gate drive circuit of the nth row. The first output terminal OUT_C_Qn of the third flip-flop DFF3 of the gate driver circuit in the nth row (which can serve as the third shift signal output terminal) is connected to the input terminal IN_C_Dn+1 of the third flip-flop DFF3 of the gate driver circuit in the n+1th row (which can serve as the third signal input terminal). The first output terminal OUT_C_Qn+1 of the third flip-flop DFF3 of the gate driver circuit in the n+1th row is connected to the input IN_C_Dn of the third flip-flop DFF3 of the gate driver circuit in the nth row. The first output terminal OUT_D_Qn of the fourth flip-flop DFF4 of the gate driver circuit in the nth row is connected to the input terminal IN_D_Dn+1 of the fourth flip-flop DFF4 of the gate driver circuit in the n+1th row. The first output terminal OUT_D_Qn+1 of the fourth flip-flop DFF4 of the gate driver circuit in the n+1th row is connected to the input terminal IN_D_Dn of the fourth flip-flop DFF4 of the gate driver circuit in the nth row.

[0251] In an exemplary embodiment, as shown in Figure 18, the logic control circuit 10 in the gate drive circuit may include a forward and reverse scan control circuit, and the forward and reverse scan control circuit may include a forward scan control circuit 10-1 and a reverse scan control circuit 10-2. Each forward and reverse scan control circuit may include a first forward and reverse scan control terminal GSD_FW and a second forward and reverse scan control terminal GSD_BW. The two cascaded triggers can be connected through the forward and reverse scan control circuit. Taking the first trigger as an example: the first output terminal OUT_A_Qn of the first trigger DFF1 of the n-th stage gate drive circuit is connected to the input terminal IN_A_Dn+1 of the first trigger DFF1 of the n+1-th stage gate drive circuit through the forward scan control circuit 10-1; the first output terminal OUT_A_Qn+1 of the first trigger DFF1 of the n+1-th stage gate drive circuit is connected to the input terminal IN_A_Dn (which can be used as the above-mentioned first signal input terminal) of the first trigger DFF1 of the n-th stage gate drive circuit through the reverse scan control circuit 10-2. In the case of forward scanning, the forward scanning control circuit 10-1 is turned on and scans in the direction from the nth row to the n+1th row (i.e., the forward scanning control circuit 10-1 is turned on and the reverse scanning control circuit 10-2 is turned off by the signal input to the first forward and reverse scanning control terminal GSD_FW and the second forward and reverse scanning control terminal GSD_BW). In the case of reverse scanning, the reverse scanning control circuit 10-2 is turned on and scans in the direction from the n+1th row to the nth row (i.e., the forward scanning control circuit 10-1 is turned off and the reverse scanning control circuit 10-2 is turned on by the signal input to the first forward and reverse scanning control terminal GSD_FW and the second forward and reverse scanning control terminal GSD_BW). In an exemplary embodiment, the forward and reverse scanning control circuits may be transmission gates.

[0252] In an exemplary embodiment, FIG18 is a diagram illustrating the operating principle of a shift register circuit according to an exemplary embodiment of the present disclosure. The shift register circuit may be composed of a flip-flop (D Flip Flop) as shown in FIG19 . The flip-flop (which may be a D flip-flop) may include nine parts, namely three transmission gates (TG), four inverters (INVX), and two NAND gates (NAND). The inverters may also be referred to as NOT gates. As shown in FIG19 , the flip-flop may include a second transmission gate 202, a third transmission gate 203, a fourth transmission gate 204, a sixth NAND gate 306, a seventh NAND gate 307, a twelfth inverter 412, a thirteenth inverter 413, a fourteenth inverter 414, and a fifteenth inverter 415.

[0253] In an exemplary embodiment, an input terminal of the twelfth inverter 412 is connected to the clock signal terminal IN_CK of the shift register circuit, and an output terminal of the twelfth inverter 412 is connected to the first node CK_. An input terminal of the thirteenth inverter 413 is connected to the first node CK_, and an output terminal of the thirteenth inverter 413 is connected to the second node CK'. A first terminal of the second transmission gate 202 is connected to the input terminal IN_D of the shift register circuit, a second terminal of the second transmission gate 202 is connected to the output terminal of the fourteenth inverter 414 and the first input terminal of the sixth NAND gate 306, respectively, a high-level active enable terminal of the second transmission gate 202 is connected to the first node CK_, and a low-level active enable terminal of the second transmission gate 202 is connected to the second node CK'. A second input terminal of the sixth NAND gate 306 is connected to the reset terminal RN of the shift register circuit. An output terminal of the sixth NAND gate 306 is connected to the input terminal of the fourteenth inverter 414 and the first terminal of the third transmission gate 203, respectively. An active-high enable terminal of the fourteenth inverter 414 is connected to the second node CK′, and an active-low enable terminal of the fourteenth inverter 414 is connected to the first node CK_. A second terminal of the third transmission gate 203 is connected to the input terminal of the fifteenth inverter 415 and the first terminal of the fourth transmission gate 204, respectively. An active-high enable terminal of the third transmission gate 203 is connected to the second node CK′, and an active-low enable terminal of the third transmission gate 203 is connected to the first node CK_. The output end of the fifteenth inverter 415 is connected to the first input end of the seventh NAND gate 307 and the first output end OUT_Q of the shift register circuit, the second end of the fourth transmission gate 204 is respectively connected to the output end of the seventh NAND gate 307 and the second output end OUT_Q_ of the shift register circuit, the high-level effective enable end of the fourth transmission gate 204 is connected to the first node CK_, the low-level effective enable end of the fourth transmission gate 204 is connected to the second node CK', and the second input end of the seventh NAND gate 307 is connected to the reset end RN of the trigger.

[0254] In an exemplary embodiment, the trigger is active on a rising edge. With each rising edge, the output maintains the state of the previous stage input to the input terminal IN_D. RN is the reset signal terminal (or initialization signal terminal). When it is high, the shift register circuit is active. FIG20 shows an operational timing diagram of the trigger shown in FIG19 . In FIG20 , the horizontal axis represents time in microseconds, and the vertical axis represents voltage in volts (V). The operation of the trigger may include the first stage p1 to the sixth stage p6 (the signal input to the initialization signal terminal RN is high during the first stage p1 to the ninth stage p9):

[0255] Phase 1 p1: The input signal at the clock signal terminal CK of the flip-flop is low, the input signal D at the input terminal IN_D of the flip-flop is low, the first node CK_ is high, the second node CK' is low, the second transmission gate 202 and the fourth transmission gate 204 are turned on, and the third transmission gate 203 is turned off. Since the second transmission gate 202 is turned on, the low-level signal at the input terminal IN_D is transmitted to the node A via the second transmission gate 202. Node A (which can be called the third node of the flip-flop) is low, and node D_ (which can be called the fourth node of the flip-flop) is high. Since the third transmission gate 203 is turned off, the node D_' (which can be called the fifth node of the flip-flop) remains high. The output signal Q at the first output terminal OUT_Q of the flip-flop is low. Since the fourth transmission gate 204 is turned on, the high level of node D_' is transmitted to the second output terminal OUT_Q_ of the flip-flop via the fourth transmission gate 204. The output signal Q_ at the second output terminal OUT_Q_ of the flip-flop is high. In the second stage p2, the input signal of the clock signal terminal CK of the trigger is high, the input signal of the input terminal IN_D of the trigger is low, the first node CK_ is low, the second node CK' is high, the second transmission gate 202 and the fourth transmission gate 204 are disconnected, and the third transmission gate 203 is turned on. Since the second transmission gate 202 is disconnected, the low-level signal of the input terminal D cannot be transmitted to the node A through the second transmission gate 202. Node A maintains the low level of the previous stage, and node D_ maintains the high level of the previous stage. Since the third transmission gate 203 is turned on, node The high-level signal of D is transmitted to the node D_' via the third transmission gate 203. The node D_' is at a high level, and the output signal Q of the first output terminal OUT_Q of the trigger is at a low level. Since the fourth transmission gate 204 is disconnected, the high level of the node D_' cannot be transmitted to the second output terminal OUT_Q_ of the trigger via the fourth transmission gate 204. The low level of the first output terminal OUT_Q of the trigger and the high level of the initial signal terminal RN are NANDed by the seventh NAND gate 307 to obtain a high level. The output signal Q_ of the second output terminal OUT_Q_ of the trigger is at a high level.

[0256] The third stage p3: The working sequence is the same as the first stage p1 and will not be repeated here.

[0257] Phase 4 p4: The input signals of the clock signal terminal CK and the input signal of the input terminal IN_D of the trigger are both high, the first node CK_ is low, the second node CK' is high, the second transmission gate 202 and the fourth transmission gate 204 are disconnected, and the third transmission gate 203 is turned on. Since the second transmission gate 202 is disconnected, the high-level signal D of the input terminal IN_D cannot be transmitted to the node A through the second transmission gate 202. Node A maintains the low level of the previous phase, and node D_ maintains the high level of the previous phase. Since the third transmission gate 203 is turned on, the high level of node D The high-level signal is transmitted to the node D_' via the third transmission gate 203. The node D_' is at a high level, and the output signal Q of the first output terminal OUT_Q of the trigger is at a low level. Since the fourth transmission gate 204 is disconnected, the high level of the node D_' cannot be transmitted to the second output terminal OUT_Q_ of the trigger via the fourth transmission gate 204. The low level of the first output terminal OUT_Q of the trigger and the high level of the initial signal terminal RN are NANDed by the seventh NAND gate 307 to obtain a high level. The output signal Q_ of the second output terminal OUT_Q_ of the trigger is at a high level.

[0258] Fifth stage p5: The input signal at the clock signal terminal CK of the trigger is low, the input signal at the input terminal IN_D of the trigger is high, the first node CK_ is high, the second node CK' is low, the second transmission gate 202 and the fourth transmission gate 204 are turned on, and the third transmission gate 203 is turned off. Since the second transmission gate 202 is turned on, the high-level signal D at the input terminal IN_D is transmitted to the node A via the second transmission gate 202. Node A is high, and node D_ becomes low. Since the third transmission gate 203 is turned off, node D_' remains high. The output signal Q at the first output terminal OUT_Q of the trigger is low. Since the fourth transmission gate 204 is turned on, the high level of node D_' is transmitted to the second output terminal OUT_Q_ of the trigger via the fourth transmission gate 204. The output signal Q_ at the second output terminal OUT_Q_ of the trigger is high.

[0259] Phase 6 p6: The input signal of the clock signal terminal CK of the flip-flop and the input signal D of the input terminal OUT_D are both high, the first node CK_ is low, the second node CK' is high, the second transmission gate 202 and the fourth transmission gate 204 are disconnected, and the third transmission gate 203 is turned on. Since the second transmission gate 202 is disconnected, the high-level signal of the input terminal IN_D cannot be transmitted to the node A through the second transmission gate 202. Node A maintains the high level of the previous phase, and node D_ maintains the low level of the previous phase. Since the third transmission gate 203 is turned on, node D_ The low-level signal of the trigger is transmitted to the node D_' via the third transmission gate 203. The node D_' is at a low level, and the output signal Q of the first output terminal OUT_Q of the trigger is at a high level. Since the fourth transmission gate 204 is disconnected, the low level of the node D_' cannot be transmitted to the second output terminal OUT_Q_ of the trigger via the fourth transmission gate 204. The high level of the first output terminal OUT_Q of the trigger and the high level of the initial signal terminal RN are obtained by the NAND operation of the seventh NAND gate 307 to obtain a low level. The output signal Q_ of the second output terminal OUT_Q_ of the trigger is at a low level.

[0260] Seventh stage p7: the input signal at the clock signal terminal CK of the trigger is low, the input signal D at the input terminal IN_D of the trigger is high, the first node CK_ is high, the second node CK' is low, the second transmission gate 202 and the fourth transmission gate 204 are turned on, and the third transmission gate 203 is turned off. Since the second transmission gate 202 is turned on, the high-level signal at the input terminal IN_D is transmitted to the node A via the second transmission gate 202. Node A is high, and node D_ is low. Since the third transmission gate 203 is turned off, node D_' remains at its original low level. The output signal Q at the first output terminal OUT_Q of the trigger is high. Since the fourth transmission gate 204 is turned on, the low level at the node D_' is transmitted to the second output terminal OUT_Q_ of the trigger via the fourth transmission gate 204. The output signal Q_ at the second output terminal OUT_Q_ of the trigger is low.

[0261] The eighth stage p8: The working sequence is the same as that of the sixth stage p6, and will not be repeated here.

[0262] Ninth stage p9: the input signal of the clock signal terminal CK of the trigger is low, the input signal D of the input terminal IN_D of the trigger is low, the first node CK_ is high, the second node CK' is low, the second transmission gate 202 and the fourth transmission gate 204 are turned on, and the third transmission gate 203 is turned off. Since the second transmission gate 202 is turned on, the low-level signal at the input terminal IN_D is transmitted to the node A via the second transmission gate 202. Node A is low, and node D_ is high. Since the third transmission gate 203 is turned off, the node D_' maintains its original low level. The output signal Q of the first output terminal OUT_Q of the trigger is high. Since the fourth transmission gate 204 is turned on, the low level of the node D_' is transmitted to the second output terminal OUT_Q_ of the trigger via the fourth transmission gate 204. The output signal Q_ of the second output terminal OUT_Q_ of the trigger is low.

[0263] Combining the first stage p1 to the ninth stage p9, the working principle of the trigger is:

[0264] (1) When the input signal of the clock signal terminal CK of the trigger is at a low level and the input signal D of the input terminal IN_D of the trigger is at a low level, the second transmission gate 202 is turned on, the third transmission gate 203 is turned off, and the fourth transmission gate 204 is turned on. The node A is a low level signal, the node D_ is a high level signal, the output signal Q of the first output terminal OUT_Q of the trigger maintains the original level signal (for example, a low level), and the output signal Q_ of the second output terminal OIT_Q_ of the trigger maintains the original level signal (for example, a high level).

[0265] (2) When the input signal of the clock signal terminal CK of the trigger is at a high level and the input signal D of the input terminal IN_D of the trigger is at a low level, the second transmission gate 202 is disconnected, the third transmission gate 203 is turned on, and the fourth transmission gate 204 is disconnected. Node A and node D_ maintain their original potentials. When node A is originally a low-level signal and node D_ is originally a high-level signal, the output of the first output terminal OUT_Q of the trigger is low-level, and the output of the second output terminal OUT_Q_ of the trigger is high-level; when node A is originally a high-level signal and node D_ is originally a low-level signal, the output signal Q of the first output terminal OUT_Q of the trigger is high-level, and the output signal Q_ of the second output terminal OUT_Q_ of the trigger is low-level.

[0266] (3) When the input signal of the clock signal terminal CK of the trigger is at a low level and the input signal of the input terminal IN_D of the trigger is at a high level, the second transmission gate 202 is turned on, the third transmission gate 203 is turned off, and the fourth transmission gate 204 is turned on. Node A is a high-level signal, and node D_ is a low-level signal. The signal after the third transmission gate 203 is latched (i.e., the signal from node D_' to the first output terminal OUT_Q and the second output terminal OUT_Q_ is latched), and the output is maintained (i.e., the output signal Q of the first output terminal OUT_Q of the trigger and the output signal Q_ of the second output terminal OUT_Q_ of the trigger maintain their original levels);

[0267] (4) When the input signal of the clock signal terminal CK of the trigger is at a high level and the input signal of the input terminal IN_D of the trigger is at a high level, the second transmission gate 202 is disconnected, the third transmission gate 203 is turned on, and the fourth transmission gate 204 is disconnected. Node A and node D_ maintain their original potentials. When node A is originally a low-level signal and node D_ is originally a high-level signal, the output of the first output terminal OUT_Q of the trigger is low-level, and the output of the second output terminal OUT_Q_ of the trigger is high-level; when node A is originally a high-level signal and node D_ is originally a low-level signal, the output signal Q of the first output terminal OUT_Q of the trigger is high-level, and the output signal Q_ of the second output terminal OUT_Q_ of the trigger is low-level.

[0268] FIG21 is an equivalent circuit diagram of a trigger according to an exemplary embodiment of the present disclosure. As shown in FIG8 , the trigger of the gate drive circuit in the display substrate of the present embodiment can include 24 transistors. The second transmission gate 202, the third transmission gate 203, the fourth transmission gate 204, the twelfth inverter 412, the thirteenth inverter 413, and the fifteenth inverter 415 each include one P-type transistor and one N-type transistor, and the sixth NAND gate 306, the seventh NAND gate 307, and the fourteenth inverter 414 each include two P-type transistors and two N-type transistors.

[0269] In an exemplary embodiment, the second transmission gate 202, the sixth NAND gate 306, the fourteenth inverter 414, the third transmission gate 203, the fourth transmission gate 204, the seventh NAND gate 307, the fifteenth inverter 415, the thirteenth inverter 413 and the twelfth inverter 412 can be arranged in sequence along the first direction X (the direction close to the display area).

[0270] In the exemplary embodiment, the eighty-first P-type transistor P81 and the eighty-first N-type transistor N81 constitute the second transmission gate 202. The gate electrode of the eighty-first P-type transistor P81 is respectively connected to the gate electrode of the eighty-fifth N-type transistor N85, the gate electrode of the eighty-sixth N-type transistor N86, the gate electrode of the eighty-seventh P-type transistor P87, the second electrode of the ninety-first P-type transistor P91, and the second electrode of the ninety-first N-type transistor N91, and the gate electrode of the eighty-first N-type transistor N81 is respectively connected to the gate electrode of the eighty-fifth P-type transistor P85, the gate electrode of the eighty-sixth P-type transistor P86, the gate electrode of the eighty-seventh N-type transistor N87, the gate electrode of the ninety-first P-type transistor P91, the gate electrode of the ninety-first N-type transistor N91. The gate electrode of the ninety-second P-type transistor P82, the gate electrode of the eighty-second N-type transistor N82, the second electrode of the eighty-fifth P-type transistor P85 and the second electrode of the eighty-fifth N-type transistor N85 are connected respectively.

[0271] In the exemplary embodiment, the eighty-second P-type transistor P82, the eighty-third P-type transistor P83, the eighty-second N-type transistor N82, and the eighty-third N-type transistor N83 constitute a sixth NAND gate 306. The gate electrode of the eighty-second P-type transistor P82 and the gate electrode of the eighty-second N-type transistor N82 are connected to each other, and are respectively connected to the second electrode of the eighty-first P-type transistor P81, the second electrode of the eighty-first N-type transistor N81, the second electrode of the eighty-fifth P-type transistor P85, and the second electrode of the eighty-fifth N-type transistor N85. The gate electrode of the eighty-third P-type transistor P83 and the gate electrode of the eighty-third N-type transistor N83 are connected to each other and to the reset terminal RN. The first electrode of the eighty-second P-type transistor P82 and the first electrode of the eighty-third P-type transistor P83 are both connected to the first electrode. The source line VDD is connected, the second electrode of the eighty-second P-type transistor P82 and the second electrode of the eighty-third P-type transistor P83 are connected to each other, and are respectively connected to the second electrode of the eighty-second N-type transistor N82, the gate electrode of the eighty-fourth P-type transistor P84, the gate electrode of the eighty-fourth N-type transistor N84, the first electrode of the eighty-sixth P-type transistor P86 and the first electrode of the eighty-sixth N-type transistor N86, the first electrode of the eighty-third N-type transistor N83 is connected to the ground line GND, and the second electrode of the eighty-third N-type transistor N83 is connected to the first electrode of the eighty-second N-type transistor N82.

[0272] In an exemplary embodiment, the eighty-fourth P-type transistor P84 , the eighty-fifth P-type transistor P85 , the eighty-fourth N-type transistor N84 , and the eighty-fifth N-type transistor N85 constitute the fourteenth inverter 414 . The gate electrode of the eighty-fourth P-type transistor P84 and the gate electrode of the eighty-fourth N-type transistor N84 are connected to each other, and are respectively connected to the second electrode of the eighty-second P-type transistor P82, the second electrode of the eighty-second N-type transistor N82, the second electrode of the eighty-third P-type transistor P83, the first electrode of the eighty-sixth P-type transistor P86, and the first electrode of the eighty-sixth N-type transistor N86. The gate electrode of the eighty-fifth P-type transistor P85 is respectively connected to the gate electrode of the eighty-first N-type transistor N81, the gate electrode of the eighty-sixth P-type transistor P86, the gate electrode of the eighty-seventh N-type transistor N87, the gate electrode of the ninety-first P-type transistor P91, the gate electrode of the ninety-first N-type transistor N91, the second electrode of the ninety-second P-type transistor P92, and the second electrode of the ninety-second N-type transistor N92. The gate electrode of the eighty-fifth N-type transistor N85 is respectively connected to the gate electrode of the eighty-first P-type transistor P81, The gate electrode of the eighty-sixth N-type transistor N86, the gate electrode of the eighty-seventh P-type transistor P87, the second electrode of the ninety-first P-type transistor P91 and the second electrode of the ninety-first N-type transistor N91 are connected, the first electrode of the eighty-fourth P-type transistor P84 is connected to the first power supply line VDD, the second electrode of the eighty-fourth P-type transistor P84 is connected to the first electrode of the eighty-fifth P-type transistor P85, the first electrode of the eighty-fourth N-type transistor N84 is connected to the ground line GND, the second electrode of the eighty-fourth N-type transistor N84 is connected to the first electrode of the eighty-fifth N-type transistor N85, the second electrode of the eighty-fifth P-type transistor P85 and the second electrode of the eighty-fifth N-type transistor N85 are connected to each other, and are respectively connected to the second electrode of the eighty-first P-type transistor P81, the second electrode of the eighty-first N-type transistor N81, the gate electrode of the eighty-second P-type transistor P82 and the gate electrode of the eighty-second N-type transistor N82.

[0273] In the exemplary embodiment, the eighty-sixth P-type transistor P86 and the eighty-sixth N-type transistor N86 constitute the third transmission gate 203. The gate electrode of the eighty-sixth P-type transistor P86 is respectively connected to the gate electrode of the eighty-first N-type transistor N81, the gate electrode of the eighty-fifth P-type transistor P85, the gate electrode of the eighty-seventh N-type transistor N87, the gate electrode of the ninety-first P-type transistor P91, the gate electrode of the ninety-first N-type transistor N91, the second electrode of the ninety-second P-type transistor P92, and the second electrode of the ninety-second N-type transistor N92, and the gate electrode of the eighty-sixth N-type transistor N86 is respectively connected to the gate electrode of the eighty-first P-type transistor P81, the gate electrode of the eighty-fifth N-type transistor N85, the gate electrode of the eighty-seventh P-type transistor P87, the second electrode of the ninety-first P-type transistor P91, and the second electrode of the ninety-first N-type transistor N91. The two electrodes are connected, the first electrode of the eighty-sixth P-type transistor P86 and the first electrode of the eighty-sixth N-type transistor N86 are connected to each other, and are respectively connected to the second electrode of the eighty-second P-type transistor P82, the second electrode of the eighty-third P-type transistor P83, the second electrode of the eighty-second N-type transistor N82, the gate electrode of the eighty-fourth P-type transistor P84 and the gate electrode of the eighty-fourth N-type transistor N84, the second electrode of the eighty-sixth P-type transistor P86 and the second electrode of the eighty-sixth N-type transistor N86 are connected to each other, and are respectively connected to the first electrode of the eighty-seventh P-type transistor P87, the first electrode of the eighty-seventh N-type transistor N87, the gate electrode of the ninetieth P-type transistor P90 and the gate electrode of the ninetieth N-type transistor N90.

[0274] In the exemplary embodiment, the eighty-seventh P-type transistor P87 and the eighty-seventh N-type transistor N87 constitute the fourth transmission gate 204. The gate electrode of the eighty-seventh P-type transistor P87 is respectively connected to the gate electrode of the eighty-first P-type transistor P81, the gate electrode of the eighty-fifth N-type transistor N85, the gate electrode of the eighty-sixth N-type transistor N86, the second electrode of the ninety-first P-type transistor P91, and the second electrode of the ninety-first N-type transistor N91, and the gate electrode of the eighty-seventh N-type transistor N87 is respectively connected to the gate electrode of the eighty-first N-type transistor N81, the gate electrode of the eighty-fifth P-type transistor P85, the gate electrode of the eighty-sixth P-type transistor P86, the gate electrode of the ninety-first P-type transistor P91, the gate electrode of the ninety-first N-type transistor N91, the gate electrode of the ninety-second P-type transistor P92. The second electrode of the eighty-seventh P-type transistor P87 and the second electrode of the ninety-second N-type transistor N92 are connected, the first electrode of the eighty-seventh P-type transistor P87 and the first electrode of the eighty-seventh N-type transistor N87 are connected to each other, and are respectively connected to the second electrode of the eighty-sixth P-type transistor P86, the second electrode of the eighty-sixth N-type transistor N86, the gate electrode of the ninetieth P-type transistor P90 and the gate electrode of the ninetieth N-type transistor N90, the second electrode of the eighty-seventh P-type transistor P87 and the second electrode of the eighty-seventh N-type transistor N87 are connected to each other, and are respectively connected to the second electrode of the eighty-eighth P-type transistor P88, the second electrode of the eighty-ninth P-type transistor P89 and the second electrode of the eighty-ninth N-type transistor N89.

[0275] In an exemplary embodiment, the eighty-eighth P-type transistor P88 , the eighty-ninth P-type transistor P89 , the eighty-eighth N-type transistor N88 , and the eighty-ninth N-type transistor N89 constitute the seventh NAND gate 307 . The gate electrode of the eighty-eighth P-type transistor P88 and the gate electrode of the eighty-eighth N-type transistor N88 are connected to each other and to the reset terminal RN of the shift register circuit. The gate electrode of the eighty-ninth P-type transistor P89 and the gate electrode of the eighty-ninth N-type transistor N89 are connected to each other and to the second electrode of the ninetieth P-type transistor P90 and the second electrode of the ninetieth N-type transistor N90, respectively. The first electrode of the eighty-eighth P-type transistor P88 and the first electrode of the eighty-ninth P-type transistor P89 are both connected to the first power supply line VDD. The second electrode of the eighty-eighth P-type transistor P88 and the second electrode of the eighty-ninth P-type transistor P89 are connected to each other and to the second electrode of the eighty-ninth N-type transistor N89, the second electrode of the eighty-seventh P-type transistor P87 and the second electrode of the eighty-seventh N-type transistor N87, respectively. The first electrode of the eighty-eighth N-type transistor N88 is connected to the ground line GND, and the second electrode of the eighty-eighth N-type transistor N88 is connected to the first electrode of the eighty-ninth N-type transistor N89.

[0276] In the exemplary embodiment, the ninetieth P-type transistor P90 and the ninetieth N-type transistor N90 constitute the fifteenth inverter 415. The gate electrode of the ninetieth P-type transistor P90 and the gate electrode of the ninetieth N-type transistor N90 are connected to each other and are respectively connected to the second electrode of the eighty-sixth P-type transistor P86, the second electrode of the eighty-sixth N-type transistor N86, the first electrode of the eighty-seventh P-type transistor P87, and the first electrode of the eighty-seventh N-type transistor N87. The first electrode of the ninetieth P-type transistor P90 is connected to the first power supply line VDD, the first electrode of the ninetieth N-type transistor N90 is connected to the ground line GND, the second electrode of the ninetieth P-type transistor P90 and the second electrode of the ninetieth N-type transistor N90 are connected to each other and are respectively connected to the gate electrode of the eighty-ninth P-type transistor P89 and the gate electrode of the eighty-ninth N-type transistor N89.

[0277] In the exemplary embodiment, the ninety-first P-type transistor P91 and the ninety-first N-type transistor N91 constitute the thirteenth inverter 413. The gate electrodes of the ninety-first P-type transistor P91 and the ninety-first N-type transistor N91 are connected to each other and to the gate electrodes of the eighty-first N-type transistor N81, the eighty-fifth P-type transistor P85, the eighty-sixth P-type transistor P86, the eighty-seventh N-type transistor N87, the second electrode of the ninety-second P-type transistor P92, and the second electrode of the ninety-second N-type transistor N92, respectively. A first electrode of the ninety-first P-type transistor P91 is connected to the first power supply line VDD, a first electrode of the ninety-first N-type transistor N91 is connected to the ground line GND, and a second electrode of the ninety-first P-type transistor P91 and the second electrode of the ninety-first N-type transistor N91 are connected to each other and to the gate electrodes of the eighty-first P-type transistor P81, the eighty-fifth N-type transistor N85, the eighty-sixth N-type transistor N86, and the eighty-seventh P-type transistor P87, respectively.

[0278] In the exemplary embodiment, the ninety-second P-type transistor P92 and the ninety-second N-type transistor N92 form the twelfth inverter 412. The gate electrode of the ninety-second P-type transistor P92 and the gate electrode of the ninety-second N-type transistor N92 are connected to each other and to the clock signal terminal CK of the shift register circuit. A first electrode of the ninety-second P-type transistor P92 is connected to the first power supply line VDD, a first electrode of the ninety-second N-type transistor N92 is connected to the ground line GND, and a second electrode of the ninety-second P-type transistor P92 and the second electrode of the ninety-second N-type transistor N92 are connected to each other and to the gate electrode of the eighty-first N-type transistor N81, the gate electrode of the eighty-fifth P-type transistor P85, the gate electrode of the eighty-sixth P-type transistor P86, the gate electrode of the eighty-seventh N-type transistor N87, the gate electrode of the ninety-first P-type transistor P91, and the gate electrode of the ninety-first N-type transistor N91, respectively.

[0279] In an exemplary embodiment, the function of the first flip-flop DFF1 is to shift the first signal A_Dn input to the first signal input terminal IN_A_Dn (the shift clock signal is CKV1), the function of the second flip-flop DFF2 is to shift the second signal B_Dn input to the second signal input terminal IN_B_Dn (the shift clock signal is CKV2), the function of the third flip-flop DFF3 is to shift the third signal C_Dn input to the third signal input terminal IN_C_Dn (the shift clock signal is CKV3), and the function of the fourth flip-flop DFF4 is to shift the fourth signal D_Dn input to the fourth signal input terminal IN_D_Dn (the shift clock signal is CKV5), thereby providing an initial signal for the logic operation circuit 200.

[0280] In an exemplary embodiment, as shown in FIG22 , which is a timing diagram of row-by-row shifting of the first signal A_D1 by multiple stages of cascaded first flip-flops DFF1, the first signal A_D1 is input to the input terminal IN_A_D1 of the first-stage first flip-flop DFF1. The rising edge of the first input signal A_Q1_ of the first stage, formed after one clock signal shift (i.e., shifted by the first-stage first flip-flop DFF1), is synchronized with the falling edge of the first input signal A_Q4_ of the fourth stage, formed after four clock signal shifts (i.e., shifted by four stages of first flip-flops DFF1). Similarly, the rising edge of the first input signal A_Qn_ of the nth stage, formed after n clock signal shifts (i.e., shifted by n stages of first flip-flops DFF1), is synchronized with the falling edge of the first input signal A_Qn+4_ of the n+4th stage, formed after n+4 clock signal shifts (i.e., shifted by n+4 stages of first flip-flops DFF1).

[0281] In an exemplary embodiment, as shown in Figures 18 and 22, a first signal A_Dn is an input signal of a first flip-flop DFF1, and a first clock signal CKV1 is a clock signal of the first flip-flop DFF1. The first flip-flop DFF1 is rising-edge triggered, i.e., triggered by the rising edge of the first clock signal CKV1. When the first clock signal CKV1 rises, the first signal A_Dn is outputted at that time. This signal is outputted until the next rising edge of the first clock signal CKV1, at which point the first signal A_Dn is outputted again. Therefore, the first input signal A_Qn_, serving as the output of the first flip-flop DFF1, has a high- and low-level cycle that is an integer multiple of the cycle T1 of the first clock signal CKV1. Furthermore, the high- and low-level cycle of the inverted signal A_Qn of the first input signal A_Qn_ is also an integer multiple of the cycle T1 of the first clock signal CKV1.

[0282] In an exemplary embodiment, the first signal A_D1 received by the first flip-flop DFF1 of the first stage can serve as an initial trigger signal of the multi-stage cascaded first flip-flop DFF1, and the inverted signal A_Q1 of the first input signal A_Q1_ output by the first flip-flop DFF1 of the first stage can serve as an input of the first flip-flop DFF1 of the second stage. And so on, the inverted signal A_Qn of the first input signal A_Qn output by the first flip-flop DFF1 of the nth stage can serve as an input of the first flip-flop DFF1 of the (n+1)th stage.

[0283] In an exemplary embodiment, as shown in FIG23 , which is a timing diagram of row-by-row shifting of the second signal B_D1 by a multi-stage cascade of second flip-flops DFF2, the second signal B_D1 is input to the input terminal IN_B_D1 of the first-stage second flip-flop DFF2. The falling edge of the second input signal B_Q1 of the first stage, formed after one clock signal shift (i.e., shifted by the first-stage second flip-flop DFF2), is synchronized with the rising edge of the second input signal B_Q4_ of the fourth stage, formed after four clock signal shifts (i.e., shifted by four stages of second flip-flops DFF2). Similarly, the falling edge of the second input signal B_Qn_ of the n-th stage, formed after n clock signal shifts (i.e., shifted by n stages of second flip-flops DFF2), is synchronized with the rising edge of the second input signal B_Qn+4_ of the n+4th stage, formed after n+4 clock signal shifts (i.e., shifted by n+4 stages of second flip-flops DFF2).

[0284] In an exemplary embodiment, as shown in Figures 18 and 23, the second signal B_Dn is the input signal of the second flip-flop DFF2, and the second clock signal CKV2 is the clock signal of the second flip-flop DFF2. The second flip-flop DFF2 is rising-edge triggered, that is, triggered by the rising edge of the second clock signal CKV2. When the second clock signal CKV2 rises, the signal output of the second signal B_Dn is taken. Until the next rising edge of the second clock signal CKV2, the signal output of the second signal B_Dn is taken again. Therefore, the second input signal B_Qn serves as the output of the second flip-flop DFF2, and its high and low level periods are integer multiples of the period T2 of the second clock signal CKV2.

[0285] In an exemplary embodiment, the first signal B_D1 received by the second flip-flop DFF2 of the first stage can serve as the initial trigger signal of the multi-stage cascaded second flip-flop DFF2, and the second input signal B_Q1 output by the second flip-flop DFF2 of the first stage can serve as the input of the second flip-flop DFF2 of the second stage, and so on. The second input signal B_Qn output by the second flip-flop DFF2 of the nth stage can serve as the input of the second flip-flop DFF2 of the (n+1)th stage.

[0286] In an exemplary embodiment, as shown in FIG24 , which is a timing diagram of row-by-row shifting of the third signal C_D1 by a multi-stage cascade of third flip-flops DFF2, the third signal C_D1 is input to the input terminal IN_C_D1 of the first-stage third flip-flop DFF3. The falling edge of the third input signal C_Q1 of the first stage, formed after one clock signal shift (i.e., shifted by the first-stage third flip-flop DFF3), is synchronized with the rising edge of the third input signal C_Q4_ of the fourth stage, formed after four clock signal shifts (i.e., shifted by four-stage third flip-flops DFF3). Similarly, the falling edge of the third input signal C_Qn_ of the n-th stage, formed after n clock signal shifts (i.e., shifted by n-stage third flip-flops DFF3), is synchronized with the rising edge of the third input signal C_Qn+4_ of the n+4-th stage, formed after n+4 clock signal shifts (i.e., shifted by n+4-stage third flip-flops DFF3).

[0287] In an exemplary embodiment, as shown in Figures 18 and 24, the third signal C_Dn is the input signal of the third flip-flop DFF3, and the third clock signal CKV3 is the clock signal of the third flip-flop DFF3. The third flip-flop DFF3 is rising-edge triggered, that is, triggered by the rising edge of the third clock signal CKV3. When the third clock signal CKV3 rises, the signal output of the third signal C_Dn is taken at that time. Until the next rising edge of the third clock signal CKV3, the signal output of the third signal C_Dn at that time is taken again. Therefore, the third input signal C_Qn serves as the output of the third flip-flop DFF3, and the period of its high and low levels is an integer multiple of the period T3 of the third clock signal CKV3.

[0288] In an exemplary embodiment, the first signal C_D1 received by the third flip-flop DFF3 of the first stage can serve as an initial trigger signal of the multi-stage cascaded third flip-flop DFF3, the third input signal C_Q1 output by the third flip-flop DFF3 of the first stage can serve as an input of the third flip-flop DFF2 of the second stage, and so on. The third input signal C_Qn output by the third flip-flop DFF3 of the nth stage can serve as an input of the third flip-flop DFF3 of the (n+1)th stage.

[0289] In an exemplary embodiment, the duration of the period T1 of the first clock signal CKV1, the duration of the period T2 of the second clock signal CKV2, and the duration of the period T3 of the third clock signal CKV3 can be consistent. For example, the duration of the period T1 of the first clock signal CKV1, the duration of the period T2 of the second clock signal CKV2, and the duration of the period T3 of the third clock signal CKV3 can be the same, or there can be a certain deviation, but the deviation can be ignored.

[0290] In an exemplary embodiment, as shown in Figure 25, it is a timing diagram of the row-by-row shifting of the fourth signal D_D1 by the multi-stage cascaded fourth flip-flop DFF4. The fourth signal D_D1 is input to the input terminal IN_D_D1 of the first-stage fourth flip-flop DFF4. The rising edge of the first-stage duty ratio control signal D_Q1 formed after one clock signal shift (i.e., shifted by the first-stage fourth flip-flop DFF4) is synchronized with the first rising edge of the fifth clock signal CKV5 when the fourth signal D_D1 is high. Similarly, the rising edge of the n-th stage duty ratio control signal D_Qn formed after n clock signal shifts (i.e., shifted by n-stage fourth flip-flops DFF4) is synchronized with the n-th rising edge of the fifth clock signal CKV5 when the fourth signal D_D1 is high.

[0291] In the exemplary embodiment, as shown in Figures 18 and 25, the fourth signal D_D1 is the input signal of the fourth flip-flop DFF4, and the fifth clock signal CKV5 is the clock signal of the fourth flip-flop DFF4. The fourth flip-flop DFF4 is rising-edge triggered, that is, triggered by the rising edge of the fifth clock signal CKV5. When the fifth clock signal CKV5 rises, the signal output of the fourth signal D_D1 at that time is used. Until the next rising edge of the fifth clock signal CKV5, the signal output of the fourth signal D_D1 at that time is used again.

[0292] In an exemplary embodiment, a first signal A_D1 is shifted through n cascade-connected first flip-flops DFF1 to form an n-th stage first input signal A_Qn_, a second signal B_D1 is shifted through n cascade-connected second flip-flops DFF2 to form an n-th stage second input signal B_Qn, a third signal C_D1 is shifted through n cascade-connected third flip-flops DFF3 to form an n-th stage third input signal C_Qn, and a fourth signal D_D1 is shifted through n cascade-connected fourth flip-flops DFF4 to form an n-th stage duty control signal D_Qn. The n-th stage first input signal A_Qn_, the n-th stage second input signal B_Qn, the n-th stage third input signal C_Qn, and the n-th stage duty control signal D_Qn are input to an n-th stage logic operation circuit, and a target timing is generated by the logic operation circuit. The target timing may include a write switch signal WSn generated by the first operation circuit, a display switch signal DSn generated by the second operation circuit, and a display reset signal AZn generated by the third operation circuit. Among them, under normal working conditions (LF_pulse2=1, EN=1), the n-level write switch signal WSn is obtained by performing a logical operation on the n-level first input signal A_Qn_, the n-level second input signal B_Qn, and the n-level third input signal C_Qn: WSn=B_Qn&C_Qn+A_Qn_+CKV4; the n-level display switch signal DSn is obtained by performing a logical operation on the n-level second input signal B_Qn and the n-level proportion control signal D_Qn: DSn=B_Qn+D_Qn; the n-level display reset signal AZn is obtained by performing a logical operation on the n-level second input signal B_Qn, the n-level third input signal C_Qn, and the n-level proportion control signal D_Qn: AZn=B_Qn+C_Qn+D_Qn.

[0293] In an exemplary embodiment, as shown in FIG26 , when the high level time of the fourth clock signal CKV4 is 0, the n-th level write switch signal WSn is firstly logically ANDed by the n-th level second input signal B_Qn and the n-th level third input signal C_Qn (i.e., B_Qn&C_Qn). The rising edge of the n-th level second input signal B_Qn determines the first time t1, and the falling edge of the n-th level third input signal C_Qn determines the second time t2. The result of the logical AND operation is logically ORed with the n-th level first input signal A_Qn_ (i.e., B_Qn&C_Qn+A_Qn_). The falling edge of the n-th level first input signal A_Qn_ can determine the falling edge time t0 of the first pulse width in the n-th level write switch signal WSn. The rising edge of an input signal A_Qn_ can determine the rising edge time t3 of the second pulse width in the n-level write switch signal WSn. The width and phase of the two pulse width signals in the n-level write switch signal WSn can be controlled by adjusting the pulse width and phase of the n-level first input signal A_Qn_, the n-level second input signal B_Qn, and the n-level third input signal C_Qn. It has flexible adjustability, wherein the pulse width and phase of the n-level first input signal A_Qn_ can be adjusted by the pulse width and phase of the first signal A_D1, the n-level second input signal B_Qn can be adjusted by the pulse width and phase of the second signal B_D1, and the pulse width and phase of the n-level third input signal C_Qn can be adjusted by the pulse width and phase of the third signal C_D1.

[0294] In an exemplary embodiment, as shown in FIGS. 27a and 27b, the rising edge of the second pulse width of the nth-stage write switch signal WSn (i.e., the cut-off moment of the second valid signal) is determined by the rising edge of the nth-stage first input signal A_Qn_, and the falling edge of the first pulse width of the (n + m)th-stage write switch signal WSn+m (i.e., the start moment of the first valid signal) is determined by the falling edge of the (n + m)th-stage first input signal A_Qn+m_, where both m and n are positive integers. Since the (n + m)th-stage first input signal A_Qn+m_ is a signal formed by shifting the mth-stage first input signal A_Qm_ through multiple (m stages) first flip-flops DFF1, the falling edge of the (n + m)th-stage first input signal A_Qn+m_ differs from the rising edge of the nth-stage first input signal A_Qn_ by k periods of the first clock signal CKV1 (k can be an integer, for example, the value of k can be.... -2, -1, 0, 1, 2,....), that is, the time difference between the rising edge of the second pulse width of the nth-stage write switch signal WSn and the falling edge of the first pulse width of the (n + m)th-stage write switch signal WSn+m is k*T (T is the period of the first clock signal CKV). When the width tw1 of the first pulse width of the write switch signal WS (i.e., the pulse width of the first valid signal) plus the width tw2 of the second pulse width (i.e., the pulse width of the second valid signal) is less than the period T1 of the first clock signal CKV1, that is, tw1 + tw2 < T1, it can be ensured that any two write switch signals WS do not overlap at any moment, that is, after any number of shifts of the double pulse width of the write switch signal WS, there will be no situation where the pulse widths of two write switch signals WS overlap at any moment.

[0295] In an exemplary embodiment, in the n-th level write switch signal WSn, the falling edge of the first pulse width (i.e., the start time of the first valid signal) and the rising edge of the second pulse width (i.e., the end time of the second valid signal) differ by S cycles of the first clock signal CKV1 (i.e., the phase difference is S*T), that is, the falling edge and the rising edge of the n-th level first input signal A_Qn_ differ by S cycles of the first clock signal CKV1 (i.e., the pulse width of the valid signal of the n-th level first input signal A_Qn_ is S cycles of the first clock signal CKV1), and the n-th level write The falling edge of the first pulse width in the switch signal WSn (i.e., the starting moment of the first pulse width) and the falling edge of the first pulse width in the n+m-th level write switch signal WSn+m (i.e., the starting moment of the first valid signal) differ by m cycles of the first clock signal CKV1. Then, the rising edge of the second pulse width in the n-th level write switch signal WSn (i.e., the cut-off moment of the second valid signal) and the falling edge of the first pulse width in the n+m-th level write switch signal WSn+m (i.e., the starting moment of the first valid signal) differ by mS cycles of the first clock signal CKV1, i.e., k=mS. As shown in FIG27 , in the n-th level write switch signal WSn, the falling edge of the first pulse width (i.e., the starting moment of the first valid signal) and the rising edge of the second pulse width (i.e., the end moment of the second valid signal) differ by 3 cycles of the first clock signal CKV1, that is, the falling edge and the rising edge of the n-th level first input signal A_Qn_ differ by 3 cycles of the first clock signal CKV1 (that is, the pulse width of the valid signal in the n-th level first input signal A_Qn_ is 3 cycles of the first clock signal CKV1); the rising edge of the second pulse width of the n-th level write switch signal WSn (i.e., the end moment of the second valid signal) differs by -2 cycles from the falling edge of the first pulse width of the n+1-th level write switch signal WSn+1 (i.e., the starting moment of the first valid signal). The period T1 of the first clock signal CKV1 differs from the falling edge of the first pulse width of the n+2-th level write switch signal WSn+2 (i.e., the starting time of the first valid signal) by -1 period T1 of the first clock signal CKV1, differs from the falling edge of the first pulse width of the n+3-th level write switch signal WSn+3 (i.e., the starting time of the first valid signal) by 0 period T1 of the first clock signal CKV1, and differs from the falling edge of the first pulse width of the n+4-th level write switch signal WSn+4 (i.e., the starting time of the first pulse width) by 1 period T1 of the first clock signal CKV1. When tw1+tw2<τ, the valid signal of the n-th level write switch signal WSn will not overlap with the valid signal of the n+m-th level write switch signal WSn+m.

[0296] In an exemplary embodiment, as shown in FIG7 , at least one stage of logic operation circuit 200 may further include a fourth clock signal terminal IN_CKV4. The fourth clock signal terminal IN_CKV4 is configured to receive a fourth clock signal CKV4. Under the control of the fourth clock signal CKV4, the end time of the second valid signal in the write switch signal WSn output by the n-th stage logic operation circuit differs from the start time of the first valid signal in the write switch signal WSn+S output by the n+S-th stage logic operation circuit by a first time interval. The first time interval is the duration of the valid signal in one cycle of the fourth clock signal CKV4. In an exemplary embodiment, the valid signal in one cycle of the fourth clock signal CKV4 may be a high-level signal, but the present disclosure is not limited thereto. For example, the valid signal in one cycle of the fourth clock signal CKV4 may be a low-level signal. In an exemplary embodiment, the falling edge of the fourth clock signal CKV4 can be synchronized with the rising edge of the first clock signal CKV1 (it can be the same time, or there may be an interval, but it can be ignored), and the cycle length of the fourth clock signal CKV4 can be consistent with the cycle length of the first clock signal CKV1 (for example, the cycle length of CKV4 can be the same as the cycle length of CKV1).

[0297] In an exemplary embodiment, as shown in FIG27a, when the time of the high-level signal of the fourth clock signal CKV4 is 0 (the duration of the valid signal in a period T4 of the fourth clock signal CKV4 is 0), that is, the fourth clock signal CKV4 is always at a low level, then the end time of the second valid signal in the write switch signal WSn output by the n-th stage logic operation circuit and the start time of the first valid signal in the write switch signal WSn+S output by the n+S-th stage logic operation circuit can be synchronized (the synchronization can be coincidence, or there can be a certain time interval, which can be ignored compared with the period T1 of the first clock signal CKV1; S can be the number of first clock signals CKV1 contained in the pulse width of the valid signal in the first input signal A_Qn_, for example, the value of S as shown in FIG27a is 3). That is, under the control of the fourth clock signal CKV4, the end time of the second valid signal in the write switch signal WSn output by the n-th level logic operation circuit differs from the start time of the first valid signal in the write switch signal WSn+S output by the n+S-th level logic operation circuit by a first time interval Δt, and the length of the first time interval Δt can be 0.

[0298] In an exemplary embodiment, as shown in FIG27b, when the time Δt of the high-level signal of the fourth clock signal CKV4 is not 0 (the duration of the valid signal in one cycle T4 of the fourth clock signal CKV4 is not 0), the end time of the second valid signal in the write switch signal WSn output by the n-th stage logic operation circuit and the start time of the first valid signal in the write switch signal WSn+S output by the n+S-th stage logic operation circuit can be synchronized (S can be the number of first clock signals CKV1 included in the pulse width of the valid signal in the first input signal A_Qn_, for example, S is 3 as shown in FIG27a), but there is a duration of the first time interval Δt, that is, the end time of the second valid signal in the write switch signal WSn output by the n-th stage logic operation circuit and the time interval between the start time of the first valid signal in the write switch signal WSn+S output by the n+S-th stage logic operation circuit can be controlled by the duration of the high level in one cycle of the fourth clock signal CKV4. That is, under the control of the fourth clock signal CKV4, the end time of the second valid signal in the write switch signal WSn output by the n-th level logic operation circuit differs from the start time of the write switch signal WSn+S output by the n+S-th level logic operation circuit by a first time interval Δt, and the length of the first time interval Δt may not be 0.

[0299] In an exemplary embodiment, as shown in FIG27b , one light-emitting cycle may include S cycles of the fourth clock signal CKV4 (for example, S is 3). In one light-emitting cycle corresponding to the n-th stage logic operation circuit, the end time of the second valid signal in the write switch signal WSn output by the n-th stage logic operation circuit may be synchronized with the S-th rising edge of the fourth clock signal CKV4 received by the n-th stage logic operation circuit (they may coincide in time, or there may be a time interval, but the time interval is negligible compared to Δt). The start time of the first valid signal in the write switch signal WSn+S output by the n+S-th stage logic operation circuit may be synchronized with the S-th falling edge of the fourth clock signal CKV4 received by the n+S-th stage logic operation circuit (they may coincide in time, or there may be a time interval, but the time interval is negligible compared to Δt). In other words, the end time of the second valid signal in the write switch signal WSn output by the n-th level logic operation circuit, that is, the end time of a light-emitting cycle of the n-th level logic operation circuit, can be synchronized with the S-th rising edge of the fourth clock signal CKV4 received by the n-th level logic operation circuit; the start time of the first valid signal in the write switch signal WSn+S output by the n+S-th level logic operation circuit, that is, the start time of a light-emitting cycle of the n+S-th level logic operation circuit, can be synchronized with the S-th falling edge of the fourth clock signal CKV4 received by the n+S-th level logic operation circuit (the S-th falling edge refers to the S-th falling edge of the fourth clock signal CKV4 in a light-emitting cycle of the n-th level logic operation circuit, that is, the first falling edge of the fourth clock signal CKV4 in a light-emitting cycle of the n+S-th level logic operation circuit).

[0300] In an exemplary embodiment, when the n-th level write switch signal WSn with a double pulse width (double pulse width refers to the pulse width of two valid signals) is generated by the logical expression WSn=B_Qn&C_Qn+A_Qn_+CKV4, within one light-emitting cycle (i.e., from the falling edge of the first valid signal to the rising edge of the second valid signal in the n-th level write switch signal WSn, or within the light-emitting period of driving a row of pixels, for example, the first stage A1 to the fourth stage A4 in Figures 5a and 5b can be one light-emitting cycle), the n-th level first signal A_Dn_, the n-th level second signal B_Dn, and the n-th level third signal C_Dn need to satisfy the following phase relationship:

[0301] As shown in Figure 22, in at least one stage of shift register circuit 100, the phase relationship between the first signal A_Dn received by each stage of shift register circuit 100 in one light-emitting cycle (the first stage A1 to the fourth stage A4 in Figure 5a and Figure 5b can be one light-emitting cycle) and the first clock signal CKV1 may include: the rising edge time tA1 of the first signal A_Dn is not later than the first rising edge time t11 of the first clock signal CKV1; the falling edge time tA2 of the first signal A_Dn is not earlier than the time t13 of the Sth rising edge of the first clock signal CKV, and earlier than the time t14 of the S+1th rising edge of the first clock signal. For example, a rising edge tA1 of the n-th level first signal A_Dn_ differs from the first rising edge t11 of the first clock signal CKV1 by a first time difference Δt1 (i.e., Δt1=t11-tA1), and Δt1>0, that is, the rising edge time tA1 of the n-th level first signal A_Dn_ is earlier than the first rising edge time t11 of the first clock signal CKV1; the falling edge time tA2 of the n-th level first signal A_Dn_ is earlier than the fourth rising edge time t14 of the first clock signal CKV1 and later than the third rising edge time t13 of the first clock signal CKV1;

[0302] As shown in Figure 23, the cycle length (T2) of the second clock signal CKV2 can be consistent with the cycle length (T1) of the first clock signal CKV1. In at least one stage of the shift register circuit 100, the phase relationship between the second signal B_Dn received by each stage of the shift register circuit 100 in one light-emitting cycle (the first stage A1 to the fourth stage A4 in Figure 5a and Figure 5b can be one light-emitting cycle) and the second clock signal CKV2 can include: the rising edge time tB1 of the second signal B_Dn is not later than the first rising edge time t21 of the second clock signal CKV2; the falling edge time tB2 of the second signal B_Dn is not earlier than the time t23 of the Sth rising edge of the second clock signal CKV2, and earlier than the time t24 of the S+1th rising edge of the second clock signal CKV2. For example, the rising edge time tB1 of the n-th level second signal B_Dn differs from the first rising edge time t21 of the second clock signal CKV2 by a second time difference Δt2 (i.e., Δt2=t21-tB1), and Δt2>0, that is, the rising edge time tB1 of the n-th level second signal B_Dn is earlier than the first rising edge time t21 of the second clock signal CKV2; the falling edge time tB2 of the n-th level second signal B_Dn is earlier than the fourth rising edge time t24 of the second clock signal CKV2 and later than the third rising edge time t23 of the second clock signal CKV2;

[0303] As shown in Figure 24, the cycle length (T3) of the third clock signal CKV3 can be consistent with the cycle length (T1) of the first clock signal CKV1. In at least one stage of the shift register circuit 100, the phase relationship between the third signal C_Dn received by each stage of the shift register circuit 100 in one light-emitting cycle (the first stage A1 to the fourth stage A4 in Figure 5a and Figure 5b can be one light-emitting cycle) and the third clock signal CKV3 can include: the rising edge time tC1 of the third signal C_Dn is not later than the first rising edge time t31 of the third clock signal CKV3; the falling edge time tC2 of the third signal C_Dn is not earlier than the time t33 of the Sth rising edge of the third clock signal CKV3, and earlier than the time t34 of the S+1th rising edge of the third clock signal CKV3. For example, the rising edge time tC1 of the n-th level third signal C_Dn is earlier than the first rising edge time t31 of the third clock signal CKV3 by a third time difference Δt3 (i.e., Δt3=t31-tC1), Δt3>0, i.e., the rising edge time tC1 of the n-th level third signal C_Dn is earlier than the first rising edge time t31 of the third clock signal CKV3; the falling edge time tC2 of the n-th level third signal C_Dn is earlier than the fourth rising edge time t34 of the third clock signal CKV3 and later than the third rising edge time t33 of the third clock signal CKV3.

[0304] In an exemplary embodiment, since the inverted signal A_Qn of the first input signal A_Qn_ output by the n-th stage shift register circuit 100 can be used as the first signal A_Dn received by the n+1-th stage shift register circuit 100, the second input signal B_Qn output by the n-th stage shift register circuit 100 can be used as the second signal B_Dn received by the n+1-th stage shift register circuit 100, and the third input signal C_Qn output by the n-th stage shift register circuit 100 can be used as the third signal C_Dn received by the n+1-th stage shift register circuit 100, the first shift register circuit 100 can be adjusted to obtain the first signal A_Dn received by the n+1-th stage shift register circuit 100. The phase relationship between the first signal A_D1 received by the bit register circuit 100 and the first clock signal CKV1 is adjusted, the phase relationship between the second signal B_Dn received by the first pole shift register circuit 100 and the second clock signal CKV2 is adjusted, and the phase relationship between the third signal C_Dn received by the first pole shift register circuit 100 and the third clock signal CKV3 is adjusted, and the pulse width of the valid signal in the first input signal A_Qn_, the pulse width of the valid signal in the second input signal B_Qn, the pulse width of the valid signal in the third input signal C_Qn, and the pulse width of the two valid signals in the write switch signal WSn are adjusted.

[0305] As shown in FIG26 , the phase relationship between the n-th stage first input signal A_Qn_, the n-th stage second input signal B_Qn, and the n-th stage third input signal C_Qn needs to meet the following conditions:

[0306] The falling edge time t1 of the n-th stage first input signal A_Qn_ (i.e., the time when the valid signal in the n-th stage first input signal A_Qn_ starts) is earlier than the rising edge time t2 of the n-th stage second input signal B_Qn (i.e., the time when the valid signal in the n-th stage second input signal B_Qn starts);

[0307] The falling edge time t2 of the n-th stage first input signal A_Qn_ (i.e., the time when the valid signal in the n-th stage first input signal A_Qn_ starts) is later than the rising edge time t0 of the n-th stage third input signal C_Qn (i.e., the time when the valid signal in the n-th stage third input signal C_Qn starts);

[0308] The falling edge time t3 of the third input signal C_Qn of the nth stage (i.e., the end time of the valid signal in the third input signal C_Qn of the nth stage) is earlier than the rising edge time t4 of the first input signal A_Qn_ of the nth stage (i.e., the end time of the valid signal in the first input signal A_Qn_ of the nth stage);

[0309] The rising edge time t4 of the first input signal A_Qn_ of the nth stage is earlier than the falling edge time t5 of the second input signal B_Qn (ie, the end time of the valid signal in the second input signal B_Qn).

[0310] In an exemplary embodiment, as shown in FIG22 , the end time of the valid signal in the first input signal A_Qn_ output by the n-th stage shift register circuit differs from the start time of the valid signal A_Qn+m_ in the first input signal output by the n+m-th stage shift register circuit by mS periods T1 of the first clock signal CKV1, where m is a positive integer; the start time of the valid signal in the first input signal A_Qn_ output by the n-th stage shift register circuit differs from the start time of the valid signal in the first input signal A_Qn_ output by the n+m-th stage shift register circuit by m periods T1 of the first clock signal CKV1.

[0311] In an exemplary embodiment, as shown in FIG18 , FIG27 a , and FIG27 b , the n-th shift register circuit is connected to the n-th logic operation circuit and configured to provide a first input signal A_Qn_ to the n-th logic operation circuit; the n+m-th shift register circuit is connected to the n+m-th logic operation circuit and configured to provide a first input signal A_Qn+m_ to the n+m-th logic operation circuit;

[0312] The n-th level logic operation circuit is configured to generate a write switch signal WSn under the control of the first input signal A_Qn_ output by the n-th level shift register circuit, and the n+m-th level logic operation circuit is configured to generate a write switch signal WSn+m under the control of the first input signal output by the n+m-th level shift register circuit; the end time of the second valid signal in the write switch signal WSn generated by the n-th level logic operation circuit differs from the start time of the first valid signal in the write switch signal WSn+m generated by the n+m-th level logic operation circuit by mS cycles T1 of the first clock signal CKV1; the start time of the first valid signal in the write switch signal WSn generated by the n-th level logic operation circuit differs from the start time of the first valid signal in the write switch signal WSn+m generated by the n+m-th level logic operation circuit by m cycles T1 of the first clock signal CKV1.

[0313] In an exemplary embodiment, the end time of the second valid signal in the write switch signal WSn generated by the n-th stage logic operation circuit differs from the start time of the first valid signal in the write switch signal WSn+m generated by the n+m-th stage logic operation circuit by mS cycles T1 of the first clock signal CKV1. The difference may be exactly mS cycles T1 of the first clock signal CKV1, or there may be a certain deviation. Compared with the cycle T1 of the first clock signal CKV1, the deviation is small and can be ignored. The start time of the first valid signal in the write switch signal WSn generated by the n-th stage logic operation circuit differs from the start time of the first valid signal in the write switch signal WSn+m generated by the n+m-th stage logic operation circuit by m cycles T1 of the first clock signal CKV1. The difference may be exactly m cycles T1 of the first clock signal CKV1, or there may be a certain deviation. Compared with the cycle T1 of the first clock signal CKV1, the deviation is small and can be ignored.

[0314] In an exemplary embodiment, the duration of a cycle of the clock signal CKV1 may be equal to the average display time of one row.

[0315] In an exemplary embodiment, as shown in FIG27 a , the pulse width of the first valid signal of the write switch signal WS output by the logic operation circuit is tw1, and the pulse width of the second valid signal is tw2. When tw1+tw2≤T1, the following three situations may be included according to the value of mS:

[0316] In the case of mS=0, the start time of the first valid signal in the write switch signal WSn+m generated by the n+m-th stage logic operation circuit may coincide with the end time of the second valid signal in the write switch signal WSn generated by the n-th stage logic operation circuit, and the first valid signal in WSn+m and the second valid signal in WSn will not overlap;

[0317] In the case of (Sm)*T1≥1*T1, the start time of the first valid signal in the write switch signal WSn+m generated by the n+m-th stage logic operation circuit is earlier than the end time of the second valid signal in the write switch signal WSn generated by the n-th stage logic operation circuit. Since tw1+tw2≤1*T1, it can be concluded that (Sm)*T1≥1*T1≥tw1+tw2, and the first valid signal in WSn+m and the second valid signal in WSn will not overlap;

[0318] When (Sm)*T1<-1*T1, the start time of the first valid signal in the write switch signal WSn+m generated by the n+m-th level logic operation circuit is later than the end time of the second valid signal in the write switch signal WSn generated by the n-th level logic operation circuit, and there will be no overlap between the first valid signal in WSn+m and the second valid signal in WSn.

[0319] In an exemplary embodiment, as shown in FIG27a , the difference between the start time t1(n) of the first valid signal in the write switch signal WSn output by the n-th stage logic operation circuit 200 and the start time t1(n+1) of the first valid signal in the write switch signal WSn+1 output by the n+1-th stage logic operation circuit 200 is greater than or equal to the pulse width tw2 of the second valid signal, where n is a positive integer. In other words, the interval between the start times of the write switch signals output by two adjacent stages of the logic operation circuits is greater than or equal to the pulse width tw2 of the second valid signal. This ensures that the first valid signal in the write switch signal output by one of the first stages of the logic operation circuits does not overlap with the second valid signal in the write switch signal output by any other first-stage logic operation circuits, thereby preventing the pixel driver circuit from writing data signals to the wrong row when driving the light-emitting device EL to emit light.

[0320] In an exemplary embodiment, since the difference between the start time t1(n) of the first valid signal in the write switch signal WSn output by the n-th level logic operation circuit 200 and the start time t1(n+1) of the first valid signal in the write switch signal WSn+1 output by the n+1-th level logic operation circuit 200 is greater than or equal to the pulse width tw2 of the second valid signal, it can be inferred that the difference between the start time t1(n) of the first valid signal in the write switch signal WSn output by the n-th level logic operation circuit 200 and the start time t1(n+m) of the first valid signal in the write switch signal WSn+m output by the n+m-th level logic operation circuit 200 is greater than m*tw2, where m is a positive integer.

[0321] In an exemplary embodiment, since the difference between the start time of the first valid signal in WSn and the start time of the first valid signal in Wn+1 (one cycle T1 of CKV1) is greater than the pulse width tw2 of the second valid signal in the write switch signal, taking the kth row and the mth row as an example, k and m are both positive integers, and m is greater than k, the difference between the start time of the first valid signal in WSk and the start time of the first valid signal in WSm is greater than tw2, that is, (mk)*T1≥tw2, so that the shift interval of the first valid signal in the write switch signal WS in two adjacent rows is greater than tw2.

[0322] As shown in FIG27c , the start time of the first valid signal in the write switch signal WSm output by the m-th stage logic operation circuit is earlier than the end time of the second valid signal in the write switch signal WSk output by the k-th stage logic operation circuit, which may include at least the following two situations:

[0323] In the case of two adjacent rows, that is, mk=1, T1≥tw2, it is necessary to satisfy T1≥tw1 and T1≥tw1+tw2, so that the first valid signal in WSm and the second valid signal in WSk do not overlap;

[0324] In the case of non-adjacent rows, (mk)*T1+tw1≤S*T1-tw2, and it can be concluded that (S-m+k)*T1≥tw1+tw2.

[0325] As shown in FIG27 d , in the case where the start time of the first valid signal in the write switch signal WSm output by the m-th stage logic operation circuit is later than the end time of the second valid signal in the write switch signal WSk output by the k-th stage logic operation circuit, the following conditions must be met:

[0326] (mk)*T1≥S*T1, but the start time of the first valid signal in WSm is not later than the start time of the second valid signal in WSk+1, that is, (mk)*T1+tw1≤(S+1)*T1-tw2, and it can be concluded that (S-m+k+1)*T1≥tw1+tw2.

[0327] In an exemplary embodiment, the difference between the start time t1(n) of the first valid signal in the write switch signal WSn output by the n-th stage logic operation circuit 200 and the start time t1(n+1) of the first valid signal in the write switch signal WSn+1 output by the n+1-th stage logic operation circuit 200 may be equal to the period T1 of the first clock signal CKV1. In other words, the pulse width tw2 of the second valid signal is less than or equal to the period T1 of the first clock signal CKV1.

[0328] In an exemplary embodiment, as shown in FIG28 , the gate drive circuit may further include a first test circuit, which may be configured to test the write switch signal output by the first logic circuit. The operating principle diagram of the first test circuit is shown in FIG28 . The first test circuit may include two inverters, and the input of the first test circuit may be electrically connected to the output OUT_WS of the first operation circuit (i.e., the write switch signal terminal OUT_WSn of the logic operation circuit). As shown in FIG28 , the first test circuit may include a thirteenth inverter 413 and a fourteenth inverter 414. The input of the thirteenth inverter 413 is connected to the output OUT_DS of the second operation circuit, and the output of the thirteenth inverter 413 is connected to the input of the fourteenth inverter 414. The output of the fourteenth inverter 414 may serve as the output Test_WS of the first test circuit (i.e., the test terminal for the write switch signal DSn of the gate drive circuit).

[0329] In an exemplary embodiment, a first test circuit can detect whether a write switch signal DSn outputted from an output terminal OUT_WS of the first arithmetic circuit is consistent with a target timing. If the write switch signal WSn detected at the output terminal Test_WS of the first test circuit is inconsistent with the target timing, it indicates that an abnormality has occurred in the write switch signal WSn before the write switch signal WSn enters the level shifter 300 and the line driver enhancement circuit 400. Therefore, it can be inferred that an operational abnormality of the first arithmetic circuit has caused the write switch signal WSn to be inconsistent with the target timing. If the write switch signal WSn detected at the output terminal Test_WS of the first test circuit is consistent with the target timing, it indicates that an abnormality has occurred in the write switch signal WSn after the write switch signal WSn enters the level shifter 300 and the line driver enhancement circuit 400. Therefore, it can be inferred that the first arithmetic circuit is operating normally. Therefore, the write switch signal WSn outputted by the first arithmetic circuit can be tested at the output terminal Test_WS of the first test circuit to determine whether the first arithmetic circuit is operating normally. In an exemplary embodiment, the output terminal Test_WS of the first test circuit can be brought out through a pad around the display area. During testing, the signal input terminal of the oscilloscope can be electrically connected to the pad of the output terminal Test_WS of the first test circuit. The waveform output by the output terminal Test_WS of the first test circuit is obtained through the oscilloscope, and the waveform output by the output terminal Test_WS of the first test circuit is compared with the waveform of the target timing to see whether they are consistent. If they are consistent, it indicates that the first operation circuit is working normally, and if they are inconsistent, it indicates that the first operation circuit is working abnormally.

[0330] In an exemplary embodiment, as shown in FIG29 , the gate drive circuit may further include a second test circuit, which may be configured to test the display switch signal output by the second logic circuit. The operating principle diagram of the second test circuit is shown in FIG29 . The second test circuit may include two inverters, and the input of the second test circuit may be electrically connected to the output OUT_DS of the second operation circuit (i.e., the display switch signal terminal OUT_DSn of the logic operation circuit). As shown in FIG29 , the second test circuit may include a fifteenth inverter 415 and a sixteenth inverter 416. The input of the fifteenth inverter 415 is connected to the output OUT_DS of the second operation circuit, and the output of the fifteenth inverter 415 is connected to the input of the sixteenth inverter 416. The output of the sixteenth inverter 416 may serve as the output Test_DS of the second test circuit (i.e., the test terminal for the display switch signal DSn of the gate drive circuit).

[0331] In an exemplary embodiment, a second test circuit can detect whether the display switching signal DSn outputted from the output terminal OUT_DS of the second arithmetic circuit is consistent with a target timing. If the display switching signal DSn detected at the output terminal Test_DS of the second test circuit is inconsistent with the target timing, it indicates that the display switching signal DSn has already experienced an abnormality before entering the level shifter circuit 300 and the line driver enhancement circuit 400. Therefore, it can be inferred that the abnormal operation of the second arithmetic circuit has caused the display switching signal DSn to be inconsistent with the target timing. If the display switching signal DSn detected at the output terminal Test_DS of the second test circuit is consistent with the target timing, it indicates that the display switching signal DSn has experienced an abnormality after entering the level shifter circuit 300 and the line driver enhancement circuit 400. Therefore, it can be inferred that the second arithmetic circuit is operating normally. Therefore, the display switching signal DSn outputted by the second arithmetic circuit can be tested at the output terminal Test_DS of the second test circuit to determine whether the second arithmetic circuit is operating normally. In an exemplary embodiment, the output terminal Test_DS of the second test circuit can be brought out through a pad around the display area. During testing, the signal input terminal of the oscilloscope can be electrically connected to the pad of the output terminal Test_DS of the second test circuit. The waveform output by the output terminal Test_DS of the first test circuit is obtained through the oscilloscope, and the waveform output by the output terminal Test_DS of the second test circuit is compared with the waveform of the target timing to see whether they are consistent. If they are consistent, it indicates that the second operation circuit is working normally, and if they are inconsistent, it indicates that the second operation circuit is working abnormally.

[0332] In an exemplary embodiment, as shown in FIG30 , the gate drive circuit may further include a third test circuit, which may be configured to test the display reset signal output by the third logic circuit. The operating principle diagram of the third test circuit is shown in FIG30 . The third test circuit may include two inverters, and the input of the third test circuit may be electrically connected to the output OUT_AZ of the third operation circuit (i.e., the display reset signal terminal OUT_AZn of the logic operation circuit). As shown in FIG30 , the third test circuit may include a seventeenth inverter 417 and an eighteenth inverter 418. The input of the seventeenth inverter 417 is connected to the output OUT_AZ of the third operation circuit, and the output of the seventeenth inverter 417 is connected to the input of the eighteenth inverter 418. The output of the eighteenth inverter 418 may serve as the output Test_AZ of the third test circuit (i.e., the test terminal for the display reset signal AZn of the gate drive circuit).

[0333] In an exemplary embodiment, a third test circuit can detect whether the display reset signal AZn outputted from the output terminal OUT_AZ of the third arithmetic circuit is consistent with a target timing. If the display reset signal AZn detected at the output terminal Test_AZ of the third test circuit is inconsistent with the target timing, it indicates that the display reset signal AZn has already experienced an abnormality before entering the level shifter circuit 300 and the line driver enhancement circuit 400. Therefore, it can be inferred that the abnormal operation of the third arithmetic circuit has caused the display reset signal AZn to be inconsistent with the target timing. If the display reset signal AZn detected at the output terminal Test_AZ of the third test circuit is consistent with the target timing, it indicates that the display reset signal AZn has experienced an abnormality after entering the level shifter circuit 300 and the line driver enhancement circuit 400. Therefore, it can be inferred that the third arithmetic circuit is operating normally. Therefore, the display reset signal AZn outputted by the third arithmetic circuit can be tested at the output terminal Test_AZ of the third test circuit to determine whether the third arithmetic circuit is operating normally. In an exemplary embodiment, the output terminal Test_AZ of the third test circuit can be brought out through a pad around the display area. During testing, the signal input terminal of the oscilloscope can be electrically connected to the pad of the output terminal Test_AZ of the third test circuit. The waveform output by the output terminal Test_AZ of the third test circuit is obtained through the oscilloscope, and the waveform output by the output terminal Test_AZ of the third test circuit is compared with the waveform of the target timing to see whether they are consistent. If they are consistent, it indicates that the third operation circuit is working normally, and if they are inconsistent, it indicates that the third operation circuit is working abnormally.

[0334] An exemplary embodiment of the present disclosure further provides an operating method of a gate driving circuit, which is applied to the gate driving circuit described in any of the above embodiments, wherein the gate driving circuit includes a multi-stage shift register circuit and a multi-stage logic operation circuit respectively connected to the multi-stage shift register circuit, wherein the multi-stage shift register circuit is cascade-connected; the operating method includes:

[0335] Each shift register circuit in at least one stage of the shift register circuit receives a first clock signal and outputs a first input signal to a corresponding logic operation circuit under the control of the first clock signal;

[0336] Each level of logic operation circuit in at least one level of logic operation circuit outputs a write switch signal under the control of the first input signal, and the write switch signal includes two valid signals, and the sum of the pulse widths of the two valid signals is less than or equal to the period of the first clock signal.

[0337] An exemplary embodiment of the present disclosure also provides a display substrate, as shown in Figure 31, the display substrate may include a display area and a non-display area; the display area includes a plurality of sub-pixels, at least one sub-pixel includes a pixel driving circuit and at least one scanning signal line, and the scanning signal line is configured to provide a scanning signal to the connected pixel driving circuit; the non-display area includes a plurality of cascaded gate driving circuits, at least one gate driving circuit is connected to the scanning signal line in the display area, and at least one gate driving circuit may include the gate driving circuit described in any of the above embodiments.

[0338] In an exemplary embodiment, the display substrate provided by the present disclosure can generate the target timing required by the pixel driving circuit using standard signals through the reasonable layout of the first operation circuit, the second operation circuit and the third operation circuit in the logic operation circuit, and can drive a display panel with a pixel density of 4K or above, and can be applied to silicon-based OLED display devices with a pixel density of 4K or above.

[0339] The exemplary embodiments of the present disclosure further provide a display device, as shown in FIG32 , which may include the aforementioned display substrate. The display device of the present disclosure may be used in virtual reality (VR) devices, augmented reality (AR) devices, extended reality (XR) devices, mixed reality (MR) devices, sights and rangefinders, computers, mobile phones, wearable devices, and the like.

[0340] The present disclosure provides a gate drive circuit and its working method, a display substrate, and a display device. In the gate drive circuit, in at least one level of shift register circuit, each level of shift register circuit is configured to receive a first clock signal and output a first input signal to the corresponding logic operation circuit under the control of the first clock signal; in at least one level of logic operation circuit, each level of logic operation circuit is configured to output a write switch signal under the control of the first input signal, and the write switch signal includes two valid signals, and the sum of the pulse widths of the two valid signals is less than or equal to the period of the first clock signal. This can avoid the situation where the pulse widths of the valid signals in the write switch signals of multiple rows output by the multiple levels of logic operation circuits at the same time overlap, and further avoid the phenomenon that the first transistors in the pixel drive circuits of multiple rows are turned on at the same time, and can overcome the technical problem of data signals being written to the wrong row due to the overlap of valid signals in the write switch signals of multiple rows at the same time.

[0341] Although the embodiments disclosed in this disclosure are as described above, the contents described are merely embodiments adopted to facilitate understanding of the disclosure and are not intended to limit the disclosure. Any person skilled in the art to which the disclosure belongs may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope of the disclosure. However, the scope of patent protection of this application shall still be based on the scope defined by the attached claims.

Claims

1. A gate drive circuit comprising a multi-stage shift register circuit and a multi-stage logic operation circuit respectively connected to the multi-stage shift register circuit, wherein the multi-stage shift register circuit is cascade-connected; In the at least one stage of shift register circuit, each stage of the shift register circuit is configured to receive a first clock signal and output a first input signal to a corresponding logic operation circuit under the control of the first clock signal; In at least one level of logic operation circuit, each level of logic operation circuit is configured to output a write switch signal under the control of the first input signal, and the write switch signal includes two valid signals, and the sum of the pulse widths of the two valid signals is less than or equal to the period of the first clock signal.

2. The gate drive circuit according to claim 1, wherein: In the at least one stage of the shift register circuit, each stage of the shift register circuit includes a first signal input terminal, a first clock signal terminal, and a first shift signal output terminal, and is configured to receive a first signal through the first signal input terminal and a first clock signal through the first clock signal terminal, shift the first signal under control of the first clock signal to obtain the first input signal, and provide the first input signal to the corresponding logic operation circuit through the first shift signal output terminal; The pulse width of the effective signal in the first input signal is S periods of the first clock signal, where S is a positive integer.

3. The gate driving circuit according to claim 2, wherein: The shift register circuit is configured to control the pulse width of the effective signal in the first input signal by using the pulse width of the effective signal in the first signal.

4. The gate driving circuit according to claim 2, wherein: The end time of the valid signal in the first input signal output by the n-th stage shift register circuit is synchronized with the start time of the valid signal in the first input signal output by the n+S-th stage shift register circuit, where n is a positive integer; the start time of the valid signal in the first input signal output by the n+S-th stage shift register circuit is no earlier than the end time of the valid signal in the first input signal output by the n-th stage shift register circuit.

5. The gate driving circuit according to claim 4, wherein: In the at least one level of logic operation circuit, each level of logic operation circuit includes a first input terminal and a write switch signal terminal, and is configured to receive the first input signal through the first input terminal, generate the write switch signal under the control of the first input signal, and output the write switch signal through the write switch signal terminal; In the at least one level of logic operation circuit, each level of logic operation circuit, under the control of the first input signal received at the first input end of the level, generates a first valid signal in the write switch signal at a start time that is synchronized with the start time of the valid signal in the first input signal received at the first input end of the level; and generates a second valid signal in the write switch signal at an end time that is synchronized with the end time of the valid signal in the first input signal received at the first input end of the level. Time synchronization.

6. The gate drive circuit according to any one of claims 2 to 5, wherein: In the at least one stage of the shift register circuit, the phase relationship between the first signal received by each stage of the shift register circuit in one light-emitting cycle and the first clock signal includes: The rising edge time of the first signal is no later than the first rising edge time of the first clock signal; The falling edge time of the first signal is no earlier than the time of the Sth rising edge of the first clock signal and no earlier than the time of the S+1th rising edge of the first clock signal.

7. The gate driving circuit according to claim 5, wherein: In the at least one stage of the shift register circuit, each stage of the shift register circuit further includes a second signal input terminal, a second clock signal terminal, and a second shift signal output terminal, and is configured to receive a second signal through the second signal input terminal and a second clock signal through the second clock signal terminal, and under the control of the second clock signal, shift the second signal to obtain a second input signal, and provide the second input signal to the corresponding logic operation circuit through the second shift signal output terminal; In the at least one stage of the logic operation circuit, each stage of the logic operation circuit further includes a second input terminal, and is configured to receive the second input signal through the second input terminal, and generate the write switch signal under the control of the first input signal and the second input signal; In the at least one level of logic operation circuit, the end time of the first valid signal in the write switch signal generated by each level of logic operation circuit under the control of the second input signal received at the second input end of this level is synchronized with the start time of the valid signal in the second input signal received at the second input end of this level.

8. The gate driving circuit according to claim 7, wherein: In the at least one level of logic operation circuit, the start time of the valid signal in the first input signal received by the first input end of each level of logic operation circuit is earlier than the start time of the valid signal in the second input signal received by the second input end of this level.

9. The gate driving circuit according to claim 8, wherein: In the at least one level of logic operation circuit, each level of logic operation circuit is configured to control the pulse width of the first valid signal in the write switch signal by the difference between the start time of the valid signal in the second input signal and the start time of the valid signal in the first input signal.

10. The gate driving circuit according to any one of claims 7 to 9, wherein: The shift register circuit is configured to control the pulse width of the effective signal in the second input signal by using the pulse width of the effective signal in the second signal.

11. The gate drive circuit according to any one of claims 7 to 9, wherein: The cycle length of the second clock signal is consistent with the cycle length of the first clock signal. In the at least one stage of the shift register circuit, the phase relationship between the second signal received by each stage of the shift register circuit in one light-emitting cycle and the second clock signal includes: The rising edge time of the second signal is no later than the first rising edge time of the second clock signal; The falling edge time of the second signal is no earlier than the time of the Sth rising edge of the second clock signal and no earlier than the time of the S+1th rising edge of the second clock signal.

12. The gate driving circuit according to claim 7, wherein: In the at least one stage of the shift register circuit, each stage of the shift register circuit further includes a third signal input terminal, a third clock signal terminal, and a third shift signal output terminal, and is configured to receive a third signal through the third signal receiving terminal and a third clock signal through the third clock signal terminal, and under the control of the third clock signal, shift the third signal to obtain a third input signal, and provide the third input signal to the corresponding logic operation circuit through the third shift signal output terminal; in the at least one stage of the logic operation circuit, each stage of the logic operation circuit further includes a third input terminal, and is configured to receive the third input signal through the third input terminal, and generate the write switch signal under the control of the first input signal, the second input signal, and the third input signal; In the at least one level of logic operation circuit, the start time of the second valid signal in the write switch signal generated by each level of logic operation circuit under the control of the third input signal received at the third input terminal of this level is synchronized with the end time of the valid signal in the third input signal received at the third input terminal of this level.

13. The gate driving circuit according to claim 12, wherein: In the at least one level of logic operation circuit, the end time of the valid signal in the first input signal received by the first input end of each level of logic operation circuit is later than the end time of the valid signal in the third input signal received by the third receiving end of this level.

14. The gate driving circuit according to claim 13, wherein: In the at least one level of logic operation circuit, each level of logic operation circuit is configured to control the pulse width of the second valid signal in the write switch signal by the difference between the end time of the valid signal in the first input signal and the end time of the valid signal in the third input signal.

15. The gate driving circuit according to any one of claims 12 to 14, wherein: The shift register circuit is configured to control the pulse width of the effective signal in the third input signal by using the pulse width of the effective signal in the third signal.

16. The gate driving circuit according to any one of claims 12 to 14, wherein: The cycle length of the third clock signal is consistent with the cycle length of the first clock signal. In the at least one stage of the shift register circuit, the phase relationship between the third signal received by each stage of the shift register circuit in one light-emitting cycle and the third clock signal includes: The rising edge time of the third signal is no later than the first rising edge time of the third clock signal; The falling edge time of the third signal is no earlier than the time of the Sth rising edge of the third clock signal, and no earlier than the time of the Sth rising edge of the third clock signal. The time of the S+1th rising edge of the third clock signal.

17. The gate drive circuit according to any one of claims 2 to 5, 7 to 9, and 12 to 14, wherein: The end time of the valid signal in the first input signal output by the n-th stage shift register circuit differs from the start time of the valid signal in the first input signal output by the (n+m)-th stage shift register circuit by mS cycles of the first clock signal, where m is a positive integer; the start time of the valid signal in the first input signal output by the n-th stage shift register circuit differs from the start time of the valid signal in the first input signal output by the (n+m)-th stage shift register circuit by m cycles of the first clock signal.

18. The gate driving circuit according to claim 17, wherein: The n-th stage shift register circuit is connected to the n-th stage logic operation circuit and is configured to provide a first input signal to the n-th stage logic operation circuit; The n+mth stage shift register circuit is connected to the n+mth stage logic operation circuit and is configured to provide a first input signal to the n+mth stage logic operation circuit; The n-th level logic operation circuit is configured to generate a write switch signal under the control of the first input signal output by the n-th level shift register circuit, and the n+m-th level logic operation circuit is configured to generate a write switch signal under the control of the first input signal output by the n+m-th level shift register circuit; the end time of the second valid signal in the write switch signal generated by the n-th level logic operation circuit differs from the start time of the first valid signal in the write switch signal generated by the n+m-th level logic operation circuit by mS cycles of the first clock signal; the start time of the first valid signal in the write switch signal generated by the n-th level logic operation circuit differs from the start time of the first valid signal in the write switch signal generated by the n+m-th level logic operation circuit by m cycles of the first clock signal.

19. The gate drive circuit according to any one of claims 2 to 5, 7 to 9, and 12 to 14, wherein: At least one level of logic operation circuit includes a fourth clock signal terminal, the fourth clock signal terminal is configured to receive a fourth clock signal, and the cycle duration of the fourth clock signal is consistent with the cycle duration of the first clock signal; Under the control of the fourth clock signal, the end time of the second valid signal in the write switch signal output by the n-th level logic operation circuit is different from the start time of the first valid signal in the write switch signal output by the n+S-th level logic operation circuit by a first time interval, and the length of the first time interval is the length of the valid signal in one cycle of the fourth clock signal.

20. The gate driving circuit according to claim 19, wherein: In a light-emitting cycle, there are S cycles of the fourth clock signal. In a light-emitting cycle corresponding to the n-th level logic operation circuit, the end time of the second valid signal in the write switch signal output by the n-th level logic operation circuit is synchronized with the S-th rising edge of the fourth clock signal received by the n-th level logic operation circuit, and the start time of the first valid signal in the write switch signal output by the n+S-th level logic operation circuit is synchronized with the S-th falling edge of the fourth clock signal received by the n+S-th level logic operation circuit.

21. The gate drive circuit according to any one of claims 2 to 5, 7 to 9, and 12 to 14, wherein: The difference between the start time of the first valid signal in the write switch signal output by the n-th level logic operation circuit and the start time of the first valid signal in the write switch signal output by the n+1-th level logic operation circuit is greater than or equal to the pulse width of the second valid signal, and n is a positive integer.

22. A gate drive circuit operating method, applied to the gate drive circuit according to any one of claims 1 to 21, the gate drive circuit comprising a multi-stage shift register circuit and a multi-stage logic operation circuit respectively connected to the multi-stage shift register circuit, the multi-stage shift register circuits being cascade-connected; the operating method comprising: Each shift register circuit in at least one stage of the shift register circuit receives a first clock signal and outputs a first input signal to a corresponding logic operation circuit under the control of the first clock signal; Each level of logic operation circuit in at least one level of logic operation circuit outputs a write switch signal under the control of the first input signal, and the write switch signal includes two valid signals, and the sum of the pulse widths of the two valid signals is less than or equal to the period of the first clock signal.

23. A display substrate comprising a display area and a non-display area; the display area comprises a plurality of sub-pixels, at least one sub-pixel comprises a pixel driving circuit and at least one scanning signal line, the scanning signal line is configured to provide a scanning signal to the connected pixel driving circuit; the non-display area comprises a plurality of cascaded gate driving circuits, at least one gate driving circuit is connected to the scanning signal line in the display area, and at least one gate driving circuit comprises the gate driving circuit as described in any one of claims 1 to 21.

24. A display device comprising the display substrate according to claim 23.

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