Display device and manufacturing method therefor

Abstract

This display device comprises: a substrate comprising first, second, and third sub-pixel areas and non-emission areas corresponding to boundaries of the first, second, and third sub-pixel areas; a display element layer comprising light-emitting elements disposed in each of the first, second, and third sub-pixel areas on the substrate; a light conversion layer disposed on the display element layer and comprising banks disposed in the non-emission areas; and a color filter layer disposed on the light conversion layer and comprising first, second, and third color filters, wherein one of the first, second, and third color filters is disposed in the non-emission areas.

Description

Display device and method for manufacturing the same

[0001] The embodiments relate to a display device and a method for manufacturing the display device.

[0002] Flat panel displays are being used as replacements for cathode ray tube displays due to their lightweight and thin profile. Representative examples of these flat panel displays include liquid crystal displays and organic light-emitting diode displays.

[0003] A display device may include a light-emitting element that generates light, a color conversion unit that converts the wavelength of the light generated by the light-emitting element, and a color filter layer disposed on the color conversion unit. The color filter layer may include a plurality of color filter layers that selectively transmit light of different colors.

[0004] Embodiments provide a display device that adjusts the reflected color through a design change.

[0005] Embodiments provide a method of manufacturing a display device for manufacturing a display device.

[0006] However, the embodiments are not limited to the embodiments described herein. The embodiments described herein and other embodiments will become more apparent to those skilled in the art to which this disclosure pertains by referring to the detailed description set forth below.

[0007] A display device includes a substrate including first, second, and third sub-pixel regions and non-emitting regions corresponding to boundaries of the first, second, and third sub-pixel regions, a display element layer including light-emitting elements arranged in each of the first, second, and third sub-pixel regions on the substrate, a light conversion layer disposed on the display element layer and including a bank disposed in the non-emitting region, and a color filter layer disposed on the light conversion layer and including first, second, and third color filters, wherein one of the first, second, and third color filters is disposed in the non-emitting region.

[0008] In one embodiment, the light conversion layer further includes a first layer disposed in the first, second, and third sub-pixel areas, and a second layer covering the first layer, and the bank may be disposed in the non-emissive area on the second layer.

[0009] In one embodiment, at least one of the first, second, and third color filters can be in contact with the second layer.

[0010] In one embodiment, the light conversion layer may further include a low-refractive layer disposed on the second layer, and a third layer covering the low-refractive layer.

[0011] In one embodiment, at least one of the first, second, and third color filters can be in contact with the third layer.

[0012] In one embodiment, the first layer can be formed by a photolithography process.

[0013] In one embodiment, the first, second, and third color filters can be formed by a photolithography process.

[0014] A display device according to embodiments includes a substrate including first, second, and third sub-pixel regions and a non-emitting region corresponding to a boundary of the first, second, and third sub-pixel regions, a display element layer including light-emitting elements arranged in each of the first, second, and third sub-pixel regions on the substrate, a light conversion layer disposed on the display element layer and including a bank disposed in the non-emitting region, and a color filter layer disposed on the light conversion layer and including first, second, and third color filters, wherein two of the first, second, and third color filters are disposed in the non-emitting region.

[0015] In one embodiment, the first and second color filters may be arranged in the non-luminous region, and the first color filter may be arranged on the second color filter in the non-luminous region.

[0016] In one embodiment, the light conversion layer further includes a first layer disposed in the first, second, and third sub-pixel areas, and a second layer covering the first layer, and the bank may be disposed in the non-emissive area on the second layer.

[0017] In one embodiment, at least one of the first, second, and third color filters can be in contact with the second layer.

[0018] In one embodiment, the light conversion layer may further include a low-refractive layer disposed on the second layer, and a third layer covering the low-refractive layer.

[0019] In one embodiment, at least one of the first, second, and third color filters can be in contact with the third layer.

[0020] In one embodiment, the first layer can be formed by a photolithography process.

[0021] In one embodiment, the first, second, and third color filters can be formed by a photolithography process.

[0022] A method for manufacturing a display device according to embodiments includes the steps of providing a substrate including first, second, and third sub-pixel regions and non-emitting regions corresponding to boundaries of the first, second, and third sub-pixel regions, forming a display element layer on the substrate including light-emitting elements arranged in each of the first, second, and third sub-pixel regions on the substrate, forming a light-conversion layer on the display element layer including a bank arranged in the non-emitting region, and forming a color filter layer including first, second, and third color filters on the light-conversion layer, wherein the step of forming the color filter layer may include the step of forming one of the first, second, and third color filters in the non-emitting region on the bank.

[0023] In one embodiment, the step of forming the light conversion layer includes the step of forming a first layer in the first, second, and third sub-pixel areas, and the step of forming a second layer covering the first layer, wherein the bank can be formed in the non-emissive area on the second layer.

[0024] In one embodiment, the step of forming the light conversion layer further includes the step of forming a low-refractive layer on the second layer, and the step of forming a third layer covering the low-refractive layer, wherein at least one of the first, second, and third color filters can be in contact with the third layer.

[0025] In one embodiment, the first layer can be formed by a photolithography process.

[0026] In one embodiment, the first, second, and third color filters can be formed by a photolithography process.

[0027] The display device according to the embodiments may use the banks used to define the boundaries of the color conversion layers to define the areas where light of each color is emitted.

[0028] The display device according to the embodiments uses banks to define areas where light of each color is emitted, thereby allowing relatively free design of color filters in non-emissive areas.

[0029] The display device according to the embodiments can control the reflected color by using one or two layers of color filters in a non-luminous area.

[0030] The display device according to the embodiments can reduce the thickness of the planarization layer by using one or two layers of color filters in the non-emissive area. Accordingly, the production cost of the display device can be reduced.

[0031] However, the effects of this specification are not limited to the effects described above, and may be expanded in various ways without departing from the spirit and scope of this specification.

[0032] FIG. 1 is a schematic plan view showing a display device according to embodiments.

[0033] Figures 2 to 4 are plan views schematically showing embodiments of the pixels of Figure 1.

[0034] Figure 5 is a schematic cross-sectional view illustrating the display panel of Figure 1.

[0035] FIG. 6 is a schematic diagram showing an equivalent circuit of one embodiment of a sub-pixel included in the pixels of FIGS. 2 to 4.

[0036] Fig. 7 is a cross-sectional view schematically illustrating one embodiment of the light-emitting element of Fig. 6. Fig. 8 is a cross-sectional view schematically illustrating another embodiment of the light-emitting element of Fig. 6.

[0037] FIG. 9 is a cross-sectional view schematically illustrating one embodiment of a pixel including the light emitting element of FIG. 7 or FIG. 8.

[0038] Fig. 10 is a cross-sectional view schematically showing the light conversion layer and color filter layer of Fig. 9.

[0039] Fig. 11 is a cross-sectional view schematically illustrating the thickness of the bank of Fig. 10 according to the transmittance of the second color filter.

[0040] FIGS. 12 and 13 are cross-sectional views schematically showing a light conversion layer and a color filter layer of a display device according to embodiments.

[0041] Fig. 14 is a cross-sectional view schematically showing a light conversion layer and a color filter layer of a display device according to embodiments.

[0042] Figures 15 to 17 are cross-sectional views schematically showing a light conversion layer and a color filter layer of a display device according to embodiments.

[0043] Fig. 18 is a flowchart showing a method for manufacturing a display device according to embodiments.

[0044] Figures 19 to 23 are drawings schematically showing step S300 of Figure 18.

[0045] Figures 24 and 25 are drawings schematically showing step S400 of Figure 18.

[0046] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. It should be noted that the following description only describes portions necessary for understanding the operation of the present invention, and that explanations of other portions will be omitted to avoid obscuring the gist of the present invention. Furthermore, the present invention is not limited to the embodiments described herein and may be embodied in other forms. However, the embodiments described herein are provided to provide a detailed explanation of the technical concepts of the present invention to a person skilled in the art to which the present invention pertains, to a degree that allows the technical concepts of the present invention to be easily implemented.

[0047] Throughout the specification, when a part is said to be "connected" to another part, this includes not only the case where it is "directly connected" but also the case where it is "indirectly connected" with another element in between. The terminology used herein is for the purpose of describing particular embodiments and is not intended to limit the present invention. Throughout the specification, when a part is said to "comprise" a certain element, this does not exclude other elements unless specifically stated to the contrary, but rather means that other elements can be included. "At least one of X, Y, and Z", and "at least one selected from the group consisting of X, Y, and Z" can be interpreted as one X, one Y, one Z, or any combination of two or more of X, Y, and Z (e.g., XYZ, XYY, YZ, ZZ). Here, "and / or" includes any combination of one or more of the configurations.

[0048] Here, terms such as "first" and "second" may be used to describe various components, but these components are not limited to these terms. These terms are used to distinguish one component from another. Accordingly, a "first component" may refer to a "second component" within the scope disclosed herein.

[0049] Spatially relative terms, such as "below," "above," and the like, may be used for descriptive purposes to describe one element or feature in relation to other elements or features as depicted in the drawings. Spatially relative terms are intended to encompass different orientations during use, operation, and / or manufacturing, in addition to the orientation depicted in the drawings. For example, if a device depicted in the drawings is turned over, elements depicted as being positioned "below" other elements or features would instead be positioned "above" the other elements or features. Thus, in one embodiment, the term "below" can encompass both above and below. Furthermore, the device may be oriented in other orientations (e.g., rotated 90 degrees or in other directions), and the spatially relative terms used herein are to be interpreted accordingly.

[0050] Various embodiments are described with reference to drawings illustrating ideal embodiments. Accordingly, it is to be understood that the shapes may vary, for example, depending on tolerances and / or manufacturing techniques. Therefore, the embodiments disclosed herein should not be construed as limited to the specific shapes depicted, but rather to encompass, for example, variations in shapes resulting from manufacturing processes. Likewise, the shapes depicted in the drawings may not depict the actual shapes of areas of the device, and the embodiments are not limited thereto.

[0051] Hereinafter, the present specification will be described in more detail with reference to the attached drawings.

[0052] FIG. 1 is a schematic plan view showing a display device according to embodiments.

[0053] Referring to FIG. 1, according to one embodiment, the display panel (DP) (or display device (DD)) may be provided in various shapes, and for example, may be provided in the shape of a rectangular plate having two pairs of sides that are parallel to each other, but embodiments are not limited thereto. When the display panel (DP) is provided in the shape of a rectangular plate, one of the two pairs of sides may be provided to be longer than the other pair of sides.

[0054] The display panel (DP) may have at least a portion of flexibility and may be foldable in the flexible portion, but embodiments are not limited thereto.

[0055] A display panel (DP) can display an image. As the display panel (DP), a self-luminous display panel such as an organic light-emitting display panel (OLED panel) that uses an organic light-emitting diode as a light-emitting element, an ultra-small light-emitting diode display panel (micro-LED or nano-LED display panel) that uses an ultra-small light-emitting diode as a light-emitting element, and a quantum dot organic light-emitting display panel (QD OLED panel) that uses quantum dots and organic light-emitting diodes can be used. In addition, a non-luminous display panel such as a liquid crystal display panel (LCD panel), an electrophoretic display panel (EPD panel), and an electro-wetting display panel (EWD panel) can be used as the display panel (DP). When a non-luminous display panel is used as the display panel (DP), the display device (DD) can be provided with a backlight unit that supplies light to the display panel (DP).

[0056] The display panel (DP) may include a substrate (SUB) and pixels (PXL) provided on the substrate (SUB).

[0057] The substrate (SUB) may include a transparent insulating material to enable light transmission. The substrate (SUB) may be a rigid substrate or a flexible substrate. The rigid substrate may be, for example, one of a glass substrate, a quartz substrate, a glass ceramic substrate, and a crystalline glass substrate.

[0058] The flexible substrate may be one of a film substrate including a polymer organic material and a plastic substrate. For example, the flexible substrate may include at least one of polystyrene, polyvinyl alcohol, polymethyl methacrylate, polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, triacetate cellulose, and cellulose acetate propionate.

[0059] The display device (DD) may have various shapes. For example, the display device (DD) may be provided in a rectangular shape, but embodiments are not limited thereto. For example, the display device (DD) may have a circular or oval shape. In addition, the display device (DD) may include angled corners and / or curved corners. For convenience, in FIG. 1, the display device (DD) is illustrated as having a rectangular plate shape. For example, in FIG. 1, the extension direction of the short side (for example, the horizontal direction) of the display device (DD) is represented as a first direction (DR1), and the extension direction of the long side (for example, the vertical direction) is represented as a second direction (DR2).

[0060] The substrate (SUB) (and the display device (DD)) may include a display area (DA) for displaying an image and a peripheral area (PA) (or non-display area) excluding the display area (DA). The substrate (SUB) may include a display area (DA) including pixel areas in which each pixel (PXL) is arranged, and a peripheral area (PA) arranged around the display area (DA) (or adjacent to the display area (DA)).

[0061] The peripheral area (PA) may be positioned adjacent to the display area (DA). The peripheral area (PA) may be provided on at least one side of the display area (DA). For example, the peripheral area (PA) may surround the perimeter (or edge) of the display area (DA). In embodiments, the peripheral area (PA) may be a bezel area of ​​the display device (DD).

[0062] Pixels (PXL) may be arranged in a display area (DA) on a substrate (SUB). A peripheral area (PA) may be arranged around the display area (DA). The peripheral area (PA) may have a structure for protecting a configuration included in the pixels (PXL) arranged in the display area (DA), but embodiments are not limited thereto. For example, a wiring unit connected to each pixel (PXL) and a driving unit connected to the wiring unit may be provided in the peripheral area (PA). The driving unit may drive the pixels (PXL).

[0063] A pixel (PXL) may include a plurality of sub-pixels (SPX1 to SPX3). For example, the pixel (PXL) may include a first sub-pixel (SPX1), a second sub-pixel (SPX2), and a third sub-pixel (SPX3). The first sub-pixel (SPX1), the second sub-pixel (SPX2), and the third sub-pixel (SPX3) may be sequentially arranged in a first direction (DR1). However, embodiments are not limited thereto, and the first sub-pixel (SPX1), the second sub-pixel (SPX2), and the third sub-pixel (SPX3) may be sequentially arranged in a second direction (DR2) intersecting the first direction (DR1).

[0064] The first to third sub-pixels (SPX1 to SPX3) can emit light in different colors. For example, the first sub-pixel (SPX1) can be a red sub-pixel that emits red light, the second sub-pixel (SPX2) can be a green sub-pixel that emits green light, and the third sub-pixel (SPX3) can be a blue sub-pixel that emits blue light. However, the color, type, and / or number of the sub-pixels constituting the pixel (PXL) are not particularly limited, and for example, the color of the light emitted by each of the first to third sub-pixels (SPX1 to SPX3) can be variously changed. Hereinafter, when collectively naming the first to third sub-pixels (SPX1 to SPX3), they are referred to as pixels (PXL).

[0065] Figures 2 to 4 are plan views schematically showing embodiments of the pixels of Figure 1.

[0066] Referring to FIGS. 1 to 4, a pixel (PXL) may include a plurality of sub-pixels (SPX1 to SPX3). In FIGS. 2 to 4, each pixel (PXL) is illustrated as including a first sub-pixel (SPX1), a second sub-pixel (SPX2), and a third sub-pixel (SPX3), but the embodiments are not limited thereto.

[0067] The first sub-pixel (SPX1), the second sub-pixel (SPX2), and the third sub-pixel (SPX3) can be connected to any one of the data lines and at least one scan line among the scan lines.

[0068] Referring to FIGS. 2 to 4, each of the first sub-pixel (SPX1), the second sub-pixel (SPX2), and the third sub-pixel (SPX3) may have a rectangular, square, or polygonal planar shape.

[0069] Referring to FIG. 2, each of the first sub-pixel (SPX1), the second sub-pixel (SPX2), and the third sub-pixel (SPX3) may have a rectangular planar shape having a short side in the first direction (DR1) and a long side in the second direction (DR2). However, embodiments are not limited thereto, and according to embodiments, each of the first sub-pixel (SPX1), the second sub-pixel (SPX2), and the third sub-pixel (SPX3) may have a square or rhombus planar shape including sides having the same length in the first direction (DR1) and the second direction (DR2). In embodiments, the first sub-pixel (SPX1), the second sub-pixel (SPX2), and the third sub-pixel (SPX3) may be arranged in the first direction (DR1). In embodiments, the areas of the first to third sub-pixels (SPX1 to SPX3) may be substantially the same, but embodiments are not limited thereto. For example, at least one of the areas of the first to third sub-pixels (SPX1 to SPX3) may be different from another one. As another example, any two of the area of ​​the first sub-pixel (SPX1), the area of ​​the second sub-pixel (SPX2), and the area of ​​the third sub-pixel (SPX3) may be substantially the same, and the remaining one may be different from the two. Alternatively, the area of ​​the first sub-pixel (SPX1), the area of ​​the second sub-pixel (SPX2), and the area of ​​the third sub-pixel (SPX3) may be different from each other.

[0070] Referring to FIG. 3, the first sub-pixel (SPX1) may be arranged in a first direction (DR1) with one of the second sub-pixel (SPX2) and the third sub-pixel (SPX3), and may be arranged in a second direction (DR2) with the other of the second sub-pixel (SPX2) and the third sub-pixel (SPX3). For example, the first sub-pixel (SPX1) may be arranged parallel to the second sub-pixel (SPX2) in the first direction (DR1), and the first sub-pixel (SPX1) may be arranged in the second direction (DR2) with the third sub-pixel (SPX3). In embodiments, the third sub-pixel (SPX3) may be arranged in the second direction (DR2) with the first sub-pixel (SPX1) and the second sub-pixel (SPX2). In embodiments, the areas of the first and second sub-pixels (SPX1, SPX2) may be substantially the same, and the area of ​​the third sub-pixel (SPX3) may be different from the areas of the first and second sub-pixels (SPX1, SPX2). For example, the area of ​​the third sub-pixel (SPX3) may be larger than the areas of the first and second sub-pixels (SPX1, SPX2).

[0071] Referring to FIG. 4, each of the first sub-pixel (SPX1), the second sub-pixel (SPX2), and the third sub-pixel (SPX3) may have a hexagonal or regular hexagonal planar shape. In embodiments, two adjacent sides of the six sides of each of the first to third sub-pixels (SPX1 to SPX3) may face one side of the adjacent sub-pixels.

[0072] Referring to FIGS. 2 to 4, a first sub-pixel (SPX1) can emit a first light, a second sub-pixel (SPX2) can emit a second light, and a third sub-pixel (SPX3) can emit a third light. The first light can be light in a red wavelength band, the second light can be light in a green wavelength band, and the third light can be light in a blue wavelength band. The red wavelength band can be a wavelength band of about 600 nm to about 750 nm, the green wavelength band can be a wavelength band of about 480 nm to about 560 nm, and the blue wavelength band can be a wavelength band of about 370 nm to about 460 nm, but the embodiments are not limited thereto.

[0073] Each of the first sub-pixel (SPX1), the second sub-pixel (SPX2), and the third sub-pixel (SPX3) may include a light-emitting element that emits light (e.g., the light-emitting element (LD) of FIG. 7 or FIG. 8), and the light-emitting element may include an organic light-emitting element having an organic layer.

[0074] Figure 5 is a schematic cross-sectional view illustrating the display panel of Figure 1.

[0075] Referring to FIG. 5, the display panel (DP) may include a substrate (SUB), a pixel circuit layer (PCL), a display element layer (DPL), an encapsulation layer (TFE), a light conversion layer (LCL), and a color filter layer (CFL). In embodiments, the substrate (SUB), the pixel circuit layer (PCL), the display element layer (DPL), the encapsulation layer (TFE), the light conversion layer (LCL), and the color filter layer (CFL) may be sequentially stacked in a third direction (DR3).

[0076] A pixel circuit layer (PCL) is provided (or arranged) on a substrate (SUB) and may include a plurality of transistors and signal lines connected to the transistors. For example, each transistor may have a semiconductor pattern, a gate electrode, a source electrode, and a drain electrode sequentially stacked with an insulating layer therebetween. The semiconductor pattern may include amorphous silicon, polysilicon, low temperature polysilicon, an organic semiconductor, and / or an oxide semiconductor. The gate electrode, the source electrode, and the drain electrode may include one of aluminum (Al), copper (Cu), titanium (Ti), and molybdenum (Mo), but embodiments are not limited thereto. For example, the pixel circuit layer (PCL) may include at least one insulating layer.

[0077] A display element layer (DPL) may be disposed on a pixel circuit layer (PCL). The display element layer (DPL) may include a light-emitting element that emits light (e.g., a light-emitting element (LD) of FIG. 7 or 8). The light-emitting element may be, for example, an organic light-emitting diode, but embodiments are not limited thereto. According to embodiments, the light-emitting element may be an inorganic light-emitting element including an inorganic light-emitting material, or a light-emitting element that changes (or converts) the wavelength of emitted light by using quantum dots to emit light.

[0078] The encapsulation layer (TFE) may be disposed on the display element layer (DPL). The encapsulation layer (TFE) may be in the form of an encapsulation substrate or an encapsulation film formed of a multilayer film. When the encapsulation layer (TFE) is in the form of the encapsulation film, it may include an inorganic film and / or an organic film. For example, the encapsulation layer (TFE) may be in the form of an inorganic film, an organic film, and an inorganic film sequentially laminated. The encapsulation layer (TFE) may prevent external air and moisture from penetrating into the display element layer (DPL) and the pixel circuit layer (PCL).

[0079] The light conversion layer (LCL) may be disposed on the encapsulation layer (TFE). The light conversion layer (LCPL) may include elements for converting light emitted from the display element layer (DPL) into light of a specific color and for increasing light emission efficiency. In embodiments, the light conversion layer (LCL) may include a color conversion layer (e.g., the color conversion layer (CCL) of FIG. 9) and a low-refractive layer (e.g., the low-refractive layer (LRL) of FIG. 9).

[0080] A color filter layer (CFL) may be disposed on a light conversion layer (LCL). The color filter layer (CFL) may selectively transmit light that has passed through the light conversion layer (LCL) (or the display element layer (DPL)). The color filter layer (CFL) may include first to third color filters (e.g., first to third color filters CF1 to CF3 of FIG. 9).

[0081] FIG. 6 is a schematic diagram showing an equivalent circuit of one embodiment of a sub-pixel included in the pixels of FIGS. 2 to 4.

[0082] The sub-pixel (SPX) illustrated in FIG. 6 may be any one of the sub-pixels (SPX1 to SPX3) illustrated in FIG. 1, and the sub-pixels (SPX1 to SPX3) arranged in the display area of ​​each display device (DD) may be configured to be substantially identical or similar to each other.

[0083] For convenience, in Fig. 6, a sub-pixel (SPX) located in the i-th pixel row (or i-th horizontal line) and the j-th pixel column is illustrated (where i and j are positive integers).

[0084] Referring to FIG. 6, the sub-pixel (SPX) may include a light emitting unit (EMU) that generates light of a brightness corresponding to a data signal. In addition, the sub-pixel (SPX) may further include a pixel circuit (PXC) for driving the light emitting unit (EMU).

[0085] The light-emitting unit (EMU) may include a light-emitting element (LD) connected between a first power line (PL1) supplied with a voltage of a first driving power supply (VDD) (or a first power supply) and a second power line (PL2) supplied with a voltage of a second driving power supply (VSS) (or a second power supply). For example, the light-emitting unit (EMU) may include a light-emitting element (LD) including a first pixel electrode (AE) connected to the first driving power supply (VDD) via a pixel circuit (PXC) and the first power line (PL1) and a second pixel electrode (CE) connected to the second driving power supply (VSS) via a second power line (PL2). The first pixel electrode (AE) may be an anode, and the second pixel electrode (CE) may be a cathode. The first driving power supply (VDD) and the second driving power supply (VSS) may have different potentials. At this time, the potential difference between the first and second driving power supplies (VDD, VSS) can be set to be higher than the threshold voltage of the light-emitting element (LD) during the light-emitting period of the sub-pixel (SPX).

[0086] When a sub-pixel (SPX) is located in the i-th pixel row and the j-th pixel column in the display area (DA), a pixel circuit (PXC) of the sub-pixel (SPX) (or the sub-pixel) may be electrically connected to the i-th scan line (Si) and the j-th data line (Dj). In addition, the pixel circuit (PXC) may be electrically connected to the i-th control line (CLi) and the j-th sensing line (SENj).

[0087] The pixel circuit (PXC) described above may include first to third transistors (T1 to T3) and a storage capacitor (Cst).

[0088] The first transistor (T1) is a driving transistor for controlling a driving current applied to a light-emitting element (LD), and can be electrically connected between a first driving power source (VDD) and the light-emitting element (LD). For example, a first terminal of the first transistor (T1) can be electrically connected to the first driving power source (VDD) via a first power line (PL1), a second terminal of the first transistor (T1) can be electrically connected to a second node (N2), and a gate electrode of the first transistor (T1) can be electrically connected to the first node (N1). The first transistor (T1) can control the amount of driving current applied to the light-emitting element (LD) from the first driving power source (VDD) via the second node (N2) according to a voltage applied to the first node (N1). In an embodiment, the first terminal of the first transistor (T1) may be a drain electrode, and the second terminal of the first transistor (T1) may be a source electrode, but the embodiments are not limited thereto. Depending on the embodiment, the first terminal may be a source electrode, and the second terminal may be a drain electrode.

[0089] The second transistor (T2) may be a switching transistor that selects a sub-pixel (SPX) in response to a scan signal and activates the sub-pixel (SPX), and may be electrically connected between a data line (Dj) (e.g., a j-th data line) and a first node (N1). A first terminal of the second transistor (T2) may be electrically connected to the data line (Dj), a second terminal of the second transistor (T2) may be electrically connected to the first node (N1) (or a gate electrode of the first transistor (T1)), and a gate electrode of the second transistor (T2) may be electrically connected to a scan line (Si) (or an ith scan line). The first terminal and the second terminal of the second transistor (T2) may be different terminals, for example, if the first terminal is a drain electrode, the second terminal may be a source electrode.

[0090] Such a second transistor (T2) is turned on when a scan signal of a gate-on voltage (e.g., a high level voltage) is supplied from the scan line (Si), and can electrically connect the data line (Dj) and the first node (N1). The first node (N1) is a point where the second terminal of the second transistor (T2) and the gate electrode of the first transistor (T1) are connected, and the second transistor (T2) can transmit a data signal to the gate electrode of the first transistor (T1).

[0091] The third transistor (T3) electrically connects the first transistor (T1) to the sensing line (SENj) (for example, the j-th sensing line), thereby obtaining a sensing signal through the sensing line (SENj), and using the sensing signal, detecting the characteristics of the sub-pixel (SPX), including the threshold voltage of the first transistor (T1). Information about the characteristics of the sub-pixel (SPX) can be used to convert image data so that the characteristic deviation between the sub-pixels (SPX) can be compensated for. The second terminal of the third transistor (T3) can be electrically connected to the second terminal of the first transistor (T1), the first terminal of the third transistor (T3) can be electrically connected to the sensing line (SENj), and the gate electrode of the third transistor (T3) can be electrically connected to the control line (CLi) (for example, the i-th control line). The first terminal can be a drain electrode, and the second terminal can be a source electrode.

[0092] The third transistor (T3) is an initialization transistor capable of initializing the second node (N2). When a sensing control signal is supplied from the control line (CLi), it is turned on and can transmit the voltage of the initialization power supply to the second node (N2). Accordingly, the storage capacitor (Cst) electrically connected to the second node (N2) can be initialized.

[0093] The storage capacitor (Cst) may include a lower electrode (LE) (or a first storage electrode) and an upper electrode (UE) (or a second storage electrode). The lower electrode (LE) may be electrically connected to a first node (N1), and the upper electrode (UE) may be electrically connected to a second node (N2). The storage capacitor (Cst) charges a data voltage corresponding to a data signal supplied to the first node (N1) during one frame period. Accordingly, the storage capacitor (Cst) may store a voltage corresponding to a difference between a voltage of a gate electrode of the first transistor (T1) and a voltage of the second node (N2).

[0094] Although FIG. 6 discloses an embodiment in which all of the first to third transistors (T1 to T3) are N-type transistors, the embodiments are not limited thereto. For example, at least one of the above-described first to third transistors (T1 to T3) may be changed to a P-type transistor. The structure of the pixel circuit (PXC) may be implemented with various changes.

[0095] In the following examples, for convenience of explanation, the horizontal direction (X-axis direction or horizontal direction) on a plane is indicated as the first direction (DR1), the vertical direction (Y-axis direction or vertical direction) on a plane is indicated as the second direction (DR2), and the vertical direction on a cross-section is indicated as the third direction (DR3).

[0096] Fig. 7 is a cross-sectional view schematically illustrating one embodiment of the light-emitting element of Fig. 6. Fig. 8 is a cross-sectional view schematically illustrating another embodiment of the light-emitting element of Fig. 6.

[0097] Referring to FIG. 7, the light emitting element (LD) may include a first pixel electrode (AE), an organic light emitting portion (EL), and a second pixel electrode (CE) that are sequentially stacked.

[0098] In one embodiment, the first pixel electrode (AE) can be patterned to correspond to the first to third sub-pixels (e.g., the first to third sub-pixels (SPX1 to SPX3)).

[0099] In one embodiment, an organic light-emitting element (EL) may be provided on a first pixel electrode (AE). The organic light-emitting element (EL) may have a multilayer thin film structure including a plurality of light generation layers. The organic light-emitting element (EL) may include a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL), and an electron injection layer (EIL) that are sequentially stacked.

[0100] The hole injection layer (HIL) may be an organic layer disposed between the first pixel electrode (AE) and the hole transport layer (HTL) to facilitate the injection of holes from the first pixel electrode (AE) to the light emitting layer (EML). The hole transport layer (HTL) may be disposed between the hole injection layer (HIL) and the light emitting layer (EML) to receive holes from the first pixel electrode (AE) and transport them to the light emitting layer (EML).

[0101] An electron injection layer (EIL) may be disposed between an electron transport layer (ETL) and a second pixel electrode (CE). The electron transport layer (ETL) may be disposed on the emission layer (EML) and may serve to receive electrons from the second pixel electrode (CE) and transport them to the emission layer (EML).

[0102] The emission layer (EML) is a region where light is generated by the combination of electrons and holes supplied from the first pixel electrode (AE) and the second pixel electrode (CE). The emission layer (EML) may include an organic light-emitting material, such as a high-molecular organic material or a low-molecular organic material, that emits light of a predetermined color. For example, the emission layer (EML) may be formed of an organic material that emits blue light. However, embodiments are not limited thereto. In embodiments, the emission layer (EML) may be formed of an organic material that emits red or green light, or may be formed of an inorganic material or a quantum dot.

[0103] In one embodiment, the second pixel electrode (CE) may be integrally formed. The second pixel electrode (CE) may be disposed on the organic light-emitting element (EL). The second pixel electrode (CE) may be integrally formed with the light-emitting elements.

[0104] Referring to FIG. 8, the light emitting element (LD) may include a first pixel electrode (AE), an organic light emitting portion (EL), and a second pixel electrode (CE).

[0105] The organic light-emitting element (EL) may include a plurality of light-generating layers. In embodiments, the organic light-emitting element (EL) may include a first organic light-emitting element (ELa), a charge generation layer (CGL), and a second organic light-emitting element (ELb). The first pixel electrode (AE), the first organic light-emitting element (ELa), the charge generation layer (CGL), the second organic light-emitting element (ELb), and the second pixel electrode (CE) may be sequentially stacked.

[0106] The first organic light-emitting portion (ELa) may be provided with a structure in which a hole injection layer (HIL), a first hole transport layer (HTLa), a first organic light-emitting layer (EMLa), and a first electron transport layer (ETLa) are sequentially laminated. The second organic light-emitting portion (ELb) may be provided with a structure in which a second hole transport layer (HTLb), a second organic light-emitting layer (EMLb), a second electron transport layer (ETLb), and an electron injection layer (EIL) are sequentially laminated.

[0107] In one embodiment, a buffer layer (not shown) may be disposed on the first organic light-emitting layer (EMLa) and the second organic light-emitting layer (EMLb). The buffer layer may include an electron-transporting compound.

[0108] The charge generation layer (CGL) may serve to supply charges to the first organic light-emitting portion (ELa) and the second organic light-emitting portion (ELb). The charge generation layer (CGL) may include an n-type charge generation layer (n-CGL) for supplying charges (or electrons) to the first organic light-emitting portion (ELa) and a p-type charge generation layer (p-CGL) for supplying holes to the second organic light-emitting portion (ELb). In this case, the n-type charge generation layer (n-CGL) may be provided by including a metal material as a dopant.

[0109] In Fig. 8, two organic light-emitting parts (ELa, ELb) of the light-emitting element (LD) are shown to be stacked and provided, but the embodiments are not limited thereto. For example, three or four or more organic light-emitting parts may be stacked and provided within the light-emitting element (LD).

[0110] FIG. 9 is a cross-sectional view schematically illustrating one embodiment of a pixel including the light emitting element of FIG. 7 or FIG. 8.

[0111] Referring to FIGS. 1 and 9, the display device (DD) includes a display area (DA), and the display area (DA) may include first to third sub-pixel areas (SPA1 to SPA3) and a non-emission area (NEA). In embodiments, the first sub-pixel area (SPA1) may be an area where light of a first color of the first sub-pixel (SPX1) is emitted. The second sub-pixel area (SPA2) may be an area where light of a second color of the second sub-pixel (SPX2) is emitted. The third sub-pixel area (SPA3) may be an area where light of a third color of the third sub-pixel (SPX3) is emitted. In embodiments, the emission areas of the display area (DA) may correspond to the first to third sub-pixel areas (SPA1 to SPA3). The first to third sub-pixel areas (SPA1 to SPA3) and the non-emitting area (NEA) can be defined by a bank (BNK) of the light conversion layer (LCL).

[0112] Referring to FIG. 9, an embodiment is illustrated in which the first to third sub-pixel areas (SPA1 to SPA3) are adjacent to each other in a direction intersecting the third direction (DR3), but the embodiments are not necessarily limited thereto.

[0113] In one embodiment, a pixel (PXL) may include a pixel circuit layer (PCL), a display element layer (DPL), an encapsulation layer (TFE), a light conversion layer (LCL), and a color filter layer (CFL) sequentially arranged in a third direction (DR3) on a substrate (SUB).

[0114] Circuit elements (for example, the first to third transistors T1 to T3 of FIG. 6) and signal wires electrically connected to the circuit elements may be arranged on a pixel circuit layer (PCL). The pixel circuit layer (PCL) may be arranged on a substrate (SUB). The pixel circuit layer (PCL) may include a first transistor (T1), a buffer layer (BFL), a gate insulating layer (GI), an interlayer insulating layer (ILD), a passivation layer (PVX), and a via layer (VIA). Although one transistor (T1) is illustrated as an example, the sub-pixel (SPX) may include a plurality of transistors and at least one capacitor for driving a light-emitting element (LD).

[0115] A buffer layer (BFL) may be disposed on the substrate (SUB). The buffer layer (BFL) can prevent impurities from diffusing from the outside. The buffer layer (BFL) can prevent impurities from diffusing into the first transistor (T1) provided (or disposed) on the substrate (SUB), thereby improving the flatness of the substrate (SUB). The buffer layer (BFL) may be provided (or formed) as a single layer, but may also be provided as a multi-layer. The buffer layer (BFL) may be an inorganic insulating film including an inorganic material. The inorganic insulating film may include, for example, at least one of a metal oxide such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiOxNy), and aluminum oxide (AlOx). When the buffer layer (BFL) is provided as a multi-layer, each layer may be formed of the same material or different materials. The buffer layer (BFL) may be omitted in some cases.

[0116] A first transistor (T1) may include a semiconductor pattern (SCP), a gate electrode (GE), a first terminal (TE1), and a second terminal (TE1). The first terminal (TE1) may be one of a source electrode and a drain electrode, and the second terminal (TE1) may be the other of the source electrode and the drain electrode. For example, when the first terminal (TE1) is a drain electrode, the second terminal (TE1) may be a source electrode.

[0117] A semiconductor pattern (SCP) may be provided and / or formed on a buffer layer (BFL). The semiconductor pattern (SCP) may include a first region in contact with a first terminal (TE1), a second region in contact with a second terminal (TE1), and a channel region between the first region and the second region. The channel region may overlap with a gate electrode (GE) of the first transistor (T1). The semiconductor pattern (SCP) may be a semiconductor pattern made of amorphous silicon, polysilicon, low-temperature polysilicon, an oxide semiconductor, or an organic semiconductor. The channel region may be, for example, an intrinsic semiconductor as a semiconductor pattern that is not doped with impurities. The first region and the second region may be semiconductor patterns doped with impurities. In embodiments, the first terminal (TE1) may be electrically connected to the light emitting element (LD) through connection electrodes (CNE1, CNE2).

[0118] A gate insulating layer (GI) may be provided and / or formed on a semiconductor pattern (SCP). The gate insulating layer (GI) may be an inorganic insulating film including an inorganic material. The gate insulating layer (GI) may include one or more materials selected from the materials exemplified as constituent materials of the buffer layer (BFL). For example, the gate insulating layer (GI) and the buffer layer (BFL) may include the same material. In embodiments, the gate insulating layer (GI) may be provided as an organic insulating film including an organic material. The gate insulating layer (GI) may be provided as a single film, but may be provided as a multi-film including at least two films.

[0119] A gate electrode (GE) may be provided and / or formed on a gate insulating layer (GI) so as to correspond to (or overlap) a channel region of a semiconductor pattern (SCP). The gate electrode (GE) may be provided (or arranged) on the gate insulating layer (GI) so as to overlap a channel region of the semiconductor pattern (SCP). The gate electrode (GE) may be formed as a single film using a single material or a mixture thereof selected from the group consisting of copper (Cu), molybdenum (Mo), tungsten (W), titanium (Ti), aluminum (Al), silver (Ag), and alloys thereof (e.g., aluminum neodymium (AlNd)), or may be formed as a double film or multi-film structure using low-resistance materials such as molybdenum (Mo), titanium (Ti), copper (Cu), aluminum (Al), or silver (Ag) to reduce wiring resistance.

[0120] An interlayer insulating layer (ILD) may be provided and / or formed on the gate electrode (GE). A first connection electrode (CNE1) may be disposed on the interlayer insulating layer (ILD). The first connection electrode (CNE1) may be electrically connected to a first terminal (TE1) through a contact hole penetrating the gate insulating layer (GI) and the interlayer insulating layer (ILD).

[0121] A passivation layer (PVX) may be provided and / or formed on the first connection electrode (CNE1). A second connection electrode (CNE2) may be disposed on the passivation layer (PVX). The second connection electrode (CNE2) may be electrically connected to the first connection electrode (CNE1) through a contact hole penetrating the passivation layer (PVX).

[0122] The passivation layer (PVX) may be provided in the form of a composite insulating film disposed on an organic insulating film or an organic insulating film disposed on an inorganic insulating film. The inorganic insulating film may include, for example, at least one of a metal oxide such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), and aluminum oxide (AlOx). The organic insulating film may include, for example, at least one of a polyacrylate resin, an epoxy resin, a phenol resin, a polyamide resin, a polyimide resin, an unsaturated polyester resin, a polyphenylene ether resin, a polyphenylene sulfide resin, and a benzocyclobutene resin.

[0123] The via layer (VIA) may be provided and / or formed entirely on the passivation layer (PVX). The via layer (VIA) may be an inorganic insulating film including an inorganic material or an organic insulating film including an organic material.

[0124] A display element layer (DPL) may be disposed on a via layer (VIA). The display element layer (DPL) may include a light emitting element (LD) and a pixel defining layer (PDL). The light emitting element (LD) and the pixel defining layer (PDL) may be provided and / or formed on the via layer (VIA). The light emitting element (LD) may include a first light emitting element (LD1) disposed in a first sub-pixel area (SPA1), a second light emitting element (LD2) disposed in a second sub-pixel area (SPA2), and a third light emitting element (LD3) disposed in a third sub-pixel area (SPA3).

[0125] Each of the light-emitting elements (LD) may include a first pixel electrode (AE), an organic light-emitting portion (EL), and a second pixel electrode (CE). The light-emitting element (LD) may be electrically connected to a pixel circuit of the corresponding pixel (e.g., the pixel circuit (PXC) of FIG. 6).

[0126] A first pixel electrode (AE) may be provided and / or formed on a via layer (VIA) of the corresponding pixel. The first pixel electrode (AE) may be an anode electrode of a light emitting element (LD). The first pixel electrode (AE) may be electrically connected to a first terminal (TE1) through a corresponding contact portion. In embodiments, the first pixel electrode (AE) may include anode electrodes corresponding to the first to third sub-pixel areas (SPA1 to SPA3). The first pixel electrode (AE) may be patterned to correspond to (or overlap) the first to third sub-pixel areas (SPA1 to SPA3).

[0127] Each of the first pixel electrodes (AE) may be made of a conductive material (or materials). The conductive material may include an opaque metal. For example, the opaque metal may include metals such as silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), and alloys thereof. However, the material of each of the first pixel electrodes (AE) is not limited to the above-described embodiments. According to embodiments, the first pixel electrodes (AE) may include a transparent conductive material (or materials). The transparent conductive material (or material) may include conductive oxides such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnOx), indium gallium zinc oxide (IGZO), and indium tin zinc oxide (ITZO), and conductive polymers such as poly(3,4-ethylenedioxythiophene) (PEDOT). When the first pixel electrode (AE) includes a transparent conductive material (or material), a separate conductive layer made of an opaque metal may be added to reflect light emitted from the organic light-emitting portion (EL) in the image display direction (or encapsulation layer (TFE)) of the display device (e.g., the display device (DD) of FIG. 1).

[0128] A pixel defining layer (PDL) can define (or partition) an area where an organic light-emitting element (EL) is arranged. The pixel defining layer (PDL) can be an organic insulating layer made of an organic material. In one embodiment, the pixel defining layer (PDL) can include a light-absorbing material or a light absorbing agent can be applied to absorb light introduced from the outside. For example, the pixel defining layer (PDL) can include a carbon-based black pigment. However, the embodiments are not limited thereto.

[0129] A pixel defining layer (PDL) is partially opened to include an opening (not shown) (or a second opening) exposing a region of a first pixel electrode (AE), and may protrude in a third direction (DR3) from a via layer (VIA) along a perimeter of a sub-pixel area (SPA). The pixel defining layer (PDL) may be disposed on the via layer (VIA) to define a region in which an organic light-emitting element (EL) is disposed and received on the first pixel electrode (AE). An organic light-emitting element (EL) may be disposed on the first pixel electrode (AE) exposed by the opening of the pixel defining layer (PDL).

[0130] The organic light-emitting element (EL) may have a multilayer thin film structure including a light generation layer that generates light. The organic light-emitting element (EL) may emit one of red light, green light, and blue light, but embodiments are not limited thereto. For example, the organic light-emitting element (EL) may include a white light-emitting layer that emits white light. The internal design of the organic light-emitting element (EL) may also vary depending on the color of light to be implemented.

[0131] A second pixel electrode (CE) may be arranged on the organic light-emitting element (EL) and the pixel defining layer (PDL). The second pixel electrode (CE) may be provided in a plate shape over the entire area of ​​the display area (DA).

[0132] The second pixel electrode (CE) may be a thin-film metal layer having a thickness sufficient to transmit light emitted from the organic light-emitting portion (EL). The second pixel electrode (CE) may be formed of a metal material to have a relatively thin thickness or may be composed of a transparent conductive material. The second pixel electrode (CE) includes at least one of various transparent conductive materials including indium tin oxide, indium zinc oxide, indium tin zinc oxide, aluminum zinc oxide, gallium zinc oxide, zinc tin oxide, or gallium tin oxide, and may be implemented to be substantially transparent or translucent to satisfy a predetermined light transmittance. Accordingly, light emitted from the organic light-emitting portion (EL) located below the second pixel electrode (CE) may pass through the second pixel electrode (CE) and be emitted upwardly toward the encapsulation layer (TFE).

[0133] An encapsulation layer (TFE) may be provided and / or formed over the entire surface of the second pixel electrode (CE). The encapsulation layer (TFE) may include first to third encapsulation layers (EN1 to EN3) sequentially positioned on the second pixel electrode (CE). The first encapsulation layer (EN1) and the third encapsulation layer (EN3) may be inorganic layers including an inorganic material, and the second encapsulation layer (EN2) may be an organic layer including an organic material. The first encapsulation layer (EN1) and the third encapsulation layer (EN3) may protect the sub-pixel (SPX) from moisture and oxygen. The second encapsulation layer (EN2) may protect the sub-pixel (SPX) from foreign substances such as dust particles.

[0134] A light conversion layer (LCL) may be disposed on the encapsulation layer (TFE). In embodiments, the light conversion layer (LCL) may be disposed on the third encapsulation layer (EN3) of the encapsulation layer (TFE). The light conversion layer (LCL) may include a bank (BNK), a first capping layer (CAP1) (or a second layer of the light conversion layer (LCL)), a color conversion layer (CCL) (or a first layer of the light conversion layer (LCL)), a low refractive layer (LRL), and a second capping layer (CAP2) (or a third layer of the light conversion layer (LCL)).

[0135] The color conversion layer (CCL) may be arranged in an area overlapping the first to third sub-pixel areas (SPA1 to SPA3). The color conversion layer (CCL) may include first to third color conversion layers (CCL1 to CCL3) corresponding to (or overlapping) the first to third sub-pixel areas (SPA1 to SPA3), respectively. The first color conversion layer (CCL1) may be arranged in the first sub-pixel area (SPA1), the second color conversion layer (CCL2) may be arranged in the second sub-pixel area (SPA2), and the third color conversion layer (CCL3) may be arranged in the third sub-pixel area (SPA3).

[0136] The color conversion layer (CCL) may include color conversion particles (QD) (or wavelength conversion particles or quantum dot particles). For example, the color conversion layer (CCL) may include color conversion particles (QD) that convert light of a first color (or a first wavelength band) incident from a light emitting element (LD) into light of a second color (or a specific color, a second wavelength band) and emit the converted light. For example, the color conversion layer (CCL) may be formed through a photolithography process. However, the embodiments are not limited to the method of forming the color conversion layer.

[0137] In one embodiment, the first to third sub-pixel areas (SPA1 to SPA3) may include first to third light-emitting elements (LD1 to LD3) that emit light of the same color. For example, the first to third light-emitting elements (LD1 to LD3) may emit light of a third color (or blue). By arranging first to third color conversion layers (CCL1 to CCL3) each including color conversion particles on the first to third sub-pixel areas (SPA1 to SPA3), a full-color image can be displayed.

[0138] The first color conversion layer (CCL1) may include first color conversion particles that convert light of a third color emitted from the first light-emitting element (LD1) into light of a first color (or red light). For example, the first color conversion layer (CCL1) may include first quantum dot particles (QD) dispersed within a predetermined matrix material, such as a base resin. The first quantum dot particles (QD) of the first color conversion layer (CCL1) may absorb blue light and shift the wavelength according to energy transition to emit red light.

[0139] The second color conversion layer (CCL2) may include second color conversion particles that convert third color light emitted from the second light-emitting element (LD2) into second color light (or green light). For example, the second color conversion layer (CCL2) may include second quantum dot particles (QD) dispersed within a predetermined matrix material, such as a base resin. The second quantum dot particles (QD) of the second color conversion layer (CCL2) may absorb blue light and shift the wavelength according to energy transition to emit green light.

[0140] The third color conversion layer (CCL3) may be provided to efficiently utilize the third color (or blue) light emitted from the third light-emitting element (LD3). For example, when the third light-emitting element (LD3) is a blue light-emitting element that emits blue light and the third sub-pixel area (SPA3) is a blue sub-pixel area, the third color conversion layer (CCL3) may include at least one type of scatterer (SCT) to efficiently utilize the light emitted from the third light-emitting element (LD3).

[0141] The first capping layer (CAP1) can cover the color conversion layer (CCL). For example, the first capping layer (CAP1) can be disposed over the entire surface of the color conversion layer (CCL). The first capping layer (CAP1) can prevent moisture or foreign substances from penetrating into the color conversion layer (CCL). The first capping layer (CAP1) can include an inorganic material.

[0142] In one embodiment, a low-refractive layer (LRL) may be disposed on the first capping layer (CAP1). The low-refractive layer (LRL) may control the path of light emitted from the lower portion of the color conversion layer (CCL) (or the display element layer (DPL)). For example, the low-refractive layer (LRL) may change the path of light incident at an angle to a direction perpendicular to the planarization layer (OC). The low-refractive layer (LRL) may include a polymer material and a silica-based material.

[0143] In one embodiment, the second capping layer (CAP2) may cover the low-refractive layer (LRL). For example, the second capping layer (CAP2) may be disposed on the low-refractive layer (LRL). The second capping layer (CAP2) may prevent moisture or foreign substances from penetrating into the low-refractive layer (LRL). The second capping layer (CAP2) may include an inorganic material.

[0144] The bank (BNK) may be disposed on the second capping layer (CAP2). The bank (BNK) may be disposed between or at a boundary between the first to third sub-pixel areas (SPA1 to SPA3) (or the first to third sub-pixels (SPX1 to SPX3) of FIG. 1). For example, the bank (BNK) may define a boundary of the color conversion layers (CCL).

[0145] A bank (BNK) can define first to third sub-pixel areas (SPA1 to SPA3) and a non-emission area (NEA). The first to third sub-pixel areas (SPA1 to SPA3) are areas corresponding to (or overlapping) areas between the banks (BNK), and the non-emission area (NEA) can be an area corresponding to (or overlapping) the bank (BNK).

[0146] In one embodiment, the non-emissive area (NEA) may be an area corresponding to an area where a bank (BNK) is arranged. When viewed in a plan view, the bank (BNK) may surround the first to third sub-pixel areas (SPA1 to SPA3).

[0147] The bank (BNK) may include an organic material such as an acrylate resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, a polyester resin, a polyphenylenesulfides resin, or a benzocyclobutene (BCB). However, the embodiments are not limited thereto, and the bank (BNK) may include various types of inorganic materials including silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), aluminum nitride (AlNx), aluminum oxide (AlOx), zirconium oxide (ZrOx), hafnium oxide (HfOx), or titanium oxide (TiOx).

[0148] The bank (BNK) may include at least one light-shielding and / or reflective material. Accordingly, light leakage between adjacent sub-pixels may be prevented or blocked by the bank (BNK). For example, the bank (BNK) may include a black pigment, but embodiments are not limited thereto.

[0149] The bank (BNK) can be used to define the boundary of the color conversion layers. In addition, the bank (BNK) can be used to define the area where light of each color is emitted (e.g., the first to third sub-pixel areas (SPA1 to SPA3)). If the area where light of each color is emitted (e.g., the first to third sub-pixel areas (SPA1 to SPA3)) is defined by the color filter (CF), the color filter (CF) in the non-emission area (NEA) can only be used to block light. However, since the bank (BNK) is used to define the area where light of each color is emitted (e.g., the first to third sub-pixel areas (SPA1 to SPA3)), the design of the color filter (CF) in the non-emission area (NEA) can be relatively free. For example, one or two layers of color filters (CF) can be used in the non-emission area (NEA).

[0150] A detailed description of the color filter layer (CLF) is provided below with reference to FIG. 10.

[0151] Fig. 10 is a cross-sectional view schematically showing the light conversion layer and color filter layer of Fig. 9.

[0152] Referring to FIG. 10, a color filter layer (CFL) may be disposed on a light conversion layer (LCL). In embodiments, the color filter layer (CFL) may be disposed on a second capping layer (CAP2) in a sub-pixel area (SPA), and on a bank (BNK) in a non-emission area (NEA). The color filter layer (CFL) may include color filters (CF) and a planarization layer (OC). The color filters (CF) may include first to third color filters (CF1 to CF3) corresponding to first to third sub-pixel areas (SPA1 to SPA3), respectively. The color filters (CF) may be in contact with the second capping layer (CAP2) in the sub-pixel area (SPA) and may be disposed on the second capping layer (CAP2). For example, the first to third color filters (CF1 to CF3) may be formed by a photolithography process.

[0153] In one embodiment, the first color filter (CF1), the second color filter (CF2), and the third color filter (CF3) may be a red color filter, a green color filter, and a blue color filter, respectively, but embodiments are not limited thereto.

[0154] In one embodiment, the first color filter (CF1) is disposed on the second capping layer (CAP2) corresponding to (or overlapping) the first sub-pixel area (SPA1) and can selectively transmit light emitted from the first light-emitting element (LD1) and the first color conversion layer (CCL1). In embodiments, the first color filter (CF1) can overlap the first color conversion layer (CCL1) in the third direction (DR3). The first color filter (CF1) can include a color material that selectively transmits light of the first color (or, red). For example, when the first sub-pixel area (SPA1) is a red sub-pixel area, the first color filter (CF1) can include a red color filter material.

[0155] In one embodiment, the second color filter (CF2) is disposed on the second capping layer (CAP2) corresponding to (or overlapping) the second sub-pixel area (SPA2) and can selectively transmit light emitted from the second light-emitting element (LD2) and the second color conversion layer (CCL2). In embodiments, the second color filter (CF2) can overlap the second color conversion layer (CCL2) in the third direction (DR3). The second color filter (CF2) can include a color filter material that selectively transmits light of a second color (or green). For example, when the second sub-pixel area (SPA2) is a green sub-pixel area, the second color filter (CF2) can include a green color filter material.

[0156] In one embodiment, the third color filter (CF3) is disposed on the second capping layer (CAP2) corresponding to (or overlapping) the third sub-pixel area (SPA3) and can selectively transmit light emitted from the third light-emitting element (LD3) and the third color conversion layer (CCL3). In embodiments, the third color filter (CF3) can overlap the third color conversion layer (CCL3) in the third direction (DR3). The third color filter (CF3) can include a color filter material that selectively transmits light of a second color (or blue). For example, when the third sub-pixel area (SPA3) is a blue sub-pixel area, the third color filter (CF3) can include a blue color filter material.

[0157] In one embodiment, a planarization layer (OC) may be disposed on the first to second color filters (CF1 to CF3). The planarization layer (OC) may cover the first to third color filters (CF1 to CF3). The planarization layer (OC) is not limited to a material having excellent planarization characteristics and light transmittance, but may include an organic material or an inorganic material.

[0158] In one embodiment, a second color filter (CF2) may be positioned in the non-emissive area (NEA). For example, the second color filter (CF2) may be positioned on the bank (BNK) in the non-emissive area (NEA). For example, the transmittance of the second color filter (CF2) may be lower than the transmittance of the first color filter (CF1) and the transmittance of the third color filter (CF3).

[0159] For convenience of explanation, assume that the second color is green. The human eye is more sensitive to green than to red and blue. Therefore, reducing the transmittance of the green color filter is most effective in reducing the reflectance of the display panel (DP, see Fig. 1). For example, the transmittance of the second color filter (CF2) can be reduced by changing the material of the second color filter (CF2).

[0160] However, when the transmittance of the green color filter is reduced, the color of the reflected light (i.e., the reflected color) due to external light may appear closer to magenta. Therefore, by placing the green color filter in the non-emitting area (NEA), the green ratio of the reflected light can be increased and the reflected color can be controlled. However, in the present specification, the reason for appearing close to magenta is not necessarily limited to the transmittance. For example, even if the transmittance of the first to third color filters (CF1, CF2, CF3) is the same, if the reflected color appears close to magenta, the second color filter (CF2) may be placed in the non-emitting area (NEA).

[0161] Additionally, by placing only the second color filter (CF2) in the non-emissive area (NEA), the thickness of the planarization layer (OC) can be reduced. Accordingly, the production cost of the display device (DD, see FIG. 1) can be reduced.

[0162] Fig. 11 is a cross-sectional view schematically illustrating the thickness of the bank of Fig. 10.

[0163] Referring to FIG. 11, the thickness (BNK_D) of the bank (BNK) may be determined based on the color of the reflected light. For example, as the thickness (BNK_D) of the bank (BNK) becomes thinner, the reflected light may be relatively reduced. Accordingly, the bank (BNK) may be formed to a thin thickness in order to somewhat reduce the increase in the proportion of the second color by the second color filter (CF2) of the non-emissive area (NEA).

[0164] FIGS. 12 and 13 are cross-sectional views schematically showing a light conversion layer and a color filter layer of a display device according to embodiments.

[0165] The color filter layer (CFL) according to the present embodiments is substantially the same as the configuration of the color filter layer of FIG. 10, except for the color filter (CF) disposed in the non-emitting area (NEA), and therefore the same reference numbers and reference symbols are used for the same or similar components, and redundant descriptions are omitted for convenience of explanation.

[0166] Referring to FIGS. 12 and 13, the color filter (CF) positioned in the non-emissive area (NEA) may vary depending on the reflected color. For example, as shown in FIG. 12, if the reflected color is close to cyan, a first color filter (CF1) may be positioned in the non-emissive area (NEA). For example, as shown in FIG. 13, if the reflected color is close to yellow, a third color filter (CF3) may be positioned in the non-emissive area (NEA).

[0167] Fig. 14 is a cross-sectional view schematically showing a light conversion layer and a color filter layer of a display device according to embodiments.

[0168] The light conversion layer (LCL) according to the present embodiments is substantially the same as the configuration of the light conversion layer of FIG. 10, except that it does not include a low refractive layer (LRL, see FIG. 10) and a second capping layer (CAP2, see FIG. 10). Therefore, the same reference numbers and reference symbols are used for the same or similar components, and redundant descriptions are omitted for convenience of explanation.

[0169] Referring to FIG. 14, the bank (BNK) may be disposed on the first capping layer (CAP1), and the color filter (CF) may be disposed on the first capping layer (CAP1) in the sub-pixel area (SPA). For example, the color filters (CF) may be in contact with the first capping layer (CAP1) in the sub-pixel area (SPA) and may be disposed on the first capping layer (CAP1).

[0170] Figures 15 to 17 are cross-sectional views schematically showing a light conversion layer and a color filter layer of a display device according to embodiments.

[0171] The color filter layer (CFL) according to the present embodiments is substantially the same as the configuration of the color filter layer of FIG. 10, except for the color filter (CF) disposed in the non-emitting area (NEA), and therefore the same reference numbers and reference symbols are used for the same or similar components, and redundant descriptions are omitted for convenience of explanation.

[0172] Referring to FIGS. 15 to 17, the color filter (CF) positioned in the non-emissive area (NEA) may vary depending on the reflected color. For example, the color filter (CF) positioned in the non-emissive area (NEA) may vary depending on the color of the reflected light.

[0173] For example, as shown in Fig. 15, when the reflected color appears close to blue, a first color filter (CF1) and a second color filter (CF2) may be placed in the non-emissive area (NEA).

[0174] In this embodiment, the first color filter (CF1) is arranged on the second color filter (CF2) in the non-emissive area (NEA), but the embodiments are not limited thereto. For example, the second color filter (CF2) may be arranged on the first color filter (CF1).

[0175] For example, as shown in Fig. 16, when the reflected color appears close to red, a second color filter (CF2) and a third color filter (CF3) may be placed in the non-emissive area (NEA).

[0176] In this embodiment, the third color filter (CF3) is exemplified as being positioned on the second color filter (CF2) in the non-emissive area (NEA), but the embodiments are not limited thereto. For example, the second color filter (CF2) may be positioned on the third color filter (CF3).

[0177] For example, as shown in Fig. 17, when the reflected color appears close to green, the first color filter (CF1) and the third color filter (CF3) may be placed in the non-emissive area (NEA).

[0178] In this embodiment, the third color filter (CF3) is exemplified as being positioned on the first color filter (CF1) in the non-emissive area (NEA), but the embodiments are not limited thereto. For example, the first color filter (CF1) may be positioned on the third color filter (CF3).

[0179] Fig. 18 is a flowchart showing a method for manufacturing a display device according to embodiments.

[0180] Referring to FIG. 18, a method for manufacturing a display device (DD) may include providing a substrate (SUB) including first to third sub-pixel areas (SPA1, SPA2, SPA3) and a non-emitting area (NEA) corresponding to a boundary of the first to third sub-pixel areas (SPA1, SPA2, SPA3) (S100), forming a display element layer (DPL) including light-emitting elements (LD) arranged in each of the first to third sub-pixel areas (SPA1, SPA2, SPA3) on the substrate (SUB) (S200), forming a light conversion layer (LCL) on the display element layer (DPL) (S300), and forming a color filter layer (CFL) including first to third color filters (CF1, CF2, CF3) on the light conversion layer (LCL) (S400).

[0181] Figures 19 to 23 are drawings schematically showing step S300 of Figure 18.

[0182] Referring to Fig. 19, a color conversion layer (CCL) may be formed on an encapsulation layer (TFE) formed on a display element layer (DPL). For example, the color conversion layer (CCL) may be formed through a photolithography process.

[0183] A first color conversion layer (CCL1) may be disposed in a first sub-pixel area (SPA1), a second color conversion layer (CCL2) may be disposed in a second sub-pixel area (SPA2), and a third color conversion layer (CCL3) may be disposed in a third sub-pixel area (SPA3).

[0184] Referring to FIG. 20, the first capping layer (CAP1) may be formed to cover the color conversion layer (CCL). For example, the first capping layer (CAP1) may be disposed over the entire surface of the color conversion layer (CCL).

[0185] Referring to FIGS. 21 and 22, a low refractive layer (LRL) may be formed on a first capping layer (CAP1). And, a second capping layer (CAP2) may be formed on the low refractive layer (LRL).

[0186] For example, the steps of forming the low refractive layer (LRL) and the second capping layer (CAP2) may be omitted. For example, the bank (BNK, see FIG. 23) may be formed in a non-emissive area (NEA, see FIG. 10) on the first capping layer (CAP1), and the color filter (CF, see FIG. 24) may be formed in a sub-pixel area (SPA, see FIG. 10) on the first capping layer (CAP1).

[0187] Referring to FIG. 23, a bank (BNK) may be formed in a non-emitting area (NEA, see FIG. 10) on a first capping layer (CAP1). In addition, a second color filter (CF2, see FIG. 24) may be formed on the bank (BNK).

[0188] Figures 24 and 25 are drawings schematically showing step S400 of Figure 18.

[0189] Referring to FIGS. 24 and 25, a color filter (CF) may be formed in a sub-pixel area (SPA, see FIG. 10) on a second capping layer (CAP2). In addition, the second color filter (CF2) may be formed on a bank (BNK) in a non-emission area (NEA, see FIG. 10). A planarization layer (OC) may be disposed on the color filter (CF).

[0190] Although specific embodiments and applications have been described herein, they are provided solely to aid in a more general understanding of the present disclosure, and those skilled in the art will understand that the embodiments are not limited to the embodiments described above and that various modifications, additions, and substitutions are possible.

[0191] Therefore, the spirit of this specification should not be limited to the described embodiments, and all things that are equivalent or equivalent to the following claims as well as the claims are considered to fall within the scope of the spirit of this specification.

[0192] This specification can be applied to display devices and electronic devices including them. For example, this specification can be applied to digital TVs, 3D TVs, mobile phones, smart phones, tablet computers, VR devices, PCs, home electronic devices, laptop computers, PDAs, PMPs, digital cameras, music players, portable game consoles, navigation systems, and the like.

[0193] Although the present invention has been described with reference to the above embodiments, it will be understood by those skilled in the art that various modifications and changes can be made to the present invention without departing from the spirit and scope of the present invention as set forth in the claims below.

Claims

1. A substrate including first, second, and third sub-pixel regions and a non-luminous region corresponding to a boundary between the first, second, and third sub-pixel regions; A display element layer including light-emitting elements arranged in each of the first, second, and third sub-pixel areas on the substrate; A light conversion layer disposed on the display element layer and including a bank disposed in the non-light-emitting region; and A color filter layer is disposed on the light conversion layer and includes first, second, and third color filters, A display device characterized in that one of the first, second, and third color filters is arranged in the non-luminous area.

2. In the first paragraph, the light conversion layer A first layer disposed in the first, second, and third sub-pixel areas; and Further comprising a second layer covering the first layer, A display device, characterized in that the above bank is arranged in the non-luminous area on the second layer.

3. A display device according to claim 2, characterized in that at least one of the first, second, and third color filters is in contact with the second layer.

4. In the second paragraph, the light conversion layer a low refractive layer disposed on the second layer; and A display device characterized by further comprising a third layer covering the above low refractive layer.

5. A display device according to claim 4, characterized in that at least one of the first, second, and third color filters is in contact with the third layer.

6. A display device according to claim 2, characterized in that the first layer is formed by a photolithography process.

7. A display device according to claim 1, characterized in that the first, second, and third color filters are formed by a photolithography process.

8. A substrate including first, second, and third sub-pixel regions and a non-luminous region corresponding to a boundary of the first, second, and third sub-pixel regions; A display element layer including light-emitting elements arranged in each of the first, second, and third sub-pixel areas on the substrate; A light conversion layer disposed on the display element layer and including a bank disposed in the non-light-emitting region; and A color filter layer is disposed on the light conversion layer and includes first, second, and third color filters, A display device characterized in that two of the first, second, and third color filters are arranged in the non-luminous area.

9. In the 8th paragraph, the first and second color filters are arranged in the non-luminous area, A display device, characterized in that the first color filter is arranged on the second color filter in the non-emitting area.

10. In the 9th paragraph, the light conversion layer A first layer disposed in the first, second, and third sub-pixel areas; and Further comprising a second layer covering the first layer, A display device, characterized in that the above bank is arranged in the non-luminous area on the second layer.

11. A display device according to claim 10, characterized in that at least one of the first, second, and third color filters is in contact with the second layer.

12. In the 10th paragraph, the light conversion layer a low refractive layer disposed on the second layer; and A display device characterized by further comprising a third layer covering the above low refractive layer.

13. A display device according to claim 12, characterized in that at least one of the first, second, and third color filters is in contact with the third layer.

14. A display device according to claim 10, characterized in that the first layer is formed by a photolithography process.

15. A display device according to claim 8, characterized in that the first, second, and third color filters are formed by a photolithography process.

16. A step of providing a substrate including first, second, and third sub-pixel regions and a non-luminous region corresponding to a boundary of the first, second, and third sub-pixel regions; A step of forming a display element layer on the substrate, the display element layer including light-emitting elements arranged in each of the first, second, and third sub-pixel areas on the substrate; A step of forming a light conversion layer including a bank arranged in the non-light-emitting region on the display element layer; and Comprising a step of forming a color filter layer including first, second, and third color filters on the light conversion layer, The step of forming the above color filter layer is A method for manufacturing a display device, comprising the step of forming one of the first, second, and third color filters in the non-luminous area on the bank.

17. In the 16th paragraph, the step of forming the light conversion layer is A step of forming a first layer in the first, second, and third sub-pixel areas; and Comprising a step of forming a second layer covering the first layer, A method for manufacturing a display device, characterized in that the bank is formed in the non-light-emitting area on the second layer.

18. In the 17th paragraph, the step of forming the light conversion layer is a step of forming a low refractive layer on the second layer; and Further comprising a step of forming a third layer covering the above low refractive layer, A method for manufacturing a display device, characterized in that at least one of the first, second, and third color filters is in contact with the third layer.

19. A method for manufacturing a display device according to claim 17, characterized in that the first layer is formed by a photolithography process.

20. A method for manufacturing a display device according to claim 16, characterized in that the first, second, and third color filters are formed by a photolithography process.

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