Solar cell and preparation method therefor, photovoltaic module and photovoltaic system

Abstract

The present application relates to a solar cell and a preparation method therefor, a photovoltaic module and a photovoltaic system. The solar cell (1) comprises: an intrinsic semiconductor substrate (111), comprising an intrinsic region (111a), a first surface (111b) and a second surface (111c), the first surface (111b) and the second surface (111c) being provided on two opposite sides of the intrinsic semiconductor substrate (111), and the intrinsic region (111a) being provided between the first surface (111b) and the second surface (111c); a first doping structure (112) having a first doping type, the first doping structure (112) being provided on the side of the intrinsic region (111a) close to the first surface (111b); and a second doping structure (113) having a second doping type, the second doping structure (113) being provided on the side of the intrinsic region (111a) close to the second surface (111c), wherein the first doping type is opposite to the second doping type, and the first doping structure (112), the intrinsic region (111a) and the second doping structure (113) form a p-i-n structure.

Description

Solar cell and preparation method thereof, photovoltaic module, and photovoltaic system

[0001] Related applications

[0002] This application claims priority to Chinese patent application No. 2024100846697, filed on January 19, 2024, entitled “Solar cells and methods for preparing the same, photovoltaic modules, and photovoltaic systems,” the entire text of which is hereby incorporated by reference. Technical Field

[0003] The present application relates to the field of solar cell technology, and in particular to a solar cell and a preparation method thereof, a photovoltaic module, and a photovoltaic system. Background Art

[0004] Solar cells are devices that convert light energy directly into electrical energy through the photoelectric effect. Generally speaking, solar cells are manufactured on semiconductor wafers or substrates using semiconductor processing techniques to form a pn junction near the substrate's surface.

[0005] The silicon substrate for solar cells is generally p-type or n-type. Regardless of whether the substrate is p-type or n-type, relevant elements are doped during the growth of the silicon single crystal. Due to the complex growth process of silicon single crystals, the distribution of doped elements in the radial or longitudinal direction of the silicon single crystal varies, resulting in different resistivities for silicon wafers cut from a single silicon rod. Furthermore, for a single silicon wafer, the resistivity can also vary from the center to the edge of the wafer. This not only complicates the solar cell manufacturing process but also affects the solar cell conversion efficiency.

[0006] Summary of the Invention

[0007] Based on this, it is necessary to provide a solar cell and its preparation method, photovoltaic module, and photovoltaic system to address the above problems.

[0008] In a first aspect, an embodiment of the present application provides a solar cell, comprising:

[0009] An intrinsic semiconductor substrate, comprising an intrinsic region, a first surface and a second surface, wherein the first surface and the second surface are arranged on opposite sides of the intrinsic semiconductor substrate, and the intrinsic region is arranged between the first surface and the second surface;

[0010] a first doping structure having a first doping type, the first doping structure being disposed on a side of the intrinsic region close to the first surface; and

[0011] a second doping structure having a second doping type, the second doping structure being disposed on a side of the intrinsic region close to the second surface;

[0012] The first doping type and the second doping type are opposite to each other, and the first doping structure, the intrinsic region and the second doping structure form a pin structure.

[0013] In one embodiment, the resistivity of the intrinsic region is greater than 100Ω·cm;

[0014] And / or, the doping concentration of the p-type dopant in the intrinsic region is less than or equal to 1.3×10 14 ㎝ -3 , and the doping concentration of the n-type dopant in the intrinsic region is less than or equal to 4.4×10 13 ㎝ -3 .

[0015] In one embodiment, the thickness of the intrinsic semiconductor substrate is between 50 μm and 300 μm.

[0016] In one embodiment, the doping concentration of the first doping structure is between 3×10 18 ㎝ -3 -5×10 20 ㎝ -3 ;

[0017] And / or, the doping concentration of the second doping structure is between 3×10 18 ㎝ -3 -5×10 20 ㎝ -3 .

[0018] In one embodiment, a first dimension is defined between a side of the first doping structure close to the first surface and a side of the first doping structure away from the first surface, and the first dimension is between 5 nm and 5000 nm.

[0019] And / or, a second dimension is present between a side of the second doping structure close to the first surface and a side of the second doping structure away from the first surface, and the second dimension is between 5 nm and 5000 nm.

[0020] In one embodiment, the solar cell further includes a third doping structure, the third doping structure having the second doping type and being disposed on a side of the first doping structure away from the intrinsic region;

[0021] The third doping structure and the first doping structure form a pn junction.

[0022] In one embodiment, the solar cell further includes a fourth doping structure, the fourth doping structure having the first doping type and being disposed on a side of the second doping structure away from the intrinsic region;

[0023] The fourth doping structure and the second doping structure form a pn junction.

[0024] In one embodiment, the first doping structure is embedded in the intrinsic semiconductor substrate and located between the intrinsic region and the first surface.

[0025] In one embodiment, the second doping structure is embedded in the intrinsic semiconductor substrate and located between the intrinsic region and the second surface.

[0026] In one embodiment, the second doping structure is disposed on a side of the second surface away from the first surface.

[0027] In one embodiment, the solar cell further includes a first tunneling layer, the first tunneling layer is disposed on the second surface, and the second doping structure is disposed on a side of the first tunneling layer away from the first surface.

[0028] In one embodiment, the solar cell further comprises:

[0029] a first passivation anti-reflection layer, provided on a side of the first doping structure away from the intrinsic region;

[0030] a first electrode, disposed on a side of the first doped structure away from the second doped structure, penetrating the first passivation anti-reflection layer and electrically connected to the first doped structure;

[0031] a second passivation anti-reflection layer, disposed on a side of the second doped structure away from the intrinsic region; and

[0032] The second electrode is provided on a side of the second doping structure away from the first doping structure, passes through the second passivation anti-reflection layer and is electrically connected to the second doping structure.

[0033] In one embodiment, the first doping structure is disposed on a side of the first surface away from the second surface.

[0034] In one embodiment, the second doping structure is disposed on a side of the second surface away from the first surface.

[0035] In one embodiment, the solar cell further comprises: a first intrinsic semiconductor layer, the first intrinsic semiconductor layer being disposed on the first surface, the first doping structure being disposed on a side of the first intrinsic semiconductor layer away from the second surface; and

[0036] A second intrinsic semiconductor layer is provided on the second surface, and the second doping structure is provided on a side of the second intrinsic semiconductor layer away from the first surface.

[0037] In one embodiment, the solar cell further comprises:

[0038] a first transparent conductive layer, disposed on a side of the first doped structure away from the first intrinsic semiconductor layer;

[0039] a first electrode, disposed on a side of the first transparent conductive layer away from the first intrinsic semiconductor layer and electrically connected to the first transparent conductive layer;

[0040] a second transparent conductive layer, disposed on a side of the second doped structure away from the second intrinsic semiconductor layer; and

[0041] The second electrode is disposed on a side of the second transparent conductive layer away from the second intrinsic semiconductor layer and is electrically connected to the second transparent conductive layer.

[0042] In one embodiment, the solar cell further comprises:

[0043] a second tunneling layer, wherein the second tunneling layer is provided on the first surface, and the first doping structure is provided on a side of the second tunneling layer away from the second surface; and

[0044] A third tunneling layer is provided on the second surface, and the second doping structure is provided on a side of the third tunneling layer away from the first surface.

[0045] In a second aspect, an embodiment of the present application provides another solar cell, comprising:

[0046] An intrinsic semiconductor substrate having a first surface and a second surface opposite to each other; a first conductive region and a second conductive region arranged along a first direction are provided on the intrinsic semiconductor substrate, wherein the first direction is perpendicular to a thickness direction of the intrinsic semiconductor substrate;

[0047] a first passivation layer, disposed on the first surface and located in the first conductive area;

[0048] a second passivation layer, disposed on the first surface and located in the second conductive area;

[0049] a first doping structure having a first doping type and disposed on a side of the first passivation layer away from the intrinsic semiconductor substrate; and

[0050] a second doping structure having a second doping type and disposed on a side of the second passivation layer away from the intrinsic semiconductor substrate;

[0051] The first doping type and the second doping type are opposite to each other, and the first doping structure, the intrinsic semiconductor substrate and the second doping structure form a pin structure.

[0052] In one embodiment, the resistivity of the intrinsic semiconductor substrate is greater than 100Ω·cm;

[0053] And / or, the doping concentration of the p-type dopant in the intrinsic semiconductor substrate is less than or equal to 1.3×10 14 ㎝ -3 , and the doping concentration of the n-type dopant in the intrinsic semiconductor substrate is less than or equal to 4.4×10 13 ㎝ -3 .

[0054] In one embodiment, the thickness of the intrinsic semiconductor substrate is between 50 μm and 300 μm.

[0055] In one embodiment, the doping concentration of the first doping structure is between 3×10 18 ㎝ -3 -5×10 20 ㎝ -3 ;

[0056] And / or, the doping concentration of the second doping structure is between 3×10 18 ㎝ -3 -5×10 20 ㎝ -3 .

[0057] In one embodiment, a third dimension exists between a side of the first doping structure close to the first surface and a side of the first doping structure away from the first surface, and the third dimension is between 5 nm and 5000 nm.

[0058] And / or, a fourth dimension is present between a side of the second doping structure close to the first surface and a side of the second doping structure away from the first surface, and the fourth dimension is between 5 nm and 5000 nm.

[0059] In one embodiment, the solar cell further includes a third doping structure, the third doping structure having the second doping type and disposed on a side of the first doping structure away from the intrinsic semiconductor substrate;

[0060] The third doping structure and the first doping structure form a pn junction.

[0061] In one embodiment, the solar cell further includes a fourth doping structure, the fourth doping structure having the first doping type and disposed on a side of the second doping structure away from the intrinsic semiconductor substrate;

[0062] The fourth doping structure and the second doping structure form a pn junction.

[0063] In one embodiment, the first passivation layer and the second passivation layer are configured as tunnel dielectric layers;

[0064] And / or, the material of the first doping structure and the material of the second doping structure include polysilicon.

[0065] In one embodiment, the material of the first passivation layer and the material of the second passivation layer include intrinsic semiconductor materials;

[0066] And / or, the material of the first doping structure and the material of the second doping structure include microcrystalline silicon or amorphous silicon.

[0067] In one embodiment, the solar cell further comprises:

[0068] a first anti-reflection layer, disposed on a side of the first doped structure away from the intrinsic semiconductor substrate, and a side of the second doped structure away from the intrinsic semiconductor substrate;

[0069] a first electrode, disposed on a side of the first doped structure away from the intrinsic semiconductor substrate, penetrating the first anti-reflection layer and electrically connected to the first doped structure;

[0070] a second electrode, disposed on a side of the second doped structure away from the intrinsic semiconductor substrate, penetrating the first anti-reflection layer and electrically connected to the second doped structure;

[0071] a third passivation layer, disposed on the second surface; and

[0072] The second anti-reflection layer is arranged on a side of the third passivation layer away from the intrinsic semiconductor substrate.

[0073] In a third aspect, an embodiment of the present application provides a method for preparing a solar cell, comprising:

[0074] Providing an intrinsic semiconductor substrate, the intrinsic semiconductor substrate comprising an intrinsic region, a first surface and a second surface, wherein the first surface and the second surface are disposed on opposite sides of the intrinsic semiconductor substrate, and the intrinsic region is disposed between the first surface and the second surface;

[0075] A first doping structure and a second doping structure are formed on the intrinsic semiconductor substrate; the first doping structure has a first doping type and is arranged on a side of the intrinsic region close to the first surface; the second doping structure has a second doping type and is arranged on a side of the intrinsic region close to the second surface; the first doping type and the second doping type are opposite, and the first doping structure, the intrinsic region and the second doping structure constitute a pin structure.

[0076] In a fourth aspect, embodiments of the present application provide another method for preparing a solar cell, comprising:

[0077] Providing an intrinsic semiconductor substrate, the intrinsic semiconductor substrate having a first surface and a second surface disposed opposite to each other; the intrinsic semiconductor substrate being provided with a first conductive region and a second conductive region arranged along a first direction, the first direction being perpendicular to a thickness direction of the intrinsic semiconductor substrate;

[0078] forming a first passivation layer on the first surface, and forming a first doping structure on a side of the first passivation layer away from the intrinsic semiconductor substrate; the first passivation layer is located in the first conductive region, and the first doping structure has a first doping type;

[0079] A second passivation layer is formed on the first surface, and a second doping structure is formed on a side of the second passivation layer away from the intrinsic semiconductor substrate; the second passivation layer is located in the second conductive region, the second doping structure has a second doping type, the first doping type and the second doping type are opposite, and the first doping structure, the intrinsic semiconductor substrate and the second doping structure constitute a pin structure.

[0080] In a fifth aspect, an embodiment of the present application provides a photovoltaic assembly comprising the solar cell described in any one of the first and second aspects.

[0081] In a sixth aspect, an embodiment of the present application provides a photovoltaic system, comprising the photovoltaic component in the fifth aspect.

[0082] The details of one or more embodiments of the present application are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the present application will become apparent from the description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0083] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the conventional technology, the following briefly introduces the drawings required for use in the embodiments or the conventional technology descriptions. Obviously, the drawings described below are merely embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the disclosed drawings without any creative work.

[0084] FIG1 is a schematic diagram of a partial cross-sectional structure of a solar cell provided in one embodiment of the present application.

[0085] FIG2 is a schematic diagram of a partial cross-sectional structure of another solar cell provided in an embodiment of the present application.

[0086] FIG3 is a schematic diagram of a partial cross-sectional structure of another solar cell provided in an embodiment of the present application.

[0087] FIG4 is a schematic diagram of a partial cross-sectional structure of another solar cell provided in an embodiment of the present application.

[0088] FIG5 is a schematic diagram of a partial cross-sectional structure of another solar cell provided in an embodiment of the present application.

[0089] FIG6 is a schematic diagram of a partial cross-sectional structure of another solar cell provided in an embodiment of the present application.

[0090] FIG7 is a schematic diagram of a partial cross-sectional structure of another solar cell provided in an embodiment of the present application.

[0091] FIG8 is a schematic diagram of a partial cross-sectional structure of another solar cell provided in an embodiment of the present application.

[0092] FIG9 is a schematic flow chart of a method for preparing a solar cell according to an embodiment of the present application.

[0093] FIG10 is a schematic flow chart of a method for preparing a solar cell according to an embodiment of the present application.

[0094] Figure numerals: 1, solar cell; 111, semiconductor substrate; 111a, intrinsic region; 111b, first surface; 111c, second surface; 111d, first conductive region; 111e, second conductive region; 112, first doping structure; 113, second doping structure; 114, first tunneling layer; 115, first passivation anti-reflection layer; 116, second passivation anti-reflection layer; 117, first electrode; 118, second electrode; 119, first intrinsic semiconductor layer; 120, second intrinsic semiconductor layer; 121, first transparent conductive layer; 122, second transparent conductive layer; 123, second tunneling layer; 124, third tunneling layer; 125, first passivation layer; 126, second passivation layer; 127, first anti-reflection layer; 128, second anti-reflection layer; 129, third passivation layer; 130, third doping structure; 131, fourth doping structure. DETAILED DESCRIPTION

[0095] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0096] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application.

[0097] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to, or coupled to" another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer, or there can be intervening elements or layers. In contrast, when an element is referred to as being "directly on, directly adjacent to, directly connected to, or directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of the present application, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion.

[0098] Spatially relative terms such as "under," "beneath," "beneath," "under," "above," "above," etc., may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the drawings is turned over, the element or feature described as "under" or "beneath" or "beneath" the other elements will be oriented as "above" the other elements or features. Thus, the exemplary terms "under" and "under" can include both upper and lower orientations. In addition, the device can also include alternative orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0099] As used herein, the singular forms "a," "an," and "the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include," "comprising," "having," and the like specify the presence of stated features, integers, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof. Also, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.

[0100] Embodiments of the application are described herein with reference to cross-sectional views which are schematic illustrations of ideal embodiments (and intermediate structures) of the application, such that variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances are anticipated. Accordingly, embodiments of the application should not be limited to the specific shapes of the regions shown herein, but rather include deviations in shapes due to, for example, manufacturing techniques. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges, rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation occurs. Accordingly, the regions shown in the figures are schematic in nature, their shapes do not represent the actual shape of the region of the device, and do not limit the scope of the application.

[0101] In a first aspect, as shown in FIG1 , an embodiment of the present application provides a solar cell 1, which may be a PERT (Passivated Emitter Rear Totally-diffused) cell, a TOPCon (Tunnel Oxide Passivated Contact) cell, an SHJ (Silicon Hetero Junction) cell, a stacked cell, or the like.

[0102] Specifically, the solar cell 1 includes an intrinsic semiconductor substrate 111, a first doped structure 112, and a second doped structure 113. The intrinsic semiconductor substrate 111 includes an intrinsic region 111a, a first surface 111b, and a second surface 111c. The first surface 111b and the second surface 111c are disposed on opposite sides of the intrinsic semiconductor substrate 111, and the intrinsic region 111a is disposed between the first surface 111b and the second surface 111c. The first surface 111b may be one of the light-facing and backlight-facing surfaces of the solar cell 1, and the second surface 111c may be the other of the light-facing and backlight-facing surfaces of the solar cell 1.

[0103] Furthermore, the first doping structure 112 has a first doping type and is disposed on a side of the intrinsic region 111a close to the first surface 111b. The second doping structure 113 has a second doping type and is disposed on a side of the intrinsic region 111a close to the second surface 111c. The first doping type and the second doping type are opposite, and the first doping structure 112, the intrinsic region 111a, and the second doping structure 113 form a pin structure. It will be understood that, in one example, the first doping type is p-type and the second doping type is n-type. In an opposite example, the first doping type is n-type and the second doping type is p-type.

[0104] It should be noted that the first doping structure 112 and the second doping structure 113 can be doped regions disposed on the intrinsic semiconductor substrate 111, or can be film structures containing dopants. When at least one of the first doping structure 112 and the second doping structure 113 is a doped region disposed on the intrinsic semiconductor substrate 111, the intrinsic region 111a is a portion of the intrinsic semiconductor substrate 111. When both the first doping structure 112 and the second doping structure 113 are film structures containing dopants, the intrinsic region 111a is the entire region of the intrinsic semiconductor substrate 111.

[0105] The solar cell 1 provided in the embodiment of the present application comprises an intrinsic region 111a disposed on an intrinsic semiconductor substrate 111, and a first doping structure 112 and a second doping structure 113 disposed on opposite sides of the intrinsic region 111a, such that the first doping structure 112, the intrinsic region 111a, and the second doping structure 113 form a pin structure. Thus, compared to conventional techniques for fabricating solar cells 1 using p-type or n-type semiconductor substrates 111, the solar cell 1 provided in the embodiment of the present application utilizes an intrinsic semiconductor substrate 111 containing the intrinsic region 111a. Therefore, during the fabrication of the blank (e.g., silicon ingot) for the intrinsic semiconductor substrate 111, no p-type or n-type dopant is required. This reduces the complexity of the solar cell 1 fabrication process and facilitates silicon crystal growth, reducing dislocation density in the silicon crystal, increasing crystal pulling speed, and reducing defect density. Furthermore, after the silicon rods are cut into slices, there is no resistivity difference in the radial and longitudinal directions of the intrinsic silicon wafers. On the one hand, this is beneficial to improving the electrical consistency of the silicon wafers, thereby improving the conversion efficiency of the solar cell 1; on the other hand, it is beneficial to improving the utilization rate of the silicon rods, thereby reducing the manufacturing cost of the solar cell 1.

[0106] It should also be noted that the solar cell 1 provided in the embodiment of the present application is equivalent to having a pi junction and an in junction on both sides of the intrinsic semiconductor substrate 111. This structure can achieve a better carrier separation effect, thereby improving the photoelectric conversion efficiency of the solar cell 1. Specifically, compared to the substrate of a traditional solar cell 1, the intrinsic semiconductor substrate 111 in the embodiment of the present application includes an intrinsic region 111a, so the doping concentration of the intrinsic semiconductor substrate 111 is much lower than the doping concentration of the traditional substrate. Because the lower the doping concentration of the substrate, the deeper the built-in electric field of the solar cell 1 extends into the substrate, the built-in electric field of the solar cell 1 in the embodiment of the present application extends into the substrate at a deeper depth, and the influence range of the built-in electric field is larger, thereby improving the carrier separation effect.

[0107] In one embodiment, the resistivity of the intrinsic region 111a is greater than 100 Ω·cm. This effectively reduces the dopant content in the intrinsic region 111a. This helps increase the depth of the built-in electric field into the intrinsic semiconductor substrate 111, thereby enhancing carrier separation.

[0108] In one embodiment, the doping concentration of the p-type dopant in the intrinsic region 111a is less than or equal to 1.3×10 14 ㎝ -3 , and the doping concentration of the n-type dopant in the intrinsic region 111a is less than or equal to 4.4×10 13 ㎝ -3 This is equivalent to making the dopant content in the intrinsic region 111a extremely small, which is beneficial for increasing the depth of the built-in electric field extending into the intrinsic semiconductor substrate 111, thereby helping to improve the carrier separation effect.

[0109] In one embodiment, the thickness of the intrinsic semiconductor substrate 111 is between 50 μm and 300 μm. For example, the thickness of the intrinsic semiconductor substrate 111 can be 50 μm, 60 μm, 65 μm, 80 μm, 100 μm, 130 μm, 160 μm, 190 μm, 230 μm, 270 μm, 290 μm, 300 μm, or any two values ​​between the above. By ensuring that the thickness of the intrinsic semiconductor substrate 111 is within the above range, it is beneficial to reduce the thickness of the solar cell 1 and to form a stable PIN structure.

[0110] In one embodiment, the doping concentration of the first doping structure 112 is between 3×10 18 ㎝ -3 to 5×10 20 ㎝ -3 For example, the doping concentration of the first doping structure 112 may be 3×10 18 ㎝ -3 , 5×10 18 ㎝ -3 , 1×10 19 ㎝ -3 , 5×10 20 ㎝ -3 By making the doping concentration of the first doping structure 112 within the above range, it is beneficial to reduce the manufacturing cost on the one hand, and on the other hand, the first doping structure 112 can have better conductivity.

[0111] In one embodiment, the doping concentration of the second doping structure 113 is between 3×10 18 ㎝ -3 to 5×10 20 ㎝-3 For example, the doping concentration of the second doping structure 113 may be 3×10 18 ㎝ -3 , 5×10 18 ㎝ -3 , 1×10 19 ㎝ -3 , 5×10 20 ㎝ -3 By making the doping concentration of the second doping structure 113 within the above range, it is beneficial to reduce the manufacturing cost on the one hand, and on the other hand, the second doping structure 113 can have better conductive properties.

[0112] In one embodiment, as shown in FIG1 , a first dimension H1 is defined between a side of the first doping structure 112 proximal to the first surface 111b and a side of the first doping structure 112 distal to the first surface 111b. The first dimension H1 is between 5 nm and 5000 nm. For example, the first dimension H1 can be 5 nm, 10 nm, 100 nm, 1500 nm, 2500 nm, 3000 nm, 4000 nm, 5000 nm, or any two values ​​therebetween. By ensuring that the first dimension H1 is within the above range, manufacturing costs can be reduced while also facilitating the formation of a stable PIN structure.

[0113] In one embodiment, as shown in FIG1 , a second dimension H2 is defined between a side of the second doping structure 113 proximal to the first surface 111 b and a side of the second doping structure 113 distal to the first surface 111 b. The second dimension H2 is between 5 nm and 5000 nm. For example, the second dimension H2 can be 5 nm, 10 nm, 100 nm, 1500 nm, 2500 nm, 3000 nm, 4000 nm, 5000 nm, or any value between the aforementioned values. By ensuring that the second dimension H2 is within the aforementioned range, manufacturing costs can be reduced while also facilitating the formation of a stable PIN structure.

[0114] In one embodiment, as shown in FIG2 , the solar cell 1 further includes a third doping structure 130 having the second doping type and disposed on a side of the first doping structure 112 away from the intrinsic region 111a. The third doping structure 130 forms a pn junction with the first doping structure 112. The provision of the third doping structure 130 facilitates increasing the doping concentration at the interface between the first electrode 117 and the intrinsic semiconductor substrate 111, thereby reducing the contact resistance at the interface between the first electrode 117 and the intrinsic semiconductor substrate 111, and thereby improving the efficiency of the solar cell 1.

[0115] In one embodiment, the solar cell 1 further includes a fourth doping structure 131 having the first doping type and disposed on a side of the second doping structure 113 away from the intrinsic region 111a. The fourth doping structure 131 forms a pn junction with the second doping structure 113. The provision of the fourth doping structure 131 facilitates increasing the doping concentration at the interface between the second electrode 118 and the intrinsic semiconductor substrate 111, thereby reducing the contact resistance at the interface between the second electrode 118 and the intrinsic semiconductor substrate 111, and thereby improving the efficiency of the solar cell 1.

[0116] In one embodiment, as shown in Figures 1, 2, 3, and 4, a first doping structure 112 is embedded in an intrinsic semiconductor substrate 111 and located between the intrinsic region 111a and the first surface 111b. Specifically, a first doping region is defined in the intrinsic semiconductor substrate 111. The first doping region is doped with a dopant of a first doping type, and the first doping region serves as the first doping structure 112.

[0117] In one embodiment, the first doping region may be formed by diffusion from the first surface 111b toward the second surface 111c. The doping depth of the first doping region may be between 0.1 μm and 3 μm. The doping concentration of the first doping region may be between 3×10 18 ㎝ -3 to 5×10 20 ㎝ -3 .

[0118] In one embodiment, the doping concentration of the first doping region gradually decreases from the first surface 111 b to the second surface 111 c .

[0119] In one embodiment, as shown in Figures 1 and 2, a second doping structure 113 is embedded in the intrinsic semiconductor substrate 111 and located between the intrinsic region 111a and the second surface 111c. Specifically, a second doping region is provided in the intrinsic semiconductor substrate 111, and the second doping region is doped with a dopant of a second doping type, and the second doping region is the second doping structure 113.

[0120] In one embodiment, the second doping region can be formed by diffusion from the second surface 111c toward the first surface 111b. The doping depth of the second doping region can be between 0.1 μm and 3 μm. The doping concentration of the second doping region can be between 3×10 18 ㎝ -3 to 5×10 20 ㎝ -3 .

[0121] In one embodiment, the doping concentration of the second doping region gradually decreases from the second surface 111 c to the first surface 111 b .

[0122] In one embodiment, as shown in FIG2 , a third doping structure 130 and a fourth doping structure 131 are also embedded in the intrinsic semiconductor substrate 111. Specifically, a third doping region and a fourth doping region are provided in the intrinsic semiconductor substrate 111. The third doping region is of the second doping type, and the fourth doping region is of the first doping type. The third doping region is located on a side of the first doping region close to the first surface 111 b, and the fourth doping region is located on a side of the second doping region close to the second surface 111 c. The third doping region forms the third doping structure 130, and the fourth doping region forms the fourth doping structure 131.

[0123] This is beneficial for increasing the doping concentration on the surface of the intrinsic semiconductor substrate 111 , thereby reducing the contact resistance between the electrode and the intrinsic semiconductor substrate 111 , and further improving the efficiency of the solar cell 1 .

[0124] In one embodiment, as shown in FIG3 and FIG4, the second doping structure 113 is provided on the side of the second surface 111c away from the first surface 111b. For example, the second doping structure 113 can be a polysilicon film containing dopants. Furthermore, the thickness of the polysilicon film can be between 10nm and 300nm, and the doping concentration of the polysilicon film can be between 1×10 19 ㎝ -3 to 5×10 20 ㎝ -3 .

[0125] In one embodiment, the solar cell 1 further includes a first tunneling layer 114, which is disposed on the second surface 111c. The second doping structure 113 is disposed on a side of the first tunneling layer 114 away from the first surface 111b. In this manner, a passivation contact structure can be formed on the second surface 111c, thereby increasing the open-circuit voltage of the solar cell 1 and thereby improving the conversion efficiency of the solar cell 1.

[0126] In one embodiment, the thickness of the first tunneling layer 114 is between 0.5 nm and 5 nm.

[0127] In one embodiment, as shown in Figures 1-4, the solar cell 1 further includes a first passivation anti-reflection layer 115, a first electrode 117, a second passivation anti-reflection layer 116, and a second electrode 118. The first passivation anti-reflection layer 115 is disposed on a side of the first doped structure 112 away from the intrinsic region 111a. The first electrode 117 is disposed on a side of the first doped structure 112 away from the second doped structure 113, penetrates the first passivation anti-reflection layer 115, and is electrically connected to the first doped structure 112. The second passivation anti-reflection layer 116 is disposed on a side of the second doped structure 113 away from the intrinsic region 111a. The second electrode 118 is disposed on a side of the second doped structure 113 away from the first doped structure 112, penetrates the second passivation anti-reflection layer 116, and is electrically connected to the second doped structure 113. Specifically, the solar cell 1 shown in Figures 1 and 2 is a PERT cell, and the solar cell 1 shown in Figures 3 and 4 is a TOPCon cell.

[0128] In one embodiment, as shown in FIG. 4 , a third doping structure 130 may be embedded in the intrinsic semiconductor substrate 111 . This helps to increase the doping concentration on the surface of the intrinsic semiconductor substrate 111 , thereby reducing the contact resistance between the first electrode 117 and the intrinsic semiconductor substrate 111 , thereby improving the efficiency of the solar cell 1 .

[0129] In one embodiment, the material of the first passivation anti-reflection layer includes one or more materials selected from the group consisting of AlOx, SiNx, SiOx, SiNxOy, TiOx, and MgF2.

[0130] In one example, the first passivation anti-reflection layer is an AlOx layer, and the thickness of the AlOx layer is between 1 nm and 20 nm.

[0131] In one example, the first passivation anti-reflection layer is a SiNx layer, and the thickness of the SiNx layer is between 10 nm and 100 nm.

[0132] In one example, the first passivation anti-reflection layer is a SiOx layer, and the thickness of the SiOx layer is between 10 nm and 150 nm.

[0133] In one example, the first passivation anti-reflection layer is a SiNxOy layer, and the thickness of the SiNxOy layer is between 10 nm and 150 nm.

[0134] In one example, the first passivation anti-reflection layer is a TiOx layer, and the thickness of the TiOx layer is between 10 nm and 150 nm.

[0135] In one example, the first passivation anti-reflection layer is a MgF 2 layer, and the thickness of the MgF 2 layer is between 10 nm and 150 nm.

[0136] In one embodiment, the material of the second passivation anti-reflection layer includes one or more materials selected from the group consisting of AlOx, SiNx, SiOx, SiNxOy, TiOx, and MgF2. The material of the second passivation anti-reflection layer can be the same as that of the first passivation anti-reflection layer, and the thickness of the second passivation anti-reflection layer can be the same as that of the first passivation anti-reflection layer. This embodiment of the present application is not further described herein.

[0137] In one embodiment, the materials of the first electrode 117 and the second electrode 118 may include one or more metals such as Ag, Al, Cu, Ni, or a mixture of these metals and glass frit.

[0138] In one embodiment, as shown in Figures 5 and 6 , the first doping structure 112 is disposed on a side of the first surface 111b away from the second surface 111c. For example, the first doping structure 112 may be a microcrystalline or amorphous thin film containing a dopant. Furthermore, the thickness of the first doping structure 112 may be between 5 nm and 25 nm.

[0139] In one embodiment, the second doping structure 113 is disposed on a side of the second surface 111c away from the first surface 111b. For example, the second doping structure 113 may be a microcrystalline or amorphous thin film containing a dopant. Furthermore, the thickness of the second doping structure 113 may be between 5 nm and 25 nm.

[0140] In one embodiment, the solar cell 1 further includes a first intrinsic semiconductor layer 119 and a second intrinsic semiconductor layer 120. The first intrinsic semiconductor layer 119 is disposed on the first surface 111b, and the first doping structure 112 is disposed on a side of the first intrinsic semiconductor layer 119 away from the second surface 111c. The second intrinsic semiconductor layer 120 is disposed on the second surface 111c, and the second doping structure 113 is disposed on a side of the second intrinsic semiconductor layer 120 away from the first surface 111b. Exemplarily, the first intrinsic semiconductor layer 119 and the second intrinsic semiconductor layer 120 are both intrinsic amorphous silicon thin films.

[0141] In one embodiment, the thickness of the first intrinsic semiconductor layer 119 and the second intrinsic semiconductor layer 120 is between 2 nm and 20 nm.

[0142] In one embodiment, as shown in FIG5 , the solar cell 1 further includes a first transparent conductive layer 121, a first electrode 117, a second transparent conductive layer 122, and a second electrode 118. The first transparent conductive layer 121 is disposed on a side of the first doped structure 112 away from the first intrinsic semiconductor layer 119. The first electrode 117 is disposed on a side of the first transparent conductive layer 121 away from the first intrinsic semiconductor layer 119 and is electrically connected to the first transparent conductive layer 121. The second transparent conductive layer 122 is disposed on a side of the second doped structure 113 away from the second intrinsic semiconductor layer 120. The second electrode 118 is disposed on a side of the second transparent conductive layer 122 away from the second intrinsic semiconductor layer 120 and is electrically connected to the second transparent conductive layer 122. For example, the material of the first transparent conductive layer 121 may include one or more of indium tin oxide, tin oxide, and zinc oxide. The material of the second transparent conductive layer 122 may include one or more of indium tin oxide, tin oxide, and zinc oxide.

[0143] It should be noted that the solar cell 1 shown in FIG5 is an SHJ cell, and the solar cell 1 shown in FIG6 is a tandem cell. The figure only shows the bottom cell in the tandem cell, which is an SHJ cell. For example, the tandem cell may be a perovskite-silicon heterojunction tandem cell.

[0144] In one embodiment, as shown in FIG7 , the solar cell 1 further includes a second tunneling layer 123 and a third tunneling layer 124. The second tunneling layer 123 is disposed on the first surface 111 b, and the first doping structure 112 is disposed on a side of the second tunneling layer 123 away from the second surface 111 c. The third tunneling layer 124 is disposed on the second surface 111 c, and the second doping structure 113 is disposed on a side of the third tunneling layer 124 away from the first surface 111 b.

[0145] It should be noted that the solar cell 1 shown in FIG7 is a tandem cell, and the figure only shows the bottom cell in the tandem cell, which is a TOPCon cell. Exemplarily, the tandem cell may be a perovskite-TOPCon tandem cell.

[0146] In one example, the first doping structure 112 is a polysilicon film containing an n-type dopant. Furthermore, the doping concentration of the first doping structure 112 is between 1×10 19 ㎝ -3 to 5×10 20 ㎝ -3 The thickness of the first doping structure 112 is between 10 nm and 300 nm.

[0147] In one example, the second doping structure 113 is a polysilicon film containing a p-type dopant. Furthermore, the doping concentration of the second doping structure 113 is between 5×10 18 ㎝-3 to 5×10 20 ㎝ -3 The thickness of the second doping structure 113 is between 10 nm and 300 nm.

[0148] It should be noted that the solar cell 1 shown in Figures 5, 6, and 7 may also include a third doping structure 130 and / or a fourth doping structure 131. In one example, the third doping structure 130 and the first doping structure 112 may be disposed in the same film layer, and the fourth doping structure 131 may be disposed in the same film layer as the second doping structure 113. In another example, the first doping structure 112, the second doping structure 113, the third doping structure 130, and the fourth doping structure 131 may each be a separate film layer structure.

[0149] In a second aspect, as shown in FIG8 , an embodiment of the present application provides another solar cell 1, which is a BC (Back Contact) cell. Specifically, the solar cell 1 includes an intrinsic semiconductor substrate 111, a first passivation layer 125, a second passivation layer 126, a first doping structure 112, and a second doping structure 113. The intrinsic semiconductor substrate 111 has a first surface 111b and a second surface 111c disposed opposite each other. The intrinsic semiconductor substrate 111 is provided with first and second conductive regions 111d, 111e arranged along a first direction X, which is perpendicular to the thickness of the intrinsic semiconductor substrate 111. The first passivation layer 125 is provided on the first surface 111b and located in the first conductive region 111d. The second passivation layer 126 is provided on the first surface 111b and located in the second conductive region 111e. The first doping structure 112 has a first doping type and is provided on a side of the first passivation layer 125 away from the intrinsic semiconductor substrate 111. The second doping structure 113 has a second doping type and is disposed on a side of the second passivation layer 126 away from the intrinsic semiconductor substrate 111 .

[0150] The first doping type and the second doping type are opposite to each other, and the first doping structure 112 , the intrinsic semiconductor substrate 111 and the second doping structure 113 form a pin structure.

[0151] The solar cell 1 provided in the embodiment of the present application comprises an intrinsic region 111a, a first doping structure 112, and a second doping structure 113 disposed on an intrinsic semiconductor substrate 111, such that the first doping structure 112, the intrinsic region 111a, and the second doping structure 113 form a pin structure. Thus, compared to conventional techniques for fabricating solar cells 1 using p-type or n-type semiconductor substrates 111, the substrate of the solar cell 1 provided in the embodiment of the present application utilizes an intrinsic semiconductor substrate 111 containing the intrinsic region 111a. Therefore, during the fabrication of the blank (e.g., a silicon rod) for the intrinsic semiconductor substrate 111, no p-type or n-type dopant is required. This reduces the complexity of the solar cell 1 fabrication process and facilitates silicon crystal growth, reducing dislocation density in the silicon crystal, increasing crystal pulling speed, and reducing defect density. Furthermore, after the silicon rods are cut into slices, there is no resistivity difference in the radial and longitudinal directions of the intrinsic silicon wafers. On the one hand, this is beneficial to improving the electrical consistency of the silicon wafers, thereby improving the conversion efficiency of the solar cell 1; on the other hand, it is beneficial to improving the utilization rate of the silicon rods, thereby reducing the manufacturing cost of the solar cell 1.

[0152] It should also be noted here that the solar cell 1 provided in the embodiment of the present application is equivalent to having a pi junction and an in junction on the intrinsic semiconductor substrate 111. This structure can achieve a better carrier separation effect, thereby improving the photoelectric conversion efficiency of the solar cell 1. Specifically, compared to the substrate of the traditional solar cell 1, the intrinsic semiconductor substrate 111 in the embodiment of the present application includes an intrinsic region 111a, so the doping concentration of the intrinsic semiconductor substrate 111 is much lower than the doping concentration of the traditional substrate. Because the lower the doping concentration of the substrate, the deeper the built-in electric field of the solar cell 1 extends into the substrate, therefore, the built-in electric field of the solar cell 1 in the embodiment of the present application extends deeper into the substrate, and the influence range of the built-in electric field is larger, thereby improving the carrier separation effect.

[0153] It is understood that a plurality of first conductive regions 111 d and a plurality of second conductive regions 111 e may be provided on the intrinsic semiconductor substrate 111, and the plurality of first conductive regions 111 d and the plurality of second conductive regions 111 e are alternately arranged along the first direction X. Each first conductive region 111 d is provided with a first passivation layer 125 and a first doping structure 112, and each second conductive region 111 e is provided with a second passivation layer 126 and a second doping structure 113. Isolation trenches are provided between adjacent first doping structures 112 and second doping structures 113.

[0154] In one embodiment, the resistivity of the intrinsic semiconductor substrate 111 is greater than 100 Ω·cm. This effectively reduces the dopant content in the intrinsic region 111a. This increases the depth of the built-in electric field into the intrinsic semiconductor substrate 111, thereby enhancing carrier separation.

[0155] In one embodiment, the doping concentration of the p-type dopant in the intrinsic semiconductor substrate 111 is less than or equal to 1.3×10 14 ㎝ -3 , and the doping concentration of the n-type dopant in the intrinsic semiconductor substrate 111 is less than or equal to 4.4×10 13 ㎝ -3 This is equivalent to making the dopant content in the intrinsic region 111a extremely small, which is beneficial for increasing the depth of the built-in electric field extending into the intrinsic semiconductor substrate 111, thereby helping to improve the carrier separation effect.

[0156] In one embodiment, the thickness of the intrinsic semiconductor substrate 111 is between 50 μm and 300 μm. For example, the thickness of the intrinsic semiconductor substrate 111 can be 50 μm, 60 μm, 65 μm, 80 μm, 100 μm, 130 μm, 160 μm, 190 μm, 230 μm, 270 μm, 290 μm, 300 μm, or any two values ​​between the above. By ensuring that the thickness of the intrinsic semiconductor substrate 111 is within the above range, it is beneficial to reduce the thickness of the solar cell 1 and to form a stable PIN structure.

[0157] In one embodiment, the doping concentration of the first doping structure 112 is between 3×10 18 ㎝ -3 to 5×10 20 ㎝ -3 For example, the doping concentration of the first doping structure 112 may be 3×10 18 ㎝ -3 , 5×10 18 ㎝ -3 , 1×10 19 ㎝ -3 , 5×10 20 ㎝ -3 By making the doping concentration of the first doping structure 112 within the above range, it is beneficial to reduce the manufacturing cost on the one hand, and on the other hand, the first doping structure 112 can have better conductivity.

[0158] In one embodiment, the doping concentration of the second doping structure 113 is between 3×10 18 ㎝ -3 to 5×10 20㎝ -3 For example, the doping concentration of the second doping structure 113 may be 3×10 18 ㎝ -3 , 5×10 18 ㎝ -3 , 1×10 19 ㎝ -3 , 5×10 20 ㎝ -3 By making the doping concentration of the second doping structure 113 within the above range, it is beneficial to reduce the manufacturing cost on the one hand, and on the other hand, the second doping structure 113 can have better conductive properties.

[0159] In one embodiment, a third dimension H3 is defined between a side of the first doped structure 112 proximal to the first surface 111b and a side of the first doped structure 112 distal to the first surface 111b. The third dimension H3 is between 5 nm and 5000 nm. For example, the third dimension H3 can be 5 nm, 10 nm, 100 nm, 1500 nm, 2500 nm, 3000 nm, 4000 nm, or 5000 nm, or between any two of the aforementioned values. By ensuring that the third dimension H3 is within the aforementioned range, manufacturing costs can be reduced while also facilitating the formation of a stable PIN structure.

[0160] In one embodiment, a fourth dimension H4 is defined between a side of the second doped structure 113 proximal to the first surface 111b and a side of the second doped structure 113 distal to the first surface 111b. The fourth dimension H4 is between 5 nm and 5000 nm. For example, the fourth dimension H4 can be 5 nm, 10 nm, 100 nm, 1500 nm, 2500 nm, 3000 nm, 4000 nm, 5000 nm, or any value between the aforementioned values. By ensuring that the fourth dimension H4 is within the aforementioned range, manufacturing costs can be reduced while also facilitating the formation of a stable PIN structure.

[0161] In one embodiment, the solar cell 1 further includes a third doping structure 130, which has a second doping type and is disposed on a side of the first doping structure 112 away from the intrinsic semiconductor substrate 111; the third doping structure 130 and the first doping structure 112 form a pn junction. In one example, the third doping structure 130 and the first doping structure 112 can be disposed in the same film layer structure. This is beneficial for increasing the doping concentration at the contact interface between the first electrode 117 and the intrinsic semiconductor substrate 111, thereby reducing the contact resistance at the contact interface between the first electrode 117 and the intrinsic semiconductor substrate 111, and thereby improving the efficiency of the solar cell 1. It is understandable that the first doping structure 112 and the third doping structure 130 can also be separate film layer structures.

[0162] In one embodiment, the solar cell 1 further includes a fourth doping structure 131 having a first doping type and disposed on a side of the second doping structure 113 away from the intrinsic semiconductor substrate 111; the fourth doping structure 131 and the second doping structure 113 form a pn junction. In one example, the fourth doping structure 131 and the second doping structure 113 can be disposed in the same film layer structure. This helps to increase the doping concentration at the interface between the second electrode 118 and the intrinsic semiconductor substrate 111, thereby reducing the contact resistance at the interface between the second electrode 118 and the intrinsic semiconductor substrate 111, and thereby improving the efficiency of the solar cell 1. It is understood that the second doping structure 113 and the fourth doping structure 131 can also be separate film layer structures.

[0163] In one embodiment, the first passivation layer 125 and the second passivation layer 126 are configured as tunnel dielectric layers. For example, the first passivation layer 125 and the second passivation layer 126 may be made of SiOx. The thickness of the first passivation layer 125 and the second passivation layer 126 may be between 0.5 nm and 5 nm.

[0164] Furthermore, the material of the first doping structure 112 and the material of the second doping structure 113 include polysilicon. The thickness of the first doping structure 112 and the second doping structure 113 may be between 10 nm and 300 nm.

[0165] In one embodiment, the material of the first passivation layer 125 and the material of the second passivation layer 126 include intrinsic semiconductor materials. For example, the material of the first passivation layer 125 and the material of the second passivation layer 126 may be intrinsic microcrystalline silicon or intrinsic amorphous silicon. The thickness of the first passivation layer 125 and the second passivation layer 126 may be between 2 nm and 20 nm. Furthermore, the material of the first doped structure 112 and the material of the second doped structure 113 include microcrystalline silicon or amorphous silicon. The thickness of the first doped structure 112 and the second doped structure 113 may be between 5 nm and 25 nm.

[0166] In one embodiment, the solar cell 1 further includes a first anti-reflection layer 127, a first electrode 117, a second electrode 118, a third passivation layer 129, and a second anti-reflection layer 128. The first anti-reflection layer 127 is disposed on a side of the first doped structure 112 away from the intrinsic semiconductor substrate 111, and on a side of the second doped structure 113 away from the intrinsic semiconductor substrate 111. The first electrode 117 is disposed on a side of the first doped structure 112 away from the intrinsic semiconductor substrate 111, penetrates the first anti-reflection layer 127, and is electrically connected to the first doped structure 112. The second electrode 118 is disposed on a side of the second doped structure 113 away from the intrinsic semiconductor substrate 111, penetrates the first anti-reflection layer 127, and is electrically connected to the second doped structure 113. The third passivation layer 129 is disposed on the second surface 111c. The second anti-reflection layer 128 is disposed on a side of the third passivation layer 129 away from the intrinsic semiconductor substrate 111.

[0167] In one embodiment, the material of the third passivation layer 129 may include SiNx, AlOx, amorphous silicon, etc. When the material of the third passivation layer 129 is SiNx, the thickness of the third passivation layer 129 may be between 50 nm and 120 nm. When the material of the third passivation layer 129 is AlOx, the thickness of the third passivation layer 129 may be between 1 nm and 20 nm. When the material of the third passivation layer 129 is amorphous silicon, the thickness of the first passivation layer 125 and the second passivation layer 126 may be between 2 nm and 20 nm.

[0168] In one embodiment, the material of the first anti-reflection layer 127 and the second anti-reflection layer 128 may include one or more of SiNx, SiOx, SiNxOyAlOx, ITO, SnO2, MgF2, TiOx and ZnO.

[0169] It should be noted that the inventors have conducted experiments on the electrical performance of traditional BC batteries using silicon substrates and silicon wafers and the BC batteries in the embodiments of this application. The data are shown in the following table:

[0170] Electrical performance comparison table

[0171] As can be seen from the above table, compared with traditional BC batteries, the embodiments of the present application improve the fill factor and open circuit voltage, reduce the short-circuit current, and in particular, improve the efficiency by 0.04%. It can be seen that the embodiments of the present application have obvious efficiency gains.

[0172] It should be noted that the above experimental results are limited by the current experimental level. The inventors believe that there is still room for further improvement in solar cells using intrinsic semiconductor substrates.

[0173] In a third aspect, as shown in FIG9 , an embodiment of the present application provides a method for preparing a solar cell. The method is used to prepare the solar cell of the first aspect. Specifically, the method comprises the following steps:

[0174] S100: providing an intrinsic semiconductor substrate, wherein the intrinsic semiconductor substrate comprises an intrinsic region, a first surface and a second surface, wherein the first surface and the second surface are located at opposite sides of the intrinsic semiconductor substrate, and the intrinsic region is located between the first surface and the second surface.

[0175] S200: Forming a first doping structure and a second doping structure on an intrinsic semiconductor substrate. The first doping structure has a first doping type and is disposed on a side of the intrinsic region close to the first surface; the second doping structure has a second doping type and is disposed on a side of the intrinsic region close to the second surface. The first doping type and the second doping type are opposite, and the first doping structure, the intrinsic region, and the second doping structure constitute a pin structure.

[0176] In one embodiment, taking the solar cell shown in FIG. 1 as an example, S200 specifically includes the following steps:

[0177] S210: Place the intrinsic semiconductor substrate in a high-temperature diffusion furnace, diffuse a p-type dopant (such as boron) into the intrinsic semiconductor substrate, and then remove the oxide layer (borosilicate glass) and the diffusion layer on the second surface of the intrinsic semiconductor substrate to form a first doping structure. For example, the diffusion depth can be 0.8 μm and the doping concentration can be 5×10 18 ㎝ -3 It is understandable that before S210 , pyramid velvet surfaces need to be fabricated on the first surface and the second surface of the intrinsic semiconductor substrate.

[0178] S220: Cleaning the intrinsic semiconductor substrate.

[0179] S230: Place the intrinsic semiconductor substrate in a high-temperature diffusion furnace, diffuse n-type dopants (such as phosphorus) into the intrinsic semiconductor substrate, then remove the oxide layers (such as borosilicate glass, phosphosilicate glass) on the first and second surfaces to form a second doping structure, and clean the intrinsic semiconductor substrate. For example, the diffusion depth can be 0.8 μm and the doping concentration can be 1×10 20 ㎝ -3 .

[0180] S240: forming a first passivation anti-reflection layer on the first doping structure, and forming a second passivation anti-reflection layer on the second doping structure.

[0181] S250: Forming a first electrode and a second electrode, wherein the first electrode penetrates the first passivation anti-reflection layer and is electrically connected to the first doped structure, and the second electrode penetrates the second passivation anti-reflection layer and is electrically connected to the second doped structure. For example, a silver-aluminum paste can be screen-printed on the first passivation anti-reflection layer and a silver paste can be printed on the second passivation anti-reflection layer, and then sintered to form the first and second electrodes.

[0182] It should be noted that if the solar cell shown in FIG2 is to be manufactured, a third doping structure needs to be diffused on the side of the intrinsic region close to the first surface in S210, and a fourth doping structure needs to be diffused on the side of the intrinsic region close to the second surface in S230.

[0183] In one embodiment, taking the solar cell shown in FIG3 as an example, S200 specifically includes the following steps:

[0184] S210: Place the intrinsic semiconductor substrate in a high-temperature diffusion furnace, diffuse a p-type dopant (such as boron) into the intrinsic semiconductor substrate, and then remove the oxide layer (borosilicate glass) and the diffusion layer on the second surface of the intrinsic semiconductor substrate to form a first doping structure. For example, the diffusion depth can be 0.8 μm and the doping concentration can be 5×10 18 ㎝ -3 It is understandable that before S210 , pyramid velvet surfaces need to be fabricated on the first surface and the second surface of the intrinsic semiconductor substrate.

[0185] S220: Cleaning the intrinsic semiconductor substrate.

[0186] S230: forming a first tunneling layer on the second surface of the intrinsic semiconductor substrate.

[0187] S240: forming a second doping structure on the first tunneling layer. Exemplarily, a polysilicon film doped with an n-type dopant is first deposited on the first tunneling layer, and then the polysilicon film is annealed to activate the dopant, thereby forming the second doping structure.

[0188] S250: forming a first passivation anti-reflection layer on the first doping structure, and forming a second passivation anti-reflection layer on the second doping structure.

[0189] S260: Forming a first electrode and a second electrode, wherein the first electrode penetrates the first passivation anti-reflection layer and is electrically connected to the first doped structure, and the second electrode penetrates the second passivation anti-reflection layer and is electrically connected to the second doped structure. For example, a silver-aluminum paste can be printed on the first passivation anti-reflection layer and a silver paste can be printed on the second passivation anti-reflection layer using a screen printing process, and then sintered to obtain the first and second electrodes.

[0190] In one embodiment, taking the solar cell shown in FIG. 5 as an example, S200 specifically includes the following steps:

[0191] S210 : forming a first intrinsic semiconductor layer on a first surface of an intrinsic semiconductor substrate.

[0192] S220 : forming a second intrinsic semiconductor layer on the second surface of the intrinsic semiconductor substrate.

[0193] S230: forming a first doping structure on the first intrinsic semiconductor layer.

[0194] S240: forming a second doping structure on the second intrinsic semiconductor layer.

[0195] S250: forming a first transparent conductive layer on the first doping structure.

[0196] S260: forming a second transparent conductive layer on the second doping structure.

[0197] S270: forming a first electrode on the first transparent conductive layer and forming a second electrode on the second transparent conductive layer. For example, electrode paste may be printed using a screen printing process and then cured to obtain the first electrode and the second electrode.

[0198] It should be noted that if the solar cell shown in Figure 8 needs to be manufactured, then before manufacturing the first doping structure and the second doping structure, it is necessary to form a second tunneling layer on the first surface, form a third tunneling layer on the second surface, and then form the first doping structure on the second tunneling layer, and form the second doping structure on the third tunneling layer.

[0199] In a fourth aspect, as shown in FIG10 , an embodiment of the present application provides another method for preparing a solar cell, which is used to prepare the solar cell in the second aspect. The method specifically comprises the following steps:

[0200] S10: Providing an intrinsic semiconductor substrate, wherein the intrinsic semiconductor substrate has a first surface and a second surface opposite to each other, and a first conductive region and a second conductive region arranged along a first direction perpendicular to a thickness direction of the intrinsic semiconductor substrate.

[0201] S20: forming a first passivation layer on the first surface, and forming a first doping structure on a side of the first passivation layer away from the intrinsic semiconductor substrate. The first passivation layer is located in the first conductive region, and the first doping structure has a first doping type.

[0202] S30: Forming a second passivation layer on the first surface, and forming a second doping structure on a side of the second passivation layer away from the intrinsic semiconductor substrate. The second passivation layer is located in the second conductive region, and the second doping structure has a second doping type, where the first doping type and the second doping type are opposite, and the first doping structure, the intrinsic semiconductor substrate, and the second doping structure form a pin structure.

[0203] In one embodiment, the preparation method further comprises the following steps:

[0204] S40: forming a first anti-reflection layer on the first surface, the first anti-reflection layer covering the first doping structure and the second doping structure, and forming a third passivation layer and a second anti-reflection layer on the second surface, the third passivation layer being located between the intrinsic semiconductor substrate and the second anti-reflection layer.

[0205] S50: forming a first electrode and a second electrode, wherein the first electrode is electrically connected to the first doping structure, and the second electrode is electrically connected to the second doping structure.

[0206] In a fifth aspect, an embodiment of the present application provides a photovoltaic assembly comprising a solar cell according to any one of the first and second aspects.

[0207] For example, the photovoltaic module includes multiple solar cells, which can be connected in series by welding ribbons, so that the electricity generated by the individual solar cells can be collected for subsequent transmission. Of course, the solar cells can be arranged at intervals or stacked in a shingled form.

[0208] Furthermore, the photovoltaic module also includes an encapsulation layer and a cover plate (not shown), the encapsulation layer is used to cover the surface of the battery string, and the cover plate is used to cover the surface of the encapsulation layer away from the battery string. The solar cells are electrically connected in the form of a whole piece or multiple pieces to form a plurality of battery strings, and the plurality of battery strings are electrically connected in series and / or in parallel. Specifically, in some embodiments, the plurality of battery strings can be electrically connected by a conductive tape. The encapsulation layer covers the surface of the solar cell. For example, the encapsulation layer can be an organic encapsulation film such as an ethylene-vinyl acetate copolymer film, a polyethylene octene co-elastomer film or a polyethylene terephthalate film. The cover plate can be a cover plate with a light-transmitting function such as a glass cover plate or a plastic cover plate.

[0209] The photovoltaic module provided in the embodiment of the present application is provided by providing an intrinsic region on an intrinsic semiconductor substrate, and providing a first doping structure and a second doping structure on opposite sides of the intrinsic region, so that the first doping structure, the intrinsic region and the second doping structure constitute a pin structure. Thus, compared with the conventional technology of making solar cells using a p-type or n-type semiconductor substrate, the substrate of the solar cell provided in the embodiment of the present application, because it uses an intrinsic semiconductor substrate containing an intrinsic region, does not require the addition of p-type or n-type dopants during the process of making the blank (such as a silicon rod) of the intrinsic semiconductor substrate. On the one hand, it is conducive to reducing the complexity of the solar cell preparation process, and on the other hand, it is more conducive to the growth of silicon crystals, can reduce the dislocation density in the silicon crystal, increase the crystal pulling speed, and reduce the defect density. Furthermore, after the silicon rod is cut into slices, there is no resistivity difference in the radial and longitudinal directions of the intrinsic silicon wafer, which is conducive to improving the electrical consistency of the silicon wafer, thereby improving the conversion efficiency of the solar cell; on the other hand, it is conducive to improving the utilization rate of the silicon rod, thereby reducing the manufacturing cost of the solar cell.

[0210] In a sixth aspect, an embodiment of the present application provides a photovoltaic system, comprising the photovoltaic component in the fifth aspect.

[0211] Specifically, photovoltaic systems can be used in photovoltaic power stations, such as ground power stations, rooftop power stations, water surface power stations, etc., and can also be used in equipment or devices that use solar energy to generate electricity, such as user solar power supplies, solar street lights, solar cars, solar buildings, etc. Of course, it is understandable that the application scenarios of photovoltaic systems are not limited to this, that is to say, photovoltaic systems can be used in all fields that require solar energy to generate electricity. Taking the photovoltaic power generation system network as an example, the photovoltaic system may include a photovoltaic array, a junction box and an inverter. The photovoltaic array can be an array combination of multiple photovoltaic components. For example, multiple photovoltaic components can form multiple photovoltaic arrays. The photovoltaic array is connected to the junction box. The junction box can converge the current generated by the photovoltaic array. The converged current flows through the inverter to be converted into the alternating current required by the mains power grid and then connected to the mains power network to achieve solar power supply.

[0212] The photovoltaic system provided in the embodiment of the present application is provided by providing an intrinsic region on an intrinsic semiconductor substrate, and providing a first doping structure and a second doping structure on opposite sides of the intrinsic region, so that the first doping structure, the intrinsic region and the second doping structure constitute a pin structure. Thus, compared with the conventional technology of making solar cells using a p-type or n-type semiconductor substrate, the substrate of the solar cell provided in the embodiment of the present application, because it uses an intrinsic semiconductor substrate containing an intrinsic region, does not require the addition of p-type or n-type dopants during the process of making the blank (such as a silicon rod) of the intrinsic semiconductor substrate. On the one hand, it is conducive to reducing the complexity of the solar cell preparation process, and on the other hand, it is more conducive to the growth of silicon crystals, can reduce the dislocation density in the silicon crystal, increase the crystal pulling speed, and reduce the defect density. Furthermore, after the silicon rod is cut into slices, there is no resistivity difference in the radial and longitudinal directions of the intrinsic silicon wafer, which is conducive to improving the electrical consistency of the silicon wafer, thereby improving the conversion efficiency of the solar cell; on the other hand, it is conducive to improving the utilization rate of the silicon rod, thereby reducing the manufacturing cost of the solar cell.

[0213] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0214] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present application, and these modifications and improvements fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.

Claims

1. A solar cell, wherein, Comprising: An intrinsic semiconductor substrate, including an intrinsic region, a first surface, and a second surface, the first surface and the second surface being disposed on opposite sides of the intrinsic semiconductor substrate, and the intrinsic region being disposed between the first surface and the second surface; A first doping structure, having a first doping type, the first doping structure being disposed on a side of the intrinsic region close to the first surface; And A second doping structure, having a second doping type, the second doping structure being disposed on a side of the intrinsic region close to the second surface; Wherein, the first doping type and the second doping type are opposite, and the first doping structure, the intrinsic region, and the second doping structure form a p-i-n structure.

2. The solar cell according to claim 1, wherein, The resistivity of the intrinsic region is greater than 100 Ω·cm.

3. The solar cell according to claim 1, wherein, The doping concentration of the p-type dopant in the intrinsic region is less than or equal to 1.3×10 14 cm -3 , and the doping concentration of the n-type dopant in the intrinsic region is less than or equal to 4.4×10 13 cm -3 .

4. The solar cell according to claim 1, wherein, The thickness of the intrinsic semiconductor substrate is between 50 μm and 300 μm.

5. The solar cell according to claim 1, wherein, The doping concentration of the first doping structure is between 3×10 18 cm -3 -5×10 20 cm -3 .

6. The solar cell according to claim 1, wherein, The doping concentration of the second doping structure is between 3×10 18 cm -3 -5×10 20 cm -3 .

7. The solar cell according to claim 1, wherein, There is a first dimension between a side of the first doping structure close to the first surface and a side of the first doping structure far from the first surface, and the first dimension is between 5 nm and 5000 nm.

8. The solar cell according to claim 1, wherein, There is a second dimension between a side of the second doping structure close to the first surface and a side of the second doping structure far from the first surface, and the second dimension is between 5 nm and 5000 nm.

9. The solar cell according to claim 1, wherein, The solar cell further includes a third doping structure, the third doping structure having the second doping type and being disposed on a side of the first doping structure far from the intrinsic region; The third doping structure and the first doping structure form a p-n junction.

10. The solar cell according to claim 9, wherein, The solar cell further includes a fourth doping structure, the fourth doping structure having the first doping type and being disposed on a side of the second doping structure far from the intrinsic region; The fourth doping structure and the second doping structure form a p-n junction.

11. The solar cell according to any one of claims 1-10, wherein, The first doping structure is embedded in the intrinsic semiconductor substrate and is located between the intrinsic region and the first surface.

12. The solar cell according to claim 11, wherein, The second doping structure is embedded in the intrinsic semiconductor substrate and is located between the intrinsic region and the second surface.

13. The solar cell according to claim 11, wherein, The second doping structure is disposed on a side of the second surface far from the first surface.

14. The solar cell according to claim 13, wherein, The solar cell further includes a first tunneling layer, the first tunneling layer being disposed on the second surface, and the second doping structure being disposed on a side of the first tunneling layer far from the first surface.

15. The solar cell according to any one of claims 1-14, wherein, The solar cell further includes: A first passivation and antireflection layer, disposed on a side of the first doping structure far from the intrinsic region; A first electrode, disposed on a side of the first doping structure far from the second doping structure, passing through the first passivation and antireflection layer and being electrically connected to the first doping structure; A second passivation and antireflection layer, disposed on a side of the second doping structure far from the intrinsic region; and A second electrode, disposed on a side of the second doping structure far from the first doping structure, passing through the second passivation and antireflection layer and being electrically connected to the second doping structure.

16. The solar cell according to any one of claims 1 to 10, wherein, The first doping structure is disposed on a side of the first surface far from the second surface.

17. The solar cell according to claim 16, wherein, The second doping structure is disposed on a side of the second surface far from the first surface.

18. The solar cell according to claim 17, wherein, The solar cell further includes: a first intrinsic semiconductor layer disposed on the first surface, and the first doping structure is disposed on a side of the first intrinsic semiconductor layer away from the second surface; and a second intrinsic semiconductor layer disposed on the second surface, and the second doping structure is disposed on a side of the second intrinsic semiconductor layer away from the first surface.

19. The solar cell according to claim 18, wherein, The solar cell further includes: a first transparent conductive layer disposed on a side of the first doping structure away from the first intrinsic semiconductor layer; a first electrode disposed on a side of the first transparent conductive layer away from the first intrinsic semiconductor layer and electrically connected to the first transparent conductive layer; a second transparent conductive layer disposed on a side of the second doping structure away from the second intrinsic semiconductor layer; and a second electrode disposed on a side of the second transparent conductive layer away from the second intrinsic semiconductor layer and electrically connected to the second transparent conductive layer.

20. The solar cell according to claim 17, wherein, The solar cell further includes: a second tunneling layer disposed on the first surface, and the first doping structure is disposed on a side of the second tunneling layer away from the second surface; and a third tunneling layer disposed on the second surface, and the second doping structure is disposed on a side of the third tunneling layer away from the first surface.

21. A solar cell, wherein, It includes: an intrinsic semiconductor substrate having a first surface and a second surface disposed opposite to each other; a first conductive region and a second conductive region arranged along a first direction are provided on the intrinsic semiconductor substrate, and the first direction is perpendicular to the thickness direction of the intrinsic semiconductor substrate; a first passivation layer disposed on the first surface and located in the first conductive region; a second passivation layer disposed on the first surface and located in the second conductive region; a first doping structure having a first doping type and disposed on a side of the first passivation layer away from the intrinsic semiconductor substrate; and a second doping structure having a second doping type and disposed on a side of the second passivation layer away from the intrinsic semiconductor substrate; wherein the first doping type and the second doping type are opposite, and the first doping structure, the intrinsic semiconductor substrate, and the second doping structure form a p-i-n structure.

22. The solar cell according to claim 21, wherein, The resistivity of the intrinsic semiconductor substrate is greater than 100 Ω·cm.

23. The solar cell according to claim 21, wherein, The doping concentration of the p-type dopant in the intrinsic semiconductor substrate is less than or equal to 1.3×10 14 cm -3 , and the doping concentration of the n-type dopant in the intrinsic semiconductor substrate is less than or equal to 4.4×10 13 cm -3 .

24. The solar cell according to claim 21, wherein, The thickness of the intrinsic semiconductor substrate is between 50 μm and 300 μm.

25. The solar cell according to claim 21, wherein, The doping concentration of the first doping structure is between 3×10 18 cm -3 -5×10 20 cm -3 .

26. The solar cell according to claim 21, wherein, The doping concentration of the second doping structure is between 3×10 18 cm -3 -5×10 20 cm -3 .

27. The solar cell according to claim 21, wherein, A third dimension exists between a side of the first doping structure close to the first surface and a side of the first doping structure away from the first surface, and the third dimension is between 5 nm and 5000 nm.

28. The solar cell according to claim 21, wherein, A fourth dimension exists between a side of the second doping structure close to the first surface and a side of the second doping structure away from the first surface, and the fourth dimension is between 5 nm and 5000 nm.

29. The solar cell according to claim 21, wherein, The solar cell further includes a third doping structure having a second doping type and disposed on a side of the first doping structure away from the intrinsic semiconductor substrate; The third doping structure and the first doping structure form a p-n junction.

30. The solar cell according to claim 21, wherein, The solar cell further includes a fourth doping structure having a first doping type and disposed on a side of the second doping structure away from the intrinsic semiconductor substrate; The fourth doping structure and the second doping structure form a p-n junction.

31. The solar cell according to claim 21, wherein, The first passivation layer and the second passivation layer are configured as tunneling dielectric layers.

32. The solar cell according to claim 21, wherein, The material of the first doping structure and the material of the second doping structure include polysilicon.

33. The solar cell according to claim 21, wherein, The material of the first passivation layer and the material of the second passivation layer include intrinsic semiconductor materials.

34. The solar cell according to claim 21, wherein, The material of the first doping structure and the material of the second doping structure include microcrystalline silicon or amorphous silicon.

35. The solar cell according to claim 21, wherein, The solar cell further includes: a first antireflection layer disposed on a side of the first doping structure away from the intrinsic semiconductor substrate and on a side of the second doping structure away from the intrinsic semiconductor substrate; a first electrode disposed on a side of the first doping structure away from the intrinsic semiconductor substrate, passing through the first antireflection layer and electrically connected to the first doping structure; a second electrode disposed on a side of the second doping structure away from the intrinsic semiconductor substrate, passing through the first antireflection layer and electrically connected to the second doping structure; a third passivation layer disposed on the second surface; and a second antireflection layer disposed on a side of the third passivation layer away from the intrinsic semiconductor substrate.

36. A method for preparing a solar cell, wherein, including: providing an intrinsic semiconductor substrate including an intrinsic region, a first surface and a second surface, the first surface and the second surface being disposed on opposite sides of the intrinsic semiconductor substrate, and the intrinsic region being disposed between the first surface and the second surface; forming a first doping structure and a second doping structure on the intrinsic semiconductor substrate; the first doping structure having a first doping type and being disposed on a side of the intrinsic region close to the first surface; the second doping structure having a second doping type and being disposed on a side of the intrinsic region close to the second surface; the first doping type and the second doping type being opposite, and the first doping structure, the intrinsic region and the second doping structure form a p-i-n structure.

37. A method for preparing a solar cell, wherein, including: providing an intrinsic semiconductor substrate having a first surface and a second surface disposed opposite to each other; a first conductive region and a second conductive region arranged along a first direction are provided on the intrinsic semiconductor substrate, and the first direction is perpendicular to the thickness direction of the intrinsic semiconductor substrate; forming a first passivation layer on the first surface, and forming a first doping structure on a side of the first passivation layer away from the intrinsic semiconductor substrate; the first passivation layer is located in the first conductive region, and the first doping structure has a first doping type; forming a second passivation layer on the first surface, and forming a second doping structure on a side of the second passivation layer away from the intrinsic semiconductor substrate; the second passivation layer is located in the second conductive region, and the second doping structure has a second doping type, the first doping type and the second doping type are opposite, and the first doping structure, the intrinsic semiconductor substrate and the second doping structure form a p-i-n structure. ​ 38. A photovoltaic module, wherein, Comprising a solar cell as described in any one of claims 1 - 35.

39. A photovoltaic system, wherein, Comprising a photovoltaic module as described in claim 38.

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