Receiver, data receiving structure and memory

Abstract

The present disclosure relates to the field of semiconductor circuit design, and in particular to a receiver, a data receiving structure and a memory. The receiver comprises: a first-stage sampling circuit, which is configured to receive an input signal and a reference signal, and, during a sampling stage, generate and output a sampling signal and a complementary sampling signal on the basis of the input signal and the reference signal; a second-stage sampling circuit, which is configured to receive the sampling signal and the complementary sampling signal, and, during the sampling stage, perform amplification on the basis of the voltage difference between the sampling signal and the complementary sampling signal, and output a data signal and a complementary data signal; and a regulation circuit, which is separately connected to the first-stage sampling circuit and the second-stage sampling circuit, and is configured to receive the sampling signal and the complementary sampling signal, and, during the sampling stage, regulate the amplification speed of the second-stage sampling circuit on the basis of the sampling signal and the complementary sampling signal.

Description

Receiver, data receiving structure and memory

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to the Chinese patent application filed with the China Patent Office on January 18, 2024, with application number 202410077246.2 and application name “Receiver, data receiving structure and memory”, the entire contents of which are incorporated by reference into this application. Technical Field

[0003] The present disclosure relates to the field of semiconductor circuit design, and in particular to a receiver, a data receiving structure, and a memory. Background Art

[0004] In the design of dynamic random access memory (DRAM), the data receiving circuit (data buffer) is the channel for data input and data output, and is an important interface for receiving external data and reading internal data.

[0005] Currently, the performance of data receiving circuits in DRAM structures needs to be improved. Summary of the Invention

[0006] Embodiments of the present disclosure provide a receiver, a data receiving structure, and a memory, which are at least used to improve the electrical performance of the receiver.

[0007] An embodiment of the present disclosure provides a receiver, comprising: a first-stage sampling circuit configured to receive an input signal and a reference signal, and generate and output a sampling signal and a complementary sampling signal based on the input signal and the reference signal during a sampling phase; wherein if the potential of the input signal is greater than the potential of the reference signal, the potential of the generated complementary sampling signal is greater than the potential of the sampling signal; and if the potential of the reference signal is greater than the potential of the input signal, the potential of the generated sampling signal is greater than the potential of the complementary sampling signal; a second-stage sampling circuit configured to receive the sampling signal and the complementary sampling signal, and, during the sampling phase, amplify the sampling signal and the complementary sampling signal based on a voltage difference between the sampling signal and the complementary sampling signal, and output a data signal and a complementary data signal; wherein if the potential of the sampling signal is greater than the potential of the complementary sampling signal, the generated complementary data signal is high and the data signal is low; and if the potential of the complementary sampling signal is greater than the potential of the sampling signal, the generated data signal is high and the complementary data signal is low; and an adjustment circuit connected to the first-stage sampling circuit and the second-stage sampling circuit, respectively, configured to receive the sampling signal and the complementary sampling signal, and, during the sampling phase, adjust an amplification speed of the second-stage sampling circuit based on the sampling signal and the complementary sampling signal.

[0008] In some embodiments, the first-stage sampling circuit is further configured to discharge its output end based on the clock signal or the complementary clock signal during the pre-charging stage to generate and output a sampling signal and a complementary sampling signal at a low level; the second-stage sampling circuit is further configured to pre-charge its output end based on the clock signal or the complementary clock signal during the pre-charging stage to generate and output a data signal and a complementary data signal at a high level; the adjustment circuit is further configured to adjust the pre-charging speed of the second-stage sampling circuit based on the sampling signal and the complementary sampling signal during the pre-charging stage.

[0009] In some embodiments, when the clock signal is high or the complementary clock signal is low, the receiver is in a sampling phase; when the clock signal is low or the complementary clock signal is high, the receiver is in a pre-charging phase.

[0010] In some embodiments, the adjustment circuit includes: a first pull-up transistor, a first end of which is used to receive a first power supply voltage, a second end of which is connected to a first output end of a second-stage sampling circuit, and a control end of which is used to receive a sampling signal; a second pull-up transistor, a first end of which is used to receive a first power supply voltage, a second end of which is connected to a second output end of the second-stage sampling circuit, and a control end of which is used to receive a complementary sampling signal; wherein the first output end is used to output a data signal, and the second output end is used to output a complementary data signal.

[0011] In some embodiments, the adjustment circuit further includes: a first balancing transistor, a first end of which is connected to the first output end, a second end of which is connected to the second output end, and a control end of which is used to receive a clock signal.

[0012] In some embodiments, the adjustment circuit is driven based on a first power supply voltage, and the first sampling circuit and the second sampling circuit are driven based on a second power supply voltage, wherein the voltage value of the first power supply voltage is greater than the voltage value of the second power supply voltage.

[0013] In some embodiments, the adjustment circuit includes: a plurality of first pull-up control circuits configured to adjust the pull-up speed of the first output terminal of the second-stage sampling circuit based on the first control signal and the sampling signal; wherein each first pull-up control circuit includes a first control transistor and a first pull-up transistor connected in series, and the first control signal includes a plurality of first control sub-signals corresponding to the first control transistors one by one; wherein the first end of the first control transistor is used to receive the first power supply voltage, the second end of the first control transistor is connected to the first end of the first pull-up transistor, the second end of the first pull-up transistor is connected to the first output terminal of the second-stage sampling circuit, the control end of the first control transistor is used to receive the first control sub-signal corresponding thereto, and the control end of the first pull-up transistor is used to receive the sampling signal; a plurality of second pull-up control circuits, It is configured to adjust the pull-up speed of the second output end of the second-stage sampling circuit based on the second control signal and the complementary sampling signal; wherein each second pull-up control circuit includes a second control transistor and a second pull-up transistor connected in series, and the second control signal includes a plurality of second control sub-signals corresponding one-to-one to the second control transistors; wherein the first end of the second control transistor is used to receive the first power supply voltage, the second end of the second control transistor is connected to the first end of the second pull-up transistor, the second end of the second pull-up transistor is connected to the second output end of the second-stage sampling circuit, the control end of the second control transistor is used to receive the second control sub-signal corresponding thereto, and the control end of the second pull-up transistor is used to receive the complementary sampling signal; wherein the first output end is used to output the data signal, and the second output end is used to output the complementary data signal.

[0014] In some embodiments, the receiver also includes: an adjustment control circuit, which is respectively connected to multiple first pull-up control circuits and multiple second pull-up control circuits, and is configured to adjust the first control signal and the second control signal, and obtain and latch the current first control signal and the second control signal based on the optimal eye diagram of the data signal and the complementary data signal.

[0015] In some embodiments, the first-stage sampling circuit includes: a first driving transistor, whose control end is used to receive a complementary clock signal, and whose first end is used to receive a second power supply voltage; a first P-type transistor, whose control end is used to receive an input signal, whose first end is connected to the second end of the first driving transistor, and whose second end is used to output a sampling signal; a second P-type transistor, whose control end is used to receive a reference signal, whose first end is connected to the second end of the first driving transistor, and whose second end is used to output a complementary sampling signal; a first N-type transistor, whose control end is used to receive a complementary clock signal, whose first end is connected to the second end of the first P-type transistor, and whose second end is grounded; and a second N-type transistor, whose control end is connected to the control end of the first N-type transistor, whose first end is connected to the second end of the second P-type transistor, and whose second end is grounded.

[0016] In some embodiments, the second-stage sampling circuit includes: a second driver transistor, having a control terminal for receiving a clock signal and a first terminal for receiving a second power supply voltage; a third driver transistor, having a control terminal for receiving a clock signal and a first terminal for receiving the second power supply voltage; a third P-type transistor, having a control terminal connected to the second terminal of the second driver transistor and for outputting a complementary data signal, a first terminal for receiving the second power supply voltage, and a second terminal connected to the second terminal of the second driver transistor; a fourth P-type transistor, having a control terminal connected to the second terminal of the third driver transistor and for outputting a data signal, a first terminal for receiving the second power supply voltage, and a second terminal connected to the second terminal of the third driver transistor; a third N-type transistor, having a control terminal connected to the second terminal of the second driver transistor and a first terminal connected to the second terminal of the second driver transistor; a fourth N-type transistor, having a control terminal connected to the second terminal of the third driver transistor and a first terminal connected to the second terminal of the third driver transistor; a fifth N-type transistor, having a control terminal for receiving a sampling signal, a first terminal connected to the second terminal of the third N-type transistor, and a second terminal grounded; and a sixth N-type transistor, having a control terminal for receiving a complementary sampling signal, a first terminal connected to the second terminal of the fourth N-type transistor, and a second terminal grounded.

[0017] In some embodiments, the second stage sampling circuit further includes: a second balancing transistor having a first end connected to the first end of the third N-type transistor, a second end connected to the first end of the fourth N-type transistor, and a control end for receiving a complementary clock signal.

[0018] In some embodiments, the receiver further includes: a decision feedback equalization circuit configured to feedback-adjust the potential of the sampling signal and the potential of the complementary sampling signal based on the previously output data signal and the complementary data signal.

[0019] Another embodiment of the present disclosure further provides a data receiving structure, comprising: N data receiving units, the N data receiving units being driven sequentially based on N phase clocks, and each of the N data receiving units being configured based on the receiver provided in the above embodiment, where N is a positive integer.

[0020] Yet another embodiment of the present disclosure provides a memory that receives input data based on the receiver provided by the above embodiment, or receives input data based on the data receiving structure provided by the above embodiment. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] One or more embodiments are exemplarily illustrated by the pictures in the corresponding drawings. These exemplified descriptions do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the drawings do not constitute a scale limitation. In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0022] FIG1 is a schematic structural diagram of a data receiving structure provided by an embodiment of the present disclosure;

[0023] FIG2 is a schematic diagram of the output principle of a receiver in the pre-charging stage and the sampling stage according to an embodiment of the present disclosure;

[0024] FIG3 is a schematic structural diagram of a receiver provided by an embodiment of the present disclosure;

[0025] FIG4 is a schematic structural diagram of a specific receiver provided by an embodiment of the present disclosure;

[0026] FIG5 is a schematic structural diagram of an adjustment circuit based on a single transistor arrangement based on the example of FIG3 , provided by an embodiment of the present disclosure;

[0027] FIG6 is a schematic structural diagram of an adjustment circuit based on a multi-transistor arrangement based on the example of FIG3 , provided in one embodiment of the present disclosure;

[0028] FIG7 is a schematic structural diagram of a regulation control circuit in a receiver according to an embodiment of the present disclosure;

[0029] FIG8 is a schematic structural diagram of a data receiving structure provided by another embodiment of the present disclosure;

[0030] FIG9 is a schematic diagram of the receiving principle of a data receiving structure provided by another embodiment of the present disclosure. DETAILED DESCRIPTION

[0031] For DRAM, a digital eye diagram is used to analyze memory performance. This diagram can be derived by combining the eye diagram of the receiver input waveform with the critical comparison time. The better the receiver, the larger the digital eye diagram area.

[0032] An embodiment of the present disclosure provides a receiver, which is at least used to improve the electrical performance of the receiver.

[0033] Those skilled in the art will appreciate that many technical details are provided in the various embodiments of the present disclosure to facilitate a better understanding of the present disclosure. However, even without these technical details and the various variations and modifications based on the following embodiments, the technical solutions claimed in the present disclosure can be implemented. The division of the following embodiments is for ease of description and should not constitute any limitation on the specific implementation of the present disclosure. The various embodiments may be combined and referenced with each other as long as there is no contradiction.

[0034] The receiver provided in this embodiment is described in detail below with reference to the accompanying drawings, specifically as follows:

[0035] Referring to Figure 1, a data receiving structure is shown as an example. The data receiving structure includes two working phases: a sampling phase and a pre-charging phase. Specifically, the data receiving structure is controlled by a clock signal wck to operate in the sampling phase or the pre-charging phase.

[0036] In the example of Figure 1, when the clock signal wck is at a low level, the data receiving structure operates in the pre-charging stage, and the inverted signal wckN of the clock signal is at a high level; when the clock signal wck is at a high level, the data receiving structure operates in the sampling stage, and the inverted signal wckN of the clock signal is at a low level.

[0037] In the pre-charging stage, the clock signal wck is at a low level, the A10 and A13 tubes are turned on, and the nodes OUT and OUTN are pre-charged to a high level; the inverted signal wckN of the clock signal is at a high level, the A3 and A4 tubes are turned on, and the nodes Node1 and Node2 are pulled down to a low level.

[0038] In the sampling phase, the clock signal wck is at a high level, the A10 and A13 tubes are turned off, the inverted signal wckN of the clock signal is at a low level, the A3 and A4 tubes are turned off, and the data receiving structure samples the input signal DQ based on the reference signal Vref, and outputs the sampling results at nodes OUT and OUTN.

[0039] Assume that the level of the input signal DQ is greater than the level of the reference signal Vref, the conductivity of the A2 tube is greater than the conductivity of the A1 tube, and the A5 tube is turned on based on the inverted signal wckN of the low-level clock signal, so that the voltage of the node Node2 is greater than the voltage of the node Node1. The voltage of the node Node2 is used to turn on the A7 tube, and the voltage of the node Node1 is used to turn on the A6 tube. At this time, the conductivity of the A7 tube is greater than the conductivity of the A6 tube, and after pre-charging, the node OUT and the node OUTN are both high levels. The A8 and A9 tubes are turned on, the A7 tube pulls down the potential of the node OUTN, and the A6 tube pulls down the potential of the node OUT. Since the pull-down speed of the A7 tube is faster, the potential of the node OUTN drops faster than the potential of the node OUT. The A11 tube is turned on first. After the A11 tube is turned on, it charges the node OUT, causing the potential of the node OUT to rise, thereby making the node OUT a high level and the node OUTN a low level.

[0040] Assume that the level of the input signal DQ is lower than the level of the reference signal Vref, the conduction degree of the A2 tube is lower than the conduction degree of the A1 tube, and the A5 tube is turned on based on the inverted signal wckN of the low-level clock signal, so that the voltage of the node Node2 is lower than the voltage of the node Node1. The voltage of the node Node2 is used to turn on the A7 tube, and the voltage of the node Node1 is used to turn on the A6 tube. At this time, the conduction degree of the A7 tube is lower than the conduction degree of the A6 tube, and after pre-charging, the node OUT and the node OUTN are both high. The A8 and A9 tubes are turned on, the A7 tube pulls down the potential of the node OUTN, and the A6 tube pulls down the potential of the node OUT. Since the pull-down speed of the A6 tube is faster, the potential of the node OUT drops faster than the potential of the node OUTN. The A12 tube is turned on first. After the A12 tube is turned on, it charges the node OUTN, causing the potential of the node OUTN to rise, thereby making the node OUTN high and the node OUT low.

[0041] It should be noted that, in some embodiments, the data receiving structure further includes a decision feedback equalization (DFE) module, as shown in Figure 1. DFE is a method for reducing inter-symbol interference (ISI) by using previous data to feed back subsequent data. Using DFE technology helps optimize the data eye diagram, increase the time domain span and voltage domain span, and ensure that the memory bus can transmit signals at a higher transmission rate.

[0042] Referring to Figure 2, which illustrates the output principle of a receiver during the precharge and sampling phases according to an embodiment of the present disclosure, the sampling phase includes S2 and S3. Ideally, during precharge phase S1, nodes OUT1 and OUT2 (where one of OUT1 and OUT2 represents OUT and the other represents OUTN) are precharged to the same value, as shown in Figure 2(A). At this point, during comparison phase S2, OUT2, which is pulled down faster, will preferentially turn on its corresponding transistor, allowing OUT1 to be charged during amplification phase S3. At this point, the output relationship between OUT1 and OUT2 is correct.

[0043] However, as the timing requirements of memory increase, more data needs to be output in the same time, which shortens the output time of each data and reduces the processing time of a single data. At this time, the time of S1 to S3 will be shortened, which may cause insufficient pre-charge time. After pre-charge, the potential of OUT2 is still smaller than that of OUT1, as shown in Figure 2(B) and Figure 2(C).

[0044] Assume that the voltage difference between OUT1 and OUT2 after pre-charging is V0. The potential of OUT1 drops by V1 in the comparison phase S2, and the potential of OUT2 drops by V2 in the comparison phase S2. When the value of V1-V2 is greater than V0, as shown in Figure 2(B), OUT1 will preferentially turn on the corresponding transistor, so that OUT2 is charged in the amplification phase S3. Since OUT1 drops faster in the comparison phase S2, it should output a low level. At this time, the output relationship between OUT1 and OUT2 is correct.

[0045] Assume that the voltage difference between OUT1 and OUT2 after pre-charging is V0. The potential of OUT1 drops by V1 in the comparison phase S2, and the potential of OUT2 drops by V2 in the comparison phase S2. When the value of V1-V2 is less than V0, as shown in Figure 2(C), OUT2 will preferentially turn on the corresponding transistor, so that OUT1 is charged in the amplification phase S3. Since OUT1 drops faster in the comparison phase S2, it should output a low level. At this time, the output relationship between OUT1 and OUT2 is incorrect, and the data receiving structure samples the input signal DQ incorrectly.

[0046] The receiver provided in this embodiment is used to avoid sampling errors of the input signal DQ.

[0047] Refer to Figure 3, which is a structural diagram of a receiver provided by an embodiment of the present disclosure. The receiver illustrated in Figure 3(A) does not include a DFE structure, while the receiver illustrated in Figure 3(B) includes a DFE structure. The receiver includes a first-stage sampling circuit 101, a second-stage sampling circuit 102, and an adjustment circuit 104.

[0048] The first-stage sampling circuit 101 is configured to receive an input signal DQ and a reference signal Vref, and to generate and output a sampling signal n1 and a complementary sampling signal p1 based on the input signal DQ and the reference signal during a sampling phase. In the sampling phase, if the potential of the input signal DQ is greater than the potential of the reference signal Vref, the potential of the generated complementary sampling signal p1 is greater than the potential of the sampling signal n1; and if the potential of the reference signal Vref is greater than the potential of the input signal DQ, the potential of the generated sampling signal n1 is greater than the potential of the complementary sampling signal p1.

[0049] The second-stage sampling circuit 102 is configured to receive a sampling signal n1 and a complementary sampling signal p1, and to amplify the sampling signal n1 and the complementary sampling signal p1 based on the voltage difference between the sampling signal n1 and the complementary sampling signal p1 during the sampling phase, and output a data signal OUT and a complementary data signal OUTN. In the sampling phase, if the potential of the sampling signal n1 is greater than the potential of the complementary sampling signal p1, the generated complementary data signal OUTN is high and the data signal OUT is low; if the potential of the complementary sampling signal p1 is greater than the potential of the sampling signal n1, the generated data signal OUT is high and the complementary data signal OUTN is low.

[0050] For the first-stage sampling circuit 101 and the second-stage sampling circuit 102, in the sampling phase, if the potential of the input signal DQ is greater than the potential of the reference signal Vref, the generated data signal OUT is high and the complementary data signal OUTN is low; if the potential of the reference signal Vref is greater than the potential of the input signal DQ, the generated complementary data signal OUTN is high and the data signal OUT is low.

[0051] The adjustment circuit 104 is connected to the first-stage sampling circuit 101 and the second-stage sampling circuit 102 respectively, and is configured to receive the sampling signal n1 and the complementary sampling signal p1, and adjust the amplification speed of the second-stage sampling circuit 102 based on the sampling signal n1 and the complementary sampling signal p1 during the sampling phase.

[0052] Referring to FIG2 , the receiver provided in this example is used to improve the amplification speed of the second-stage sampling circuit 102 . Referring to FIG2(D), the adjusted OUT1 and OUT2 are illustrated with dotted lines, so that in the comparison phase S2, the pull-down speeds of OUT1 and OUT2 are faster to conform to the output example shown in FIG2(B). Even if there is a voltage difference after pre-charging, the pull-down speeds of OUT1 and OUT2 are fast enough to compensate for the voltage difference after pre-charging, so that the output relationship between OUT1 and OUT2 is correct.

[0053] In some embodiments, the first-stage sampling circuit 101 is further configured to discharge its output terminal based on the clock signal wck or the complementary clock signal wckN during a precharge phase to generate and output a low-level sampling signal n1 and a complementary sampling signal p1; wherein the clock signal wck and the complementary clock signal wckN are inverted signals of each other. The second-stage sampling circuit 102 is further configured to precharge its output terminal at a precharge node based on the clock signal wck or the complementary clock signal wckN to generate and output a high-level data signal OUT and a complementary data signal OUTN. The adjustment circuit 104 is further configured to adjust the precharge speed of the second-stage sampling circuit 102 based on the sampling signal n1 and the complementary sampling signal p1 during the precharge phase.

[0054] 2 , the receiver provided in this example is also used to improve the pre-charging speed of the second-stage sampling circuit 102 . Referring to FIG. 2 (D ), the adjusted OUT1 and OUT2 are illustrated with dotted lines so that before the comparison stage S2 , the potentials of OUT1 and OUT2 are as consistent as possible to conform to the output example of FIG. 2 (A ). At this time, the output relationship between OUT1 and OUT2 must be correct.

[0055] In one example, when the clock signal wck is high or the complementary clock signal wckN is low, the receiver is in the sampling phase; when the clock signal wcn is low or the complementary clock signal wckN is high, the receiver is in the pre-charging phase.

[0056] In some embodiments, the receiver further includes a decision feedback equalization (DFE) circuit 103 configured to adjust the potential of the sampled signal n1 and the complementary sampled signal p1 based on the previously output data signal OUT and the complementary data signal OUTN. The DFE technique is used to reduce intersymbol interference between adjacent input signals, thereby optimizing the data eye diagram, increasing the time domain span and the voltage domain span, and ensuring that the memory bus can transmit signals at a higher transmission rate.

[0057] Specifically, the decision feedback equalization circuit 103 adjusts the potential of the sampling signal n1 and the potential of the complementary sampling signal p1 based on the feedback of the previous data signal or the previous complementary data signal, where the previous data signal and the previous complementary data signal are inverted signals. If the previous data signal is at a high level, the potential of the complementary sampling signal p1 is adaptively reduced and the potential of the sampling signal n1 is increased. If the previous data signal is at a low level, the potential of the complementary sampling signal p1 is adaptively increased and the potential of the sampling signal n1 is reduced.

[0058] It should be noted that the decision feedback equalization circuit 103 is assumed to exist in the subsequent figures and descriptions of this embodiment, and the potential of the sampling signal n1 and the potential of the complementary sampling signal p1 are assumed to be the potentials adjusted by the decision feedback equalization circuit 103. The presence or absence of the decision feedback equalization circuit 103 does not constitute a limitation on the receiver provided by this embodiment. In some examples, the decision feedback equalization circuit 103 may not be provided in the receiver provided by this embodiment.

[0059] In some embodiments, referring to Figures 3 and 4, Figure 4 is a structural diagram of a specific receiver provided by an embodiment of the present disclosure, and the first-stage sampling circuit 101 includes: a first driving transistor P3, a control end for receiving a complementary clock signal wckN, and a first end for receiving a second power supply voltage; a first P-type transistor P1, a control end for receiving an input signal DQ, a first end connected to the second end of the first driving transistor P3, and a second end for outputting a sampling signal n1; a second P-type transistor P2, a control end for receiving a reference signal Vref, a first end connected to the second end of the first driving transistor P3, and a second end for outputting a complementary sampling signal p1; a first N-type transistor N1, a control end for receiving the complementary clock signal wckN, a first end connected to the second end of the first P-type transistor P1, and a second end grounded; a second N-type transistor N2, a control end connected to the control end of the first N-type transistor N1, a first end connected to the second end of the second P-type transistor P2, and a second end grounded.

[0060] When the clock signal wck is low (the complementary clock signal wckN is high), the first-stage sampling circuit 101 operates in a precharge phase. When the clock signal wck is high (the complementary clock signal wckN is low), the first-stage sampling circuit 101 operates in a sampling phase. During the precharge phase, the complementary clock signal wckN is high, the first driver transistor P3 is off, and the first N-type transistor N1 and the second N-type transistor N2 are on, pulling the potential of the sampling signal n1 and the potential of the complementary sampling signal p1 down to a low level. During the sampling phase, the complementary clock signal wckN is low, the first N-type transistor N1 and the second N-type transistor N2 are off, the first driver transistor P3 is on, and the first P-type transistor P1 and the second P-type transistor P2 sample the input signal DQ and the reference signal Vref, respectively, to generate the sampling signal n1 and the complementary sampling signal p1. Specifically, assuming that the level of the input signal DQ is greater than the level of the reference signal Vref, the conductivity of the second P-type transistor P2 is greater than the conductivity of the first P-type transistor P1, so that the potential of the complementary sampling signal p1 is greater than the potential of the sampling signal n1; assuming that the level of the input signal DQ is less than the level of the reference signal Vref, the conductivity of the second P-type transistor P2 is less than the conductivity of the first P-type transistor P1, so that the potential of the complementary sampling signal p1 is less than the potential of the sampling signal n1.

[0061] In some embodiments, referring to FIG3 and FIG4, the second-stage sampling circuit 102 includes: a second driving transistor P6, a control terminal for receiving the clock signal wck, and a first terminal for receiving the second power supply voltage; a third driving transistor P7, a control terminal for receiving the clock signal wck, and a first terminal for receiving the second power supply voltage; a third P-type transistor P4, a control terminal connected to the second terminal of the second driving transistor P6 and for outputting the complementary data signal OUTN, a first terminal for receiving the second power supply voltage, and a second terminal connected to the second terminal of the second driving transistor P6; a fourth P-type transistor P5, a control terminal connected to the second terminal of the third driving transistor P7, and for outputting the data signal OUT. The first end is used to receive the second power supply voltage, and the second end is connected to the second end of the third driving transistor P7; the third N-type transistor N3, the control end is connected to the second end of the second driving transistor P6, and the first end is connected to the second end of the second driving transistor P6; the fourth N-type transistor N4, the control end is connected to the second end of the third driving transistor P7, and the first end is connected to the second end of the third driving transistor P7; the fifth N-type transistor N5, the control end is used to receive the sampling signal n1, the first end is connected to the second end of the third N-type transistor N3, and the second end is grounded; the sixth N-type transistor N6, the control end is used to receive the complementary sampling signal p1, the first end is connected to the second end of the fourth N-type transistor N4, and the second end is grounded.

[0062] When the clock signal wck is low (the complementary clock signal wckN is high), the second-stage sampling circuit 102 operates in a precharge phase. When the clock signal wck is high (the complementary clock signal wckN is low), the second-stage sampling circuit 102 operates in a sampling phase. During the precharge phase, the second driver transistor P6 and the third driver transistor P7 are turned on, precharging the potential of the data signal OUT and the potential of the complementary data signal OUTN to a high level. During the sampling phase, the second driver transistor P6 and the third driver transistor P7 are turned off, outputting the data signal OUT and the complementary data signal OUTN. Specifically, assuming that the level of the input signal DQ is greater than the level of the reference signal Vref, the complementary sampling signal p1 is used to turn on the sixth N-type transistor N6, and the sampling signal n1 is used to turn on the fifth N-type transistor N5. At this time, the conductivity of the sixth N-type transistor N6 is greater than that of the fifth N-type transistor N5, and after pre-charging, the data signal OUT and the complementary data signal OUTN are both high. The third N-type transistor N3 and the fourth N-type transistor N4 are turned on, the sixth N-type transistor N6 pulls down the potential of the complementary data signal OUTN, and the fifth N-type transistor N5 pulls down the potential of the data signal OUT. Since the sixth N-type transistor N6 pulls down faster, the potential of the complementary data signal OUTN drops faster than the potential of the data signal OUT. The third P-type transistor P4 is turned on first. After the third P-type transistor P4 is turned on, the data signal OUT is charged, causing the potential of the data signal OUT to rise, thereby causing the data signal OUT to be high and the complementary data signal OUTN to be low. Assume that the level of the input signal DQ is lower than the level of the reference signal Vref, the complementary sampling signal p1 is used to turn on the sixth N-type transistor N6, and the sampling signal n1 is used to turn on the fifth N-type transistor N5. At this time, the conduction degree of the sixth N-type transistor N6 is lower than the conduction degree of the fifth N-type transistor N5, and after pre-charging, the data signal OUT and the complementary data signal OUTN are both high. The third N-type transistor N3 and the fourth N-type transistor N4 are turned on, the sixth N-type transistor N6 pulls down the potential of the complementary data signal OUTN, and the fifth N-type transistor N5 pulls down the potential of the data signal OUT. Since the fifth N-type transistor N5 pulls down the potential faster, the potential of the data signal OUT drops faster than the potential of the complementary data signal OUTN. The fourth P-type transistor P5 is turned on first. After the fourth P-type transistor P5 is turned on, the complementary data signal OUTN is charged, causing the potential of the complementary data signal OUTN to rise, thereby causing the complementary data signal OUTN to be high and the data signal OUT to be low.

[0063] In some embodiments, referring to Figures 4 and 5, Figure 5 is a structural diagram of an adjustment circuit based on a single transistor arrangement provided in an embodiment of the present disclosure based on the example of Figure 3. The adjustment circuit 104 includes: a first pull-up transistor TP1, a first end for receiving a first power supply voltage, a second end connected to a first output end of the second-stage sampling circuit 102, the first output end for outputting a data signal OUT, and a control end for receiving a sampling signal n1; a second pull-up transistor TP2, a first end for receiving the first power supply voltage, a second end connected to a second output end of the second-stage sampling circuit 102, the second output end for outputting a complementary data signal OUTN, and a control end for receiving a complementary sampling signal p1.

[0064] Based on the foregoing, it can be seen that in the pre-charging stage, the sampling signal n1 and the complementary sampling signal p1 are at a low level. The low-level sampling signal n1 turns on the first pull-up transistor TP1. After the first pull-up transistor TP1 is turned on, the first output terminal is pre-charged based on the first power supply voltage to increase the pre-charging speed of the data signal OUT; the low-level complementary sampling signal p1 turns on the second pull-up transistor TP2. After the second pull-up transistor TP2 is turned on, the second output terminal is pre-charged based on the first power supply voltage to increase the pre-charging speed of the complementary data signal OUTN.

[0065] In the sampling phase, assuming that the level of the input signal DQ is greater than the level of the reference signal Vref, and the level of the sampling signal n1 is less than the level of the complementary sampling signal p1, the charging speed of the first pull-up transistor TP1 is greater than the charging speed of the second pull-up transistor TP2, so as to ensure that the data signal OUT outputted from the first output terminal is a high level; assuming that the level of the input signal DQ is less than the level of the reference signal Vref, and the level of the sampling signal n1 is greater than the level of the complementary sampling signal p1, the charging speed of the first pull-up transistor TP1 is less than the charging speed of the second pull-up transistor TP2, so as to ensure that the complementary data signal OUTN outputted from the second output terminal is a low level.

[0066] In some embodiments, referring to FIG. 4 , the adjustment circuit 104 further includes a first equalizing transistor EQ1 having a first terminal connected to the first output terminal, a second terminal connected to the second output terminal, and a control terminal configured to receive a clock signal wck. The first equalizing transistor EQ1 is configured to be turned on in response to a low-level clock signal wck. When the clock signal wck is low, the receiver is in a pre-charge phase. That is, in the pre-charge phase, the first equalizing transistor EQ1 is configured to connect the first output terminal and the second output terminal to ensure that the potential of the data signal OUT is consistent with the potential of the complementary data signal OUTN.

[0067] In some embodiments, referring to FIG4 and FIG5 , the adjustment circuit 104 is driven based on a first power supply voltage Vcc1, and the first-stage sampling circuit 101 and the second-stage sampling circuit 102 are driven based on a second power supply voltage Vcc2. The first power supply voltage Vcc1 is greater than the second power supply voltage Vcc2. By configuring the adjustment circuit 104 to be driven based on the larger first power supply voltage Vcc1, the pre-charging capability of the adjustment circuit 104 is enhanced and the efficiency of the amplification speed is increased, thereby enabling the adjustment circuit 104 to achieve a better improvement effect on the receiver.

[0068] In some embodiments, referring to FIG6, FIG6 is a schematic structural diagram of an adjustment circuit based on a multi-transistor arrangement provided in an embodiment of the present disclosure based on the example of FIG3, the adjustment circuit 104 includes: a plurality of first pull-up control circuits 204, configured to, based on the first control signal K1 <n:0>and sampling signal n1, adjust the pull-up speed of the first output terminal of the second stage sampling circuit 102; wherein each first pull-up control circuit 204 includes a first control transistor KP1 and a first pull-up transistor TP1 connected in series, and the first control signal K1 <n:0>The first control sub-signals K1 correspond to the first control transistors KP1. <0> ~K1 <n>wherein the first end of the first control transistor KP1 is used to receive the first power supply voltage Vcc1, the second end of the first control transistor KP1 is connected to the first end of the first pull-up transistor TP1, the second end of the first pull-up transistor TP1 is connected to the first output end of the second-stage sampling circuit 102, and the control end of the first control transistor KP1 is used to receive the first control sub-signal (K1) corresponding thereto; <0> ~K1 <n>One of the first pull-up transistor TP1, the control end is used to receive the sampling signal n1; a plurality of second pull-up control circuits 205, is configured to, based on the second control signal K2 <n:0>and complementary sampling signal p1, adjust the pull-up speed of the second output terminal of the second sampling circuit 102; wherein each second pull-up control circuit 205 includes a second control transistor KP2 and a second pull-up transistor TP2 connected in series, and the second control signal K2 <n:0>including a plurality of second control sub-signals K2 corresponding one to one with the second control transistors KP2 <0> ~K2 <n>wherein the first end of the second control transistor KP2 is used to receive the first power supply voltage Vcc1, the second end of the second control transistor KP2 is connected to the first end of the second pull-up transistor TP2, the second end of the second pull-up transistor TP2 is connected to the second output end of the second-stage sampling circuit 102, and the control end of the second control transistor KP2 is used to receive the second control sub-signal (K2) corresponding thereto; <0> ~K2 <n>The control terminal of the second pull-up transistor TP2 is used to receive the complementary sampling signal p1. The adjustment circuit 104 implemented by the first pull-up control circuit 204 and the second pull-up control circuit 205 can be controlled by the first control signal K1 <n:0>and the second control signal K2 <n:0>A corresponding number of first pull-up transistors TP1 and second pull-up transistors TP2 are selectively turned on to implement compensation control of the pull-up speed of the first output terminal and the second output terminal with adjustable adjustment.

[0069] In some embodiments, referring to FIG7 , FIG7 is a schematic diagram of the structure of the regulation control circuit provided in a receiver according to an embodiment of the present disclosure. The receiver further includes: a regulation control circuit 401, which is respectively connected to a plurality of first pull-up control circuits 204 and a plurality of second pull-up control circuits 205 and is configured to regulate the first control signal K1 <n:0>and the second control signal K2 <n:0>, and acquire and latch the current first control signal K1 based on the optimal eye diagram of the data signal OUT and the complementary data signal OUTN <n:0>and the second control signal K2 <n:0>By setting the adjustment control circuit 401 to adjust the first control signal K1 during the test phase <n:0>and the second control signal K2 <n:0>To make the eye diagram of the receiver achieve the best effect, after the receiver is put into use, based on the latched first control signal K1 <n:0>and the second control signal K2 <n:0>The first pull-up control circuit 204 and the second pull-up control circuit 205 are driven to achieve optimal compensation for the first output terminal and the second output terminal.

[0070] In some embodiments, referring to FIG. 4 , the second-stage sampling circuit 102 further includes a second equalizing transistor EQ2 having a first end connected to the first end of the third N-type transistor N3, a second end connected to the first end of the fourth N-type transistor N4, and a control end configured to receive the complementary clock signal wckN. The second equalizing transistor EQ2 is configured to be turned on in response to a high-level complementary clock signal wckN. When the complementary clock signal wckN is high, the receiver is in a pre-charge phase. That is, in the pre-charge phase, the second equalizing transistor EQ2 is configured to connect the first end of the third N-type transistor N3 and the first end of the fourth N-type transistor N4, so that the second-stage sampling circuit 102 pulls down the potential of the data signal OUT at the same speed as the complementary data signal OUTN, thereby ensuring that the potential of the data signal OUT is consistent with the potential of the complementary data signal OUTN.

[0071] In the description of the transistor in the above embodiment, the control terminal serves as the gate of the transistor, one of the first terminal and the second terminal serves as the source of the transistor, and the other serves as the drain of the transistor, and the positions of the source and drain of the transistor are interchangeable.

[0072] It should be noted that the features disclosed in the receivers provided in the above embodiments can be arbitrarily combined without conflict to obtain new receiver embodiments.

[0073] Another embodiment of the present disclosure further provides a data receiving structure, which is at least used to improve the electrical performance of a receiver.

[0074] The receiver provided in this embodiment is described in detail below with reference to the accompanying drawings, specifically as follows:

[0075] Refer to Figure 8, which is a structural diagram of a data receiving structure provided by another embodiment of the present disclosure. The data receiving structure 300 includes: N data receiving units 301, which are driven in sequence based on N phase clocks (wck0~wckn), and each of the N data receiving units 301 is set based on the receiver provided in the above embodiment, where N is a positive integer.

[0076] In an example, assuming N=4, the four phase clocks are wck0, wck1, wck2, and wck3. Among the four data receiving units 301, the first data receiving unit 301-0 is used to output the data signal OUT0 and the complementary data signal OUTN0, the second data receiving unit 301-1 is used to output the data signal OUT1 and the complementary data signal OUTN1, the third data receiving unit 301-2 is used to output the data signal OUT2 and the complementary data signal OUTN2, and the fourth data receiving unit 301-3 is used to output the data signal OUT3 and the complementary data signal OUTN3.

[0077] Specifically, referring to Figure 9, which illustrates the receiving principle of a data receiving structure according to another embodiment of the present disclosure, the first data receiving unit 301-0 is controlled by clock signal wck0. When wck0 is high, the first data receiving unit 301-0 samples data and outputs data signal OUT0 and complementary data signal OUTN0. When wck0 is low, the first data receiving unit 301-0 performs a precharge. As previously mentioned, during the sampling process of data receiving unit 301, the first P-type transistor turns on to gradually pull up the sampling signal p0, and the second P-type transistor turns on to gradually pull up the complementary sampling signal n0. In Figure 9, the waveform of p0 is also plotted within n0 to illustrate the difference between n0 and p0, thereby enabling data sampling by the first data receiving unit 301-0. The second data receiving unit 301-1 is controlled by clock signal wck1. When wck1 is high, the second data receiving unit 301-1 samples data and outputs data signal OUT1 and complementary data signal OUTN1. When wck1 is low, the second data receiving unit 301-1 performs a precharge. As previously mentioned, during the sampling process of data receiving unit 301, the first P-type transistor turns on to gradually pull up the sampling signal p1, and the second P-type transistor turns on to gradually pull up the complementary sampling signal n1. In Figure 9, the waveform of p1 is also plotted within n1 to illustrate the difference between n1 and p1, thereby enabling data sampling for the second data receiving unit 301-1. The third data receiving unit 301-2 is controlled by clock signal wck2. When wck2 is high, the third data receiving unit 301-2 performs data sampling and outputs the data signal OUT2 and the complementary data signal OUTN2. When wck2 is low, the third data receiving unit 301-2 performs precharging. As previously mentioned, during the sampling process of data receiving unit 301, the first P-type transistor turns on to gradually pull up the sampling signal p1, and the second P-type transistor turns on to gradually pull up the complementary sampling signal n1. In Figure 9, the waveform of p2 is also plotted within n2 to illustrate the difference between n2 and p2, thereby enabling data sampling for the third data receiving unit 301-2. The fourth data receiving unit 301-3 is controlled by clock signal wck3. When wck3 is high, the fourth data receiving unit 301-3 samples data and outputs data signal OUT3 and complementary data signal OUTN3. When wck3 is low, the fourth data receiving unit 301-3 performs precharging. As previously mentioned, during the sampling process of data receiving unit 301, the first P-type transistor turns on to gradually pull up the sampling signal p3, and the second P-type transistor turns on to gradually pull up the complementary sampling signal n3. In Figure 9, the waveform of p3 is also plotted within n3 to illustrate the difference between n3 and p3, thereby implementing data sampling in the fourth data receiving unit 301-3.

[0078] For the driving process of the 4-phase clock, referring to Figure 9, the first data receiving unit 301-0 samples the input data Data based on wck0 and the reference signal Vref to output the first input data to the data signal OUT0 and the complementary data signal OUTN0; then, the second data receiving unit 301-1 samples the input data Data based on wck1 and the reference signal Vref to output the second input data to the data signal OUT1 and the complementary data signal OUTN1; then, the third data receiving unit 301-2 samples the input data Data based on wck2 and the reference signal Vref to output the third input data to the data signal OUT2 and the complementary data signal OUTN2; then, the fourth data receiving unit 301-3 samples the input data Data based on wck3 and the reference signal Vref to output the fourth input data to the data signal OUT3 and the complementary data signal OUTN3; thereafter, the input data Data is sampled in sequence according to the order of the first data receiving unit 301-0, the second data receiving unit 301-1, the third data receiving unit 301-2 and the fourth data receiving unit 301-3.

[0079] It is not difficult to find that this embodiment can be implemented in conjunction with the receiver provided in the previous embodiment. The relevant technical details mentioned in the previous embodiment are still valid in this embodiment and will not be repeated here to reduce repetition.

[0080] Another embodiment of the present disclosure provides a memory, which receives input data based on the receiver provided by the above embodiment, or receives input data based on the data receiving structure provided by the above embodiment, at least for improving the electrical performance of the receiver.

[0081] It should be noted that the memory may be a storage unit or device based on a semiconductor device or component. For example, the memory device may be a volatile memory, such as dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), low power double data rate synchronous dynamic random access memory (LPDDR SDRAM), graphic double data rate synchronous dynamic random access memory (GDDR SDRAM), double data rate type dual synchronous dynamic random access memory (DDR2 SDRAM), double data rate type triple synchronous dynamic random access memory (DDR3 SDRAM), double data rate fourth generation synchronous dynamic random access memory (DDR4 SDRAM), thyristor random access memory (TRAM), etc.; or it may be a non-volatile memory, such as phase change random access memory (PRAM), magnetic random access memory (MRAM), resistive random access memory (RRAM), etc.

[0082] Those skilled in the art will appreciate that the above embodiments are specific embodiments for implementing the present disclosure, and that in actual applications, various changes may be made thereto in form and detail without departing from the spirit and scope of the present disclosure. < / n> < / n> < / n> < / n>

Claims

1. A receiver, wherein, Comprising: A first - stage sampling circuit (101), configured to receive an input signal (DQ) and a reference signal (Vref), and in a sampling phase, generate and output a sampling signal (n1) and a complementary sampling signal (p1) based on the input signal (DQ) and the reference signal (Vref); Wherein, if the potential of the input signal (DQ) is greater than the potential of the reference signal (Vref), the potential of the generated complementary sampling signal (p1) is greater than the potential of the sampling signal (n1); if the potential of the reference signal (Vref) is greater than the potential of the input signal (DQ), the potential of the generated sampling signal (n1) is greater than the potential of the complementary sampling signal (p1); A second - stage sampling circuit (102), configured to receive the sampling signal (n1) and the complementary sampling signal (p1), and in the sampling phase, amplify based on the voltage difference between the sampling signal (n1) and the complementary sampling signal (p1), and output a data signal (OUT) and a complementary data signal (OUTN); Wherein, if the potential of the sampling signal (n1) is greater than the potential of the complementary sampling signal (p1), the generated complementary data signal (OUTN) is at a high level and the data signal (OUT) is at a low level; if the potential of the complementary sampling signal (p1) is greater than the potential of the sampling signal (n1), the generated data signal (OUT) is at a high level and the complementary data signal (OUTN) is at a low level; An adjustment circuit (104), connected to the first - stage sampling circuit (101) and the second - stage sampling circuit (102) respectively, configured to receive the sampling signal (n1) and the complementary sampling signal (p1), and in the sampling phase, adjust the amplification speed of the second - stage sampling circuit (102) based on the sampling signal (n1) and the complementary sampling signal (p1).

2. The receiver according to claim 1, wherein, Comprising: The first - stage sampling circuit (101) is further configured to, in a pre - charge phase, discharge its output terminal based on a clock signal (wck) or a complementary clock signal (wckN) to generate and output the sampling signal (n1) and the complementary sampling signal (p1) at a low level; The second - stage sampling circuit (102) is further configured to, in the pre - charge phase, pre - charge its output terminal based on the clock signal (wck) or the complementary clock signal (wckN) to generate and output the data signal (OUT) and the complementary data signal (OUTN) at a high level; The adjustment circuit (104) is further configured to, in the pre - charge phase, adjust the pre - charge speed of the second - stage sampling circuit (102) based on the sampling signal (n1) and the complementary sampling signal (p1).

3. The receiver according to claim 2, wherein When the clock signal (wck) is at a high level or the complementary clock signal (wckN) is at a low level, the receiver is in the sampling phase; when the clock signal (wck) is at a low level or the complementary clock signal (wckN) is at a high level, the receiver is in the pre-charge phase.

4. The receiver according to any one of claims 1 to 3, wherein, The adjustment circuit (104) includes: A first pull-up transistor (TP1), the first end for receiving a first power supply voltage, the second end connected to the first output end of the second-stage sampling circuit (102), and the control end for receiving the sampling signal (n1); A second pull-up transistor (TP2), the first end for receiving a first power supply voltage, the second end connected to the second output end of the second-stage sampling circuit (102), and the control end for receiving the complementary sampling signal (p1); Wherein, the first output end is used to output the data signal (OUT), and the second output end is used to output the complementary data signal (OUTN).

5. The receiver according to claim 4, wherein, The adjustment circuit (104) further includes: a first equalization transistor (EQ1), the first end connected to the first output end, the second end connected to the second output end, and the control end for receiving the clock signal (wck).

6. The receiver according to any one of claims 1 to 5, wherein, The adjustment circuit (104) is driven based on a first power supply voltage, and the first-stage sampling circuit (101) and the second-stage sampling circuit (102) are driven based on a second power supply voltage, wherein the voltage value of the first power supply voltage is greater than the voltage value of the second power supply voltage.

7. The receiver according to any one of claims 1 to 6, wherein, The adjustment circuit (104) includes: A plurality of first pull-up control circuits (204), configured to adjust the pull-up speed of the first output end of the second-stage sampling circuit (102) based on a first control signal and the sampling signal (n1); Wherein, each of the first pull-up control circuits (204) includes a first control transistor (KP1) and a first pull-up transistor (TP1) connected in series, and the first control signal includes a plurality of first control sub-signals corresponding one-to-one to the first control transistor (KP1); wherein, the first end of the first control transistor (KP1) is for receiving a first power supply voltage, the second end of the first control transistor (KP1) is connected to the first end of the first pull-up transistor (TP1), the second end of the first pull-up transistor (TP1) is connected to the first output end of the second-stage sampling circuit (102), the control end of the first control transistor (KP1) is for receiving the corresponding first control sub-signal, and the control end of the first pull-up transistor (TP1) is for receiving the sampling signal (n1); A plurality of second pull-up control circuits (205), configured to adjust the pull-up speed of the second output end of the second-stage sampling circuit (102) based on a second control signal and the complementary sampling signal (p1); Each of the second pull-up control circuits (205) includes a second control transistor (KP2) and a second pull-up transistor (TP2) connected in series. The second control signal includes a plurality of second control sub-signals corresponding one-to-one to the second control transistors (KP2). The first end of the second control transistor (KP2) is configured to receive a first power supply voltage. The second end of the second control transistor (KP2) is connected to the first end of the second pull-up transistor (TP2). The second end of the second pull-up transistor (TP2) is connected to the second output end of the second-stage sampling circuit (102). The control end of the second control transistor (KP2) is configured to receive the corresponding second control sub-signal. The control end of the second pull-up transistor (TP2) is configured to receive the complementary sampling signal (p1). The first output end is configured to output the data signal (OUT), and the second output end is configured to output the complementary data signal (OUTN).

8. The receiver according to claim 7, wherein, Further comprising: An adjustment control circuit (401) connected to the plurality of first pull-up control circuits (204) and the plurality of second pull-up control circuits (205) respectively, configured to adjust the first control signal and the second control signal, and acquire and latch the current first control signal and second control signal based on the best eye diagram of the data signal (OUT) and the complementary data signal (OUTN).

9. The receiver according to any one of claims 1 to 8, wherein, The first-stage sampling circuit (101) includes: A first driving transistor (P3) whose control end is configured to receive a complementary clock signal (wckN) and whose first end is configured to receive a second power supply voltage; A first P-type transistor (P1) whose control end is configured to receive the input signal (DQ), whose first end is connected to the second end of the first driving transistor (P3), and whose second end is configured to output the sampling signal (n1); A second P-type transistor (P2) whose control end is configured to receive a reference signal (Vref), whose first end is connected to the second end of the first driving transistor (P3), and whose second end is configured to output the complementary sampling signal (p1); A first N-type transistor (N1) whose control end is configured to receive a complementary clock signal (wckN), whose first end is connected to the second end of the first P-type transistor (P1), and whose second end is grounded; A second N-type transistor (N2) whose control end is connected to the control end of the first N-type transistor (N1), whose first end is connected to the second end of the second P-type transistor (P2), and whose second end is grounded.

10. The receiver according to any one of claims 1 to 9, wherein, The second-stage sampling circuit (102) includes: A second driving transistor (P6) whose control end is configured to receive a clock signal (wck) and whose first end is configured to receive a second power supply voltage; A third driving transistor (P7) whose control end is configured to receive a clock signal (wck) and whose first end is configured to receive a second power supply voltage; A third P-type transistor (P4) whose control end is connected to the second end of the second driving transistor (P6) and is configured to output the complementary data signal (OUTN), whose first end is configured to receive a second power supply voltage, and whose second end is connected to the second end of the second driving transistor (P6); The fourth P-type transistor (P5) has its control terminal connected to the second terminal of the third driving transistor (P7) and is used for outputting the data signal (OUT). Its first terminal is used for receiving the second power supply voltage, and its second terminal is connected to the second terminal of the third driving transistor (P7). The third N-type transistor (N3) has its control terminal connected to the second terminal of the second driving transistor (P6), and its first terminal is connected to the second terminal of the second driving transistor (P6). The fourth N-type transistor (N4) has its control terminal connected to the second terminal of the third driving transistor (P7), and its first terminal is connected to the second terminal of the third driving transistor (P7). The fifth N-type transistor (N5) has its control terminal for receiving the sampling signal (n1), its first terminal connected to the second terminal of the third N-type transistor (N3), and its second terminal grounded. The sixth N-type transistor (N6) has its control terminal for receiving the complementary sampling signal (p1), its first terminal connected to the second terminal of the fourth N-type transistor (N4), and its second terminal grounded.

11. The receiver according to claim 10, wherein, The second-stage sampling circuit (102) further includes: a second equalization transistor (EQ2), whose first terminal is connected to the first terminal of the third N-type transistor (N3), second terminal is connected to the first terminal of the fourth N-type transistor (N4), and control terminal is for receiving the complementary clock signal (wckN).

12. The receiver according to any one of claims 1 to 11, wherein, It further includes: a decision feedback equalization circuit (103), configured to feedback and adjust the potential of the sampling signal (n1) and the potential of the complementary sampling signal (p1) based on the previously output data signal (OUT) and the complementary data signal (OUTN).

13. A data receiving structure (300), wherein, It includes: N data receiving units (301), the N data receiving units (301) are driven in sequence based on an N-phase clock, and each data receiving unit (301) among the N data receiving units (301) is arranged according to the receiver described in any one of claims 1 to 12, where N is a positive integer.

14. A memory, wherein, Receiving input data based on the receiver described in any one of claims 1 to 12, or receiving input data based on the data receiving structure (300) described in claim 13.

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