Capacitor and method for producing same

Abstract

In this capacitor, a p-type silicon substrate includes a porous part having a plurality of pores. In the porous part, the spacing between adjacent pores among the plurality of pores is non-uniform in the thickness direction of the p-type silicon substrate. The p-type silicon substrate has a surface region including a portion of the surface of the porous part in the thickness direction of the p-type silicon substrate, and a body region surrounding the surface region. The carrier concentration in the surface region is lower than the carrier concentration in the body region. The plurality of pores are formed across the surface region and the body region in the thickness direction of the p-type silicon substrate. A first external connection electrode is disposed in a body region of the p-type silicon substrate.

Description

Capacitor and manufacturing method thereof

[0001] The present disclosure relates to a capacitor and a manufacturing method thereof, and more particularly to a capacitor including a porous portion and a manufacturing method thereof.

[0002] The capacitor disclosed in Patent Document 1 includes a silicon substrate, a conductive layer, and a dielectric layer. The silicon substrate includes a porous portion extending in the thickness direction. The porous portion has a plurality of pores.

[0003] International Publication No. 2020 / 184517

[0004] In a capacitor, it is sometimes desired to increase the capacitance while reducing the ESR (Equivalent Series Resistance).

[0005] A capacitor according to one aspect of the present disclosure comprises a p-type silicon substrate, a dielectric layer, a conductor layer, a first external connection electrode, and a second external connection electrode. The p-type silicon substrate includes a porous portion having a plurality of pores. The dielectric layer is disposed on the surface of the porous portion of the p-type silicon substrate. The conductor layer is laminated on the dielectric layer. The first external connection electrode is connected to the p-type silicon substrate. The second external connection electrode is connected to the conductor layer. In the porous portion, the spacing between adjacent pores among the plurality of pores is non-uniform in the thickness direction of the p-type silicon substrate. The p-type silicon substrate has a surface region including a portion of the surface of the porous portion in the thickness direction of the p-type silicon substrate, and a body region surrounding the surface region. The carrier concentration of the surface region is lower than the carrier concentration of the body region. The plurality of pores are formed across the surface region and the body region in the thickness direction of the p-type silicon substrate. The first external connection electrode is disposed in the body region of the p-type silicon substrate.

[0006] A capacitor manufacturing method according to another aspect of the present disclosure is the capacitor manufacturing method according to the above aspect, comprising the steps of preparing a p-type silicon wafer that will become the p-type silicon substrate, forming a p-type doped region that will become the surface region in the p-type silicon wafer, forming a porous portion by anodizing the doped region of the p-type silicon wafer while it is exposed, forming a dielectric layer on the surface of the porous portion in the p-type silicon wafer, forming a conductor layer on the dielectric layer, forming a first external connection electrode on the p-type silicon wafer, and forming a second external connection electrode on the conductor layer.

[0007] According to the capacitor and the manufacturing method thereof according to the above aspects of the present disclosure, it is possible to increase the capacitance while reducing the ESR.

[0008] FIG. 1 is a schematic cross-sectional view of a capacitor according to an embodiment. FIG. 2 is a plan view of the capacitor. FIG. 3A is a cross-sectional view illustrating steps of a method for manufacturing the capacitor. FIG. 3B is a cross-sectional view illustrating steps of a method for manufacturing the capacitor. FIG. 4A is a cross-sectional view illustrating steps of a method for manufacturing the capacitor. FIG. 4B is a cross-sectional view illustrating steps of a method for manufacturing the capacitor. FIG. 5 is a plan view illustrating steps of a method for manufacturing the capacitor. FIG. 6A is a cross-sectional view illustrating steps of a method for manufacturing the capacitor. FIG. 6B is a cross-sectional view illustrating steps of a method for manufacturing the capacitor.

[0009] 1 to 6 described in the following embodiments are schematic diagrams, and the ratios of the sizes and thicknesses of the components in the drawings do not necessarily reflect the actual dimensional ratios.

[0010] (Embodiment) (1) Capacitor A capacitor 1 according to an embodiment will be described below with reference to Figures 1 and 2. Figure 1 is a cross-sectional view taken along line XX of Figure 2.

[0011] The capacitor 1 according to the embodiment includes a p-type silicon substrate 2, a dielectric layer 4, a conductor layer 5, a first external connection electrode 6, and a second external connection electrode 7. The p-type silicon substrate 2 includes a porous portion 23 having a plurality of pores 24. The dielectric layer 4 is disposed on a surface 231 of the porous portion 23 in the p-type silicon substrate 2. The conductor layer 5 is laminated on the dielectric layer 4. The first external connection electrode 6 is connected to the p-type silicon substrate 2. The second external connection electrode 7 is connected to the conductor layer 5. In the porous portion 23, the spacing L1 between adjacent pores 24 is non-uniform in the thickness direction D1 of the p-type silicon substrate 2. The p-type silicon substrate 2 includes a surface region 25 including a portion of the surface 231 of the porous portion 23 in the thickness direction D1 of the p-type silicon substrate 2, and a body region 26 surrounding the surface region 25. The carrier concentration of the surface region 25 is lower than the carrier concentration of the body region 26. The plurality of pores 24 are formed across the surface region 25 and the body region 26 in the thickness direction D1 of the p-type silicon substrate 2. The first external connection electrode 6 is disposed in the body region 26 of the p-type silicon substrate 2.

[0012] The capacitor 1 according to the embodiment can increase the capacitance while reducing the ESR.

[0013] (2) Components of the Capacitor Each component of the capacitor 1 according to the embodiment will be described below with reference to FIGS. 1 and 2. FIG.

[0014] (2.1) Silicon Substrate As shown in FIG. 1 , the p-type silicon substrate 2 has a first main surface 21 and a second main surface 22 opposite to the first main surface 21. The first main surface 21 and the second main surface 22 are aligned in the thickness direction D1 and are both perpendicular to the thickness direction D1. When viewed from above in the thickness direction D1 of the p-type silicon substrate 2, the outer edge of the p-type silicon substrate 2 has a rectangular shape. The thickness of the p-type silicon substrate 2 is, for example, not less than 300 μm and not more than 1 mm.

[0015] The p-type silicon substrate 2 includes a porous portion 23. In a plan view from the thickness direction D1 of the p-type silicon substrate 2, a first region A1 in which the porous portion 23 is formed is a rectangular region. In a plan view from the thickness direction D1 of the p-type silicon substrate 2, the first region A1 is surrounded by the second region A2. When viewed from the thickness direction D1 of the p-type silicon substrate 2, the first region A1 is not limited to a rectangular region, and may be, for example, a circular region or a polygonal region other than a rectangular shape.

[0016] The porous portion 23 has a plurality of pores 24 arranged along the thickness direction D1 of the p-type silicon substrate 2. In the porous portion 23, the distance L1 between adjacent pores 24 in directions D2 and D3 perpendicular to the thickness direction D1 is non-uniform in the thickness direction D1 of the p-type silicon substrate 2.

[0017] The plurality of pores 24 are formed in the first main surface 21 of the p-type silicon substrate 2. Each of the plurality of pores 24 is an elongated hole extending from the first main surface 21 of the p-type silicon substrate 2 in the thickness direction D1 of the p-type silicon substrate 2, with the depth being longer than the opening width of the pore 24 in the first main surface 21 of the p-type silicon substrate 2. The plurality of pores 24 are formed from the first main surface 21 of the p-type silicon substrate 2 along the thickness direction D1 of the p-type silicon substrate 2, and do not reach the second main surface 22 of the p-type silicon substrate 2. In other words, the plurality of pores 24 do not penetrate the p-type silicon substrate 2 in the thickness direction D1 of the p-type silicon substrate 2. That is, the plurality of pores 24 are separated from the second main surface 22 of the p-type silicon substrate 2. The opening width of each of the plurality of pores 24 in the first main surface 21 of the p-type silicon substrate 2 is, for example, not less than 0.1 μm and not more than 10 μm. The depth of the pores 24 is smaller than the thickness of the p-type silicon substrate 2. The depth of each of the pores 24 in the thickness direction D1 of the p-type silicon substrate 2 is, for example, 20 μm or more and 300 μm or less, and more preferably 30 μm or more and 100 μm or less. The upper limit of the depth of the pores 24 may be determined appropriately depending on, for example, the opening width of the pores 24 and the methods for forming the dielectric layer 4 and the conductor layer 5. The opening width and depth of the pores 24 in the porous portion 23 of the p-type silicon substrate 2 are values ​​determined, for example, from a cross-sectional SEM (Scanning Electron Microscope) image of the capacitor 1.

[0018] The surface 231 of the porous portion 23 includes an inner surface 241 including the inner side surfaces 24a and bottom surfaces 242 of each of the multiple pores 24 formed in the first main surface 21 of the p-type silicon substrate 2, and a surface 21a in the first region A1 of the first main surface 21 of the p-type silicon substrate 2.

[0019] In the capacitor 1, the deeper the pores 24 in the porous portion 23, the larger the surface area of ​​the surface 231 of the porous portion 23, thereby increasing the capacitance of the capacitor 1. Furthermore, in the capacitor 1, the larger the number of pores 24 in the porous portion 23, the larger the surface area of ​​the surface 231 of the porous portion 23, thereby increasing the capacitance of the capacitor 1.

[0020] As described above, in the capacitor 1, the distance L1 between two adjacent pores 24 among the plurality of pores 24 is non-uniform in the thickness direction D1 of the p-type silicon substrate 2. In the capacitor 1, the surface area of ​​the surface 231 of the porous portion 23 can be increased compared to when the distance L1 between two adjacent pores 24 among the plurality of pores 24 is uniform in the thickness direction D1 of the p-type silicon substrate 2. Note that the distance L1 between two adjacent pores 24 among the plurality of pores 24 becomes uniform in the thickness direction D1 of the p-type silicon substrate 2 when the plurality of pores 24 are formed by, for example, dry etching. Furthermore, in the capacitor 1, the opening width of each of the plurality of pores 24 is non-uniform in the thickness direction D1 of the p-type silicon substrate 2.

[0021] In a cross-sectional view of the p-type silicon substrate 2 from a second direction D2 (see FIG. 2 ) perpendicular to the thickness direction D1 (hereinafter also referred to as the first direction D1) and the direction D3, as shown in FIG. 1 , the inner surface 24 a of one of two adjacent pores 24 and the inner surface 24 a of the other pore 24 are not straight lines but rather lines with irregularities. The height difference between the peaks and valleys of the irregularities is smaller than the opening width of the pores 24. The height difference between the peaks and valleys of the irregularities is a value determined, for example, from a cross-sectional SEM image of the capacitor 1. The height difference between the peaks and valleys of the irregularities can be changed, for example, by the impurity concentration of the p-type silicon wafer 20 (see FIG. 3A ) that is the basis of the p-type silicon substrate 2, the anodization conditions, etc.

[0022] The p-type silicon substrate 2 has a surface region 25 including a part of the surface 231 of the porous portion 23 in the thickness direction D1 of the p-type silicon substrate 2, and a body region 26 surrounding the surface region 25. In this embodiment, the body region 26 in the p-type silicon substrate 2 is a region (bulk region) other than the surface region 25 in the p-type silicon substrate 2.

[0023] In the p-type silicon substrate 2, the conductivity type of the body region 26 is p-type. Also, in the p-type silicon substrate 2, the conductivity type of the surface region 25 is p-type. In the p-type silicon substrate 2, the carrier concentration of the surface region 25 is lower than the carrier concentration of the body region 26. The multiple pores 24 are formed across the surface region 25 and the body region 26 in the thickness direction D1 of the p-type silicon substrate 2.

[0024] In the p-type silicon substrate 2, the body region 26 contains, for example, boron (B) as an impurity. In the p-type silicon substrate 2, the surface region 25 contains, for example, boron as an impurity. That is, in the p-type silicon substrate 2, the p-type impurity contained in the surface region 25 is the same as the p-type impurity contained in the body region 26. Each of the surface region 25 and the body region 26 contains boron as an impurity, but may contain indium as an impurity instead of boron.

[0025] The carrier concentration of the body region 26 in the p-type silicon substrate 2 is 1×10 １８ cm －３ The carrier concentration of the body region 26 is 1×10 １９ cm －３ The carrier concentration of the surface region 25 is 1×10 １３ cm －３ 1x10 or more １８ cm －３ is less than 1×10 １４ cm －３ 1x10 or more １６ cm －３ More preferably, it is less than 1000 .mu.m.

[0026] Each of the body region 26 and the surface region 25 contains boron or indium, and the surface region 25 further contains phosphorus, arsenic, or antimony.

[0027] The carrier concentration of the surface region 25 and the carrier concentration of the body region 26 are values ​​measured by observing the carrier concentration distribution of a cross section of the capacitor 1 using a scanning microwave impedance microscope (sMIM).

[0028] In the p-type silicon substrate 2, the thickness of the surface region 25 is preferably 0.2 μm or more and 2 μm or less, and more preferably 0.5 μm or more and 1.5 μm or less. In this embodiment, the thickness of the surface region 25 is 1 μm, for example. The thickness of the surface region 25 is a value determined by observing the cross section of the capacitor 1 by sMIM.

[0029] (2.2) Dielectric Layer The dielectric layer 4 is disposed across the surface 231 of the porous portion 23 in the p-type silicon substrate 2 and the surface in the second region A2 of the first main surface 21 of the p-type silicon substrate 2. More specifically, the dielectric layer 4 has a shape that follows the surface 231 of the porous portion 23 in the p-type silicon substrate 2 and the surface in the second region A2 of the first main surface 21 of the p-type silicon substrate 2. In other words, the dielectric layer 4 has a shape that follows the inner side surface 24 a and bottom surface 242 of the porous portion 23 and the first main surface 21 of the p-type silicon substrate 2.

[0030] The thickness of the dielectric layer 4 is, for example, 10 nm to 500 nm, and the upper limit of the thickness of the dielectric layer 4 is limited by the opening width of the pores 24 of the porous portion 23 in one direction along the first main surface 21 of the p-type silicon substrate 2, the thickness of the conductor layer 5 in the pores 24 of the porous portion 23 in the above-mentioned one direction, and the like.

[0031] The dielectric layer 4 has a multilayer structure in which a plurality of dielectric films are stacked, but is not limited to this and may be a single dielectric layer. When the dielectric layer 4 has a multilayer structure, it includes, for example, a first dielectric film (e.g., a first silicon oxide film), a second dielectric film (e.g., a silicon nitride film) on the first dielectric film, and a third dielectric film (e.g., a second silicon oxide film) on the second dielectric film. The material of the first silicon oxide film and the second silicon oxide film may be, for example, silicon dioxide (SiO ２ The composition of each of the first silicon oxide film and the second silicon oxide film is strictly SiO ２It is not essential that the first silicon oxide film and the second silicon oxide film have different compositions. When the dielectric layer 4 is formed of a single dielectric film, the material of the dielectric film is, for example, silicon oxide. The material of the dielectric film is not limited to silicon oxide, and may be, for example, titanium oxide, zirconium oxide, hafnium oxide, vanadium oxide, tungsten oxide, niobium oxide, tantalum oxide, or aluminum oxide.

[0032] (2.3) Conductor Layer The conductor layer 5 is laminated on the dielectric layer 4. The conductor layer 5 is formed on the dielectric layer 4. When viewed from above in the thickness direction D1 of the p-type silicon substrate 2, the conductor layer 5 overlaps the first region A1 and the second region A2 of the p-type silicon substrate 2. When viewed from above in the thickness direction D1 of the p-type silicon substrate 2, the conductor layer 5 overlaps the porous portion 23 and the surface region 25.

[0033] The conductive layer 5 is, for example, a conductive polysilicon layer. The impurity concentration of the conductive polysilicon layer is, for example, 1×10 １８ cm －３ 1x10 or more ２１ cm －３ is less than or equal to 5×10 １８ cm －３ 1x10 or more ２０ cm －３ It is more preferable that the impurity of the conductive polysilicon layer is, for example, one selected from the group consisting of boron, indium, phosphorus, arsenic, and antimony. The conductor layer 5 is not limited to a conductive polysilicon layer, and may be, for example, a metal electrode layer. The material of the metal electrode layer is, for example, at least one selected from the group consisting of ruthenium, titanium, tantalum, tungsten, and aluminum. More specifically, the material of the metal electrode layer is, for example, ruthenium, titanium, tantalum, tungsten, aluminum, or an alloy mainly containing any of these metals.

[0034] The conductor layer 5 has a first portion 51 overlapping the first region A1 and a second portion 52 overlapping the second region A2 in the thickness direction D1 of the p-type silicon substrate 2. The first portion 51 of the conductor layer 5 overlaps the porous portion 23 in a plan view from the thickness direction D1 of the p-type silicon substrate 2. The first portion 51 of the conductor layer 5 includes a plurality of columnar portions 512 located in a plurality of pores 24 of the porous portion 23 of the p-type silicon substrate 2, and a portion 511 where the plurality of columnar portions 512 are connected.

[0035] (2.4) First External Connection Electrode and Second External Connection Electrode The first external connection electrode 6 is connected to the body region 26 of the p-type silicon substrate 2, as shown in FIG. 1 . More specifically, the first external connection electrode 6 is connected to the body region 26 of the p-type silicon substrate 2 through a contact hole 47 formed in a portion 42 of the dielectric layer 4 that is located on the first main surface 21 of the p-type silicon substrate 2 in the second region A2 of the p-type silicon substrate 2. In the capacitor 1, the first external connection electrode 6 is electrically connected to the body region 26 of the p-type silicon substrate 2. "The first external connection electrode 6 is electrically connected to the body region 26 of the p-type silicon substrate 2" means that the first external connection electrode 6 and the body region 26 of the p-type silicon substrate 2 are in ohmic contact.

[0036] In a plan view from the thickness direction D1 of the p-type silicon substrate 2, the outer edge of the first external connection electrode 6 is, for example, rectangular (see FIG. 2 ), but is not limited to a rectangular shape and may be, for example, circular. In a plan view from the thickness direction D1 of the p-type silicon substrate 2, the first external connection electrode 6 overlaps a part of the second region A2 of the p-type silicon substrate 2, but does not overlap the first region A1. Therefore, in a plan view from the thickness direction D1 of the p-type silicon substrate 2, the first external connection electrode 6 does not overlap the porous portion 23 of the p-type silicon substrate 2.

[0037] The second external connection electrode 7 is connected to the conductive layer 5. In the capacitor 1, the second external connection electrode 7 is electrically connected to the conductive layer 5. "The second external connection electrode 7 is electrically connected to the conductive layer 5" means that the second external connection electrode 7 and the conductive layer 5 are in ohmic contact. In a plan view from the thickness direction D1 of the p-type silicon substrate 2, the second external connection electrode 7 overlaps a part of the second region A2 of the p-type silicon substrate 2, but does not overlap the first region A1. Therefore, in a plan view from the thickness direction D1 of the p-type silicon substrate 2, the second external connection electrode 7 does not overlap the porous portion 23 of the p-type silicon substrate 2.

[0038] The material of the first external connection electrode 6 and the second external connection electrode 7 includes, for example, aluminum, but is not limited to aluminum and may include, for example, gold, platinum, ruthenium, etc. The material of the second external connection electrode 7 is the same as the material of the first external connection electrode 6, but may be a material different from the material of the first external connection electrode 6.

[0039] The thickness of the first external connection electrode 6 and the second external connection electrode 7 is, for example, 1 μm or more and 3 μm or less. The thickness of the second external connection electrode 7 is the same as the thickness of the first external connection electrode 6, but may be different from the thickness of the first external connection electrode 6.

[0040] (3) Capacitor Manufacturing Method The method for manufacturing the capacitor 1 includes, for example, steps 1, 2, 3, 4, 5, 6, 7, 8, and 9. The method for manufacturing the capacitor 1 will be described below with reference to Figures 3A, 3B, 4A, 4B, 5, 6A, and 6B.

[0041] In the first step, a p-type silicon wafer 20 is prepared, which is the base of the p-type silicon substrate 2. The carrier concentration of the p-type silicon wafer 20 prepared in the first step is, for example, 1×10 １８ cm －３ 1x10 or more １９ cm －３The p-type silicon wafer 20 has a first main surface 201 and a second main surface 202 opposite to the first main surface 201. The first main surface 201 of the p-type silicon wafer 20 corresponds to the first main surface 21 of the p-type silicon substrate 2, and the second main surface 202 of the p-type silicon wafer 20 corresponds to the second main surface 22 of the p-type silicon substrate 2. The first main surface 201 of the p-type silicon wafer 20 is, for example, a (100) plane, but is not limited thereto and may be, for example, a (110) plane or a (111) plane. Furthermore, the first main surface 201 of the p-type silicon wafer 20 may be, for example, a crystal plane having an off-angle from the (100) plane of more than 0° and not more than 5°. Here, the "off-angle" refers to the inclination angle of the first main surface 201 with respect to the (100) plane. Therefore, if the off-angle is 0°, the first main surface 201 is a (100) plane.

[0042] In the second step, an insulating layer 9 (see FIG. 3A ) is formed on the first main surface 201 of the p-type silicon wafer 20. When forming the insulating layer 9, for example, a silicon oxide layer is formed on the entire surface of the first main surface 201 of the p-type silicon wafer 20 by, for example, thermal oxidation, and a silicon nitride layer is formed on the silicon oxide layer by, for example, a CVD (Chemical Vapor Deposition) method.

[0043] In the third step, the insulating layer 9 is patterned into a predetermined pattern using photolithography and etching (see FIG. 3B ). The predetermined pattern of the insulating layer 9 covers, for example, the region on the first main surface 201 of the p-type silicon wafer 20 that corresponds to the second region A2 of the p-type silicon substrate 2, but does not cover the region that corresponds to the first region A1.

[0044] In the fourth step, the p-type silicon wafer 20 is doped with n-type impurities using the insulating layer 9 as a mask, thereby forming a p-type doped region 250 having a lower carrier concentration than the body region 260 of the p-type silicon wafer 20 that is not doped with n-type impurities. The fourth step includes a diffusion step. In the diffusion step, the doped region 250 is formed by thermally diffusing n-type impurities (e.g., phosphorus, arsenic, etc.) into the p-type silicon wafer 20. This results in the formation of a p-type silicon wafer 20 having the doped region 250 and a p-type body region 260, which is a region other than the doped region 250. The carrier concentration of the doped region 250 is 1×10 １３ cm －３ 1x10 or more １８ cm －３ is less than 1×10 １４ cm －３ 1x10 or more １６ cm －３ More preferably, it is less than 1000 .mu.m.

[0045] In the fifth step, the p-type silicon wafer 20 is anodized using the p-type silicon wafer 20 as an anode, thereby forming a p-type silicon wafer 20 having a porous portion 23 (see FIGS. 4B and 5 ). In the anodization process, platinum electrodes are placed in an electrolyte solution facing the doped region 250 and the insulating layer 9 on the first main surface 201 of the p-type silicon wafer 20. A current of a predetermined current density is passed between the anode and the cathode for a predetermined time, with the p-type silicon wafer 20 serving as the anode and the platinum electrode serving as the cathode. This anodization process thereby renders a portion of the p-type silicon wafer 20 porous, thereby forming the porous portion 23. The electrolyte is, for example, a mixture of hydrofluoric acid, ethanol, and water. Before the anodization process, an electrode to be used in the anodization process is formed on the second main surface 202 of the p-type silicon wafer 20. This electrode is removed after the anodization process. The electrode is, for example, a metal film.

[0046] In the fifth step, the shape and depth of the pores 24 can be controlled by changing at least one of the hydrogen fluoride concentration in the electrolyte, the predetermined current density, and the predetermined time. The hydrogen fluoride concentration in the electrolyte is, for example, 1 wt % to 80 wt %, and more preferably 1 wt % to 25 wt %. In addition, in the method for manufacturing the capacitor 1, the shape of the pores 24 can also be changed by changing the resistivity of the p-type silicon wafer 20, which is determined by the carrier concentration of the p-type silicon wafer 20.

[0047] In the sixth step, the insulating layer 9 is removed by, for example, wet etching.

[0048] 6A, the dielectric layer 4 is formed. In the seventh step, the first silicon oxide film of the dielectric layer 4 is formed by, for example, CVD, the silicon nitride film of the dielectric layer 4 is formed by, for example, CVD, and the second silicon oxide film of the dielectric layer 4 is formed by, for example, CVD. The first silicon oxide film may be formed by thermal oxidation.

[0049] 6B , in the eighth step, the conductor layer 5 is formed on the dielectric layer 4. More specifically, in the eighth step, a conductor material layer that will become the conductor layer 5 is first formed on the dielectric layer 4. In the eighth step, the conductor material layer is formed by, for example, a CVD method, and then the conductor material layer is patterned using, for example, photolithography and etching techniques to form the conductor layer 5 made of a part of the conductor material layer.

[0050] In the ninth step, the first external connection electrode 6 (see FIG. 1 ) and the second external connection electrode 7 (see FIG. 1 ) are formed. More specifically, in the ninth step, a contact hole 47 (see FIG. 1 ) is first formed in the dielectric layer 4 to expose a portion of the first main surface 21 of the p-type silicon wafer 20. In the ninth step, the contact hole 47 is formed using, for example, photolithography and etching techniques. Thereafter, the first external connection electrode 6 and the second external connection electrode 7 are formed using, for example, a thin-film formation method, photolithography and etching techniques, etc. The thin-film formation method is, for example, a vapor deposition method, a sputtering method, or a CVD method. The ninth step may also include a heat treatment to obtain ohmic contact between the first external connection electrode 6 and the p-type silicon wafer 20.

[0051] In the method for manufacturing the capacitor 1, a p-type silicon wafer 20 is prepared in the first step, and then steps 2 to 9 are performed to obtain a wafer including a plurality of capacitors 1. In the method for manufacturing the capacitor 1, after step 9, the wafer is cut with, for example, a dicing saw or a laser dicing device, thereby obtaining a plurality of capacitors 1.

[0052] (4) Advantages In the capacitor 1 according to the embodiment, the p-type silicon substrate 2 includes a porous portion 23 having a plurality of pores 24. In the porous portion 23, the distance L1 between adjacent pores 24 is non-uniform in the thickness direction D1 of the p-type silicon substrate 2. The p-type silicon substrate 2 has a surface region 25 including a portion of the surface 231 of the porous portion 23 in the thickness direction D1 of the p-type silicon substrate 2, and a body region 26 surrounding the surface region 25. The carrier concentration of the surface region 25 is lower than the carrier concentration of the body region 26. The plurality of pores 24 are formed across the surface region 25 and the body region 26 in the thickness direction D1 of the p-type silicon substrate 2. The first external connection electrode 6 is disposed in the body region 26 of the p-type silicon substrate 2.

[0053] The above configuration makes it possible to increase capacitance while reducing ESR. More specifically, in the capacitor 1 according to the embodiment, the carrier concentration in the surface region 25 is lower than the carrier concentration in the body region 26. This prevents the formation of a surface coating having a plurality of micropores smaller than the plurality of micropores 24 in the body region 26 in the porous portion 23 of the p-type silicon substrate 2 in the surface region 25. This improves the film-forming properties of the dielectric layer 4 and the conductor layer 5 within the plurality of micropores 24, thereby increasing the capacitance of the capacitor 1. The opening width of each of the plurality of micropores 24 is, for example, 1 μm or more and 2 μm or less. The thickness of the surface coating formed in the absence of the surface region 25 is less than 1 μm, and the opening width of each of the plurality of micropores is, for example, 2 nm or more and 10 nm or less. The thickness of the surface coating formed in the absence of the surface region 25 depends on the resistivity of the p-type silicon substrate, and therefore on the carrier concentration of the p-type silicon substrate. Furthermore, in the capacitor 1 according to the embodiment, the carrier concentration in the body region 26 of the p-type silicon substrate 2 is higher than the carrier concentration in the surface region 25, so that the resistivity of the body region 26 can be reduced below the resistivity of the surface region 25, thereby making it possible to reduce the ESR.

[0054] In the capacitor 1, in order to prevent the generation of a surface film having a plurality of micropores smaller than the plurality of pores 24 in the body region 26 in the surface region 25, the carrier concentration in the surface region 25 is set to 1×10 １３ cm －３ 1x10 or more １８ cm －３ It is preferable that it is less than 10 ...

[0055] In addition, in the capacitor 1, from the viewpoint of reducing ESR, the carrier concentration of the surface region 25 is set to 1×10 １３ cm －３ It is preferable that this is equal to or greater than this.

[0056] In addition, in the capacitor 1, from the viewpoint of reducing ESR, the carrier concentration of the body region 26 is set to 1×10 １８ cm －３ It is preferable that this is equal to or greater than this.

[0057] In addition, in the capacitor 1, from the viewpoint of reducing the ESR, it is preferable that the thickness of the surface region 25 is 1 μm or less.

[0058] In the manufacturing method of the capacitor 1 according to the embodiment, a p-type silicon wafer 20 that will become the p-type silicon substrate 2 is prepared, a p-type doped region 250 that will become the surface region 25 is formed by doping the p-type silicon wafer 20 with n-type impurities, a porous portion 23 is formed by anodizing the doped region 250 of the p-type silicon wafer 20 while it is exposed, a dielectric layer 4 is formed on the surface 231 of the porous portion 23 in the p-type silicon wafer 20, a conductor layer 5 is formed on the dielectric layer 4, a first external connection electrode 6 is formed on the p-type silicon wafer 20, and a second external connection electrode 7 is formed on the conductor layer 5.

[0059] According to the above configuration, it is possible to increase the capacitance while reducing the ESR.

[0060] (Modifications) The embodiment is merely one of various embodiments of the present disclosure. The embodiment can be modified in various ways depending on the design, etc., as long as the object of the present disclosure can be achieved.

[0061] For example, a plurality of circuit elements (e.g., MOSFETs) other than the capacitor 1 may be formed on the p-type silicon substrate 2. In other words, the capacitor 1 according to the present disclosure can be applied to a semiconductor device including the capacitor 1, for example, an IC (Integrated Circuit) chip including the capacitor 1.

[0062] (Aspects) Based on the above-described embodiments, the present specification discloses the following aspects.

[0063] A capacitor (1) according to a first aspect includes a p-type silicon substrate (2), a dielectric layer (4), a conductor layer (5), a first external connection electrode (6), and a second external connection electrode (7). The p-type silicon substrate (2) includes a porous portion (23) having a plurality of pores (24). The dielectric layer (4) is disposed on a surface (231) of the porous portion (23) in the p-type silicon substrate (2). The conductor layer (5) is laminated on the dielectric layer (4). The first external connection electrode (6) is connected to the p-type silicon substrate (2). The second external connection electrode (7) is connected to the conductor layer (5). In the porous portion (23), the spacing (L1) between adjacent pores (24) among the plurality of pores (24) is non-uniform in the thickness direction (D1) of the p-type silicon substrate (2). The p-type silicon substrate (2) has a surface region (25) including a portion of the surface (231) of the porous portion (23) in the thickness direction (D1) of the p-type silicon substrate (2), and a body region (26) surrounding the surface region (25). The carrier concentration of the surface region (25) is lower than the carrier concentration of the body region (26). A plurality of pores (24) are formed across the surface region (25) and the body region (26) in the thickness direction (D1) of the p-type silicon substrate (2). A first external connection electrode (6) is disposed in the body region (26) of the p-type silicon substrate (2).

[0064] According to this aspect, it is possible to reduce the ESR while increasing the capacitance.

[0065] In the capacitor (1) according to the second aspect, in the first aspect, the carrier concentration of the surface region (25) is 1×10 １８ cm －３ is less than.

[0066] In the capacitor (1) according to the third aspect, in the second aspect, the carrier concentration of the surface region (25) is 1×10 １３ cm －３ That's all.

[0067] In the capacitor (1) according to the fourth aspect, in any one of the first to third aspects, the carrier concentration of the body region (26) is 1×10 １８ cm －３ That's all.

[0068] In the capacitor (1) according to the fifth aspect, in the fourth aspect, the carrier concentration of the body region (26) is 1×10 １９ cm －３ The following is the result.

[0069] In a capacitor (1) according to a sixth aspect, in any one of the first to fifth aspects, the body region (26) and the surface region (25) each contain boron or indium, and the surface region (25) further contains phosphorus, arsenic, or antimony.

[0070] In the capacitor (1) according to the seventh aspect, in any one of the first to sixth aspects, the thickness of the surface region (25) is 1 μm or less.

[0071] A manufacturing method of a capacitor (1) according to an eighth aspect is a manufacturing method of the capacitor (1) according to any one of aspects 1 to 7. In the manufacturing method of the capacitor (1) according to the eighth aspect, a p-type silicon wafer (20) that will be the basis of a p-type silicon substrate (2) is prepared, a p-type doped region (250) that will be the basis of a surface region (25) is formed in the p-type silicon wafer (20), a porous portion (23) is formed by anodizing the doped region (250) of the p-type silicon wafer (20) while the doped region (250) is exposed, a dielectric layer (4) is formed on the surface (231) of the porous portion (23) in the p-type silicon wafer (20), a conductor layer (5) is formed on the dielectric layer (4), a first external connection electrode (6) is formed on the p-type silicon wafer (20), and a second external connection electrode (7) is formed on the conductor layer (5).

[0072] According to this aspect, it is possible to reduce the ESR while increasing the capacitance.

[0073] REFERENCE SIGNS LIST 1 capacitor 2 p-type silicon substrate 21 first main surface 22 second main surface 23 porous portion 231 surface 24 pores 25 surface region 26 body region 4 dielectric layer 5 conductive layer 6 first external connection electrode 7 second external connection electrode 20 p-type silicon wafer 250 doping region D1 thickness direction L1 spacing

Claims

1. A capacitor comprising a p-type silicon substrate including a porous portion having a plurality of pores, a dielectric layer disposed on a surface of the porous portion in the p-type silicon substrate, a conductor layer laminated on the dielectric layer, a first external connection electrode connected to the p-type silicon substrate, and a second external connection electrode connected to the conductor layer, wherein in the porous portion, a distance between adjacent pores among the plurality of pores is non-uniform in a thickness direction of the p-type silicon substrate, the p-type silicon substrate has a surface region including a part of the surface of the porous portion in the thickness direction of the p-type silicon substrate and a body region surrounding the surface region, a carrier concentration of the surface region is lower than a carrier concentration of the body region, the plurality of pores are formed across the surface region and the body region in the thickness direction of the p-type silicon substrate, and the first external connection electrode is disposed in the body region of the p-type silicon substrate.

2. The carrier concentration of the surface region is less than 1×10 １８ cm －３ The capacitor according to claim 1.

3. The carrier concentration in the surface region is 1×10 １３ cm －３ or more. The capacitor according to claim 2.

4. The carrier concentration in the body region is 1 × 10 １８ cm －３ or more. The capacitor according to claim 1.

5. The carrier concentration in the body region is 1 × 10 １９ cm －３ or less. The capacitor according to claim 4.

6. The capacitor according to claim 1, wherein each of the body region and the surface region contains boron or indium, and the surface region further contains phosphorus, arsenic, or antimony.

7. The capacitor according to claim 1, wherein a thickness of the surface region is 1 μm or less.

8. A method for manufacturing the capacitor according to claim 1, the method comprising: preparing a p-type silicon wafer serving as the p-type silicon substrate; forming a p-type doping region serving as the surface region in the p-type silicon wafer; forming a porous portion by performing an anodization process with the doping region of the p-type silicon wafer exposed; forming a dielectric layer on a surface of the porous portion in the p-type silicon wafer; forming a conductor layer on the dielectric layer; forming a first external connection electrode on the p-type silicon wafer and forming a second external connection electrode on the conductor layer.

Images