Shift register and driving method therefor, and display device

Abstract

A shift register and a driving method therefor, and a display device. The shift register comprises: a node control sub-circuit, configured to provide to a first node a signal of a first power supply end (VGH) or a signal of a second gating clock signal end (CK2), provide to a second node (N2) the signal of the second gating clock signal end (CK2), and provide to a third node the signal of the first power supply end (VGH) or a signal of a first gating clock signal end (CK1); a decoding sub-circuit, configured to provide to the second node (N2) the signal of the second gating clock signal end (CK2) under the control of a signal of at least one gating signal end; and an output control sub-circuit, configured to provide to a first signal output end (OUT1) a signal of a first output clock signal end (CKE1) or a signal of a second power supply end (VGL), and provide to a second signal output end (OUT2) a signal of a second output clock signal end (CKE2) or the signal of the second power supply end (VGL) under the control of the signal of the first node (N1) and the signal of the third node (N3).

Description

Shift register, driving method thereof, and display device Technical Field

[0001] The present disclosure relates to, but is not limited to, the field of display technology, and particularly to a shift register and a driving method thereof, and a display device. Background Art

[0002] Organic Light Emitting Diodes (OLEDs) and Quantum-dot Light Emitting Diodes (QLEDs) are active light-emitting display devices with advantages such as self-luminescence, wide viewing angles, high contrast, low power consumption, extremely fast response times, thinness, flexibility, and low cost. With the continuous advancement of display technology, flexible displays using OLEDs or QLEDs as light-emitting devices and thin-film transistors (TFTs) for signal control have become mainstream products in the display field.

[0003] Summary of the Invention

[0004] The following is an overview of the subject matter described in detail in this disclosure. This overview is not intended to limit the scope of the claims.

[0005] In a first aspect, the present disclosure provides a shift register, comprising: a node control subcircuit, a decoding subcircuit, and an output control subcircuit;

[0006] The node control subcircuit is electrically connected to the first gating clock signal terminal, the second gating clock signal terminal, the first power supply terminal, the second power supply terminal, the first node, the second node, and the third node, respectively, and is configured to provide a signal from the first power supply terminal or the second gating clock signal terminal to the first node, provide a signal from the second gating clock signal terminal to the second node, and provide a signal from the first power supply terminal or the first gating clock signal terminal to the third node under the control of the signals from the first gating clock signal terminal, the second gating clock signal terminal, and the second node;

[0007] The decoding sub-circuit is electrically connected to the at least one gating signal terminal, the second gating clock signal terminal and the second node respectively, and is configured to provide the signal of the second gating clock signal terminal to the second node under the control of the signal of the at least one gating signal terminal;

[0008] The output control subcircuit is electrically connected to the first output clock signal terminal, the second output clock signal terminal, the first signal output terminal, the second signal output terminal, the second power supply terminal, the first node and the third node, respectively, and is configured to provide a signal from the first output clock signal terminal or the second power supply terminal to the first signal output terminal, and provide a signal from the second output clock signal terminal or the second power supply terminal to the second signal output terminal under the control of the signals from the first node and the third node.

[0009] In an exemplary embodiment, the node control subcircuit includes: a first node control subcircuit;

[0010] The first node control subcircuit is electrically connected to the first selection clock signal terminal, the second selection clock signal terminal, the second power supply terminal, the first node, the second node and the third node, respectively, and is configured to provide the signal of the second selection clock signal terminal to the first node under the control of the signals of the first selection clock signal terminal, the second selection clock signal terminal, the second node and the third node, and store the voltage difference between the first node and the second power supply terminal.

[0011] In an exemplary embodiment, the first node control subcircuit includes: a first transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, and a first capacitor;

[0012] The control electrode and the first electrode of the first transistor are electrically connected to the second selection clock signal terminal respectively, and the second electrode of the first transistor is electrically connected to the first node;

[0013] A control electrode of the thirteenth transistor is electrically connected to the second node, a first electrode of the thirteenth transistor is electrically connected to the first node, and a second electrode of the thirteenth transistor is electrically connected to the second electrode of the fourteenth transistor;

[0014] The control electrode of the fourteenth transistor is electrically connected to the first selection clock signal terminal, and the first electrode of the fourteenth transistor is electrically connected to the second selection clock signal terminal;

[0015] A control electrode of the fifteenth transistor is electrically connected to the third node, a first electrode of the fifteenth transistor is electrically connected to the first node, and a second electrode of the fifteenth transistor is electrically connected to the second selection clock signal terminal;

[0016] A first end of the first capacitor is electrically connected to the first node, and a second end of the first capacitor is electrically connected to the second power supply end.

[0017] In an exemplary embodiment, the node control subcircuit includes: a first node control subcircuit;

[0018] The first node control subcircuit is electrically connected to the first selection clock signal terminal, the second selection clock signal terminal, the first power supply terminal, the second power supply terminal, the first node, the second node and the third node, respectively, and is configured to provide the signal of the first power supply terminal or the second selection clock signal terminal to the first node under the control of the signals of the first selection clock signal terminal, the second selection clock signal terminal, the second node and the third node, and store the voltage difference between the first node and the second power supply terminal.

[0019] In an exemplary embodiment, the first node control subcircuit includes: a first transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, and a first capacitor;

[0020] The control electrode of the first transistor is electrically connected to the second selection clock signal terminal, the first electrode of the first transistor is electrically connected to the first power supply terminal, and the second electrode of the first transistor is electrically connected to the first node;

[0021] A control electrode of the thirteenth transistor is electrically connected to the second node, a first electrode of the thirteenth transistor is electrically connected to the first node, and a second electrode of the thirteenth transistor is electrically connected to the second electrode of the fourteenth transistor;

[0022] The control electrode of the fourteenth transistor is electrically connected to the first selection clock signal terminal, and the first electrode of the fourteenth transistor is electrically connected to the second selection clock signal terminal;

[0023] A control electrode of the fifteenth transistor is electrically connected to the third node, a first electrode of the fifteenth transistor is electrically connected to the first node, and a second electrode of the fifteenth transistor is electrically connected to the second selection clock signal terminal;

[0024] A first end of the first capacitor is electrically connected to the first node, and a second end of the first capacitor is electrically connected to the second power supply end.

[0025] In an exemplary embodiment, the node control subcircuit further includes: a second node control subcircuit;

[0026] The second node control subcircuit is electrically connected to the first selection clock signal terminal, the second selection clock signal terminal, the first power supply terminal, the second node and the third node, respectively, and is configured to provide the signal of the second selection clock signal terminal to the second node under the control of the signal of the first selection clock signal terminal, and to provide the signal of the first selection clock signal terminal or the first power supply terminal to the third node under the control of the signal of the first selection clock signal terminal, the second selection clock signal terminal and the second node.

[0027] In an exemplary embodiment, the second node control subcircuit includes: a tenth transistor, an eleventh transistor, a twelfth transistor, and a sixteenth transistor and a second capacitor;

[0028] The control electrode and the first electrode of the tenth transistor are electrically connected to the second selection clock signal terminal respectively, and the second electrode of the tenth transistor is electrically connected to the second node;

[0029] The control electrode of the eleventh transistor is electrically connected to the second node, the first electrode of the eleventh transistor is electrically connected to the first power supply terminal, and the second electrode of the eleventh transistor is electrically connected to the first electrode of the twelfth transistor;

[0030] The control electrode of the twelfth transistor is electrically connected to the first selection clock signal terminal, and the second electrode of the twelfth transistor is electrically connected to the third node;

[0031] A control electrode of the sixteenth transistor is electrically connected to the second selection clock signal terminal, a first electrode of the sixteenth transistor is electrically connected to the first selection clock signal terminal, and a second electrode of the sixteenth transistor is electrically connected to the third node;

[0032] A first end of the second capacitor is electrically connected to the first power supply end, and a second end of the second capacitor is electrically connected to the second node.

[0033] In an exemplary embodiment, the decoding sub-circuit includes: a first selection signal terminal to an eighth selection signal terminal, and the decoding sub-circuit includes: a second transistor to a ninth transistor;

[0034] The control electrode of the second transistor is electrically connected to the first selection signal terminal, the first electrode of the second transistor is electrically connected to the second selection clock signal terminal, and the second electrode of the second transistor is electrically connected to the second node;

[0035] The control electrode of the third transistor is electrically connected to the second selection signal terminal, the first electrode of the third transistor is electrically connected to the second selection clock signal terminal, and the second electrode of the third transistor is electrically connected to the second node;

[0036] The control electrode of the fourth transistor is electrically connected to the third selection signal terminal, the first electrode of the fourth transistor is electrically connected to the second selection clock signal terminal, and the second electrode of the fourth transistor is electrically connected to the second node;

[0037] a control electrode of the fifth transistor electrically connected to the fourth selection signal terminal, a first electrode of the fifth transistor electrically connected to the second selection clock signal terminal, and a second electrode of the fifth transistor electrically connected to the second node;

[0038] a control electrode of the sixth transistor electrically connected to the fifth selection signal terminal, a first electrode of the sixth transistor electrically connected to the second selection clock signal terminal, and a second electrode of the sixth transistor electrically connected to the second node;

[0039] The control electrode of the seventh transistor is electrically connected to the sixth selection signal terminal, the first electrode of the seventh transistor is electrically connected to the second selection clock signal terminal, and the second electrode of the seventh transistor is electrically connected to the second node;

[0040] a control electrode of the eighth transistor electrically connected to the seventh selection signal terminal, a first electrode of the eighth transistor electrically connected to the second selection clock signal terminal, and a second electrode of the eighth transistor electrically connected to the second node;

[0041] The control electrode of the ninth transistor is electrically connected to the eighth selection signal terminal, the first electrode of the ninth transistor is electrically connected to the second selection clock signal terminal, and the second electrode of the ninth transistor is electrically connected to the second node.

[0042] In an exemplary embodiment, the output control subcircuit includes: a seventeenth transistor to a twentieth transistor and a third capacitor and a fourth capacitor;

[0043] A control electrode of the seventeenth transistor is electrically connected to the third node, a first electrode of the seventeenth transistor is electrically connected to the first output clock signal terminal, and a second electrode of the seventeenth transistor is electrically connected to the first signal output terminal;

[0044] The control electrode of the eighteenth transistor is electrically connected to the first node, the first electrode of the eighteenth transistor is electrically connected to the second power supply terminal, and the second electrode of the eighteenth transistor is electrically connected to the first signal output terminal;

[0045] A control electrode of the nineteenth transistor is electrically connected to the third node, a first electrode of the nineteenth transistor is electrically connected to the second clock signal output terminal, and a second electrode of the nineteenth transistor is electrically connected to the second signal output terminal;

[0046] The control electrode of the twentieth transistor is electrically connected to the first node, the first electrode of the twentieth transistor is electrically connected to the second power supply terminal, and the second electrode of the twentieth transistor is electrically connected to the second signal output terminal;

[0047] A first end of the third capacitor is electrically connected to the third node, and a second end of the third capacitor is electrically connected to the first signal output end;

[0048] A first end of the fourth capacitor is electrically connected to the third node, and a second end of the fourth capacitor is electrically connected to the second signal output end.

[0049] In an exemplary embodiment, the present invention further includes: an isolation sub-circuit; the output control sub-circuit is electrically connected to the third node via the isolation sub-circuit;

[0050] The isolation sub-circuit is electrically connected to the first power supply terminal, the third node, the fourth node and the fifth node respectively, and is configured to provide the signal of the third node to the fourth node and the fifth node under the control of the signal of the first power supply terminal;

[0051] The output control subcircuit is also electrically connected to the fourth node and the fifth node, respectively, and is configured to provide the signal of the first output clock signal terminal to the first signal output terminal and the signal of the second output clock signal terminal to the second signal output terminal under the control of the signals of the fourth node and the fifth node, and to provide the signal of the second power supply terminal to the first signal output terminal and the second signal output terminal under the control of the signal of the first node.

[0052] In an exemplary embodiment, the isolation sub-circuit includes: a twenty-second transistor and a twenty-third transistor;

[0053] The control electrode of the twenty-second transistor is electrically connected to the first power supply terminal, the first electrode of the twenty-second transistor is electrically connected to the third node, and the second electrode of the twenty-second transistor is electrically connected to the fifth node;

[0054] The control electrode of the twenty-third transistor is electrically connected to the first power supply terminal, the first electrode of the twenty-third transistor is electrically connected to the third node, and the second electrode of the twenty-third transistor is electrically connected to the fourth node.

[0055] In an exemplary embodiment, the output control subcircuit includes: a seventeenth transistor to a twentieth transistor and a third capacitor and a fourth capacitor;

[0056] A control electrode of the seventeenth transistor is electrically connected to the fourth node, a first electrode of the seventeenth transistor is electrically connected to the first output clock signal terminal, and a second electrode of the seventeenth transistor is electrically connected to the first signal output terminal;

[0057] The control electrode of the eighteenth transistor is electrically connected to the first node, the first electrode of the eighteenth transistor is electrically connected to the second power supply terminal, and the second electrode of the eighteenth transistor is electrically connected to the first signal output terminal;

[0058] A control electrode of the nineteenth transistor is electrically connected to the fifth node, a first electrode of the nineteenth transistor is electrically connected to the second clock signal output terminal, and a second electrode of the nineteenth transistor is electrically connected to the second signal output terminal;

[0059] The control electrode of the twentieth transistor is electrically connected to the first node, the first electrode of the twentieth transistor is electrically connected to the second power supply terminal, and the second electrode of the twentieth transistor is electrically connected to the second signal output terminal;

[0060] A first end of the third capacitor is electrically connected to the fourth node, and a second end of the third capacitor is electrically connected to the first signal output terminal;

[0061] A first end of the fourth capacitor is electrically connected to the fifth node, and a second end of the fourth capacitor is electrically connected to the second signal output end.

[0062] In an exemplary embodiment, the present invention further includes: an isolation sub-circuit; the output control sub-circuit is electrically connected to the third node via the isolation sub-circuit;

[0063] The isolation sub-circuit is electrically connected to the first power supply terminal, the third node and the fourth node respectively, and is configured to provide the signal of the third node to the fourth node under the control of the signal of the first power supply terminal;

[0064] The output control subcircuit is also electrically connected to the fourth node and is configured to provide a signal from the first output clock signal terminal to the first signal output terminal and a signal from the second output clock signal terminal to the second signal output terminal under the control of the signal of the fourth node, and to provide a signal from the second power supply terminal to the first signal output terminal and the second signal output terminal under the control of the signal of the first node.

[0065] In an exemplary embodiment, the isolation sub-circuit includes: a twenty-second transistor;

[0066] The control electrode of the twenty-second transistor is electrically connected to the first power supply terminal, the first electrode of the twenty-second transistor is electrically connected to the third node, and the second electrode of the twenty-second transistor is electrically connected to the fourth node.

[0067] In an exemplary embodiment, the output control subcircuit includes: a seventeenth transistor to a twentieth transistor, a third capacitor, and a fourth capacitor;

[0068] A control electrode of the seventeenth transistor is electrically connected to the fourth node, a first electrode of the seventeenth transistor is electrically connected to the first output clock signal terminal, and a second electrode of the seventeenth transistor is electrically connected to the first signal output terminal;

[0069] The control electrode of the eighteenth transistor is electrically connected to the first node, the first electrode of the eighteenth transistor is electrically connected to the second power supply terminal, and the second electrode of the eighteenth transistor is electrically connected to the first signal output terminal;

[0070] A control electrode of the nineteenth transistor is electrically connected to the fourth node, a first electrode of the nineteenth transistor is electrically connected to the second clock signal output terminal, and a second electrode of the nineteenth transistor is electrically connected to the second signal output terminal;

[0071] The control electrode of the twentieth transistor is electrically connected to the first node, the first electrode of the twentieth transistor is electrically connected to the second power supply terminal, and the second electrode of the twentieth transistor is electrically connected to the second signal output terminal;

[0072] A first end of the third capacitor is electrically connected to the fourth node, and a second end of the third capacitor is electrically connected to the first signal output terminal;

[0073] A first end of the fourth capacitor is electrically connected to the fourth node, and a second end of the fourth capacitor is electrically connected to the second signal output end.

[0074] In an exemplary embodiment, further comprising: a reset subcircuit;

[0075] The reset subcircuit is electrically connected to the reset signal terminal, the third node and the second power terminal respectively, and is configured to provide the signal of the second power terminal to the third node under the control of the signal of the reset signal terminal.

[0076] In an exemplary embodiment, the reset sub-circuit includes: a twenty-first transistor;

[0077] The control electrode of the twenty-first transistor is electrically connected to the reset signal terminal, the first electrode of the twenty-first transistor is electrically connected to the second power supply terminal, and the second electrode of the twenty-first transistor is electrically connected to the third node.

[0078] In a second aspect, the present disclosure further provides a display device having a display area and a non-display area, wherein the display area is provided with sub-pixels arranged in an array, and the non-display area is provided with a gate driving circuit, wherein the gate driving circuit includes: a plurality of the above-mentioned shift registers;

[0079] A first signal output terminal of at least one shift register is electrically connected to at least one row of sub-pixels, and a second signal output terminal of at least one shift register is electrically connected to at least one row of sub-pixels.

[0080] In an exemplary embodiment, the first signal output terminal of the nth shift register is electrically connected to the sub-pixels in the 2n-1th row, and the second signal output terminal of the nth shift register is electrically connected to the sub-pixels in the 2nth row, 1≤n≤N, where N is the total number of shift registers.

[0081] In an exemplary embodiment, the non-display area is further provided with a gate signal line group, which includes: a plurality of gate signal lines, and a plurality of gate signal terminals in at least one shift register are electrically connected to some of the gate signal lines in the gate signal line group.

[0082] In an exemplary embodiment, the shift register includes: M strobe signal terminals, and the strobe signal line group includes: 2M strobe signal lines;

[0083] The mth gate signal terminal is electrically connected to one of the 2m-1th gate signal line and the 2mth gate signal line.

[0084] In an exemplary embodiment, signals of at least two gate signal lines are inverted signals to each other during a partial period.

[0085] In an exemplary embodiment, the non-display area is further provided with a clock signal line group, the clock signal line group including: a plurality of clock signal lines;

[0086] At least one of the first output clock signal terminal, the second output clock signal terminal, the first selection clock signal terminal and the second selection clock signal terminal in at least one shift register is electrically connected to a clock signal line among the plurality of clock signal terminals.

[0087] In an exemplary embodiment, the plurality of clock signal lines include: a first gated clock signal line, a second gated clock signal line, a first output clock signal line, a second output clock signal line, a third output clock signal line, and a fourth output clock signal line;

[0088] The first gated clock signal terminal of at least one shift register is electrically connected to one of the first gated clock signal line and the second gated clock signal line, and the second gated clock signal terminal of at least one shift register is electrically connected to the other of the first gated clock signal line and the second gated clock signal line;

[0089] The first selection clock signal terminals of adjacent shift registers are connected to different signal lines, and the second selection clock signal terminals of adjacent shift registers are connected to different signal lines;

[0090] The first output clock signal terminal of at least one shift register is electrically connected to the first output clock signal line, and the second output clock signal terminal of at least one shift register is electrically connected to the second output clock signal line, or the first output clock signal terminal of at least one shift register is electrically connected to the third output clock signal line, and the second output clock signal terminal of at least one shift register is electrically connected to the fourth output clock signal line;

[0091] The first clock signal output terminals of adjacent shift registers are connected to different signal lines, and the second clock signal output terminals of adjacent shift registers are connected to different signal lines.

[0092] In an exemplary embodiment, a portion of the strobe signal lines to which the plurality of strobe signal terminals of at least one shift register are connected is referred to as a strobe signal line unit;

[0093] The strobe signal line included in the strobe signal line unit connected to the 2n-1th shift register is the same as the strobe signal line included in the strobe signal line unit connected to the 2n-th shift register, and the strobe signal line included in the strobe signal line unit connected to the 2n-1th shift register is different from at least one of the strobe signal lines included in the strobe signal line unit connected to the 2n+1th shift register;

[0094] The first output clock signal terminal of the 2n-1th shift register is electrically connected to the first output clock signal line, and the second output clock signal terminal of the 2n-1th shift register is electrically connected to the second output clock signal line;

[0095] The first output clock signal terminal of the 2nth shift register is electrically connected to the third output clock signal line, and the second output clock signal terminal of the 2nth shift register is electrically connected to the fourth output clock signal line.

[0096] In an exemplary embodiment, when the signal of the first gated clock signal line is a first level signal, the signal of the second gated clock signal line is a second level signal; when the signal of the second gated clock signal line is a first level signal, the signal of the first gated clock signal line is a second level signal;

[0097] The voltage value of the first level signal is greater than the voltage value of the second level signal.

[0098] In an exemplary embodiment, the time periods during which the signals of at least two of the first to fourth output clock signal lines are first level signals do not overlap.

[0099] In an exemplary embodiment, a time period during which a signal of at least one of the first selection clock signal line and the second selection clock signal line is a first level signal does not overlap with a time period during which a signal of at least one of the first to fourth output clock signal lines is a first level signal.

[0100] In an exemplary embodiment, the operating modes of the display device include: a first scanning mode, in which a signal outputted by a first signal output terminal of an nth shift register is earlier than a signal outputted by a second signal output terminal of the nth shift register, and a timing of the signal outputted by the first signal output terminal of the nth shift register does not overlap with a timing of the signal outputted by the second signal output terminal of the nth shift register;

[0101] The signals of the first gate clock signal line, the second gate clock signal line, and the first output clock signal line to the fourth output clock signal line include a plurality of pulse signals;

[0102] In the first scanning mode, the time when the rth pulse signal of the first selection clock signal line occurs is earlier than the time when the rth pulse signal of the second selection clock signal line occurs, the time when the rth pulse signal of the second selection clock signal line occurs is earlier than the time when the r+1th pulse signal of the first selection clock signal line occurs, the time when the rth pulse of the first output clock signal line occurs is earlier than the time when the rth pulse of the second output clock signal line occurs, the time when the rth pulse of the second output clock signal line occurs is earlier than the time when the rth pulse of the third output clock signal line occurs, the time when the rth pulse of the third output clock signal line occurs is earlier than the time when the rth pulse of the fourth output clock signal line occurs, and the first output clock signal line is earlier than the rth pulse of the fourth output clock signal line. The time when the rth pulse of the first selection clock signal line occurs and the time when the rth pulse of the second output clock signal line occurs are between the time when the rth pulse signal of the first selection clock signal line occurs and the time when the rth pulse signal of the second selection clock signal line occurs; the time when the rth pulse of the third output clock signal line occurs and the time when the rth pulse of the fourth output clock signal line occurs are between the time when the rth pulse signal of the second selection clock signal line occurs and the time when the r+1th pulse signal of the first selection clock signal line occurs, 1≤r≤R, R is the number of pulse signals included in the signals of the first selection clock signal line, the second selection clock signal line, and the first output clock signal line to the fourth output clock signal line.

[0103] In an exemplary embodiment, the operating modes of the display device include: a second scanning mode, in which a signal outputted by the first signal output terminal of the nth shift register is later than a signal outputted by the second signal output terminal of the nth shift register, and a timing of the signal outputted by the first signal output terminal of the nth shift register does not overlap with a timing of the signal outputted by the second signal output terminal of the nth shift register;

[0104] The signals of the first gate clock signal line, the second gate clock signal line, and the first output clock signal line to the fourth output clock signal line include a plurality of pulse signals;

[0105] In the second scanning mode, the rth pulse signal of the first selection clock signal line occurs earlier than the rth pulse signal of the second selection clock signal line, the rth pulse signal of the second selection clock signal line occurs earlier than the r+1th pulse signal of the first selection clock signal line, the rth pulse of the fourth output clock signal line occurs earlier than the rth pulse of the third output clock signal line, the rth pulse of the third output clock signal line occurs earlier than the rth pulse of the second output clock signal line, the rth pulse of the second output clock signal line occurs earlier than the rth pulse of the first output clock signal line, and the fourth output clock signal line occurs earlier than the rth pulse of the fourth output clock signal line. The time when the rth pulse of the first selection clock signal line occurs and the time when the rth pulse of the third output clock signal line occurs are between the time when the rth pulse signal of the first selection clock signal line occurs and the time when the rth pulse signal of the second selection clock signal line occurs; the time when the rth pulse of the second output clock signal line occurs and the time when the rth pulse of the first output clock signal line occurs are between the time when the rth pulse signal of the second selection clock signal line occurs and the time when the r+1th pulse signal of the first selection clock signal line occurs, 1≤r≤R, R is the number of pulse signals included in the signals of the first selection clock signal line, the second selection clock signal line, and the first output clock signal line to the fourth output clock signal line.

[0106] In a third aspect, the present disclosure further provides a shift register driving method, which is configured to drive the above-mentioned shift register, the method comprising:

[0107] The node control subcircuit, under the control of the first gated clock signal terminal, the second gated clock signal terminal, and the signal of the second node, provides a signal of the first power supply terminal or the second gated clock signal terminal to the first node, provides a signal of the second gated clock signal terminal to the second node, and provides a signal of the first power supply terminal or the first gated clock signal terminal to the third node;

[0108] The decoding sub-circuit provides a signal from a second gated clock signal terminal to the second node under the control of a signal from at least one gated signal terminal;

[0109] Under the control of the signals of the first node and the third node, the output control subcircuit provides a signal of the first output clock signal terminal or the second power supply terminal to the first signal output terminal, and provides a signal of the second output clock signal terminal or the second power supply terminal to the second signal output terminal.

[0110] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description.

[0111] Summary of the Figures

[0112] The accompanying drawings are used to provide an understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation to the technical solution of the present disclosure.

[0113] FIG1 is a schematic structural diagram of a display device;

[0114] FIG2 is a schematic diagram of a planar structure of a display substrate;

[0115] FIG3 is a second schematic diagram of a planar structure of a display substrate;

[0116] FIG4 is a third schematic diagram of a planar structure of a display substrate;

[0117] FIG5 is a schematic diagram of an equivalent circuit of a pixel driving circuit;

[0118] FIG6 is a schematic diagram of the external compensation principle of the display device;

[0119] FIG7 is a schematic structural diagram of a shift register provided by an embodiment of the present disclosure;

[0120] FIG8 is a schematic diagram of the structure of the node control subcircuit;

[0121] FIG9 is an equivalent circuit diagram 1 of the first node control subcircuit;

[0122] FIG10 is a second equivalent circuit diagram of the first node control sub-circuit;

[0123] FIG11 is an equivalent circuit diagram of the second node control sub-circuit;

[0124] FIG12 is an equivalent circuit diagram of a decoding subcircuit;

[0125] FIG13 is an equivalent circuit diagram of the output control subcircuit;

[0126] FIG14 is a schematic structural diagram of a shift register provided by an exemplary embodiment;

[0127] FIG15 is an equivalent circuit diagram 1 of the isolation sub-circuit and the output control sub-circuit;

[0128] FIG16 is a schematic structural diagram of a shift register provided by another exemplary embodiment;

[0129] FIG17 is a second equivalent circuit diagram of the isolation sub-circuit and the output control sub-circuit;

[0130] FIG18 is a schematic structural diagram of a shift register provided by yet another exemplary embodiment;

[0131] FIG19 is an equivalent circuit diagram of the reset subcircuit;

[0132] FIG20 is an equivalent circuit diagram 1 of a shift register provided in an embodiment of the present disclosure;

[0133] FIG21 is a second equivalent circuit diagram of a shift register provided by an embodiment of the present disclosure;

[0134] FIG22 is a third equivalent circuit diagram of a shift register provided by an embodiment of the present disclosure;

[0135] FIG23 is a fourth equivalent circuit diagram of a shift register provided by an embodiment of the present disclosure;

[0136] FIG24 is a fifth equivalent circuit diagram of a shift register provided by an embodiment of the present disclosure;

[0137] FIG25 is a sixth equivalent circuit diagram of a shift register provided in an embodiment of the present disclosure;

[0138] FIG26 is an operation timing diagram of the shift register provided in FIG20 and FIG23 in the first scanning mode;

[0139] FIG27 is an operation timing diagram of the shift register provided in FIG21 and FIG24 in the first scanning mode;

[0140] FIG28 is an operation timing diagram of the shift register provided in FIG22 and FIG25 in the first scanning mode;

[0141] FIG29 is an operation timing diagram of the shift register provided in FIG20 and FIG23 in the second scanning mode;

[0142] FIG30 is an operation timing diagram of the shift register provided in FIG21 and FIG24 in the second scanning mode;

[0143] FIG31 is an operation timing diagram of the shift register provided in FIG22 and FIG25 in the second scanning mode;

[0144] FIG32 is a schematic structural diagram of a display device;

[0145] FIG33 is a connection diagram of a gate drive circuit;

[0146] FIG34 is a timing diagram of multiple strobe signal lines;

[0147] FIG35 is a timing diagram of multiple clock signal lines of the display device in the first scanning mode;

[0148] FIG36 is a timing diagram of a plurality of clock signal lines of the display device in the second scanning mode.

[0149] Details

[0150] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Note that the embodiments can be implemented in a variety of different forms. A person of ordinary skill in the art can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. Unless there is a conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other. In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits detailed descriptions of some known functions and known components. The drawings of the embodiments of the present disclosure only involve structures related to the embodiments of the present disclosure. Other structures can refer to the general design

[0151] The scales of the figures in this disclosure can be used as a reference for actual processes, but are not limited to such. For example, the width-to-length ratio of the channel, the thickness and spacing of the various film layers, and the width and spacing of the various signal lines can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures. The figures described in this disclosure are merely schematic structural diagrams, and one embodiment of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0152] In this specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0153] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limiting the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the direction in which each constituent element is described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced according to the circumstances.

[0154] In this specification, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the specific meanings of these terms in this disclosure.

[0155] In this specification, a transistor refers to a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0156] In this specification, the first electrode can be a drain electrode and the second electrode can be a source electrode, or vice versa. The functions of "source electrode" and "drain electrode" may be interchanged when using transistors with opposite polarity or when the direction of current changes during circuit operation. Therefore, in this specification, "source electrode" and "drain electrode" may be interchanged.

[0157] In this specification, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables the transfer of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0158] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state where the angle is greater than 85° and less than 95°.

[0159] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film." Similarly, "insulating film" may be replaced with "insulating layer."

[0160] In this specification, the term "same-layer arrangement" refers to a structure formed by patterning two (or more) structures using the same patterning process. The materials of these structures can be the same or different. For example, the precursor materials for forming the multiple structures arranged in the same layer can be the same, and the materials of the final structures can be the same or different.

[0161] The triangles, rectangles, trapezoids, pentagons or hexagons in this specification are not in the strict sense, but may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.

[0162] The term "about" in the present disclosure refers to a numerical value that is not strictly defined and allows for process and measurement errors.

[0163] Figure 1 is a schematic diagram of the structure of a display device. As shown in Figure 1, the OLED display device may include a timing controller, a data signal driver, a scan signal driver, and a pixel array. The pixel array may include multiple scan signal lines (S1 to Sm), multiple data signal lines (D1 to Dn), and multiple sub-pixels Pxij. In an exemplary embodiment, the timing controller may provide grayscale values ​​and control signals suitable for the specifications of the data signal driver to the data signal driver, and may provide clock signals, scan start signals, etc. suitable for the specifications of the scan signal driver to the scan signal driver. The data signal driver may use the grayscale values ​​and control signals received from the timing controller to generate data voltages to be provided to the data signal lines D1, D2, D3, ..., and Dn. For example, the data signal driver may use the clock signal to sample the grayscale values ​​and apply data voltages corresponding to the grayscale values ​​to the data signal lines D1 to Dn in units of sub-pixel rows, where n can be a natural number. The scan signal driver may generate scan signals to be provided to the scan signal lines S1, S2, S3, ..., and Sm by receiving the clock signal, scan start signal, etc. from the timing controller. For example, the scan signal driver may sequentially provide a scan signal having an on-level pulse to the scan signal lines S1 to Sm. For example, the scan signal driver may be configured in the form of a shift register and may generate a scan signal in a manner that sequentially transmits a scan start signal provided in the form of an on-level pulse to a next-stage circuit under the control of a clock signal, and m may be a natural number.

[0164] In an exemplary embodiment, the sub-pixel array may include a plurality of sub-pixels Pxij. Each sub-pixel Pxij may be connected to a corresponding data signal line and a corresponding scan signal line, where i and j may be natural numbers. Sub-pixel Pxij may refer to a sub-pixel in which a transistor is connected to the i-th scan signal line and to the j-th data signal line.

[0165] Figure 2 is a schematic diagram of a planar structure of a display substrate (I), Figure 3 is a schematic diagram of a planar structure of a display substrate (II), and Figure 4 is a schematic diagram of a planar structure of a display substrate (III). As shown in Figures 2 to 4, the display substrate may include a plurality of pixel units P arranged in a matrix. At least one of the plurality of pixel units P includes a first subpixel P1 that emits a first color light, a second subpixel P2 that emits a second color light, and a third subpixel P3 that emits a third color light. The first subpixel P1, the second subpixel P2, and the third subpixel P3 each include a pixel driving circuit and a light-emitting device. The pixel driving circuits in the first subpixel P1, the second subpixel P2, and the third subpixel P3 are respectively connected to a scan signal line, a data signal line, and a light-emitting signal line. The pixel driving circuits are configured to receive a data voltage transmitted by the data signal line under the control of the scan signal line and the light-emitting signal line and output a corresponding current to the light-emitting device. The light-emitting devices in the first subpixel P1, the second subpixel P2, and the third subpixel P3 are respectively connected to the pixel driving circuit of the subpixel in which they are located. The light-emitting devices are configured to emit light of corresponding brightness in response to the current output by the pixel driving circuit of the subpixel in which they are located.

[0166] In an exemplary embodiment, the light emitting device may be an organic light emitting diode (OLED), comprising a first electrode (anode), an organic light emitting layer, and a second electrode (cathode) stacked

[0167] In an exemplary embodiment, the organic light-emitting layer may include an emissive layer (EML) and any one or more of the following layers: a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). In an exemplary embodiment, one or more of the hole injection layer, hole transport layer, electron blocking layer, hole blocking layer, electron transport layer, and electron injection layer of all sub-pixels may be a common layer connected together, and the emissive layers of adjacent sub-pixels may have a small overlap or may be isolated.

[0168] In an exemplary embodiment, the first subpixel P1 may be a red subpixel (R) emitting red light, the second subpixel P2 may be a blue subpixel (B) emitting blue light, and the third subpixel P3 may be a green subpixel (G) emitting green light.

[0169] In an exemplary embodiment, the shape of the sub-pixel may be a rectangle, a diamond, a pentagon, or a hexagon, which is not limited in the present disclosure.

[0170] In an exemplary embodiment, the three sub-pixels may be arranged in parallel horizontally, in parallel vertically, or in a herringbone pattern, which is not limited in the present disclosure.

[0171] In other exemplary embodiments, the pixel unit may include four sub-pixels, and the four sub-pixels may be arranged in parallel horizontally, in parallel vertically, or in a square, etc., which is not limited in the present disclosure.

[0172] In example embodiments, the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure.

[0173] In an exemplary embodiment, the pixel driving circuit in a medium or large-sized display device (eg, a television) is a 3T1C circuit.

[0174] Figure 5 is a schematic diagram of an equivalent circuit of a pixel driving circuit. As shown in Figure 5, the pixel driving circuit has a 3T1C structure and can include three transistors (a switching transistor M1, a driving transistor M2, and a sensing transistor M3), a storage capacitor C, and six signal lines (a data signal line DL, a first scanning signal line GL, a second scanning signal line SL, a sensing signal line Sense, a first power line VDD, and a second power line VSS).

[0175] In an exemplary embodiment, as shown in FIG5 , a gate electrode of the switching transistor M1 is coupled to the first scan signal line GL, a first electrode of the switching transistor M1 is coupled to the data signal line DL, and a second electrode of the switching transistor M1 is coupled to the gate electrode of the driving transistor M2. A gate electrode of the driving transistor M2 is coupled to the second electrode of the switching transistor M1, a first electrode of the driving transistor M2 is coupled to the first power line VDD, and a second electrode of the driving transistor M2 is coupled to the first electrode of the light-emitting device L. A gate electrode of the sensing transistor M3 is coupled to the second scan signal line SL, a first electrode of the sensing transistor M3 is coupled to the sensing signal line Sense, and a second electrode of the sensing transistor M3 is coupled to the first electrode of the light-emitting device L. A first terminal of the storage capacitor C is coupled to the gate electrode of the driving transistor M2, and a second terminal of the storage capacitor C is coupled to the second electrode of the driving transistor M2.

[0176] In an exemplary embodiment, the switching transistor M1 is configured to receive a data signal transmitted by the data signal line DL under the control of a signal from the first scan signal line GL, causing the gate electrode of the driving transistor M2 to receive the data signal. The driving transistor M2 is configured to generate a corresponding drive current under the control of the received data signal. The sensing transistor M3 is configured to extract the threshold voltage Vth and mobility of the driving transistor M2 and the anode voltage of the light-emitting device L in response to a sensing timing, thereby providing external compensation for the pixel driving circuit. The first electrode of the light-emitting device L is coupled to the second electrode of the driving transistor M2, and the second electrode of the light-emitting device L is coupled to the second power line VSS. The light-emitting device L is configured to emit light of a corresponding brightness in response to the drive current from the second electrode of the driving transistor M2.

[0177] In an exemplary embodiment, when the pixel driving circuit turns on the switching transistor M1 through the first scanning signal line GL, the data signal provided by the data signal line DL is stored in the storage capacitor C via the switching transistor M1, thereby controlling the driving transistor M2 to generate a driving current to drive the light-emitting device L to emit light. In addition, the sensing transistor M3 can respond to the sensing timing to extract the threshold voltage Vth and mobility of the driving transistor M2 and the anode voltage of the light-emitting device L. The storage capacitor C is used to maintain the voltage difference between the gate electrode and the second electrode of the driving transistor M2 within a frame of the light-emitting period.

[0178] Transistors can be divided into N-type transistors and P-type transistors according to their characteristics. When the transistor is a P-type transistor, the turn-on voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltages), and the turn-off voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltages). When the transistor is an N-type transistor, the turn-on voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltages), and the turn-off voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltages).

[0179] In an exemplary embodiment, the switch transistor M1, the drive transistor M2, and the sensing transistor M3 may be P-type transistors or N-type transistors. Using the same type of transistors in the pixel drive circuit can simplify the process flow, reduce the manufacturing difficulty of the display panel, and improve the product yield.

[0180] Because the light-emitting device L emits light of corresponding brightness in response to the driving current of the second electrode of the driving transistor M2, the uniformity of the driving transistor M2 determines the display uniformity of the display device. To ensure the display uniformity of the display device, the display device performs external compensation on the pixel driving circuit to eliminate the differences in the driving transistor M2, thereby ensuring the display uniformity of the display device.

[0181] In an exemplary embodiment, characteristics of the driving transistor M2 and the light emitting device L may be evaluated by an external system.

[0182] FIG6 is a schematic diagram of an external compensation principle of a display device. As shown in FIG6 , the display device may further include: a memory 10 , a controller 20 , a digital-to-analog converter 30 , a buffer 40 , an analog-to-digital converter 50 , a reference power supply 60 , a first switch 71 , and a second switch 72 .

[0183] In an exemplary embodiment, the memory 10 may be connected to the analog-to-digital converter 50 and configured to store the compensation signal output from the analog-to-digital converter 50 .

[0184] In an exemplary embodiment, the memory 10 may be an external non-volatile memory.

[0185] In an exemplary embodiment, the controller 20 is electrically connected to the DAC 30 and the memory 10 , respectively, and is configured to obtain the compensation signal stored in the memory 10 , generate a first data signal based on the compensation signal, and send the first data signal to the DAC 30 .

[0186] In an exemplary embodiment, the first data signal is a digital signal.

[0187] In an exemplary embodiment, the digital-to-analog converter 30 is electrically connected to the buffer 40 and is configured to convert the first data signal into a second data signal and transmit the second data signal to the buffer 40 .

[0188] In an exemplary embodiment, the second data signal is an analog signal.

[0189] In an exemplary embodiment, the buffer 40 is electrically connected to the data signal line DL and is configured to transmit the second data signal to the data signal line DL.

[0190] In an exemplary embodiment, the analog-to-digital converter 50 is electrically connected to the sensing signal line Sense through the first switch 71 and is configured to obtain device parameters from the sensing signal line Sense and convert the device parameters into compensation signals when the first switch 71 is turned on.

[0191] In an exemplary embodiment, the device parameters include at least a threshold voltage and mobility of a driving transistor and an anode electrode of a light emitting device.

[0192] In an exemplary embodiment, the device parameter is an analog signal and the compensation signal is a data signal.

[0193] In an exemplary embodiment, the reference power source 60 is electrically connected to the sensing signal line Sense through the second switch 72 and is configured to provide a reference signal to the sensing signal line Sense when the second switch 72 is turned on.

[0194] In an exemplary embodiment, the controller 20 is further configured to obtain a grayscale signal corresponding to the connected pixel driving circuit. When the display device refreshes the data voltage in each pixel driving circuit, the controller corrects the grayscale signal corresponding to each pixel driving circuit according to the compensation signal to generate a first data signal.

[0195] In an exemplary embodiment, as shown in FIG6 , the display device further includes a data storage capacitor C DL , data storage capacitor C DL The first end of the capacitor C is electrically connected to the data signal line DL. DL The second end of the capacitor C is electrically connected to the ground terminal GND.DL The setting can ensure the stability of the signal of the data signal line DL.

[0196] In an exemplary embodiment, as shown in FIG6 , the display device further includes a compensation storage capacitor C SL , compensation storage capacitor C SL The first end of the compensation signal line Sense is electrically connected to the compensation storage capacitor C SL The second end of the compensation storage capacitor C is electrically connected to the ground terminal GND. SL The setting can ensure the stability of the signal of the compensation signal line Sense.

[0197] With the continuous development of display technology, the market has placed higher demands on low-cost, narrow-bezel, and lightweight designs for display devices. In response, Gate Driver on Array (GOA) technology has become a research hotspot for major manufacturers due to its advantages in achieving narrow bezels and lightweight designs.

[0198] GOA technology integrates the gate drive circuit on an array substrate provided with a pixel array, so that the gate drive circuit can directly provide a gate drive signal to the pixel array without the need for an additional gate drive chip and corresponding binding structure, thereby reducing costs and reducing border width.

[0199] High-end monitors have stringent image quality requirements, especially professional gaming monitors, which require extremely high refresh rates. To achieve good compatibility between power consumption and extremely high refresh rates, high-end monitors use regional high-refresh technology (i.e., frequency variation within a display frame, with only the dynamic or fixation areas using a high refresh rate and non-dynamic areas using a low refresh rate). This technology requires the driver circuit to be able to flexibly enable and randomly select. The gate drive circuit has multiple shift registers, and these shift registers are cascaded, so they can only be enabled sequentially from the first to the last shift register. This results in a single display drive capability and an inability to adjust to the image in real time, which cannot meet the display requirements of high-end monitors.

[0200] FIG7 is a schematic diagram of the structure of the shift register provided by an embodiment of the present disclosure. As shown in FIG7 , a shift register provided by an embodiment of the present disclosure may include: a node control subcircuit, a decoding subcircuit, and an output control subcircuit. The node control subcircuit is electrically connected to the first selection clock signal terminal CK1, the second selection clock signal terminal CK2, the first power supply terminal VGH, the second power supply terminal VGL, the first node N1, the second node N2, and the third node N3, respectively, and is configured to provide the first power supply terminal VGH or the second selection clock signal terminal CK2 signal to the first node N1, provide the second selection clock signal terminal CK2 signal to the second node N2, and provide the first power supply terminal VGH or the first selection clock signal terminal CK1 signal to the third node N3 under the control of the first selection clock signal terminal CK1, the second selection clock signal terminal CK2, and the second node N2; the decoding subcircuit is electrically connected to at least one selection signal terminal, the second selection clock signal terminal CK2, and the third node N3. The second node N2 is electrically connected and configured to provide a signal from the second selection clock signal terminal CK2 to the second node N2 under the control of a signal from at least one selection signal terminal. The output control sub-circuit is electrically connected to the first output clock signal terminal CKE1, the second output clock signal terminal CKE2, the first signal output terminal OUT1, the second signal output terminal OUT2, the second power supply terminal VGL, the first node N1, and the third node N3, respectively. The output control sub-circuit is configured to provide a signal from the first output clock signal terminal CKE1 or the second power supply terminal VGL to the first signal output terminal OUT1 and a signal from the second output clock signal terminal CKE2 or the second power supply terminal VGL to the second signal output terminal OUT2 under the control of signals from the first node N1 and the third node N3. FIG7 is illustrative using M selection signal terminals D0 to DM as an example.

[0201] In an exemplary embodiment, the signal of the first power supply terminal VGH is a DC signal and a high-level signal.

[0202] In an exemplary embodiment, the signal of the second power terminal VGL is a DC signal and a low-level signal.

[0203] In an exemplary embodiment, the signal at either the first selection clock signal terminal CK1 or the second selection clock signal terminal CK2 is a square wave signal that repeats a high voltage and a low voltage. For example, the signals at the first selection clock signal terminal CK1 and the second selection clock signal terminal CK2 may have the same period and may be configured as phase-shifted signals. The signals at the first output clock signal terminal CKE1 and the second output clock signal terminal CKE2 may have the same period and may be configured as phase-shifted signals.

[0204] In an exemplary embodiment, the time when the signal of the first gate clock signal terminal CK1 is a high level signal may overlap with the time when the signal of the second gate clock signal terminal CK2 is a low level signal.

[0205] In an exemplary embodiment, the signal at either the first output clock signal terminal CKE1 or the second output clock signal terminal CKE2 is a square wave signal that repeats a high voltage and a low voltage. For example, the signals at the first output clock signal terminal CKE1 and the second output clock signal terminal CKE2 may have the same period and may be configured as phase-shifted signals.

[0206] In an exemplary embodiment, a time period during which the signal of the first output clock signal terminal CKE1 is a high-level signal may overlap with a time period during which the second output clock signal terminal CKE2 is a low-level signal.

[0207] The shift register provided by the disclosed embodiments eliminates the need for cascading multiple shift registers, allowing the shift registers to operate independently and enabling the gate driver circuit to randomly select a subpixel row. This allows the gate driver circuit to partially refresh the display without requiring row-by-row scanning, significantly increasing the refresh rate. For example, when only a portion of the display needs to be refreshed, this portion can be targeted, significantly improving the refresh rate.

[0208] The shift register provided by the embodiment of the present disclosure includes: a node control subcircuit, a decoding subcircuit and an output control subcircuit; the node control subcircuit is electrically connected to the first selection clock signal terminal, the second selection clock signal terminal, the first power supply terminal, the second power supply terminal, the first node, the second node and the third node, and is configured to provide a signal of the first power supply terminal or the second selection clock signal terminal to the first node, a signal of the second selection clock signal terminal to the second node, and a signal of the first power supply terminal or the first selection clock signal terminal to the third node under the control of the signal of the first selection clock signal terminal, the second selection clock signal terminal and the second node; the decoding subcircuit is respectively The present disclosure can flexibly control the shift register through the cooperation of the node control subcircuit, the decoding subcircuit and the output control subcircuit, so that any shift register can be randomly turned on, can be turned on sequentially from the first shift register, and can also be turned on sequentially from the last shift register, thereby improving the driving capability of the display and being able to adjust the partition of the display in real time according to the display image, thereby meeting the display requirements of high-end displays.

[0209] Fig. 8 is a schematic diagram of the structure of the node control subcircuit. As shown in Fig. 8, in an exemplary embodiment, the node control subcircuit includes: a first node control subcircuit and a second node control subcircuit. The first node control sub-circuit may be electrically connected to the first selection clock signal terminal CK1, the second selection clock signal terminal CK2, the second power supply terminal VGL, the first node N1, the second node N2, and the third node N3, respectively, and configured to provide a signal of the second selection clock signal terminal CK2 to the first node N1 under the control of the signals of the first selection clock signal terminal CK1, the second selection clock signal terminal CK2, the second node N2, and the third node N3, and store a voltage difference between the first node N1 and the second power supply terminal VGL. Alternatively, the first node control sub-circuit may be electrically connected to the first selection clock signal terminal CK1, the second selection clock signal terminal CK2, the first power supply terminal VGH, the second power supply terminal VGL, the first node N1, the second node N2, and the third node N3, and configured to provide a signal of the first power supply terminal VGH or the second selection clock signal terminal CK2 to the first node N1 under the control of the signals of the first selection clock signal terminal CK1, the second selection clock signal terminal CK2, the second node N2, and the third node N3, and store a voltage difference between the first node N1 and the second power supply terminal VGL.

[0210] In an exemplary embodiment, FIG9 is an equivalent circuit diagram of a first node control subcircuit. As shown in FIG9 , when the first node control subcircuit is electrically connected to the first selection clock signal terminal CK1, the second selection clock signal terminal CK2, the second power supply terminal VGL, the first node N1, the second node N2, and the third node N3, the first node control subcircuit may include: a first transistor T1, a thirteenth transistor T13, a fourteenth transistor T14, a fifteenth transistor T15, and a first capacitor C1.

[0211] In an exemplary embodiment, as shown in FIG9 , a control electrode and a first electrode of the first transistor T1 are electrically connected to the second selection clock signal terminal CK2, respectively, and the second electrode of the first transistor T1 is electrically connected to the first node N1; a control electrode of the thirteenth transistor T13 is electrically connected to the second node N2, a first electrode of the thirteenth transistor T13 is electrically connected to the first node N1, and a second electrode of the thirteenth transistor T13 is electrically connected to the second electrode of the fourteenth transistor T14; a control electrode of the fourteenth transistor T14 is electrically connected to the first selection clock signal terminal CK1, and a first electrode of the fourteenth transistor T14 is electrically connected to the second selection clock signal terminal CK2; a control electrode of the fifteenth transistor T15 is electrically connected to the third node N3, a first electrode of the fifteenth transistor T15 is electrically connected to the first node N1, and a second electrode of the fifteenth transistor T15 is electrically connected to the second selection clock signal terminal CK2; a first end of the first capacitor C1 is electrically connected to the first node N1, and a second end of the first capacitor C1 is electrically connected to the second power supply terminal VGL.

[0212] FIG10 is a second equivalent circuit diagram of the first node control sub-circuit. In an exemplary embodiment, as shown in FIG10 , the first node control sub-circuit is electrically connected to the first gate clock signal terminal CK1, the second gate clock signal terminal CK2, the first power supply terminal VGH, the second power supply terminal VGL, the first node N1, the second node N2, and the third node N3, and includes a first transistor T1, a thirteenth transistor T13, a fourteenth transistor T14, a fifteenth transistor T15, and a first capacitor C1.

[0213] In an exemplary embodiment, as shown in FIG10 , a control electrode of the first transistor T1 is electrically connected to the second selection clock signal terminal CK2, a first electrode of the first transistor T1 is electrically connected to the first power supply terminal VGH, and a second electrode of the first transistor T1 is electrically connected to the first node N1; a control electrode of the thirteenth transistor T13 is electrically connected to the second node N2, a first electrode of the thirteenth transistor T13 is electrically connected to the first node N1, and a second electrode of the thirteenth transistor T13 is electrically connected to the second electrode of the fourteenth transistor T14; a control electrode of the fourteenth transistor T14 is electrically connected to the first selection clock signal terminal CK1, and a first electrode of the fourteenth transistor T14 is electrically connected to the second selection clock signal terminal CK2; a control electrode of the fifteenth transistor T15 is electrically connected to the third node N3, a first electrode of the fifteenth transistor T15 is electrically connected to the first node N1, and a second electrode of the fifteenth transistor T15 is electrically connected to the second selection clock signal terminal CK2; a first end of the first capacitor C1 is electrically connected to the first node N1, and a second end of the first capacitor C1 is electrically connected to the second power supply terminal VGL.

[0214] In an exemplary embodiment, the control electrode of the first transistor T1 is electrically connected to the second selection clock signal terminal CK2, the first electrode of the first transistor T1 is electrically connected to the first power supply terminal VGH, and the second electrode of the first transistor T1 is electrically connected to the first node N1. This can ensure that the first transistor T1 can be completely turned off, avoid leakage through the first transistor, and improve the reliability of the shift register.

[0215] An exemplary structure of the first node control subcircuit is shown in Figures 9 and 10. Those skilled in the art will readily appreciate that the implementation of the first node control subcircuit is not limited thereto.

[0216] In an exemplary embodiment, as shown in FIG8 , the second node control sub-circuit is electrically connected to the first selection clock signal terminal CK1, the second selection clock signal terminal CK2, the first power supply terminal VGH, the second node N2, and the third node N3, respectively, and is configured to provide the signal of the second selection clock signal terminal CK2 to the second node N2 under the control of the signal of the first selection clock signal terminal CK1, and to provide the signal of the first selection clock signal terminal CK1 or the first power supply terminal VGH to the third node N3 under the control of the signal of the first selection clock signal terminal CK1, the second selection clock signal terminal CK2, and the second node N2.

[0217] Figure 11 is an equivalent circuit diagram of the second node control subcircuit. In an exemplary embodiment, as shown in Figure 11 , the second node control subcircuit may include: a tenth transistor T10, an eleventh transistor T11, a twelfth transistor T12, and a sixteenth transistor T16, and a second capacitor C2.

[0218] In an exemplary embodiment, a control electrode and a first electrode of the tenth transistor T10 are respectively electrically connected to the second selection clock signal terminal CK2, and the second electrode of the tenth transistor T10 is electrically connected to the second node N2; a control electrode of the eleventh transistor T11 is electrically connected to the second node N2, a first electrode of the eleventh transistor T11 is electrically connected to the first power supply terminal VGH, and a second electrode of the eleventh transistor T11 is electrically connected to the first electrode of the twelfth transistor T12; a control electrode of the twelfth transistor T12 is electrically connected to the first selection clock signal terminal CK1, and a second electrode of the twelfth transistor T12 is electrically connected to the third node N3; a control electrode of the sixteenth transistor T16 is electrically connected to the second selection clock signal terminal CK2, a first electrode of the sixteenth transistor T16 is electrically connected to the first selection clock signal terminal CK1, and a second electrode of the sixteenth transistor T16 is electrically connected to the third node N3; a first end of the second capacitor C2 is electrically connected to the first power supply terminal VGH, and a second end of the second capacitor C2 is electrically connected to the second node N2.

[0219] An exemplary structure of the second node control subcircuit is shown in Figure 11. Those skilled in the art will readily appreciate that the implementation of the second node control subcircuit is not limited thereto.

[0220] Figure 12 is an equivalent circuit diagram of the decoding sub-circuit. In an exemplary embodiment, the at least one selection signal terminal may include: a first selection signal terminal D0 to an eighth selection signal terminal D7. As shown in Figure 12, the decoding sub-circuit may include: a second transistor T2 to a ninth transistor T9.

[0221] As shown in FIG12 , the control electrode of the second transistor T2 is electrically connected to the first selection signal terminal D0, the first electrode of the second transistor T2 is electrically connected to the second selection clock signal terminal CK2, and the second electrode of the second transistor T2 is electrically connected to the second node N2; the control electrode of the third transistor T3 is electrically connected to the second selection signal terminal D1, the first electrode of the third transistor T3 is electrically connected to the second selection clock signal terminal CK2, and the second electrode of the third transistor T3 is electrically connected to the second node N2; the control electrode of the fourth transistor T4 is electrically connected to the third selection signal terminal D2, the first electrode of the fourth transistor T4 is electrically connected to the second selection clock signal terminal CK2, and the second electrode of the fourth transistor T4 is electrically connected to the second node N2; the control electrode of the fifth transistor T5 is electrically connected to the fourth selection signal terminal D3, the first electrode of the fifth transistor T5 is electrically connected to the second selection clock signal terminal CK2, and the second electrode of the fifth transistor T5 is electrically connected to the second node N2 The first electrode of the sixth transistor T6 is electrically connected to the fifth selection signal terminal D4, the first electrode of the sixth transistor T6 is electrically connected to the second selection clock signal terminal CK2, and the second electrode of the sixth transistor T6 is electrically connected to the second node N2; the control electrode of the seventh transistor T7 is electrically connected to the sixth selection signal terminal D5, the first electrode of the seventh transistor T7 is electrically connected to the second selection clock signal terminal CK2, and the second electrode of the seventh transistor T7 is electrically connected to the second node N2; the control electrode of the eighth transistor T8 is electrically connected to the seventh selection signal terminal D6, the first electrode of the eighth transistor T8 is electrically connected to the second selection clock signal terminal CK2, and the second electrode of the eighth transistor T8 is electrically connected to the second node N2; the control electrode of the ninth transistor T9 is electrically connected to the eighth selection signal terminal D7, the first electrode of the ninth transistor T9 is electrically connected to the second selection clock signal terminal CK2, and the second electrode of the ninth transistor T9 is electrically connected to the second node N2.

[0222] In an exemplary embodiment, the decoding sub-circuit in the shift register may include multiple strobe signal terminals. FIG12 illustrates an example in which the decoding sub-circuit includes eight strobe signal terminals.

[0223] In an exemplary embodiment, any one of the select signal terminals in the shift register can receive two select signals, and both select signals are inverted signals. Different select signal terminals receive different select signals. Only when all the select signal terminals are at an inactive level is the shift register in the select phase and the shift register outputs normally. When at least one of the select signal terminals is at an active level, the shift register is in the non-select phase, and the first and second signal output terminals of the shift register do not output or maintain a low-level signal. The provision of multiple select signal terminals allows at least some of the shift registers in the gate drive circuit to operate independently, without adjacent shift registers being cascaded. When the decoding subcircuit includes eight transistors, 2^8=256 shift registers can operate independently. A valid level signal at a signal terminal refers to a signal that turns on the transistor connected to the signal terminal, and an inactive level signal at a signal terminal refers to a signal that turns off the transistor connected to the signal terminal.

[0224] Exemplarily, when all transistors in the gating subcircuit are N-type transistors, the shift register is in the gating phase and outputs normally only when the signals at all the gating signal terminals are low-level signals. When the signal at at least one of the gating signal terminals is a high-level signal, the shift register is in the non-gating phase, and the first signal output terminal and the second signal output terminal of the shift register do not output or maintain a low-level signal.

[0225] An exemplary structure of a decoding sub-circuit is shown in Figure 12. Those skilled in the art will readily appreciate that the implementation of the decoding sub-circuit is not limited thereto.

[0226] FIG13 is an equivalent circuit diagram of the output control sub-circuit. In an exemplary embodiment, as shown in FIG13 , the output control sub-circuit includes: a seventeenth transistor T17 to a twentieth transistor T20, a third capacitor C3, and a fourth capacitor C4.

[0227] As shown in FIG13 , the control electrode of the seventeenth transistor T17 is electrically connected to the third node N3, the first electrode of the seventeenth transistor T17 is electrically connected to the first output clock signal terminal CKE1, and the second electrode of the seventeenth transistor T17 is electrically connected to the first signal output terminal OUT1; the control electrode of the eighteenth transistor T18 is electrically connected to the first node N1, the first electrode of the eighteenth transistor T18 is electrically connected to the second power supply terminal VGL, and the second electrode of the eighteenth transistor T18 is electrically connected to the first signal output terminal OUT1; the control electrode of the nineteenth transistor T19 is electrically connected to the third node N3, and the first electrode of the nineteenth transistor T19 is electrically connected to the second output clock signal terminal CKE1. The clock signal terminal CKE2 is electrically connected, the second electrode of the nineteenth transistor T19 is electrically connected to the second signal output terminal OUT2; the control electrode of the twentieth transistor T20 is electrically connected to the first node N1, the first electrode of the twentieth transistor T20 is electrically connected to the second power supply terminal VGL, and the second electrode of the twentieth transistor T20 is electrically connected to the second signal output terminal OUT2; the first end of the third capacitor C3 is electrically connected to the third node N3, and the second end of the third capacitor C3 is electrically connected to the first signal output terminal OUT1; the first end of the fourth capacitor C4 is electrically connected to the third node N3, and the second end of the fourth capacitor C4 is electrically connected to the second signal output terminal OUT2.

[0228] In an exemplary embodiment, the capacitance value of the third capacitor C3 is substantially the same as the capacitance value of the fourth node C4, so that the influence of the third capacitor C3 on the third node N3 and the influence of the fourth capacitor C4 on the third node N3 are substantially the same, thereby ensuring the stability of the signal of the third node N3.

[0229] The output control subcircuit provided in FIG13 can adjust the falling edge of the output signal of the shift register through the third capacitor and the fourth capacitor, thereby ensuring the stability of the output signal of the shift register and achieving a better driving effect.

[0230] In an exemplary embodiment, FIG14 is a schematic diagram of the structure of a shift register provided by an exemplary embodiment. As shown in FIG14 , the shift register may further include an isolation subcircuit. The output control subcircuit is electrically connected to the third node N3 via the isolation subcircuit.

[0231] As shown in FIG14 , the isolation sub-circuit is electrically connected to the first power supply terminal VGH, the third node N3, the fourth node N4, and the fifth node N5, respectively, and is configured to provide a signal from the third node N3 to the fourth node N4 and the fifth node N5 under the control of a signal from the first power supply terminal VGH. The output control sub-circuit is also electrically connected to the fourth node N4 and the fifth node N5, respectively, and is configured to provide a signal from the first output clock signal terminal CKE1 to the first signal output terminal OUT1 and a signal from the second output clock signal terminal CKE2 to the second signal output terminal OUT2 under the control of a signal from the fourth node N4 and the fifth node N5. Furthermore, the output control sub-circuit is electrically connected to the fourth node N4 and the fifth node N5, respectively, and is configured to provide a signal from the first output clock signal terminal CKE1 to the first signal output terminal OUT1 and a signal from the second output clock signal terminal CKE2 to the second signal output terminal OUT2 under the control of a signal from the first node N1. Furthermore, the output control sub-circuit is electrically connected to the fourth node N4 and the fifth node N5, respectively, and is configured to provide a signal from the second power supply terminal VGL to the first signal output terminal OUT1 and the second signal output terminal OUT2 under the control of a signal from the first node N1.

[0232] 15 is an equivalent circuit diagram of the isolation sub-circuit and the output control sub-circuit 1. In an exemplary embodiment, as shown in FIG15 , the isolation sub-circuit may include: a twenty-second transistor T22 and a twenty-third transistor T23.

[0233] As shown in Figure 15, the control electrode of the twenty-second transistor T22 is electrically connected to the first power supply terminal VGH, the first electrode of the twenty-second transistor T22 is electrically connected to the third node N3, and the second electrode of the twenty-second transistor T22 is electrically connected to the fifth node N5; the control electrode of the twenty-third transistor T23 is electrically connected to the first power supply terminal VGH, the first electrode of the twenty-third transistor T23 is electrically connected to the third node N3, and the second electrode of the twenty-third transistor T23 is electrically connected to the fourth node N4.

[0234] In an exemplary embodiment, the twenty-second transistor T22 can function to isolate the third node N3 from the fifth node N5, and the twenty-third transistor T23 can function to isolate the third node N3 from the fourth node N4. The configuration of the twenty-second transistor T22 and the twenty-third transistor T23 can ensure the stability of the signal of the third node N3.

[0235] In an exemplary embodiment, as shown in FIG. 15 , the output control sub-circuit may include: seventeenth to twentieth transistors T17 to T20 , and a third capacitor C3 and a fourth capacitor C4 .

[0236] As shown in FIG15 , the control electrode of the seventeenth transistor T17 is electrically connected to the fourth node N4, the first electrode of the seventeenth transistor T17 is electrically connected to the first output clock signal terminal CKE1, and the second electrode of the seventeenth transistor T17 is electrically connected to the first signal output terminal OUT1; the control electrode of the eighteenth transistor T18 is electrically connected to the first node N1, the first electrode of the eighteenth transistor T18 is electrically connected to the second power supply terminal VGL, and the second electrode of the eighteenth transistor T18 is electrically connected to the first signal output terminal OUT1; the control electrode of the nineteenth transistor T19 is electrically connected to the fifth node N5, and the first electrode of the nineteenth transistor T19 is electrically connected to the second output clock signal terminal CKE1. The clock signal terminal CKE2 is electrically connected, the second electrode of the nineteenth transistor T19 is electrically connected to the second signal output terminal OUT2; the control electrode of the twentieth transistor T20 is electrically connected to the first node N1, the first electrode of the twentieth transistor T20 is electrically connected to the second power supply terminal VGL, and the second electrode of the twentieth transistor T20 is electrically connected to the second signal output terminal OUT2; the first end of the third capacitor C3 is electrically connected to the fourth node N4, and the second end of the third capacitor C3 is electrically connected to the first signal output terminal OUT1; the first end of the fourth capacitor C4 is electrically connected to the fifth node N5, and the second end of the fourth capacitor C4 is electrically connected to the second signal output terminal OUT2.

[0237] FIG16 is a schematic diagram of the structure of a shift register provided by another exemplary embodiment. As shown in FIG16 , the shift register may further include an isolation subcircuit. The output control subcircuit may be electrically connected to the third node N3 via the isolation subcircuit.

[0238] As shown in Figure 16, the isolation sub-circuit is electrically connected to the first power supply terminal VGH, the third node N3 and the fourth node N4, respectively, and is configured to provide the signal of the third node N3 to the fourth node N4 under the control of the signal of the first power supply terminal VGH; the output control sub-circuit is also electrically connected to the fourth node N4, and is configured to provide the signal of the first output clock signal terminal CKE1 to the first signal output terminal OUT1 and the signal of the second output clock signal terminal CKE2 to the second signal output terminal OUT2 under the control of the signal of the fourth node N4, and provide the signal of the second power supply terminal VGL to the first signal output terminal OUT1 and the second signal output terminal OUT2 under the control of the signal of the first node N1.

[0239] Fig. 17 is a second equivalent circuit diagram of the isolation sub-circuit and the output control sub-circuit. In an exemplary embodiment, as shown in Fig. 17 , the isolation sub-circuit may include: a twenty-second transistor T22.

[0240] As shown in FIG17 , the control electrode of the 22nd transistor T22 is electrically connected to the first power supply terminal VGH, the first electrode of the 22nd transistor T22 is electrically connected to the third node N3 , and the second electrode of the 22nd transistor T22 is electrically connected to the fourth node N4 .

[0241] In an exemplary embodiment, the twenty-second transistor T22 can function to isolate the third node N3 from the fourth node N4, thereby ensuring the stability of the signal at the third node N3. In an exemplary embodiment, as shown in FIG17 , the output control subcircuit includes seventeenth to twentieth transistors T17 to T20, a third capacitor C3, and a fourth capacitor C4.

[0242] As shown in FIG17 , the control electrode of the seventeenth transistor T17 is electrically connected to the fourth node N4, the first electrode of the seventeenth transistor T17 is electrically connected to the first output clock signal terminal CKE1, and the second electrode of the seventeenth transistor T17 is electrically connected to the first signal output terminal OUT1; the control electrode of the eighteenth transistor T18 is electrically connected to the first node N1, the first electrode of the eighteenth transistor T18 is electrically connected to the second power supply terminal VGL, and the second electrode of the eighteenth transistor T18 is electrically connected to the first signal output terminal OUT1; the control electrode of the nineteenth transistor T19 is electrically connected to the fourth node N4, and the first electrode of the nineteenth transistor T19 is electrically connected to the second output clock signal terminal CKE1. The clock signal terminal CKE2 is electrically connected, the second electrode of the nineteenth transistor T19 is electrically connected to the second signal output terminal OUT2; the control electrode of the twentieth transistor T20 is electrically connected to the first node N1, the first electrode of the twentieth transistor T20 is electrically connected to the second power supply terminal VGL, and the second electrode of the twentieth transistor T20 is electrically connected to the second signal output terminal OUT2; the first end of the third capacitor C3 is electrically connected to the fourth node N4, and the second end of the third capacitor C3 is electrically connected to the first signal output terminal OUT1; the first end of the fourth capacitor C4 is electrically connected to the fourth node N4, and the second end of the fourth capacitor C4 is electrically connected to the second signal output terminal OUT2.

[0243] Three exemplary structures of the output control sub-circuit are shown in Figures 13, 15 and 17. Those skilled in the art will readily appreciate that the implementation of the output control sub-circuit is not limited thereto.

[0244] Two exemplary structures of the isolation sub-circuit are shown in Figures 15 and 17. Those skilled in the art will readily appreciate that the implementation of the isolation sub-circuit is not limited thereto.

[0245] In an exemplary embodiment, the setting of the isolation sub-circuit can ensure the stability of the signal of the third node, prevent the third node from being affected by the coupling effect of the third capacitor and the fourth capacitor, improve the output stability of the shift register, and improve the reliability of the shift register.

[0246] In an exemplary embodiment, the shift register may include multiple signal output terminals, each of which may be connected to at least one row of sub-pixels. The shift registers provided in Figures 13, 15, and 17 include two signal output terminals. When each signal output terminal is connected to a row of sub-pixels, the shift register may be connected to two rows of sub-pixels.

[0247] In an exemplary embodiment, Figure 18 is a schematic structural diagram of a shift register provided by another exemplary embodiment. As shown in Figure 18 , the shift register may further include a reset subcircuit.

[0248] As shown in Figure 18, the reset sub-circuit can be electrically connected to the reset signal terminal TRS, the third node N3 and the second power terminal VGL respectively, and is configured to provide the signal of the second power terminal VGL to the third node N3 under the control of the signal of the reset signal terminal TRS.

[0249] FIG19 is an equivalent circuit diagram of a reset sub-circuit. In an exemplary embodiment, as shown in FIG19 , the reset sub-circuit may include: a twenty-first transistor T21.

[0250] As shown in FIG19 , a control electrode of the 21st transistor T21 is electrically connected to the reset signal terminal TRS, a first electrode of the 21st transistor T21 is electrically connected to the second power supply terminal VGL, and a second electrode of the 21st transistor T21 is electrically connected to the third node N3 .

[0251] An exemplary structure of the reset sub-circuit is shown in Figure 19. Those skilled in the art will readily appreciate that the implementation of the reset sub-circuit is not limited thereto.

[0252] FIG20 is an equivalent circuit diagram 1 of the shift register provided by an embodiment of the present disclosure. As shown in FIG20 , in an exemplary embodiment, the shift register includes: a first transistor T1 to a twenty-first transistor T21 and a first capacitor C1 to a fourth capacitor C4. The control electrode and the first electrode of the first transistor T1 are electrically connected to the second selection clock signal terminal CK2, respectively, and the second electrode of the first transistor T1 is electrically connected to the first node N1; the control electrode of the second transistor T2 is electrically connected to the first selection signal terminal D0, the first electrode of the second transistor T2 is electrically connected to the second selection clock signal terminal CK2, and the second electrode of the second transistor T2 is electrically connected to the second node N2; the control electrode of the third transistor T3 is electrically connected to the second selection signal terminal D1, the first electrode of the third transistor T3 is electrically connected to the second selection clock signal terminal CK2, and the second electrode of the third transistor T3 is electrically connected to the second node N2; the fourth transistor T3 is electrically connected to the second selection signal terminal D1, the first electrode of the third transistor T3 is electrically connected to the second selection clock signal terminal CK2, and the second electrode of the third transistor T3 is electrically connected to the second node N2; the fourth transistor T3 is electrically connected to the second selection signal terminal D1, the first electrode of the third transistor T3 is electrically connected to the second selection clock signal terminal CK2, and the second electrode of the third transistor T3 is electrically connected to the second node N2. The control electrode of the transistor T4 is electrically connected to the third selection signal terminal D2, the first electrode of the fourth transistor T4 is electrically connected to the second selection clock signal terminal CK2, and the second electrode of the fourth transistor T4 is electrically connected to the second node N2; the control electrode of the fifth transistor T5 is electrically connected to the fourth selection signal terminal D3, the first electrode of the fifth transistor T5 is electrically connected to the second selection clock signal terminal CK2, and the second electrode of the fifth transistor T5 is electrically connected to the second node N2; the control electrode of the sixth transistor T6 is electrically connected to the fifth selection signal terminal D4, the first electrode of the sixth transistor T6 is electrically connected to the second selection clock signal terminal CK2, and the second electrode of the sixth transistor T6 is electrically connected to the second selection clock signal terminal CK2. The control electrode of the seventh transistor T7 is electrically connected to the sixth selection signal terminal D5, the first electrode of the seventh transistor T7 is electrically connected to the second selection clock signal terminal CK2, and the second electrode of the seventh transistor T7 is electrically connected to the second node N2; the control electrode of the eighth transistor T8 is electrically connected to the seventh selection signal terminal D6, the first electrode of the eighth transistor T8 is electrically connected to the second selection clock signal terminal CK2, and the second electrode of the eighth transistor T8 is electrically connected to the second node N2; the control electrode of the ninth transistor T9 is electrically connected to the eighth selection signal terminal D7, the first electrode of the ninth transistor T9 is electrically connected to the second selection clock signal terminal CK2, and the ninth transistor T9 is electrically connected to the second node N2. The second electrode of the transistor T9 is electrically connected to the second node N2; the control electrode and the first electrode of the tenth transistor T10 are respectively electrically connected to the second selection clock signal terminal CK2, and the second electrode of the tenth transistor T10 is electrically connected to the second node N2; the control electrode of the eleventh transistor T11 is electrically connected to the second node N2, the first electrode of the eleventh transistor T11 is electrically connected to the first power supply terminal VGH, and the second electrode of the eleventh transistor T11 is electrically connected to the first electrode of the twelfth transistor T12; the control electrode of the twelfth transistor T12 is electrically connected to the first selection clock signal terminal CK1, and the second electrode of the twelfth transistor T12 is electrically connected to the third node N3;A control electrode of the thirteenth transistor T13 is electrically connected to the second node N2, a first electrode of the thirteenth transistor T13 is electrically connected to the first node N1, and a second electrode of the thirteenth transistor T13 is electrically connected to the second electrode of the fourteenth transistor T14; a control electrode of the fourteenth transistor T14 is electrically connected to the first selection clock signal terminal CK1, and a first electrode of the fourteenth transistor T14 is electrically connected to the second selection clock signal terminal CK2; a control electrode of the fifteenth transistor T15 is electrically connected to the third node N3, a first electrode of the fifteenth transistor T15 is electrically connected to the first node N1, and a second electrode of the fifteenth transistor T15 is electrically connected to the second selection clock signal terminal CK2; A control electrode of the sixteenth transistor T16 is electrically connected to the second selection clock signal terminal CK2, a first electrode of the sixteenth transistor T16 is electrically connected to the first selection clock signal terminal CK1, and a second electrode of the sixteenth transistor T16 is electrically connected to the third node N3; a control electrode of the seventeenth transistor T17 is electrically connected to the third node N3, a first electrode of the seventeenth transistor T17 is electrically connected to the first output clock signal terminal CKE1, and a second electrode of the seventeenth transistor T17 is electrically connected to the first signal output terminal OUT1; a control electrode of the eighteenth transistor T18 is electrically connected to the first node N1, and a first electrode of the eighteenth transistor T18 is electrically connected to the second power supply terminal VGL. The second electrode of the eighteenth transistor T18 is electrically connected to the first signal output terminal OUT1; the control electrode of the nineteenth transistor T19 is electrically connected to the third node N3, the first electrode of the nineteenth transistor T19 is electrically connected to the second output clock signal terminal CKE2, and the second electrode of the nineteenth transistor T19 is electrically connected to the second signal output terminal OUT2; the control electrode of the twentieth transistor T20 is electrically connected to the first node N1, the first electrode of the twentieth transistor T20 is electrically connected to the second power supply terminal VGL, and the second electrode of the twentieth transistor T20 is electrically connected to the second signal output terminal OUT2; the control electrode of the twenty-first transistor T21 is electrically connected to the reset signal terminal TRS, and the twenty-first transistor T22 is electrically connected to the reset signal terminal TRS. A first electrode of transistor T21 is electrically connected to the second power supply terminal VGL, and a second electrode of the twenty-first transistor T21 is electrically connected to the third node N3. A first end of the first capacitor C1 is electrically connected to the first node N1, and a second end of the first capacitor C1 is electrically connected to the second power supply terminal VGL. A first end of the second capacitor C2 is electrically connected to the first power supply terminal VGH, and a second end of the second capacitor C2 is electrically connected to the second node N2. A first end of the third capacitor C3 is electrically connected to the third node N3, and a second end of the third capacitor C3 is electrically connected to the first signal output terminal OUT1. A first end of the fourth capacitor C4 is electrically connected to the third node N3, and a second end of the fourth capacitor C4 is electrically connected to the second signal output terminal OUT2.

[0253] FIG21 is a second equivalent circuit diagram of the shift register provided by an embodiment of the present disclosure. As shown in FIG21 , in an exemplary embodiment, the shift register includes: a first transistor T1 to a twenty-second transistor T22 and a first capacitor C1 to a fourth capacitor C4. The control electrode and the first electrode of the first transistor T1 are electrically connected to the second selection clock signal terminal CK2, respectively, and the second electrode of the first transistor T1 is electrically connected to the first node N1; the control electrode of the second transistor T2 is electrically connected to the first selection signal terminal D0, the first electrode of the second transistor T2 is electrically connected to the second selection clock signal terminal CK2, and the second electrode of the second transistor T2 is electrically connected to the second node N2; the control electrode of the third transistor T3 is electrically connected to the second selection signal terminal D1, the first electrode of the third transistor T3 is electrically connected to the second selection clock signal terminal CK2, and the second electrode of the third transistor T3 is electrically connected to the second node N2; the fourth transistor T3 is electrically connected to the second selection signal terminal D1, the first electrode of the third transistor T3 is electrically connected to the second selection clock signal terminal CK2, and the second electrode of the third transistor T3 is electrically connected to the second node N2; the fourth transistor T3 is electrically connected to the second selection signal terminal D1, the first electrode of the third transistor T3 is electrically connected to the second selection clock signal terminal CK2, and the second electrode of the third transistor T3 is electrically connected to the second node N2. The control electrode of the transistor T4 is electrically connected to the third selection signal terminal D2, the first electrode of the fourth transistor T4 is electrically connected to the second selection clock signal terminal CK2, and the second electrode of the fourth transistor T4 is electrically connected to the second node N2; the control electrode of the fifth transistor T5 is electrically connected to the fourth selection signal terminal D3, the first electrode of the fifth transistor T5 is electrically connected to the second selection clock signal terminal CK2, and the second electrode of the fifth transistor T5 is electrically connected to the second node N2; the control electrode of the sixth transistor T6 is electrically connected to the fifth selection signal terminal D4, the first electrode of the sixth transistor T6 is electrically connected to the second selection clock signal terminal CK2, and the second electrode of the sixth transistor T6 is electrically connected to the second selection clock signal terminal CK2. The control electrode of the seventh transistor T7 is electrically connected to the sixth selection signal terminal D5, the first electrode of the seventh transistor T7 is electrically connected to the second selection clock signal terminal CK2, and the second electrode of the seventh transistor T7 is electrically connected to the second node N2; the control electrode of the eighth transistor T8 is electrically connected to the seventh selection signal terminal D6, the first electrode of the eighth transistor T8 is electrically connected to the second selection clock signal terminal CK2, and the second electrode of the eighth transistor T8 is electrically connected to the second node N2; the control electrode of the ninth transistor T9 is electrically connected to the eighth selection signal terminal D7, the first electrode of the ninth transistor T9 is electrically connected to the second selection clock signal terminal CK2, and the ninth transistor T9 is electrically connected to the second node N2. The second electrode of the transistor T9 is electrically connected to the second node N2; the control electrode and the first electrode of the tenth transistor T10 are respectively electrically connected to the second selection clock signal terminal CK2, and the second electrode of the tenth transistor T10 is electrically connected to the second node N2; the control electrode of the eleventh transistor T11 is electrically connected to the second node N2, the first electrode of the eleventh transistor T11 is electrically connected to the first power supply terminal VGH, and the second electrode of the eleventh transistor T11 is electrically connected to the first electrode of the twelfth transistor T12; the control electrode of the twelfth transistor T12 is electrically connected to the first selection clock signal terminal CK1, and the second electrode of the twelfth transistor T12 is electrically connected to the third node N3;A control electrode of the thirteenth transistor T13 is electrically connected to the second node N2, a first electrode of the thirteenth transistor T13 is electrically connected to the first node N1, and a second electrode of the thirteenth transistor T13 is electrically connected to the second electrode of the fourteenth transistor T14; a control electrode of the fourteenth transistor T14 is electrically connected to the first selection clock signal terminal CK1, and a first electrode of the fourteenth transistor T14 is electrically connected to the second selection clock signal terminal CK2; a control electrode of the fifteenth transistor T15 is electrically connected to the third node N3, a first electrode of the fifteenth transistor T15 is electrically connected to the first node N1, and a second electrode of the fifteenth transistor T15 is electrically connected to the second selection clock signal terminal CK2; a control electrode of the sixteenth transistor T16 is electrically connected to the second selection clock signal terminal CK2, a first electrode of the sixteenth transistor T16 is electrically connected to the first selection clock signal terminal CK1, and a second electrode of the sixteenth transistor T16 is electrically connected to the third node N3; a control electrode of the seventeenth transistor T17 is electrically connected to the fourth node N4, and a first electrode of the seventeenth transistor T17 is electrically connected to the first output clock signal terminal CKE1 The first electrode of the 17th transistor T17 is electrically connected to the first signal output terminal OUT1; the control electrode of the 18th transistor T18 is electrically connected to the first node N1, the first electrode of the 18th transistor T18 is electrically connected to the second power supply terminal VGL, and the second electrode of the 18th transistor T18 is electrically connected to the first signal output terminal OUT1; the control electrode of the 19th transistor T19 is electrically connected to the fourth node N4, the first electrode of the 19th transistor T19 is electrically connected to the second output clock signal terminal CKE2, and the second electrode of the 19th transistor T19 is electrically connected to the second signal output terminal OUT2; the control electrode of the 20th transistor T20 is electrically connected to the first node N1, the first electrode of the 20th transistor T20 is electrically connected to the second power supply terminal VGL, and the second electrode of the 20th transistor T20 is electrically connected to the second signal output terminal OUT2; the control electrode of the 21st transistor T21 is electrically connected to the reset signal terminal TRS, and the 21st transistor T21 is electrically connected to the reset signal terminal TRS. A first electrode of the transistor T21 is electrically connected to the second power supply terminal VGL, and a second electrode of the twenty-first transistor T21 is electrically connected to the third node N3; a control electrode of the twenty-second transistor T22 is electrically connected to the first power supply terminal VGH, a first electrode of the twenty-second transistor T22 is electrically connected to the third node N3, and a second electrode of the twenty-second transistor T22 is electrically connected to the fourth node N4; a first end of the first capacitor C1 is electrically connected to the first node N1, and a second end of the first capacitor C1 is electrically connected to the second power supply terminal VGL; a first end of the second capacitor C2 is electrically connected to the first power supply terminal VGH, and a second end of the second capacitor C2 is electrically connected to the second node N2; a first end of the third capacitor C3 is electrically connected to the fourth node N4, and a second end of the third capacitor C3 is electrically connected to the first signal output terminal OUT1; a first end of the fourth capacitor C4 is electrically connected to the fourth node N4, and a second end of the fourth capacitor C4 is electrically connected to the second signal output terminal OUT2.

[0254] Figure 22 is the third equivalent circuit diagram of the shift register provided by the embodiment of the present disclosure. As shown in Figure 22, in an exemplary embodiment, the shift register includes: a first transistor T1 to a twenty-third transistor T23 and a first capacitor C1 to a fourth capacitor C4. The control electrode and the first electrode of the first transistor T1 are electrically connected to the second selection clock signal terminal CK2, respectively, and the second electrode of the first transistor T1 is electrically connected to the first node N1; the control electrode of the second transistor T2 is electrically connected to the first selection signal terminal D0, the first electrode of the second transistor T2 is electrically connected to the second selection clock signal terminal CK2, and the second electrode of the second transistor T2 is electrically connected to the second node N2; the control electrode of the third transistor T3 is electrically connected to the second selection signal terminal D1, the first electrode of the third transistor T3 is electrically connected to the second selection clock signal terminal CK2, and the second electrode of the third transistor T3 is electrically connected to the second node N2; the fourth transistor T3 is electrically connected to the second selection signal terminal D1, the first electrode of the third transistor T3 is electrically connected to the second selection clock signal terminal CK2, and the second electrode of the third transistor T3 is electrically connected to the second node N2; The control electrode of the transistor T4 is electrically connected to the third selection signal terminal D2, the first electrode of the fourth transistor T4 is electrically connected to the second selection clock signal terminal CK2, and the second electrode of the fourth transistor T4 is electrically connected to the second node N2; the control electrode of the fifth transistor T5 is electrically connected to the fourth selection signal terminal D3, the first electrode of the fifth transistor T5 is electrically connected to the second selection clock signal terminal CK2, and the second electrode of the fifth transistor T5 is electrically connected to the second node N2; the control electrode of the sixth transistor T6 is electrically connected to the fifth selection signal terminal D4, the first electrode of the sixth transistor T6 is electrically connected to the second selection clock signal terminal CK2, and the second electrode of the sixth transistor T6 is electrically connected to the second selection clock signal terminal CK2. The control electrode of the seventh transistor T7 is electrically connected to the sixth selection signal terminal D5, the first electrode of the seventh transistor T7 is electrically connected to the second selection clock signal terminal CK2, and the second electrode of the seventh transistor T7 is electrically connected to the second node N2; the control electrode of the eighth transistor T8 is electrically connected to the seventh selection signal terminal D6, the first electrode of the eighth transistor T8 is electrically connected to the second selection clock signal terminal CK2, and the second electrode of the eighth transistor T8 is electrically connected to the second node N2; the control electrode of the ninth transistor T9 is electrically connected to the eighth selection signal terminal D7, the first electrode of the ninth transistor T9 is electrically connected to the second selection clock signal terminal CK2, and the ninth transistor T9 is electrically connected to the second node N2. The second electrode of the transistor T9 is electrically connected to the second node N2; the control electrode and the first electrode of the tenth transistor T10 are respectively electrically connected to the second selection clock signal terminal CK2, and the second electrode of the tenth transistor T10 is electrically connected to the second node N2; the control electrode of the eleventh transistor T11 is electrically connected to the second node N2, the first electrode of the eleventh transistor T11 is electrically connected to the first power supply terminal VGH, and the second electrode of the eleventh transistor T11 is electrically connected to the first electrode of the twelfth transistor T12; the control electrode of the twelfth transistor T12 is electrically connected to the first selection clock signal terminal CK1, and the second electrode of the twelfth transistor T12 is electrically connected to the third node N3;The control electrode of the thirteenth transistor T13 is electrically connected to the second node N2, the first electrode of the thirteenth transistor T13 is electrically connected to the first node N1, and the second electrode of the thirteenth transistor T13 is electrically connected to the second electrode of the fourteenth transistor T14; the control electrode of the fourteenth transistor T14 is electrically connected to the first selection clock signal terminal CK1, and the first electrode of the fourteenth transistor T14 is electrically connected to the second selection clock signal terminal CK2; the control electrode of the fifteenth transistor T15 is electrically connected to the third node N3, the first electrode of the fifteenth transistor T15 is electrically connected to the first node N1, and the second electrode of the fifteenth transistor T15 is electrically connected to the second selection clock signal terminal CK2; the control electrode of the sixteenth transistor T16 is electrically connected to the second selection clock signal terminal CK2, and the control electrode of the sixteenth transistor T17 is electrically connected to the second selection clock signal terminal CK2. A first electrode of the sixteenth transistor T16 is electrically connected to the first selection clock signal terminal CK1, and a second electrode of the sixteenth transistor T16 is electrically connected to the third node N3; a control electrode of the seventeenth transistor T17 is electrically connected to the fourth node N4, a first electrode of the seventeenth transistor T17 is electrically connected to the first output clock signal terminal CKE1, and a second electrode of the seventeenth transistor T17 is electrically connected to the first signal output terminal OUT1; a control electrode of the eighteenth transistor T18 is electrically connected to the first node N1, a first electrode of the eighteenth transistor T18 is electrically connected to the second power supply terminal VGL, and a second electrode of the eighteenth transistor T18 is electrically connected to the first signal output terminal OUT1; a control electrode of the nineteenth transistor T19 is electrically connected to the fifth node N5, and the nineteenth transistor T19 is electrically connected to the fifth node N5. The first electrode of the 21st transistor T21 is electrically connected to the reset signal terminal TRS, the first electrode of the 21st transistor T21 is electrically connected to the second power supply terminal VGL, and the second electrode of the 21st transistor T21 is electrically connected to the third node N3; the control electrode of the 22nd transistor T22 is electrically connected to the first power supply terminal VGH, and the first electrode of the 22nd transistor T22 is electrically connected to the reset signal terminal TRS. a control electrode of the twenty-third transistor T23 electrically connected to the first power supply terminal VGH, a first electrode of the twenty-third transistor T23 electrically connected to the third node N3, and a second electrode of the twenty-third transistor T23 electrically connected to the fourth node N4; a first end of the first capacitor C1 electrically connected to the first node N1, and a second end of the first capacitor C1 electrically connected to the second power supply terminal VGL; a first end of the second capacitor C2 electrically connected to the first power supply terminal VGH, and a second end of the second capacitor C2 electrically connected to the second node N2; a first end of the third capacitor C3 electrically connected to the fourth node N4, and a second end of the third capacitor C3 electrically connected to the first signal output terminal OUT1;A first end of the fourth capacitor C4 is electrically connected to the fifth node N5, and a second end of the fourth capacitor C4 is electrically connected to the second signal output terminal OUT2.

[0255] Figure 23 is a fourth equivalent circuit diagram of the shift register provided by an embodiment of the present disclosure. As shown in Figure 23, in an exemplary embodiment, the shift register includes: a first transistor T1 to a twenty-first transistor T21 and a first capacitor C1 to a fourth capacitor C4. The control electrode of the first transistor T1 is electrically connected to the second selection clock signal terminal CK2, the first electrode of the first transistor T1 is electrically connected to the first power supply terminal VGH, and the second electrode of the first transistor T1 is electrically connected to the first node N1; the control electrode of the second transistor T2 is electrically connected to the first selection signal terminal D0, the first electrode of the second transistor T2 is electrically connected to the second selection clock signal terminal CK2, and the second electrode of the second transistor T2 is electrically connected to the second node N2; the control electrode of the third transistor T3 is electrically connected to the second selection signal terminal D1, the first electrode of the third transistor T3 is electrically connected to the second selection clock signal terminal CK2, and the second electrode of the third transistor T3 is electrically connected to the The second node N2 is electrically connected; the control electrode of the fourth transistor T4 is electrically connected to the third selection signal terminal D2, the first electrode of the fourth transistor T4 is electrically connected to the second selection clock signal terminal CK2, and the second electrode of the fourth transistor T4 is electrically connected to the second node N2; the control electrode of the fifth transistor T5 is electrically connected to the fourth selection signal terminal D3, the first electrode of the fifth transistor T5 is electrically connected to the second selection clock signal terminal CK2, and the second electrode of the fifth transistor T5 is electrically connected to the second node N2; the control electrode of the sixth transistor T6 is electrically connected to the fifth selection signal terminal D4, the first electrode of the sixth transistor T6 is electrically connected to the second selection clock signal terminal CK2, and the sixth transistor The second electrode of T6 is electrically connected to the second node N2; the control electrode of the seventh transistor T7 is electrically connected to the sixth selection signal terminal D5, the first electrode of the seventh transistor T7 is electrically connected to the second selection clock signal terminal CK2, and the second electrode of the seventh transistor T7 is electrically connected to the second node N2; the control electrode of the eighth transistor T8 is electrically connected to the seventh selection signal terminal D6, the first electrode of the eighth transistor T8 is electrically connected to the second selection clock signal terminal CK2, and the second electrode of the eighth transistor T8 is electrically connected to the second node N2; the control electrode of the ninth transistor T9 is electrically connected to the eighth selection signal terminal D7, and the first electrode of the ninth transistor T9 is electrically connected to the second selection clock signal terminal CK2 a control electrode of the twelfth transistor T12 and the first gate clock signal terminal CK1, and a second gate of the twelfth transistor T12 and the second gate clock signal terminal CK3; a control electrode of the twelfth transistor T12 and the first gate clock signal terminal CK1, respectively; a control electrode of the twelfth transistor T12 and the second gate clock signal terminal CK3, respectively ...The control electrode of the thirteenth transistor T13 is electrically connected to the second node N2, the first electrode of the thirteenth transistor T13 is electrically connected to the first node N1, and the second electrode of the thirteenth transistor T13 is electrically connected to the second electrode of the fourteenth transistor T14; the control electrode of the fourteenth transistor T14 is electrically connected to the first selection clock signal terminal CK1, and the first electrode of the fourteenth transistor T14 is electrically connected to the second selection clock signal terminal CK2; the control electrode of the fifteenth transistor T15 is electrically connected to the third node N3, the first electrode of the fifteenth transistor T15 is electrically connected to the first node N1, and the second electrode of the fifteenth transistor T15 is electrically connected to the second selection clock signal terminal CK2; The control electrode of the transistor T16 is electrically connected to the second selection clock signal terminal CK2, the first electrode of the sixteenth transistor T16 is electrically connected to the first selection clock signal terminal CK1, and the second electrode of the sixteenth transistor T16 is electrically connected to the third node N3; the control electrode of the seventeenth transistor T17 is electrically connected to the third node N3, the first electrode of the seventeenth transistor T17 is electrically connected to the first output clock signal terminal CKE1, and the second electrode of the seventeenth transistor T17 is electrically connected to the first signal output terminal OUT1; the control electrode of the eighteenth transistor T18 is electrically connected to the first node N1, the first electrode of the eighteenth transistor T18 is electrically connected to the second power supply terminal VGL, and the eighteenth transistor T18 is electrically connected to the third node N3. The second electrode of the twentieth transistor T20 is electrically connected to the first node N1, the first electrode of the twentieth transistor T20 is electrically connected to the second power supply terminal VGL, and the second electrode of the twentieth transistor T20 is electrically connected to the second signal output terminal OUT2; the control electrode of the twenty-first transistor T21 is electrically connected to the reset signal terminal TRS, and the first electrode of the twenty-first transistor T21 is electrically connected to the reset signal terminal TRS. One electrode is electrically connected to the second power supply terminal VGL, and the second electrode of the twenty-first transistor T21 is electrically connected to the third node N3; a first end of the first capacitor C1 is electrically connected to the first node N1, and a second end of the first capacitor C1 is electrically connected to the second power supply terminal VGL; a first end of the second capacitor C2 is electrically connected to the first power supply terminal VGH, and a second end of the second capacitor C2 is electrically connected to the second node N2; a first end of the third capacitor C3 is electrically connected to the third node N3, and a second end of the third capacitor C3 is electrically connected to the first signal output terminal OUT1; a first end of the fourth capacitor C4 is electrically connected to the third node N3, and a second end of the fourth capacitor C4 is electrically connected to the second signal output terminal OUT2.

[0256] Figure 24 is an equivalent circuit diagram 5 of the shift register provided by an embodiment of the present disclosure. As shown in Figure 24, in an exemplary embodiment, the shift register includes: a first transistor T1 to a twenty-second transistor T22 and a first capacitor C1 to a fourth capacitor C4. The control electrode of the first transistor T1 is electrically connected to the second selection clock signal terminal CK2, the first electrode of the first transistor T1 is electrically connected to the first power supply terminal VGH, and the second electrode of the first transistor T1 is electrically connected to the first node N1; the control electrode of the second transistor T2 is electrically connected to the first selection signal terminal D0, the first electrode of the second transistor T2 is electrically connected to the second selection clock signal terminal CK2, and the second electrode of the second transistor T2 is electrically connected to the second node N2; the control electrode of the third transistor T3 is electrically connected to the second selection signal terminal D1, the first electrode of the third transistor T3 is electrically connected to the second selection clock signal terminal CK2, and the second electrode of the third transistor T3 is electrically connected to the The second node N2 is electrically connected; the control electrode of the fourth transistor T4 is electrically connected to the third selection signal terminal D2, the first electrode of the fourth transistor T4 is electrically connected to the second selection clock signal terminal CK2, and the second electrode of the fourth transistor T4 is electrically connected to the second node N2; the control electrode of the fifth transistor T5 is electrically connected to the fourth selection signal terminal D3, the first electrode of the fifth transistor T5 is electrically connected to the second selection clock signal terminal CK2, and the second electrode of the fifth transistor T5 is electrically connected to the second node N2; the control electrode of the sixth transistor T6 is electrically connected to the fifth selection signal terminal D4, the first electrode of the sixth transistor T6 is electrically connected to the second selection clock signal terminal CK2, and the sixth transistor The second electrode of T6 is electrically connected to the second node N2; the control electrode of the seventh transistor T7 is electrically connected to the sixth selection signal terminal D5, the first electrode of the seventh transistor T7 is electrically connected to the second selection clock signal terminal CK2, and the second electrode of the seventh transistor T7 is electrically connected to the second node N2; the control electrode of the eighth transistor T8 is electrically connected to the seventh selection signal terminal D6, the first electrode of the eighth transistor T8 is electrically connected to the second selection clock signal terminal CK2, and the second electrode of the eighth transistor T8 is electrically connected to the second node N2; the control electrode of the ninth transistor T9 is electrically connected to the eighth selection signal terminal D7, and the first electrode of the ninth transistor T9 is electrically connected to the second selection clock signal terminal CK2 a control electrode of the twelfth transistor T12 and the first gate clock signal terminal CK1, and a second gate of the twelfth transistor T12 and the second gate clock signal terminal CK3; a control electrode of the twelfth transistor T12 and the first gate clock signal terminal CK1, respectively; a control electrode of the twelfth transistor T12 and the second gate clock signal terminal CK3, respectively ...The control electrode of the thirteenth transistor T13 is electrically connected to the second node N2, the first electrode of the thirteenth transistor T13 is electrically connected to the first node N1, and the second electrode of the thirteenth transistor T13 is electrically connected to the second electrode of the fourteenth transistor T14; the control electrode of the fourteenth transistor T14 is electrically connected to the first selection clock signal terminal CK1, and the first electrode of the fourteenth transistor T14 is electrically connected to the second selection clock signal terminal CK2; the control electrode of the fifteenth transistor T15 is electrically connected to the third node N3, the first electrode of the fifteenth transistor T15 is electrically connected to the first node N1, and the second electrode of the fifteenth transistor T15 is electrically connected to the second selection clock signal terminal CK2; the control electrode of the sixteenth transistor T16 is electrically connected to the second selection clock signal terminal C The first electrode of the sixteenth transistor T16 is electrically connected to the first selection clock signal terminal CK1, and the second electrode of the sixteenth transistor T16 is electrically connected to the third node N3; the control electrode of the seventeenth transistor T17 is electrically connected to the fourth node N4, the first electrode of the seventeenth transistor T17 is electrically connected to the first output clock signal terminal CKE1, and the second electrode of the seventeenth transistor T17 is electrically connected to the first signal output terminal OUT1; the control electrode of the eighteenth transistor T18 is electrically connected to the first node N1, the first electrode of the eighteenth transistor T18 is electrically connected to the second power supply terminal VGL, and the second electrode of the eighteenth transistor T18 is electrically connected to the first signal output terminal OUT1; the control electrode of the nineteenth transistor T19 is electrically connected to the fourth node N4, the first electrode of the seventeenth transistor T17 is electrically connected to the first output clock signal terminal CKE1, and the second electrode of the seventeenth transistor T17 is electrically connected to the first signal output terminal OUT1; N4 is electrically connected, a first electrode of the nineteenth transistor T19 is electrically connected to the second output clock signal terminal CKE2, and a second electrode of the nineteenth transistor T19 is electrically connected to the second signal output terminal OUT2; a control electrode of the twentieth transistor T20 is electrically connected to the first node N1, a first electrode of the twentieth transistor T20 is electrically connected to the second power supply terminal VGL, and a second electrode of the twentieth transistor T20 is electrically connected to the second signal output terminal OUT2; a control electrode of the twenty-first transistor T21 is electrically connected to the reset signal terminal TRS, a first electrode of the twenty-first transistor T21 is electrically connected to the second power supply terminal VGL, and a second electrode of the twenty-first transistor T21 is electrically connected to the third node N3; a control electrode of the twenty-second transistor T22 is electrically connected to the first The power supply terminal VGH is electrically connected, the first electrode of the twenty-second transistor T22 is electrically connected to the third node N3, and the second electrode of the twenty-second transistor T22 is electrically connected to the fourth node N4. The first end of the first capacitor C1 is electrically connected to the first node N1, and the second end of the first capacitor C1 is electrically connected to the second power supply terminal VGL. The first end of the second capacitor C2 is electrically connected to the first power supply terminal VGH, and the second end of the second capacitor C2 is electrically connected to the second node N2. The first end of the third capacitor C3 is electrically connected to the fourth node N4, and the second end of the third capacitor C3 is electrically connected to the first signal output terminal OUT1. The first end of the fourth capacitor C4 is electrically connected to the fourth node N4, and the second end of the fourth capacitor C4 is electrically connected to the second signal output terminal OUT2.

[0257] Figure 25 is an equivalent circuit diagram of the shift register provided by an embodiment of the present disclosure. As shown in Figure 26, in an exemplary embodiment, the shift register includes: a first transistor T1 to a twenty-third transistor T23 and a first capacitor C1 to a fourth capacitor C4. The control electrode of the first transistor T1 is electrically connected to the second selection clock signal terminal CK2, the first electrode of the first transistor T1 is electrically connected to the first power supply terminal VGH, and the second electrode of the first transistor T1 is electrically connected to the first node N1; the control electrode of the second transistor T2 is electrically connected to the first selection signal terminal D0, the first electrode of the second transistor T2 is electrically connected to the second selection clock signal terminal CK2, and the second electrode of the second transistor T2 is electrically connected to the second node N2; the control electrode of the third transistor T3 is electrically connected to the second selection signal terminal D1, the first electrode of the third transistor T3 is electrically connected to the second selection clock signal terminal CK2, and the second electrode of the third transistor T3 is electrically connected to the The second node N2 is electrically connected; the control electrode of the fourth transistor T4 is electrically connected to the third selection signal terminal D2, the first electrode of the fourth transistor T4 is electrically connected to the second selection clock signal terminal CK2, and the second electrode of the fourth transistor T4 is electrically connected to the second node N2; the control electrode of the fifth transistor T5 is electrically connected to the fourth selection signal terminal D3, the first electrode of the fifth transistor T5 is electrically connected to the second selection clock signal terminal CK2, and the second electrode of the fifth transistor T5 is electrically connected to the second node N2; the control electrode of the sixth transistor T6 is electrically connected to the fifth selection signal terminal D4, the first electrode of the sixth transistor T6 is electrically connected to the second selection clock signal terminal CK2, and the sixth transistor The second electrode of T6 is electrically connected to the second node N2; the control electrode of the seventh transistor T7 is electrically connected to the sixth selection signal terminal D5, the first electrode of the seventh transistor T7 is electrically connected to the second selection clock signal terminal CK2, and the second electrode of the seventh transistor T7 is electrically connected to the second node N2; the control electrode of the eighth transistor T8 is electrically connected to the seventh selection signal terminal D6, the first electrode of the eighth transistor T8 is electrically connected to the second selection clock signal terminal CK2, and the second electrode of the eighth transistor T8 is electrically connected to the second node N2; the control electrode of the ninth transistor T9 is electrically connected to the eighth selection signal terminal D7, and the first electrode of the ninth transistor T9 is electrically connected to the second selection clock signal terminal CK2 a control electrode of the twelfth transistor T12 and the first gate clock signal terminal CK1, and a second gate of the twelfth transistor T12 and the second gate clock signal terminal CK3; a control electrode of the twelfth transistor T12 and the first gate clock signal terminal CK1, respectively; a control electrode of the twelfth transistor T12 and the second gate clock signal terminal CK3, respectively ...The control electrode of the thirteenth transistor T13 is electrically connected to the second node N2, the first electrode of the thirteenth transistor T13 is electrically connected to the first node N1, and the second electrode of the thirteenth transistor T13 is electrically connected to the second electrode of the fourteenth transistor T14; the control electrode of the fourteenth transistor T14 is electrically connected to the first selection clock signal terminal CK1, and the first electrode of the fourteenth transistor T14 is electrically connected to the second selection clock signal terminal CK2; the control electrode of the fifteenth transistor T15 is electrically connected to the third node N3, the first electrode of the fifteenth transistor T15 is electrically connected to the first node N1, and the second electrode of the fifteenth transistor T15 is electrically connected to the second selection clock signal terminal CK2; the control electrode of the sixteenth transistor T16 is electrically connected to the second selection clock signal terminal CK2, and the control electrode of the sixteenth transistor T17 is electrically connected to the second selection clock signal terminal CK2. A first electrode of the sixteenth transistor T16 is electrically connected to the first selection clock signal terminal CK1, and a second electrode of the sixteenth transistor T16 is electrically connected to the third node N3; a control electrode of the seventeenth transistor T17 is electrically connected to the fourth node N4, a first electrode of the seventeenth transistor T17 is electrically connected to the first output clock signal terminal CKE1, and a second electrode of the seventeenth transistor T17 is electrically connected to the first signal output terminal OUT1; a control electrode of the eighteenth transistor T18 is electrically connected to the first node N1, a first electrode of the eighteenth transistor T18 is electrically connected to the second power supply terminal VGL, and a second electrode of the eighteenth transistor T18 is electrically connected to the first signal output terminal OUT1; a control electrode of the nineteenth transistor T19 is electrically connected to the fifth node N5, and the nineteenth transistor T19 is electrically connected to the fifth node N5. The first electrode of the 21st transistor T21 is electrically connected to the reset signal terminal TRS, the first electrode of the 21st transistor T21 is electrically connected to the second power supply terminal VGL, and the second electrode of the 21st transistor T21 is electrically connected to the third node N3; the control electrode of the 22nd transistor T22 is electrically connected to the first power supply terminal VGH, and the first electrode of the 22nd transistor T22 is electrically connected to the reset signal terminal TRS. a control electrode of the twenty-third transistor T23 electrically connected to the first power supply terminal VGH, a first electrode of the twenty-third transistor T23 electrically connected to the third node N3, and a second electrode of the twenty-third transistor T23 electrically connected to the fourth node N4; a first end of the first capacitor C1 electrically connected to the first node N1, and a second end of the first capacitor C1 electrically connected to the second power supply terminal VGL; a first end of the second capacitor C2 electrically connected to the first power supply terminal VGH, and a second end of the second capacitor C2 electrically connected to the second node N2; a first end of the third capacitor C3 electrically connected to the fourth node N4, and a second end of the third capacitor C3 electrically connected to the first signal output terminal OUT1;A first end of the fourth capacitor C4 is electrically connected to the fifth node N5, and a second end of the fourth capacitor C4 is electrically connected to the second signal output terminal OUT2.

[0258] In an exemplary embodiment, any capacitor among the first capacitor C1 to the fourth capacitor C4 can be a capacitor device made by a process. For example, a capacitor device can be realized by making a special capacitor electrode, and multiple capacitor electrodes of the capacitor can be realized by a metal layer, a semiconductor layer (such as doped polysilicon), etc. Alternatively, any capacitor among the first capacitor C1 to the fourth capacitor C4 can be a parasitic capacitance between multiple devices, which can be realized by the transistor itself and other devices and circuits. The connection method of any capacitor among the first capacitor C1 to the fourth capacitor C4 includes but is not limited to the method described above, and can be other applicable connection methods, and the level of the corresponding node can be stored. Here, the exemplary embodiment of the present disclosure is not limited to this.

[0259] In example embodiments, at least one transistor among the first to twenty-first transistors T1 to T21 in the shift register provided in FIG. 20 and FIG. 23 may be an N-type transistor.

[0260] In an exemplary embodiment, at least one transistor among the first to twenty-second transistors T1 to T22 in the shift register provided in FIG. 21 and FIG. 24 may be an N-type transistor.

[0261] In example embodiments, at least one transistor among the first to twenty-third transistors T1 to T23 in the shift register provided in FIG. 22 and FIG. 25 may be an N-type transistor.

[0262] In an exemplary embodiment, a shift register may be provided in a display device. The operating modes of the display device may include a first scanning mode and a second scanning mode. In the first scanning mode, a signal outputted by the first signal output terminal OUT1 of the shift register is earlier than a signal outputted by the second signal output terminal OUT2 of the shift register, and the timing of the signal outputted by the first signal output terminal OUT1 of the shift register does not overlap with the timing of the signal outputted by the second signal output terminal OUT2 of the shift register. In the second scanning mode, a signal outputted by the second signal output terminal OUT2 of the shift register is earlier than the signal outputted by the first signal output terminal OUT1 of the shift register, and the timing of the signal outputted by the first signal output terminal OUT1 of the shift register does not overlap with the timing of the signal outputted by the second signal output terminal OUT2 of the shift register.

[0263] FIG26 is an operation timing diagram of the shift register provided in FIG20 and FIG23 in the first scanning mode. The shift register in FIG26 includes twenty-one transistors (first transistor T1 to twenty-first transistor T21) and four capacitors (first capacitor C1 to fourth capacitor C4), wherein the first transistor T1 to twenty-first transistor T21 are N-type transistors.

[0264] In an exemplary embodiment, as shown in FIG. 26 , in the first scanning mode, the operation process of the shift register provided in FIG. 20 and FIG. 23 includes: a first stage S11 to a sixth stage S16 .

[0265] In the first phase S11, referred to as the reset phase, the signals at the reset signal terminal TRS and the first to eighth select signal terminals D0 to D7 are high-level signals, and the signals at the first select clock signal terminal CK1, the second select clock signal terminal CK2, the first output clock signal terminal CKE1, and the second output clock signal terminal CKE2 are low-level signals. The second to ninth transistors T2 to T9 and the twenty-first transistor T21 are turned on, while the first transistor T1, the tenth transistor T10, the twelfth transistor T12, the fourteenth transistor T14, and the sixteenth transistor T16 are turned off.

[0266] The twenty-first transistor T21 is turned on, and the signal at the third node N3 is pulled low by the low-level signal from the second power supply terminal VGL. The seventeenth transistor T17 and the nineteenth transistor T19 are turned off, and the first signal output terminal OUT1 and the second signal output terminal OUT2 are in a floating state. The second transistor T2 through the ninth transistor T9 are turned on, and the low-level signal from the second selection clock signal terminal CK2 is written to the second node N2, causing the signal at the second node N2 to be a low-level signal. The eleventh transistor T11 and the thirteenth transistor T13 are turned off, causing the signal at the first node N1 to be a low-level signal. The eighteenth transistor T18 and the twentieth transistor T20 are turned off. In this stage, the signals at the first node N1, the second node N2, and the third node N3 are all low-level signals.

[0267] In the second phase S12, referred to as the third node set phase, the signal at the second selection clock signal terminal CK2 is a high-level signal, the signals at the reset signal terminal TRS, the first selection clock signal terminal CK1, the first output clock signal terminal CKE1, and the second output clock signal terminal CKE2 are low-level signals, and the signal at any selection signal terminal from the first selection signal terminal D0 to the eighth selection signal terminal D7 changes from a high-level signal to a low-level signal. The first transistor T1, the tenth transistor T10, and the sixteenth transistor T16 are turned on, and any transistor from the second transistor T2 to the ninth transistor T9 is turned on for part of the time period and turned off for part of the time period, and the time when any transistor from the second transistor T2 to the ninth transistor T9 is turned on occurs before the time when any transistor from the second transistor T2 to the ninth transistor T9 is turned off, and the twelfth transistor T12, the fourteenth transistor T14, and the twenty-first transistor T21 are turned off.

[0268] The first transistor T1 is turned on, and a high-level signal from the second selection clock signal terminal CK2 or the first power supply terminal VGH is written to the first node N1, and the signal at the first node N1 is a high-level signal. The eighteenth transistor T18 and the twentieth transistor T20 are turned on, and a low-level signal from the second power supply terminal VGL is written to the first signal output terminal OUT1 and the second signal output terminal OUT2. The tenth transistor T10 is turned on, and a high-level signal from the second selection clock signal terminal CK2 is written to the second node N2, and the signal at the second node N2 is a high-level signal. The eleventh transistor T11 is turned on, and a high-level signal from the first power supply terminal VGH is written to the first electrode of the twelfth transistor T12. The thirteenth transistor T13 is turned on. The twelfth transistor T12 is turned off, and the signal from the first power supply terminal VGH cannot be written to the third node N3. The sixteenth transistor T16 is turned on, and a low-level signal from the first selection clock signal terminal CK1 is written to the third node N3, and the signal at the third node N3 is a low-level signal. The seventeenth transistor T17 and the nineteenth transistor T19 remain turned off. In this stage, the signals at the first node N1 and the second node N2 are high level signals, the signal at the third node N3 is low level signal, and the signals at the first signal output terminal OUT1 and the second signal output terminal OUT2 are low level signals.

[0269] In this stage, since any transistor from the second transistor T2 to the ninth transistor T9 is disconnected at a time point in the time period when the signal at the second selection clock signal terminal CK2 is a high-level signal, when the signal at the second selection clock signal terminal CK2 changes from a high-level signal to a low-level signal, the signal at the second node N2 will not be pulled down by the signal at the second selection clock signal terminal CK2.

[0270] After the signal at the second selection clock signal terminal CK2 changes from a high-level signal to a low-level signal, the signal at the first selection clock signal terminal CK1 remains a low-level signal for a portion of the time period. At this time, although the first transistor T1 is disconnected, the signal at the first node N1 still remains a high-level signal under the action of the first capacitor C1.

[0271] In the third phase S13, referred to as the third node set phase, the signal at the first selection clock signal terminal CK1 is a high-level signal, the signals at the reset signal terminal TRS, the second selection clock signal terminal CK2, the first output clock signal terminal CKE1, and the second output clock signal terminal CKE2 are low-level signals, and the signal at any of the first selection signal terminal D0 to the eighth selection signal terminal D7 is a low-level signal. The twelfth transistor T12 and the fourteenth transistor T14 are turned on, and the first transistor T1, the second transistor T2 to the ninth transistor T9, the tenth transistor T10, the sixteenth transistor T16, and the twenty-first transistor T21 are turned off.

[0272] Although the signal at the second selection clock signal terminal CK2 is a low-level signal, the signal at the second node N2 remains a high-level signal due to the action of the second capacitor C2. The eleventh transistor T11 is turned on, and the high-level signal at the first power supply terminal VGH is written to the third node N3 through the turned-on eleventh transistor T11 and the twelfth transistor T12. The fifteenth transistor T15, the seventeenth transistor T17, and the nineteenth transistor T19 are turned on, and the low-level signal at the first output clock signal terminal CKE1 is written to the first signal output terminal OUT1, and the low-level signal at the second output clock signal terminal CKE2 is written to the second signal output terminal OUT2. The low-level signal at the second selection clock signal terminal CK2 is written to the first node N1 through the turned-on thirteenth transistor T13 and the fourteenth transistor T14. The low-level signal at the second selection clock signal terminal CK2 is also written to the first node N1 through the turned-on fifteenth transistor T15, causing the signal at the first node N1 to be a low-level signal. The eighteenth transistor T18 and the twentieth transistor T20 are turned off. In this stage, the signal of the first node N1 is a low level signal, the signals of the second node N2 and the third node N3 are high level signals, and the signals of the first signal output terminal OUT1 and the second signal output terminal OUT2 are low level signals.

[0273] In the fourth phase S14, referred to as the output phase, the signals at the reset signal terminal TRS, the first selection clock signal terminal CK1, the second selection clock signal terminal CK2, and any of the first selection signal terminals D0 through the eighth selection signal terminal D7 are low-level signals. The output phase comprises a first time period t1, a third time period t3, and a second time period t2, which occur sequentially. The signal at the first output clock signal terminal CKE1 is high-level in the first time period t1, and the signal at the second output clock signal terminal CKE2 is high-level in the second time period t2. The first transistor T1, the second transistor T2 through the ninth transistor T9, the tenth transistor T10, the twelfth transistor T12, the fourteenth transistor T14, the sixteenth transistor T16, and the twenty-first transistor T21 are disconnected.

[0274] The second node N2 and the third node N3 maintain the high-level signal of the previous stage, the fifteenth transistor T15 is turned on, and the low-level signal of the second selection clock signal terminal CK2 is written into the first node N1, so that the signal of the first node N1 is a low-level signal, the seventeenth transistor T17 and the nineteenth transistor T19 are turned on, the eighteenth transistor T18 and the twentieth transistor T20 are turned off, and the low-level signal of the second power supply terminal VGL cannot be written into the first signal output terminal OUT1 and the second signal output terminal OUT2.

[0275] During the first time period t1, the signal at the first output clock signal terminal CKE1 is a high-level signal, and the signal at the second output clock signal terminal CKE2 is a low-level signal. The seventeenth transistor T17 is turned on, and the high-level signal at the first output clock signal terminal CKE1 is written to the first signal output terminal OUT1. The nineteenth transistor T19 is turned on, and the low-level signal at the second output clock signal terminal CKE2 is written to the second signal output terminal OUT2. During this phase, under the action of the third capacitor C3, although the signal at the third node N3 is pulled high by the signal at the first signal output terminal OUT1, the signal at the third node N3 is pulled low by the signal at the second signal output terminal OUT2 under the action of the fourth capacitor C4, causing the signal at the third node N3 to remain unchanged. During this phase, the signal at the first signal output terminal OUT1 is a high-level signal, and the signal at the second signal output terminal OUT2 is a low-level signal.

[0276] During the third time period t3, the signals at the first output clock signal terminal CKE1 and the second output clock signal terminal CKE2 are low-level signals. The seventeenth transistor T17 is turned on, and the high-level signal at the first output clock signal terminal CKE1 is written to the first signal output terminal OUT1. The nineteenth transistor T19 is turned on, and the low-level signal at the second output clock signal terminal CKE2 is written to the second signal output terminal OUT2. During this phase, the signals at the first signal output terminal OUT1 and the second signal output terminal OUT2 are low-level signals.

[0277] During the second time period t2, the signal at the first output clock signal terminal CKE1 is a low-level signal, and the signal at the second output clock signal terminal CKE2 is a high-level signal. The seventeenth transistor T17 is turned on, and the low-level signal at the first output clock signal terminal CKE1 is written to the first signal output terminal OUT1. The nineteenth transistor T19 is turned on, and the high-level signal at the second output clock signal terminal CKE2 is written to the second signal output terminal OUT2. During this phase, under the action of the third capacitor C3, although the signal at the third node N3 is pulled low by the signal at the first signal output terminal OUT1, the signal at the third node N3 is pulled high by the signal at the second signal output terminal OUT2 under the action of the fourth capacitor C4, causing the signal at the third node N3 to remain unchanged. During this phase, the signal at the first signal output terminal OUT1 is a low-level signal, and the signal at the second signal output terminal OUT2 is a high-level signal.

[0278] In the fifth phase S15, referred to as the second and third node set phase, the signal at the second selection clock signal terminal CK2 is a high-level signal, the signals at the reset signal terminal TRS, the first selection clock signal terminal CK1, the first output clock signal terminal CKE1, and the second output clock signal terminal CKE2 are low-level signals, the signal at the first selection signal terminal D0 changes from a low-level signal to a high-level signal, and the signal at any of the second selection signal terminals D1 to the eighth selection signal terminal D7 is a low-level signal. The first transistor T1, the tenth transistor T10, and the sixteenth transistor T16 are turned on, the second transistor T2 is partially turned off and partially turned on, and the period of time during which the second transistor T2 is turned on occurs after the period during which the second transistor T2 is turned off. Any of the third transistor T3 to the ninth transistor T9 is turned off, and the twelfth transistor T12, the fourteenth transistor T14, and the twenty-first transistor T21 are turned off.

[0279] The first transistor T1 is turned on, and a high-level signal from the second selection clock signal terminal CK2 or the first power supply terminal VGH is written to the first node N1, and the signal at the first node N1 is a high-level signal. The eighteenth transistor T18 and the twentieth transistor T20 are turned on, and a low-level signal from the second power supply terminal VGL is written to the first signal output terminal OUT1 and the second signal output terminal OUT2. The tenth transistor T10 is turned on, and a high-level signal from the second selection clock signal terminal CK2 is written to the second node N2, and the signal at the second node N2 is a high-level signal. The eleventh transistor T11 is turned on, and the sixteenth transistor T16 is turned on, and a low-level signal from the first selection clock signal terminal CK1 is written to the third node N3, and the signal at the third node N3 is a low-level signal. The fifteenth transistor T15, the seventeenth transistor T17, and the nineteenth transistor T19 are turned off. In this stage, the signals at the first node N1 and the second node N2 are high-level signals, the signal at the third node N3 is a low-level signal, and the signals at the first signal output terminal OUT1 and the second signal output terminal OUT2 are low-level signals.

[0280] In this stage, the second transistor T2 is turned on before the signal at the second selection clock signal terminal CK2 changes from a high level signal to a low level signal. Therefore, the signal at the second node N2 changes with the change of the signal at the second selection clock signal terminal CK2.

[0281] In the sixth phase S16, referred to as the non-selection phase, the signals at the second selection clock signal terminal CK2 and the reset signal terminal TRS are low-level signals, and the signal at at least one of the first selection signal terminal D0 to the eighth selection signal terminal D7 is high-level. The first transistor T1, the tenth transistor T10, and the sixteenth transistor T16 are turned off, and at least one of the second transistor T2 to the ninth transistor T9 is turned on.

[0282] At least one of the second to ninth transistors T2 to T9 is turned on. The low-level signal of the second selection clock signal terminal CK2 is written to the second node N2. The eleventh and thirteenth transistors T11 and T13 are turned off. The first node N1 maintains the high-level signal from the previous stage. The eighteenth and twentieth transistors T18 and T20 are turned on. The signal of the second power supply terminal VGL is written to the first and second signal output terminals OUT1 and OUT2. Because the eleventh transistor T11 is turned off, regardless of whether the first selection clock signal is a high-level signal or a low-level signal, the third node N3 still maintains the low-level signal from the previous stage. The seventeenth and nineteenth transistors T17 and T19 are turned off. The signal of the first output clock signal terminal CKE1 cannot be written to the first signal output terminal OUT1, and the signal of the second output clock signal terminal CKE2 cannot be written to the second signal output terminal OUT2.

[0283] FIG27 is an operating timing diagram of the shift register provided in FIG21 and FIG24 in the first scanning mode. The shift register in FIG27 includes twenty-two transistors (first transistor T1 to twenty-second transistor T22) and four capacitors (first capacitor C1 to fourth capacitor C4), where the first transistor T1 to twenty-second transistor T22 are N-type transistors.

[0284] In an exemplary embodiment, as shown in FIG. 27 , in the first scanning mode, the operation process of the shift register provided in FIG. 21 and FIG. 24 includes: a first stage S21 to a sixth stage S26 .

[0285] In the first phase S21, referred to as the reset phase, the signals at the reset signal terminal TRS and the first to eighth select signal terminals D0 to D7 are high-level signals, and the signals at the first select clock signal terminal CK1, the second select clock signal terminal CK2, the first output clock signal terminal CKE1, and the second output clock signal terminal CKE2 are low-level signals. The second to ninth transistors T2 to T9, the twenty-first transistor T21, and the second second transistor T22 are turned on, while the first transistor T1, the tenth transistor T10, the twelfth transistor T12, the fourteenth transistor T14, and the sixteenth transistor T16 are turned off.

[0286] The twenty-first transistor T21 is turned on, the signal at the third node N3 is pulled low by the low-level signal from the second power supply terminal VGL, and the signal at the fourth node N4 is pulled low by the signal at the third node N3. The seventeenth transistor T17 and the nineteenth transistor T19 are turned off, and the first signal output terminal OUT1 and the second signal output terminal OUT2 are in a floating state. The second transistor T2 through the ninth transistor T9 are turned on, and the low-level signal from the second selection clock signal terminal CK2 is written to the second node N2, making the signal at the second node N2 a low-level signal. The eleventh transistor T11 and the thirteenth transistor T13 are turned off, and the signal at the first node N1 is a low-level signal. The eighteenth transistor T18 and the twentieth transistor T20 are turned off. In this stage, the signals at the first node N1, the second node N2, the third node N3, and the fourth node N4 are all low-level signals.

[0287] In the second phase S22, referred to as the third node set phase, the signal at the second selection clock signal terminal CK2 is a high-level signal, the signals at the reset signal terminal TRS, the first selection clock signal terminal CK1, the first output clock signal terminal CKE1, and the second output clock signal terminal CKE2 are low-level signals, and the signal at at least one of the first selection signal terminal D0 to the eighth selection signal terminal D7 changes from a high-level signal to a low-level signal. The first transistor T1, the tenth transistor T10, the sixteenth transistor T16, and the twenty-second transistor T22 are turned on, and any one of the second transistor T2 to the ninth transistor T9 is turned on for part of the time period and turned off for part of the time period, and the time when any one of the second transistor T2 to the ninth transistor T9 is turned on occurs before the time when any one of the second transistor T2 to the ninth transistor T9 is turned off, and the twelfth transistor T12, the fourteenth transistor T14, and the twenty-first transistor T21 are turned off.

[0288] The first transistor T1 is turned on, and a high-level signal from the second selection clock signal terminal CK2 or the first power supply terminal VGH is written to the first node N1, and the signal at the first node N1 is a high-level signal. The eighteenth transistor T18 and the twentieth transistor T20 are turned on, and a low-level signal from the second power supply terminal VGL is written to the first signal output terminal OUT1 and the second signal output terminal OUT2. The tenth transistor T10 is turned on, and a high-level signal from the second selection clock signal terminal CK2 is written to the second node N2, and the signal at the second node N2 is a high-level signal. The eleventh transistor T11 is turned on, and a high-level signal from the first power supply terminal VGH is written to the first electrode of the twelfth transistor T12. The thirteenth transistor T13 is turned on. The twelfth transistor T12 is turned off, and the signal from the first power supply terminal VGH cannot be written to the third node N3. The sixteenth transistor T16 is turned on, and a low-level signal from the first selection clock signal terminal CK1 is written to the third node N3, and the signal at the third node N3 is a low-level signal. The signal at the fourth node N4 is also a low-level signal. The seventeenth transistor T17 and the nineteenth transistor T19 remain turned off. In this stage, the signals at the first node N1 and the second node N2 are high level signals, the signals at the third node N3 and the fourth node N4 are low level signals, and the signals at the first signal output terminal OUT1 and the second signal output terminal OUT2 are low level signals.

[0289] In this stage, since any transistor from the second transistor T2 to the ninth transistor T9 is disconnected at a time point in the time period when the signal at the second selection clock signal terminal CK2 is a high-level signal, when the signal at the second selection clock signal terminal CK2 changes from a high-level signal to a low-level signal, the signal at the second node N2 will not be pulled down by the signal at the second selection clock signal terminal CK2.

[0290] After the signal at the second selection clock signal terminal CK2 changes from a high-level signal to a low-level signal, the signal at the first selection clock signal terminal CK1 remains a low-level signal for a portion of the time period. At this time, although the first transistor T1 is disconnected, the signal at the first node N1 still remains a high-level signal under the action of the first capacitor C1.

[0291] In the third phase S23, referred to as the third node set phase, the signal at the first selection clock signal terminal CK1 is a high-level signal, the signals at the reset signal terminal TRS, the second selection clock signal terminal CK2, the first output clock signal terminal CKE1, and the second output clock signal terminal CKE2 are low-level signals, and the signal at any of the first selection signal terminal D0 to the eighth selection signal terminal D7 is a low-level signal. The twelfth transistor T12, the fourteenth transistor T14, and the twenty-second transistor T22 are turned on, and the first transistor T1, the second transistor T2 to the ninth transistor T9, the tenth transistor T10, the sixteenth transistor T16, and the twenty-first transistor T21 are turned off.

[0292] Although the signal at the second selection clock signal terminal CK2 is a low-level signal, the signal at the second node N2 remains a high-level signal due to the action of the second capacitor C2. The eleventh transistor T11 is turned on, and the high-level signal at the first power supply terminal VGH is written to the third node N3 through the turned-on eleventh transistor T11 and the twelfth transistor T12. The fifteenth transistor T15 is turned on, and the signal at the fourth node N4 is pulled high by the signal at the third node N3. The seventeenth transistor T17 and the nineteenth transistor T19 are turned on, and the low-level signal at the first output clock signal terminal CKE1 is written to the first signal output terminal OUT1, and the low-level signal at the second output clock signal terminal CKE2 is written to the second signal output terminal OUT2. The low-level signal at the second selection clock signal terminal CK2 is written to the first node N1 through the turned-on thirteenth transistor T13 and the fourteenth transistor T14. The low-level signal at the second selection clock signal terminal CK2 is also written to the first node N1 through the turned-on fifteenth transistor T15, causing the signal at the first node N1 to be a low-level signal. The eighteenth transistor T18 and the twentieth transistor T20 are turned off. In this stage, the signal of the first node N1 is a low level signal, the signals of the second node N2, the third node N3 and the fourth node N4 are high level signals, and the signals of the first signal output terminal OUT1 and the second signal output terminal OUT2 are low level signals.

[0293] In the fourth phase S24, referred to as the output phase, the signals at the reset signal terminal TRS, the first selection clock signal terminal CK1, the second selection clock signal terminal CK2, and any of the first selection signal terminals D0 through the eighth selection signal terminal D7 are low-level signals. The output phase comprises a first time period t1, a third time period t3, and a second time period t2, which occur sequentially. The signal at the first output clock signal terminal CKE1 is high-level in the first time period t1, and the signal at the second output clock signal terminal CKE2 is high-level in the second time period t2. The twenty-second transistor T22 is turned on, while the first transistor T1, the second transistor T2 through the ninth transistor T9, the tenth transistor T10, the twelfth transistor T12, the fourteenth transistor T14, the sixteenth transistor T16, and the twenty-first transistor T21 are turned off.

[0294] The second node N2, the third node N3 and the fourth node N4 maintain the high-level signal of the previous stage, the fifteenth transistor T15 is turned on, and the low-level signal of the second selection clock signal terminal CK2 is written into the first node N1, so that the signal of the first node N1 is a low-level signal, the seventeenth transistor T17 and the nineteenth transistor T19 are turned on, the eighteenth transistor T18 and the twentieth transistor T20 are turned off, and the low-level signal of the second power supply terminal VGL cannot be written into the first signal output terminal OUT1 and the second signal output terminal OUT2.

[0295] During the first time period t1, the signal at the first output clock signal terminal CKE1 is a high-level signal, and the signal at the second output clock signal terminal CKE2 is a low-level signal. The seventeenth transistor T17 is turned on, and the high-level signal at the first output clock signal terminal CKE1 is written to the first signal output terminal OUT1. The nineteenth transistor T19 is turned on, and the low-level signal at the second output clock signal terminal CKE2 is written to the second signal output terminal OUT2. During this phase, under the action of the third capacitor C3, although the signal at the fourth node N4 is pulled high by the signal at the first signal output terminal OUT1, the signal at the fourth node N4 is pulled low by the signal at the second signal output terminal OUT2 under the action of the fourth capacitor C4, causing the signal at the fourth node N4 to remain unchanged. During this phase, the signal at the first signal output terminal OUT1 is a high-level signal, and the signal at the second signal output terminal OUT2 is a low-level signal.

[0296] During the third time period t3, the signals at the first output clock signal terminal CKE1 and the second output clock signal terminal CKE2 are low-level signals. The seventeenth transistor T17 is turned on, and the high-level signal at the first output clock signal terminal CKE1 is written to the first signal output terminal OUT1. The nineteenth transistor T19 is turned on, and the low-level signal at the second output clock signal terminal CKE2 is written to the second signal output terminal OUT2. During this phase, the signals at the first signal output terminal OUT1 and the second signal output terminal OUT2 are low-level signals.

[0297] During the second time period t2, the signal at the first output clock signal terminal CKE1 is a low-level signal, and the signal at the second output clock signal terminal CKE2 is a high-level signal. The seventeenth transistor T17 is turned on, and the low-level signal at the first output clock signal terminal CKE1 is written to the first signal output terminal OUT1. The nineteenth transistor T19 is turned on, and the high-level signal at the second output clock signal terminal CKE2 is written to the second signal output terminal OUT2. During this phase, under the action of the third capacitor C3, although the signal at the fourth node N4 is pulled low by the signal at the first signal output terminal OUT1, the signal at the fourth node N4 is pulled high by the signal at the second signal output terminal OUT2 under the action of the fourth capacitor C4, causing the signal at the fourth node N4 to remain unchanged. During this phase, the signal at the first signal output terminal OUT1 is a low-level signal, and the signal at the second signal output terminal OUT2 is a high-level signal.

[0298] In the fifth stage S25, referred to as the second and third node set phase, the signal at the second selection clock signal terminal CK2 is a high-level signal, the signals at the reset signal terminal TRS, the first selection clock signal terminal CK1, the first output clock signal terminal CKE1, and the second output clock signal terminal CKE2 are low-level signals, the signal at the first selection signal terminal D0 changes from a low-level signal to a high-level signal, and the signal at any of the second selection signal terminals D1 to the eighth selection signal terminal D7 is a low-level signal. The first transistor T1, the tenth transistor T10, the sixteenth transistor T16, and the twenty-second transistor T22 are turned on, the second transistor T2 is turned off for part of the time period and turned on for part of the time period, and the time period in which the second transistor T2 is turned on occurs after the time period in which the second transistor T2 is turned off. Any of the third transistor T3 to the ninth transistor T9 is turned off, and the twelfth transistor T12, the fourteenth transistor T14, and the twenty-first transistor T21 are turned off.

[0299] The first transistor T1 is turned on, and a high-level signal from the second selection clock signal terminal CK2 or the first power supply terminal VGH is written to the first node N1, and the signal at the first node N1 is a high-level signal. The eighteenth transistor T18 and the twentieth transistor T20 are turned on, and a low-level signal from the second power supply terminal VGL is written to the first signal output terminal OUT1 and the second signal output terminal OUT2. The tenth transistor T10 is turned on, and a high-level signal from the second selection clock signal terminal CK2 is written to the second node N2, and the signal at the second node N2 is a high-level signal. The eleventh transistor T11 is turned on, and the sixteenth transistor T16 is turned on, and a low-level signal from the first selection clock signal terminal CK1 is written to the third node N3, and the signal at the third node N3 is a low-level signal. The signal at the fourth node N4 is pulled low by the signal at the third node N3. The fifteenth transistor T15, the seventeenth transistor T17, and the nineteenth transistor T19 are turned off. In this stage, the signals at the first node N1 and the second node N2 are high-level signals, the signals at the third node N3 and the fourth node N4 are low-level signals, and the signals at the first signal output terminal OUT1 and the second signal output terminal OUT2 are low-level signals.

[0300] In this phase, the second transistor T2 is turned on before the signal at the second selection clock signal terminal CK2 changes from a high-level signal to a low-level signal. Therefore, the signal at the second node N2 changes with the change in the signal at the second selection clock signal terminal CK2. In the sixth phase S26, referred to as the non-selection phase, the signals at the second selection clock signal terminal CK2 and the reset signal terminal TRS are low-level signals, and the signal at at least one of the first selection signal terminal D0 to the eighth selection signal terminal D7 is high-level. The first transistor T1, the tenth transistor T10, and the sixteenth transistor T16 are turned off, at least one of the second transistor T2 to the ninth transistor T9 is turned on, and the twenty-second transistor T22 is turned on.

[0301] At least one of the second to ninth transistors T2 to T9 is turned on. The low-level signal of the second selection clock signal terminal CK2 is written to the second node N2. The eleventh and thirteenth transistors T11 and T13 are turned off. The first node N1 maintains the high-level signal from the previous stage. The eighteenth and twentieth transistors T18 and T20 are turned on. The signal of the second power supply terminal VGL is written to the first signal output terminal OUT1 and the second signal output terminal OUT2. Because the eleventh transistor T11 is turned off, regardless of whether the first selection clock signal is a high-level signal or a low-level signal, the third node N3 still maintains the low-level signal from the previous stage. The signal of the fourth node N4 is pulled low by the signal of the third node N3. The seventeenth and nineteenth transistors T17 and T19 are turned off. The signal of the first output clock signal terminal CKE1 cannot be written to the first signal output terminal OUT1, and the signal of the second output clock signal terminal CKE2 cannot be written to the second signal output terminal OUT2.

[0302] FIG28 is an operating timing diagram of the shift register provided in FIG22 and FIG25 in the first scanning mode. The shift register in FIG25 includes twenty-three transistors (first transistor T1 to twenty-third transistor T23) and four capacitors (first capacitor C1 to fourth capacitor C4). The first transistor T1 to twenty-third transistor T23 are N-type transistors.

[0303] In an exemplary embodiment, as shown in FIG. 28 , in the first scanning mode, the operation process of the shift register provided in FIG. 22 and FIG. 25 includes: a first stage S31 to a sixth stage S36 .

[0304] In the first phase S31, referred to as the reset phase, the signals at the reset signal terminal TRS and the first to eighth selection signal terminals D0 to D7 are high-level signals, and the signals at the first selection clock signal terminal CK1, the second selection clock signal terminal CK2, the first output clock signal terminal CKE1, and the second output clock signal terminal CKE2 are low-level signals. The second to ninth transistors T2 to T9, the twenty-first transistor T21, the twenty-second transistor T22, and the twenty-third transistor T23 are turned on, while the first transistor T1, the tenth transistor T10, the twelfth transistor T12, the fourteenth transistor T14, and the sixteenth transistor T16 are turned off.

[0305] The twenty-first transistor T21 is turned on, the signal at the third node N3 is pulled low by the low-level signal from the second power supply terminal VGL, the signals at the fourth node N4 and the fifth node N5 are pulled low by the signal from the third node N3, the seventeenth transistor T17 and the nineteenth transistor T19 are turned off, and the first signal output terminal OUT1 and the second signal output terminal OUT2 are in a floating state. The second through ninth transistors T2 to T9 are turned on, the low-level signal from the second selection clock signal terminal CK2 is written to the second node N2, and the signal at the second node N2 is a low-level signal. The eleventh transistor T11 and the thirteenth transistor T13 are turned off, the signal at the first node N1 is a low-level signal, and the eighteenth transistor T18 and the twentieth transistor T20 are turned off. In this stage, the signals at the first node N1, the second node N2, the third node N3, the fourth node N4, and the fifth node N5 are all low-level signals.

[0306] In the second phase S32, referred to as the third node set phase, the signal at the second selection clock signal terminal CK2 is a high-level signal, the signals at the reset signal terminal TRS, the first selection clock signal terminal CK1, the first output clock signal terminal CKE1, and the second output clock signal terminal CKE2 are low-level signals, and the signal at at least one of the first selection signal terminal D0 to the eighth selection signal terminal D7 changes from a high-level signal to a low-level signal. The first transistor T1, the tenth transistor T10, the sixteenth transistor T16, the twenty-second transistor T22, and the twenty-third transistor T23 are turned on, and any one of the second transistor T2 to the ninth transistor T9 is turned on for part of the time period and turned off for part of the time period, and the time when any one of the second transistor T2 to the ninth transistor T9 is turned on occurs before the time when any one of the second transistor T2 to the ninth transistor T9 is turned off, and the twelfth transistor T12, the fourteenth transistor T14, and the twenty-first transistor T21 are turned off.

[0307] The first transistor T1 is turned on, and a high-level signal from the second selection clock signal terminal CK2 or the first power supply terminal VGH is written to the first node N1, and the signal at the first node N1 is a high-level signal. The eighteenth transistor T18 and the twentieth transistor T20 are turned on, and a low-level signal from the second power supply terminal VGL is written to the first signal output terminal OUT1 and the second signal output terminal OUT2. The tenth transistor T10 is turned on, and a high-level signal from the second selection clock signal terminal CK2 is written to the second node N2, and the signal at the second node N2 is a high-level signal. The eleventh transistor T11 is turned on, and a high-level signal from the first power supply terminal VGH is written to the first electrode of the twelfth transistor T12. The thirteenth transistor T13 is turned on. The twelfth transistor T12 is turned off, and the signal from the first power supply terminal VGH cannot be written to the third node N3. The sixteenth transistor T16 is turned on, and a low-level signal from the first selection clock signal terminal CK1 is written to the third node N3, and the signal at the third node N3 is a low-level signal. The signals at the fourth node N4 and the fifth node N5 are also low-level signals. The seventeenth transistor T17 and the nineteenth transistor T19 remain turned off. In this stage, the signals of the first node N1 and the second node N2 are high level signals, the signals of the third node N3, the fourth node N4 and the fifth node N5 are low level signals, and the signals of the first signal output terminal OUT1 and the second signal output terminal OUT2 are low level signals.

[0308] In this stage, since any transistor from the second transistor T2 to the ninth transistor T9 is disconnected at a time point in the time period when the signal at the second selection clock signal terminal CK2 is a high-level signal, when the signal at the second selection clock signal terminal CK2 changes from a high-level signal to a low-level signal, the signal at the second node N2 will not be pulled down by the signal at the second selection clock signal terminal CK2.

[0309] After the signal at the second selection clock signal terminal CK2 changes from a high-level signal to a low-level signal, the signal at the first selection clock signal terminal CK1 remains a low-level signal for a portion of the time period. At this time, although the first transistor T1 is disconnected, the signal at the first node N1 still remains a high-level signal under the action of the first capacitor C1.

[0310] In the third phase S33, referred to as the third node set phase, the signal at the first selection clock signal terminal CK1 is a high-level signal, the signals at the reset signal terminal TRS, the second selection clock signal terminal CK2, the first output clock signal terminal CKE1, and the second output clock signal terminal CKE2 are low-level signals, and the signal at any of the first selection signal terminal D0 to the eighth selection signal terminal D7 is a low-level signal. The twelfth transistor T12, the fourteenth transistor T14, the twenty-second transistor T22, and the twenty-third transistor T23 are turned on, and the first transistor T1, the second transistor T2 to the ninth transistor T9, the tenth transistor T10, the sixteenth transistor T16, and the twenty-first transistor T21 are turned off.

[0311] Although the signal at the second selection clock signal terminal CK2 is a low-level signal, the signal at the second node N2 remains a high-level signal due to the action of the second capacitor C2. The eleventh transistor T11 is turned on, and the high-level signal at the first power supply terminal VGH is written to the third node N3 through the turned-on eleventh transistor T11 and the twelfth transistor T12. The fifteenth transistor T15 is turned on, and the signals at the fourth node N4 and the fifth node N5 are pulled high by the signal at the third node N3. The seventeenth transistor T17 and the nineteenth transistor T19 are turned on, and the low-level signal at the first output clock signal terminal CKE1 is written to the first signal output terminal OUT1, and the low-level signal at the second output clock signal terminal CKE2 is written to the second signal output terminal OUT2. The low-level signal at the second selection clock signal terminal CK2 is written to the first node N1 through the turned-on thirteenth transistor T13 and the fourteenth transistor T14. The low-level signal at the second selection clock signal terminal CK2 is also written to the first node N1 through the turned-on fifteenth transistor T15, causing the signal at the first node N1 to be a low-level signal. The eighteenth transistor T18 and the twentieth transistor T20 are turned off. In this stage, the signal of the first node N1 is a low level signal, the signals of the second node N2, the third node N3, the fourth node N4 and the fifth node N5 are high level signals, and the signals of the first signal output terminal OUT1 and the second signal output terminal OUT2 are low level signals.

[0312] In the fourth phase S34, referred to as the output phase, the signals at the reset signal terminal TRS, the first selection clock signal terminal CK1, the second selection clock signal terminal CK2, and any of the first selection signal terminals D0 through the eighth selection signal terminal D7 are low-level signals. The output phase comprises a first time period t1, a third time period t3, and a second time period t2, which occur sequentially. The signal at the first output clock signal terminal CKE1 is high-level in the first time period t1, and the signal at the second output clock signal terminal CKE2 is high-level in the second time period t2. The twenty-second transistor T22 and the twenty-third transistor T23 are turned on, while the first transistor T1, the second transistor T2 through the ninth transistor T9, the tenth transistor T10, the twelfth transistor T12, the fourteenth transistor T14, the sixteenth transistor T16, and the twenty-first transistor T21 are turned off.

[0313] The second node N2, the third node N3, the fourth node N4 and the fifth node N5 maintain the high-level signal of the previous stage, the fifteenth transistor T15 is turned on, and the low-level signal of the second selection clock signal terminal CK2 is written into the first node N1, so that the signal of the first node N1 is a low-level signal, the seventeenth transistor T17 and the nineteenth transistor T19 are turned on, the eighteenth transistor T18 and the twentieth transistor T20 are turned off, and the low-level signal of the second power supply terminal VGL cannot be written into the first signal output terminal OUT1 and the second signal output terminal OUT2.

[0314] During the first time period t1, the signal at the first output clock signal terminal CKE1 is a high-level signal, and the signal at the second output clock signal terminal CKE2 is a low-level signal. The seventeenth transistor T17 is turned on, and the high-level signal at the first output clock signal terminal CKE1 is written to the first signal output terminal OUT1. The nineteenth transistor T19 is turned on, and the low-level signal at the second output clock signal terminal CKE2 is written to the second signal output terminal OUT2. During this phase, the signal at the fourth node N4 is pulled high by the signal at the first signal output terminal OUT1 under the action of the third capacitor C3. During this phase, the signal at the first signal output terminal OUT1 is a high-level signal, and the signal at the second signal output terminal OUT2 is a low-level signal.

[0315] During the third time period t3, the signals at the first output clock signal terminal CKE1 and the second output clock signal terminal CKE2 are low-level signals. The seventeenth transistor T17 is turned on, and the high-level signal at the first output clock signal terminal CKE1 is written to the first signal output terminal OUT1. The nineteenth transistor T19 is turned on, and the low-level signal at the second output clock signal terminal CKE2 is written to the second signal output terminal OUT2. During this phase, the signals at the first signal output terminal OUT1 and the second signal output terminal OUT2 are low-level signals.

[0316] During the second time period t2, the signal at the first output clock signal terminal CKE1 is a low-level signal, and the signal at the second output clock signal terminal CKE2 is a high-level signal. The seventeenth transistor T17 is turned on, and the low-level signal at the first output clock signal terminal CKE1 is written to the first signal output terminal OUT1. The nineteenth transistor T19 is turned on, and the high-level signal at the second output clock signal terminal CKE2 is written to the second signal output terminal OUT2. During this phase, the signal at the fifth node N5 is pulled high by the signal at the second signal output terminal OUT2 under the action of the fourth capacitor C4. During this phase, the signal at the first signal output terminal OUT1 is a low-level signal, and the signal at the second signal output terminal OUT2 is a high-level signal.

[0317] In the fifth stage S35, referred to as the second and third node set phase, the signal at the second selection clock signal terminal CK2 is a high-level signal, the signals at the reset signal terminal TRS, the first selection clock signal terminal CK1, the first output clock signal terminal CKE1, and the second output clock signal terminal CKE2 are low-level signals, the signal at the first selection signal terminal D0 changes from a low-level signal to a high-level signal, and the signal at any of the second selection signal terminals D1 to the eighth selection signal terminal D7 is a low-level signal. The first transistor T1, the tenth transistor T10, the sixteenth transistor T16, and the twenty-second transistor T22 are turned on, the second transistor T2 is turned off for part of the time period and turned on for part of the time period, and the time period in which the second transistor T2 is turned on occurs after the time period in which the second transistor T2 is turned off. Any of the third transistor T3 to the ninth transistor T9 is turned off, and the twelfth transistor T12, the fourteenth transistor T14, and the twenty-first transistor T21 are turned off.

[0318] The first transistor T1 is turned on, and a high-level signal of the second selection clock signal terminal CK2 or the first power supply terminal VGH is written into the first node N1, and the signal of the first node N1 is a high-level signal. The eighteenth transistor T18 and the twentieth transistor T20 are turned on, and a low-level signal of the second power supply terminal VGL is written into the first signal output terminal OUT1 and the second signal output terminal OUT2. The tenth transistor T10 is turned on, and a high-level signal of the second selection clock signal terminal CK2 is written into the second node N2, and the signal of the second node N2 is a high-level signal. The eleventh transistor T11 is turned on, and the sixteenth transistor T16 is turned on, and a low-level signal of the first selection clock signal terminal CK1 is written into the third node N3, and the signal of the third node N3 is a low-level signal. The signals of the fourth node N4 and the fifth node N5 are pulled low by the signal of the third node N3, and the fifteenth transistor T15, the seventeenth transistor T17, and the nineteenth transistor T19 are turned off. In this stage, the signals of the first node N1 and the second node N2 are high level signals, the signals of the third node N3, the fourth node N4 and the fifth node N5 are low level signals, and the signals of the first signal output terminal OUT1 and the second signal output terminal OUT2 are low level signals.

[0319] In this phase, the second transistor T2 is turned on before the signal at the second selection clock signal terminal CK2 changes from a high-level signal to a low-level signal. Therefore, the signal at the second node N2 changes with the change in the signal at the second selection clock signal terminal CK2. The sixth phase S36, referred to as the non-selection phase, is characterized by low-level signals at the second selection clock signal terminal CK2 and the reset signal terminal TRS, and a high-level signal at at least one of the first selection signal terminal D0 to the eighth selection signal terminal D7. The first transistor T1, the tenth transistor T10, and the sixteenth transistor T16 are turned off, at least one of the second transistor T2 to the ninth transistor T9 is turned on, and the twenty-second transistor T22 and the twenty-third transistor T23 are turned on.

[0320] At least one of the second to ninth transistors T2 to T9 is turned on. The low-level signal of the second selection clock signal terminal CK2 is written to the second node N2. The eleventh and thirteenth transistors T11 and T13 are turned off. The first node N1 maintains the high-level signal from the previous stage. The eighteenth and twentieth transistors T18 and T20 are turned on. The signal of the second power supply terminal VGL is written to the first signal output terminal OUT1 and the second signal output terminal OUT2. Because the eleventh transistor T11 is turned off, regardless of whether the first selection clock signal is a high-level signal or a low-level signal, the third node N3 still maintains the low-level signal from the previous stage. The signals of the fourth and fifth nodes N4 and N5 are pulled low by the signal of the third node N3. The seventeenth and nineteenth transistors T17 and T19 are turned off. The signal of the first output clock signal terminal CKE1 cannot be written to the first signal output terminal OUT1, and the signal of the second output clock signal terminal CKE2 cannot be written to the second signal output terminal OUT2.

[0321] According to the working process of the shift register provided in FIG. 26 to FIG. 28 , it can be seen that the time when the first signal output terminal OUT1 of the shift register outputs a signal is earlier than the time when the second signal output terminal OUT2 of the shift register outputs a signal.

[0322] FIG29 is an operating timing diagram of the shift register provided in FIG20 and FIG23 in the second scanning mode. The shift register in FIG29 includes twenty-one transistors (first transistor T1 to twenty-first transistor T21) and four capacitors (first capacitor C1 to fourth capacitor C4), wherein the first transistor T1 to twenty-first transistor T21 are N-type transistors.

[0323] In an exemplary embodiment, as shown in FIG. 29 , in the second scanning mode, the operation process of the shift register provided in FIG. 20 and FIG. 23 includes: a first stage S41 to a sixth stage S46 .

[0324] In the first phase S41, referred to as the reset phase, the signals at the reset signal terminal TRS and the first to eighth select signal terminals D0 to D7 are high-level signals, and the signals at the first select clock signal terminal CK1, the second select clock signal terminal CK2, the first output clock signal terminal CKE1, and the second output clock signal terminal CKE2 are low-level signals. The second to ninth transistors T2 to T9 and the twenty-first transistor T21 are turned on, while the first transistor T1, the tenth transistor T10, the twelfth transistor T12, the fourteenth transistor T14, and the sixteenth transistor T16 are turned off.

[0325] The twenty-first transistor T21 is turned on, and the signal at the third node N3 is pulled low by the low-level signal from the second power supply terminal VGL. The seventeenth transistor T17 and the nineteenth transistor T19 are turned off, and the first signal output terminal OUT1 and the second signal output terminal OUT2 are in a floating state. The second transistor T2 through the ninth transistor T9 are turned on, and the low-level signal from the second selection clock signal terminal CK2 is written to the second node N2, causing the signal at the second node N2 to be a low-level signal. The eleventh transistor T11 and the thirteenth transistor T13 are turned off, causing the signal at the first node N1 to be a low-level signal. The eighteenth transistor T18 and the twentieth transistor T20 are turned off. In this stage, the signals at the first node N1, the second node N2, and the third node N3 are all low-level signals.

[0326] In the second phase S42, referred to as the third node set phase, the signal at the second selection clock signal terminal CK2 is a high-level signal, the signals at the reset signal terminal TRS, the first selection clock signal terminal CK1, the first output clock signal terminal CKE1, and the second output clock signal terminal CKE2 are low-level signals, the signals at the first selection signal terminal D0, the third selection signal terminal D2 through the eighth selection signal terminal D7 are low-level signals, and the signal at the second selection signal terminal D1 changes from a high-level signal to a low-level signal. The first transistor T1, the tenth transistor T10, and the sixteenth transistor T16 are turned on, the second transistor T2, and any of the fourth transistor T4 through the ninth transistor T9 are turned off, the third transistor T3 is turned on for part of the time period and turned off for part of the time period, and the time when the third transistor T3 is turned on occurs before the time when the third transistor T3 is turned off, and the twelfth transistor T12, the fourteenth transistor T14, and the twenty-first transistor T21 are turned off.

[0327] The first transistor T1 is turned on, and a high-level signal from the second selection clock signal terminal CK2 or the first power supply terminal VGH is written to the first node N1, and the signal at the first node N1 is a high-level signal. The eighteenth transistor T18 and the twentieth transistor T20 are turned on, and a low-level signal from the second power supply terminal VGL is written to the first signal output terminal OUT1 and the second signal output terminal OUT2. The tenth transistor T10 is turned on, and a high-level signal from the second selection clock signal terminal CK2 or the first power supply terminal VGH is written to the second node N2, and the signal at the second node N2 is a high-level signal. The eleventh transistor T11 is turned on, and a high-level signal from the first power supply terminal VGH is written to the first electrode of the twelfth transistor T12. The thirteenth transistor T13 is turned on. The twelfth transistor T12 is turned off, and the signal from the first power supply terminal VGH cannot be written to the third node N3. The sixteenth transistor T16 is turned on, and a low-level signal from the first selection clock signal terminal CK1 is written to the third node N3, and the signal at the third node N3 is a low-level signal. The seventeenth transistor T17 and the nineteenth transistor T19 remain turned off. In this stage, the signals at the first node N1 and the second node N2 are high level signals, the signal at the third node N3 is low level signal, and the signals at the first signal output terminal OUT1 and the second signal output terminal OUT2 are low level signals.

[0328] In this stage, since the third transistor T3 is disconnected at a time point in the time period when the signal at the second selection clock signal terminal CK2 is a high-level signal, when the signal at the second selection clock signal terminal CK2 changes from a high-level signal to a low-level signal, the signal at the second node N2 will not be pulled down by the signal at the second selection clock signal terminal CK2.

[0329] After the signal at the second selection clock signal terminal CK2 changes from a high-level signal to a low-level signal, the signal at the first selection clock signal terminal CK1 remains a low-level signal for a portion of the time period. At this time, although the first transistor T1 is disconnected, the signal at the first node N1 still remains a high-level signal under the action of the first capacitor C1.

[0330] In the third phase S43, referred to as the third node set phase, the signal at the first selection clock signal terminal CK1 is a high-level signal, the signals at the reset signal terminal TRS, the second selection clock signal terminal CK2, the first output clock signal terminal CKE1, and the second output clock signal terminal CKE2 are low-level signals, and the signal at any of the first selection signal terminal D0 to the eighth selection signal terminal D7 is a low-level signal. The twelfth transistor T12 and the fourteenth transistor T14 are turned on, and the first transistor T1, the second transistor T2 to the ninth transistor T9, the tenth transistor T10, the sixteenth transistor T16, and the twenty-first transistor T21 are turned off.

[0331] Although the signal at the second selection clock signal terminal CK2 is a low-level signal, the signal at the second node N2 remains a high-level signal due to the action of the second capacitor C2. The eleventh transistor T11 is turned on, and the high-level signal at the first power supply terminal VGH is written to the third node N3 through the turned-on eleventh transistor T11 and the twelfth transistor T12. The fifteenth transistor T15, the seventeenth transistor T17, and the nineteenth transistor T19 are turned on, and the low-level signal at the first output clock signal terminal CKE1 is written to the first signal output terminal OUT1, and the low-level signal at the second output clock signal terminal CKE2 is written to the second signal output terminal OUT2. The low-level signal at the second selection clock signal terminal CK2 is written to the first node N1 through the turned-on thirteenth transistor T13 and the fourteenth transistor T14. The low-level signal at the second selection clock signal terminal CK2 is also written to the first node N1 through the turned-on fifteenth transistor T15, causing the signal at the first node N1 to be a low-level signal. The eighteenth transistor T18 and the twentieth transistor T20 are turned off. In this stage, the signal of the first node N1 is a low level signal, the signals of the second node N2 and the third node N3 are high level signals, and the signals of the first signal output terminal OUT1 and the second signal output terminal OUT2 are low level signals.

[0332] In the fourth phase S44, referred to as the output phase, the signals at the reset signal terminal TRS, the first selection clock signal terminal CK1, the second selection clock signal terminal CK2, and any of the first selection signal terminals D0 through D7 are low-level signals. The output phase comprises a first time period t1, a third time period t3, and a second time period t2, which occur sequentially. The signal at the second output clock signal terminal CKE2 is high-level in the first time period t1, and the signal at the first output clock signal terminal CKE1 is high-level in the second time period t2. The first transistor T1, the second transistor T2 through the ninth transistor T9, the tenth transistor T10, the twelfth transistor T12, the fourteenth transistor T14, the sixteenth transistor T16, and the twenty-first transistor T21 are disconnected.

[0333] The second node N2 and the third node N3 maintain the high-level signal of the previous stage, the fifteenth transistor T15 is turned on, and the low-level signal of the second selection clock signal terminal CK2 is written into the first node N1, so that the signal of the first node N1 is a low-level signal, the seventeenth transistor T17 and the nineteenth transistor T19 are turned on, the eighteenth transistor T18 and the twentieth transistor T20 are turned off, and the low-level signal of the second power supply terminal VGL cannot be written into the first signal output terminal OUT1 and the second signal output terminal OUT2.

[0334] During the first time period t1, the signal at the first output clock signal terminal CKE1 is a low-level signal, and the signal at the second output clock signal terminal CKE2 is a high-level signal. The seventeenth transistor T17 is turned on, and the low-level signal at the first output clock signal terminal CKE1 is written to the first signal output terminal OUT1. The nineteenth transistor T19 is turned on, and the high-level signal at the second output clock signal terminal CKE2 is written to the second signal output terminal OUT2. During this phase, the signal at the third node N3 is pulled high by the signal at the second signal output terminal OUT2 under the action of the fourth capacitor C4. The signal at the third node N3 remains unchanged under the action of the third capacitor C3. During this phase, the signal at the first signal output terminal OUT1 is a low-level signal, and the signal at the second signal output terminal OUT2 is a high-level signal.

[0335] During the third time period t3, the signals at the first output clock signal terminal CKE1 and the second output clock signal terminal CKE2 are low-level signals. The seventeenth transistor T17 is turned on, and the high-level signal at the first output clock signal terminal CKE1 is written to the first signal output terminal OUT1. The nineteenth transistor T19 is turned on, and the low-level signal at the second output clock signal terminal CKE2 is written to the second signal output terminal OUT2. During this phase, the signals at the first signal output terminal OUT1 and the second signal output terminal OUT2 are low-level signals.

[0336] During the second time period t2, the signal at the first output clock signal terminal CKE1 is a high-level signal, and the signal at the second output clock signal terminal CKE2 is a low-level signal. The seventeenth transistor T17 is turned on, and the high-level signal at the first output clock signal terminal CKE1 is written to the first signal output terminal OUT1. The nineteenth transistor T19 is turned on, and the low-level signal at the second output clock signal terminal CKE2 is written to the second signal output terminal OUT2. During this phase, the signal at the third node N3 is pulled high by the signal at the first signal output terminal OUT1 under the action of the third capacitor C3. The signal at the third node N3 is maintained constant by the action of the fourth capacitor C4. During this phase, the signal at the first signal output terminal OUT1 is a high-level signal, and the signal at the second signal output terminal OUT2 is a low-level signal.

[0337] In the fifth stage S45, referred to as the second and third node set stages, the signal at the second selection clock signal terminal CK2 is a high-level signal, the signals at the reset signal terminal TRS, the first selection clock signal terminal CK1, the first output clock signal terminal CKE1, and the second output clock signal terminal CKE2 are low-level signals, the signal at the first selection signal terminal D0 changes from a low-level signal to a high-level signal, and the signal at any of the second selection signal terminals D1 to the eighth selection signal terminal D7 is a low-level signal. The first transistor T1, the tenth transistor T10, and the sixteenth transistor T16 are turned on, the second transistor T2 is partially turned off and partially turned on, and the period of time during which the second transistor T2 is turned on occurs after the period during which the second transistor T2 is turned off. Any of the third transistor T3 to the ninth transistor T9 is turned off, and the twelfth transistor T12, the fourteenth transistor T14, and the twenty-first transistor T21 are turned off.

[0338] The first transistor T1 is turned on, and a high-level signal from the second selection clock signal terminal CK2 or the first power supply terminal VGH is written to the first node N1, and the signal at the first node N1 is a high-level signal. The eighteenth transistor T18 and the twentieth transistor T20 are turned on, and a low-level signal from the second power supply terminal VGL is written to the first signal output terminal OUT1 and the second signal output terminal OUT2. The tenth transistor T10 is turned on, and a high-level signal from the second selection clock signal terminal CK2 is written to the second node N2, and the signal at the second node N2 is a high-level signal. The eleventh transistor T11 is turned on, and the sixteenth transistor T16 is turned on, and a low-level signal from the first selection clock signal terminal CK1 is written to the third node N3, and the signal at the third node N3 is a low-level signal. The fifteenth transistor T15, the seventeenth transistor T17, and the nineteenth transistor T19 are turned off. In this stage, the signals at the first node N1 and the second node N2 are high-level signals, the signal at the third node N3 is a low-level signal, and the signals at the first signal output terminal OUT1 and the second signal output terminal OUT2 are low-level signals.

[0339] In this stage, the second transistor T2 is turned on before the signal at the second selection clock signal terminal CK2 changes from a high level signal to a low level signal. Therefore, the signal at the second node N2 changes with the change of the signal at the second selection clock signal terminal CK2.

[0340] In the sixth phase S46, referred to as the non-selection phase, the signals at the second selection clock signal terminal CK2 and the reset signal terminal TRS are low-level signals, and the signal at at least one of the first selection signal terminal D0 to the eighth selection signal terminal D7 is high-level signals. The first transistor T1, the tenth transistor T10, and the sixteenth transistor T16 are turned off, and at least one of the second transistor T2 to the ninth transistor T9 is turned on.

[0341] At least one of the second to ninth transistors T2 to T9 is turned on. The low-level signal of the second selection clock signal terminal CK2 is written to the second node N2. The eleventh and thirteenth transistors T11 and T13 are turned off. The first node N1 maintains the high-level signal from the previous stage. The eighteenth and twentieth transistors T18 and T20 are turned on. The signal of the second power supply terminal VGL is written to the first and second signal output terminals OUT1 and OUT2. Because the eleventh transistor T11 is turned off, regardless of whether the first selection clock signal is a high-level signal or a low-level signal, the third node N3 still maintains the low-level signal from the previous stage. The seventeenth and nineteenth transistors T17 and T19 are turned off. The signal of the first output clock signal terminal CKE1 cannot be written to the first signal output terminal OUT1, and the signal of the second output clock signal terminal CKE2 cannot be written to the second signal output terminal OUT2.

[0342] FIG30 is an operating timing diagram of the shift register provided in FIG21 and FIG24 in the second scanning mode. The shift register in FIG30 includes twenty-two transistors (first transistor T1 to twenty-second transistor T22) and four capacitors (first capacitor C1 to fourth capacitor C4), wherein the first transistor T1 to twenty-second transistor T22 are N-type transistors.

[0343] In an exemplary embodiment, as shown in FIG. 30 , in the second scanning mode, the operation process of the shift register provided in FIG. 21 and FIG. 24 includes: a first stage S51 to a sixth stage S56 .

[0344] In the first phase S51, referred to as the reset phase, the signals at the reset signal terminal TRS and the first to eighth select signal terminals D0 to D7 are high-level signals, and the signals at the first select clock signal terminal CK1, the second select clock signal terminal CK2, the first output clock signal terminal CKE1, and the second output clock signal terminal CKE2 are low-level signals. The second to ninth transistors T2 to T9, the twenty-first transistor T21, and the second second transistor T22 are turned on, while the first transistor T1, the tenth transistor T10, the twelfth transistor T12, the fourteenth transistor T14, and the sixteenth transistor T16 are turned off.

[0345] The twenty-first transistor T21 is turned on, the signal at the third node N3 is pulled low by the low-level signal from the second power supply terminal VGL, and the signal at the fourth node N4 is pulled low by the signal at the third node N3. The seventeenth transistor T17 and the nineteenth transistor T19 are turned off, and the first signal output terminal OUT1 and the second signal output terminal OUT2 are in a floating state. The second transistor T2 through the ninth transistor T9 are turned on, and the low-level signal from the second selection clock signal terminal CK2 is written to the second node N2, making the signal at the second node N2 a low-level signal. The eleventh transistor T11 and the thirteenth transistor T13 are turned off, and the signal at the first node N1 is a low-level signal. The eighteenth transistor T18 and the twentieth transistor T20 are turned off. In this stage, the signals at the first node N1, the second node N2, the third node N3, and the fourth node N4 are all low-level signals.

[0346] In the second phase S52, referred to as the third node set phase, the signal at the second selection clock signal terminal CK2 is a high-level signal, the signals at the reset signal terminal TRS, the first selection clock signal terminal CK1, the first output clock signal terminal CKE1, and the second output clock signal terminal CKE2 are low-level signals, the signals at the first selection signal terminal D0, the third selection signal terminal D2 through the eighth selection signal terminal D7 are low-level signals, and the signal at the second selection signal terminal D1 changes from a high-level signal to a low-level signal. The first transistor T1, the tenth transistor T10, the sixteenth transistor T16, and the twenty-second transistor T22 are turned on, the second transistor T2, and any of the fourth transistor T4 through the ninth transistor T9 are turned off, the third transistor T3 is turned on for part of the time period and turned off for part of the time period, and the time when the third transistor T3 is turned on occurs before the time when the third transistor T3 is turned off, and the twelfth transistor T12, the fourteenth transistor T14, and the twenty-first transistor T21 are turned off.

[0347] The first transistor T1 is turned on, and a high-level signal from the second selection clock signal terminal CK2 or the first power supply terminal VGH is written to the first node N1, and the signal at the first node N1 is a high-level signal. The eighteenth transistor T18 and the twentieth transistor T20 are turned on, and a low-level signal from the second power supply terminal VGL is written to the first signal output terminal OUT1 and the second signal output terminal OUT2. The tenth transistor T10 is turned on, and a high-level signal from the second selection clock signal terminal CK2 is written to the second node N2, and the signal at the second node N2 is a high-level signal. The eleventh transistor T11 is turned on, and a high-level signal from the first power supply terminal VGH is written to the first electrode of the twelfth transistor T12. The thirteenth transistor T13 is turned on. Since the twelfth transistor T12 is turned off, the signal from the first power supply terminal VGH cannot be written to the third node N3. The sixteenth transistor T16 is turned on, and a low-level signal from the first selection clock signal terminal CK1 is written to the third node N3, and the signal at the third node N3 is a low-level signal. The signal at the fourth node N4 also remains a low-level signal. The seventeenth transistor T17 and the nineteenth transistor T19 remain turned off. In this stage, the signals of the first node N1 and the second node N2 are high level signals, the signals of the third node N3 and the fourth node N4 are low level signals, and the signals of the first signal output terminal OUT1 and the second signal output terminal OUT2 are low level signals.

[0348] In this stage, since the third transistor T3 is disconnected at a time point in the time period when the signal at the second selection clock signal terminal CK2 is a high-level signal, when the signal at the second selection clock signal terminal CK2 changes from a high-level signal to a low-level signal, the signal at the second node N2 will not be pulled down by the signal at the second selection clock signal terminal CK2.

[0349] After the signal at the second selection clock signal terminal CK2 changes from a high-level signal to a low-level signal, the signal at the first selection clock signal terminal CK1 remains a low-level signal for a portion of the time period. At this time, although the first transistor T1 is disconnected, the signal at the first node N1 still remains a high-level signal under the action of the first capacitor C1.

[0350] In the third phase S53, referred to as the third node set phase, the signal at the first selection clock signal terminal CK1 is a high-level signal, the signals at the reset signal terminal TRS, the second selection clock signal terminal CK2, the first output clock signal terminal CKE1, and the second output clock signal terminal CKE2 are low-level signals, and the signal at any of the first selection signal terminals D0 to the eighth selection signal terminal D7 is a low-level signal. The twelfth transistor T12, the fourteenth transistor T14, and the twenty-second transistor T22 are turned on, and the first transistor T1, the second transistor T2 to the ninth transistor T9, the tenth transistor T10, the sixteenth transistor T16, and the twenty-first transistor T21 are turned off.

[0351] Although the signal at the second selection clock signal terminal CK2 is a low-level signal, the signal at the second node N2 remains a high-level signal due to the action of the second capacitor C2. The eleventh transistor T11 is turned on, and the high-level signal at the first power supply terminal VGH is written to the third node N3 through the turned-on eleventh transistor T11 and the twelfth transistor T12. The fifteenth transistor T15 is turned on, and the signal at the fourth node N4 is pulled high by the signal at the third node N3. The seventeenth transistor T17 and the nineteenth transistor T19 are turned on, and the low-level signal at the first output clock signal terminal CKE1 is written to the first signal output terminal OUT1, and the low-level signal at the second output clock signal terminal CKE2 is written to the second signal output terminal OUT2. The low-level signal at the second selection clock signal terminal CK2 is written to the first node N1 through the turned-on thirteenth transistor T13 and the fourteenth transistor T14. The low-level signal at the second selection clock signal terminal CK2 is also written to the first node N1 through the turned-on fifteenth transistor T15, causing the signal at the first node N1 to be a low-level signal. The eighteenth transistor T18 and the twentieth transistor T20 are turned off. In this stage, the signal of the first node N1 is a low level signal, the signals of the second node N2, the third node N3 and the fourth node N4 are high level signals, and the signals of the first signal output terminal OUT1 and the second signal output terminal OUT2 are low level signals.

[0352] In the fourth phase S54, referred to as the output phase, the signals at the reset signal terminal TRS, the first selection clock signal terminal CK1, the second selection clock signal terminal CK2, and any of the first selection signal terminals D0 through D7 are low-level signals. The output phase comprises a first time period t1, a third time period t3, and a second time period t2, which occur sequentially. The signal at the second output clock signal terminal CKE2 is high-level in the first time period t1, and the signal at the first output clock signal terminal CKE1 is high-level in the second time period t2. The twenty-second transistor T22 is turned on, while the first transistor T1, the second transistor T2 through the ninth transistor T9, the tenth transistor T10, the twelfth transistor T12, the fourteenth transistor T14, the sixteenth transistor T16, and the twenty-first transistor T21 are turned off.

[0353] The second node N2, the third node N3 and the fourth node N4 maintain the high-level signal of the previous stage, the fifteenth transistor T15 is turned on, and the low-level signal of the second selection clock signal terminal CK2 is written into the first node N1, so that the signal of the first node N1 is a low-level signal, the seventeenth transistor T17 and the nineteenth transistor T19 are turned on, the eighteenth transistor T18 and the twentieth transistor T20 are turned off, and the low-level signal of the second power supply terminal VGL cannot be written into the first signal output terminal OUT1 and the second signal output terminal OUT2.

[0354] During the first time period t1, the signal at the first output clock signal terminal CKE1 is a low-level signal, and the signal at the second output clock signal terminal CKE2 is a high-level signal. The seventeenth transistor T17 is turned on, and the low-level signal at the first output clock signal terminal CKE1 is written to the first signal output terminal OUT1. The nineteenth transistor T19 is turned on, and the high-level signal at the second output clock signal terminal CKE2 is written to the second signal output terminal OUT2. During this phase, the signal at the fourth node N4 is pulled high by the signal at the second signal output terminal OUT2 under the action of the fourth capacitor C4. The signal at the fourth node N4 remains unchanged under the action of the third capacitor C3. During this phase, the signal at the first signal output terminal OUT1 is a low-level signal, and the signal at the second signal output terminal OUT2 is a high-level signal.

[0355] During the third time period t3, the signals at the first output clock signal terminal CKE1 and the second output clock signal terminal CKE2 are low-level signals. The seventeenth transistor T17 is turned on, and the high-level signal at the first output clock signal terminal CKE1 is written to the first signal output terminal OUT1. The nineteenth transistor T19 is turned on, and the low-level signal at the second output clock signal terminal CKE2 is written to the second signal output terminal OUT2. During this phase, the signals at the first signal output terminal OUT1 and the second signal output terminal OUT2 are low-level signals.

[0356] During the second time period t2, the signal at the first output clock signal terminal CKE1 is a high-level signal, and the signal at the second output clock signal terminal CKE2 is a low-level signal. The seventeenth transistor T17 is turned on, and the high-level signal at the first output clock signal terminal CKE1 is written to the first signal output terminal OUT1. The nineteenth transistor T19 is turned on, and the low-level signal at the second output clock signal terminal CKE2 is written to the second signal output terminal OUT2. During this phase, the signal at the fourth node N4 is pulled high by the signal at the first signal output terminal OUT1 under the action of the third capacitor C3. The signal at the fourth node N4 is maintained unchanged by the action of the fourth capacitor C4. During this phase, the signal at the first signal output terminal OUT1 is a high-level signal, and the signal at the second signal output terminal OUT2 is a low-level signal.

[0357] In the fifth stage S55, referred to as the second and third node set stages, the signal at the second selection clock signal terminal CK2 is a high-level signal, the signals at the reset signal terminal TRS, the first selection clock signal terminal CK1, the first output clock signal terminal CKE1, and the second output clock signal terminal CKE2 are low-level signals, the signal at the first selection signal terminal D0 changes from a low-level signal to a high-level signal, and the signal at any of the second selection signal terminals D1 to the eighth selection signal terminal D7 is a low-level signal. The first transistor T1, the tenth transistor T10, the sixteenth transistor T16, and the twenty-second transistor T22 are turned on, the second transistor T2 is partially turned off and partially turned on, and the period of time during which the second transistor T2 is turned on occurs after the period during which the second transistor T2 is turned off. Any of the third transistor T3 to the ninth transistor T9 is turned off, and the twelfth transistor T12, the fourteenth transistor T14, and the twenty-first transistor T21 are turned off.

[0358] The first transistor T1 is turned on, and a high-level signal from the second selection clock signal terminal CK2 or the first power supply terminal VGH is written to the first node N1, and the signal at the first node N1 is a high-level signal. The eighteenth transistor T18 and the twentieth transistor T20 are turned on, and a low-level signal from the second power supply terminal VGL is written to the first signal output terminal OUT1 and the second signal output terminal OUT2. The tenth transistor T10 is turned on, and a high-level signal from the second selection clock signal terminal CK2 is written to the second node N2, and the signal at the second node N2 is a high-level signal. The eleventh transistor T11 is turned on, and the sixteenth transistor T16 is turned on, and a low-level signal from the first selection clock signal terminal CK1 is written to the third node N3, and the signal at the third node N3 is a low-level signal. The signal at the fourth node N4 is pulled low by the signal at the third node N3. The fifteenth transistor T15, the seventeenth transistor T17, and the nineteenth transistor T19 are turned off. In this stage, the signals at the first node N1 and the second node N2 are high-level signals, the signals at the third node N3 and the fourth node N4 are low-level signals, and the signals at the first signal output terminal OUT1 and the second signal output terminal OUT2 are low-level signals.

[0359] In this stage, the second transistor T2 is turned on before the signal at the second selection clock signal terminal CK2 changes from a high level signal to a low level signal. Therefore, the signal at the second node N2 changes with the change of the signal at the second selection clock signal terminal CK2.

[0360] In the sixth phase S56, referred to as the non-selection phase, the signals at the second selection clock signal terminal CK2 and the reset signal terminal TRS are low-level signals, and the signal at at least one of the first selection signal terminal D0 to the eighth selection signal terminal D7 is high-level signals. The first transistor T1, the tenth transistor T10, and the sixteenth transistor T16 are turned off, at least one of the second transistor T2 to the ninth transistor T9 is turned on, and the twenty-second transistor T22 is turned on.

[0361] At least one of the second to ninth transistors T2 to T9 is turned on. The low-level signal of the second selection clock signal terminal CK2 is written to the second node N2. The eleventh and thirteenth transistors T11 and T13 are turned off. The first node N1 maintains the high-level signal from the previous stage. The eighteenth and twentieth transistors T18 and T20 are turned on. The signal of the second power supply terminal VGL is written to the first signal output terminal OUT1 and the second signal output terminal OUT2. Because the eleventh transistor T11 is turned off, regardless of whether the first selection clock signal is a high-level signal or a low-level signal, the third node N3 still maintains the low-level signal from the previous stage. The signal of the fourth node N4 is pulled low by the signal of the third node N3. The seventeenth and nineteenth transistors T17 and T19 are turned off. The signal of the first output clock signal terminal CKE1 cannot be written to the first signal output terminal OUT1, and the signal of the second output clock signal terminal CKE2 cannot be written to the second signal output terminal OUT2.

[0362] FIG31 is an operating timing diagram of the shift register provided in FIG22 and FIG25 in the second scanning mode. The shift register in FIG22 and FIG25 includes twenty-three transistors (first transistor T1 to twenty-third transistor T23) and four capacitors (first capacitor C1 to fourth capacitor C4), wherein the first transistor T1 to the twenty-third transistor T23 are N-type transistors.

[0363] In an exemplary embodiment, as shown in FIG. 31 , in the second scanning mode, the operation process of the shift register provided in FIG. 22 and FIG. 25 includes: a first stage S61 to a sixth stage S66 .

[0364] In the first phase S61, referred to as the reset phase, the signals at the reset signal terminal TRS and the first to eighth selection signal terminals D0 to D7 are high-level signals, and the signals at the first selection clock signal terminal CK1, the second selection clock signal terminal CK2, the first output clock signal terminal CKE1, and the second output clock signal terminal CKE2 are low-level signals. The second to ninth transistors T2 to T9, the twenty-first transistor T21, the twenty-second transistor T22, and the twenty-third transistor T23 are turned on, while the first transistor T1, the tenth transistor T10, the twelfth transistor T12, the fourteenth transistor T14, and the sixteenth transistor T16 are turned off.

[0365] The twenty-first transistor T21 is turned on, the signal at the third node N3 is pulled low by the low-level signal from the second power supply terminal VGL, the signals at the fourth node N4 and the fifth node N5 are pulled low by the signal from the third node N3, the seventeenth transistor T17 and the nineteenth transistor T19 are turned off, and the first signal output terminal OUT1 and the second signal output terminal OUT2 are in a floating state. The second through ninth transistors T2 to T9 are turned on, the low-level signal from the second selection clock signal terminal CK2 is written to the second node N2, and the signal at the second node N2 is a low-level signal. The eleventh transistor T11 and the thirteenth transistor T13 are turned off, the signal at the first node N1 is a low-level signal, and the eighteenth transistor T18 and the twentieth transistor T20 are turned off. In this stage, the signals at the first node N1, the second node N2, the third node N3, the fourth node N4, and the fifth node N5 are all low-level signals.

[0366] In the second phase S62, referred to as the third node set phase, the signal at the second selection clock signal terminal CK2 is a high-level signal, the signals at the reset signal terminal TRS, the first selection clock signal terminal CK1, the first output clock signal terminal CKE1, and the second output clock signal terminal CKE2 are low-level signals, the signals at the first selection signal terminal D0, the third selection signal terminal D2 to the eighth selection signal terminal D7 are low-level signals, and the signal at the second selection signal terminal D1 changes from a high-level signal to a low-level signal. The first transistor T1, the tenth transistor T10, the sixteenth transistor T16, the twenty-second transistor T22, and the twenty-third transistor T23 are turned on, the second transistor T2, and any of the fourth transistor T4 to the ninth transistor T9 are turned off, the third transistor T3 is turned on for part of the time period and turned off for part of the time period, and the time when the third transistor T3 is turned on occurs before the time when the third transistor T3 is turned off, and the twelfth transistor T12, the fourteenth transistor T14, and the twenty-first transistor T21 are turned off.

[0367] The first transistor T1 is turned on, and a high-level signal from the second selection clock signal terminal CK2 or the first power supply terminal VGH is written to the first node N1, and the signal at the first node N1 is a high-level signal. The eighteenth transistor T18 and the twentieth transistor T20 are turned on, and a low-level signal from the second power supply terminal VGL is written to the first signal output terminal OUT1 and the second signal output terminal OUT2. The tenth transistor T10 is turned on, and a high-level signal from the second selection clock signal terminal CK2 is written to the second node N2, and the signal at the second node N2 is a high-level signal. The eleventh transistor T11 is turned on, and a high-level signal from the first power supply terminal VGH is written to the first electrode of the twelfth transistor T12. The thirteenth transistor T13 is turned on. Since the twelfth transistor T12 is turned off, the signal from the first power supply terminal VGH cannot be written to the third node N3. The sixteenth transistor T16 is turned on, and a low-level signal from the first selection clock signal terminal CK1 is written to the third node N3, and the signal at the third node N3 is a low-level signal. The signals at the fourth node N4 and the fifth node N5 also remain low-level signals. The seventeenth transistor T17 and the nineteenth transistor T19 remain turned off. In this stage, the signals of the first node N1 and the second node N2 are high level signals, the signals of the third node N3, the fourth node N4 and the fifth node N5 are low level signals, and the signals of the first signal output terminal OUT1 and the second signal output terminal OUT2 are low level signals.

[0368] In this stage, since any one of the third transistors T3 is disconnected at a time point in the time period when the signal at the second selection clock signal terminal CK2 is a high-level signal, when the signal at the second selection clock signal terminal CK2 changes from a high-level signal to a low-level signal, the signal at the second node N2 will not be pulled down by the signal at the second selection clock signal terminal CK2.

[0369] After the signal at the second selection clock signal terminal CK2 changes from a high-level signal to a low-level signal, the signal at the first selection clock signal terminal CK1 remains a low-level signal for a portion of the time period. At this time, although the first transistor T1 is disconnected, the signal at the first node N1 still remains a high-level signal under the action of the first capacitor C1.

[0370] In the third phase S63, referred to as the third node set phase, the signal at the first selection clock signal terminal CK1 is a high-level signal, the signals at the reset signal terminal TRS, the second selection clock signal terminal CK2, the first output clock signal terminal CKE1, and the second output clock signal terminal CKE2 are low-level signals, and the signal at any of the first selection signal terminal D0 to the eighth selection signal terminal D7 is a low-level signal. The twelfth transistor T12, the fourteenth transistor T14, the twenty-second transistor T22, and the twenty-third transistor T23 are turned on, and the first transistor T1, the second transistor T2 to the ninth transistor T9, the tenth transistor T10, the sixteenth transistor T16, and the twenty-first transistor T21 are turned off.

[0371] Although the signal at the second selection clock signal terminal CK2 is a low-level signal, the signal at the second node N2 remains a high-level signal due to the action of the second capacitor C2. The eleventh transistor T11 is turned on, and the high-level signal at the first power supply terminal VGH is written to the third node N3 through the turned-on eleventh transistor T11 and the twelfth transistor T12. The fifteenth transistor T15 is turned on, and the signals at the fourth node N4 and the fifth node N5 are pulled high by the signal at the third node N3. The seventeenth transistor T17 and the nineteenth transistor T19 are turned on, and the low-level signal at the first output clock signal terminal CKE1 is written to the first signal output terminal OUT1, and the low-level signal at the second output clock signal terminal CKE2 is written to the second signal output terminal OUT2. The low-level signal at the second selection clock signal terminal CK2 is written to the first node N1 through the turned-on thirteenth transistor T13 and the fourteenth transistor T14. The low-level signal at the second selection clock signal terminal CK2 is also written to the first node N1 through the turned-on fifteenth transistor T15, causing the signal at the first node N1 to be a low-level signal. The eighteenth transistor T18 and the twentieth transistor T20 are turned off. In this stage, the signal of the first node N1 is a low level signal, the signals of the second node N2, the third node N3, the fourth node N4 and the fifth node N5 are high level signals, and the signals of the first signal output terminal OUT1 and the second signal output terminal OUT2 are low level signals.

[0372] In the fourth phase S64, referred to as the output phase, the signals at the reset signal terminal TRS, the first selection clock signal terminal CK1, the second selection clock signal terminal CK2, and any of the first selection signal terminals D0 through D7 are low-level signals. The output phase comprises a first time period t1, a third time period t3, and a second time period t2, which occur sequentially. The signal at the second output clock signal terminal CKE2 is high-level in the first time period t1, and the signal at the first output clock signal terminal CKE1 is high-level in the second time period t2. The twenty-second transistor T22 and the twenty-third transistor T23 are turned on, while the first transistor T1, the second transistor T2 through the ninth transistor T9, the tenth transistor T10, the twelfth transistor T12, the fourteenth transistor T14, the sixteenth transistor T16, and the twenty-first transistor T21 are turned off.

[0373] The second node N2, the third node N3, the fourth node N4 and the fifth node N5 maintain the high-level signal of the previous stage, the fifteenth transistor T15 is turned on, and the low-level signal of the second selection clock signal terminal CK2 is written into the first node N1, so that the signal of the first node N1 is a low-level signal, the seventeenth transistor T17 and the nineteenth transistor T19 are turned on, the eighteenth transistor T18 and the twentieth transistor T20 are turned off, and the low-level signal of the second power supply terminal VGL cannot be written into the first signal output terminal OUT1 and the second signal output terminal OUT2.

[0374] During the first time period t1, the signal at the first output clock signal terminal CKE1 is a low-level signal, and the signal at the second output clock signal terminal CKE2 is a high-level signal. The seventeenth transistor T17 is turned on, and the low-level signal at the first output clock signal terminal CKE1 is written to the first signal output terminal OUT1. The nineteenth transistor T19 is turned on, and the high-level signal at the second output clock signal terminal CKE2 is written to the second signal output terminal OUT2. During this phase, the signal at the fifth node N5 is pulled high by the signal at the second signal output terminal OUT2 under the action of the fourth capacitor C4. During this phase, the signal at the first signal output terminal OUT1 is a low-level signal, and the signal at the second signal output terminal OUT2 is a high-level signal.

[0375] During the third time period t3, the signals at the first output clock signal terminal CKE1 and the second output clock signal terminal CKE2 are low-level signals. The seventeenth transistor T17 is turned on, and the high-level signal at the first output clock signal terminal CKE1 is written to the first signal output terminal OUT1. The nineteenth transistor T19 is turned on, and the low-level signal at the second output clock signal terminal CKE2 is written to the second signal output terminal OUT2. During this phase, the signals at the first signal output terminal OUT1 and the second signal output terminal OUT2 are low-level signals.

[0376] During the second time period t2, the signal at the first output clock signal terminal CKE1 is a high-level signal, and the signal at the second output clock signal terminal CKE2 is a low-level signal. The seventeenth transistor T17 is turned on, and the high-level signal at the first output clock signal terminal CKE1 is written to the first signal output terminal OUT1. The nineteenth transistor T19 is turned on, and the low-level signal at the second output clock signal terminal CKE2 is written to the second signal output terminal OUT2. During this phase, the signal at the fourth node N4 is pulled high by the signal at the first signal output terminal OUT1 under the action of the third capacitor C3. During this phase, the signal at the first signal output terminal OUT1 is a high-level signal, and the signal at the second signal output terminal OUT2 is a low-level signal.

[0377] In the fifth stage S65, referred to as the second and third node set stages, the signal at the second selection clock signal terminal CK2 is a high-level signal, the signals at the reset signal terminal TRS, the first selection clock signal terminal CK1, the first output clock signal terminal CKE1, and the second output clock signal terminal CKE2 are low-level signals, the signal at the first selection signal terminal D0 changes from a low-level signal to a high-level signal, and the signal at any of the second selection signal terminals D1 to the eighth selection signal terminal D7 is a low-level signal. The first transistor T1, the tenth transistor T10, the sixteenth transistor T16, and the twenty-second transistor T22 are turned on, the second transistor T2 is turned off for a portion of the time period and turned on for a portion of the time period, and the time period in which the second transistor T2 is turned on occurs after the time period in which the second transistor T2 is turned off. Any of the third transistor T3 to the ninth transistor T9 is turned off, and the twelfth transistor T12, the fourteenth transistor T14, and the twenty-first transistor T21 are turned off.

[0378] The first transistor T1 is turned on, and a high-level signal of the second selection clock signal terminal CK2 or the first power supply terminal VGH is written into the first node N1, and the signal of the first node N1 is a high-level signal. The eighteenth transistor T18 and the twentieth transistor T20 are turned on, and a low-level signal of the second power supply terminal VGL is written into the first signal output terminal OUT1 and the second signal output terminal OUT2. The tenth transistor T10 is turned on, and a high-level signal of the second selection clock signal terminal CK2 is written into the second node N2, and the signal of the second node N2 is a high-level signal. The eleventh transistor T11 is turned on, and the sixteenth transistor T16 is turned on, and a low-level signal of the first selection clock signal terminal CK1 is written into the third node N3, and the signal of the third node N3 is a low-level signal. The signals of the fourth node N4 and the fifth node N5 are pulled low by the signal of the third node N3, and the fifteenth transistor T15, the seventeenth transistor T17, and the nineteenth transistor T19 are turned off. In this stage, the signals of the first node N1 and the second node N2 are high level signals, the signals of the third node N3, the fourth node N4 and the fifth node N5 are low level signals, and the signals of the first signal output terminal OUT1 and the second signal output terminal OUT2 are low level signals.

[0379] In this stage, the second transistor T2 is turned on before the signal at the second selection clock signal terminal CK2 changes from a high level signal to a low level signal. Therefore, the signal at the second node N2 changes with the change of the signal at the second selection clock signal terminal CK2.

[0380] In the sixth phase S66, referred to as the non-selection phase, the signals at the second selection clock signal terminal CK2 and the reset signal terminal TRS are low-level signals, and the signal at at least one of the first selection signal terminal D0 to the eighth selection signal terminal D7 is high-level signals. The first transistor T1, the tenth transistor T10, and the sixteenth transistor T16 are turned off, at least one of the second transistor T2 to the ninth transistor T9 is turned on, and the twenty-second transistor T22 and the twenty-third transistor T23 are turned on.

[0381] At least one of the second to ninth transistors T2 to T9 is turned on. The low-level signal of the second selection clock signal terminal CK2 is written to the second node N2. The eleventh and thirteenth transistors T11 and T13 are turned off. The first node N1 maintains the high-level signal from the previous stage. The eighteenth and twentieth transistors T18 and T20 are turned on. The signal of the second power supply terminal VGL is written to the first signal output terminal OUT1 and the second signal output terminal OUT2. Because the eleventh transistor T11 is turned off, regardless of whether the first selection clock signal is a high-level signal or a low-level signal, the third node N3 still maintains the low-level signal from the previous stage. The signals of the fourth and fifth nodes N4 and N5 are pulled low by the signal of the third node N3. The seventeenth and nineteenth transistors T17 and T19 are turned off. The signal of the first output clock signal terminal CKE1 cannot be written to the first signal output terminal OUT1, and the signal of the second output clock signal terminal CKE2 cannot be written to the second signal output terminal OUT2.

[0382] According to the working process of the shift register provided in FIG. 29 to FIG. 31 , it can be seen that the time when the first signal output terminal OUT1 of the shift register outputs a signal is later than the time when the second signal output terminal OUT2 of the shift register outputs a signal.

[0383] An embodiment of the present disclosure further provides a shift register driving method, which is configured to drive the shift register provided by any of the aforementioned embodiments. The shift register driving method may include:

[0384] Step S100, under the control of the first selection clock signal terminal, the second selection clock signal terminal and the signal of the second node, the node control subcircuit provides the signal of the first power supply terminal or the second selection clock signal terminal to the first node, provides the signal of the second selection clock signal terminal to the second node, and provides the signal of the first power supply terminal or the first selection clock signal terminal to the third node.

[0385] Step S200: The decoding sub-circuit provides a signal from a second selection clock signal terminal to a second node under the control of a signal from at least one selection signal terminal.

[0386] Step S300: Under the control of the signals of the first node and the third node, the output control subcircuit provides a signal of the first output clock signal terminal or the second power supply terminal to the first signal output terminal, and provides a signal of the second output clock signal terminal or the second power supply terminal to the second signal output terminal.

[0387] Figure 32 is a schematic diagram of the structure of a display device, and Figure 33 is a schematic diagram of the connection of a gate drive circuit. As shown in Figures 32 and 33, embodiments of the present disclosure also provide a display device having a display area AA and a non-display area AA'. The display area AA is provided with array-arranged sub-pixels Px, and the non-display area AA' is provided with a gate drive circuit 100. The gate drive circuit 100 includes: a plurality of shift registers provided by any of the aforementioned embodiments. The first signal output terminal OUT1 of at least one shift register is electrically connected to at least one row of sub-pixels, and the second signal output terminal OUT2 of at least one shift register is electrically connected to at least one row of sub-pixels.

[0388] In an exemplary embodiment, the gate driving circuit 100 may be located on at least one side of the display area AA. FIG32 illustrates an example in which the gate driving circuit 100 is located on two opposite sides of the display area 200. This disclosure does not limit this.

[0389] In an exemplary embodiment, the number of rows of sub-pixels driven by a shift register depends on the number of selection signal terminals, the number of signal output terminals of the shift register, and the shifting method of the first selection clock signal terminal and the second selection clock signal terminal. In the present disclosure, when the selection sub-circuit in at least one shift register includes 8 transistors, the shift register is connected to two rows of sub-pixels, and combined with the shifting of the first selection clock signal terminal and the second selection clock signal terminal, a gate drive circuit including multiple shift registers can independently drive 2*2*(2^8)=1024 rows of sub-pixels. If the number of rows of independently operating sub-pixels is to be increased, the number of transistors included in the selection sub-circuit or the number of output terminals can be increased.

[0390] When the number of rows of independently working sub-pixels is increased by increasing the number of transistors included in the gating sub-circuit, the number of rows of independently working sub-pixels that can be driven by the gate drive circuit including multiple shift registers is doubled for each new transistor added to the gating sub-circuit. For example, when the gating sub-circuit includes 9 transistors, the gate drive circuit including multiple shift registers can achieve independent driving of 2*2*(2^9)=2048 rows of sub-pixels. The number of rows of independently working sub-pixels driven by the gate drive circuit including 9 transistors in the gating sub-circuit is twice the number of rows of independently working sub-pixels driven by the gate drive circuit including 8 transistors in the gating sub-circuit. Exemplarily, the gating sub-circuit may also include 10 transistors, and the number of rows of independently working sub-pixels driven by the gate drive circuit including 10 transistors in the gating sub-circuit is twice the number of rows of independently working sub-pixels driven by the gate drive circuit including 9 transistors in the gating sub-circuit.

[0391] In an exemplary embodiment, the first signal output terminal OUT1 of the nth shift register is electrically connected to the sub-pixels in the 2n-1th row, and the second signal output terminal OUT2 of the nth shift register is electrically connected to the sub-pixels in the 2nth row, where 1≤n≤N, and N is the total number of shift registers. For example, the first signal output terminal OUT1 of the first shift register GOA (1) is electrically connected to the sub-pixel R (1) in the first row, the second signal output terminal OUT2 of the first shift register GOA (1) is electrically connected to the sub-pixel R (2) in the second row, the first signal output terminal OUT1 of the second shift register GOA (2) is electrically connected to the sub-pixel R (3) in the third row, the second signal output terminal OUT2 of the second shift register GOA (2) is electrically connected to the sub-pixel R (4) in the fourth row, and so on. The first signal output terminal OUT1 of the 511th shift register GOA (511) is electrically connected to the sub-pixel R (1021) in the 1021st row, and the second signal output terminal OUT2 of the 511th shift register GOA (511) is electrically connected to the sub-pixel R (1022) in the 1022nd row.

[0392] In an exemplary embodiment, FIG34 is a timing diagram of multiple strobe signal lines. As shown in FIG33 and FIG34 , the non-display area is further provided with a strobe signal line group. The strobe signal line group includes: multiple strobe signal lines. Multiple strobe signal terminals in at least one shift register are electrically connected to some of the strobe signal lines in the strobe signal line group. Figures 33 and 34 are explained by taking the sixteen selection signal lines, namely the first selection signal line DL0, the second selection signal line DLN0, the third selection signal line DL1, the fourth selection signal line DLN1, the fifth selection signal line DL2, the sixth selection signal line DLN2, the seventh selection signal line DL3, the eighth selection signal line DLN3, the ninth selection signal line DL4, the tenth selection signal line DLN4, the eleventh selection signal line DL5, the twelfth selection signal line DLN5, the thirteenth selection signal line DL6, the fourteenth selection signal line DLN6, the fifteenth selection signal line DL7 and the sixteenth selection signal line DLN7 as examples.

[0393] In an exemplary embodiment, the shift register includes: M selection signal terminals, and the selection signal line group includes: 2M selection signal lines; the mth selection signal terminal is electrically connected to one of the 2m-1th selection signal line and the 2mth selection signal line. Taking M=8 as an example, as shown in FIG33, the first selection signal terminal D0 is electrically connected to the first selection signal line DL0 or the second selection signal line DLN0, the second selection signal terminal D1 is electrically connected to the third selection signal line DL1 or the fourth selection signal line DLN1, the third selection signal terminal D2 is electrically connected to the fifth selection signal line DL2 or the sixth selection signal line DLN2, and the fourth selection signal terminal D3 is electrically connected to the seventh selection signal line DL3 or the eighth selection signal line DLN3. The fifth selection signal terminal D4 is electrically connected to the ninth selection signal line DL4 or the tenth selection signal line DLN4, the sixth selection signal terminal D5 is electrically connected to the eleventh selection signal line DL5 or the twelfth selection signal line DLN5, the seventh selection signal terminal D6 is electrically connected to the thirteenth selection signal line DL6 or the fourteenth selection signal line DLN6, and the eighth selection signal terminal D7 is electrically connected to the fifteenth selection signal line DL7 or the sixteenth selection signal line DLN7.

[0394] In an exemplary embodiment, as shown in FIG. 34 , the frequencies of the signals of the first to eighth selection signal terminals D0 to D7 may sequentially decrease, ie, the signal pulses of the first to eighth selection signal terminals D0 to D7 may sequentially increase. Illustratively, the signal frequency of the selection signal at the first selection signal terminal D0 is the highest, the signal frequency of the selection signal at the second selection signal terminal D1 is half of the signal frequency of the selection signal at the first selection signal terminal D0, the signal frequency of the selection signal at the third selection signal terminal D2 is half of the signal frequency of the selection signal at the second selection signal terminal D1, the signal frequency of the selection signal at the fourth selection signal terminal D3 is half of the signal frequency of the selection signal at the third selection signal terminal D2, the signal frequency of the selection signal at the fifth selection signal terminal D4 is half of the signal frequency of the selection signal at the fourth selection signal terminal D3, the signal frequency of the selection signal at the sixth selection signal terminal D5 is half of the signal frequency of the selection signal at the fifth selection signal terminal D4, the signal frequency of the selection signal at the seventh selection signal terminal D6 is half of the signal frequency of the selection signal at the sixth selection signal terminal D5, and the signal frequency of the selection signal at the eighth selection signal terminal D7 is half of the signal frequency of the selection signal at the seventh selection signal terminal D6. The signal pulse width of the selection signal at the first selection signal terminal D0 is the smallest, the signal pulse width of the selection signal at the second selection signal terminal D1 is twice the signal pulse width of the selection signal at the first selection signal terminal D0, the signal pulse width of the selection signal at the third selection signal terminal D2 is twice the signal pulse width of the selection signal at the second selection signal terminal D1, the signal pulse width of the selection signal at the fourth selection signal terminal D3 is twice the signal pulse width of the selection signal at the third selection signal terminal D2, and the signal pulse width of the selection signal at the fifth selection signal terminal D4 is twice the signal pulse width of the selection signal at the fifth selection signal terminal D5. The signal pulse width of the selection signal is twice the signal pulse width of the selection signal at the fourth selection signal terminal D3, the signal pulse width of the selection signal at the sixth selection signal terminal D5 is twice the signal pulse width of the selection signal at the fifth selection signal terminal D4, the signal pulse width of the selection signal at the seventh selection signal terminal D6 is twice the signal pulse width of the selection signal at the sixth selection signal terminal D5, and the signal pulse width of the selection signal at the eighth selection signal terminal D7 is twice the signal pulse width of the selection signal at the seventh selection signal terminal D6.

[0395] In an exemplary embodiment, signals of at least two gate signal lines are inverted signals to each other during a partial period.

[0396] In an exemplary embodiment, the non-display area is further provided with a clock signal line group, the clock signal line group including a plurality of clock signal lines. At least one of a first output clock signal terminal, a second output clock signal terminal, a first selection clock signal terminal, and a second selection clock signal terminal in at least one shift register is electrically connected to one of the plurality of clock signal terminals.

[0397] In an exemplary embodiment, as shown in FIG. 33 , the plurality of clock signal lines include a first selection clock signal line CLK1 , a second selection clock signal line CLK2 , a first output clock signal line CLKE1 , a second output clock signal line CLKE2 , a third output clock signal line, and a fourth output clock signal line CLKE4 .

[0398] In an exemplary embodiment, the first selection clock signal terminal CK1 of at least one shift register is electrically connected to one of the first selection clock signal line CLK1 and the second selection clock signal line CLK2, and the second selection clock signal terminal CK2 of at least one shift register is electrically connected to the other of the first selection clock signal line CLK1 and the second selection clock signal line CLK2. The first selection clock signal terminals of adjacent shift registers are connected to different signal lines, and the second selection clock signal terminals of adjacent shift registers are connected to different signal lines. Specifically, the first selection clock signal terminal CK1 of the 2n-1th shift register is electrically connected to the first selection clock signal line CLK1, the second selection clock signal terminal CK2 of the 2n-1th shift register is electrically connected to the second selection clock signal line CLK2, the first selection clock signal terminal CK1 of the 2nth shift register is electrically connected to the second selection clock signal line CLK2, and the second selection clock signal terminal CK2 of the 2nth shift register is electrically connected to the first selection clock signal line CLK1. For example, as shown in FIG33 , the first selection clock signal terminal CK1 of the first shift register GOA (1) is electrically connected to the first selection clock signal line CLK1, the second selection clock signal terminal CK2 of the first shift register GOA (1) is electrically connected to the second selection clock signal line CLK2, the first selection clock signal terminal CK1 of the second shift register GOA (2) is electrically connected to the second selection clock signal line CLK2, the second selection clock signal terminal CK2 of the second shift register GOA (2) is electrically connected to the first selection clock signal line CLK1, and so on. The first selection clock signal terminal CK1 of the 511th shift register GOA (511) is electrically connected to the second selection clock signal line CLK2, the second selection clock signal terminal CK2 of the 511th shift register GOA (511) is electrically connected to the first selection clock signal line CLK1, and so on.

[0399] In an exemplary embodiment, as shown in FIG33 , the first output clock signal terminal CKE1 of at least one shift register is electrically connected to the first output clock signal line CLKE1, and the second output clock signal terminal CKE2 of at least one shift register is electrically connected to the second output clock signal line CLKE2. Alternatively, the first output clock signal terminal CKE1 of at least one shift register is electrically connected to the third output clock signal line CLKE3, and the second output clock signal terminal CKE2 of at least one shift register is electrically connected to the fourth output clock signal line CLKE4. Adjacent shift registers have their first output clock signal terminals CKE1 connected to different signal lines, and their second output clock signal terminals CKE2 connected to different signal lines. Among them, the first output clock signal terminal CKE1 of the 2n-1th shift register is electrically connected to the first output clock signal line CLKE1, and the second output clock signal terminal CKE2 of the 2n-1th shift register is electrically connected to the second output clock signal line CLKE2; the first output clock signal terminal CKE1 of the 2nth shift register is electrically connected to the third output clock signal line CLKE3, and the second output clock signal terminal CKE2 of the 2nth shift register is electrically connected to the fourth output clock signal line CLKE4. Exemplarily, the first output clock signal terminal CKE1 of the first shift register GOA (1) is electrically connected to the first output clock signal line CLKE1, and the second output clock signal terminal CKE2 of the first shift register GOA (1) is electrically connected to the second output clock signal line CLKE2; the first output clock signal terminal CKE1 of the second shift register GOA (2) is electrically connected to the third output clock signal line CLKE3, and the second output clock signal terminal CKE2 of the second shift register GOA (2) is electrically connected to the fourth output clock signal line CLKE4, and so on.

[0400] In an exemplary embodiment, a portion of the strobe signal lines connected to the plurality of strobe signal terminals of at least one shift register is referred to as a strobe signal line unit. The strobe signal lines included in the strobe signal line unit connected to the 2n-1th shift register are the same as the strobe signal lines included in the strobe signal line unit connected to the 2n-th shift register, and the strobe signal lines included in the strobe signal line unit connected to the 2n-1th shift register are different from at least one of the strobe signal lines included in the strobe signal line unit connected to the 2n+1th shift register. For example, FIG33 shows that the first selection signal terminal D0 of the first shift register GOA (1) and the second shift register GOA (2) is electrically connected to the first selection signal line DL0, the second selection signal terminal D1 is electrically connected to the third selection signal line DL1, the third selection signal terminal D2 is electrically connected to the fifth selection signal line DL2, the fourth selection signal terminal D3 is electrically connected to the seventh selection signal line DL3, the fifth selection signal terminal D4 is electrically connected to the ninth selection signal line DL4, the sixth selection signal terminal D5 is electrically connected to the tenth selection signal line DL6, and the sixth selection signal terminal D6 is electrically connected to the tenth selection signal line DL7. A selection signal line DL5 is electrically connected, a seventh selection signal terminal D6 is electrically connected to a thirteenth selection signal line DL6, an eighth selection signal terminal D7 is electrically connected to a fifteenth selection signal line DL7, a first selection signal terminal D0 in the third shift register GOA (3) and a fourth shift register GOA (4) is electrically connected to a second selection signal line DLN0, a second selection signal terminal D1 is electrically connected to a third selection signal line DL1, a third selection signal terminal D2 is electrically connected to a fifth selection signal line DL2, and a fourth selection signal terminal D3 is electrically connected to a fifth selection signal line DL4. The first selection signal terminal D0 of the five hundred and eleventh shift register GOA (511) is electrically connected to the second selection signal line DLN0, the second selection signal terminal D1 is electrically connected to the second selection signal line DLN2, the third selection signal terminal D2 is electrically connected to the fifth selection signal line DLN3, the fourth selection signal terminal D3 is electrically connected to the seventh selection signal line DL3, the fifth selection signal terminal D4 is electrically connected to the ninth selection signal line DL4, the sixth selection signal terminal D5 is electrically connected to the eleventh selection signal line DL5, the seventh selection signal terminal D6 is electrically connected to the thirteenth selection signal line DL6, the eighth selection signal terminal D7 is electrically connected to the fifteenth selection signal line DL7, and so on. The signal terminal D1 is electrically connected to the third selection signal line DL1, the third selection signal terminal D2 is electrically connected to the sixth selection signal line DLN2, the fourth selection signal terminal D3 is electrically connected to the eighth selection signal line DLN3, the fifth selection signal terminal D4 is electrically connected to the tenth selection signal line DLN4, the sixth selection signal terminal D5 is electrically connected to the twelfth selection signal line DLN5, the seventh selection signal terminal D6 is electrically connected to the fourteenth selection signal line DLN6, and the eighth selection signal terminal D7 is electrically connected to the sixteenth selection signal line DLN7.

[0401] The smallest partition that can be achieved in the display device provided by the embodiment of the present disclosure can drive four rows of sub-pixels.

[0402] In an exemplary embodiment, the operating modes of the display device include a first scanning mode, in which the signal output by the first signal output terminal of the nth shift register is earlier than the signal output by the second signal output terminal of the nth shift register, and the timing of the signal output by the first signal output terminal of the nth shift register does not overlap with the timing of the signal output by the second signal output terminal of the nth shift register. When the display device is in the first scanning mode, the gate driver circuit sequentially outputs signals from the first row of sub-pixels to the last row of sub-pixels. When the display device is in the first scanning mode, the multiple selection signal terminals in the shift register are decoded starting from the smallest number, for example, starting with 0 corresponding to the first shift register.

[0403] In an exemplary embodiment, the operating modes of the display device may further include a second scanning mode, in which the signal output by the first signal output terminal of the nth shift register is later than the signal output by the second signal output terminal OUT2 of the nth shift register, and the timing of the signal output by the first signal output terminal OUT1 of the nth shift register does not overlap with the timing of the signal output by the second signal output terminal of the nth shift register. When the display device is in the second scanning mode, the gate drive circuit sequentially outputs signals from the last row of sub-pixels to the first row of sub-pixels. When the display device is in the first scanning mode, the multiple selection signal terminals in the shift register are decoded starting from the largest number. For example, decoding starts with 254 corresponding to the 511th shift register.

[0404] In an exemplary embodiment, FIG35 is a timing diagram of multiple clock signal lines of a display device in a first scanning mode, and FIG36 is a timing diagram of multiple clock signal lines of a display device in a second scanning mode. As shown in FIG35 and FIG36 , when the signal of the first selection clock signal line CLK1 is a first-level signal, the signal of the second selection clock signal line CLK2 is a second-level signal; when the signal of the second selection clock signal line CLK2 is a first-level signal, the signal of the first selection clock signal line CLK1 is a second-level signal; the voltage value of the first-level signal is greater than the voltage value of the second-level signal.

[0405] In an exemplary embodiment, as shown in FIG. 35 and FIG. 36 , times when signals of at least two of the first to fourth output clock signal lines CLKE1 to CLKE4 are first level signals do not overlap.

[0406] In an exemplary embodiment, as shown in Figures 35 and 36, a time period in which a signal of at least one of the first selection clock signal line CLK1 and the second selection clock signal line CLK2 is a first level signal does not overlap with a time period in which a signal of at least one of the first output clock signal line CLKE1 to the fourth output clock signal line CLKE4 is a first level signal.

[0407] In an exemplary embodiment, as shown in FIG. 35 and FIG. 36 , the signals of the first gate clock signal line CLK1 , the second gate clock signal line CLK2 , and the first to fourth output clock signal lines CLKE1 to CLKE4 include a plurality of pulse signals.

[0408] In an exemplary embodiment, as shown in FIG35 , in the first scan mode, the r-th pulse signal of the first selection clock signal line CLK1 occurs earlier than the r-th pulse signal of the second selection clock signal line CLK2, the r-th pulse signal of the second selection clock signal line CLK2 occurs earlier than the r+1-th pulse signal of the first selection clock signal line CLK1, the r-th pulse of the first output clock signal line CLKE1 occurs earlier than the r-th pulse of the second output clock signal line CLKE2, the r-th pulse of the second output clock signal line CLKE2 occurs earlier than the r-th pulse of the third output clock signal line CLKE3, and the r-th pulse of the third output clock signal line CLKE3 occurs earlier than the r-th pulse of the fourth output clock signal line CLKE4. The time when the rth pulse of the first output clock signal line CLKE1 occurs and the time when the rth pulse of the second output clock signal line CLKE2 occurs are between the time when the rth pulse signal of the first selection clock signal line CLK1 occurs and the time when the rth pulse signal of the second selection clock signal line CLK2 occurs; the time when the rth pulse of the third output clock signal line CLKE3 occurs and the time when the rth pulse of the fourth output clock signal line CLKE4 occurs are between the time when the rth pulse signal of the second selection clock signal line CLK2 occurs and the time when the r+1th pulse signal of the first selection clock signal line CLK1 occurs, 1≤r≤R, R is the number of pulse signals included in the signals of the first selection clock signal line CLK1, the second selection clock signal line CLK2, and the first output clock signal line CLKE1 to the fourth output clock signal line CLKE4.

[0409] In an exemplary embodiment, as shown in FIG36 , in the second scanning mode, the r-th pulse signal of the first selection clock signal line CLK1 occurs earlier than the r-th pulse signal of the second selection clock signal line CLK2, the r-th pulse signal of the second selection clock signal line CLK2 occurs earlier than the r+1-th pulse signal of the first selection clock signal line CLK1, the r-th pulse of the fourth output clock signal line CLKE4 occurs earlier than the r-th pulse of the third output clock signal line CLKE3, the r-th pulse of the third output clock signal line CLKE3 occurs earlier than the r-th pulse of the second output clock signal line CLKE2, the r-th pulse of the second output clock signal line CLKE2 occurs earlier than the r-th pulse of the first output clock signal line CLKE1, and the time when the r-th pulse of the fourth output clock signal line CLKE4 and the time when the r-th pulse of the third output clock signal line CLKE3 occur are located between the first selection clock signal line CLK1 and the second selection clock signal line CLK2. The time when the rth pulse signal of the second selection clock signal line CLKE2 occurs is between the time when the rth pulse signal of the second selection clock signal line CLKE2 occurs and the time when the rth pulse signal of the first output clock signal line CLKE1 occurs. The time when the rth pulse of the second selection clock signal line CLKE2 occurs is between the time when the rth pulse of the first output clock signal line CLKE1 occurs and the time when the r+1th pulse signal of the first selection clock signal line CLK1 occurs, 1≤r≤R, R is the number of pulse signals included in the signals of the first selection clock signal line CLK1, the second selection clock signal line CLK2, and the first output clock signal line CLKE1 to the fourth output clock signal line CLKE4.

[0410] In an exemplary embodiment, signals of at least two gate signal lines are inverted signals to each other during a partial period.

[0411] Figures 26 to 28 can be understood as the operation timing diagrams of the first shift register when the display device operates in the first scanning mode. Figures 29 to 31 can be understood as the operation timing diagrams of the last shift register when the display device operates in the second scanning mode.

[0412] In an exemplary embodiment, the display device may be any product or component with a display function, such as a wearable device, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, or a navigator.

[0413] The drawings of the embodiments of the present disclosure only relate to the structures involved in the embodiments of the present disclosure, and other structures may refer to general designs.

[0414] For the sake of clarity, the thickness and size of layers or microstructures are exaggerated in the drawings used to describe the embodiments of the present disclosure. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, the element can be "directly on" or "under" the other element, or intervening elements may be present.

[0415] Although the embodiments disclosed in this disclosure are as described above, the contents described are merely embodiments adopted to facilitate understanding of the disclosure and are not intended to limit the disclosure. Any person skilled in the art to which the disclosure belongs may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope of the disclosure. However, the scope of patent protection of the disclosure shall still be based on the scope defined by the attached claims.

Claims

1. A shift register comprising: a node control subcircuit, a decoding subcircuit, and an output control subcircuit; The node control subcircuit is electrically connected to the first gating clock signal terminal, the second gating clock signal terminal, the first power supply terminal, the second power supply terminal, the first node, the second node, and the third node, respectively, and is configured to provide a signal from the first power supply terminal or the second gating clock signal terminal to the first node, provide a signal from the second gating clock signal terminal to the second node, and provide a signal from the first power supply terminal or the first gating clock signal terminal to the third node under the control of the signals from the first gating clock signal terminal, the second gating clock signal terminal, and the second node; The decoding sub-circuit is electrically connected to the at least one gating signal terminal, the second gating clock signal terminal and the second node respectively, and is configured to provide the signal of the second gating clock signal terminal to the second node under the control of the signal of the at least one gating signal terminal; The output control subcircuit is electrically connected to the first output clock signal terminal, the second output clock signal terminal, the first signal output terminal, the second signal output terminal, the second power supply terminal, the first node and the third node, respectively, and is configured to provide a signal from the first output clock signal terminal or the second power supply terminal to the first signal output terminal, and provide a signal from the second output clock signal terminal or the second power supply terminal to the second signal output terminal under the control of the signals from the first node and the third node.

2. The shift register according to claim 1, wherein: The node control subcircuit includes: a first node control subcircuit; The first node control subcircuit is electrically connected to the first selection clock signal terminal, the second selection clock signal terminal, the second power supply terminal, the first node, the second node and the third node, respectively, and is configured to provide the signal of the second selection clock signal terminal to the first node under the control of the signals of the first selection clock signal terminal, the second selection clock signal terminal, the second node and the third node, and store the voltage difference between the first node and the second power supply terminal.

3. The shift register according to claim 2, wherein: The first node control subcircuit includes: a first transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor and a first capacitor; The control electrode and the first electrode of the first transistor are electrically connected to the second selection clock signal terminal respectively, and the second electrode of the first transistor is electrically connected to the first node; A control electrode of the thirteenth transistor is electrically connected to the second node, a first electrode of the thirteenth transistor is electrically connected to the first node, and a second electrode of the thirteenth transistor is electrically connected to the second electrode of the fourteenth transistor; The control electrode of the fourteenth transistor is electrically connected to the first selection clock signal terminal, and the first electrode of the fourteenth transistor is electrically connected to the second selection clock signal terminal; A control electrode of the fifteenth transistor is electrically connected to the third node, a first electrode of the fifteenth transistor is electrically connected to the first node, and a second electrode of the fifteenth transistor is electrically connected to the second selection clock signal terminal; A first end of the first capacitor is electrically connected to the first node, and a second end of the first capacitor is electrically connected to the second power supply end.

4. The shift register according to claim 1, wherein: The node control subcircuit includes: a first node control subcircuit; The first node control subcircuit is electrically connected to the first selection clock signal terminal, the second selection clock signal terminal, the first power supply terminal, the second power supply terminal, the first node, the second node and the third node, respectively, and is configured to provide the signal of the first power supply terminal or the second selection clock signal terminal to the first node under the control of the signals of the first selection clock signal terminal, the second selection clock signal terminal, the second node and the third node, and store the voltage difference between the first node and the second power supply terminal.

5. The shift register according to claim 4, wherein: The first node control subcircuit includes: a first transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor and a first capacitor; The control electrode of the first transistor is electrically connected to the second selection clock signal terminal, the first electrode of the first transistor is electrically connected to the first power supply terminal, and the second electrode of the first transistor is electrically connected to the first node; A control electrode of the thirteenth transistor is electrically connected to the second node, a first electrode of the thirteenth transistor is electrically connected to the first node, and a second electrode of the thirteenth transistor is electrically connected to the second electrode of the fourteenth transistor; The control electrode of the fourteenth transistor is electrically connected to the first selection clock signal terminal, and the first electrode of the fourteenth transistor is electrically connected to the second selection clock signal terminal; A control electrode of the fifteenth transistor is electrically connected to the third node, a first electrode of the fifteenth transistor is electrically connected to the first node, and a second electrode of the fifteenth transistor is electrically connected to the second selection clock signal terminal; A first end of the first capacitor is electrically connected to the first node, and a second end of the first capacitor is electrically connected to the second power supply end.

6. The shift register according to claim 2 or 4, wherein: The node control subcircuit further includes: a second node control subcircuit; The second node control subcircuit is electrically connected to the first selection clock signal terminal, the second selection clock signal terminal, the first power supply terminal, the second node and the third node, respectively, and is configured to provide the signal of the second selection clock signal terminal to the second node under the control of the signal of the first selection clock signal terminal, and to provide the signal of the first selection clock signal terminal or the first power supply terminal to the third node under the control of the signal of the first selection clock signal terminal, the second selection clock signal terminal and the second node.

7. The shift register according to claim 6, wherein: The second node control subcircuit includes: a tenth transistor, an eleventh transistor, a twelfth transistor, a sixteenth transistor and a second capacitor; The control electrode and the first electrode of the tenth transistor are electrically connected to the second selection clock signal terminal respectively, and the second electrode of the tenth transistor is electrically connected to the second node; The control electrode of the eleventh transistor is electrically connected to the second node, the first electrode of the eleventh transistor is electrically connected to the first power supply terminal, and the second electrode of the eleventh transistor is electrically connected to the first electrode of the twelfth transistor; The control electrode of the twelfth transistor is electrically connected to the first selection clock signal terminal, and the second electrode of the twelfth transistor is electrically connected to the third node; A control electrode of the sixteenth transistor is electrically connected to the second gate clock signal terminal, a first electrode of the sixteenth transistor is electrically connected to the first gate clock signal terminal, and a second electrode of the sixteenth transistor is electrically connected to the third node; A first end of the second capacitor is electrically connected to the first power supply end, and a second end of the second capacitor is electrically connected to the second node.

8. The shift register according to claim 1 or 7, wherein: The decoding sub-circuit includes a first selection signal terminal to an eighth selection signal terminal, and the decoding sub-circuit includes: a second transistor to a ninth transistor; The control electrode of the second transistor is electrically connected to the first selection signal terminal, the first electrode of the second transistor is electrically connected to the second selection clock signal terminal, and the second electrode of the second transistor is electrically connected to the second node; The control electrode of the third transistor is electrically connected to the second selection signal terminal, the first electrode of the third transistor is electrically connected to the second selection clock signal terminal, and the second electrode of the third transistor is electrically connected to the second node; The control electrode of the fourth transistor is electrically connected to the third selection signal terminal, the first electrode of the fourth transistor is electrically connected to the second selection clock signal terminal, and the second electrode of the fourth transistor is electrically connected to the second node; a control electrode of the fifth transistor electrically connected to the fourth selection signal terminal, a first electrode of the fifth transistor electrically connected to the second selection clock signal terminal, and a second electrode of the fifth transistor electrically connected to the second node; a control electrode of the sixth transistor electrically connected to the fifth selection signal terminal, a first electrode of the sixth transistor electrically connected to the second selection clock signal terminal, and a second electrode of the sixth transistor electrically connected to the second node; The control electrode of the seventh transistor is electrically connected to the sixth selection signal terminal, the first electrode of the seventh transistor is electrically connected to the second selection clock signal terminal, and the second electrode of the seventh transistor is electrically connected to the second node; a control electrode of the eighth transistor electrically connected to the seventh selection signal terminal, a first electrode of the eighth transistor electrically connected to the second selection clock signal terminal, and a second electrode of the eighth transistor electrically connected to the second node; The control electrode of the ninth transistor is electrically connected to the eighth selection signal terminal, the first electrode of the ninth transistor is electrically connected to the second selection clock signal terminal, and the second electrode of the ninth transistor is electrically connected to the second node.

9. The shift register according to claim 1 or 8, wherein: The output control subcircuit includes: a seventeenth transistor to a twentieth transistor and a third capacitor and a fourth capacitor; A control electrode of the seventeenth transistor is electrically connected to the third node, a first electrode of the seventeenth transistor is electrically connected to the first output clock signal terminal, and a second electrode of the seventeenth transistor is electrically connected to the first signal output terminal; The control electrode of the eighteenth transistor is electrically connected to the first node, the first electrode of the eighteenth transistor is electrically connected to the second power supply terminal, and the second electrode of the eighteenth transistor is electrically connected to the first signal output terminal; A control electrode of the nineteenth transistor is electrically connected to the third node, a first electrode of the nineteenth transistor is electrically connected to the second clock signal output terminal, and a second electrode of the nineteenth transistor is electrically connected to the second signal output terminal; The control electrode of the twentieth transistor is electrically connected to the first node, the first electrode of the twentieth transistor is electrically connected to the second power supply terminal, and the second electrode of the twentieth transistor is electrically connected to the second signal output terminal; A first end of the third capacitor is electrically connected to the third node, and a second end of the third capacitor is electrically connected to the first signal output end; A first end of the fourth capacitor is electrically connected to the third node, and a second end of the fourth capacitor is electrically connected to the second signal output end.

10. The shift register according to claim 1 or 8, further comprising: Isolating sub-circuits; The output control subcircuit is electrically connected to the third node via the isolation subcircuit; The isolation sub-circuit is electrically connected to the first power supply terminal, the third node, the fourth node and the fifth node respectively, and is configured to provide the signal of the third node to the fourth node and the fifth node under the control of the signal of the first power supply terminal; The output control subcircuit is also electrically connected to the fourth node and the fifth node, respectively, and is configured to provide the signal of the first output clock signal terminal to the first signal output terminal and the signal of the second output clock signal terminal to the second signal output terminal under the control of the signals of the fourth node and the fifth node, and to provide the signal of the second power supply terminal to the first signal output terminal and the second signal output terminal under the control of the signal of the first node.

11. The shift register according to claim 10, wherein: The isolation sub-circuit includes: a twenty-second transistor and a twenty-third transistor; The control electrode of the twenty-second transistor is electrically connected to the first power supply terminal, the first electrode of the twenty-second transistor is electrically connected to the third node, and the second electrode of the twenty-second transistor is electrically connected to the fifth node; The control electrode of the twenty-third transistor is electrically connected to the first power supply terminal, the first electrode of the twenty-third transistor is electrically connected to the third node, and the second electrode of the twenty-third transistor is electrically connected to the fourth node.

12. The shift register according to claim 11, wherein: The output control subcircuit includes: a seventeenth transistor to a twentieth transistor and a third capacitor and a fourth capacitor; A control electrode of the seventeenth transistor is electrically connected to the fourth node, a first electrode of the seventeenth transistor is electrically connected to the first output clock signal terminal, and a second electrode of the seventeenth transistor is electrically connected to the first signal output terminal; The control electrode of the eighteenth transistor is electrically connected to the first node, the first electrode of the eighteenth transistor is electrically connected to the second power supply terminal, and the second electrode of the eighteenth transistor is electrically connected to the first signal output terminal; The control electrode of the nineteenth transistor is electrically connected to the fifth node, and the first electrode of the nineteenth transistor is electrically connected to the second output clock signal. The second electrode of the nineteenth transistor is electrically connected to the second signal output terminal; The control electrode of the twentieth transistor is electrically connected to the first node, the first electrode of the twentieth transistor is electrically connected to the second power supply terminal, and the second electrode of the twentieth transistor is electrically connected to the second signal output terminal; A first end of the third capacitor is electrically connected to the fourth node, and a second end of the third capacitor is electrically connected to the first signal output terminal; A first end of the fourth capacitor is electrically connected to the fifth node, and a second end of the fourth capacitor is electrically connected to the second signal output end.

13. The shift register according to claim 1 or 8, further comprising: Isolating sub-circuits; The output control subcircuit is electrically connected to the third node via the isolation subcircuit; The isolation sub-circuit is electrically connected to the first power supply terminal, the third node and the fourth node respectively, and is configured to provide the signal of the third node to the fourth node under the control of the signal of the first power supply terminal; The output control subcircuit is also electrically connected to the fourth node and is configured to provide a signal from the first output clock signal terminal to the first signal output terminal and a signal from the second output clock signal terminal to the second signal output terminal under the control of the signal of the fourth node, and to provide a signal from the second power supply terminal to the first signal output terminal and the second signal output terminal under the control of the signal of the first node.

14. The shift register according to claim 13, wherein: The isolation sub-circuit includes: a twenty-second transistor; The control electrode of the twenty-second transistor is electrically connected to the first power supply terminal, the first electrode of the twenty-second transistor is electrically connected to the third node, and the second electrode of the twenty-second transistor is electrically connected to the fourth node.

15. The shift register according to claim 14, wherein: The output control subcircuit includes: a seventeenth transistor to a twentieth transistor, a third capacitor and a fourth capacitor; A control electrode of the seventeenth transistor is electrically connected to the fourth node, a first electrode of the seventeenth transistor is electrically connected to the first output clock signal terminal, and a second electrode of the seventeenth transistor is electrically connected to the first signal output terminal; The control electrode of the eighteenth transistor is electrically connected to the first node, the first electrode of the eighteenth transistor is electrically connected to the second power supply terminal, and the second electrode of the eighteenth transistor is electrically connected to the first signal output terminal; A control electrode of the nineteenth transistor is electrically connected to the fourth node, a first electrode of the nineteenth transistor is electrically connected to the second clock signal output terminal, and a second electrode of the nineteenth transistor is electrically connected to the second signal output terminal; The control electrode of the twentieth transistor is electrically connected to the first node, the first electrode of the twentieth transistor is electrically connected to the second power supply terminal, and the second electrode of the twentieth transistor is electrically connected to the second signal output terminal; A first end of the third capacitor is electrically connected to the fourth node, and a second end of the third capacitor is electrically connected to the first signal output terminal; A first end of the fourth capacitor is electrically connected to the fourth node, and a second end of the fourth capacitor is electrically connected to the second signal output end.

16. The shift register according to any one of claims 1, 9, 12 and 15, further comprising: reset subcircuit; The reset subcircuit is electrically connected to the reset signal terminal, the third node and the second power terminal respectively, and is configured to provide the signal of the second power terminal to the third node under the control of the signal of the reset signal terminal.

17. The shift register according to claim 16, wherein: The reset sub-circuit includes: a twenty-first transistor; The control electrode of the twenty-first transistor is electrically connected to the reset signal terminal, the first electrode of the twenty-first transistor is electrically connected to the second power supply terminal, and the second electrode of the twenty-first transistor is electrically connected to the third node.

18. A display device comprising a display area and a non-display area, wherein the display area is provided with sub-pixels arranged in an array, and the non-display area is provided with a gate driving circuit, wherein the gate driving circuit comprises: A plurality of shift registers according to any one of claims 1 to 17; A first signal output terminal of at least one shift register is electrically connected to at least one row of sub-pixels, and a second signal output terminal of at least one shift register is electrically connected to at least one row of sub-pixels.

19. The display device according to claim 18, wherein The first signal output terminal of the nth shift register is electrically connected to the sub-pixels in the 2n-1th row, and the second signal output terminal of the nth shift register is electrically connected to the sub-pixels in the 2nth row, 1≤n≤N, where N is the total number of shift registers.

20. The display device according to claim 18, wherein The non-display area is further provided with a gate signal line group, which includes: a plurality of gate signal lines, and a plurality of gate signal terminals in at least one shift register are electrically connected to some of the gate signal lines in the gate signal line group.

21. The display substrate according to claim 20, wherein: The shift register includes: M strobe signal terminals, and the strobe signal line group includes: 2M strobe signal lines; The mth gate signal terminal is electrically connected to one of the 2m-1th gate signal line and the 2mth gate signal line.

22. The display substrate according to claim 21, wherein The signals of at least two strobe signal lines are mutually inverted signals during a partial period.

23. The display substrate according to claim 21, wherein The non-display area is further provided with a clock signal line group, and the clock signal line group includes: a plurality of clock signal lines; At least one of the first output clock signal terminal, the second output clock signal terminal, the first selection clock signal terminal and the second selection clock signal terminal in at least one shift register is electrically connected to a clock signal line among the plurality of clock signal terminals.

24. The display substrate according to claim 23, wherein: The plurality of clock signal lines include: a first gated clock signal line, a second gated clock signal line, a first output clock signal line, a second output clock signal line, a third output clock signal line and a fourth output clock signal line; The first gated clock signal terminal of at least one shift register is electrically connected to one of the first gated clock signal line and the second gated clock signal line, and the second gated clock signal terminal of at least one shift register is electrically connected to the other of the first gated clock signal line and the second gated clock signal line; The first selection clock signal terminals of adjacent shift registers are connected to different signal lines, and the second selection clock signal terminals of adjacent shift registers are connected to different signal lines; The first output clock signal terminal of at least one shift register is electrically connected to the first output clock signal line, and the second output clock signal terminal of at least one shift register is electrically connected to the second output clock signal line, or the first output clock signal terminal of at least one shift register is electrically connected to the third output clock signal line, and the second output clock signal terminal of at least one shift register is electrically connected to the fourth output clock signal line; The first clock signal output terminals of adjacent shift registers are connected to different signal lines, and the second clock signal output terminals of adjacent shift registers are connected to different signal lines.

25. The display substrate according to claim 24, wherein: The part of the strobe signal lines connected to the multiple strobe signal terminals of at least one shift register is called a strobe signal line unit; The strobe signal line included in the strobe signal line unit connected to the 2n-1th shift register is the same as the strobe signal line included in the strobe signal line unit connected to the 2n-th shift register, and the strobe signal line included in the strobe signal line unit connected to the 2n-1th shift register is different from at least one of the strobe signal lines included in the strobe signal line unit connected to the 2n+1th shift register; The first output clock signal terminal of the 2n-1th shift register is electrically connected to the first output clock signal line, and the second output clock signal terminal of the 2n-1th shift register is electrically connected to the second output clock signal line; The first output clock signal terminal of the 2nth shift register is electrically connected to the third output clock signal line, and the second output clock signal terminal of the 2nth shift register is electrically connected to the fourth output clock signal line.

26. The display device according to claim 25, wherein When the signal of the first strobe clock signal line is a first level signal, the signal of the second strobe clock signal line is a second level signal; when the signal of the second strobe clock signal line is a first level signal, the signal of the first strobe clock signal line is a second level signal; The voltage value of the first level signal is greater than the voltage value of the second level signal.

27. The display device according to claim 26, wherein: Times during which the signals of at least two of the first to fourth output clock signal lines are first level signals do not overlap.

28. The display device according to claim 27, wherein: The time period during which the signal of at least one of the first selection clock signal line and the second selection clock signal line is a first level signal does not overlap with the time period during which the signal of at least one of the first output clock signal line to the fourth output clock signal line is a first level signal.

29. The display device according to claim 28, wherein The operating modes of the display device include: a first scanning mode, in which a signal outputted by the first signal output terminal of the nth shift register is earlier than a signal outputted by the second signal output terminal of the nth shift register, and a timing of the signal outputted by the first signal output terminal of the nth shift register does not overlap with a timing of the signal outputted by the second signal output terminal of the nth shift register; The signals of the first gate clock signal line, the second gate clock signal line, and the first output clock signal line to the fourth output clock signal line include a plurality of pulse signals; In the first scanning mode, the time when the rth pulse signal of the first selection clock signal line occurs is earlier than the time when the rth pulse signal of the second selection clock signal line occurs, the time when the rth pulse signal of the second selection clock signal line occurs is earlier than the time when the r+1th pulse signal of the first selection clock signal line occurs, the time when the rth pulse of the first output clock signal line occurs is earlier than the time when the rth pulse of the second output clock signal line occurs, the time when the rth pulse of the second output clock signal line occurs is earlier than the time when the rth pulse of the third output clock signal line occurs, the time when the rth pulse of the third output clock signal line occurs is earlier than the time when the rth pulse of the fourth output clock signal line occurs, and the first output clock signal line is earlier than the rth pulse of the fourth output clock signal line. The time when the rth pulse of the first selection clock signal line occurs and the time when the rth pulse of the second output clock signal line occurs are between the time when the rth pulse signal of the first selection clock signal line occurs and the time when the rth pulse signal of the second selection clock signal line occurs; the time when the rth pulse of the third output clock signal line occurs and the time when the rth pulse of the fourth output clock signal line occurs are between the time when the rth pulse signal of the second selection clock signal line occurs and the time when the r+1th pulse signal of the first selection clock signal line occurs, 1≤r≤R, R is the number of pulse signals included in the signals of the first selection clock signal line, the second selection clock signal line, and the first output clock signal line to the fourth output clock signal line.

30. The display device according to claim 28, wherein The operating modes of the display device include: a second scanning mode, in which a signal outputted from the first signal output terminal of the nth shift register is later than a signal outputted from the second signal output terminal of the nth shift register, and a timing of the signal outputted from the first signal output terminal of the nth shift register does not overlap with a timing of the signal outputted from the second signal output terminal of the nth shift register; The signals of the first gate clock signal line, the second gate clock signal line, and the first output clock signal line to the fourth output clock signal line include a plurality of pulse signals; In the second scanning mode, the time when the rth pulse signal of the first strobe clock signal line occurs is earlier than the time when the rth pulse signal of the second strobe clock signal line occurs. The time when the rth pulse of the fourth output clock signal line occurs is earlier than the time when the rth pulse of the third output clock signal line occurs, the time when the rth pulse of the third output clock signal line occurs is earlier than the time when the rth pulse of the second output clock signal line occurs, the time when the rth pulse of the second output clock signal line occurs is earlier than the time when the rth pulse of the first output clock signal line occurs, the time when the rth pulse of the fourth output clock signal line occurs and the time when the rth pulse of the third output clock signal line occurs are between the time when the rth pulse signal of the first selection clock signal line occurs and the time when the rth pulse of the second selection clock signal line occurs; the time when the rth pulse of the second output clock signal line occurs and the time when the rth pulse of the first output clock signal line occurs are between the time when the rth pulse signal of the second selection clock signal line occurs and the time when the r+1th pulse signal of the first selection clock signal line occurs, 1≤r≤R, R is the number of pulse signals included in the signals of the first selection clock signal line, the second selection clock signal line, and the first output clock signal line to the fourth output clock signal line.

31. A method for driving a shift register, configured to drive the shift register according to any one of claims 1 to 17, the method comprising: The node control subcircuit, under the control of the first gated clock signal terminal, the second gated clock signal terminal, and the signal of the second node, provides a signal of the first power supply terminal or the second gated clock signal terminal to the first node, provides a signal of the second gated clock signal terminal to the second node, and provides a signal of the first power supply terminal or the first gated clock signal terminal to the third node; The decoding sub-circuit provides a signal from a second gated clock signal terminal to the second node under the control of a signal from at least one gated signal terminal; Under the control of the signals of the first node and the third node, the output control subcircuit provides a signal of the first output clock signal terminal or the second power supply terminal to the first signal output terminal, and provides a signal of the second output clock signal terminal or the second power supply terminal to the second signal output terminal.

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