Method, apparatus and system for determining machine check exception error type of processor

Abstract

Embodiments of the present application provide a method, apparatus and system for determining a machine check exception error type of a processor, a server, a non-volatile readable storage medium, and an electronic device. The method comprises: acquiring a register value stored in a target register of a target processor; on the basis of an event type byte and an event sequence byte comprised in the register value, determining a fault type of a target fault occurring in the target processor; and when the fault type indicates that the type of the target fault is a first machine check exception error type, on the basis of error value bytes comprised in the register value, determining whether the target fault is a machine check exception fault, wherein the error value bytes are bytes used for indicating error values. The present application solves the problem in the related art of inaccurate determination of a machine check exception error type of a processor, thereby improving the accuracy of determining the machine check exception error type of the processor.

Description

Method, device, and system for determining machine check exception error type of processor

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to a Chinese patent application filed with the Patent Office of China on January 24, 2024, with application number 202410098513.4 and application name “Method, device, and system for determining the machine check exception error type of a processor,” the entire contents of which are incorporated herein by reference. Technical Field

[0003] Embodiments of the present application relate to the field of processors, and more specifically, to a method, apparatus, system, server, non-volatile readable storage medium, and electronic device for determining a machine check exception error type of a processor. Background Art

[0004] In the related art, when classifying and analyzing processor errors, some non-MCE (Machine Check Exception) error data will be recorded in the MCE error category.

[0005] It can be seen from this that the related art has a problem of inaccurately determining the type of the machine check exception error of the processor.

[0006] Currently, no effective solution has been proposed to the above-mentioned problems existing in the related technologies.

[0007] Summary of the Invention

[0008] Embodiments of the present application provide a method, apparatus, system, server, non-volatile readable storage medium, and electronic device for determining a machine check exception error type of a processor, so as to at least solve the problem of inaccurate determination of a machine check exception error type of a processor existing in the related art.

[0009] According to one embodiment of the present application, a method for determining a machine check exception error type of a processor is provided, comprising: obtaining a register value stored in a target register of a target processor, wherein the target register is configured to store a fault value, the fault value comprising a value written to the target register when a component included in the target processor fails; determining a fault type of a target fault occurring in the target processor based on an event type byte and an event sequence byte included in the register value, wherein the event type byte is a byte for indicating an event type, and the event sequence byte is a byte for indicating an order in which events occur; in a case where the fault type indicates that the type of the target fault is a first machine check exception error type, determining whether the target fault is a machine check exception fault based on an error value byte included in the register value, wherein the error value byte is a byte for indicating an error value.

[0010] In an exemplary embodiment, the method further includes: determining that the target fault is a machine check exception fault if the fault type indicates that the type of the target fault is a second machine check exception error type.

[0011] In an exemplary embodiment, determining whether the target fault is a machine check exception fault based on an error value byte included in a register value includes: determining a first value of a first subbyte included in the error value byte; and determining whether the target fault is a machine check exception fault based on the first value.

[0012] In an exemplary embodiment, determining whether a target fault is a machine check exception fault based on a first value includes: determining a second value, wherein the second value is a value included in a first fault value stored in a target register when a first fault exists in firmware included in a device where a target processor is located, the value of a byte included in the first fault value for indicating a fault type is the same as the value of an event type byte, the value of a byte included in the first fault value for indicating a fault order is the same as the value of an event order byte, and the order of the second value in the first fault value is the same as the order of the first value in the register value; when there is a value in the second value that is the same as the first value, determining that the target fault is a non-machine check exception fault; and when the values ​​included in the first value and the second value are different, determining whether the target fault is a machine check exception fault based on the error value byte.

[0013] In an exemplary embodiment, determining whether the target fault is a machine check exception fault based on the error value byte includes: determining a second subbyte included in the error value byte; and determining whether the target fault is a machine check exception fault based on the second subbyte and the first value.

[0014] In an exemplary embodiment, determining whether a target fault is a machine check exception fault based on a second subbyte and a first numerical value includes: determining a third numerical value, wherein the third numerical value is a value included in a second fault value stored in a target register when a second fault exists in firmware included in a device where a target processor is located, the numerical value of a byte included in the second fault value for indicating a fault type is the same as the numerical value of an event type byte, the numerical value of a byte included in the second fault value for indicating a fault order is the same as the numerical value of an event order byte, and the order of the third numerical value in the second fault value is the same as the order of the first numerical value in the register numerical value; when the first numerical value is the same as the third numerical value, determining a fourth numerical value of the second subbyte; and determining whether the target fault is a machine check exception fault based on the fourth numerical value.

[0015] In an exemplary embodiment, determining whether the target fault is a machine check abnormality fault based on the fourth numerical value includes: when the fourth numerical value is different from the target numerical value, determining that the target fault is a machine check abnormality fault; when the fourth numerical value is the same as the target numerical value, determining that the target fault is not a machine check abnormality fault.

[0016] In an exemplary embodiment, determining whether a target fault is a machine check exception fault based on the second subbyte and the first numerical value includes: determining a fifth numerical value, wherein the fifth numerical value is a value included in a third fault value stored in a target register when a third fault exists in the firmware included in the device where the target processor is located, the numerical value of the byte included in the third fault value for indicating the fault type is the same as the numerical value of the event type byte, the numerical value of the byte included in the third fault value for indicating the fault order is the same as the numerical value of the event order byte, and the order of the fifth numerical value in the third fault value is the same as the order of the first numerical value in the register numerical value; when the first numerical value is the same as the fifth numerical value, determining whether the target fault is a machine check exception fault based on the second subbyte and the third subbyte included in the error value byte.

[0017] In an exemplary embodiment, determining whether a target fault is a machine check exception fault based on the second subbyte and the third subbyte included in the error value byte includes: determining a sixth value of the second subbyte, and determining a seventh value of the third subbyte; determining an eighth value and a ninth value, wherein the eighth value is a value included in the fourth fault value stored in the target register when the firmware included in the device where the target processor is located has a fourth fault, the value of the byte included in the fourth fault value for indicating the fault type is the same as the value of the event type byte, the value of the byte included in the fourth fault value for indicating the fault sequence is the same as the value of the event sequence byte, and the byte included in the fourth fault value for indicating the error value includes The value of the first-order subbyte in the enclosed register is the same as the first value, the eighth value is the value located in the second-order subbyte included in the byte for indicating the error value, the ninth value is the value located in the third-order subbyte included in the byte for indicating the error value, the order of the eighth value in the fourth fault value is the same as the order of the sixth value in the register value, and the order of the ninth value in the fourth fault value is the same as the order of the seventh value in the register value; when the sixth value is the same as the eighth value and the seventh value is the same as the ninth value, the target fault is determined to be a machine check exception fault; when the sixth value is different from the eighth value, and / or the seventh value is different from the ninth value, the target fault is determined to be a non-machine check exception fault.

[0018] In an exemplary embodiment, after determining whether the target fault is a machine check exception fault based on the error value byte included in the register value, the method further includes: in the case where it is determined that the target fault is a machine check exception fault, determining fault information of the machine check exception fault; and recording the fault information in a target log.

[0019] In an exemplary embodiment, obtaining a register value stored in a target register of a target processor includes: determining a value obtaining cycle; and polling the target register according to the value obtaining cycle to obtain the register value.

[0020] In an exemplary embodiment, before obtaining the register value stored in the target register of the target processor, the method further includes: determining a target frequency; and setting a bus clock frequency communicating with the target register to the target frequency.

[0021] According to another embodiment of the present application, a system for determining a machine check exception error type of a processor is provided, for indicating a method in any one of the above embodiments, comprising: a target processor, the target processor comprising a component; a target register, wherein the target register is configured to store a fault value, the fault value comprising a value written into the target register when a fault occurs in a component included in the target processor; a baseboard management controller, wherein the baseboard management controller is configured to obtain a register value stored in the target register of the target processor, and determine a fault type of a target fault occurring in the target processor based on an event type byte and an event sequence byte included in the register value, wherein the event type byte is a byte for indicating an event type, and the event sequence byte is a byte for indicating an order in which events occur, and when the fault type indicates that the type of the target fault is a first machine check exception error type, determine whether the target fault is a machine check exception fault based on an error value byte included in the register value, wherein the error value byte is a byte for indicating an error value.

[0022] According to another embodiment of the present application, a server is provided, comprising: the system for determining the machine check exception error type of the processor in the above embodiment.

[0023] According to another embodiment of the present application, a device for determining a machine check exception error type of a processor is provided, comprising: an acquisition module configured to acquire a register value stored in a target register of a target processor, wherein the target register is configured to store a fault value, the fault value comprising a value written to the target register when a component included in the target processor fails; a first determination module configured to determine a fault type of a target fault occurring in the target processor based on an event type byte and an event sequence byte included in the register value, wherein the event type byte is a byte for indicating an event type, and the event sequence byte is a byte for indicating an order in which events occur; a second determination module configured to determine whether the target fault is a machine check exception fault based on an error value byte included in the register value when the fault type indicates that the type of the target fault is a first machine check exception error type, wherein the error value byte is a byte for indicating an error value.

[0024] According to another embodiment of the present application, a computer non-volatile readable storage medium is provided, in which a computer program is stored, wherein the computer program is configured to execute the steps of any of the above method embodiments when running.

[0025] According to another embodiment of the present application, an electronic device is provided, including a memory and a processor, wherein a computer program is stored in the memory, and the processor is configured to run the computer program to execute the steps in any one of the above method embodiments.

[0026] Through the present application, a register value stored in a target register of a target processor is obtained, wherein the target register is configured to store a fault value, the fault value including a value written to the target register when a component included in the target processor fails; the fault type of a target fault occurring in the target processor is determined based on an event type byte and an event sequence byte included in the register value, wherein the event type byte is a byte used to indicate the event type, and the event sequence byte is a byte used to indicate the order in which events occur; when the fault type indicates that the type of the target fault is a first machine check exception error type, whether the target fault is a machine check exception fault is determined based on an error value byte included in the register value, wherein the error value byte is a byte used to indicate the error value. Since when determining whether the target fault is a machine check exception fault, the register value in the target register can be analyzed to determine that the fault type of the target fault is the first machine check exception error type by determining the event type byte and the event sequence byte in the register value, further judgment is made based on the error value byte in the register value to determine whether the target fault is a machine check exception fault. By comprehensively determining whether the target fault is a machine check exception fault using the event type byte, event sequence byte, and error value byte, it is possible to effectively prevent other faults from being identified as machine check exception faults. This solves the problem of inaccurate determination of a processor's machine check exception error type in related technologies and improves the accuracy of determining the processor's machine check exception error type. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] FIG1 is a hardware structure block diagram of a server device for a method for determining a machine check exception error type of a processor according to an embodiment of the present application;

[0028] 2 is a flowchart of a method for determining a machine check exception error type of a processor according to an embodiment of the present application;

[0029] FIG3 is a schematic diagram of the target processor structure according to an embodiment of the present application;

[0030] 4 is a flow chart of a method for determining a machine check exception error type of a processor according to an embodiment of the present application;

[0031] 5 is a swim-lane diagram of a method for determining a machine check exception error type of a processor according to an embodiment of the present application;

[0032] FIG6 is a structural block diagram of a device for determining a machine check exception error type of a processor according to an embodiment of the present application. DETAILED DESCRIPTION

[0033] The embodiments of the present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0034] It should be noted that the terms "first", "second", etc. in the description and claims of this application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0035] The method embodiments provided in the embodiments of the present application can be executed in a server device or a similar computing device. Taking operation on a server device as an example, FIG1 is a hardware structure block diagram of a server device of a method for determining the machine check exception error type of a processor in an embodiment of the present application. As shown in FIG1 , the server device may include one or more (only one is shown in FIG1 ) processors 102 (the processor 102 may include but is not limited to a processing device such as a microprocessor MCU or a programmable logic device FPGA) and a memory 104 for storing data, wherein the above-mentioned server device may also include a transmission device 106 and an input and output device 108 for communication functions. It will be understood by those skilled in the art that the structure shown in FIG1 is only for illustration and does not limit the structure of the above-mentioned server device. For example, the server device may also include more or fewer components than those shown in FIG1 , or have a configuration different from that shown in FIG1 .

[0036] The memory 104 can be used to store computer programs, for example, software programs and modules of application software, such as the computer program corresponding to the method for determining the machine check exception error type of the processor in the embodiment of the present application. The processor 102 executes various functional applications and data processing by running the computer program stored in the memory 104, that is, implementing the above-mentioned method. The memory 104 may include a high-speed random access memory, and may also include a non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, the memory 104 may further include a memory remotely located relative to the processor 102, and these remote memories may be connected to a server device via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0037] The transmission device 106 is used to receive or send data via a network. A specific example of the aforementioned network may include a wireless network provided by a communication provider of the server device. In one embodiment, the transmission device 106 includes a network interface controller (NIC), which can be connected to other network devices via a base station to enable communication with the Internet. In another embodiment, the transmission device 106 may be a radio frequency (RF) module, which is used to communicate with the Internet wirelessly.

[0038] In this embodiment, a method for determining a machine check exception error type of a processor is provided. FIG2 is a flow chart of the method for determining a machine check exception error type of a processor according to an embodiment of the present application. As shown in FIG2 , the flow chart includes the following steps:

[0039] Step S202 , obtaining a register value stored in a target register of a target processor, wherein the target register is configured to store a fault value, the fault value including a value written to the target register when a component included in the target processor fails;

[0040] Step S204: determining the fault type of the target fault occurring in the target processor based on the event type byte and the event sequence byte included in the register value, wherein the event type byte is a byte for indicating the event type, and the event sequence byte is a byte for indicating the order in which the events occur;

[0041] Step S206 , when the fault type indicates that the type of the target fault is a first machine check exception error type, determining whether the target fault is a machine check exception fault based on an error value byte included in the register value, wherein the error value byte is a byte used to indicate an error value.

[0042] In the above embodiment, the target processor can be an ARM (Advanced RISC Machine) architecture processor. The target processor can be used in related fields of the electronics industry, such as automobiles and the Internet of Things. It can also be used in mobile phones, computers, servers, and other fields. CPUs based primarily on the ARM architecture have low energy consumption, which can achieve energy conservation. A schematic diagram of the target processor structure can be found in Figure 3. As shown in Figure 3, the target processor may include multiple components, which can be further divided into device components and bus components, such as memory bus devices, PCI link devices, ARM core chips, SMpro management components, PMpro management components, Mesh bus, OCM devices, CCIX bus, GIC, and other core key components. PCI (Peripheral Component Interconnect, a standard that defines local buses), SMpro is a system management controller, PMpro is a power management controller, Mesh is an internal CPU bus, OCM (On-Chip Memory), and CCIX (Cache Coherent Interconnect for Accelerators) are high-performance Internet protocols. GIC (Generic Interrupt Controller) is a general-purpose interrupt controller.

[0043] In the above embodiment, the target register can be an SCP (System Control Processor) register or a byte value register. The target register can store various fault values. The fault value can be stored in the target register in byte form. The fault value can correspond to 6 bytes, 8 bytes, etc. This application does not impose any restrictions on the number of bytes. When the fault value is 6 bytes, it can include an event type byte, an event order byte, and four error value bytes. The fault value includes the value written to the target register when a component included in the target processor fails. For example, when a component included in the target processor fails, the value written to the target register may include, but is not limited to, error information related to ARM architecture internal buses and components, such as Mesh bus errors, SMpro error information, PMpro error information, GIC interrupt errors, SMMU error information, CPM error information, and OCM error information. The fault value may also include the value written to the target register when other firmware in the device where the target processor is located fails. The device where the target processor is located may include an automobile, a computer, a mobile phone, a server, etc.

[0044] In the above embodiment, the ARM architecture processor contains multiple components, such as memory bus devices, PCI link devices, ARM core chips, SMpro management components, PMpro management components, Mesh bus, OCM devices, CCIX bus, GIC and other core key components. Once these components produce errors, they will inevitably cause serious or fatal errors to the ARM server system. Therefore, the error register values ​​of the ARM processor can be parsed according to certain rules. For example, the BMC (baseboard management controller) can perform polling on the SCP register of the ARM processor through the I2C bus to read the register value, and parse it according to certain rules to determine whether the target fault is a machine check abnormality fault. In the case of a machine check abnormality fault, the register value can be displayed in the BMC's sel log, which is convenient for rapid parsing and positioning to achieve efficient and rapid positioning of the processor fault location information.

[0045] In the above embodiment, the first machine check exception error type may be a fault type in a device component included in the target processor. In this case, the value of the event type byte may be 0x12, and the value of the event sequence byte may be 0x8E. That is, when the value of the first two bytes included in the register value is 0x128E, the first machine check exception error type may be a fault type in a device component included in the target processor. When a device component is faulty, the values ​​of the event type byte and event sequence byte in the register value generated may be the same as the values ​​of the event type byte and event sequence byte in the register value generated when other firmware in the device where the target processor is located fails. Therefore, further judgment can be made based on the error value bytes in the register value. This improves the accuracy of determining a machine check exception fault.

[0046] Through the present application, a register value stored in a target register of a target processor is obtained, wherein the target register is configured to store a fault value, the fault value including a value written to the target register when a component included in the target processor fails; the fault type of a target fault occurring in the target processor is determined based on an event type byte and an event sequence byte included in the register value, wherein the event type byte is a byte used to indicate the event type, and the event sequence byte is a byte used to indicate the order in which events occur; when the fault type indicates that the type of the target fault is a first machine check exception error type, whether the target fault is a machine check exception fault is determined based on an error value byte included in the register value, wherein the error value byte is a byte used to indicate the error value. Since when determining whether the target fault is a machine check exception fault, the register value in the target register can be analyzed to determine that the fault type of the target fault is the first machine check exception error type by determining the event type byte and the event sequence byte in the register value, further judgment is made based on the error value byte in the register value to determine whether the target fault is a machine check exception fault. By comprehensively determining whether the target fault is a machine check exception fault using the event type byte, event sequence byte, and error value byte, it is possible to effectively prevent other faults from being identified as machine check exception faults. This solves the problem of inaccurate determination of a processor's machine check exception error type in related technologies and improves the accuracy of determining the processor's machine check exception error type.

[0047] The execution subject of the above steps may be a processor, such as a baseboard management controller BMC in the processor, but is not limited thereto.

[0048] In an exemplary embodiment, the method further includes determining that the target fault is a machine check exception fault if the fault type indicates that the target fault type is a second machine check exception error type. In this embodiment, the second machine check exception error type may be a fault type of a bus component included in the target processor. When the fault type indicates a fault in a bus included in the target processor, it can be assumed that an MCE error has occurred. Therefore, further parsing of the error value bytes included in the register value is unnecessary, saving time in determining an MCE fault.

[0049] In the above embodiment, when the target fault type is a second machine check exception error type, the value of the event type byte may be 0x07, and the value of the event sequence byte may be 0x8C. That is, when the first two bytes in the register value are 0x078C, it can be considered that the target fault type is a second machine check exception error type.

[0050] It should be noted that the above values ​​are merely exemplary and are not intended to be limiting. Different values ​​in the event type byte and event sequence byte may represent different types. The correspondence between the values ​​in the event type byte and event sequence byte and the fault type may be pre-set. When a fault occurs, the values ​​in the event type byte and event sequence byte corresponding to the fault type are written to the target register.

[0051] In one exemplary embodiment, determining whether a target fault is a machine check exception fault based on an error value byte included in a register value includes: determining a first value of a first subbyte included in the error value byte; and determining whether the target fault is a machine check exception fault based on the first value. In this embodiment, when the fault type indicates that the target fault is a first machine check exception fault, it can be considered that a component other than the bus included in the target processor has a fault. However, when a fault occurs in another device within the target processor, the event type byte and event sequence byte in the value written to the target register may be the same as the event type byte and event sequence byte written when a component within the processor has a fault. Therefore, the error value byte included in the register value can be further parsed to determine whether the target fault is a machine check exception fault.

[0052] In the above embodiment, the error value byte may include multiple bytes. For example, when the register value includes six bytes, it may include one event type byte, one event order byte, and four error value bytes. That is, the error value byte includes four subbytes. When the fault type of the target fault is determined to be the first machine check exception error type, the first subbyte included in the error value byte may be further parsed to determine whether the target fault is a machine check exception fault based on the first subbyte. This eliminates the need to parse each subbyte included in the error value byte, thereby increasing the speed of determining a machine check exception fault.

[0053] In one exemplary embodiment, determining whether a target fault is a machine check exception fault based on a first value includes: determining a second value, wherein the second value is a value included in a first fault value stored in a target register when the firmware included in the device where the target processor is located has a first fault, the value of a byte included in the first fault value indicating the fault type is the same as the value of an event type byte, the value of a byte included in the first fault value indicating the fault order is the same as the value of an event order byte, and the order of the second values ​​in the first fault value is the same as the order of the first values ​​in the register value; if the second value includes a value that is the same as the first value, determining that the target fault is a non-machine check exception fault; and if the values ​​included in the first value and the second value are different, determining whether the target fault is a machine check exception fault based on the error value byte. In this embodiment, when other firmware in the device where the target processor is located has a fault, the first fault value can be written to the target register. The structure of the first fault value is the same as that of the register value, i.e., the first fault value includes a byte indicating the fault type and a byte indicating the event order. The values ​​of the first fault value and the second fault value are the same as the values ​​of the event type byte and the event order byte included in the register value. The first fault value also includes a byte for indicating an error value, and the number of subbytes included in this byte is the same as the number of subbytes included in the error value byte included in the register value. The second value is the value in the byte for indicating the error value included in the first fault value. The order of the second values ​​in the first fault value is the same as the order of the first subbytes in the error value byte.

[0054] It should be noted that the second value may also be a value included in the first fault value generated when a component included in the target processor has an error other than an MCE type error, that is, a first fault.

[0055] In the above embodiment, the second value may include 0xC3, 0x04, 0x07, 0x08, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, and 0x3F. When the second value has the same value as the first value, the target fault may be considered to be a non-machine check exception fault.

[0056] In the above embodiment, when the values ​​included in the first value and the second value are different, whether the target fault is a machine check exception fault can be further determined based on the error value byte. For example, whether the target fault is a machine check exception fault can be determined based on the second subbyte included in the error value byte. Further parsing the error value byte and determining whether the target fault is a machine check exception fault based on the error value byte can improve the accuracy of determining whether the target fault is a machine check exception fault.

[0057] In one exemplary embodiment, determining whether the target fault is a machine check exception fault based on the error value byte includes: determining a second subbyte included in the error value byte; and determining whether the target fault is a machine check exception fault based on the second subbyte and the first value. In this embodiment, when the values ​​included in the first and second values ​​are different, whether the target fault is a machine check exception fault can be determined based on the second subbyte and the first value included in the error value byte, that is, the determination is made based on the combination of the first subbyte and the second subbyte of the error value byte. When determining a machine check exception fault, the error value bytes can be parsed one by one. When the first subbyte is sufficient to determine whether the target fault is a machine check exception fault, no further determination is required. When the first subbyte is insufficient to determine whether the target fault is a machine check exception fault, further parsing the next byte is performed, rather than parsing the values ​​in all error value bytes. This improves the accuracy of determining the type of machine check exception fault and saves computing power.

[0058] In one exemplary embodiment, determining whether the target fault is a machine check exception fault based on the second subbyte and the first value includes: determining a third value, wherein the third value is a value included in a second fault value stored in a target register when the firmware included in the device where the target processor is located has a second fault, the value of a byte included in the second fault value for indicating a fault type is the same as the value of an event type byte, the value of a byte included in the second fault value for indicating a fault order is the same as the value of an event order byte, and the order of the third value in the second fault value is the same as the order of the first value in the register value; determining a fourth value of the second subbyte when the first value and the third value are the same; and determining whether the target fault is a machine check exception fault based on the fourth value. In this embodiment, when the firmware included in the device where the target processor is located has a second fault, the second fault value can be written to the target register; the structure of the second fault value is the same as the structure of the register value, the value of the byte included in the second fault value for indicating a fault type is the same as the value of the event type byte, and the value of the byte included in the second fault value for indicating a fault order is the same as the value of the event order byte. The third value in the second fault value may be the first subbyte in a byte in the second fault value that indicates an error value, i.e., the third value and the first value appear in the same order in their respective error value bytes. When the third value is the same as the first value, whether the target fault is a machine check exception fault may be determined based on the fourth value of the second subbyte.

[0059] In the above embodiment, the firmware included in the device where the target processor is located may include firmware included in the device where the target processor is located other than the components included in the target processor, and may also include components included in the target processor. When a component of a certain type included in the target processor experiences a fault other than an MCE type error, a second fault value may be written to the target register. When a firmware included in the device where the target processor is located other than the components included in the target processor experiences a certain type of error, a second fault value may also be written to the target register. The third value in the second fault value may be 0x05.

[0060] In the above embodiment, in order to prevent the fault from being mistakenly identified as a machine check exception fault when the above situation occurs, the first subbyte and the second subbyte can be combined and parsed, thereby improving the accuracy of determining the machine check exception error type.

[0061] In one exemplary embodiment, determining whether the target fault is a machine check anomaly fault based on the fourth value includes: if the fourth value differs from the target value, determining the target fault is a machine check anomaly fault; if the fourth value is the same as the target value, determining the target fault is not a machine check anomaly fault. In this embodiment, the target value may be 0. When the fourth value is non-0, the target fault may be determined to be a machine check anomaly fault. When the fourth value is 0, the target fault is considered not to be a machine check anomaly fault.

[0062] In an exemplary embodiment, determining whether the target fault is a machine check exception fault based on the second subbyte and the first value includes: determining a fifth value, wherein the fifth value is a value included in a third fault value stored in a target register when the firmware included in the device where the target processor is located has a third fault, the value of the byte included in the third fault value for indicating the fault type is the same as the value of the event type byte, the value of the byte included in the third fault value for indicating the fault order is the same as the value of the event order byte, and the order of the fifth value in the third fault value is the same as the order of the first value in the register value; and when the first value and the fifth value are the same, determining whether the target fault is a machine check exception fault based on the second subbyte and the third subbyte included in the error value byte. In this embodiment, when the firmware included in the device where the target processor is located has a third fault, the third fault value can be written to the target register; the structure of the third fault value is the same as the structure of the register value, and the value of the byte included in the third fault value for indicating the fault type is the same as the value of the event type byte, and the value of the byte included in the third fault value for indicating the fault order is the same as the value of the event order byte. The fifth value in the third fault value may be the first subbyte in a byte in the third fault value that indicates an error value, i.e., the fifth value and the first value appear in the same order in their respective error value bytes. When the fifth value is the same as the first value, whether the target fault is a machine check exception fault may be determined based on the second subbyte and the third subbyte.

[0063] In the above embodiment, the firmware included in the device where the target processor is located may include firmware included in the device where the target processor is located other than the components included in the target processor, and may also include components included in the target processor. When a certain type of fault other than an MCE type error occurs in a certain type of component included in the target processor, a third fault value may be written to the target register. When a certain type of error occurs in firmware included in the device where the target processor is located other than the components included in the target processor, a third fault value may also be written to the target register. The fifth value in the third fault value may be 0xFF.

[0064] In the above embodiment, in order to prevent the fault from being mistakenly identified as a machine check exception fault when the above situation occurs, the first subbyte, the second subbyte, and the third subbyte can be combined and parsed, thereby improving the accuracy of determining the machine check exception error type.

[0065] In an exemplary embodiment, determining whether a target fault is a machine check exception fault based on the second subbyte and the third subbyte included in the error value byte includes: determining a sixth value of the second subbyte, and determining a seventh value of the third subbyte; determining an eighth value and a ninth value, wherein the eighth value is a value included in the fourth fault value stored in the target register when the firmware included in the device where the target processor is located has a fourth fault, the value of the byte included in the fourth fault value for indicating the fault type is the same as the value of the event type byte, the value of the byte included in the fourth fault value for indicating the fault sequence is the same as the value of the event sequence byte, and the byte included in the fourth fault value for indicating the error value includes The value of the first-order subbyte enclosed is the same as the first value, the eighth value is the value located in the second-order subbyte included in the byte used to indicate the error value, and the ninth value is the value located in the third-order subbyte included in the byte used to indicate the error value. The order of the eighth value in the fourth fault value is the same as the order of the sixth value in the register value, and the order of the ninth value in the fourth fault value is the same as the order of the seventh value in the register value. If the sixth value is the same as the eighth value, and the seventh value is the same as the ninth value, the target fault is determined to be a machine check exception fault. If the sixth value is different from the eighth value, and / or the seventh value is different from the ninth value, the target fault is determined to be a non-machine check exception fault. In this embodiment, when the error value byte includes four subbytes, the four subbytes may be Evtdata1, Evtdata2, Evtdata3, and Evtdata4, respectively. The first subbyte may be Evtdata1, the second subbyte may be Evtdata2, and the third subbyte may be Evtdata4. Different subbyte values ​​can represent different error identifiers. The combination of multiple subbytes, or the error value byte, represents a specific fault code. When different firmware faults occur, different values ​​at different bytes can be generated based on the type of fault, forming the error value byte.

[0066] In the above embodiment, when the first value and the fifth value are the same, the sixth value of the second subbyte and the seventh value of the third subbyte can be further determined. When the firmware included in the device where the target processor resides has a fourth fault, a fourth fault value can be written to the target register. The structure of the fourth fault value is the same as the register value, and the value of the byte indicating the fault type included in the fourth fault value is the same as the value of the event type byte, and the value of the byte indicating the fault sequence is the same as the value of the event sequence byte. The eighth value in the fourth fault value can be the second subbyte in the byte indicating the error value in the fourth fault value, i.e., the eighth value and the sixth value have the same order in their respective error value bytes. The ninth value in the fourth fault value can be the third subbyte in the byte indicating the error value in the fourth fault value, i.e., the ninth value and the seventh value have the same order in their respective error value bytes. If the eighth value and the sixth value are the same, and the ninth value and the seventh value are the same, the target fault can be determined to be a machine check exception fault; otherwise, it is not a machine check exception fault.

[0067] In the above embodiment, the firmware included in the device where the target processor is located may include firmware included in the device where the target processor is located other than the components included in the target processor, and may also include components included in the target processor. When a certain type of fault other than an MCE type error occurs in a certain type of component included in the target processor, a fourth fault value may be written to the target register. When a certain type of error occurs in firmware included in the device where the target processor is located other than the components included in the target processor, a fourth fault value may also be written to the target register. The eighth and ninth values ​​in the fourth fault value may both be 0xFF.

[0068] In the above embodiment, by parsing the first subbyte, the second subbyte, and the third subbyte, it is determined whether the target fault is a machine check abnormality fault, thereby improving the accuracy of identifying the machine check abnormality fault.

[0069] In one exemplary embodiment, after determining whether the target fault is a machine check exception fault based on the error value byte included in the register value, the method further includes: if the target fault is determined to be a machine check exception fault, determining fault information related to the machine check exception fault; and recording the fault information in a target log. In this embodiment, the target log may be an SEL log. The register value is checked to determine whether an MCE error has occurred. If an MCE error has occurred, the corresponding MCE error information is recorded and displayed in the BMC's SEL log, facilitating user troubleshooting of the MCE error.

[0070] In the above embodiment, when it is determined that the target processor has an MCE error, the user can be reminded to replace the new processor to prevent the target processor from malfunctioning and causing the device where the target processor is located, such as a server, to malfunction.

[0071] In an exemplary embodiment, obtaining a register value stored in a target register of a target processor includes: determining a value acquisition period; polling the target register according to the value acquisition period to obtain the register value. In this embodiment, a periodic polling mechanism can be set up, and the BMC polls the target register according to the value acquisition period to obtain the register value. Among them, the value acquisition period can be 2s. It should be noted that this value is only an exemplary description, and this application does not limit this. The polling mechanism facilitates real-time tracking and positioning to determine whether a server failure has occurred, and facilitates express positioning of the root cause of the problem and the adoption of corresponding maintenance measures.

[0072] In an exemplary embodiment, before obtaining the register value stored in the target register of the target processor, the method further includes: determining a target frequency; and setting the bus clock frequency for communicating with the target register to the target frequency. In this embodiment, the clock frequency supported by the basic input and output system of the device where the target processor is located can be determined, the target frequency can be determined based on the clock frequency supported by the basic input and output system, and the bus clock frequency for communicating between the BMC and the target register can be set to the target frequency to improve the performance of the device where the target processor is located. The target frequency can be 100kHz. It should be noted that this value is only an example and is not limited in this application.

[0073] In the above embodiment, the generation type of MCE error information of the ARM architecture processor is determined by initializing the I2C bus frequency of 100 kHz for communication with the SCP through the BMC and reading the 0xDA register of the SCP through a periodic polling mechanism. The 6-byte values ​​returned by the 0xDA register of the SCP are verified one by one. According to different verification results, it is determined whether an MCE error has occurred and the results are displayed and recorded in the form of the BMC sel log. This facilitates R&D personnel and maintenance personnel to quickly provide solutions to the located problems, such as replacing the problematic CPU in the system, thereby improving the stability and security of system operation, improving operation and maintenance efficiency, and reducing the labor costs of operation and maintenance personnel.

[0074] In an exemplary embodiment, multiple registers can be set in the target processor, with different registers being used to store different contents, and an MCE fault register is included in the multiple registers. When a component included in the target processor fails with an MCE type error, the component that fails with the MCE type error can be controlled to store the fault value in the MCE fault register. The BMC can determine whether the MCE fault register is empty. If the MCE fault register is empty, it is determined that the target processor has not suffered an MCE type fault, i.e., a machine check exception fault. When the MCE fault register is not empty, it is determined that an MCE type error, i.e., a machine check exception fault, has occurred in the target processor. Therefore, when determining whether a machine check exception fault has occurred in the target processor, it is only necessary to determine whether the MCE fault register is empty, without having to make a judgment based on the value in the MCE fault register. This improves the efficiency of determining whether a machine check exception fault has occurred in the target processor.

[0075] In the above embodiment, when it is determined that the MCE fault register is not empty, it is determined that an MCE type error occurs in the target processor. Therefore, the value in the MCE fault register can be obtained and the fault can be located according to the value.

[0076] The following describes a method for determining a machine check exception error type of a processor in conjunction with an embodiment:

[0077] FIG4 is a flow chart of a method for determining a machine check exception error type of a processor according to an embodiment of the present application, and FIG5 is a swim-lane diagram of a method for determining a machine check exception error type of a processor according to an embodiment of the present application. As shown in FIG4-5, the above-mentioned 48-byte MCE error parsing scheme is distinguished by defining 6-byte values. The 6 bytes are designed with 1-byte event type, 1-byte event sequence number, and 4-byte error value for custom parsing. The parsing rules are as follows: whether the event type and time sequence number values ​​of the first 2 bytes of the 6 bytes are 0x128E, if not, it is not an MCE error type. If it is 0x128E, the subsequent 4 bytes need to be combined and judged one by one to confirm whether it is an MCE error. If the value of the third byte is 0xC3,0 If the error is 0x04, 0x07, 0x08, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, or 0x3F, it is not considered an MCE error. If it is not one of the above types, the third and fourth values ​​must be combined for evaluation. For example, if the third value is 0x05 and the fourth value is non-zero, it is considered an MCE error. If the third value is 0xFF and the fourth and sixth bytes are also 0xFF, it is considered an MCE error. Otherwise, it is not an MCE error. Similarly, if the first and second bytes are 0x078C, it is also classified as an MCE error. If the BMC interprets it as an MCE error, the server CPU must be replaced immediately to ensure safe and reliable operation. After the BMC interprets the MCE error, it will be recorded in the BMC SEL log and saved to remind users to update the device.

[0078] The implementation process is as follows:

[0079] 1) The BMC sets the I2C link for communication with the SCP to 100 kHz. At the same time, a periodic polling mechanism (reading the SCP register every 2 seconds) is used to poll the value of the SCP register 0xDA.

[0080] 2) The BMC parses the value of the 0xDA register read by SCP. Reading the 0xDA register returns 6 bytes of data.

[0081] 3) First, determine whether the obtained 6 bytes are 0x078C or 0x128E. If it is not the above value, it is a non-MCE error; if it is 0x078C, it is an MCE error; if it is 0x128E, it is necessary to further determine and process the read bytes 3 to 6;

[0082] 4) When the first and second values ​​are 0x128E, the third byte needs to be judged and processed. If it is not 0xC3, 0x04, 0x07, 0x08, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, or 0x3F, it is an MCE error. If it is 0x05 or 0xFF, the fourth and sixth bytes need to be judged and processed.

[0083] 5) If the third byte is 0x05 and the fourth byte is not 0x0, it is considered an MCE error type;

[0084] 6) If the third byte is 0xFF, the fourth byte is 0xFF, and the sixth byte is 0xFF, it is considered an MCE error type;

[0085] 7) If steps 3 through 6 do not occur, the value does not correspond to an MCE error and can be ignored. If it does, the BMC interprets the value as an MCE error and records it in the BMC SEL log for easy review to ensure server stability and reliability.

[0086] The corresponding numerical relationship of MCE error can be seen in Table 1.

[0087] Table 1

[0088] In the above embodiment, the I2C bus clock frequency for communicating with the SCP is set to 100 kHz during BMC initialization. During the operation phase after the server is started, a 2s polling mechanism is used to read the 6-byte value of the 0xDA register of the SCP. The first 2 bytes of the obtained 6 bytes are checked and verified. If they are not 0x078c or 0x128E, it is considered a non-MCE error. If they are 0x078c, it is considered an MCE error message and the BMC records it in the SEL log. If they are 0x128E, the 3rd, 4th and 6th bytes need to be checked. If the first 2 bytes are 0x078c or 0x128E, it is considered a non-MCE error. If they are 0x078c, it is considered an MCE error message and the BMC records it in the SEL log. If they are 0x128E, the 3rd, 4th and 6th bytes need to be checked. If the three bytes are not 0xC3, 0x04, 0x07, 0x08, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, or 0x3F, it is considered an MCE error and recorded in the SEL log. If the third byte is 0x05, the data of the fourth byte is checked to see if it is a non-zero value. If not, it is an MCE error. If otherwise, it is not an MCE error. If the third byte is 0xFF, the data of the fourth and fifth bytes are checked to see if they are 0xFF. If so, it is an MCE error. If not, it is not an MCE error and no SEL log information is recorded. Therefore, the key point of this patent is that the BMC initializes the I2C bus with a frequency of 100kHz and periodically polls for 2 seconds to read the 0xDA register of the SCP and obtain the returned 6 bytes of data. By verifying the different numerical states of the 6 bytes, it is determined whether an MCE error occurs and the corresponding MCE error information is recorded in the BMC's SEL log and displayed. At the same time, the polling mechanism facilitates real-time tracking and positioning to determine whether the server has a fault, which facilitates the rapid location of the root cause of the problem and the implementation of corresponding maintenance measures.

[0089] It should be noted that the values ​​of the above bytes or sub-bytes are only exemplary. Different components may generate different values ​​when different types of failures occur. The values ​​generated when different types of failures occur in each component may be pre-configured.

[0090] This embodiment further provides a system for determining a machine check exception error type of a processor, configured to execute the method described in any one of the above embodiments. The system includes:

[0091] a target processor, the target processor including components;

[0092] a target register, wherein the target register is configured to store a fault value, the fault value comprising a value written to the target register when a component included in the target processor fails;

[0093] A baseboard management controller, wherein the baseboard management controller is configured to obtain a register value stored in a target register of a target processor, determine a fault type of a target fault occurring in the target processor based on an event type byte and an event sequence byte included in the register value, wherein the event type byte is a byte used to indicate an event type, and the event sequence byte is a byte used to indicate an order in which events occur, and when the fault type indicates that the type of the target fault is a first machine check exception error type, determine whether the target fault is a machine check exception fault based on an error value byte included in the register value, wherein the error value byte is a byte used to indicate an error value.

[0094] In the above embodiment, the target processor can be an ARM (Advanced RISC Machine) architecture processor. The target processor can be used in related fields of the electronics industry, such as automobiles and the Internet of Things. It can also be used in mobile phones, computers, servers, and other fields. CPUs based primarily on the ARM architecture have low energy consumption, which can achieve energy conservation. A schematic diagram of the target processor structure can be found in Figure 3. As shown in Figure 3, the target processor may include multiple components, which can be further divided into device components and bus components, such as memory bus devices, PCI link devices, ARM core chips, SMpro management components, PMpro management components, Mesh bus, OCM devices, CCIX bus, GIC, and other core key components. PCI (Peripheral Component Interconnect, a standard that defines local buses), SMpro is a system management controller, PMpro is a power management controller, Mesh is an internal CPU bus, OCM (On-Chip Memory), and CCIX (Cache Coherent Interconnect for Accelerators) are high-performance Internet protocols. GIC (Generic Interrupt Controller) is a general-purpose interrupt controller.

[0095] In the above embodiment, the target register can be an SCP (System Control Processor) register or a byte value register. The target register can store various fault values. The fault value can be stored in the target register in byte form. The fault value can correspond to 6 bytes, 8 bytes, etc. This application does not impose any restrictions on the number of bytes. When the fault value is 6 bytes, it can include an event type byte, an event order byte, and four error value bytes. The fault value includes the value written to the target register when a component included in the target processor fails. For example, when a component included in the target processor fails, the value written to the target register may include, but is not limited to, error information related to ARM architecture internal buses and components, such as Mesh bus errors, SMpro error information, PMpro error information, GIC interrupt errors, SMMU error information, CPM error information, and OCM error information. The fault value may also include the value written to the target register when other firmware in the device where the target processor is located fails. The device where the target processor is located may include an automobile, a computer, a mobile phone, a server, etc.

[0096] In the above embodiment, the ARM architecture processor contains multiple components, such as memory bus devices, PCI link devices, ARM core chips, SMpro management components, PMpro management components, Mesh bus, OCM devices, CCIX bus, GIC and other core key components. Once these components produce errors, they will inevitably cause serious or fatal errors to the ARM server system. Therefore, the error register values ​​of the ARM processor can be parsed according to certain rules. For example, the BMC (baseboard management controller) can perform polling on the SCP register of the ARM processor through the I2C bus to read the register value, and parse it according to certain rules to determine whether the target fault is a machine check abnormality fault. In the case of a machine check abnormality fault, the register value can be displayed in the BMC's sel log, which is convenient for rapid parsing and positioning to achieve efficient and rapid positioning of the processor fault location information.

[0097] In the above embodiment, the first machine check exception error type may be a fault type in a device component included in the target processor. In this case, the value of the event type byte may be 0x12, and the value of the event sequence byte may be 0x8E. That is, when the value of the first two bytes included in the register value is 0x128E, the first machine check exception error type may be a fault type in a device component included in the target processor. When a device component is faulty, the values ​​of the event type byte and event sequence byte in the register value generated may be the same as the values ​​of the event type byte and event sequence byte in the register value generated when other firmware in the device where the target processor is located fails. Therefore, further judgment can be made based on the error value bytes in the register value. This improves the accuracy of determining a machine check exception fault.

[0098] Through the present application, a register value stored in a target register of a target processor is obtained, wherein the target register is configured to store a fault value, the fault value including a value written to the target register when a component included in the target processor fails; the fault type of a target fault occurring in the target processor is determined based on an event type byte and an event sequence byte included in the register value, wherein the event type byte is a byte used to indicate the event type, and the event sequence byte is a byte used to indicate the order in which events occur; when the fault type indicates that the type of the target fault is a first machine check exception error type, whether the target fault is a machine check exception fault is determined based on an error value byte included in the register value, wherein the error value byte is a byte used to indicate the error value. Since when determining whether the target fault is a machine check exception fault, the register value in the target register can be analyzed to determine that the fault type of the target fault is the first machine check exception error type by determining the event type byte and the event sequence byte in the register value, further judgment is made based on the error value byte in the register value to determine whether the target fault is a machine check exception fault. By comprehensively determining whether the target fault is a machine check exception fault using the event type byte, event sequence byte, and error value byte, it is possible to effectively prevent other faults from being identified as machine check exception faults. This solves the problem of inaccurate determination of a processor's machine check exception error type in related technologies and improves the accuracy of determining the processor's machine check exception error type.

[0099] This embodiment further provides a server, comprising the system for determining the machine check exception error type of the processor in the above embodiment.

[0100] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus the necessary general hardware platform, and of course it can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art can be embodied in the form of a software product, which is stored in a non-volatile readable storage medium (such as ROM / RAM, magnetic disk, optical disk), including a number of instructions for enabling a terminal device (which can be a mobile phone, computer, server, or network device, etc.) to execute the methods of each embodiment of the present application.

[0101] In this embodiment, a device for determining the type of a machine check exception error of a processor is also provided. The device is used to implement the above-mentioned embodiments and preferred embodiments, and the details that have been described will not be repeated. As used below, the term "module" can refer to a combination of software and / or hardware that implements a predetermined function. Although the devices described in the following embodiments are preferably implemented in software, implementation using hardware, or a combination of software and hardware, is also possible and contemplated.

[0102] FIG6 is a structural block diagram of an apparatus for determining a machine check exception error type of a processor according to an embodiment of the present application. As shown in FIG6 , the apparatus includes:

[0103] an acquisition module 62 configured to acquire a register value stored in a target register of a target processor, wherein the target register is configured to store a fault value, the fault value including a value written to the target register when a component included in the target processor fails;

[0104] A first determination module 64 is configured to determine a fault type of a target fault occurring in a target processor based on an event type byte and an event order byte included in the register value, wherein the event type byte is a byte for indicating an event type, and the event order byte is a byte for indicating an event occurrence order;

[0105] The second determination module 66 is configured to determine whether the target fault is a machine check exception fault based on an error value byte included in the register value when the fault type indicates that the type of the target fault is a first machine check exception error type, wherein the error value byte is a byte used to indicate an error value.

[0106] In an exemplary embodiment, the apparatus is further configured to: determine that the target fault is a machine check exception fault if the fault type indicates that the type of the target fault is a second machine check exception error type.

[0107] In an exemplary embodiment, the second determination module 66 can determine whether the target fault is a machine check exception fault based on the error value byte included in the register value in the following manner: determine the first value of the first subbyte included in the error value byte; and determine whether the target fault is a machine check exception fault based on the first value.

[0108] In an exemplary embodiment, the second determination module 66 can determine whether the target fault is a machine check exception fault based on the first value in the following manner: determine a second value, wherein the second value is a value included in the first fault value stored in the target register when the firmware included in the device where the target processor is located has a first fault, the value of the byte included in the first fault value for indicating the fault type is the same as the value of the event type byte, the value of the byte included in the first fault value for indicating the fault order is the same as the value of the event order byte, and the order of the second value in the first fault value is the same as the order of the first value in the register value; when there is a value in the second value that is the same as the first value, determine that the target fault is not a machine check exception fault; when the values ​​included in the first value and the second value are different, determine whether the target fault is a machine check exception fault based on the error value byte.

[0109] In an exemplary embodiment, the second determination module 66 can determine whether the target fault is a machine check exception fault based on the error value byte in the following manner: determine the second subbyte included in the error value byte; and determine whether the target fault is a machine check exception fault based on the second subbyte and the first value.

[0110] In an exemplary embodiment, the second determination module 66 can determine whether the target fault is a machine check exception fault based on the second sub-byte and the first numerical value in the following manner: determine a third numerical value, wherein the third numerical value is the value included in the second fault value stored in the target register when there is a second fault in the firmware included in the device where the target processor is located, the numerical value of the byte included in the second fault value for indicating the fault type is the same as the numerical value of the event type byte, the numerical value of the byte included in the second fault value for indicating the fault order is the same as the numerical value of the event order byte, and the order of the third numerical value in the second fault value is the same as the order of the first numerical value in the register numerical value; when the first numerical value is the same as the third numerical value, determine the fourth numerical value of the second sub-byte; and determine whether the target fault is a machine check exception fault based on the fourth numerical value.

[0111] In an exemplary embodiment, the second determination module 66 can determine whether the target fault is a machine check abnormality fault based on the fourth numerical value in the following manner: when the fourth numerical value is different from the target numerical value, the target fault is determined to be a machine check abnormality fault; when the fourth numerical value is the same as the target numerical value, the target fault is determined to be a non-machine check abnormality fault.

[0112] In an exemplary embodiment, the second determination module 66 can determine whether the target fault is a machine check exception fault based on the second sub-byte and the first numerical value in the following manner: determine a fifth numerical value, wherein the fifth numerical value is the value included in the third fault value stored in the target register when there is a third fault in the firmware included in the device where the target processor is located, the numerical value of the byte included in the third fault value for indicating the fault type is the same as the numerical value of the event type byte, the numerical value of the byte included in the third fault value for indicating the fault order is the same as the numerical value of the event order byte, and the order of the fifth numerical value in the third fault value is the same as the order of the first numerical value in the register numerical value; when the first numerical value is the same as the fifth numerical value, determine whether the target fault is a machine check exception fault based on the second sub-byte and the third sub-byte included in the error value byte.

[0113] In an exemplary embodiment, the second determination module 66 can determine whether the target fault is a machine check exception fault based on the second subbyte and the third subbyte included in the error value byte in the following manner: determine the sixth value of the second subbyte, and determine the seventh value of the third subbyte; determine the eighth value and the ninth value, wherein the eighth value is the value included in the fourth fault value stored in the target register when the firmware included in the device where the target processor is located has a fourth fault, the value of the byte included in the fourth fault value for indicating the fault type is the same as the value of the event type byte, the value of the byte included in the fourth fault value for indicating the fault sequence is the same as the value of the event sequence byte, and the value of the byte included in the fourth fault value for indicating the error sequence is the same as the value of the event sequence byte. The value of the first-order subbyte included in the byte of the error value is the same as the first value, the eighth value is the value located in the second-order subbyte included in the byte used to indicate the error value, the ninth value is the value located in the third-order subbyte included in the byte used to indicate the error value, the order of the eighth value in the fourth fault value is the same as the order of the sixth value in the register value, and the order of the ninth value in the fourth fault value is the same as the order of the seventh value in the register value; when the sixth value is the same as the eighth value, and the seventh value is the same as the ninth value, the target fault is determined to be a machine check exception fault; when the sixth value is different from the eighth value, and / or the seventh value is different from the ninth value, the target fault is determined to be a non-machine check exception fault.

[0114] In an exemplary embodiment, the device is also used to determine whether the target fault is a machine check exception fault based on the error value byte included in the register value, and if the target fault is determined to be a machine check exception fault, determine the fault information of the machine check exception fault; and record the fault information in the target log.

[0115] In an exemplary embodiment, the acquisition module 62 may acquire the register value stored in the target register of the target processor in the following manner: determining a value acquisition cycle; and polling the target register according to the value acquisition cycle to acquire the register value.

[0116] In an exemplary embodiment, the apparatus is further configured to determine a target frequency before acquiring a register value stored in a target register of a target processor; and set a bus clock frequency communicating with the target register to the target frequency.

[0117] It should be noted that the above modules can be implemented through software or hardware. For the latter, it can be implemented in the following ways, but not limited to: the above modules are all located in the same processor; or the above modules are located in different processors in any combination.

[0118] An embodiment of the present application further provides a computer non-volatile readable storage medium, in which a computer program is stored, wherein the computer program is configured to execute the steps of any of the above method embodiments when running.

[0119] In an exemplary embodiment, the above-mentioned computer non-volatile readable storage medium may include but is not limited to: a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk, and other non-volatile readable storage media that can store computer programs.

[0120] An embodiment of the present application further provides an electronic device, comprising a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to execute the steps in any one of the above method embodiments.

[0121] In an exemplary embodiment, the electronic device may further include a transmission device and an input / output device, wherein the transmission device is connected to the processor, and the input / output device is connected to the processor.

[0122] The examples in this embodiment can refer to the examples described in the above embodiments and exemplary implementation modes, and this embodiment will not be described in detail here.

[0123] Obviously, those skilled in the art should understand that the modules or steps of the present application described above can be implemented using a general-purpose computing device, they can be concentrated on a single computing device, or distributed across a network composed of multiple computing devices, they can be implemented using program code executable by the computing device, and thus, they can be stored in a storage device and executed by the computing device, and in some cases, the steps shown or described can be performed in a different order than herein, or they can be fabricated into separate integrated circuit modules, or multiple modules or steps can be fabricated into a single integrated circuit module for implementation. Thus, the present application is not limited to any specific combination of hardware and software.

[0124] The above description is merely a preferred embodiment of the present application and is not intended to limit the present application. Various modifications and variations are possible for those skilled in the art. Any modifications, equivalent substitutions, improvements, etc. made within the principles of the present application shall be included within the scope of protection of the present application.

Claims

1. A method for determining a machine check exception error type of a processor, characterized in that: It includes: Obtain the register value stored in the target register of the target processor, where the target register is configured to store a fault value, and the fault value includes the value written into the target register when a component included in the target processor fails; Determine the fault type of the target fault that occurs in the target processor based on the event type byte and the event sequence byte included in the register value, where the event type byte is a byte used to indicate the event type, and the event sequence byte is a byte used to indicate the event occurrence sequence; When the fault type indicates that the type of the target fault is the first machine check exception error type, determine whether the target fault is a machine check exception fault based on the error value byte included in the register value, where the error value byte is a byte used to indicate the error value.

2. The method according to claim 1, characterized in that: The method further includes: When the fault type indicates that the type of the target fault is the second machine check exception error type, determine that the target fault is a machine check exception fault.

3. The method according to claim 1, characterized in that: The determining whether the target fault is a machine check exception fault based on the error value byte included in the register value includes: Determine the first value of the first sub-byte included in the error value byte; Determine whether the target fault is a machine check exception fault based on the first value.

4. The method according to claim 3, characterized in that: The determining whether the target fault is a machine check exception fault based on the first value includes: Determine a second value, where the second value is the value included in the first fault value stored in the target register when there is a first fault in the firmware included in the device where the target processor is located, the value of the byte used to indicate the fault type in the first fault value is the same as the value of the event type byte, the value of the byte used to indicate the fault sequence in the first fault value is the same as the value of the event sequence byte, and the order of the second value in the first fault value is the same as the order of the first value in the register value; When there is a value in the second value that is the same as the first value, determine that the target fault is not the machine check exception fault; When the values included in the first value and the second value are all different, determine whether the target fault is the machine check exception fault based on the error value byte.

5. The method according to claim 4, characterized in that: The determining whether the target fault is a machine check exception fault based on the error value byte includes: Determine the second sub-byte included in the error value byte; Determine whether the target fault is the machine check exception fault based on the second sub-byte and the first value.

6. The method according to claim 5, characterized in that: Determining whether the target fault is the machine check exception fault based on the second sub-byte and the first value includes: Determining a third value, where the third value is a value included in a second fault value stored in the target register when there is a second fault in the firmware included in the device where the target processor is located, the value of the byte for indicating the fault type included in the second fault value is the same as the value of the event type byte, the value of the byte for indicating the fault order included in the second fault value is the same as the value of the event order byte, and the order of the third value in the second fault value is the same as the order of the first value in the register value; When the first value is the same as the third value, determining a fourth value of the second sub-byte; Determining whether the target fault is the machine check exception fault based on the fourth value.

7. The method according to claim 6, wherein: Determining whether the target fault is the machine check exception fault based on the fourth value includes: When the fourth value is different from a target value, determining that the target fault is the machine check exception fault; When the fourth value is the same as the target value, determining that the target fault is not the machine check exception fault.

8. The method according to claim 5, wherein: Determining whether the target fault is the machine check exception fault based on the second sub-byte and the first value includes: Determining a fifth value, where the fifth value is a value included in a third fault value stored in the target register when there is a third fault in the firmware included in the device where the target processor is located, the value of the byte for indicating the fault type included in the third fault value is the same as the value of the event type byte, the value of the byte for indicating the fault order included in the third fault value is the same as the value of the event order byte, and the order of the fifth value in the third fault value is the same as the order of the first value in the register value; When the first value is the same as the fifth value, based on the second sub-byte and the third sub-byte included in the error value byte to determine whether the target fault is the machine check exception fault.

9. The method according to claim 8, wherein: Determining whether the target fault is the machine check exception fault based on the second sub-byte and the third sub-byte included in the error value byte includes: Determining a sixth value of the second sub-byte and determining a seventh value of the third sub-byte; Determine an eighth value and a ninth value, where the eighth value is the value included in the fourth fault value stored in the target register when there is a fourth fault in the firmware included in the device where the target processor is located. The value of the byte for indicating the fault type included in the fourth fault value is the same as the value of the event type byte. The value of the byte for indicating the fault order included in the fourth fault value is the same as the value of the event order byte. The value of the first order sub-byte included in the byte for indicating the error value included in the fourth fault value is the same as the first value. The eighth value is the value located in the second order sub-byte included in the byte for indicating the error value. The ninth value is the value located in the third order sub-byte included in the byte for indicating the error value. The order of the eighth value in the fourth fault value is the same as the order of the sixth value in the register value. The order of the ninth value in the fourth fault value is the same as the order of the seventh value in the register value; In the case where the sixth value is the same as the eighth value and the seventh value is the same as the ninth value, determine that the target fault is the machine check exception fault; In the case where the sixth value is different from the eighth value, and / or the seventh value is different from the ninth value, determine that the target fault is not the machine check exception fault.

10. The method according to claim 1, wherein: The determining the fault type of the target fault that occurs in the target processor based on the event type byte and the event order byte included in the register value includes: In the case where the data of the time type byte is 0x12 and the value of the event order byte is 0x8E, determine that the fault type of the target fault is the first machine check exception error type.

11. The method according to claim 1, wherein: The determining the fault type of the target fault that occurs in the target processor based on the event type byte and the event order byte included in the register value includes: In the case where the data of the time type byte is 0x07 and the value of the event order byte is 0x8C, determine that the fault type of the target fault is the second machine check exception error type.

12. The method according to claim 1, wherein: After determining whether the target fault is a machine check exception fault based on the error value byte included in the register value, the method further includes: In the case where it is determined that the target fault is the machine check exception fault, determine the fault information of the machine check exception fault; Record the fault information in a target log.

13. The method according to claim 1, wherein: Obtaining the register value stored in the target register of the target processor includes: Determine a value acquisition period; Poll the target register according to the value acquisition period to obtain the register value.

14. The method according to claim 1, wherein: Before obtaining the register value stored in the target register of the target processor, the method further includes: Determining a target frequency; Setting the bus clock frequency for communicating with the target register to the target frequency.

15. The method according to claim 14, wherein: The determining the target frequency includes: Determining the clock frequencies supported by the basic input / output system of the device where the target processor is located; Determining the target frequency according to the clock frequencies supported by the basic input / output system.

16. A system for determining a machine check exception error type of a processor, characterized in that, For performing the method according to any one of claims 1 to 15, including: A target processor, the target processor including components; A target register, wherein the target register is configured to store a fault value, and the fault value includes a value written into the target register when a component included in the target processor fails; A baseboard management controller, wherein the baseboard management controller is configured to obtain the register value stored in the target register of the target processor, and determine the fault type of the target fault that occurs in the target processor based on the event type byte and the event sequence byte included in the register value, wherein the event type byte is a byte for indicating the event type, the event sequence byte is a byte for indicating the event occurrence sequence, and in the case where the fault type indicates that the type of the target fault is the first machine check exception error type, determining whether the target fault is a machine check exception fault based on the error value byte included in the register value, wherein the error value byte is a byte for indicating the error value.

17. A server, characterized in that, A determining system for the machine check exception error type including the processor according to claim 16.

18. A determining device for the machine check exception error type of a processor, wherein: It includes: An obtaining module, configured to obtain the register value stored in the target register of the target processor, wherein the target register is configured to store a fault value, and the fault value includes a value written into the target register when a component included in the target processor fails; A first determining module, configured to determine the fault type of the target fault that occurs in the target processor based on the event type byte and the event sequence byte included in the register value, wherein the event type byte is a byte for indicating the event type, and the event sequence byte is a byte for indicating the event occurrence sequence; A second determining module, configured to, in the case where the fault type indicates that the type of the target fault is the first machine check exception error type, determine whether the target fault is a machine check exception fault based on the error value byte included in the register value, wherein the error value byte is a byte for indicating the error value.

19. A computer non-volatile readable storage medium, wherein: A computer program is stored in the computer non-volatile readable storage medium, and when the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 15 are implemented.

20. An electronic device, comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, wherein when the processor executes the computer program, the steps of the method described in any one of claims 1 to 15 are implemented.

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