Solar cell and manufacturing method therefor, and photovoltaic module

Abstract

Disclosed in the present application are a solar cell and a manufacturing method therefor, and a photovoltaic module. The solar cell comprises: a semiconductor substrate, which has a first surface and a second surface opposite to each other; and a first semiconductor layer, which is arranged on the first surface, and comprises a first part and a second part that is closely adjacent to the first part in a second direction, wherein the degree of crystallization of the first part is greater than that of the second part, and the first semiconductor layer is made of at least one of amorphous silicon, nanocrystalline silicon and microcrystalline silicon. By providing a rational crystallized area and a rational non-crystallized area on the first semiconductor layer, the overall cell efficiency of the solar cell is optimized by means of the higher degree of crystallization of the first part, thereby improving the cell efficiency; in addition, the passivation effect of the second part is ensured by means of the lower degree of crystallization of the second part, thereby preventing electric leakage.

Description

Solar cell and manufacturing method thereof, and photovoltaic module

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of the Chinese patent application number 202410092536.4 filed with the Chinese Patent Office on January 23, 2024, entitled “A solar cell, a method for preparing the same, and a battery assembly”, the priority of the Chinese patent application number 202410190935.4 filed with the Chinese Patent Office on February 20, 2024, entitled “A solar cell, a method for preparing the same, and a battery assembly”, and the priority of the Chinese patent application number 202411017051.5 filed with the Chinese Patent Office on July 26, 2024, entitled “ The application claims priority of the Chinese patent application entitled “A solar cell, a method for manufacturing the same, and a photovoltaic module”, the Chinese patent application number 202411231900.7 filed with the Patent Office of China on September 3, 2024, and entitled “A solar cell, a method for manufacturing the same, and a photovoltaic module”, and the Chinese patent application number 202411231282.6 filed with the Patent Office of China on September 3, 2024, and entitled “A solar cell, a method for manufacturing the same, and a photovoltaic module”, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present application relates to the field of photovoltaic technology, and in particular to a solar cell and a manufacturing method thereof, and a photovoltaic module. Background Art

[0004] In solar cell structures, laser treatment is used to treat the semiconductor layer on the velvet surface. Some semiconductor layers contain hydrogen. After absorbing light, the hydrogen-containing semiconductor layer heats up, allowing hydrogen in the semiconductor layer to escape, increasing the effective doping level. Laser treatment can also reduce the contact resistance of the solar cell, thereby reducing energy loss during current collection and improving cell efficiency. However, if the laser treatment area is not properly selected, it can lead to a greater risk of leakage in certain areas of the solar cell, affecting cell efficiency. Summary of the Invention

[0005] The purpose of this application is to provide a solar cell and a method for manufacturing the same, as well as a photovoltaic module, so as to reduce contact resistance while reducing leakage risk and improving battery efficiency.

[0006] In order to achieve the above objectives, this application provides the following technical solutions:

[0007] A solar cell comprising:

[0008] a semiconductor substrate having a first surface and a second surface opposite to each other;

[0009] The first semiconductor layer is arranged on the first surface, and the first semiconductor layer includes a first part and a second part adjacent to the first part along the second direction. The degree of crystallization of the first part is greater than the degree of crystallization of the second part. The first semiconductor layer includes at least one of amorphous silicon, nanocrystalline silicon, and microcrystalline silicon.

[0010] When the above technical solution is adopted, a crystallized structure is formed in the first part of the first semiconductor layer, so that the first part has a crystallized part and another part that is not crystallized. The first part is not entirely a crystallized structure, but mostly an amorphous structure, with only a portion forming a crystallized structure, such as a nanocrystal. The second part of the first semiconductor layer adjacent to the first part along the second direction is not crystallized, retaining the original amorphous structure (it should be noted that when the first semiconductor layer includes nanocrystalline silicon or microcrystalline silicon, the degree of crystallization or crystallinity of the nanocrystalline silicon or microcrystalline silicon in the second part remains unchanged), so that the overall degree of crystallization of the first part of the first semiconductor layer is greater than the overall degree of crystallization of the second part. It can be understood that, under the same other factors, when the degree of crystallization of the semiconductor layer is smaller, the grains in the semiconductor layer are smaller, and even the disorder of the amorphous silicon material is presented. The smaller the grains in the semiconductor layer, the more interfaces between the grains in the semiconductor layer, so the resistance of the grain interface will be greater. Therefore, the crystallized structure in the first part of the first semiconductor layer reduces the contact resistance, reduces the contact resistance between the first part and the conductive material (transparent conductive layer or electrode), and thus helps to reduce the transmission loss of the carriers collected in the first semiconductor layer to the conductive material. At the same time, the degree of crystallization of the second part of the first semiconductor layer is less than that of the first part, ensuring the passivation effect of the second part adjacent to the first part along the second direction, reducing the recombination of the edge of the first semiconductor layer, that is, for the back-contact solar cell, the second part of the first semiconductor layer is closer to the second semiconductor, and the degree of crystallization of the second part is smaller to ensure the passivation effect of the second part, preventing leakage between the second part and the second semiconductor layer. As can be seen from the above, by setting reasonable crystallized areas and amorphous areas on the first semiconductor layer, the higher degree of crystallization of the first part is utilized to optimize the overall cell efficiency of the solar cell, thereby improving the cell efficiency, while the lower degree of crystallization of the second part is utilized to ensure the passivation effect of the second part and prevent leakage.

[0011] In one implementation, the solar cell further includes a second semiconductor layer disposed on the first surface. The first semiconductor layer and the second semiconductor layer are arranged adjacent to each other along a second direction. The first semiconductor layer and the second semiconductor layer have different conductivity types. Furthermore, along the second direction, the second portion is closer to the second semiconductor layer than the first portion. The second semiconductor layer has a side surface adjacent to the first semiconductor layer. Using the above technical solution, for a back-contact solar cell, the second portion of the first semiconductor layer is closer to the second semiconductor layer, and the second portion has a lower degree of crystallization to ensure a passivation effect on the second portion, thereby preventing leakage between the second portion and the second semiconductor layer and reducing the solar cell's photoelectric conversion efficiency.

[0012] In one implementation, the second semiconductor layer includes a third portion and a fourth portion adjacent to the third portion along the second direction, the degree of crystallization of the third portion is greater than that of the fourth portion, and the second semiconductor layer includes at least one of amorphous silicon, nanocrystalline silicon, and microcrystalline silicon.

[0013] In one implementation, the second portion extends from the edge of the first portion along the second direction to near the adjacent side surface, but does not contact the adjacent side surface. This technical solution prevents the second portion from contacting the second semiconductor layer and allows for a greater distance between the second portion and the second semiconductor layer, further reducing the risk of electrical leakage between the second portion and the second semiconductor layer.

[0014] In one implementation, the second portion extends from the edge of the first portion to the adjacent side surface along the second direction and contacts the adjacent side surface. With this technical solution, the second portion overlaps at least a portion of the adjacent side surface of the second semiconductor layer. The second portion has a lower degree of crystallization, allowing weaker current to be transmitted through the second portion and the adjacent side surface of the second semiconductor layer. When the solar cell is shaded, the current can form a leakage path through the second portion and the adjacent side surface of the second semiconductor layer, preventing the shaded cell from becoming a load and consuming energy generated by other illuminated cells, thereby reducing the risk of hot spots.

[0015] In one implementation, along the second direction, the distance between the edge of the first portion and the adjacent side surface is greater than or equal to 20 μm. This arrangement ensures that the first portion, which has a stronger transmission circuit capability, is farther away from the second semiconductor layer, reducing the risk of leakage between the first portion and the second semiconductor layer.

[0016] In one implementation, a portion of the second portion is disposed on the second semiconductor layer to form an overlapping portion, and the second portion extends from an edge of the first portion to the overlapping portion along the second direction. In this technical solution, extending the second portion from the edge of the first portion to the overlapping portion can increase the ability to transmit current between the second portion and the second semiconductor layer. When the solar cell is blocked, current can form a leakage path through the second portion and the surface of the second semiconductor layer facing away from the semiconductor substrate. This leakage path has a stronger current transmission capability, further reducing the risk of hot spots.

[0017] In one implementation, the width of the second portion along the second direction is less than or equal to 500 μm and greater than or equal to 20 μm. With this configuration, if the second portion is too large, for example, greater than 500 μm, it will significantly block the second semiconductor layer, preventing effective current collection in the second semiconductor layer, and the leakage channel will be too large, resulting in a significant loss in battery efficiency. If the second portion is too small, for example, less than 20 microns, the laser will be difficult to control and may irradiate other parts (such as the second semiconductor layer), causing damage to other parts.

[0018] In one implementation, the solar cell further includes a first transparent conductive layer overlying the first semiconductor layer, wherein the projection of the first portion on the semiconductor substrate is completely within the projection of the first transparent conductive layer on the semiconductor substrate. This configuration improves the carrier transport capability of the first semiconductor layer, enabling good ohmic contact with the electrode and enhancing electrical conductivity. The first portion having a crystallized structure does not extend beyond the boundaries of the first transparent conductive layer, thereby reducing contact resistance within the effective conductive region of the first transparent conductive layer, improving electrical conductivity, and ultimately increasing cell efficiency.

[0019] In one implementation, along the second direction, the first transparent conductive layer extends to the adjacent side surface or to the second portion located above the second semiconductor layer. In this way, the first transparent conductive layer can cover a larger area of ​​the first semiconductor layer, further improving the conductive performance.

[0020] In one implementation, the solar cell further includes a second transparent conductive layer, the second transparent conductive layer overlying the second semiconductor layer; a PN isolation region is defined between the second transparent conductive layer and the first transparent conductive layer, the PN isolation region being located on the second semiconductor layer. The PN isolation region provides electrical insulation between the P region and the N region. The projection of the first portion is located within the boundary of the first transparent conductive layer, and therefore, the first portion does not enter the boundary of the PN isolation region. Consequently, the laser irradiation range does not enter the PN isolation region. Because the PN isolation region lacks a crystalline structure or has a low degree of crystallization, the electrical insulation effect of the PN isolation region is maintained.

[0021] In one implementation, a portion of the second portion is disposed on the second semiconductor layer to form an overlapping portion, and the PN isolation region is disposed on the overlapping portion.

[0022] In one implementation, the solar cell further comprises a third semiconductor layer disposed on the second surface, wherein the material of the third semiconductor layer comprises at least one of polycrystalline silicon, amorphous silicon, nanocrystalline silicon, or microcrystalline silicon, and the third semiconductor layer has a different conductivity type from the first semiconductor layer. In this arrangement, when the third semiconductor layer comprises an amorphous silicon layer, both sides of the semiconductor substrate are provided with a full-surface amorphous silicon layer, and the amorphous silicon layers on both sides can form a heterojunction structure, thereby forming a double-sided heterojunction cell. When the third semiconductor layer comprises polycrystalline silicon, a polycrystalline silicon layer passivation structure can be formed on the second side, and an amorphous silicon layer or a nanocrystalline silicon layer passivation structure can be formed on the first side, thereby forming a double-sided hybrid cell. As long as there is an amorphous silicon layer and / or a nanocrystalline silicon layer, the double-sided heterojunction cell and the double-sided hybrid cell can also be applied to the cell structure in which the edge is an amorphous structure and the middle region is a crystalline structure in the present application to improve cell efficiency.

[0023] In one implementation, the first portion and the second portion both extend in a strip shape along a first direction, and the first direction and the second direction intersect. Specifically, the first portion and the second portion are arranged in a substantially parallel strip shape, so that they can gradually move along the first direction during laser irradiation, which facilitates the laser irradiation formation of the first portion.

[0024] In one implementation, the contact resistance of the first portion is lower than the contact resistance of the second portion. Because the first portion can have a crystalline structure and the second portion has an amorphous structure, the effective doping of the crystalline structure of the first portion is increased, which can reduce the contact resistance of the first portion relative to the second portion, thereby reducing energy loss during current collection in the first portion and improving battery efficiency.

[0025] In one implementation, the first portion extends along the first direction to the edge of the first surface, so that the area of ​​the first portion can be maximized, the contact resistance can be reduced, and the current collection capability can be improved.

[0026] In one implementation, the second portion surrounds the first portion. With this arrangement, the second portion surrounding the first portion has a lower degree of crystallization, which can further reduce the risk of electrical leakage and ensure the photoelectric conversion efficiency of the solar cell.

[0027] In one implementation, the first portion is made of amorphous silicon and nanocrystalline silicon, while the second portion is made of amorphous silicon. This allows the second portion to have a better passivation effect. By properly arranging crystallized and amorphized regions on the first semiconductor layer, the overall efficiency of the solar cell is optimized, thereby improving the cell efficiency.

[0028] In one implementation, the semiconductor substrate includes a recessed portion on a first surface, the recessed portion being recessed relative to the remainder of the first surface toward the second surface, with the first portion located within the recessed portion. In this configuration, the recessed portion is formed by etching into the surface of the semiconductor substrate and typically has a textured surface. Positioning the first portion comprising amorphous silicon, nanocrystalline silicon, and / or microcrystalline silicon within the recessed portion increases the contact area of ​​the first portion, facilitating current collection.

[0029] In one implementation, the solar cell further includes a first gate line electrode, which is stacked above the first semiconductor layer, and a projection of the first gate line electrode on the semiconductor substrate overlaps with a projection of the first portion on the semiconductor substrate, and an area of ​​the projection of the first gate line electrode on the semiconductor substrate is smaller than an area of ​​the projection of the first portion on the semiconductor substrate.

[0030] A photovoltaic assembly includes a solar cell, wherein the solar cell is any one of the solar cells described above.

[0031] Since the photovoltaic module adopts the solar cell of the first aspect and any one of the above items, the photovoltaic module has the same beneficial effects as the first aspect, which will not be described in detail here.

[0032] The present application also provides a method for manufacturing a solar cell, comprising:

[0033] Providing a semiconductor substrate, the semiconductor substrate having a first surface and a second surface opposite to each other;

[0034] forming a first semiconductor layer on the first surface, wherein the first semiconductor layer includes at least one of amorphous silicon, nanocrystalline silicon, and microcrystalline silicon;

[0035] A laser is used to irradiate a first portion of the first semiconductor layer, and a second portion of the first semiconductor layer is not irradiated, so that the degree of crystallization of the first portion is greater than the degree of crystallization of the second portion; the first region and the second region are adjacent to each other along the second direction. When the above technical solution is adopted, the region corresponding to the first portion of the first semiconductor layer is crystallized by laser, so that the degree of crystallization is improved, while the region corresponding to the second portion of the first semiconductor layer adjacent to the first portion is not laser irradiated, retaining the amorphous structure (it should be noted that when the first semiconductor layer includes nanocrystalline silicon or microcrystalline silicon, the degree of crystallization or crystallinity of the nanocrystalline silicon or microcrystalline silicon of the second portion remains unchanged), so that the overall degree of crystallization of the first portion of the first semiconductor layer is greater than the overall degree of crystallization of the second portion. It can be understood that, under the same other factors, when the degree of crystallization of the semiconductor layer is smaller, the grains in the semiconductor layer are smaller, and even the disorder of amorphous silicon material is exhibited. The smaller the grains in the semiconductor layer, the more interfaces between the grains in the semiconductor layer, so the resistance of the grain interface will be greater. Therefore, the crystallized structure in the first part of the first semiconductor layer reduces the contact resistance, reduces the contact resistance between the first part and the conductive material (transparent conductive layer or electrode), and thus helps to reduce the transmission loss of the carriers collected in the first semiconductor layer to the conductive material. At the same time, the degree of crystallization of the second part of the first semiconductor layer is less than that of the first part, ensuring the passivation effect of the second part adjacent to the first part along the second direction, reducing the recombination of the edge of the first semiconductor layer, that is, for the back-contact solar cell, the second part of the first semiconductor layer is closer to the second semiconductor, and the degree of crystallization of the second part is smaller to ensure the passivation effect of the second part, preventing leakage between the second part and the second semiconductor layer. As can be seen from the above, by setting reasonable crystallized areas and amorphous areas on the first semiconductor layer, the higher degree of crystallization of the first part is utilized to optimize the overall cell efficiency of the solar cell, thereby improving the cell efficiency, while the lower degree of crystallization of the second part is utilized to ensure the passivation effect of the second part and prevent leakage.

[0036] In one implementation, the first semiconductor layer is an amorphous silicon layer. Laser irradiation of the first portion causes the amorphous silicon layer to partially crystallize into nanocrystals. Using an amorphous silicon layer for the first semiconductor layer provides better passivation in the portion not irradiated by the laser, and provides enhanced insulation in the isolation region.

[0037] In one implementation, before irradiating the first portion with a laser, the method further includes forming a second semiconductor layer on the first surface, wherein the first semiconductor layer and the second semiconductor layer are arranged adjacent to each other along a second direction, the first semiconductor layer and the second semiconductor layer have different conductivity types, and the second semiconductor layer has an adjacent side surface proximal to the first semiconductor layer, and the second portion is closer to the second semiconductor layer than the first portion. For a back-contact solar cell, the second portion of the first semiconductor layer is closer to the second semiconductor layer, and the second portion has a lower degree of crystallization to ensure a passivation effect on the second portion, thereby preventing leakage between the second portion and the second semiconductor layer and reducing the photoelectric conversion efficiency of the solar cell.

[0038] In one implementation, the first portion extends along a first direction and is strip-shaped. Irradiating the first portion with a laser includes: irradiating the first portion with the laser along the first direction, with the laser starting or ending at a first distance from the adjacent side surface along a second direction. An end of the second portion facing away from the first portion is spaced a certain distance from the adjacent side surface. The second portion does not contact the second semiconductor layer, and the distance between the second portion and the second semiconductor layer is relatively large, thereby further reducing the risk of leakage between the second portion and the second semiconductor layer.

[0039] In one implementation, along the first direction, the starting or ending position of the laser is a second distance from the boundary of the first semiconductor layer. The second distance is the extension distance of the second portion along the first direction. The second distance prevents the laser from irradiating both ends of the first semiconductor layer along the first direction, preserving the amorphous structure. This ensures a passivation effect at the edge portion and reduces recombination at the edge portion.

[0040] In one implementation, the second distance is greater than the first distance.

[0041] In one implementation, the wavelength of the laser is 325 nm to 532 nm; and / or the energy density of the laser is 200 mJ / cm 2 ~6000mJ / cm 2 . By setting this wavelength range, it can be absorbed by the amorphous semiconductor layer, which is conducive to the crystallization of the amorphous semiconductor layer. If the laser energy density is too high, the high temperature range will expand, and the temperature at the top of the velvet structure will be too high, thereby affecting the passivation of the top area of ​​the velvet structure. If the laser energy density is too small, the energy accumulation time is too long, affecting production efficiency, and the energy may not reach the energy required for crystallization. Therefore, by selecting the laser energy density in this range, it is possible to achieve high temperature only at the top of the velvet structure, achieve morphological changes, and form a crystallized structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0043] FIG1 is a schematic diagram of a solar cell provided in an embodiment of the present application;

[0044] FIG2 is a schematic diagram of another solar cell provided in an embodiment of the present application;

[0045] FIG3 is a schematic diagram of a partial arrangement of a transparent conductive layer on a first surface of a solar cell provided in an embodiment of the present application;

[0046] FIG4 is a partial enlarged view of FIG3 provided in an embodiment of the present application;

[0047] FIG5 is a schematic cross-sectional view of the BB section in FIG4 ;

[0048] FIG6 is a cross-sectional schematic diagram of the AA section in FIG4 ;

[0049] 7 to 18 are schematic flow charts of the steps of a method for manufacturing a solar cell provided in an embodiment of the present application;

[0050] FIG19 is a schematic diagram comparing EL test images of a solar cell provided by an embodiment of the present application (B in the figure) and a solar cell with a conventional amorphous region (C in the figure);

[0051] FIG20 is a schematic diagram comparing the contact resistance of the P region of the solar cell provided by the embodiment of the present application and the conventional solar cell without a crystallization region;

[0052] FIG21 is a schematic diagram of the crystallization of the pyramid top provided in an embodiment of the present application.

[0053] FIG22 is a schematic diagram of another solar cell provided in an embodiment of the present application.

[0054] Figure numerals: 100 is the first semiconductor layer, 1 is the first strip portion, 11 is the first part, 12 is the second part, 13 is the intrinsic amorphous silicon layer, 14 is the p-type amorphous silicon layer, 15 is the overlapping part, 2 is the second semiconductor layer, 201 is the third part, 202 is the fourth part, 21 is the tunneling oxide layer, 22 is the n-type doped polysilicon layer, 23 is the intrinsic polysilicon layer, 24 is the phosphosilicate glass layer, 25 is the silicon nitride mask layer, 3 is the edge isolation region, 4 is the first gate line electrode, 5 is the second gate line electrode, 6 is the semiconductor substrate, 7 is the transparent conductive layer, 71 is the first transparent conductive layer, 72 is the second transparent conductive layer, 73 is the third transparent conductive layer, 8 is the passivation layer, 9 is the anti-reflection layer, and 10 is the PN isolation region. DETAILED DESCRIPTION

[0055] In order to make the technical problems, technical solutions and beneficial effects to be solved by this application more clearly understood, this application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0056] It should be noted that when an element is referred to as being “fixed on” or “disposed on” another element, it may be directly on the other element or indirectly on the other element. When an element is referred to as being “connected to” another element, it may be directly connected to the other element or indirectly connected to the other element.

[0057] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, "multiple" means two or more, unless otherwise clearly and specifically defined. "Several" means one or more, unless otherwise clearly and specifically defined.

[0058] In the description of this application, it should be understood that the terms "up", "down", "front", "back", "left", "right", etc., indicating directions or positional relationships, are based on the directions or positional relationships shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction. Therefore, they should not be understood as limitations on this application.

[0059] In the description of this application, it should be noted that, unless otherwise expressly specified or limited, the terms "installed," "connected," and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium; they can refer to internal communication between two components or the interaction between two components. Those skilled in the art will understand the specific meanings of the above terms in this application based on the specific circumstances.

[0060] As shown in Figures 1-6, an embodiment of the present application provides a solar cell comprising a semiconductor substrate 6 and a first semiconductor layer 100. The semiconductor substrate 6 has a first surface and a second surface opposite each other. The first semiconductor layer 100 is disposed on the first surface of the semiconductor substrate 6. The first semiconductor layer 100 comprises a first portion 11 and a second portion 12, wherein the first portion 11 and the second portion 12 are adjacent to each other along a second direction. That is, along the second direction, both sides of the first portion 11 are adjacent to the second portion 12, or one side of the first portion 11 is adjacent to the second portion 12.

[0061] The degree of crystallization of the first portion 11 is greater than that of the second portion 12. The first semiconductor layer 100 includes at least one of amorphous silicon, nanocrystalline silicon, and microcrystalline silicon, that is, the first semiconductor layer 100 can be an amorphous silicon layer, a nanocrystalline silicon layer, or a microcrystalline silicon layer. Alternatively, the first semiconductor layer 100 can be a combination of any two or three of amorphous silicon, nanocrystalline silicon, and microcrystalline silicon. The degree of crystallization of amorphous silicon, nanocrystalline silicon, and microcrystalline silicon can be improved after laser crystallization. For example, when the first semiconductor layer 100 is an amorphous silicon layer, the laser crystallized portion will partially crystallize inside the amorphous silicon layer to form nanocrystalline grains. Nanocrystalline silicon refers to a crystalline structure in which most of the grains are nanometer-sized, for example, the grain size is less than 200 nm. When the first semiconductor layer 100 includes a nanocrystalline silicon layer or a microcrystalline silicon layer, the crystallinity or degree of crystallization of the laser crystallized portion of the first semiconductor layer 100 will increase.

[0062] In actual applications, the present embodiment does not specifically limit the material and conductivity type of the semiconductor substrate 6. For example, the semiconductor substrate 6 may be a silicon substrate. Alternatively, the semiconductor substrate 6 may be a substrate made of any semiconductor material, such as a silicon germanium substrate, a germanium substrate, or a gallium arsenide substrate. The conductivity type of the semiconductor substrate 6 may be an N-type semiconductor substrate, a P-type semiconductor substrate, or an intrinsic semiconductor substrate.

[0063] Secondly, the semiconductor substrate 6 has a first surface and a second surface opposite to each other. The first surface of the semiconductor substrate 6 can correspond to the light-facing surface of the solar cell, in which case the second surface of the semiconductor substrate 6 corresponds to the backlight surface of the solar cell; alternatively, the first surface of the semiconductor substrate 6 can correspond to the backlight surface of the solar cell, in which case the second surface of the semiconductor substrate 6 corresponds to the light-facing surface of the solar cell.

[0064] When the above technical solution is employed, a crystallized structure is formed within the first portion 11 of the first semiconductor layer 100, resulting in a crystallized portion and a non-crystallized portion within the first portion 11. The first portion 11 is not entirely crystallized, but rather mostly amorphous, with only a portion forming a crystallized structure, such as nanocrystals. A second portion 12 of the first semiconductor layer 100, adjacent to the first portion 11 along the second direction, remains uncrystallized, retaining its original amorphous structure (it should be noted that when the first semiconductor layer 100 comprises nanocrystalline silicon or microcrystalline silicon, the degree of crystallization or crystallinity of the nanocrystalline silicon or microcrystalline silicon in the second portion 12 remains unchanged). This results in the overall degree of crystallization of the first portion 11 of the first semiconductor layer 100 being greater than the overall degree of crystallization of the second portion 12. It is understood that, with other factors being equal, the smaller the degree of crystallization of the semiconductor layer, the smaller the grains in the semiconductor layer, and the layer may even exhibit the disordered nature of amorphous silicon. Furthermore, the smaller the grains in the semiconductor layer, the more interfaces there are between the grains, resulting in a higher resistance at the grain interfaces. Therefore, the crystallized structure in the first portion 11 of the first semiconductor layer 100 reduces contact resistance, thereby reducing the contact resistance between the first portion 11 and the conductive material (transparent conductive layer or electrode), thereby helping to reduce transmission losses of carriers collected in the first semiconductor layer 100 to the conductive material. At the same time, the degree of crystallization of the second portion 12 of the first semiconductor layer 100 is less than that of the first portion 11, ensuring a passivation effect of the second portion 12 adjacent to the first portion 11 along the second direction, and reducing recombination at the edge of the first semiconductor layer 100. That is, for a back-contact solar cell, the second portion 12 of the first semiconductor layer 100 is closer to the second semiconductor layer 2, and the degree of crystallization of the second portion 12 is less, thereby ensuring a passivation effect of the second portion 12 and preventing leakage between the second portion 12 and the second semiconductor layer 2. As can be seen from the above, by setting reasonable crystallization areas and amorphization areas on the first semiconductor layer 100, the higher degree of crystallization of the first part 11 is utilized to optimize the overall cell efficiency of the solar cell and improve the cell efficiency. At the same time, the lower degree of crystallization of the second part 12 is utilized to ensure the passivation effect of the second part 12 and prevent leakage.

[0065] It can be understood that when at least a portion of the first surface of the semiconductor substrate 6 is a velvet surface, a plurality of pyramid-like structures are formed on the velvet surface. As shown in FIG21 , the first semiconductor layer 100 is conformally arranged on the velvet surface, and the degree of crystallization of the portion of the first semiconductor layer 100 covering at least a portion of the top of the pyramid-like structure is greater than the degree of crystallization of the other portion of the first semiconductor layer 100 covering the base of the pyramid-like structure. In the process of observing the degree of crystallization of the first semiconductor layer 100, if the observed area is too small, the degree of crystallization of the first semiconductor layer 100 cannot be accurately obtained by observing only the base area of ​​the pyramid-like structure. Therefore, the observed area should contain at least one pyramid-like structure. Preferably, the observed area should be greater than or equal to 5*5μm. 2 This is to prevent the inability to accurately obtain the crystallization degree of the first semiconductor layer 100 by only observing the pyramid-like base region.

[0066] In some possible implementations, the contact resistance of the first portion 11 is lower than the contact resistance of the second portion 12. Because the first portion 11 has a crystalline structure or a higher degree of crystallization, and the second portion 12 has an amorphous structure or a lower degree of crystallization, the effective doping of the first portion 11 is increased, which can reduce the contact resistance of the first portion 11 relative to the second portion 12, thereby reducing energy loss during the current collection process of the first portion 11 and improving battery efficiency. For example, as shown in FIG20 , when the first semiconductor layer 100 is disposed in the P region, by comparing the P region contact resistance of a cell without a crystallized region and a cell with a crystallized region, it can be seen that the overall contact resistance of a solar cell having the first semiconductor layer 100 with the first portion 11 is lower than the overall contact resistance of a solar cell having the first semiconductor layer 100 without the first portion 11.

[0067] As shown in FIG1 , in this embodiment, the solar cell further includes a second semiconductor layer 2 disposed on the first surface. The first semiconductor layer 100 and the second semiconductor layer 2 are arranged adjacent to each other along the second direction. That is, the solar cell is a back-contact solar cell. The first semiconductor layer 100 and the second semiconductor layer 2 are both disposed on the first surface, and the first semiconductor layer 100 and the second semiconductor layer 2 are arranged adjacent to each other along the second direction. As shown in FIG4-FIG5 , the second semiconductor layer 2 has a side surface adjacent to the first semiconductor layer 100. Along the second direction, the second portion 12 is closer to the second semiconductor layer 2 than the first portion 11. That is, along the second direction, the second portion 12 is located between the first portion 11 and the second semiconductor layer 2. The first semiconductor layer 100 and the second semiconductor layer 2 have different conductivity types. To achieve the arrangement of P and N regions on the first surface, the first semiconductor layer 100 is one of a P region and an N region, and the second semiconductor layer 2 is the other of a P region and an N region.

[0068] By adopting the above technical solution, for the back-contact solar cell, the second part 12 of the first semiconductor layer 100 is closer to the second semiconductor layer 2, and the degree of crystallization of the second part 12 is relatively low to ensure the passivation effect of the second part 12, thereby preventing leakage between the second part 12 and the second semiconductor layer 2 and reducing the photoelectric conversion efficiency of the solar cell.

[0069] In the above technical solution, as shown in Figure 1, the first semiconductor layer 100 may include a plurality of first strip portions 1 extending along the first direction, and the second semiconductor layer 2 may include a plurality of second strip portions extending along the first direction. The first strip portions 1 and the second strip portions are alternately arranged along the second direction, and the first direction and the second direction intersect. In this embodiment, the first strip portion 1 extends as a whole along the first direction, and the width direction of the first strip portion 1 is the same as the second direction; along the width direction of the first strip portion 1, the first strip portion 1 includes a first portion 11 and a second portion 12 that are adjacent to each other, that is, the first portion 11 and the second portion 12 are arranged adjacent to each other along the width direction of the first strip portion 1, and the second portion 12 is arranged closer to the second strip portion, and the second portion 12 is located between the first portion 11 and the second strip portion, thereby preventing leakage between the second portion 12 and the second strip portion. In this embodiment, in the structure of the first strip portion 1, the second portion 12 can be provided on both sides of the first portion 11 along the second direction, further reducing the risk of leakage.

[0070] As shown in Figures 1 and 2, in this embodiment, both the first portion 11 and the second portion 12 are strip-shaped and extend along a first direction, intersecting the first and second directions. Specifically, the first portion 11 and the second portion 12 are arranged in a substantially parallel strip shape. This allows for gradual movement along the first direction during laser irradiation, facilitating the formation of the first portion 11 by laser irradiation.

[0071] As shown in FIG5 , in some embodiments, along the second direction, the second portion 12 extends from the edge of the first portion 11 to a position close to the adjacent side surface, but does not contact the adjacent side surface. Specifically, the second portion 12 extends from the edge of the first portion 11 to the region S3 in FIG5 , i.e., the end of the second portion 12 facing away from the first portion 11 is spaced a certain distance from the adjacent side surface. With this technical solution, the second portion 12 does not contact the second semiconductor layer 2, and the distance between the second portion 12 and the second semiconductor layer 2 is larger, which helps further reduce the risk of leakage between the second portion 12 and the second semiconductor layer 2.

[0072] As shown in FIG5 , in other embodiments, along the second direction, the second portion 12 extends from the edge of the first portion 11 to the adjacent side surface and contacts the adjacent side surface. Specifically, the second portion 12 extends from the edge of the first portion 11 to the S2 region in FIG5 , that is, the end of the second portion 12 facing away from the first portion 11 contacts the adjacent side surface, and the second portion 12 overlaps with at least part of the adjacent side surface. With this technical solution, the second portion 12 overlaps with at least part of the adjacent side surface of the second semiconductor layer 2, and the degree of crystallization of the second portion 12 is low. In this way, a weaker current can be transmitted through the adjacent side surfaces of the second portion 12 and the second semiconductor layer 2. When the solar cell is blocked, the current can form a leakage channel through the adjacent side surfaces of the second portion 12 and the second semiconductor layer 2, thereby preventing the blocked cell from becoming a load that consumes the energy generated by other illuminated cells, thereby reducing the risk of hot spots.

[0073] Furthermore, in the above technical solution, along the second direction, the distance between the edge of the first portion 11 and the adjacent side surface is greater than or equal to 20 μm. This arrangement ensures that the first portion 11, which has a stronger transmission circuit capability, is spaced farther from the second semiconductor layer 2, reducing the potential for leakage between the first portion 11 and the second semiconductor layer 2. For example, the distance between the edge of the first portion 11 and the adjacent side surface is 20 μm, 22 μm, 24 μm, 25 μm, 50 μm, 70 μm, 100 μm, etc.

[0074] As shown in FIG5 , in some other embodiments, a portion of the second portion 12 is disposed on the second semiconductor layer 2 to form an overlapping portion 15. That is, a portion of the second portion 12 extends to the upper side of the second semiconductor layer 2, and the portion of the second portion 12 located on the side of the second semiconductor layer 2 facing away from the semiconductor substrate 6 is the overlapping portion 15. Along the second direction, the second portion 12 extends from the edge of the first portion 11 to the overlapping portion 15. Specifically, the second portion 12 extends from the edge of the first portion 11 to the region S1 in FIG5 , that is, the end of the second portion 12 facing away from the first portion 11 contacts the side of the second semiconductor layer 2 facing away from the semiconductor substrate 6. Since the current transmission capability of the surface of the second semiconductor layer 2 facing away from the semiconductor substrate 6 is stronger than that of the adjacent side, in this technical solution, the second part 12 is extended from the edge of the first part 11 to the overlapping part 15, which can increase the current transmission capability between the second part 12 and the second semiconductor layer 2. When the solar cell is blocked, the current can form a leakage channel through the second part 12 and the surface of the second semiconductor layer 2 facing away from the semiconductor substrate 6. The leakage channel has a stronger current transmission capability, further reducing the risk of hot spots.

[0075] In some embodiments, the width of the second portion 12 along the second direction is less than or equal to 500 μm and greater than or equal to 20 μm. As shown in FIG5 , along the second direction, the extension distance of the second portion 12 is less than or equal to 500 μm and greater than or equal to 20 μm. In this configuration, if the width of the second portion 12 is set too large, for example, greater than 500 μm, it will block the second semiconductor layer 2 to a large extent, and effective current collection of the second semiconductor layer 2 cannot be formed. The leakage channel is too large, and the battery efficiency is greatly lost. If the width of the second portion 12 is set too small, for example, less than 20 microns, the laser crystallization process is difficult to control and may process other parts (such as the second semiconductor layer 2), causing damage to other parts. For example, the width of the second portion 12 along the second direction can be 100 μm, 90 μm, 80 μm, etc. Preferably, the width of the second portion 12 along the second direction is greater than or equal to 100 μm and less than or equal to 400 μm. Such a design allows the second portion 12 to at least partially contact the second semiconductor layer 2 to form a leakage channel, while not overlapping the second semiconductor layer 2 too much to reduce the current collection area of ​​the second semiconductor layer 2 .

[0076] As shown in Figures 3 and 4, in some possible implementations, the solar cell further includes a first transparent conductive layer 71 covering the first semiconductor layer 100, with the projection of the first portion 11 on the semiconductor substrate 6 completely located within the projection of the first transparent conductive layer 71 on the semiconductor substrate 6. This configuration improves the carrier transport capability of the first semiconductor layer 100 by providing the first transparent conductive layer 71, enabling good ohmic contact with the electrode and enhancing conductivity. The first portion 11 having a crystallized structure does not extend beyond the boundaries of the first transparent conductive layer 71, thereby reducing contact resistance within the effective conductive region of the first transparent conductive layer 71, improving conductivity, and increasing cell efficiency.

[0077] As shown in FIG5 , further, in the above technical solution, along the second direction, the first transparent conductive layer 71 extends to the adjacent side surface or extends to the second portion 12 located above the second semiconductor layer 2. Specifically, along the second direction, the first transparent conductive layer 71 can extend to the region S2 as shown in FIG5 , or the first transparent conductive layer 71 can extend to the region S1 as shown in FIG5 . With this arrangement, the first transparent conductive layer 71 can cover a larger area of ​​the first semiconductor layer 100, further improving the conductive performance.

[0078] As shown in Figures 3 and 4 , in some embodiments, the solar cell further includes a second transparent conductive layer 72, which covers the second semiconductor layer 2; a PN isolation region 10 is provided between the second transparent conductive layer 72 and the first transparent conductive layer 71, and the PN isolation region 10 is located on the second semiconductor layer 2. When the above technical solution is adopted, electrical insulation between the P region and the N region is achieved by the PN isolation region 10. The projection of the first portion 11 is located within the boundary of the first transparent conductive layer 71. Therefore, the first portion 11 does not enter the boundary of the PN isolation region 10, and the irradiation range of the laser does not enter the PN isolation region 10. Because the PN isolation region 10 does not have a crystallized structure or has a low degree of crystallization, the electrical insulation effect of the PN isolation region 10 is guaranteed.

[0079] As shown in Figures 3 and 4, the solar cell may further include a third transparent conductive layer 73, which covers a portion of the second portion 12. In this embodiment, the first transparent conductive layer 71 covers the first portion 11, and an edge isolation region 3 is provided between the first transparent conductive layer 71 and the third transparent conductive layer 73.

[0080] As shown in Figures 5 to 7 , the first transparent conductive layer 71, the second transparent conductive layer 72, and the third transparent conductive layer 73 can further be at least one of fluorine-doped tin oxide, aluminum-doped zinc oxide, tin-doped indium oxide, tungsten-doped indium oxide, molybdenum-doped indium oxide, cerium-doped indium oxide, and indium hydroxide. The transparent conductive layer can be a single-layer film or a laminated film.

[0081] For example, as shown in FIG5 , a portion of the second portion 12 is disposed on the second semiconductor layer 2 to form an overlapping portion 15, and the PN isolation region 10 is disposed on the overlapping portion 15. For example, when the second semiconductor layer 2 includes a stacked tunneling oxide layer 21 and an n-type doped polysilicon layer 22, and the first semiconductor layer 100 includes a stacked intrinsic amorphous silicon layer 13 and a p-type amorphous silicon layer 14, at the junction of the first semiconductor layer 100 and the second semiconductor layer 2, the first semiconductor layer 100 overlaps the second semiconductor layer 2 to form an overlapping portion 15. In this case, the PN isolation region 10 is located across the overlapping portion 15. The width of the overlapping portion 15 needs to be reasonably set, for example, it can be in the range of 100-300 μm, so as to achieve the balance between the leakage channel and the current collection as described above. The width of the second portion 12 directly affects the width of the overlapping portion 15 . Since the first portion 11 is at a certain distance from the adjacent side surface of the second semiconductor layer 2 , the width of the overlapping portion 15 should be preferably within the range of 100-300 μm.

[0082] In some embodiments, when the first surface of a solar cell comprises a first semiconductor layer 100 and a second semiconductor layer 2, that is, when the solar cell is a back-contact cell, the second semiconductor layer 2 may comprise amorphous silicon, nanocrystalline silicon, and / or microcrystalline silicon. The second semiconductor layer 2 has a structure similar to that of the first semiconductor layer 100, except for a different conductivity type. That is, the second semiconductor layer 2 also has a first portion and a second portion adjacent to each other along the second direction, specifically referred to below as the third portion 201 and the fourth portion 202. The third portion 201 of the second semiconductor layer 2 may or may not be entirely laser crystallized. For reference, see the above description of the first portion 11 of the first semiconductor layer 100, which will not be further elaborated here.

[0083] For example, taking the case where the first semiconductor layer 100 corresponds to the P region and the second semiconductor layer 2 corresponds to the N region, the first semiconductor layer 100 may include a first intrinsic amorphous silicon layer and a p-type amorphous silicon layer stacked together, and the second semiconductor layer 2 may include a second intrinsic amorphous silicon layer and an n-type amorphous silicon layer stacked together, with both the first intrinsic amorphous silicon layer and the second intrinsic amorphous silicon layer being disposed close to the semiconductor substrate 6. Of course, the conductivity types of the first semiconductor layer 100 and the second semiconductor layer 2 may be interchangeable, which will not be described in detail.

[0084] With this arrangement, the first semiconductor layer 100 and the second semiconductor layer 2, both of which have different conductivity types and are disposed on the first surface, can form a heterojunction structure, resulting in a heterojunction back-contact cell having both a P-region heterojunction structure and an N-region heterojunction structure on the back side. This cell has the advantages of a heterojunction structure with good passivation, high conversion efficiency, long service life, and low energy consumption. As long as it has an amorphous silicon layer and / or a nanocrystalline silicon layer, the heterojunction back-contact cell can also be applied to the cell structure described in this application with an amorphous structure at the edge and a crystalline structure in the middle region to improve cell efficiency.

[0085] As shown in Figures 1 to 6, in some embodiments, when the first surface of the solar cell has a first semiconductor layer 100 and a second semiconductor layer 2, that is, when the solar cell is a back-contact cell, the second semiconductor layer 2 can be at least one of a polycrystalline silicon layer, a nanocrystalline silicon layer and a microcrystalline silicon layer, and the first semiconductor layer 100 can be a heterojunction structure. When the second semiconductor layer 2 is a polycrystalline silicon layer, a tunneling passivation contact structure can be formed, and the second semiconductor layer 2 and the first semiconductor layer 100 have different conductivity types.

[0086] For example, the second semiconductor layer 2 may include a tunneling oxide layer 21 and a doped polysilicon layer stacked on the first surface, wherein the tunneling oxide layer 21 is disposed close to the semiconductor substrate 6. For example, when the second semiconductor layer 2 corresponds to the N region and the first semiconductor layer 100 corresponds to the P region, the doped polysilicon layer of the second semiconductor layer 2 is an n-type doped polysilicon layer 22. The first semiconductor layer 100 includes an intrinsic amorphous silicon layer 13 and a p-type amorphous silicon layer 14 stacked on the first surface, wherein the intrinsic amorphous silicon layer 13 is disposed close to the semiconductor substrate 6. Of course, when the second semiconductor layer 2 corresponds to the P region and the first semiconductor layer 100 corresponds to the N region, the doped polysilicon layer is a p-type doped polysilicon layer, and the doped amorphous silicon layer in the first semiconductor layer 100 is an n-type amorphous silicon layer.

[0087] In this way, by arranging a second semiconductor layer 2 and a first semiconductor layer 100 of different conductivity types on the first surface, a hybrid back contact cell having both a tunneling passivation contact structure and a heterojunction structure on the back is formed, wherein the first semiconductor layer 100 is a heterojunction structure. The cell has the advantages of high conversion efficiency, good stability, and low Auger recombination of the tunneling passivation contact structure and good passivation effect, high conversion efficiency, long service life, and low energy consumption for preparation of the heterojunction structure. As long as it has an amorphous silicon layer and / or a nanocrystalline silicon layer, the hybrid back contact cell can also be applied to the cell structure in which the edge is an amorphous structure and the middle area is a crystalline structure in the present application to improve the cell efficiency. Of course, when the second semiconductor layer 2 is other semiconductor layers, such as microcrystalline silicon or nanocrystalline silicon, a heterojunction structure can also be formed. By selecting different materials for the second semiconductor layer 2, a back contact cell with different structures in the P region and N region can be formed.

[0088] In other embodiments, the solar cell further includes a third semiconductor layer disposed on the second surface. The material of the third semiconductor layer includes at least one of polycrystalline silicon, amorphous silicon, nanocrystalline silicon, or microcrystalline silicon. The third semiconductor layer has a different conductivity type from the first semiconductor layer 100. For example, if the entire second surface is covered with an amorphous silicon layer, the third semiconductor layer may also form a heterojunction structure. The structure of the third semiconductor layer may be similar to that of the first semiconductor layer 100, similarly having a first portion 11 and a second portion 12, with the first portion 11 having a greater degree of crystallization than the second portion 12.

[0089] In one example, the conductivity type of the first semiconductor layer 100 is P-type and the conductivity type of the third semiconductor layer is N-type. The first semiconductor layer 100 includes a first intrinsic amorphous silicon layer and a p-type amorphous silicon layer stacked on the first surface, with the first intrinsic amorphous silicon layer disposed proximate to the first surface. The third semiconductor layer includes a third intrinsic amorphous silicon layer and an n-type amorphous silicon layer stacked on the second surface, with the third intrinsic amorphous silicon layer disposed proximate to the second surface, thereby forming a bifacial heterojunction cell. Of course, the conductivity type of the first semiconductor layer 100 can also be N-type, and the conductivity type of the third semiconductor layer can be P-type, which will not be further described.

[0090] In another example, a polysilicon layer is disposed on the second surface, and the third semiconductor layer can form a tunneling passivation contact structure. Specifically, the first semiconductor layer 100 has a P-type conductivity type and the third semiconductor layer has an N-type conductivity type. The first semiconductor layer 100 includes a first intrinsic amorphous silicon layer and a p-type amorphous silicon layer stacked on the first surface, with the first intrinsic amorphous silicon layer disposed proximate the first surface. The third semiconductor layer includes an N-type doped polysilicon layer disposed on the second surface, with a tunneling oxide layer disposed between the N-type doped polysilicon layer and the second surface. The tunneling oxide layer and the N-type doped polysilicon layer form a tunneling passivation contact structure. The third semiconductor layer can be disposed locally on the second surface, for example, in the form of multiple strips, forming a poly-finger structure. Doped field regions can be selectively formed on the substrate between the poly-finger structures. Alternatively, the third semiconductor layer can be formed entirely on the second surface, with only a thicker portion in the metallized contact area and a thinner portion in the non-metallized area. The first semiconductor layer 100 may be a heterojunction structure, thus forming a double-sided hybrid solar cell. Of course, the conductivity type of the first semiconductor layer 100 may also be N-type, and the conductivity type of the third semiconductor layer may be P-type, which will not be described in detail.

[0091] As long as they have an amorphous silicon layer, a nanocrystalline silicon layer and / or a microcrystalline silicon layer, bifacial heterojunction cells and bifacial hybrid solar cells can also be applied to the cell structure in which the degree of crystallization of the first part 11 is greater than that of the second part 12 in this application to improve cell efficiency.

[0092] In some possible implementations, as shown in FIG1 , the first portion 11 extends along the first direction to the edge of the first surface. That is, along the first direction, both ends of the first portion 11 extend to the edge of the first surface of the semiconductor substrate 6. This maximizes the area of ​​the first portion 11, reduces contact resistance, and improves current collection capability. It should be noted that because the portion of the first semiconductor layer 100 near the edge of the semiconductor substrate 6 has large defects, poor passivation, high leakage current, and severe recombination, the portion of the first portion 11 near the edge of the first surface of the semiconductor substrate 6 may not serve as a current collection area.

[0093] In other possible implementations, as shown in Figure 2 , the second portion 12 can surround the first portion 11. Specifically, the second portion 12 is disposed on both sides of the first portion 11, whether along the first direction or the second direction, completely surrounding the first portion 11. This arrangement allows the second portion 12 surrounding the first portion 11 to have a lower degree of crystallization, further reducing the risk of electrical leakage and ensuring the photovoltaic conversion efficiency of the solar cell.

[0094] In the above technical solution, the first portion 11 is rectangular and the second portion 12 is annular. That is, the first portion 11 located in the middle region corresponds to a rectangular shape, and the second portion 12 located in the edge region corresponds to a rectangular ring. The first semiconductor layer 100 can form a continuous structure covering the entire first surface. In this case, the first semiconductor layer 100 can form one side of a bifacial solar cell, serving as either a P region or an N region. Because the first semiconductor layer 100 includes amorphous silicon and / or nanocrystalline silicon, the first semiconductor layer 100 can form a heterojunction structure.

[0095] In the above technical solution, the width of the second portion 12, extending from the first portion 11 to the second portion 12 and perpendicular to the side length of the semiconductor substrate 6, is 0.3 mm to 12 mm. This means that a 0.3 mm to 12 mm edge region around the first portion 11 is reserved and not subjected to laser crystallization. If the width of the second portion 12 is too wide, the area of ​​the first portion 11 with the crystallized structure of the solar cell as a whole is smaller, resulting in less reduction in series resistance and greater current collection losses. If the width of the second portion 12 is too small, on the one hand, the edges of the first semiconductor layer 100 are thinner due to limitations of the coating process. On the other hand, the angle of laser irradiation at the edge of the solar cell is too large, resulting in deviations in the energy distribution within the laser spot. This can easily lead to excessive laser energy density in some areas, potentially damaging the passivation of the first semiconductor layer 100 at the edge. Therefore, considering the overall reduction in contact resistance of the solar cell and minimizing damage to the passivation, the width of the second portion 12 is selected to be 0.3 mm to 12 mm.

[0096] Furthermore, the width of the second portion 12 is 0.3 mm to 3 mm. This further increases the area of ​​the first portion 11 of the first semiconductor layer 100, reduces contact resistance, and improves battery efficiency. Specifically, the width of the second portion 12 can be 0.3 mm, 0.5 mm, 1 mm, 1.5 mm, 2 mm, 2.5 mm, 3 mm, etc.

[0097] For example, for the first semiconductor layer 100 including the plurality of first strip-shaped portions 1, along the extension direction (first direction) of the first strip-shaped portions 1, the extension lengths of the second portions 12 at both end edges of the first strip-shaped portions 1 are 1 mm, 1.2 mm, 1.5 mm, etc. Along the arrangement direction (second direction) of the plurality of first strip-shaped portions 1, the degree of crystallization of the two first strip-shaped portions 1 near the two side edges of the first surface is the same as the degree of crystallization of the second portions 12.

[0098] Optionally, the material of the first portion 11 includes at least one of amorphous silicon and nanocrystalline silicon, that is, the first portion 11 can be an amorphous silicon layer, a nanocrystalline silicon layer, or a combination of nanocrystalline silicon and amorphous silicon, and the degree of crystallization can be improved after laser crystallization. For example, when the first semiconductor layer 100 is an amorphous silicon layer, the laser crystallized portion will partially crystallize inside the amorphous silicon layer to form nanocrystalline grains. When the first semiconductor layer 100 is a nanocrystalline silicon layer or a combination of amorphous silicon and nanocrystalline, the crystallinity or degree of crystallization of the first semiconductor layer 100 will be increased in the laser crystallized portion.

[0099] The material of the second portion 12 can be amorphous silicon, so that the second portion 12 has a better passivation effect. By setting reasonable crystallization areas and amorphization areas on the first semiconductor layer 100, the overall cell efficiency of the solar cell is optimized and the cell efficiency is improved.

[0100] In some embodiments, when the first semiconductor layer 100 includes a plurality of first strip-shaped portions 1 extending along the first direction and the second semiconductor layer 2 includes a plurality of second strip-shaped portions extending along the first direction, the degree of crystallization of at least one first strip-shaped portion 1 near the edge of the first surface along the second direction is the same as the degree of crystallization of the second portion 12. With this arrangement, for the strip-shaped first strip-shaped portions 1, the plurality of first strip-shaped portions 1 are arranged along the second direction, and in the arrangement direction, the entire area of ​​at least one first strip-shaped portion 1 near the edge of the first surface has the same degree of crystallization as the second portion 12. That is, at least one first strip-shaped portion 1 near the edge is not laser crystallized, while the remaining first strip-shaped portions 1 form amorphous second portions 12 only at both side edges in the second direction, thereby achieving an amorphous structure at both side edges of the first semiconductor layer 100.

[0101] For example, in the second direction, the degree of crystallization of the entire area of ​​the two strip-shaped portions respectively located on the two edges of the first surface is the same as the degree of crystallization of the second part 12, or two, three or more first strip-shaped portions 1 having the same degree of crystallization as the second part 12 are reserved near the edge of each first surface.

[0102] As shown in Figures 5 and 6, in some possible implementations, the semiconductor substrate 6 includes a recessed portion on the first surface, the recessed portion including sidewalls and a bottom wall. The recessed portion is recessed relative to the remainder of the first surface toward the second surface, and the first portion 11 is located within the recessed portion. In this configuration, the recessed portion is formed by etching into the surface of the semiconductor substrate 6 and typically has a textured surface. Positioning the first portion 11, which comprises amorphous silicon, nanocrystalline silicon, and / or microcrystalline silicon, within the recessed portion increases the contact area of ​​the first portion 11, facilitating current collection.

[0103] In some embodiments, the side of the semiconductor substrate 6 on which the amorphous semiconductor layer is provided has a velvet structure, and the amorphous semiconductor layer is conformal to the velvet structure. The velvet structure has a light trapping effect, which increases the collection of light, and the velvet structure can achieve better contact with the electrode. When the first portion 11 of the first semiconductor layer 100 is laser crystallized, the laser is irradiated on the velvet structure of the first portion 11, and the crystallization temperature can be reached, so that a local area of ​​the first portion 11 forms a crystallized microcrystalline structure or nanocrystalline structure. In this way, the crystallized area has both an amorphous structure and a crystallized structure. The crystallized structure reduces the contact resistance, but reduces the passivation effect, and the recombination may increase, which is not conducive to the photoelectric efficiency. Therefore, by forming a crystallized structure in a local area of ​​a part of the velvet structure, the two factors of contact resistance and passivation effect can be balanced, so that the battery efficiency is optimized.

[0104] As shown in Figure 19, in this embodiment, the EL (electroluminescent) test of a solar cell is a method for detecting internal defects in solar cells. In the image obtained by the EL test, the brightness of the first portion 11, which has a relatively high degree of crystallization, is greater than that of the second portion 12, which has a relatively low degree of crystallization. Under the same conditions, the brightness of the first portion 11 in the EL test image is greater than that of the second portion 12, indicating that the contact resistance of the first portion 11 is lower than that of the second portion 12. When the solar cell is powered on for testing, the electroluminescent brightness of the first portion 11, which has a lower contact resistance, is higher, while the electroluminescent brightness of the second portion 12 is lower. The image of solar cell B in Figure 19 shows that the brightness of the first portion 11 of solar cell B is greater than that of the second portion 12. Comparing it with the image of solar cell C shows that the brightness of solar cell C is consistent across the entire surface and is lower overall than that of solar cell B, indicating that the overall contact resistance of solar cell C is higher.

[0105] In some possible implementations, the solar cell further includes a first gateline electrode 4 extending along a first direction, and the first gateline electrode 4 is conductively disposed on the first portion 11 of the first semiconductor layer 100. The first gateline electrode 4 extends in the same direction as the first strip-shaped portion 1, and is capable of collecting carriers from both the first portion 11 and a portion of the second portion 12 on the same first semiconductor layer 100. Thus, the first gateline electrode 4 can improve its ability to collect carriers from the first semiconductor layer 100.

[0106] For a solar cell having a second semiconductor layer 2, the solar cell further includes a second gate electrode 5 conductively disposed on the second semiconductor layer 2. The second gate electrode 5 extends along a first direction, which is consistent with the extension direction of the second semiconductor layer 2. In the case of a first transparent conductive layer 71 and a second transparent conductive layer 72, the first gate electrode 4 is disposed on the first transparent conductive layer 71, and the second gate electrode 5 is disposed on the second transparent conductive layer 72.

[0107] Furthermore, in this embodiment, along the second direction, the ratio of the width of the first gate electrode 4 to the width of the first portion 11 is 10% to 120%, and specifically can be 10%, 30%, 50%, 80%, 100%, 120%, etc. The ratio of the width of the first gate electrode 4 to the width of the middle portion is selected based on the material and carrier transport capability of the first semiconductor layer 100. If the carrier transport capability of the first semiconductor layer 100 is weak, the ratio of the width of the first gate electrode 4 to the width of the middle portion can be increased to increase the contact area between the first gate electrode 4 and the middle portion and reduce the contact resistance. Conversely, the ratio of the width of the first gate electrode 4 to the width of the middle portion can be reduced to save electrode material while still meeting current collection requirements.

[0108] For example, the width of the first gateline electrode 4 can be 30 μm to 600 μm. Specifically, when the first gateline electrode 4 is fabricated using a screen printing process, the width of the first gateline electrode 4 is 30 μm to 80 μm. When the first gateline electrode 4 is fabricated using a deposition method such as electroplating, the width of the first gateline electrode 4 is 100 μm to 600 μm. The width of the middle portion is 200 μm to 700 μm. The appropriate width of the first gateline electrode 4 is selected based on the width of the middle portion and the electrode fabrication process.

[0109] Furthermore, when the solar cell includes a first transparent conductive layer 71, the first gateline electrode 4 extends along the first direction and is disposed on the first transparent conductive layer 71. Along the second direction, the width of the first gateline electrode 4 is less than or equal to the width of the first transparent conductive layer 71, and the width of the first transparent conductive layer 71 is greater than the width of the middle portion. For example, the width of the first transparent conductive layer 71 is 120 μm to 800 μm, the width of the first portion 11 is 200 μm to 700 μm, and the ratio of the width of the first transparent conductive layer 71 to the width of the first portion 11 is 1.2 to 1.5. The width of the first transparent conductive layer 71 is selected appropriately based on the width of the first portion 11. The width of the first gateline electrode 4 is also selected appropriately based on the widths of the first portion 11, the first transparent conductive layer 71, and the electrode fabrication process. With this arrangement, the first gateline electrode 4 can be positioned directly opposite the first portion 11, with the width of the first transparent conductive layer 71 greater than the width of the middle portion, thereby improving current collection capability.

[0110] Based on the solar cell described in any of the above embodiments, an embodiment of the present application further provides a photovoltaic assembly, comprising the solar cell described in any of the above embodiments.

[0111] Since the photovoltaic module uses the solar cell described in any of the above embodiments, the photovoltaic module has the same beneficial effects as the above solar cell, which will not be described in detail here.

[0112] The present application also provides a method for manufacturing a solar cell. The method can be used to manufacture the solar cell described in Figures 1 to 6 and any of the above embodiments. The method comprises the following steps:

[0113] In step S100 , a semiconductor substrate 6 is provided. The semiconductor substrate 6 has a first surface and a second surface opposite to each other.

[0114] Step S200 , forming a first semiconductor layer 100 on the first surface, wherein the first semiconductor layer 100 includes at least one of amorphous silicon, nanocrystalline silicon, and microcrystalline silicon;

[0115] In step S300 , the first portion 11 of the first semiconductor layer 100 is irradiated with laser light, while the second portion 12 of the first semiconductor layer 100 is not irradiated, so that the degree of crystallization of the first portion 11 is greater than that of the second portion 12 ; the first portion 11 and the second portion 12 are adjacent to each other along the second direction.

[0116] When the above technical solution is adopted, a laser is used to perform crystallization treatment on the area corresponding to the first portion 11 of the first semiconductor layer 100, so that the degree of crystallization is improved, while the area corresponding to the second portion 12 of the first semiconductor layer 100 adjacent to the first portion 11 is not subjected to laser irradiation, and the amorphous structure is retained. (It should be noted that when the first semiconductor layer 100 includes nanocrystalline silicon or microcrystalline silicon, the degree of crystallization or crystallinity of the nanocrystalline silicon or microcrystalline silicon of the second portion 12 remains unchanged), so that the overall degree of crystallization of the first portion 11 of the first semiconductor layer 100 is greater than the overall degree of crystallization of the second portion 12. It can be understood that, under the same other factors, when the degree of crystallization of the semiconductor layer is smaller, the grains in the semiconductor layer are smaller, and it may even exhibit the disorder of amorphous silicon material. The smaller the grains in the semiconductor layer, the more interfaces between the grains in the semiconductor layer, so the resistance of the grain interface will be greater. Therefore, the crystallized structure in the first portion 11 of the first semiconductor layer 100 reduces contact resistance, thereby reducing the contact resistance between the first portion 11 and the conductive material (transparent conductive layer or electrode), thereby helping to reduce transmission losses of carriers collected in the first semiconductor layer 100 to the conductive material. At the same time, the degree of crystallization of the second portion 12 of the first semiconductor layer 100 is less than that of the first portion 11, ensuring the passivation effect of the second portion 12 adjacent to the first portion 11 along the second direction, and reducing recombination at the edge of the first semiconductor layer 100. That is, for a back-contact solar cell, the second portion 12 of the first semiconductor layer 100 is closer to the second semiconductor, and the degree of crystallization of the second portion 12 is less, thereby ensuring the passivation effect of the second portion 12 and preventing leakage between the second portion 12 and the second semiconductor layer 2. As can be seen from the above, by setting reasonable crystallization areas and amorphization areas on the first semiconductor layer 100, the higher degree of crystallization of the first part 11 is utilized to optimize the overall cell efficiency of the solar cell and improve the cell efficiency. At the same time, the lower degree of crystallization of the second part 12 is utilized to ensure the passivation effect of the second part 12 and prevent leakage.

[0117] Furthermore, before using the laser to irradiate the first portion 11, the following steps are further included:

[0118] In step S201, a second semiconductor layer 2 is formed on the first surface. The first semiconductor layer 100 and the second semiconductor layer 2 are arranged adjacent to each other along the second direction. The first semiconductor layer 100 and the second semiconductor layer 2 have different conductivity types, and the second semiconductor layer 2 has an adjacent side surface close to the first semiconductor layer 100. Compared with the first portion 11, the second portion 12 is closer to the second semiconductor layer 2.

[0119] In this embodiment, the solar cell is a back-contact solar cell. The first semiconductor layer 100 and the second semiconductor layer 2 are both disposed on the first surface, and the first semiconductor layer 100 and the second semiconductor layer 2 are disposed adjacent to each other along the second direction. As shown in Figures 4 and 5, the second semiconductor layer 2 has an adjacent side surface close to the first semiconductor layer 100. Compared to the first portion 11, the second portion 12 is closer to the second semiconductor layer 2. That is, along the second direction, the second portion 12 is located between the first portion 11 and the second semiconductor layer 2. The first semiconductor layer 100 and the second semiconductor layer 2 have different conductivity types. To achieve the arrangement of P and N regions on the first surface, the first semiconductor layer 100 is one of the P and N regions, and the second semiconductor layer 2 is the other of the P and N regions.

[0120] By adopting the above technical solution, for the back-contact solar cell, the second part 12 of the first semiconductor layer 100 is closer to the second semiconductor layer 2, and the degree of crystallization of the second part 12 is relatively low to ensure the passivation effect of the second part 12, thereby preventing leakage between the second part 12 and the second semiconductor layer 2 and reducing the photoelectric conversion efficiency of the solar cell.

[0121] In some possible implementations, the first semiconductor layer 100 includes an amorphous silicon layer. After laser irradiation of a central portion, the amorphous silicon layer partially crystallizes to form nanocrystals. Using an amorphous silicon layer as the first semiconductor layer 100 provides a better passivation effect in the portion not irradiated by the laser, and provides a better insulation effect in the PN isolation region 10.

[0122] Furthermore, the first portion 11 extends along the first direction and is in a strip shape, and the step S300 of irradiating the first portion 11 with laser light specifically includes the following steps:

[0123] In step S301 , a laser is irradiated on the first portion 11 along a first direction, and along a second direction, a starting position or an ending position of the laser is at a first distance from an adjacent side surface.

[0124] When using the above technical solution, the second portion 12 extends from the edge of the first portion 11 to the region S3 in Figure 5. The first distance is the width of the region S3 along the second direction, that is, there is a certain distance between the end of the second portion 12 facing away from the first portion 11 and the adjacent side surface. The second portion 12 does not contact the second semiconductor layer 2, and the distance between the second portion 12 and the second semiconductor layer 2 is large, which helps further reduce the risk of leakage between the second portion 12 and the second semiconductor layer 2.

[0125] Furthermore, along the first direction, the starting or ending position of the laser is at a second distance from the boundary of the first semiconductor layer 100. Specifically, the second distance is the extension distance of the second portion 12 along the first direction. The second distance prevents the laser from irradiating both ends of the first semiconductor layer 100 along the first direction, thereby retaining the amorphous structure. Due to the non-uniformity of the laser's full width and the non-uniform thickness of the first semiconductor layer 100, when the laser acts on the edge portion of the first semiconductor layer 100, the laser damages the passivation of the edge portion, thereby increasing the recombination of the edge portion. Therefore, the present application does not form a crystallized structure at both ends of the first semiconductor layer 100 through laser, retaining the amorphous structure of the first semiconductor layer 100 at both ends, thereby ensuring the passivation effect at the edge portion and reducing the recombination of the edge portion.

[0126] In the above embodiment, the second distance is greater than the first distance, that is, the width of the second portion 12 along the first direction (the second portion immediately adjacent to the first portion along the second direction) is greater than the width of the second portion along the second direction. For example, the first distance is less than or equal to 500 μm, and the second distance is 0.3-12 mm.

[0127] In some embodiments, the wavelength of the laser is 325 nm to 532 nm. Specifically, the wavelength of the laser can be 325 nm, 450 nm, 532 nm, etc.; and / or the energy density of the laser is 200 mJ / cm 2 ~6000mJ / cm 2 Specifically, the energy density of the laser can be 200mJ / cm 2 , 500mJ / cm 2 、1000mJ / cm 2 , 2000mJ / cm 2 、3000mJ / cm 2 , 5000mJ / cm 2 、6000mJ / cm 2 Etc. The pulse width of the laser can be on the order of picoseconds to nanoseconds. By setting this wavelength range, the laser can be absorbed by the first semiconductor layer 100, which is conducive to the crystallization of the first semiconductor layer 100. If the laser energy density is too high, the high temperature range will expand, and the temperature at the top of the velvet structure will be too high, thereby affecting the passivation of the top area of ​​the velvet structure. If the laser energy density is too small, the energy accumulation time is too long, affecting production efficiency, and the energy may not reach the energy required for crystallization. Therefore, by selecting the laser energy density in this range, it is possible to achieve high temperature only at the top of the velvet structure, achieve morphological changes, and form a crystallized structure.

[0128] As shown in FIG7 to FIG18 , this embodiment provides a specific process for manufacturing a solar cell. Taking the preparation of a hybrid back-contact cell having a tunneling passivation contact structure and a heterojunction structure on the back as an example, the preparation process of the back-contact cell is as follows:

[0129] Step 1: As shown in FIG7 , the silicon wafer is polished and cleaned. Specifically, the silicon wafer is placed in a tank-type polishing and cleaning machine for polishing to remove the cutting damage layer of the silicon wafer. The polishing morphology of both sides is regulated by controlling the temperature, time, and concentration of the chemical solution. The obtained silicon wafer is used as a semiconductor substrate 6, which can be an n-type, p-type, or intrinsic silicon substrate.

[0130] Step 2: As shown in FIG8 , a tunneling oxide layer 21 and an intrinsic polysilicon layer 23 are sequentially formed on the backlight surface of the semiconductor substrate 6, wherein the tunneling oxide layer 21 is a SiOx layer. The tunneling oxide layer 21 and the intrinsic polysilicon layer 23 are formed using one or more processes such as low-pressure chemical vapor deposition, plasma chemical vapor deposition, physical chemical vapor deposition, or plasma-enhanced atomic layer deposition. In addition, the tunneling oxide layer 21 can be formed by a high-temperature reaction of oxygen with the semiconductor substrate 6, or by a wet chemical method, such as a reaction of silicon with ozone, or an oxidation reaction of silicon with nitric acid. The thickness of the tunneling oxide layer 21 is 1 nm to 4 nm, and optionally, the thickness is 1.4 nm. The thickness of the intrinsic polysilicon layer 23 is 30 nm to 250 nm, and optionally, the thickness is 120 nm.

[0131] Step 3: As shown in FIG9 , the intrinsic polysilicon layer 23 is doped by high temperature diffusion to form an n-type doped polysilicon layer 22, and a phosphorus oxide layer, namely a phosphorus silicon glass layer 24, is generated. The doping concentration of the n-type doped polysilicon layer 22 is 1×10 19 cm -3 ~5×10 20 cm -3 .

[0132] Step 4: As shown in FIG10 , the phosphosilicate glass layer 24 formed after phosphorus diffusion is removed by using an HF solution.

[0133] Step 5: As shown in Figure 11, a silicon nitride mask layer 25 is deposited on the n-type doped polysilicon layer 22. The silicon nitride mask layer 25 acts as a hydrogen source, providing hydrogen atoms at the interface between the crystalline silicon and the tunnel oxide layer 21 to passivate dangling bonds and also passivates some defects within the crystalline silicon. It also serves as a mask to protect the N-region film layer during subsequent P-region patterning.

[0134] Step 6: As shown in FIG12 , the P region is patterned using a laser process, and all P region film layers are laser ablated until the semiconductor substrate 6 . The laser can be a 532 nm laser, and the pulse width can be a nanosecond or picosecond laser. Optionally, a 532 picosecond laser is used.

[0135] Step 7: As shown in Figure 13, the exposed semiconductor substrate 6 in the P region is textured using a wet etching process to obtain a textured structure, such as a pyramid structure. The silicon nitride mask layer 25 is then removed. This wet etching process serves two purposes: firstly, to remove the damaged layer of the semiconductor substrate 6 in the P region after laser treatment, thus cleaning the interface; and secondly, to remove the silicon nitride mask layer 25 deposited in the N region.

[0136] Step 8: As shown in Figure 14, an intrinsic amorphous silicon layer 13 and a p-type amorphous silicon layer 14 are sequentially deposited on the entire backlight surface of the semiconductor substrate 6 to form a P-region emitter. The intrinsic amorphous silicon layer 13 has a thickness of 2nm to 20nm, and optionally, a thickness of 8nm; the p-type amorphous silicon layer 14 has a thickness of 5nm to 50nm, and optionally, a thickness of 15nm. Simultaneously, a passivation layer 8 and an anti-reflection layer 9 are sequentially deposited on the front velvet surface of the semiconductor substrate 6. The anti-reflection layer 9 can be any combination of one or more of a silicon nitride layer, a silicon oxide layer, and a silicon oxynitride layer. The passivation layer 8 can be an intrinsic amorphous silicon layer or an aluminum oxide layer.

[0137] Step 9: As shown in Figure 15, the N region is patterned using a laser process to remove the intrinsic amorphous silicon layer 13 and the p-type amorphous silicon layer 14 on the n-type doped polysilicon layer 22, exposing the n-type doped polysilicon layer 22. An oxide layer will be generated on the n-type doped polysilicon layer 22, which will be removed by a wet etching process. The laser can use a 355nm or 532nm laser, and the pulse width can be a nanosecond or picosecond laser. Optionally, a 532 picosecond laser can be used. The wet etching process can use a chain device, with the semi-finished product facing up and protected by a water film. The back is in contact with the HF solution to remove the oxide layer and the silicon nitride plated on the back.

[0138] Step 10: As shown in FIG15 , a laser process is used to irradiate the corresponding area of ​​the first portion 11 of the p-type amorphous silicon layer 14 in the P region, so that the p-type amorphous silicon layer 14 forms a first portion having a crystallized structure, while the edge of the p-type amorphous silicon layer 14 along the second direction is not irradiated with laser, retaining the original amorphous structure to form a second portion 12. The laser can be a 355nm or 532nm laser, and the pulse width can be a nanosecond or picosecond laser. Optionally, a 532 picosecond laser is used. Specifically, the pulsed laser spot moves and irradiates along the extension direction of the p-type amorphous silicon layer 14. It should be noted that the laser processes in the ninth and tenth steps can be performed in the same step, and can be performed in no particular order. In order to save laser processing time, the crystallization process is performed after the P region is patterned by laser.

[0139] Step 11: As shown in FIG16 , a transparent conductive layer 7 is deposited on the backlight side of the semiconductor substrate 6. The transparent conductive layer 7 can be one or more of fluorine-doped tin oxide, aluminum-doped zinc oxide, tin-doped indium oxide, tungsten-doped indium oxide, molybdenum-doped indium oxide, cerium-doped indium oxide, and indium hydroxide, in a stacked or single layer. Optionally, a tin-doped indium oxide film layer can be used.

[0140] Step 12: As shown in FIG17 , the transparent conductive layer 7 on the N and P regions is disconnected to form a PN isolation region 10. The transparent conductive layer 7 is formed into a first transparent conductive layer 71 located on the P region and a second transparent conductive layer 72 located on the N region, thereby achieving insulation between the P and N regions. The transparent conductive layer 7 is disconnected near the edge of the semiconductor substrate 6 in the N and P regions, forming a third transparent conductive layer 73 located on the edge. The PN isolation region 10 between the P and N regions spans the overlapping area between the N and P regions and part of the p region to achieve better insulation.

[0141] Step 13: As shown in FIG18 , a first gate line electrode 4 and a second gate line electrode 5 are deposited on the first transparent conductive layer 71 in the P region and the second transparent conductive layer 72 in the N region, respectively. The first gate line electrode 4 has two ends extending onto the second portions 12 on both sides as shown in FIG1 . The first gate line electrode 4 and the second gate line electrode 5 can be made of silver, copper, aluminum, or a combination thereof.

[0142] In some embodiments, the second semiconductor layer 2 of the solar cell of the embodiments of the present application includes a third portion 201 and a fourth portion 202 adjacent to the third portion 201 along the second direction, wherein the degree of crystallization of the third portion 201 is greater than the degree of crystallization of the fourth portion 202. A portion of the second portion 12 of the first semiconductor layer 100 is disposed above the fourth portion 202 of the second semiconductor layer 2 to form an overlapping portion.

[0143] As shown in FIG22 , the solar cell according to an embodiment of the present application includes a semiconductor substrate 6, a first semiconductor layer 100, and a second semiconductor layer 2. The semiconductor substrate 6 has a first and second opposing surfaces. The first semiconductor layer 100 and the second semiconductor layer 2 are both disposed on the first surface of the semiconductor substrate 6. The first semiconductor layer 100 includes a first portion 11 and a second portion 12 adjacent to the first portion 11 along a second direction. The first portion 11 has a higher degree of crystallization than the second portion 12. The second semiconductor layer 2 includes a third portion 201 and a fourth portion 202 adjacent to the third portion 201 along the second direction. The third portion 201 has a higher degree of crystallization than the fourth portion 202. A portion of the second portion 12 of the first semiconductor layer 100 is disposed above the fourth portion 202 of the second semiconductor layer 2 to form an overlapping portion 15.

[0144] The second semiconductor layer 2 includes at least one of amorphous silicon, nanocrystalline silicon, and microcrystalline silicon. The formation method and structure of the third portion 201 and the fourth portion 202 are similar to those of the first portion 11 and the second portion 12, and are not described in detail here.

[0145] In other words, the solar cell of this embodiment includes a semiconductor substrate 6 (e.g., a silicon substrate), with a first region, a second region, and a third region adjacent to each other on one side of the semiconductor substrate 6. In the first region, a first semiconductor layer 100 and a first electrode 4 are sequentially stacked on the semiconductor substrate 6. The first semiconductor layer 100 is also referred to as a first doped layer. In the third region, a second semiconductor layer 2 and a second electrode 5 are sequentially stacked on the semiconductor substrate 6. The second semiconductor layer 2 is also referred to as a second doped layer. The first semiconductor layer 100 and the second semiconductor layer 2 have opposite conductivity. The first semiconductor layer 100 and the second semiconductor layer 2 extend into the second region. At least one of the first semiconductor layer 100 in the first region and the second semiconductor layer 2 in the third region has a crystallized region (a first portion 11 and a third portion 201). In the second region, at least a portion of the first semiconductor layer 100 is an amorphized region (a second portion 12), and at least a portion of the second semiconductor layer 2 is an amorphized region (a fourth portion 202). The second portion 12 and the fourth portion 202 form an overlapping portion 15 in the second region.

[0146] In some embodiments, when the first doped layer in the first region has a textured surface, only the raised portions of the textured surface in the laser irradiated region undergo crystal transformation, while the recessed portions do not undergo crystal transformation.

[0147] In some embodiments, when the first doped layer in the first region has a smooth surface, the first doped layer in the laser irradiation region undergoes crystal transformation.

[0148] In some embodiments, when the second doped layer in the third region has a textured surface, only the raised portions of the textured surface in the laser irradiated region undergo crystal transformation, while the recessed portions do not undergo crystal transformation.

[0149] In some embodiments, when the second doped layer in the third region has a smooth surface, the second doped layer in the laser irradiation region undergoes crystal transformation.

[0150] In the solar cell of this embodiment, since photogenerated carriers migrate and diffuse laterally (perpendicular to the thickness of the doped layers) and longitudinally (parallel to the thickness of the doped layers) in doped layers of different doping types, a high-resistivity second region is provided between the first semiconductor layer 100 in the first region and the second semiconductor layer 2 in the third region for isolation. This reduces lateral carrier migration and leakage. Furthermore, the first semiconductor layer 100 in the first region has a first portion 11 with a higher degree of crystallization, and the second semiconductor layer 2 in the third region has a third portion 201 with a higher degree of crystallization. These crystallized regions have good conductivity and are conducive to carrier collection. Furthermore, in the second region, the second portion 12 of the first semiconductor layer 100 has a lower degree of crystallization or is even an amorphous region, and the fourth portion 202 of the second semiconductor layer 2 has a lower degree of crystallization or is even an amorphous region. Amorphous regions have lower carrier mobility and lower sheet resistance than crystalline regions, significantly reducing leakage current.

[0151] In some embodiments, the solar cell further includes a first gateline electrode 4, which is stacked above the first semiconductor layer 100. The projection of the first gateline electrode 4 on the semiconductor substrate 6 overlaps with the projection of the first portion 11 on the semiconductor substrate 6, and the projection area of ​​the first gateline electrode 4 on the semiconductor substrate 6 is smaller than the projection area of ​​the first portion 11 on the semiconductor substrate 6. Generally speaking, the projection of the first gateline electrode 4 on the semiconductor substrate 6 completely falls within the projection range of the first portion 11 on the semiconductor substrate 6, thereby ensuring that the first gateline electrode 4 is in contact with the first portion 11.

[0152] As shown in FIG22 , the solar cell further includes a second gateline electrode 5. The first gateline electrode 5 is stacked above the second semiconductor layer 2, and the projection of the second gateline electrode 5 on the semiconductor substrate 6 overlaps with the projection of the third portion 201 on the semiconductor substrate 6. Furthermore, the projection area of ​​the second gateline electrode 5 on the semiconductor substrate 6 is smaller than the projection area of ​​the third portion 201 on the semiconductor substrate 6. Generally speaking, the projection of the second gateline electrode 5 on the semiconductor substrate 6 falls completely within the projection of the third portion 201 on the semiconductor substrate 6, thereby ensuring that the second gateline electrode 5 contacts the third portion 201.

[0153] In the solar cell of this embodiment, the projection of the first gateline electrode 4 on the semiconductor substrate 6 (e.g., a silicon substrate) overlaps with the projection of the first portion 11 on the semiconductor substrate 6, and the projection area of ​​the first gateline electrode 4 on the semiconductor substrate 6 is smaller than the projection area of ​​the first portion 11 on the semiconductor substrate 6. In some embodiments, the projection of the first gateline electrode 4 on the semiconductor substrate 6 (e.g., a silicon substrate) completely falls within the projection of the first portion 11 on the semiconductor substrate 6. The projection of the second gateline electrode 5 on the semiconductor substrate 6 overlaps with the projection of the third portion 201 on the semiconductor substrate 6, and the projection area of ​​the second gateline electrode 5 on the semiconductor substrate 6 is smaller than the projection area of ​​the third portion 201 on the semiconductor substrate 6. In some embodiments, the projection of the second gateline electrode 5 on the semiconductor substrate 6 (e.g., a silicon substrate) completely falls within the projection of the third portion 201 on the semiconductor substrate 6. With this arrangement, when photogenerated carriers are transmitted through the first semiconductor layer 100 / the second semiconductor layer 2 to the first gate line electrode 4 / the second gate line electrode 5, the current density here is the highest. Since the transmission efficiency of the first part 11 and the third part 201 is higher than that of the second part 12 and the fourth part 202, the larger the projected area of ​​the first part 11 and the third part 201 on the semiconductor substrate 6, the higher the transmission efficiency and the smaller the contact resistance.

[0154] The method for preparing the solar cell of the above embodiment includes the following steps:

[0155] Step 1: Polish and clean the silicon wafer, and perform texturing on the light-incident surface.

[0156] Step 2: PECVD is used to deposit a 5nm intrinsic hydrogenated amorphous silicon passivation layer, a 30nm amorphous n layer, a 100nm SiNx layer (refractive index 2.5), and a 30nm laser absorption layer on the back of the battery.

[0157] Step 3: Use laser to remove the laser absorption layer in the first region, thereby forming a laser opening to expose the SiNx layer.

[0158] Step 4: Perform a wet process, use 10% concentration hydrofluoric acid to remove the SiNx layer in the laser opening to expose the amorphous n layer, and use 10% concentration potassium hydroxide to remove the exposed amorphous n layer, the intrinsic hydrogenated amorphous silicon passivation layer underneath, and the laser absorption layer in the second and third regions, thereby exposing the silicon wafer in the first region and the silicon nitride layer in the second and third regions.

[0159] Step 5: On the back of the cell, a 5nm intrinsic hydrogenated amorphous silicon passivation layer and a 30nm amorphous p-layer are sequentially deposited on the silicon wafer in the first area, the silicon nitride layer in the second area, and the silicon nitride layer in the third area using PECVD technology.

[0160] Step 6: Use laser (the energy density of the laser spot is 200mJ / cm 2 ) removing the amorphous p-layer and the intrinsic hydrogenated amorphous silicon passivation layer in the third region to form an opening, thereby exposing the SiNx layer in the third region.

[0161] Step 7: Perform wet treatment and use 10% concentration hydrofluoric acid to remove the SiNx layer in the third area.

[0162] Step 8: Use PECVD to deposit an intrinsic hydrogenated amorphous silicon passivation layer and a SiNx anti-reflection film on the light-incident surface, with a refractive index of 2 and a thickness of 70nm.

[0163] Step 9: Perform laser crystallization treatment, using laser to crystallize the middle area of ​​the amorphous p layer in the first region into a nanocrystalline p region, that is, the first nanocrystalline silicon p-doped region and the first amorphous silicon p-doped region exist in the first region at the same time, the first amorphous silicon p-doped region surrounds the first nanocrystalline silicon p-doped region, and the part of the amorphous n layer and the electrode layer stacked in the third region is crystallized into a nanocrystalline n region.

[0164] Step 10: sequentially depositing a TCO layer and an Ag electrode (first gate electrode) on the nanocrystalline p-layer; and sequentially depositing a TCO layer and an Ag electrode (second gate electrode) on the nanocrystalline n-layer.

[0165] In the description of the above embodiments, specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.

[0166] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A solar cell, wherein, Comprising: A semiconductor substrate having opposite first and second surfaces; A first semiconductor layer disposed on the first surface, the first semiconductor layer including a first portion and a second portion adjacent to the first portion along a second direction, the degree of crystallization of the first portion being greater than that of the second portion, and the first semiconductor layer including at least one of amorphous silicon, nanocrystalline silicon, and microcrystalline silicon.

2. The solar cell according to claim 1, wherein, The solar cell further includes a second semiconductor layer disposed on the first surface, the first semiconductor layer and the second semiconductor layer being arranged adjacent to each other along the second direction, and the first semiconductor layer and the second semiconductor layer having different conduction types; And along the second direction, the second portion is closer to the second semiconductor layer than the first portion; The second semiconductor layer has an adjacent side surface close to the first semiconductor layer.

3. The solar cell according to claim 2, wherein, The second semiconductor layer includes a third portion and a fourth portion adjacent to the third portion along the second direction, the degree of crystallization of the third portion being greater than that of the fourth portion, and the second semiconductor layer including at least one of amorphous silicon, nanocrystalline silicon, and microcrystalline silicon.

4. The solar cell according to claim 2, wherein, Along the second direction, the second portion extends from the edge of the first portion to be close to the adjacent side surface but does not contact the adjacent side surface.

5. The solar cell according to claim 2, wherein Along the second direction, the second portion extends from the edge of the first portion to the adjacent side surface and contacts the adjacent side surface.

6. The solar cell according to claim 5, wherein, Along the second direction, the distance between the edge of the first portion and the adjacent side surface is greater than or equal to 20 μm.

7. The solar cell according to claim 2, wherein, A part of the second portion is disposed on the second semiconductor layer to form an overlapping portion, and along the second direction, the second portion extends from the edge of the first portion to the overlapping portion.

8. The solar cell according to claim 1, wherein, The width of the second portion in the second direction is less than or equal to 500 μm and greater than or equal to 20 μm.

9. The solar cell according to claim 2, wherein, The solar cell further includes a first transparent conductive layer covering the first semiconductor layer, and the projection of the first portion on the semiconductor substrate is completely within the projection of the first transparent conductive layer on the semiconductor substrate.

10. The solar cell according to claim 9, wherein, Along the second direction, the first transparent conductive layer extends to the adjacent side surface or extends to the second portion located above the second semiconductor layer.

11. The solar cell according to claim 9, wherein, The solar cell further includes a second transparent conductive layer covering the second semiconductor layer; There is a PN isolation region between the second transparent conductive layer and the first transparent conductive layer, and the PN isolation region is located on the second semiconductor layer.

12. The solar cell according to claim 11, wherein, A part of the second portion is disposed on the second semiconductor layer to form an overlapping portion, and the PN isolation region is disposed on the overlapping portion.

13. The solar cell according to claim 1, wherein, The solar cell further includes a third semiconductor layer disposed on the second surface, the material of the third semiconductor layer including at least one of polycrystalline silicon, amorphous silicon, nanocrystalline silicon, or microcrystalline silicon, and the third semiconductor layer having a different conduction type from the first semiconductor layer.

14. The solar cell according to claim 1, wherein, Both the first portion and the second portion extend in a strip shape along a first direction, and the first direction intersects the second direction.

15. The solar cell according to claim 1, wherein, The contact resistance of the first part is less than that of the second part.

16. The solar cell according to claim 1, wherein, The first part extends along a first direction to the edge of the first surface.

17. The solar cell according to claim 1, wherein, The second part surrounds the first part.

18. The solar cell according to claim 1, wherein, The material of the first part includes amorphous silicon and nanocrystalline silicon, and the material of the second part is amorphous silicon.

19. The solar cell according to claim 1, wherein, The semiconductor substrate includes a recessed portion on the first surface, the recessed portion is recessed in the direction of the second surface relative to the rest of the first surface, and the first part is located within the recessed portion.

20. The solar cell according to claim 1, wherein, The solar cell further includes a first grid electrode, the first grid electrode is stacked above the first semiconductor layer, and the projection of the first grid electrode on the semiconductor substrate overlaps with the projection of the first part on the semiconductor substrate, and the projection area of the first grid electrode on the semiconductor substrate is smaller than the projection area of the first part on the semiconductor substrate.

21. A photovoltaic module, comprising a solar cell, wherein, The solar cell is the solar cell according to any one of claims 1-20.

22. A method for manufacturing a solar cell, wherein, Comprising: Providing a semiconductor substrate having opposite first and second surfaces; Forming a first semiconductor layer on the first surface, the first semiconductor layer including at least one of amorphous silicon, nanocrystalline silicon, and microcrystalline silicon; Using a laser to irradiate a first part of the first semiconductor layer and not irradiating a second part of the first semiconductor layer, so that the degree of crystallization of the first part is greater than that of the second part; The first part and the second part are adjacent to each other along a second direction.

23. The method for manufacturing a solar cell according to claim 22, wherein, The first semiconductor layer is an amorphous silicon layer, and after using the laser to irradiate the first part, part of the amorphous silicon layer crystallizes to form nanocrystals.

24. The method for manufacturing a solar cell according to claim 22, wherein, Before using the laser to irradiate the first part, it further includes forming a second semiconductor layer on the first surface, the first semiconductor layer and the second semiconductor layer are arranged adjacent to each other along the second direction, the conduction types of the first semiconductor layer and the second semiconductor layer are different, and the second semiconductor layer has an adjacent side surface close to the first semiconductor layer, and the second part is closer to the second semiconductor layer than the first part.

25. The manufacturing method of the solar cell according to claim 24, wherein, The first part extends along the first direction and has a strip shape. Using the laser to irradiate the first part includes: the laser irradiates the first part along the first direction, and along the second direction, the starting or ending position of the laser is at a first distance from the adjacent side surface.

26. The manufacturing method of the solar cell according to claim 25, wherein, Along the first direction, the starting or ending position of the laser is at a second distance from the boundary of the first semiconductor layer.

27. The method for manufacturing a solar cell according to claim 26, wherein, The second distance is greater than the first distance.

28. The manufacturing method of a solar cell according to claim 22, wherein, The wavelength of the laser is 325nm - 532nm; and / or, the energy density of the laser is 200 mJ / cm 2 ~6000 mJ / cm 2 .

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