Amplification device

Abstract

This amplification device 1 includes a first amplification unit 10, a second amplification unit 20, an amplitude detection unit 30, and a control unit 40. The first amplification unit 10 can be set to any gain from among a plurality of discrete gains. The first amplification unit 10 converts an input current signal into a voltage signal on the basis of the set gain, and outputs the converted voltage signal to the second amplification unit 20. The second amplification unit 20 can be set to any gain within a continuously variable gain range. The second amplification unit 20 amplifies the voltage signal output from the first amplification unit 10 on the basis of the set gain, and outputs the amplified voltage signal. The control unit 40 controls the gain of each of the first amplification unit 10 and the second amplification unit 20 so that the amplitude detected by the amplitude detection unit 30 is constant.

Description

Amplification equipment

[0001] The present invention relates to an amplifier device.

[0002] Patent Documents 1 to 3 disclose inventions of devices that convert a current signal (e.g., a current signal output from a photodiode, which is a light-receiving element) into a voltage signal, amplify the voltage signal, and output the voltage signal. The amplification devices described in these documents include a first amplification unit that converts the current signal into a voltage signal and outputs the voltage signal, and a second amplification unit that amplifies and outputs the voltage signal output from the first amplification unit, and controls the voltage signal output from the second amplification unit to have a constant amplitude. However, conventional amplification devices, including those described in these documents, are difficult to use in, for example, computer network systems, which are expected to become more widespread in the future. This will be explained below using a data center server system as an example.

[0003] Current data center server systems include multiple racks, each containing multiple types of resources such as a CPU, GPU, and memory. Data transmission and reception occurs both within each rack and between different racks. Data transmission and reception within each rack is short distance, allowing connection using PCIe (Peripheral Component Interconnect Express), which allows for low-latency communication. However, data transmission and reception between different racks requires a maximum transmission distance of approximately 30 meters, so Ethernet (registered trademark) is used, but this has a large latency. In this configuration, when the processing capacity of a certain rack is at its limit, even if an attempt is made to distribute processing to another rack with spare processing capacity, the large latency in data transmission and reception between these two racks makes it difficult to improve processing capacity.

[0004] In server systems that are expected to become more widespread in the future, each rack will be a resource pool that collects one type of resource, such as a CPU, GPU, or memory, and the racks will be connected with low latency. Since all resource pools can be connected with each other with low latency, there will be no resources with excess processing capacity, making it possible to maximize processing capacity. This new server system is called resource-distributed computing, etc. In order to further improve processing capacity, higher speeds and lower power consumption will also be required.

[0005] PCIe 6.0 has been released as a new standard to meet the various requirements of server systems. This standard aims to achieve high speeds and low latency by adopting a lightweight forward error correction (FEC) method (3-way interleaved single symbol correction). This standard also requires a lower pre-FEC symbol error rate (SER) than conventional standards.

[0006] Furthermore, in conventional PCIe transmission, data is transmitted over copper wiring, but it is difficult to achieve the low-latency transmission over medium distances of approximately 30 meters required for resource-distributed computing. Therefore, it has been proposed to achieve medium-distance transmission by transmitting data via optical communication instead of copper wiring. However, optical communication has issues such as high power consumption and latency due to the use of a DSP. The DSP is used as an equalizer on the transmitting side, and as a distortion correction circuit on the receiving side.

[0007] When DSPs are not used to achieve low power consumption and low latency, it is important to suppress degradation of the transmission signal's eye. Meanwhile, PCIe 6.0 requires a smaller pre-FEC SER than conventional standards. This requires suppressing the noise component of the optical communication signal's eye. Furthermore, this requires reducing the noise of the optical communication receiver amplifier circuit, which must improve the signal-to-noise ratio on the optical signal receiving side.

[0008] US Patent No. 11249499 JP 2015-207923 A US Patent No. 11005573

[0009] As explained above using a data center server system as an example, in view of the future direction of signal transmission, it is important that various requirements be met in signal transmission via optical communications. However, the amplifiers described in Patent Documents 1 to 3 have difficulty meeting these requirements.

[0010] In the amplifier device described in Patent Document 1, the gain of the first amplifier is fixed, and the gain of the second amplifier is controlled so that the amplitude of the voltage signal output from the second amplifier is constant. With a first amplifier with a fixed gain, it is difficult to simultaneously meet the requirements for both low noise and a wide dynamic range.

[0011] That is, in the first amplifier section with a fixed gain, it is necessary to set the gain high to meet the demand for low noise, but in that case, if the amplitude of the input current signal is large, the output voltage signal will be distorted.In order to prevent the output voltage signal from being distorted even when the amplitude of the input current signal is large, it is necessary to set the gain low, but in that case, the noise characteristics will deteriorate.

[0012] In future optical communications, to meet the strong demand for low power consumption, it is expected that vertical cavity surface emitting lasers (VCSELs), which are advantageous for reducing power consumption, will be used as light-emitting elements on the transmitting side. However, VCSELs have large variations in their characteristics. For this reason, a wide input dynamic range is required for the first amplifier. Furthermore, as mentioned above, it is also required to reduce the pre-FEC SER. However, with a first amplifier with a fixed gain, it is difficult to simultaneously meet the demands for both low noise and a wide dynamic range.

[0013] In the amplifier device described in Patent Document 2, the first amplifier section and the second amplifier section can each be set to any gain within a continuous gain variable range, and the gains of the first amplifier section and the second amplifier section are controlled so that the amplitude of the voltage signal output from the second amplifier section is constant. This configuration can simultaneously meet the requirements for both low noise and a wide dynamic range.

[0014] However, when the input and output current signals and voltage signals are PAM4 signals, a flat frequency response is required over a wide input current range. However, if the gain of the first amplifier unit can be arbitrarily set within a continuous gain variable range, it is difficult to meet this requirement. Specifically, when the first amplifier unit that converts a current signal to a voltage signal is a feedback transimpedance amplifier (TIA), the input impedance is proportional to the gain (feedback resistance value), which significantly affects the dominant pole of the frequency response. Furthermore, when the first amplifier unit is a common-base TIA, the bias current flowing through the common-base amplifier changes, and the operating point (collector-emitter voltage) of the transistor also changes, which significantly affects the dominant pole of the frequency response due to changes in the transistor's f. Therefore, it is difficult to maintain a flat frequency response while performing continuous gain control.

[0015] In the amplifier device described in Patent Document 3, the first amplifier unit and the second amplifier unit can each be set to one of a plurality of discrete gains, and the gains of the first amplifier unit and the second amplifier unit are controlled so that the amplitude of the voltage signal output from the second amplifier unit is constant. With this configuration, it is possible to adjust the flatness of the frequency characteristics for each gain setting in the first amplifier unit.

[0016] However, to achieve a wide dynamic range, it is necessary to enable multiple gain settings in each of the first and second amplifiers, resulting in a large circuit size for the control unit for controlling the gains of the first and second amplifiers. In the amplifier device described in Patent Document 3, the first amplifier is set to one of more than 2,000 gains depending on the amplitude of the output voltage signal of the second amplifier. Furthermore, the second amplifier is set to one of multiple gains depending on the amplitude of the output voltage signal of the second amplifier and the gain of the first amplifier. Thus, the circuit size for the control unit for controlling the gains of the first and second amplifiers is large.

[0017] Furthermore, because PCIe 6.0 compatibility requires amplifiers to output large amplitudes, it is difficult to adopt an advanced CMOS process, which has limitations in terms of power supply voltage, and it is preferable to adopt a BiCMOS process. However, compared to advanced CMOS processes, the BiCMOS process has a larger logic scale, making it difficult to reduce the circuit area of ​​the control unit. As such, in the amplifier described in Patent Document 3, the control unit for controlling gain has a large circuit scale and circuit area, which increases costs. Future optical communications will require optical cable lengths of around 30 meters, which will be shorter than existing optical cables, and cost requirements will become even stronger than ever.

[0018] As described above, the amplifier devices described in Patent Documents 1 to 3 cannot meet the various requirements for future signal transmission by optical communications.

[0019] The present invention has been made to solve the above problems, and has as its object to provide an amplifier device that can meet various requirements for signal transmission by future optical communications.

[0020] A first aspect of the amplification device of the present invention comprises: (1) a first amplification unit in which one of a plurality of discrete gains is set, an input current signal is converted into a voltage signal based on the set gain, and the converted voltage signal is output; (2) a second amplification unit in which one of a plurality of gains is set from a continuous gain variable range, an input current signal is amplified based on the set gain, and the voltage signal output from the first amplification unit is output as an amplified voltage signal; (3) an amplitude detection unit in which the amplitude of the voltage signal output from the second amplification unit is detected; and (4) a control unit in which the gains of the first amplification unit and the second amplification unit are controlled so that the amplitude detected by the amplitude detection unit is constant.

[0021] In a second aspect of the amplification device of the present invention, in addition to the first aspect, the control unit controls the gain of the second amplification unit so that the amplitude detected by the amplitude detection unit is constant, and changes the gain of the first amplification unit when the gain of the second amplification unit falls outside the range of the continuous gain variable range that is equal to or greater than a first threshold and equal to or less than a second threshold.

[0022] In a third aspect of the amplification device of the present invention, in addition to the second aspect, the control unit changes the gain of the first amplification unit when the gain of the second amplification unit falls outside the range of greater than or equal to the first threshold and less than or equal to the second threshold after a certain period of time has elapsed since the gain of the first amplification unit was changed.

[0023] In a fourth aspect of the amplification device of the present invention, in addition to the second or third aspect, the control unit changes the gain of the first amplification unit to a gain that is smaller by a predetermined set value when the gain of the second amplification unit falls below a first threshold, and changes the gain of the first amplification unit to a gain that is larger by a predetermined set value when the gain of the second amplification unit exceeds a second threshold.

[0024] In a fifth aspect of the amplification device of the present invention, in addition to the second or third aspect, the control unit may change the gain of the first amplification unit to a gain that is smaller by a predetermined set value when the gain of the second amplification unit exceeds a first threshold, and may change the gain of the first amplification unit to a gain that is larger by a predetermined set value when the gain of the second amplification unit falls below a second threshold.

[0025] In a sixth aspect of the amplification device of the present invention, in addition to the second or third aspect, the control unit changes the gain of the first amplification unit to a gain that is smaller by a predetermined set value when the gain of the second amplification unit falls below a first threshold, and changes the gain of the first amplification unit to a maximum gain when the gain of the second amplification unit exceeds a second threshold.

[0026] In a seventh aspect of the amplification device of the present invention, in addition to the second or third aspect, the control unit may change the gain of the first amplification unit to a gain that is smaller by a predetermined set value when the gain of the second amplification unit exceeds a first threshold, and may change the gain of the first amplification unit to a maximum gain when the gain of the second amplification unit falls below a second threshold.

[0027] In an eighth aspect of the amplifying device of the present invention, in addition to any one of the first to seventh aspects, the control unit changes the impedance value or current value of an element included in the first amplifying unit according to the gain of the first amplifying unit.

[0028] A ninth aspect of the amplifying device of the present invention comprises a first amplifying section including a first variable gain amplifier having a digital gain control signal receiving terminal, an output signal detector connected to the output terminal of the first variable gain amplifier, and a variable impedance resistor-capacitor circuit connected between the output signal detector and the input terminal of the first variable gain amplifier, a second amplifying section including a second variable gain amplifier having an analog gain control signal receiving terminal, an amplitude detecting section connected to the output terminal of the second amplifying section, an input terminal connected to the output terminal of the amplitude detecting section, a first output terminal connected to the digital gain control signal receiving terminal, and a second output terminal connected to the analog gain control signal receiving terminal, and an automatic gain control section that outputs a digital gain control signal and an analog gain control signal in accordance with the output of the amplitude detecting section.

[0029] According to the present invention, it is possible to provide an amplifier device that can meet various requirements for future signal transmission by optical communications.

[0030] FIG. 1 is a diagram illustrating the configuration of the amplifying device 1. FIG. 2 is a diagram illustrating a first operation example of the amplifying device 1. FIG. 3 is a diagram illustrating a second operation example of the amplifying device 1. FIG. 4 is a diagram illustrating a third operation example of the amplifying device 1. FIG. 5 is a diagram illustrating a fourth operation example of the amplifying device 1. FIG. 6 is a diagram illustrating the gain G１ G ２ and the amplitude A of the input current signal ０ 7(a) and 7(b) are diagrams showing the relationship between G 1,1 = 1000Ω, G 1,2 = 500Ω, G 1,3 = 250Ω, the gain G of the first amplifier unit 10 １ and the gain G of the second amplifier 20 ２ 8(a) and 8(b) are diagrams showing examples of setting G 1,1 = 1000Ω, G 1,2 = 400Ω, G 1,3 = 200Ω, the gain G of the first amplifier unit 10 １ and the gain G of the second amplifier 20 ２ 9 is a diagram showing an example of setting. FIG. 9 is a diagram showing a schematic configuration of the first amplifier 10. FIG. 10 is a diagram showing an example of the circuit configuration of the first amplifier 10. FIG. 11 is a diagram showing an example of the configuration of the amplifying device 1. FIG. 12 is a diagram showing an example of the circuit configuration of the second amplifier 20.

[0031] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the description of the drawings, the same elements are designated by the same reference numerals, and duplicated explanations will be omitted.

[0032] FIG. 1 is a diagram showing the configuration of an amplifier device 1. The amplifier device 1 amplifies an input current signal (S ＩＮ ) is converted into a voltage signal (S ＯＵＴ The amplifying device 1 outputs a current signal, and includes a first amplifier 10, a second amplifier 20, an amplitude detector 30, and a controller 40. The current signal input to the amplifying device 1 is output from, for example, a light-receiving element. The light-receiving element is preferably a photodiode. The first amplifier 10 may include a transimpedance amplifier.

[0033] The first amplifier 10 can be set to any one of a plurality of discrete gains. The first amplifier 10 amplifies the input current signal (S ＩＮ) into a voltage signal, and outputs the converted voltage signal to the second amplifier 20.

[0034] The second amplifier 20 can be set to any gain within a continuous gain variable range. The second amplifier 20 amplifies the voltage signal output from the first amplifier 10 based on the set gain, and outputs the amplified voltage signal (S ＯＵＴ ) is output.

[0035] The gain of the first amplifier 10 is G １ [Ω], and the gain of the second amplifier 20 is G ２ The overall gain G of the amplifier device 1 is G = G １ G ２ The amplitude of the current signal input to the first amplifier 10 is A ０ The amplitude of the voltage signal output from the first amplifier 10 and input to the second amplifier 20 is V １ The amplitude of the voltage signal output from the second amplifier 20 is V ２ The relationship between these parameters is expressed by the following equation: V １ = A ０ G １ V ２ =V １ G ２ = A ０ G １ G ２ The amplitude detection unit 30 detects the amplitude V of the voltage signal output from the second amplification unit 20. ２ The control unit 40 detects the amplitude V ２ The gain G of the first amplifier 10 is set to be constant. １ and the gain G of the second amplifier 20 ２ Control.

[0036] The control unit 40 controls the gain G １ The first gain control signal (S ＣＯＮＴ１ ) to the first amplifier section 10. The first amplifier section 10 provides its first gain control signal (S ＣＯＮＴ１ ) is used to set one of a plurality of discrete gains. ＣＯＮＴ１) may be a digital signal having a number of bits corresponding to the number of gains that can be set by the first amplifier section 10.

[0037] The control unit 40 controls the gain G ２ A second gain control signal (S ＣＯＮＴ２ ) to the second amplifier section 20. The second amplifier section 20 provides its second gain control signal (S ＣＯＮＴ２ ) is used to set a gain within a continuous gain variable range. ＣＯＮＴ２ ) may be a voltage signal (analog signal) that can take on a value corresponding to a value within the continuous gain variable range of the second amplifier section 20.

[0038] In the amplifying device 1 having such a configuration, one of a plurality of discrete gains is set in the first amplifying section 10, so that it is possible to achieve both low noise and a wide dynamic range, and also to adjust the flatness of the frequency characteristics for each gain setting. Furthermore, because one of a plurality of discrete gains is set in the first amplifying section 10, while one of a plurality of gains is set in the second amplifying section 20 from a continuous gain variable range, it is possible to reduce the circuit scale of the control section 40 for controlling the gains of the first amplifying section 10 and the second amplifying section 20, which contributes to cost reduction.

[0039] 2 to 5 are diagrams illustrating operation examples (control examples of the control unit 40) of the amplifying device 1. In any of the operation examples described below, the amplifying device 1 performs continuous AGC operation and gain G １ The change operation is performed.

[0040] In the first operation example shown in FIG. 2, the control unit 40 controls the gain G １ is set to a certain set value, the amplitude V detected by the amplitude detection unit 30 ２ The gain G of the second amplifier 20 is set to be constant. ２ (Continuous AGC operation (S1)). Furthermore, the control unit 40 controls the gain G of the second amplifier unit 20 during the continuous AGC operation. ２ falls outside the set range of the continuous gain variable range that is equal to or greater than the first threshold and equal to or less than the second threshold (i.e., the second gain control signal (SＣＯＮＴ２ ) falls outside the set range (T12), the gain G １ (gain G １ Change operation) (S2). The arrows (T12, T21) indicate the transition of the operation. Gain G １ The gain G of the first amplifier 10 during the change operation １ The change of the gain is made by changing the gain from the previous gain to a predetermined set value (hereinafter referred to as the set value (ΔG Ｎ ) or a set value (ΔG Ｎ The control unit 40 is not limited to changing the gain to a smaller value by the gain G １ After the change operation (T21), the gain G １ is set to the new set value, continuous AGC operation is performed (S1).

[0041] Setting value (ΔG Ｎ ) is the step-change gain (G １ ) and may be the same value or may be different in each stage. Ｎ ) N is the gain G of the first amplifier unit 10 currently in operation. １ The order of the setting value (ΔG Ｎ ) is a predetermined value, so the gain (G １ ) can be a preset or predefined value. Regardless of the value of N, ΔG Ｎ = Z (Ω), the second gain control signal (S ＣＯＮＴ２ When the value of ) changes across the threshold, G １ changes by Z(Ω). Depending on the value of N, ΔG Ｎ The values ​​of ΔG are different. Ｎ =Z Ｎ (Ω), the second gain control signal (S ＣＯＮＴ２ When the value of ) changes across the threshold, G １ is Z Ｎ (Ω). For example, Z １ = 600Ω, Z ２ It can be a different value, such as =200Ω.

[0042] During continuous AGC operation, the gain G２ Whether or not the gain G falls outside the set range of the continuous gain variable range, which is equal to or greater than the first threshold and equal to or less than the second threshold, is determined by the gain G ２ A second gain control signal (S ＣＯＮＴ２ ) and monitors the value of this second gain control signal (S ＣＯＮＴ２ The second gain control signal (S ＣＯＮＴ２ ) and the gain G ２ The relationship between the second gain control signal (S ＣＯＮＴ２ ) one of the first and second voltage thresholds is a gain G ２ is set as the first threshold, and the other is the gain G ２ is set as the second threshold value.

[0043] In the second operation example shown in FIG. 3, the control unit 40 controls the gain G １ After a certain period of time has elapsed since the gain G of the second amplifier 20 was changed during continuous AGC operation, ２ When the gain G １ The change operation is performed (S2). The arrows (T12', T21) indicate the transition of the operation. Here, the certain period is the period during which the gain G １ After being changed to the new set value, the amplitude V of the output voltage signal ２ In this second example of operation, continuous AGC operation and gain G １ Interference with the change operation is suppressed, and more stable operation is possible. The other operations in the second operation example are the same as those in the first operation example shown in FIG.

[0044] In the third operation example shown in FIG. 4, the control unit 40 controls the gain G １ In the change operation, the gain G of the second amplifier 20 during the continuous AGC operation (S1) ２ is less than the first threshold (T121), the gain G １ The set value (ΔG Ｎ ) (S21). １After the change operation (T211), the continuous AGC operation is performed in that state (S1). ２ exceeds the second threshold (T122), the gain G １ The set value (ΔG Ｎ ) (S22). １ After the change operation (T221), continuous AGC operation is performed in that state (S1). Note that arrows (T122, T221, T211, T121) indicate the transition of operation. Alternatively, the control unit 40 may change the gain G ２ When exceeds the first threshold, the gain G １ The set value (ΔG Ｎ ) to reduce the gain of the second amplifier unit 20 by G ２ When the gain G of the first amplifier 10 falls below the second threshold value, １ The set value (ΔG Ｎ ) may be changed to a larger gain.

[0045] In the fourth operation example shown in FIG. 5, the control unit 40 controls the gain G １ In the change operation, the gain G of the second amplifier 20 during the continuous AGC operation (S1) ２ is less than the first threshold (T121), the gain G １ The set value (ΔG Ｎ ) (S21). １ After the change operation (T211), the continuous AGC operation is performed in that state (S1). ２ exceeds the second threshold (T122), the gain G １ is changed to the maximum gain (S22'). １ After the change operation (T221), continuous AGC operation is performed in that state (S1). Note that arrows (T122, T221, T211, T121) indicate the transition of operation. Alternatively, the control unit 40 may change the gain G ２ When exceeds the first threshold, the gain G １ The set value (ΔG Ｎ ) to reduce the gain of the second amplifier unit 20 by G ２When the gain G of the first amplifier 10 falls below the second threshold value, １ may be changed to the maximum gain.

[0046] Between the third operation example (FIG. 4) and the fourth operation example (FIG. 5), the gain G ２ When exceeds the second threshold, the gain G １ The content of the change operation is different. １ During the change operation, the gain G １ The set value (ΔG Ｎ ) and the gain G １ The set value (ΔG Ｎ ) of the first amplifier 10. １ On the other hand, in the fourth operation example, an up-down counter can be used as the counter for holding the set value of the gain G １ During the change operation, the gain G １ The set value (ΔG Ｎ ) of the first amplifier 10, １ When the gain is changed to a larger value, the gain is changed to the maximum value. １ Therefore, in the fourth operation example, compared to the third operation example, the gain G １ The size of the logic circuit for setting the value can be reduced.

[0047] Also, as in the fourth operation example, the gain G １ It is preferable to change to the maximum gain when changing to a larger gain. １ When changing the gain to a small value, it is not preferable to change the gain to the minimum value. The reason is as follows. In PCIe, when signal communication is stopped in a low power state, the state becomes an Electrical Idle state and no signal is input. At this time, the gain is maximum in the initial state of continuous AGC operation, so the gain G １When a current signal is input, the gain G of the first amplifier 10 is １ When the current signal is not input, the gain G of the first amplifier 10 is １ Since there is no need to gradually increase the gain G １ The gain G of the first amplifier 10 can be set to the maximum gain. １ When the gain G of the first amplifier 10 is small, the noise characteristics are poor, and if a current signal with a small amplitude is input in this state, the first amplifier 10 may output a waveform that is unclear as to whether it is a signal or noise. １ When changing to a smaller gain, it is not preferable to change to the minimum gain all at once.

[0048] Next, the control unit 40 calculates the gain G １ and the gain G of the second amplifier 20 ２ Here, the control unit 40 sets the amplitude V of the output voltage signal. ２ The gain G of the first amplifier 10 is set to be constant at 1 V. １ and the gain G of the second amplifier 20 ２ shall be controlled.

[0049] The three gains to be discretely set in the first amplifier section 10 are G １，１ ~G １，３ The gain of the first amplifier 10 is G １，１ The gain of the second amplifier 20 when ２，１ and the gain of the first amplifier 10 is G １，２ The gain of the second amplifier 20 when ２，２ and the gain of the first amplifier 10 is G １，３ The gain of the second amplifier 20 when ２，３ The gain G of the second amplifier 20 is ２，１ ~G ２，３ Each of them has the amplitude A of the input current signal. ０ It changes continuously according to the change of

[0050] FIG. 6 shows the gain G (=G １ G２ [Ω]) and the amplitude A of the input current signal ０ 1 is a diagram showing the relationship between the gain G (=G １ G ２ [Ω]) is the amplitude A of the input current signal ０ It is inversely proportional to

[0051] FIG. 7 shows the G １，１ = 1000Ω, G １，２ = 500Ω, G １，３ = 250Ω, the gain G of the first amplifier unit 10 １ and the gain G of the second amplifier 20 ２ 7A is a diagram showing an example of setting the gain G １ and the amplitude A of the input current signal ０ 7B is a diagram showing the relationship between the gain G ２ and the amplitude A of the input current signal ０ In this example, G １，１ / G １，２ = G １，２ / G １，３ = 2, so the amplitude A of the input current signal is ０ At each value of G ２，２ / G ２，１ = G ２，３ / G ２，２ = 2. That is, G １，１ is G １，２ X １ times (=2 times), G １，２ is G １，３ X ２ times (=2 times), G ２，２ is G ２，１ X ３ times (=2 times), G ２，３ is G ２，２ X ４ It is twice as long (=2 times). １ , X ２ , X ３ , X ４ The magnification of each of the above is not limited to 2 times and may be changed.

[0052] FIG. 8 shows the G １，１ = 1000Ω, G １，２ = 400Ω, G １，３= 200Ω, the gain G of the first amplifier unit 10 １ and the gain G of the second amplifier 20 ２ 8A is a diagram showing an example of setting the gain G １ and the amplitude A of the input current signal ０ 8B is a diagram showing the relationship between the gain G ２ and the amplitude A of the input current signal ０ In this example, G １，１ / G １，２ = 2.5, G １，２ / G １，３ = 2, so the amplitude A of the input current signal is ０ At each value of G ２，２ / G ２，１ = 2.5, G ２，３ / G ２，２ = 2. Also, the amplitude A of the input current signal ０ is 200 μA to 2000 μA, and 200 μA≦A ０ G in the range of ≦500 μA １ = G １，１ = 1000Ω, and 500 μA ≦ A ０ G in the range of ≦1000 μA １ = G １，２ = 400Ω, and 1000 μA ≦ A ０ G in the range of ≦2000 μA １ = G １，３ When the gain G of the second amplifier 20 is set to 200Ω, ２ It is sufficient if it is variable in the range of 2 to 5 times. １，１ is G １，２ X ５ times (=2.5 times), G １，２ is G １，３ X ６ The specific amplitude A ０ (μA), G ２，２ is G ２，１ X ７ times (=2.5 times), G ２，３ is G ２，２ X ８ It is twice as long (=2 times). ５ , X ６ , X ７ , X８ The magnifications are not limited to 2.5 times or 2 times, and may be changed.

[0053] As shown in the setting examples of FIGS. 7 and 8, the settable gain G １ Even if the number of ０ The amplitude of the output voltage signal V ２ can be controlled to a constant value.

[0054] Next, the configuration of the first amplifier 10 will be described. FIG. 9 is a diagram showing a schematic configuration of the first amplifier 10. The first amplifier 10 receives a first gain control signal (S ＣＯＮＴ１ ) and this first gain control signal (S ＣＯＮＴ１ ) is set to one of a plurality of discrete gains based on the first gain control signal (S ＣＯＮＴ１ The frequency characteristics of the first amplifier unit 10 are adjusted by changing the impedance value or current value of an element (resistor, capacitor, or inductor) included in the first amplifier unit 10 in accordance with the gain of the first amplifier unit 10.

[0055] 10 is a diagram showing an example of the circuit configuration of the first amplifier unit 10. The first amplifier unit 10 shown in this diagram can be set to one of three gains, and includes an NPN transistor 101, an NPN transistor 102, resistors 111 to 113, switches 121 to 123, capacitance elements 131 to 133, resistors 141 to 143, switches 151 to 153, current sources 161 to 163, and switches 171 to 173.

[0056] The collector of the NPN transistor 101 is connected to a node N1.

[0057] The emitter of the NPN transistor 101 is connected to the VEE supply terminal at low potential.

[0058] The base of the NPN transistor 101 is connected to an input terminal for inputting a current signal.

[0059] The collector of the NPN transistor 102 is connected to the high potential VCC supply terminal.

[0060] The emitter of the NPN transistor 102 is connected to the node N2.

[0061] The base of the NPN transistor 102 is connected to the node N1 and also to an output terminal that outputs a voltage signal to the second amplifier unit 20. The output signal detector 10B includes an NPN transistor 102. The base current of the NPN transistor 102 varies depending on the output voltage of the first amplifier unit 10.

[0062] Resistor 111 and switch 121 are connected in series with each other and are provided between the VCC supply terminal and node N1.

[0063] Resistor 112 and switch 122 are connected in series with each other and are provided between the VCC supply terminal and node N1.

[0064] Resistor 113 and switch 123 are connected in series with each other and are provided between the VCC supply terminal and node N1.

[0065] Resistors 111 to 113 are provided in parallel between the VCC supply end and node N1, and form a resistor with variable resistance. The resistance between the VCC supply end and node N1 is set by turning on / off each of switches 121 to 123. The first variable gain amplifier 10A includes a first transistor 101 and resistors 111 to 113, and can control the gain by controlling the resistance of these resistors.

[0066] The capacitance element 131 and the resistor 141 are connected in parallel with each other, and are connected in series with the switch 151. The capacitance element 131, the resistor 141, and the switch 151 are provided between the base of the NPN transistor 101 and the node N2.

[0067] The capacitance element 132 and the resistor 142 are connected in parallel with each other, and are connected in series with the switch 152. The capacitance element 132, the resistor 142, and the switch 152 are provided between the base of the NPN transistor 101 and the node N2.

[0068] The capacitance element 133 and the resistor 143 are connected in parallel with each other, and are connected in series with the switch 153. The capacitance element 133, the resistor 143, and the switch 153 are provided between the base of the NPN transistor 101 and the node N2.

[0069] Capacitance elements 131 to 133 and resistors 141 to 143 are arranged in parallel with one another between the base of NPN transistor 101 and node N2. Capacitance elements 131 to 133 form capacitance elements with variable capacitance values. Resistors 141 to 143 form resistors with variable resistance values. The impedance (capacitance value, resistance value) between the base of NPN transistor 101 and node N2 is set by turning on / off switches 151 to 153, respectively.

[0070] The current source 161 and the switch 171 are connected in series with each other and are provided between the node N2 and the VEE supply terminal.

[0071] The current source 162 and the switch 172 are connected in series with each other and are provided between the node N2 and the VEE supply terminal.

[0072] The current source 163 and the switch 173 are connected in series with each other and are provided between the node N2 and the VEE supply terminal.

[0073] The current sources 161 to 163 are provided in parallel between the node N2 and the VEE supply terminal, and constitute a current source with a variable current value that flows from the node N2 to the VEE supply terminal. The current value is set by turning on / off the switches 171 to 173, respectively.

[0074] The first gain control signal (S ＣＯＮＴ１ ) is a 3-bit digital signal [C3, C2, C1]. １ In response to this, one of C3, C2, and C1 goes to high level, and the other two go to low level.

[0075] The on / off states of the switches 121, 151, and 171 are set according to the level of C1.

[0076] The on / off states of the switches 122, 152, and 172 are set according to the level of C2.

[0077] The on / off states of the switches 123, 153, and 173 are set according to the level of C3.

[0078] When C1 is at a high level, switches 121, 151, and 171 are turned on, and the other switches are turned off. At this time, the gain of the first amplifier unit 10 corresponds to the resistance value of resistor 141. The frequency characteristics of the first amplifier unit 10 also correspond to the resistance value of resistor 111, the capacitance value of capacitive element 131, and the current value of current source 161.

[0079] When C2 is at a high level, switches 122, 152, and 172 are turned on, and the other switches are turned off. At this time, the gain of the first amplifier unit 10 corresponds to the resistance value of resistor 142. The frequency characteristics of the first amplifier unit 10 also correspond to the resistance value of resistor 112, the capacitance value of capacitive element 132, and the current value of current source 162.

[0080] When C3 is at a high level, switches 123, 153, and 173 are turned on, and the other switches are turned off. At this time, the gain of the first amplifier unit 10 corresponds to the resistance value of resistor 143. The frequency characteristics of the first amplifier unit 10 also correspond to the resistance value of resistor 113, the capacitance value of capacitive element 133, and the current value of current source 163.

[0081] In this configuration, the three gains to be selectively set in the first amplifier section 10 are G １，１ ~G １，３ Let's say.

[0082] The gain of the first amplifier 10 is set to G by the resistance value of the resistor 111, the capacitance value of the capacitor 131, the resistance value of the resistor 141, and the current value of the current source 161. １，１ , and the frequency characteristics of the first amplifier section 10 at that time can be made appropriate.

[0083] The gain of the first amplifier unit 10 is set to G by the resistance value of the resistor 112, the capacitance value of the capacitor 132, the resistance value of the resistor 142, and the current value of the current source 162. １，２ , and the frequency characteristics of the first amplifier section 10 at that time can be made appropriate.

[0084] The gain of the first amplifier 10 is set to G by the resistance value of the resistor 113, the capacitance value of the capacitor 133, the resistance value of the resistor 143, and the current value of the current source 163. １，３ , and the frequency characteristics of the first amplifier section 10 at that time can be made appropriate.

[0085] In this way, the frequency characteristics of the first amplifier unit 10 can be flattened over a wide frequency band by changing the impedance values ​​or current values ​​of the elements included in the first amplifier unit 10 in accordance with the gain of the first amplifier unit 10. Note that the circuit configuration of the first amplifier unit 10 is not limited to the example configuration shown in FIG.

[0086] The second amplifier 20 preferably has a circuit configuration in which the change in circuit current when the gain is changed is small, such as a Gilbert cell mixer, etc. By using such a circuit configuration, the second amplifier 20 can reduce the influence on the dominant pole of the frequency characteristics.

[0087] FIG. 11 is a diagram showing the configuration of the amplifier device 1.

[0088] The amplifier 1 receives an input signal S ＩＮ a second amplifying section 20 that receives the output signal of the first amplifying section 10; an amplitude detecting section 30; and a control section 40.

[0089] The first amplifier unit 10 includes a first variable gain amplifier 10A, an output signal detector 10B, a variable impedance resistor-capacitor (RC circuit) 10C, and a variable current source 10D. An example of the configuration of each circuit is shown in FIG. 10. The resistor-capacitor circuit is a circuit that combines a resistor and a capacitor.

[0090] The first variable gain amplifier 10A receives an input signal SＩＮ an input terminal for receiving an output signal S １０ It has an output terminal that outputs

[0091] The output signal detector 10B is connected to the output terminal (first node N1) of the first variable gain amplifier 10A and can directly or indirectly detect the potential of the output terminal of the first variable gain amplifier 10A. If the output signal detector 10B is configured as a bipolar transistor, the voltage between its emitter and base changes according to the potential of the output terminal of the first variable gain amplifier 10A. If the output signal detector 10B is configured as a field effect transistor (FET), the potential applied to its gate changes according to the potential of the output terminal of the first variable gain amplifier 10A. Although either a bipolar transistor or an FET can be used as the output signal detector 10B, a bipolar transistor is used in this example.

[0092] The output signal detector 10B of this example includes an NPN transistor 102. The emitter of the NPN transistor 102 is connected to a second node N2, and the collector is connected to the power supply potential VCC. The second node N2 is connected to a variable current source 10D.

[0093] The base of the NPN transistor 102 of the output signal detector 10B receives the output signal S of the first variable gain amplifier 10A. １０ The output signal S of the first variable gain amplifier 10A is １０ increases, and the base-emitter voltage (V ＢＥ ) increases, the drain current Id flowing through the NPN transistor 102 increases.

[0094] The input terminal of the RC circuit 10C is connected to the second node N2. The output terminal of the RC circuit 10C is connected to the input terminal of the first variable gain amplifier 10A. The output signal S of the first variable gain amplifier 10A １０ is fed back to the input terminal of the first variable gain amplifier 10A via an output signal detector 10B and an RC circuit 10C.

[0095] The second amplifier 20 receives the output signal S of the first amplifier 10 via the first node N1.１０ The second amplifier section 20 may include, for example, a Gilbert cell, although other amplifiers may also be used.

[0096] For example, when the amplitude detection unit 30 is configured from an analog circuit, it can be configured from a low-pass filter, a smoothing circuit, or the like, and detects the amplitude of the output signal of the second amplification unit 20 and inputs it to the control unit 40. For example, when the amplitude detection unit 30 is configured from a digital circuit, it can be configured to detect the maximum value of the output of a sampler that samples the output signal of the second amplification unit 20 as the amplitude, and detects the amplitude of the output signal of the second amplification unit 20 and inputs it to the control unit 40.

[0097] The control unit 40 generates a digital gain control signal (first gain control signal (S ＣＯＮＴ１ )) and a first control unit 41 that outputs an analog gain control signal (second gain control signal (S ＣＯＮＴ２ ) and a second control unit 42 that outputs the signal.

[0098] The control unit 40 includes an automatic gain controller that performs automatic gain control (AGC).

[0099] The second control section 42 controls the second gain control signal (S ＣＯＮＴ２ ), the gain (G ２ For example, when the amplitude detected by the amplitude detection section 30 increases above a reference value, the second control section 42 controls the analog second gain control signal (S ＣＯＮＴ２ ) is input to the second amplifier 20 to generate an output signal (S ＯＵＴ Conversely, if the amplitude detected by the amplitude detection section 30 is reduced below the reference value, the second control section 42 reduces the amplitude of the analog second gain control signal (S ＣＯＮＴ２ ) is input to the second amplifier 20 to generate an output signal (S ＯＵＴ ) to increase its amplitude.

[0100] The second control unit 42 may include, for example, a differential amplifier to which a voltage level indicating the detected amplitude and a reference voltage are input, and a resistor connected between a transistor constituting the differential amplifier and a power supply potential. The larger the difference in the input voltages to the differential amplifier, the greater the current flowing through the resistor, causing a larger voltage drop across the resistor, thereby lowering the potential at the node downstream of the resistor. This potential is controlled by a second gain control signal (S ＣＯＮＴ２ ), the second gain control signal (S ＣＯＮＴ２ ) can be controlled to be small.

[0101] The gain (G ２ ) exceeds the upper limit of the gain adjustment range, the first control unit 41 controls the first digital gain control signal (S ＣＯＮＴ１ ) is input to the first amplifier 10, and the gain (G １ ) indicated by the second control unit 42 is increased. ２ ) falls below the lower limit of the gain adjustment range, the first control unit 41 controls the digital first gain control signal (S ＣＯＮＴ１ ) is input to the first amplifier 10, and the gain (G １ ) to reduce

[0102] The first amplifier 10 receives a digital first gain control signal (S ＣＯＮＴ１ ) input, the output signal (S １０ The first variable gain amplifier 10A, the RC circuit 10C, and the variable current source 10D each adjust the frequency characteristics of the output signal S １０ The optimum values ​​of the parameters (resistance, capacitance, current) of each circuit that can obtain the desired gain and frequency characteristics can be calculated using a circuit simulator. For example, when the output signal S １０When increasing the overall gain of the amplifier, the resistance value in the first variable gain amplifier 10A is increased and the current flowing through the variable current source 10D is reduced. To increase the gain, only the switch C1 is turned ON, and C2 and C3 are turned OFF. The RC circuit 10C is located in the feedback loop inside the first amplifier 10 and can greatly contribute to changing the frequency characteristics. The gain (G １ If frequency degradation is expected when switching between the two, the impedance that suppresses frequency degradation can be calculated in advance, and the impedance (capacitor capacitance and resistance value) can be set in the RC circuit 10C.

[0103] Such a function of adjusting the frequency characteristics can also be obtained by replacing the variable current source 10D with a fixed current source.

[0104] The first control unit 41 receives, for example, the output signal S ＯＵＴ a sampler that receives a voltage at a level that directly or indirectly indicates the amplitude of the signal and samples the voltage so that it can be digitally processed; a digital signal processor that converts the value acquired by the sampler into a digital value, calculates the difference between the digital value and a target value, and adjusts the gain (G １ ) is determined, and a digital signal (first gain control signal (S ＣＯＮＴ１ The first control unit 41 may be configured from a general-purpose integrated circuit, or may be configured to perform signal processing using software that performs the above calculations.

[0105] The second gain control signal (S ＣＯＮＴ２ ) indicates the gain (G ２ ) exceeds a preset upper threshold (second threshold), the first control unit 41 outputs a first gain control signal (S ＣＯＮＴ１ ) indicates the gain (G １ ) is switched and increased, and the gain (G １ ) is increased. The second gain control signal (S ＣＯＮＴ２ ) gain (G ２) falls below a preset lower limit threshold (first threshold), the first control unit 41 outputs a first gain control signal (S ＣＯＮＴ１ ) indicates the gain (G １ ) is switched and decreased, and the gain (G １ ) decreases.

[0106] The first control unit 41 generates a second gain control signal (S ＣＯＮＴ２ ) indicates the gain (G ２ ) (level, etc.) can be monitored. ２ ) depending on the value of the first gain control signal (S ＣＯＮＴ１ ) indicates the gain (G １ ) can be switched.

[0107] In the above circuit, the potential of the first node N1 is set to the first amplifier unit 10 output signal (S １０ ) to the second amplifier 20, but the potential of the second node N2 may be input to the second amplifier 20 as the output signal of the first amplifier 10.

[0108] As described above, the first variable gain amplifier 10A controls the first gain control signal (S ＣＯＮＴ１ ), the gain (G １ ) is controlled. ＣＯＮＴ１ ) is a digital gain control signal because it is a discrete digital value (C1, C2, C2). ＣＯＮＴ１ ) and has digital gain control signal receiving terminals (input terminals of C1, C2, and C3) for receiving the digital gain control signal.

[0109] The output signal detector 10B has an input terminal connected to the output terminal of the first variable gain amplifier 10A.

[0110] The variable impedance RC circuit 10C is connected between the output signal detector 10B and the input terminal of the first variable gain amplifier 10A. The variable current source 10D can be a fixed current source or can be omitted in some cases.

[0111] The second amplifier 20 includes a second variable gain amplifier (20). The second variable gain amplifier (20) receives a second gain control signal (SＣＯＮＴ２ ), the gain (G ２ ) is controlled. ＣＯＮＴ２ ) is a continuous analog value (such as a voltage level) and is therefore an analog gain control signal. The second variable gain amplifier (20) generates an analog gain control signal (S ＣＯＮＴ２ ) and has analog gain control signal receiving terminals (B1, B2) for receiving the analog gain control signal.

[0112] The control unit 40 automatically controls the gains (G1, G2) of the first amplifying unit 10 and the second amplifying unit 20 so as to maintain a constant amplitude of the output signal of the second amplifying unit 20. That is, the control unit 40 is an automatic gain control unit that performs automatic gain control (AGC), and outputs a digital gain control signal and an analog gain control signal according to the output of the amplitude detecting unit 30. The control unit 40 has an input terminal connected to the output terminal of the amplitude detecting unit 30, a first output terminal (output terminal of the first control unit 41) connected to a digital gain control signal receiving terminal (arrows inputting C1, C2, C2), and a second output terminal (output terminal of the second control unit 42) connected to an analog gain control signal receiving terminal.

[0113] FIG. 12 is a diagram showing an example of the circuit configuration of the second amplifier 20. As shown in FIG.

[0114] As shown in the figure, the second amplifier 20 may be configured from a Gilbert cell (mixer). A typical Gilbert cell includes multiple differential amplifiers, and the output signal S １０ a pair of differential input terminals (S1, S2) for amplifying a second gain control signal (S ＣＯＮＴ２ The differential input terminals (S1, S2) are provided with a pair of differential input terminals (B1, B2) to which the output signal S of the first amplifier 10 is input. １０ A differential signal generated from is input.

[0115] In the above, the first amplifier 10 outputs a single-phase output signal S １０ However, a configuration in which a differential signal is output is also possible. For example, when the input signal S ＩＮWhen the input signal S to the first amplifier 10 is a differential signal, the positive phase signal and the negative phase signal can be amplified by a pair of first amplifiers 10 and output as a differential signal. ＩＮ Even if the output signal S is a single-phase signal, the pre-stage circuit 20P can generate a differential signal. １０ is branched, and the branched first signal is input to a buffer amplifier 21, and the branched second signal is input to an inverter circuit 22 for inversion, thereby obtaining a differential signal.

[0116] Furthermore, when the first amplifier 10 outputs a single-phase signal, this single-phase output signal may be branched, and one of the signals may be smoothed using a low-pass filter or the like to generate an average voltage, and these signals may be input to a pair of differential input terminals of the Gilbert cell. Note that, although the figure shows an example in which the pre-stage circuit 20P is arranged outside the second amplifier 20, the pre-stage circuit 20P may also be incorporated inside the second amplifier 20.

[0117] First differential amplifier DIF Ａ The second differential amplifier DIF comprises a pair of bipolar transistors (Q1, Q2) that form a differential pair, the emitters of these transistors are connected, the collector of a bipolar transistor (Q5) is connected to the node of these emitters, and a first control signal, which is an analog signal, is input to the base (control terminal) of the bipolar transistor (Q5). Ｂ The amplifier comprises a pair of bipolar transistors (Q3, Q4) that form a differential pair, the emitters of these transistors are connected, the collector of a bipolar transistor (Q6) is connected to the node of these emitters, and a second control signal, which is an analog signal, is input to the base (control terminal) of the bipolar transistor (Q6). The first control signal and the second control signal can be differential signals, and these differential signals are used as a second gain control signal (S ＣＯＮＴ２ ) The second gain control signal (S ＣＯＮＴ２ ) is an analog signal output from the second control unit 42, but if this signal is single-phase, a differential signal can be generated by the pre-stage circuit 20P. The pre-stage circuit 20P generates the second gain control signal (S ＣＯＮＴ２) is branched, and the branched first signal is input to a buffer amplifier 31, and the branched second signal is input to an inverter circuit 32 for inversion, thereby obtaining a differential signal. These differential signals can be input to differential input terminals (B1, B2), respectively.

[0118] First and second differential amplifiers (DIF Ａ , D.I.F. Ｂ ) are cross-coupled, and the first differential amplifier DIF Ａ The collector of one bipolar transistor (Q1) in the differential pair and the second differential amplifier DIF Ｂ The collector of one bipolar transistor (Q3) in the differential pair can be connected to the power supply potential VCC via a first resistor R1. This collector voltage is used as the first output signal S of the second amplifier section 20. ＯＵＴ１ It can be said that:

[0119] First differential amplifier DIF Ａ The collector of the other bipolar transistor (Q2) in the differential pair and the second differential amplifier DIF Ｂ The collector of the other bipolar transistor (Q4) in the differential pair can be connected to the power supply potential VCC via a second resistor R2. This collector voltage is used as the second output signal S of the second amplifier section 20. ＯＵＴ２ The first and second output signals (S ＯＵＴ１ , S ＯＵＴ２ ) is input to a differential amplifier as needed to generate a single-phase output signal S ＯＵＴ However, the output signal S ＯＵＴ may be a differential signal.

[0120] The bases of one bipolar transistor (Q1, Q3) in each of the first and second differential amplifiers are connected to one differential input terminal (S1), and the bases of the other bipolar transistor (Q2, Q4) in each of the first and second differential amplifiers are connected to the other differential input terminal (S2).

[0121] When the first and second differential amplifiers in the Gilbert cell are configured from bipolar transistors as described above, the gain is determined by a second gain control signal (S ＣＯＮＴ２ ) can be controlled by the third differential amplifier DIF Ｃ is composed of a pair of bipolar transistors (Q5, Q6), and the emitters of these transistors are connected to the ground potential via a current source CS.

[0122] Although the bipolar transistors described above are NPN transistors, PNP transistors can also be used. Furthermore, the bipolar transistors described above can be replaced with field-effect transistors. In this case, the control terminal of the transistor becomes the gate instead of the base.

[0123] As explained above, the above-mentioned amplifying device 1 comprises a first amplifying section 10 including a first variable gain amplifier 10A having a digital gain control signal receiving terminal, an output signal detector 10B connected to the output terminal of the first variable gain amplifier 10A, and a variable impedance resistor-capacitor circuit (RC circuit 10C) connected between the output signal detector 10B and the input terminal of the first variable gain amplifier 10A, a second amplifying section 20 including a second variable gain amplifier (20) having an analog gain control signal receiving terminal, an amplitude detecting section 30 connected to the output terminal of the second amplifying section 20, an input terminal connected to the output terminal of the amplitude detecting section 30, a first output terminal connected to the digital gain control signal receiving terminal, and a second output terminal connected to the analog gain control signal receiving terminal, and a digital gain control signal (S ＣＯＮＴ１ ) and an analog gain control signal (S ＣＯＮＴ２ and an automatic gain control section (control section 40) that outputs a first amplifier section 10. The first amplifier section 10 may include a transimpedance amplifier.

[0124] The automatic gain control unit (control unit 40) generates a digital gain control signal (S ＣＯＮＴ１ ) from a first output terminal, and an analog gain control signal (S ＣＯＮＴ２) from a second output terminal.

[0125] The digital gain control signal (S ＣＯＮＴ１ ) is referred to as the first gain (G １ ), and the analog gain control signal (S ＣＯＮＴ２ ) is referred to as the second gain (G ２ ), and the second gain (G ２ ) falls outside the set range, the first control unit 41 adjusts the second gain (G ２ ) is adjusted so that it falls within a set range. １ ) may be changed.

[0126] The lower limit of the setting range is set as a first threshold value, the upper limit of the setting range is set as a second threshold value, and the second gain (G ２ ) is smaller than the first threshold, the first control unit 41 controls the first gain (G １ ) and the second gain (G ２ ) is greater than the second threshold, the first control unit 41 adjusts the first gain (G １ ) may be increased.

[0127] The lower limit of the weapon setting range is the first threshold, the upper limit of the setting range is the second threshold, and the second gain (G ２ ) is smaller than the first threshold, the first control unit 41 controls the first gain (G １ ) and the second gain (G ２ ) is greater than the second threshold, the first control unit 41 adjusts the first gain (G １ ) may be set to a maximum value.

[0128] The output signal detector 10B includes a transistor (102) having a control terminal (base or gate) connected to the output terminal of the first variable gain amplifier 10A, and a current source (10D) is connected to the current path of the transistor. The RC circuit 10C may be connected between a node (second node N2) between the transistor and the current source (10D) and the input terminal of the first variable gain amplifier 10A.

[0129] The digital gain control signal receiving terminal may be connected to the first variable gain amplifier 10A and the RC circuit 10C.

[0130] The current source (10D) may be a variable current source 10D, and the digital gain control signal receiving terminal may be connected to the first variable gain amplifier 10A, the RC circuit 10C, and the variable current source 10D.

[0131] The present invention is not limited to the above-described embodiments, but is defined by the claims, and is intended to include all modifications within the meaning and scope of the claims.

[0132] 1...amplifying device, 10...first amplifying section, 20...second amplifying section, 30...amplitude detecting section, 40...control section.

Claims

1. A first amplification unit that sets any one of a plurality of discrete gains, converts an input current signal into a voltage signal based on the set gain, and outputs the converted voltage signal; a second amplification unit that sets any one of a continuous gain variable range, amplifies the voltage signal output from the first amplification unit based on the set gain, and outputs the amplified voltage signal; an amplitude detection unit that detects the amplitude of the voltage signal output from the second amplification unit; and a control unit that controls the gains of the first amplification unit and the second amplification unit so that the amplitude detected by the amplitude detection unit becomes constant. An amplification device comprising:

2. The amplification device according to claim 1, wherein the control unit controls the gain of the second amplification unit so that the amplitude detected by the amplitude detection unit becomes constant, and when the gain of the second amplification unit deviates from a range of equal to or greater than a first threshold value and equal to or less than a second threshold value within the continuous gain variable range, changes the gain of the first amplification unit.

3. The amplification device according to claim 2, wherein the control unit changes the gain of the first amplification unit when the gain of the second amplification unit deviates from a range of equal to or greater than the first threshold value and equal to or less than the second threshold value after a certain period has elapsed since the gain of the first amplification unit was changed.

4. The amplification device according to claim 2, wherein the control unit changes the gain of the first amplification unit to a gain smaller by a preset value when the gain of the second amplification unit is less than the first threshold value, and changes the gain of the first amplification unit to a gain larger by a preset value when the gain of the second amplification unit exceeds the second threshold value.

5. The amplification device according to claim 2, wherein the control unit changes the gain of the first amplification unit to a gain smaller by a preset value when the gain of the second amplification unit exceeds the first threshold value, and changes the gain of the first amplification unit to a gain larger by a preset value when the gain of the second amplification unit is less than the second threshold value.

6. The amplification device according to claim 2, wherein the control unit changes the gain of the first amplification unit to a gain smaller by a preset value when the gain of the second amplification unit is less than the first threshold value, and changes the gain of the first amplification unit to the maximum gain when the gain of the second amplification unit exceeds the second threshold value.

7. The amplification device according to claim 2, wherein when the gain of the second amplification unit exceeds the first threshold value, the control unit changes the gain of the first amplification unit to a gain smaller by a predetermined set value, and when the gain of the second amplification unit is below the second threshold value, the control unit changes the gain of the first amplification unit to the maximum gain.

8. The amplification device according to claim 1, wherein the control unit changes the impedance value or current value of an element included in the first amplification unit according to the gain of the first amplification unit.

9. An amplification device comprising: a first variable gain amplifier having a digital gain control signal reception terminal; an output signal detector connected to an output terminal of the first variable gain amplifier; a resistor-capacitor circuit with variable impedance connected between the output signal detector and an input terminal of the first variable gain amplifier, which constitutes a first amplification unit; a second amplification unit including a second variable gain amplifier having an analog gain control signal reception terminal; an amplitude detector connected to an output terminal of the second amplification unit; an input terminal connected to an output terminal of the amplitude detector; a first output terminal connected to the digital gain control signal reception terminal; and a second output terminal connected to the analog gain control signal reception terminal, and an automatic gain control unit that outputs the digital gain control signal and the analog gain control signal according to the output of the amplitude detector.

10. The amplification device according to claim 9, wherein the first amplification unit includes a transimpedance amplifier.

11. The amplification device according to claim 9, wherein the automatic gain control unit includes a first control unit that outputs the digital gain control signal from the first output terminal and a second control unit that outputs the analog gain control signal from the second output terminal.

12. Let the gain indicated by the digital gain control signal output from the first control unit be the first gain (G １ ), and let the gain indicated by the analog gain control signal output from the second control unit be the second gain (G ２ ). When the second gain (G ２ ) is out of the set range, the first control unit changes the first gain (G ２ ) so that the second gain (G １ ) is within the set range. The amplifier device according to claim 11.

13. Set the lower limit value of the setting range as the first threshold value, set the upper limit value of the setting range as the second threshold value, and when the second gain (G ２ ) is smaller than the first threshold value, the first control unit decreases the first gain (G １ ), and when the second gain (G ２ ) is larger than the second threshold value, the first control unit increases the first gain (G １ ). The amplifying device according to claim 12.

14. Set the lower limit value of the setting range as the first threshold value, set the upper limit value of the setting range as the second threshold value, and when the second gain (G ２ ) is smaller than the first threshold value, the first control unit decreases the first gain (G １ ), and when the second gain (G ２ ) is larger than the second threshold value, the first control unit sets the first gain (G １ ) to the maximum value. The amplifier device according to claim 12.

15. The amplification device according to claim 9, wherein the output signal detector includes a transistor having a control terminal connected to an output terminal of the first variable gain amplifier, a current source is connected to a current path of the transistor, and the resistor-capacitor circuit is connected between a node between the transistor and the current source and an input terminal of the first variable gain amplifier.

16. The amplification device according to claim 15, wherein the digital gain control signal reception terminal is connected to the first variable gain amplifier and the resistor-capacitor circuit.

17. The current source is a variable current source, and the digital gain control signal receiving terminal is connected to the first variable gain amplifier, the resistor-capacitor circuit, and the variable current source. The amplification device according to claim 15.

Images