Shift register, gate driving circuit, display panel and display device

Abstract

The present invention provides a shift register, a gate driving circuit, a display panel and a display device. The shift register comprises a substrate and a plurality of transistors, wherein the plurality of transistors comprise a first transistor group and a second transistor group. At least one transistor in the first transistor group comprises a first electrode, the first electrode comprising a first source main portion, a plurality of first source branch portions, a first drain main portion and a plurality of first drain branch portions, wherein the first source branch portions and the first drain branch portions extend in a first direction and are alternately distributed in a second direction. At least one transistor in the second transistor group comprises a second electrode, the second electrode comprising a second source main portion, a plurality of second source branch portions, a second drain main portion and a plurality of second drain branch portions, wherein the second source branch portions and the second drain branch portions extend in the second direction and are alternately distributed in the first direction.

Description

Shift register, gate drive circuit, display panel and display device Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a shift register, a gate driving circuit, a display panel, and a display device. Background Art

[0002] With the development of information technology, electronic devices have become widely used in our daily lives. Liquid crystal displays (LCDs), as the most widely used flat-panel display, occupy a key position in display panels. Gate drive circuit technology utilizes a thin-film transistor array process to fabricate gate scan drive circuits on a thin-film transistor array substrate to achieve a progressive scan drive mode. Gate driver on array (GOA) technology integrates the row scan drive circuits on the display panel's array substrate, significantly reducing the display panel's bezel and improving product competitiveness. As shown in Figure 1 below, the display panel has a display area AA and a non-display area BB located on one side of the display area AA, wherein the non-display area BB may include: a gate drive transistor 01 (which may include multiple transistors), a first common routing 02, a floating routing 03, a gate drive routing 04, a second common routing 05, and a third common routing 06; wherein, the length D of the area occupied by the gate drive transistor 01 is greater than the length E of the area occupied by the first common routing 02 and the floating routing 03, and is also greater than the length C of the area occupied by the gate drive routing 04, and is also greater than the length B of the area occupied by the second common routing 05 and the third common routing 06. That is, the layout area of ​​the gate drive transistor 01 is an important factor affecting the design of the left and right borders of the display panel. Reducing the area share of the gate drive transistor while ensuring the product's scanning signal output capability is an effective way to achieve a narrow border for the product.

[0003] Summary of the Invention

[0004] The present invention provides a shift register, a gate drive circuit, a display panel, and a display device. The shift register includes:

[0005] substrate;

[0006] A plurality of transistors are located on one side of the substrate; the plurality of transistors include: a first transistor group and a second transistor group;

[0007] At least one transistor in the first transistor group includes: a first electrode; the first electrode includes: a first source main portion, a plurality of first source branches connected to the first source main portion, a first drain main portion, and a plurality of first drain branches connected to the first drain main portion; the first source branches and the first drain branches extend along a first direction and are alternately distributed along a second direction;

[0008] At least one of the transistors in the second transistor group includes: a second electrode; the second electrode includes: a second source main portion, a plurality of second source branches connected to the second source main portion, a second drain main portion, and a plurality of second drain branches connected to the second drain main portion; the second source branches and the second drain branches extend along the second direction and are alternately distributed along the first direction.

[0009] In a possible implementation manner, in the first transistor group, the maximum length of the first electrodes of at least some of the transistors in the first direction is greater than the maximum length in the second direction;

[0010] In the second transistor group, a maximum length of the second electrodes of at least some of the transistors in the second direction is greater than a maximum length in the first direction.

[0011] In a possible implementation, the first transistor group includes: a first transistor; the first transistor has a positive projection area on the substrate that is larger than the positive projection area of ​​any other transistor on the substrate;

[0012] The first transistor group further includes: a second transistor; the orthographic projection area of ​​the second transistor on the substrate is larger than the orthographic projection area of ​​any other transistor except the first transistor on the substrate.

[0013] In a possible implementation, the first transistor group includes: a first transistor; the first transistor is configured to output a signal to an output terminal according to a signal at a clock signal terminal;

[0014] The first transistor group further includes a second transistor; the second transistor is configured to precharge the first node according to a signal inputted from the input terminal.

[0015] In a possible implementation, the first transistor group further includes: a third transistor, a fourth transistor, and a fifth transistor; the shift register is used to provide a signal to a display panel, and the display panel has a display area;

[0016] The first transistor is located on a side of the shift register close to the display area; the second transistor is located on a side of the first transistor away from the display area; the third transistor and the fourth transistor are located in an area between the first transistor and the second transistor, and the fifth transistor is located on a side of the second transistor away from the first transistor.

[0017] In a possible implementation manner, the second transistor group further includes: a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, and an eleventh transistor;

[0018] The sixth transistor is located between the second transistor and the third transistor; the seventh transistor is located between the second transistor and the fifth transistor; the eighth transistor is located between the seventh transistor and the fifth transistor; the ninth transistor is located between the fifth transistor and the eighth transistor; the tenth transistor is located on the side of the fifth transistor away from the ninth transistor; and the eleventh transistor is located between the ninth transistor and the tenth transistor.

[0019] In a possible implementation, the control electrode of the first transistor is electrically connected to the first node, the first electrode of the first transistor is electrically connected to the clock signal terminal, and the second electrode of the first transistor is electrically connected to the output terminal;

[0020] The control electrode and the first electrode of the second transistor are electrically connected to the input terminal, and the second electrode of the second transistor is electrically connected to the first node;

[0021] The control electrode of the third transistor is electrically connected to the discharge control terminal, the first electrode of the third transistor is electrically connected to the first node, and the second electrode of the third transistor is electrically connected to the second power supply terminal;

[0022] The control electrode of the fourth transistor is electrically connected to the discharge control terminal, the first electrode of the fourth transistor is electrically connected to the second power supply terminal, and the second electrode of the fourth transistor is electrically connected to the output terminal;

[0023] The control electrode of the fifth transistor is electrically connected to the second node, the first electrode of the fifth transistor is electrically connected to the first power supply terminal, and the second electrode of the fifth transistor is electrically connected to the third node;

[0024] The control electrode of the sixth transistor is electrically connected to the reset signal terminal, the first electrode of the sixth transistor is electrically connected to the first node, and the second electrode of the sixth transistor is electrically connected to the second power supply terminal;

[0025] The control electrode of the seventh transistor is electrically connected to the third node, the first electrode of the seventh transistor is electrically connected to the second power supply terminal, and the second electrode of the seventh transistor is electrically connected to the output terminal;

[0026] The control electrode of the eighth transistor is electrically connected to the third node, the first electrode of the eighth transistor is electrically connected to the first node, and the second electrode of the eighth transistor is electrically connected to the second power supply terminal;

[0027] The control electrode of the ninth transistor is electrically connected to the first node, the first electrode of the ninth transistor is electrically connected to the third node, and the second electrode of the ninth transistor is electrically connected to the second power supply terminal;

[0028] The control electrode and the first electrode of the tenth transistor are electrically connected to the first power supply terminal, and the second electrode of the tenth transistor is electrically connected to the second node;

[0029] The control electrode of the eleventh transistor is electrically connected to the first node, the first electrode of the eleventh transistor is electrically connected to the second node, and the second electrode of the eleventh transistor is electrically connected to the second power supply terminal.

[0030] In a possible implementation, the shift register further includes: a plurality of cascade lines extending along the second direction; the orthographic projections of the plurality of cascade lines on the substrate are located between the orthographic projections of the second transistor and the sixth transistor on the substrate.

[0031] In a possible implementation manner, the shift register further includes: a first via electrically connected to at least one cascade wiring among the plurality of cascade wirings;

[0032] The orthographic projection of the first via on the substrate is located between the orthographic projections of the second transistor and the sixth transistor on the substrate.

[0033] In a possible implementation, the shift register further includes: a plurality of connection lines extending along the first direction, and a first active pattern block;

[0034] The orthographic projection of the connection line on the substrate has a first overlapping area with the orthographic projection of the cascade line on the substrate; the orthographic projection of the first active pattern block on the substrate covers the first overlapping area.

[0035] In a possible implementation manner, at least one transistor among the plurality of transistors includes: an active layer; and the first active pattern block is located in the active layer.

[0036] An embodiment of the present disclosure provides a gate driving circuit, which includes a plurality of shift registers provided by the embodiment of the present disclosure, and the plurality of shift registers are cascaded.

[0037] An embodiment of the present disclosure provides a display panel, which includes a display area and a non-display area located on one side of the display area; wherein the non-display area has the gate driving circuit provided by the embodiment of the present disclosure.

[0038] In a possible implementation manner, the display panel further includes: a frame sealant located on a side of the transistor facing away from the substrate;

[0039] The orthographic projection of the frame sealing adhesive on the substrate covers the orthographic projection of the cascade trace on the substrate.

[0040] An embodiment of the present disclosure provides a display device, which includes the display panel provided by the embodiment of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] FIG1 is a schematic top view of a display panel;

[0042] FIG2 is a schematic diagram showing a comparison of channels extending in different directions;

[0043] FIG3A is a schematic top view of a shift register according to an embodiment of the present disclosure; ...

[0044] FIG3B is a schematic diagram of a single film layer of the gate layer in FIG3A ;

[0045] FIG3C is a schematic diagram of a single film layer of the active layer in FIG3A ;

[0046] FIG3D is a schematic diagram of a single film layer of the source and drain layers in FIG3A ;

[0047] FIG3E is a schematic diagram of a single film layer of the passivation layer in FIG3A ;

[0048] FIG3F is a schematic diagram of a single film layer of the conductive layer in FIG3A ;

[0049] FIG4 is an equivalent circuit diagram corresponding to FIG3A ;

[0050] FIG5 is a partial schematic diagram of a gate driving circuit provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0051] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0052] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by persons of ordinary skill in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0053] As used herein, "about" or "approximately the same" is inclusive of the stated value and means within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, "approximately the same" can mean that the difference relative to the stated value is within one or more standard deviations, or within ±30%, 20%, 10%, 5%.

[0054] In the accompanying drawings, the thickness of layers, films, panels, regions, etc. are exaggerated for clarity. Exemplary embodiments are described herein with reference to cross-sectional views that are schematic representations of idealized embodiments. As such, deviations from the shapes of the figures are to be expected as a result of, for example, manufacturing techniques and / or tolerances. Thus, the embodiments described herein should not be construed as limited to the specific shapes of the regions as shown herein, but rather include deviations in shape that result from, for example, manufacturing. For example, a region illustrated or described as flat may typically have rough and / or nonlinear features. Furthermore, sharp corners illustrated may be rounded. Thus, the regions illustrated in the figures are schematic in nature, and their shapes are not intended to illustrate the precise shape of the regions and are not intended to limit the scope of the claims.

[0055] In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits detailed descriptions of known functions and known components.

[0056] In recent years, market demand for narrow bezels has continued to increase, further reducing the bezels of display panels. At the same time, due to fierce market competition, dual-gate display products have continued to gain market share. The number of scan signals they receive is twice that of single-gate display products, further shortening pixel charging time. To ensure pixel charging rates and charging times, the output capacity of GOA needs to be continuously improved. Currently, the most effective way to ensure pixel charging is to directly increase the width-to-length ratio (W / L) of the transistors in the GOA unit, thereby ensuring charging time. However, as transistor size increases, the left and right bezels of the display panel will inevitably increase. Larger display panel bezels lack market competitiveness. The GOA design must not only meet the product bezel requirements, but also ensure the output capacity of the scan signal.

[0057] In view of this, an embodiment of the present disclosure provides a shift register, as shown in FIG. 3A to FIG. 3F , which includes:

[0058] substrate;

[0059] A plurality of transistors are located on one side of the substrate 1; the plurality of transistors include: a first transistor group MA, and a second transistor group MB;

[0060] At least one transistor of the first transistor group MA includes: a first electrode 1; the first electrode 1 includes: a first source main portion 111, a plurality of first source branches 112 connected to the first source main portion 111, a first drain main portion 121, and a plurality of first drain branches 122 connected to the first drain main portion 121; the first source branches 112 and the first drain branches 122 extend along a first direction X and are alternately distributed along a second direction Y; a channel region extending along the first direction X may be formed between adjacent first source branches 112 and first drain branches 122; optionally, the first source main portion 111 and the first source branches 112 may form sources of transistors in the first transistor group MA; the first drain main portion 121 and the first drain branches 122 may form drains of transistors in the first transistor group MA;

[0061] At least one transistor in the second transistor group MB includes: a second electrode 2; the second electrode 2 includes: a second source main portion 211, a plurality of second source branches 212 connected to the second source main portion 211, a second drain main portion 221, and a plurality of second drain branches 222 connected to the second drain main portion 221; the second source branches 212 and the second drain branches 222 extend along the second direction Y and are alternately distributed along the first direction X; a channel region extending along the second direction Y can be formed between adjacent second source branches 212 and second drain branches 222. Optionally, the second source main portion 211 and the second source branches 212 can form the source of the transistors in the second transistor group MB; the second drain main portion 221 and the second drain branches 222 can form the drain of the transistors in the second transistor group MB.

[0062] In the disclosed embodiment, a shift register includes a first transistor group MA and a second transistor group MB. In the first transistor group MA, the first source branches 112 and the first drain branches 122 extend along a first direction X and are alternately distributed along a second direction Y, while the second source branches 212 and the second drain branches 222 extend along the second direction Y and are alternately distributed along the first direction X. This allows the first transistor group MA to form multiple channel regions extending along the first direction X, while the second transistor group MB to form multiple channel regions extending along the second direction Y. This design employs a mixture of first-direction X-channels and second-direction Y-channels. This design achieves a narrow-frame design without increasing mask costs and process complexity, and without reducing the size of each transistor in the shift register (thus, without affecting charging efficiency). This improves the reliability of the narrow-frame architecture of high-resolution products and ensures product market competitiveness. Furthermore, while maintaining the same transistor layout space, transistors with X-channels along the first direction have a longer channel length than transistors with Y-channels along the second direction, thereby enhancing product competitiveness.

[0063] Specifically, as shown in Figure 2, the upper left figure of Figure 2 may correspond to a top view schematic diagram of a transistor in the second transistor group MB, the upper right figure of Figure 2 may correspond to a top view schematic diagram of a transistor in the first transistor group MA, the lower left figure of Figure 2 is a cross-sectional schematic diagram along the dotted line A1A2 in the upper left figure of Figure 2, and the lower right figure of Figure 2 is a cross-sectional schematic diagram along the dotted line A3A4 in the upper right figure of Figure 2, wherein the width f4 of the first source branch 112 in the first direction X may be equal to the width f1 of the second source branch 212 in the first direction X (for example, it may be 2.5 μm to 3.5 μm; for example, it may be 2.8 μm); the width f6 of the first drain branch 122 in the first direction X may be equal to the width f3 of the second drain branch 222 in the first direction X (for example, it may be 2.5 μm to 3.5 μm; for example, it may be 2.8 μm); the spacing f5 between the first source branch 112 and the first drain branch 122 in the first direction X The dimension a of the transistor layout space along the first direction X (e.g., 3 μm to 4 μm; e.g., 3.6 μm) may be equal to the distance f2 between the second source branch 212 and the second drain branch 222 in the first direction X. When the dimension a of the transistor layout space along the first direction X (e.g., 90 μm to 100 μm; e.g., 98.4 μm) is greater than the dimension b of the transistor layout space along the second direction Y (e.g., 55 μm to 65 μm; e.g., 60 μm), the total channel length of the transistor having an X-channel along the first direction (the upper right figure in FIG. 2 ) (i.e., equivalent to the total length of the meandering channel when straightened) is increased by 14.96% compared to the total channel length of the transistor having a Y-channel along the second direction (the upper left figure in FIG. 2 ) (i.e., equivalent to the total length of the meandering channel when straightened). When the transistor layout space remains unchanged, the transistor having an X-channel along the first direction has more advantages than the transistor having a Y-channel along the second direction, thereby improving product competitiveness.

[0064] In a possible implementation, the display panel may have a plurality of pixels distributed in an array. When the shift register is disposed on the display panel, the first direction X may be parallel to the pixel rows, and the second direction Y may be parallel to the pixel columns.

[0065] In one possible embodiment, in combination with FIG3D , in the first transistor group MA, the maximum length d1 of the first electrodes 1 of at least some of the transistors in the first direction X is greater than the maximum length d2 in the second direction Y. Specifically, for example, as in the first transistor M1 in FIG3D , the maximum length d1 of the first electrode 1 in the first direction X is greater than the maximum length d2 in the second direction Y. In the second transistor group MB, the maximum length d4 of the second electrodes 2 of at least some of the transistors in the second direction Y is greater than the maximum length d3 in the first direction X. Specifically, for example, as in the sixth transistor M6 in FIG3D , the maximum length d4 of the second electrode 2 in the second direction Y is greater than the maximum length d3 in the first direction X. In the disclosed embodiment, the channel region of the transistor having a longer length in the first direction X is arranged to extend along the first direction X, and the channel region of the transistor having a longer length in the second direction Y is arranged to extend along the second direction Y. That is, the corresponding channel extension design is performed according to the shape and size of each transistor itself. In this way, each transistor can have a longer channel length within the same layout space, and each transistor can have an optimal arrangement. Therefore, when the shift register is arranged in a display panel, a narrow frame of the display panel can be achieved.

[0066] It should be noted that, in the first transistor group MA, the maximum length d1 of the first electrode 1 of the transistor in the first direction X may be the distance between the first source main portion 111 and the first drain main portion 121 in the first direction X; in the first transistor group MA, the maximum length d2 of the first electrode 1 of the transistor in the second direction Y may be the distance between the two first source branches 112 (or the first drain branches 122) with the largest distance in the second direction Y, or may be the length of the first source main portion 111 (or the first drain main portion 121) in the second direction Y. Similarly, in the second transistor group MB, the maximum length d4 of the second electrode 2 of the transistor in the second direction Y may be the distance between the second source main portion 211 and the second drain main portion 221 in the second direction Y; in the second transistor group MB, the maximum length d3 of the second electrode 2 of the transistor in the first direction X may be the distance between the two second source branches 212 (or second drain branches 222) with the largest distance in the first direction X, or may be the length of the second source main portion 211 (or the second drain main portion 221) in the first direction X.

[0067] In one possible embodiment, as shown in FIG3A , the first transistor group MA includes: a first transistor M1; the first transistor M1 has an orthographic projection area on the substrate that is larger than the orthographic projection area of ​​any other transistor on the substrate; and the first transistor group MA further includes: a second transistor M2; the second transistor M2 has an orthographic projection area on the substrate that is larger than the orthographic projection area of ​​any other transistor other than the first transistor M1. In the disclosed embodiment, by configuring the channel regions of the first transistor M1 and the second transistor M2, which have larger areas in the shift register, to extend along the first direction X, the length of the shift register in the first direction X can be significantly reduced. Consequently, when the shift register is configured on a display panel, the width of the display panel's bezel can be significantly reduced.

[0068] In one possible embodiment, as shown in FIG3A , the first transistor group MA includes: a first transistor M1; the first transistor M1 is configured to output a signal to the output terminal OUTPUT according to the signal of the clock signal terminal CLK; the first transistor group M1 also includes: a second transistor M2; the second transistor M2 is configured to precharge the first node PU according to the signal input by the input terminal INPUT. In the embodiment of the present disclosure, since the transistors that perform the precharging function and the transistors that perform the output function in the shift register are generally large in size, by setting the channel region of the larger transistor to extend along the first direction X, the length of the shift register in the first direction X can be significantly reduced, and when the shift register is set on the display panel, the border width of the display panel can be significantly reduced.

[0069] In a possible embodiment, referring to FIG3A , the first transistor group MA further includes: a third transistor M3, a fourth transistor M4, and a fifth transistor M5; the shift register is used to provide a signal to the display panel, and the display panel has a display area AA; the first transistor M1 is located on a side of the shift register close to the display area AA; the second transistor M2 is located on a side of the first transistor M1 away from the display area AA; the third transistor M3 and the fourth transistor M4 are located in an area between the first transistor M1 and the second transistor M2, and the fifth transistor M5 is located on a side of the second transistor M2 away from the first transistor M1.

[0070] In a possible embodiment, referring to FIG3A , the second transistor group MB further includes: a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, and an eleventh transistor M11; the sixth transistor M6 is located between the second transistor M2 and the third transistor M3; the seventh transistor M7 is located between the second transistor M2 and the fifth transistor M5; the eighth transistor M8 is located between the seventh transistor M7 and the fifth transistor M5; the ninth transistor M9 is located between the fifth transistor M5 and the eighth transistor M8; the tenth transistor M10 is located on a side of the fifth transistor M5 away from the ninth transistor M9; and the eleventh transistor M11 is located between the ninth transistor M9 and the tenth transistor M10.

[0071] In one possible implementation, referring to FIG. 3A and FIG. 4 , where FIG. 4 may be an equivalent circuit diagram corresponding to FIG. 3A , a control electrode of the first transistor M1 is electrically connected to the first node PU, a first electrode of the first transistor M1 is electrically connected to the clock signal terminal CLK, and a second electrode of the first transistor M1 is electrically connected to the output terminal OUTPUT;

[0072] The control electrode and the first electrode of the second transistor M2 are electrically connected to the input terminal INPUT, and the second electrode of the second transistor M2 is electrically connected to the first node PU;

[0073] A control electrode of the third transistor M3 is electrically connected to the discharge control terminal TRST, a first electrode of the third transistor M3 is electrically connected to the first node PU, and a second electrode of the third transistor M3 is electrically connected to the second power supply terminal VGL;

[0074] The control electrode of the fourth transistor M4 is electrically connected to the discharge control terminal TRST, the first electrode of the fourth transistor M4 is electrically connected to the second power supply terminal VGH, and the second electrode of the fourth transistor M4 is electrically connected to the output terminal OUTPUT;

[0075] The control electrode of the fifth transistor M5 is electrically connected to the second node PD1, the first electrode of the fifth transistor M5 is electrically connected to the first power supply terminal VGH, and the second electrode of the fifth transistor M5 is electrically connected to the third node PD2;

[0076] a control electrode of the sixth transistor M6 electrically connected to the reset signal terminal TESET, a first electrode of the sixth transistor M6 electrically connected to the first node PU, and a second electrode of the sixth transistor M6 electrically connected to the second power supply terminal VGL;

[0077] A control electrode of the seventh transistor M7 is electrically connected to the third node PD2, a first electrode of the seventh transistor M7 is electrically connected to the second power supply terminal VGL, and a second electrode of the seventh transistor M7 is electrically connected to the output terminal OUTPUT;

[0078] The control electrode of the eighth transistor M8 is electrically connected to the third node PD2, the first electrode of the eighth transistor M8 is electrically connected to the first node PU, and the second electrode of the eighth transistor M8 is electrically connected to the second power supply terminal VGL;

[0079] The control electrode of the ninth transistor M9 is electrically connected to the first node PU, the first electrode of the ninth transistor M9 is electrically connected to the third node PD2, and the second electrode of the ninth transistor M9 is electrically connected to the second power supply terminal VGL;

[0080] The control electrode and the first electrode of the tenth transistor M10 are electrically connected to the first power supply terminal VGH, and the second electrode of the tenth transistor M10 is electrically connected to the second node PD2;

[0081] A control electrode of the eleventh transistor M11 is electrically connected to the first node PD, a first electrode of the eleventh transistor M11 is electrically connected to the second node PD2, and a second electrode of the eleventh transistor M11 is electrically connected to the second power supply terminal VGL.

[0082] In a possible implementation, referring to FIG. 3A and FIG. 4 , the shift register may further include a capacitor C, wherein one end of the capacitor C is electrically connected to the first node PU, and the other end is electrically connected to the output terminal OUTPUT.

[0083] In a possible implementation, the specific operating principles of the registers other than those shown in FIG. 3A and FIG. 4 may be as follows:

[0084] In the first stage T1: a high-level signal is input to the input terminal INPUT, and the first node PU is precharged through the second transistor M2. The potential of the first node PU changes from a low potential corresponding to the second power supply terminal VGL to a high potential corresponding to the first power supply terminal VGH. At this time, the ninth transistor is turned on, so that the potential of the third node PD2 changes from a high potential corresponding to the first power supply terminal VGH to a low potential corresponding to the second power supply terminal VGL.

[0085] In the second phase T2, the clock signal terminal CLK changes from the second power supply terminal VGL to the high potential corresponding to the first power supply terminal VGH. The first node PU is bootstrapped through the capacitor C, and the first transistor M1 is fully turned on. At this time, the output terminal OUTPUT outputs a high level.

[0086] In the third stage T3, the clock signal terminal CLK changes from the high potential corresponding to the first power supply terminal VGH to the second power supply terminal VGL, and the first node PU is reset after a delay of 1H. At this time, it is at a high level and pulls down the output terminal OUTPUT through the first transistor M1.

[0087] In the fourth stage T4: when the reset signal terminal RESET signal is pulled high, the first node PU is pulled down to a low potential corresponding to the second power supply terminal VGL through the sixth transistor, thereby turning off the first transistor M1, and the first node PD is changed from a low potential corresponding to the second power supply terminal VGL to a high potential corresponding to the first power supply terminal VGH through the output of the fifth transistor. At this time, the eighth transistor and the seventh transistor M7 respectively reduce the noise of the first node PU and the output terminal OUTPUT.

[0088] In one possible embodiment, referring to Figures 3A-3F , the shift register further includes: a plurality of cascade traces 3 extending along the second direction Y; the orthographic projections of the plurality of cascade traces 3 on the substrate are located between the orthographic projections of the second transistor M2 and the sixth transistor M6 on the substrate. In one possible embodiment, referring to Figures 3A-3E , the shift register further includes: a first via K1 electrically connected to at least one of the plurality of cascade traces 3; the orthographic projection of the first via K1 on the substrate is located between the orthographic projections of the second transistor M2 and the sixth transistor M6 on the substrate.

[0089] In the disclosed embodiment, by adjusting the channel regions of some transistors (e.g., the first transistor M1, the second transistor M2, the third transistor M3, and the fourth transistor M4) from the second direction Y to the first direction X, these transistors can be moved from a position close to the display area AA to a position away from the display area AA, i.e., the middle position of the shift register. At the same time, the associated cascade traces, including the signal traces corresponding to the output terminal OUTPUT, the input terminal INPUT, and the first node PU, and the first via K1 can be moved outward away from the display area AA, thereby reducing the number of vias near the periphery of the display area AA, facilitating the diffusion of the alignment liquid and thus improving the peripheral black line defects. In addition, the outward shift of the cascade traces 3 can also increase the ultraviolet light transmittance of the peripheral sealant area, ensuring the curing of the sealant, thereby improving product reliability.

[0090] In a possible implementation, the cascade line 3 may include: one or more of an input signal line, an output signal line, and a reset signal line.

[0091] In one possible embodiment, as shown in Figures 3A-3F , the shift register further includes: a plurality of connecting lines 4 extending along a first direction X, and a first active pattern block 50; the orthographic projection of the connecting lines 4 on the substrate has a first overlapping region S1 with the orthographic projection of the cascade trace 3 on the substrate; and the orthographic projection of the first active pattern block 50 on the substrate covers the first overlapping region S1. In the disclosed embodiment, the shift register further includes the first active pattern block 50, and the orthographic projection of the first active pattern block 50 on the substrate covers the first overlapping region S1 formed by the connecting lines 4 and the cascade trace 3, thereby preventing static electricity from causing a short circuit between the connecting lines 4 and the cascade trace 3.

[0092] In a possible embodiment, referring to Figure 2 and Figures 3A to 3F, at least one transistor among the multiple transistors includes: a gate layer MM1, an active layer MM2 located on the side of the gate layer MM1 away from the substrate 10, a source and drain layer MM3 (which may include a first electrode 1 and a second electrode 2) located on the side of the active layer MM2 away from the substrate 10, a passivation layer MM4 located on the side of the source and drain layer MM3 away from the substrate 10, and a conductive layer MM5 located on the side of the passivation layer MM4 away from the substrate 10; wherein the first active pattern block 50 may be located in the active layer 5.

[0093] In a possible embodiment, as shown in Figures 3A to 3F, the cascade trace 3 can be located in the gate layer MM1, the connecting line 4 can be located in the source and drain layer MM3, the first via K1 can be located in the passivation layer MM4, the conductive layer MM5 can include multiple strapping blocks 7, and the traces of the gate layer MM1 and the traces of the source and drain layer MM3 can be transferred through the strapping blocks 7 at the first via K1.

[0094] In a possible implementation, as shown in FIG. 2 , a gate insulating layer GI may be further provided between the gate layer MM1 and the active layer MM2 .

[0095] In the embodiment of the present disclosure, for the second transistor M2 that performs a pre-charging function for the first node PU, and the first transistor M1 that performs an output function to the output terminal OUTPUT, a channel design extending along the first direction X is adopted to ensure that the display panel frame can be effectively reduced without reducing the size of the transistors in the shift register; at the same time, when the first transistor M1 with a larger area adopts a channel design extending along the first direction X, the number of its channels (that is, the area between adjacent first source branches 112 and first drain branches 122) is reduced by about 80% compared to the original design, which greatly reduces the occurrence of channel short circuits and can avoid This prevents shift register failures caused by high incidence of foreign matter. In the new shift register layout design, except for the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, and the fifth transistor M5, all other transistors adopt a channel design extending along the second direction Y. This minimizes the shift register's area within the frame while maintaining the same transistor size. The layout areas of the first transistor M1 and the second transistor M2 are reduced by 4.3% and 8.2%, respectively, while maintaining the same transistor size. For example, the frame is reduced from 2.3mm to 2.0mm, a decrease of 13.04%. While achieving a narrow frame, this ensures output capacity and the pre-charge effect of the second transistor M2, increasing the reliability of the narrow-frame gate drive circuit architecture for high-resolution products and ensuring product market competitiveness.

[0096] Based on the same inventive concept, an embodiment of the present disclosure further provides a gate driving circuit, as shown in FIG5 , which includes a plurality of shift registers GOA1 provided by the embodiment of the present disclosure, and the plurality of shift registers GOA1 are cascaded.

[0097] Based on the same inventive concept, an embodiment of the present disclosure further provides a display panel, which includes a display area and a non-display area located on one side of the display area; wherein the non-display area has a gate driving circuit as provided in an embodiment of the present disclosure.

[0098] In one possible embodiment, in conjunction with FIG3A , dotted line F in FIG3A indicates the inner edge line of the frame sealant on the side closest to the display area. The display panel further includes: a frame sealant located on the side of the transistor facing away from the substrate; the orthographic projection of the frame sealant on the substrate covers the orthographic projection of the cascade trace 3 on the substrate 1. In the disclosed embodiment, by moving the cascade trace 3 outward, specifically to the area where the frame sealant is located, the UV transmittance of the peripheral frame sealant area can be increased, ensuring the curing of the frame sealant and improving product reliability.

[0099] In a possible implementation, as shown in FIG3A , the orthographic projection of the frame sealant on the substrate covers the orthographic projections of each transistor located on the side of the sixth transistor M6 away from the display area AA on the substrate, and covers at least a portion of the orthographic projection of the sixth transistor M6 on the substrate.

[0100] Based on the same inventive concept, an embodiment of the present disclosure further provides a display device, which includes a display panel provided by the embodiment of the present disclosure.

[0101] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0102] Obviously, those skilled in the art may make various changes and modifications to the embodiments of the present invention without departing from the spirit and scope of the embodiments of the present invention. Thus, if such changes and modifications of the embodiments of the present invention fall within the scope of the claims and their equivalents, the present invention is intended to include such changes and modifications.

Claims

1. A shift register, wherein: include: substrate; a plurality of transistors located on one side of the substrate; The plurality of transistors include: a first transistor group, and a second transistor group; At least one transistor in the first transistor group includes: a first electrode; the first electrode includes: a first source main portion, a plurality of first source branches connected to the first source main portion, a first drain main portion, and a plurality of first drain branches connected to the first drain main portion; the first source branches and the first drain branches extend along a first direction and are alternately distributed along a second direction; At least one of the transistors in the second transistor group includes: a second electrode; the second electrode includes: a second source main portion, a plurality of second source branches connected to the second source main portion, a second drain main portion, and a plurality of second drain branches connected to the second drain main portion; the second source branches and the second drain branches extend along the second direction and are alternately distributed along the first direction.

2. The shift register according to claim 1, wherein: In the first transistor group, the maximum length of the first electrodes of at least some of the transistors in the first direction is greater than the maximum length in the second direction; In the second transistor group, a maximum length of the second electrodes of at least some of the transistors in the second direction is greater than a maximum length in the first direction.

3. The shift register according to claim 1 or 2, wherein: The first transistor group includes: a first transistor; the first transistor has a positive projection area on the substrate that is larger than the positive projection area of any other transistor on the substrate; The first transistor group further includes: a second transistor; the orthographic projection area of the second transistor on the substrate is larger than the orthographic projection area of any other transistor except the first transistor on the substrate.

4. The shift register according to claim 1 or 2, wherein: The first transistor group includes: a first transistor; the first transistor is configured to output a signal to an output terminal according to a signal of a clock signal terminal; The first transistor group further includes a second transistor; the second transistor is configured to precharge the first node according to a signal inputted from the input terminal.

5. The shift register according to claim 3 or 4, wherein: The first transistor group further includes: a third transistor, a fourth transistor, and a fifth transistor; the shift register is used to provide a signal to a display panel, and the display panel has a display area; The first transistor is located on a side of the shift register close to the display area; the second transistor is located on a side of the first transistor away from the display area; the third transistor and the fourth transistor are located in an area between the first transistor and the second transistor, and the fifth transistor is located on a side of the second transistor away from the first transistor.

6. The shift register according to claim 5, wherein: The second transistor group further includes: a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, and an eleventh transistor; The sixth transistor is located between the second transistor and the third transistor; the seventh transistor is located between the second transistor and the fifth transistor; the eighth transistor is located between the seventh transistor and the fifth transistor; the ninth transistor is located between the fifth transistor and the eighth transistor; the tenth transistor is located on the side of the fifth transistor away from the ninth transistor; and the eleventh transistor is located between the ninth transistor and the tenth transistor.

7. The shift register according to claim 6, wherein: The control electrode of the first transistor is electrically connected to the first node, the first electrode of the first transistor is electrically connected to the clock signal terminal, and the second electrode of the first transistor is electrically connected to the output terminal; The control electrode and the first electrode of the second transistor are electrically connected to the input terminal, and the second electrode of the second transistor is electrically connected to the first node; The control electrode of the third transistor is electrically connected to the discharge control terminal, the first electrode of the third transistor is electrically connected to the first node, and the second electrode of the third transistor is electrically connected to the second power supply terminal; The control electrode of the fourth transistor is electrically connected to the discharge control terminal, the first electrode of the fourth transistor is electrically connected to the second power supply terminal, and the second electrode of the fourth transistor is electrically connected to the output terminal; The control electrode of the fifth transistor is electrically connected to the second node, the first electrode of the fifth transistor is electrically connected to the first power supply terminal, and the second electrode of the fifth transistor is electrically connected to the third node; The control electrode of the sixth transistor is electrically connected to the reset signal terminal, the first electrode of the sixth transistor is electrically connected to the first node, and the second electrode of the sixth transistor is electrically connected to the second power supply terminal; The control electrode of the seventh transistor is electrically connected to the third node, the first electrode of the seventh transistor is electrically connected to the second power supply terminal, and the second electrode of the seventh transistor is electrically connected to the output terminal; The control electrode of the eighth transistor is electrically connected to the third node, the first electrode of the eighth transistor is electrically connected to the first node, and the second electrode of the eighth transistor is electrically connected to the second power supply terminal; The control electrode of the ninth transistor is electrically connected to the first node, the first electrode of the ninth transistor is electrically connected to the third node, and the second electrode of the ninth transistor is electrically connected to the second power supply terminal; The control electrode and the first electrode of the tenth transistor are electrically connected to the first power supply terminal, and the second electrode of the tenth transistor is electrically connected to the second node; The control electrode of the eleventh transistor is electrically connected to the first node, the first electrode of the eleventh transistor is electrically connected to the second node, and the second electrode of the eleventh transistor is electrically connected to the second power supply terminal.

8. The shift register according to any one of claims 5 to 7, wherein: The shift register further includes: a plurality of cascade lines extending along the second direction; the orthographic projections of the plurality of cascade lines on the substrate are located between the orthographic projections of the second transistor and the sixth transistor on the substrate.

9. The shift register according to claim 8, wherein: The shift register further includes: a first via electrically connected to at least one cascade wiring among the plurality of cascade wirings; The orthographic projection of the first via on the substrate is located between the orthographic projections of the second transistor and the sixth transistor on the substrate.

10. The shift register according to any one of claims 7 to 9, wherein: The shift register further includes: a plurality of connection lines extending along the first direction, and a first active pattern block; The orthographic projection of the connection line on the substrate has a first overlapping area with the orthographic projection of the cascade line on the substrate; the orthographic projection of the first active pattern block on the substrate covers the first overlapping area.

11. The shift register according to claim 10, wherein: At least one transistor among the plurality of transistors includes: an active layer; and the first active pattern block is located in the active layer.

12. A gate drive circuit, wherein: It comprises a plurality of shift registers according to any one of claims 1 to 11, wherein the plurality of shift registers are cascaded.

13. A display panel, wherein: It comprises a display area and a non-display area located on one side of the display area; wherein the non-display area has the gate driving circuit as claimed in claim 12.

14. The display panel according to claim 13, wherein: The display panel further includes: a frame sealant located on a side of the transistor facing away from the substrate; The orthographic projection of the frame sealing adhesive on the substrate covers the orthographic projection of the cascade trace on the substrate.

15. A display device, wherein: Comprising the display panel according to claim 13 or 14.

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