Imaging device and camera system

Abstract

This imaging device includes a plurality of pixels arranged in a plurality of rows and columns, and a synthesis circuit to which analog signals output from the plurality of pixels are input. The analog signals include a reset signal that represents a reset level, and a pixel signal that represents the image of a subject. A synthesis circuit 50 outputs, within one frame period: a reset signal output from a certain pixel among the plurality of pixels; a pixel signal output from the certain pixel; and a reference signal obtained by synthesizing reset signals respectively output from two or more pixels included in a first group among the plurality of pixels.

Description

Imaging device and camera system

[0001] The present disclosure relates to an imaging device and a camera system.

[0002] 2. Description of the Related Art Image capture devices using a charge coupled device (CCD) image sensor and a complementary metal oxide semiconductor (CMOS) image sensor are widely used in digital cameras and the like.

[0003] Patent Document 1 discloses a technique for controlling an imaging device in which, when reading out a signal from the same pixel, the timing at which a first signal level of the pixel is read out after the photoelectric conversion signal has been transferred to a memory means and the timing at which a second signal level of the pixel is read out when the memory means is reset are different by one frame period.

[0004] Japanese Patent Application Laid-Open No. 2008-28517

[0005] The present disclosure provides an imaging device and the like that can improve image quality.

[0006] An imaging device according to one aspect of the present disclosure includes a plurality of pixels arranged in a plurality of rows and columns, and a synthesis circuit to which analog signals output from the plurality of pixels are input, the analog signals including a reset signal representing a reset level and a pixel signal representing an image of a subject, and the synthesis circuit outputs, within one frame period, a reference signal obtained by synthesizing the reset signal output from a first pixel of the plurality of pixels, the pixel signal output from the first pixel, and the reset signals output from each of two or more pixels included in a first group of the plurality of pixels.

[0007] A camera system according to one aspect of the present disclosure includes the imaging device described above.

[0008] According to the present disclosure, image quality can be improved.

[0009] FIG. 1 is a diagram showing an exemplary configuration of an imaging device according to Embodiment 1. FIG. 2 is a schematic diagram showing an exemplary circuit configuration of an imaging device according to Embodiment 1. FIG. 3 is a diagram showing an exemplary configuration of a column circuit according to Embodiment 1. FIG. 4 is a timing chart for explaining an example of operation of the imaging device according to Embodiment 1. FIG. 5 is a schematic diagram showing an exemplary circuit configuration of an imaging device according to Modification 1 of Embodiment 1. FIG. 6 is a timing chart for explaining an example of operation of the imaging device according to Modification 1 of Embodiment 1. FIG. 7 is a schematic diagram showing an exemplary circuit configuration of an imaging device according to Modification 2 of Embodiment 1. FIG. 8 is a timing chart for explaining an example of operation of the imaging device according to Modification 2 of Embodiment 1. FIG. 9 is a block diagram showing an example of the configuration of a camera system according to Embodiment 2.

[0010] (Knowledge forming the basis of the present disclosure) In an imaging device, image quality is one of the important qualities. Suppressing noise in signals is effective for improving image quality. For example, in the technology described in Patent Document 1, fixed pattern noise is suppressed and high image quality is achieved by subtracting, after analog-to-digital conversion (AD conversion), a first signal level of a pixel after a photoelectric conversion signal has been transferred to a memory means from a second signal level of the pixel when the memory means is reset. However, there may be cases where image quality is not sufficiently improved by merely suppressing fixed pattern noise using the technology described in Patent Document 1.

[0011] As in the technology described in Patent Document 1, analog signals output from pixels are subjected to AD conversion. When AD converting analog signals such as pixel signals representing an image of a subject, the analog signal to be AD converted may be directly AD converted, but it is more effective to AD convert the difference between the analog signal to be AD converted and a reference signal. AD converting such a difference can reduce the signal level to be AD converted, thereby enabling improved resolution in AD conversion, reduced conversion processing, reduced power consumption, and the like.

[0012] On the other hand, because noise can also occur in the reference signal, suppressing noise in the reference signal is also important for improving image quality. For example, if a pixel that outputs a pixel signal also outputs a reference signal, various noises resulting from the pixel's configuration and driving may be included in the reference signal. While a voltage supply circuit may be used to supply a reference voltage as the reference signal, it is necessary to suppress noise in the reference voltage. Furthermore, if the reference voltage is supplied uniformly to all pixels, it is not possible to supply a reference voltage that corresponds to the pixel's position, which can lead to noise. Furthermore, supplying a reference voltage that corresponds to the pixel's position requires a complex circuit configuration.

[0013] One aspect of the present disclosure is based on the findings of the inventors of the present application, and provides an imaging device and the like that can improve image quality.

[0014] (Summary of the Present Disclosure) As an overview of the present disclosure, examples of an imaging device and a camera system according to the present disclosure are described below.

[0015] For example, an imaging device according to a first aspect of the present disclosure includes a plurality of pixels arranged in a plurality of rows and columns, and a synthesis circuit to which analog signals output from the plurality of pixels are input, the analog signals including a reset signal representing a reset level and a pixel signal representing an image of a subject, and the synthesis circuit outputs, within one frame period, a reference signal obtained by synthesizing the reset signal output from a first pixel of the plurality of pixels, the pixel signal output from the first pixel, and the reset signals output from two or more pixels included in a first group of the plurality of pixels.

[0016] As a result, the combining circuit outputs a reference signal in addition to the reset signal and pixel signal, making it possible to perform AD conversion on the reset signal and pixel signal using the difference between the reference signal and the reset signal in subsequent processing. This reduces the signal level to be AD converted, improving the resolution of AD conversion, reducing the conversion process, and reducing power consumption. Furthermore, since the combining circuit outputs a reference signal that combines reset signals output from two or more pixels, the random noise in the reset signals cancels out through the combination, resulting in a noise-reduced reference signal being output. Therefore, the noise-reduced reference signal can be used to obtain the difference between the reset signal and the pixel signal, and the noise in the difference can also be reduced. From the above, the imaging device according to this aspect enables improved image quality.

[0017] Also, for example, an imaging device according to a second aspect of the present disclosure is the imaging device according to the first aspect, further comprising a conversion circuit that receives the output of the synthesis circuit and generates a digital signal, wherein the conversion circuit generates a first digital signal based on the difference between the reset signal output from the first pixel and the reference signal output at a first timing, and generates a second digital signal based on the difference between the pixel signal output from the first pixel and the reference signal output at a second timing.

[0018] This makes it possible to output the first digital signal and the second digital signal with reduced noise by using a reference signal in which noise has been reduced by combining reset signals output from two or more pixels.

[0019] Also, for example, an imaging device according to a third aspect of the present disclosure is the imaging device according to the second aspect, further comprising a frame memory and a processing circuit, wherein the frame memory temporarily holds the first digital signal generated by the conversion circuit, and the processing circuit outputs the difference between the second digital signal and the first digital signal held in the frame memory.

[0020] This allows common noise between the first digital signal and the second digital signal to be eliminated by obtaining the difference, thereby obtaining a digital signal with reduced noise.

[0021] Also, for example, an imaging device according to a fourth aspect of the present disclosure is an imaging device according to any one of the first to third aspects, in which the combining circuit has a plurality of output signal lines connected to the two or more pixels included in the first group, and at least one switch that connects the plurality of output signal lines to each other so that they are conductively connected.

[0022] This allows the synthesis circuit to switch between synthesizing the analog signals output from two or more pixels included in the first group and synthesizing the analog signals.

[0023] Also, for example, an imaging device according to a fifth aspect of the present disclosure is the imaging device according to the fourth aspect, wherein the plurality of output signal lines include a first output signal line connected to the first pixel and a second output signal line connected to a second pixel of the plurality of pixels, the at least one switch includes a switch connected between the first output signal line and the second output signal line, and the first pixel and the second pixel are sensitive to light in different wavelength ranges.

[0024] This allows the combining circuit to output a reference signal that is a combination of reset signals from pixels that are sensitive to light in different wavelength ranges.

[0025] Also, for example, an imaging device according to a sixth aspect of the present disclosure is an imaging device according to any one of the first to fifth aspects, wherein the two or more pixels included in the first group include the first pixel.

[0026] With this, the first pixel that outputs the pixel signal is included in two or more pixels in the first group that output the reset signal for combining the reference signal, so that the reference signal can be output with a simple configuration.

[0027] Also, for example, an imaging device according to a seventh aspect of the present disclosure is an imaging device according to any one of the first to sixth aspects, in which the two or more pixels included in the first group are located in the same row as the first pixel.

[0028] As a result, the first pixel that outputs the pixel signal is located in the same row as two or more pixels of the first group that output the reset signal for combining the reference signal, so that the reference signal can be output with a simple configuration.

[0029] Also, for example, an imaging device according to an eighth aspect of the present disclosure is an imaging device according to any one of the first to fifth aspects, in which the two or more pixels included in the first group are located in a different row from the first pixel.

[0030] As a result, since the first pixel that outputs the pixel signal is located in a different row from the two or more pixels in the first group that output the reset signal for synthesizing the reference signal, it is possible to generate the reference signal without performing a reset operation on the first pixel, thereby enabling faster operation.

[0031] Furthermore, for example, an imaging device according to a ninth aspect of the present disclosure is an imaging device according to any one of the first to fifth aspects and the eighth aspect, in which each of the two or more pixels included in the first group is a pixel different from the first pixel and is an ineffective pixel in which the signal level of the analog signal does not change when light is incident.

[0032] As a result, an ineffective pixel different from the first pixel that outputs a pixel signal outputs a reset signal for combining a reference signal, thereby enabling non-destructive reading of pixel signals from pixels.

[0033] Also, for example, an imaging device according to a tenth aspect of the present disclosure is an imaging device according to any one of the first to ninth aspects, wherein the number of the two or more pixels included in the first group is ten or more.

[0034] This further reduces noise in the reference signal by increasing the number of reset signals that are combined.

[0035] Also, for example, a camera system according to an eleventh aspect of the present disclosure includes the imaging device according to any one of the first to tenth aspects.

[0036] As a result, the camera system according to this aspect includes the imaging device described above, and therefore can improve image quality.

[0037] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. Note that the embodiments described below are all comprehensive or specific examples. The numerical values, shapes, materials, components, component arrangements and connection forms, steps, and step orders shown in the following embodiments are merely examples and are not intended to limit the present disclosure. The various aspects described in this specification can be combined with each other as long as no contradiction occurs. Furthermore, among the components in the following embodiments, components not recited in independent claims will be described as optional components. In the following description, components having substantially the same functions will be designated by common reference symbols, and their description may be omitted. Furthermore, to avoid overly complicated drawings, illustration of some elements may be omitted.

[0038] Furthermore, the drawings are schematic diagrams and are not necessarily drawn to scale.

[0039] Furthermore, in this specification, terms indicating relationships between elements, such as "equal," terms indicating the shapes of elements, such as "square" or "circle," and numerical ranges are not expressions that express only the strict meaning, but are expressions that also include a substantially equivalent range, for example, a difference of about a few percent.

[0040] Furthermore, in this specification, the terms "upper" and "lower" do not refer to the upper direction (vertically upper) and lower direction (vertically lower) in absolute spatial recognition, but are used as terms defined by a relative positional relationship based on the stacking order in the stacked structure. Specifically, the light-receiving side of the imaging device is referred to as "upper," and the side opposite the light-receiving side is referred to as "lower." Note that terms such as "upper" and "lower" are used solely to specify the relative arrangement of components and are not intended to limit the orientation of the imaging device during use. Furthermore, the terms "upper" and "lower" are used not only when two components are spaced apart and another component is present between the two components, but also when two components are closely arranged and in contact with each other. Furthermore, in this specification, "plan view" refers to a view perpendicular to the main surface of the semiconductor substrate, in other words, when viewed from the thickness direction of the semiconductor substrate.

[0041] Furthermore, in the description of the circuit configuration in this specification, "connected" includes not only a direct connection via a conductor but also an electrical connection via another circuit element. Furthermore, "C is connected between A and B" means that a part of C (e.g., one end) is connected to A and another part of C (e.g., the other end) is connected to B, meaning that C is arranged in series in the path connecting A and B. "A path connecting A and B" means a path made up of a conductor electrically connecting A to B.

[0042] First Embodiment An imaging device according to a first embodiment will be described below.

[0043] [Overall Configuration] First, the overall configuration of the imaging device according to this embodiment will be described.

[0044] Fig. 1 is a diagram showing an exemplary configuration of an imaging device 100 according to embodiment 1. As shown in Fig. 1, the imaging device 100 has a plurality of pixels PX and a peripheral circuit 40 formed on a semiconductor substrate 60.

[0045] Each pixel PX includes a photoelectric conversion unit 12. The photoelectric conversion unit 12 generates positive and negative charges, typically hole-electron pairs, in response to incident light. The charges generated in the photoelectric conversion unit 12 are used as signal charges. In other words, the photoelectric conversion unit 12 converts light into signal charges. The photoelectric conversion unit 12 is, for example, a photoelectric conversion structure including a photoelectric conversion layer disposed above a semiconductor substrate 60. The photoelectric conversion unit 12 may also be a photodiode formed on the semiconductor substrate 60. Note that, while FIG. 1 illustrates the photoelectric conversion units 12 of each pixel PX as being spatially separated from one another, this is merely for convenience of explanation, and the photoelectric conversion units 12 of multiple pixels PX may be disposed continuously above the semiconductor substrate 60 without any gaps between them.

[0046] The plurality of pixels PX are arranged in a plurality of rows and columns in a plan view. The plurality of pixels PX are arranged, for example, two-dimensionally on the semiconductor substrate 60 to form an imaging region R1. For example, if each pixel PX has a photoelectric conversion unit 12 arranged above the semiconductor substrate 60, the imaging region R1 can be defined as the region of the semiconductor substrate 60 that is covered by the photoelectric conversion unit 12.

[0047] The number and arrangement of the pixels PX are not limited to the example shown in the figure. Furthermore, in the example shown in Figure 1, the center of each pixel PX is located on a lattice point of a square lattice, but for example, multiple pixels PX may be arranged so that the center of each pixel PX is located on a lattice point of a triangular lattice, a hexagonal lattice, or the like. Therefore, the column direction and the row direction do not need to be perpendicular to each other as long as they intersect.

[0048] 1, each pixel PX has a color filter CF. The color filter CF is disposed on the light incident side of the photoelectric conversion unit 12. Note that when the imaging device 100 captures a black and white image, each pixel PX does not need to have a color filter CF.

[0049] In the example shown in FIG. 1 , the peripheral circuit 40 includes a vertical scanning circuit 42 and a horizontal signal readout circuit 44. Also, as shown in FIG. 1 , the peripheral circuit 40 may additionally include a control circuit 46. The peripheral circuit 40 may further include, for example, a voltage supply circuit that supplies a predetermined voltage to the pixels PX and the like. The peripheral circuit 40 may further include a signal processing circuit, an output circuit, and the like. The peripheral circuit 40 is disposed, for example, in a peripheral region R2. The peripheral region R2 is a region on the semiconductor substrate 60 surrounding the imaging region R1. Note that at least a portion of the peripheral circuit 40 may be disposed on one or more semiconductor substrates other than the semiconductor substrate 60 on which the pixels PX are formed. In other words, at least a portion of the peripheral circuit 40 does not have to be disposed in the peripheral region R2. In this case, the one or more other semiconductor substrates may be stacked on the semiconductor substrate 60. Furthermore, a portion of the components included in the pixels PX may also be disposed on one or more other semiconductor substrates.

[0050] The vertical scanning circuit 42, also called a row scanning circuit, is connected to row control lines SL provided corresponding to each row of the plurality of pixels PX. For ease of viewing, only one row control line SL is shown per row in FIG. 1 , but as will be described later, the row control line SL may include two or more control lines per row. The vertical scanning circuit 42 applies a predetermined voltage to the row control line SL to select the pixels PX row by row, and causes the pixels PX to output signals, perform reset operations, and the like.

[0051] The horizontal signal readout circuit 44, also called a column scanning circuit, is connected to vertical signal lines 35 provided corresponding to each column of pixels PX via column circuits 43 (described later). The columns of pixels PX correspond, for example, to the vertical signal lines 35 in a one-to-one relationship. The vertical signal lines 35 are an example of output signal lines. The horizontal signal readout circuit 44 sequentially reads out signals from the column circuits 43 to a subsequent circuit (not shown).

[0052] The row control lines SL and the vertical signal lines 35 are formed in, for example, a wiring layer on the semiconductor substrate 60 .

[0053] The control circuit 46 receives command data, a clock, and the like provided, for example, from outside the imaging device 100, and controls the entire imaging device 100. The control circuit 46 has, for example, a timing generator and supplies drive signals to the vertical scanning circuit 42, the horizontal signal readout circuit 44, and the like. The control circuit 46 can be realized, for example, by a microcontroller including one or more processors. The functions of the control circuit 46 may be realized by a combination of a general-purpose processing circuit and software, or by hardware specialized for such processing.

[0054] [Circuit Configuration] Next, the circuit configuration of the imaging device 100 will be described.

[0055] FIG. 2 is a schematic diagram illustrating an exemplary circuit configuration of an imaging device 100 according to the present embodiment. For ease of viewing, FIG. 2 illustrates three columns of pixels PXn, which are pixels PX in the nth row, among the multiple pixels PX. For columns other than the illustrated columns, the circuit configuration corresponding to the illustrated columns is repeated. For ease of viewing, FIG. 2 illustrates only the wiring and circuits necessary for explanation, and the circuit configuration of the imaging device 100 may include wiring, circuits, and the like not illustrated in FIG. 2 .

[0056] 2, the imaging device 100 includes, in addition to the configuration shown in FIG. 1, a reset voltage line 31, a synthesis circuit 50 including a plurality of switches 51 and a plurality of vertical signal lines 35, a current source 39, and a column circuit 43. The switches 51, the current source 39, and the column circuit 43 may be part of the peripheral circuit 40 described above. The reset voltage line 31, the current source 39, and the column circuit 43 are provided corresponding to each column of a plurality of pixels PX. In other words, the imaging device 100 includes a plurality of reset voltage lines 31, a plurality of current sources 39, and a plurality of column circuits 43.

[0057] As shown in FIG. 2, each of the plurality of pixels PX includes a photoelectric conversion unit 12, a reset transistor 22, an amplification transistor 23, a selection transistor 24, and a charge storage unit FD.

[0058] The charge storage unit FD is connected to the photoelectric conversion unit 12 and stores signal charges generated by the photoelectric conversion unit 12. The charge storage unit FD stores signal charges corresponding to light incident on the pixel PX. The charge storage unit FD is also called a "floating diffusion node."

[0059] The photoelectric conversion unit 12 includes a pixel electrode 12a, a counter electrode 12c, and a photoelectric conversion layer 12b disposed between the pixel electrode 12a and the counter electrode 12c. The pixel electrode 12a, the photoelectric conversion layer 12b, and the counter electrode 12c are stacked in this order on a semiconductor substrate 60, for example. The photoelectric conversion unit 12 may further include other elements such as an electron blocking layer and a hole blocking layer.

[0060] The counter electrode 12c and the photoelectric conversion layer 12b are formed, for example, across multiple pixels PX. The pixel electrode 12a is provided for each pixel PX. The pixel electrode 12a is electrically isolated from the pixel electrodes 12a of other pixels PX. Note that at least one of the counter electrode 12c and the photoelectric conversion layer 12b may be provided separately for one or more pixels PX.

[0061] The pixel electrode 12a is electrically connected to the photoelectric conversion layer 12b and serves to collect signal charges generated in the photoelectric conversion layer 12b. The pixel electrode 12a is connected to a charge accumulation unit FD. The pixel electrode 12a is formed using a conductive material. The signal charges collected by the pixel electrode 12a are accumulated in the charge accumulation unit FD.

[0062] The counter electrode 12c is, for example, a transparent electrode formed from a transparent conductive material. The counter electrode 12c is disposed on the side of the photoelectric conversion layer 12b where light is incident. A bias voltage VITO is supplied to the counter electrode 12c. By controlling the bias voltage VITO, either the holes or the electrons of the hole-electron pairs generated in the photoelectric conversion layer 12b by photoelectric conversion can be collected by the pixel electrode 12a as signal charges. For example, when holes are used as signal charges, a bias voltage VITO that makes the counter electrode 12c higher in potential than the pixel electrode 12a is applied to the counter electrode 12c, thereby allowing the pixel electrode 12a to selectively collect the holes. Note that it is also possible to selectively collect electrons by the pixel electrode 12a by making the counter electrode 12c lower in potential than the pixel electrode 12a. Furthermore, when the imaging device 100 is driven using the global shutter method, for example, signal reading is performed during a period when a bias voltage VITO, which does not substantially cause movement from the photoelectric conversion layer 12b to the pixel electrode 12a, is applied to the opposing electrode 12c.

[0063] The photoelectric conversion layer 12b is a layer that absorbs photons and generates photocharges that become signal charges. Specifically, the photoelectric conversion layer 12b receives incident light and generates hole-electron pairs. In other words, the signal charges are either holes or electrons. For example, when holes are used as signal charges, the holes are collected by the pixel electrode 12a. Electrons, which are charges of the opposite polarity to the signal charges, are collected by the counter electrode 12c. The photoelectric conversion layer 12b is made of a photoelectric conversion material, and is formed, for example, from an organic semiconductor material. The photoelectric conversion layer 12b may also be formed from an inorganic semiconductor material.

[0064] The reset transistor 22, the amplification transistor 23, and the selection transistor 24 are, for example, field effect transistors (FETs) formed on a semiconductor substrate 60 that supports the photoelectric conversion unit 12. For each of the reset transistor 22, the amplification transistor 23, and the selection transistor 24, for example, an N-channel MOSFET (Metal Oxide Semiconductor FET) is used.

[0065] One of the source and drain of the reset transistor 22 is connected to the charge storage unit FD. The other of the source and drain of the reset transistor 22 is connected to a reset voltage line 31. A reset voltage is supplied to the other of the source and drain of the reset transistor 22, for example, via the reset voltage line 31. The reset voltage line 31 may also be part of a feedback circuit in which a feedback path is formed for negatively feeding back the output of the pixel PX. In this case, a feedback voltage for negatively feeding back the output of the pixel PX is supplied to the reset voltage line 31 as a reset voltage. The gate of the reset transistor 22 is connected to a reset control signal line (not shown in FIG. 2 ) included in the row control line SL. A reset signal RST is supplied to the gate of the reset transistor 22 from the vertical scanning circuit 42 via the reset control signal line. The reset transistor 22 is turned on, for example, when the reset signal RST is at a high level. When the reset transistor 22 is turned on, the potential of the charge storage unit FD is reset to a reset voltage. The reset voltage is, for example, greater than 0 V and equal to or less than 1 V. Furthermore, when the reset signal RST is at a low level, the reset transistor 22 is turned off, and insulates the charge storage unit FD from the reset voltage line 31. Note that the on and off states of the transistor correspond to the conduction and non-conduction of the transistor, respectively.

[0066] The reset voltage lines 31 are provided corresponding to each column of the pixels PX. For example, there is a one-to-one correspondence between the columns of the pixels PX and the reset voltage lines 31. The reset voltage lines 31 extend in the column direction and are connected to each pixel PX in the corresponding column. The reset voltage lines 31 are formed, for example, in a wiring layer on the semiconductor substrate 60.

[0067] A power supply voltage VDD is supplied to one of the source and drain of the amplification transistor 23. The other of the source and drain of the amplification transistor 23 is connected to one of the source and drain of the selection transistor 24. The gate of the amplification transistor 23 is connected to the charge storage unit FD. As a result, the amplification transistor 23 forms a source follower circuit together with the current source 39 when the selection transistor 24 is in an on state. At this time, the other of the source and drain of the amplification transistor 23 outputs an analog signal corresponding to the potential of the charge storage unit FD to the vertical signal line 35 via the selection transistor 24. The potential of the charge storage unit FD after exposure of the pixel PX corresponds to the amount of signal charge stored in the charge storage unit FD by exposure.

[0068] One of the source and drain of the selection transistor 24 is connected to the other of the source and drain of the amplification transistor 23. The other of the source and drain of the selection transistor 24 is connected to a vertical signal line 35. The gate of the selection transistor 24 is connected to a selection control signal line (not shown in FIG. 2 ) included in the row control line SL. A selection signal SEL is supplied to the gate of the selection transistor 24 from the vertical scanning circuit 42 via the selection control signal line. When the selection signal SEL is at a high level, the selection transistor 24 is turned on and outputs an analog signal from the amplification transistor 23 to the vertical signal line 35. In other words, the analog signal is read out from the pixel PX to the column circuit 43 via the vertical signal line 35. When the selection signal SEL is at a low level, the selection transistor 24 is turned off and insulates the amplification transistor 23 from the vertical signal line 35.

[0069] The combining circuit 50 receives analog signals output from the multiple pixels PX. The analog signals input to the combining circuit 50 include a reset signal representing a reset level and a pixel signal representing an image of a subject. The reset signal is a signal output from the pixel PX when the potential of the charge storage unit FD is at a reset voltage. The pixel signal is a signal output from the pixel PX according to the amount of signal charge accumulated in the charge storage unit FD by exposure. The combining circuit 50 outputs, within one frame period, a reference signal obtained by combining the reset signal output from one pixel PX among the multiple pixels PX, the pixel signal output from that one pixel PX, and the reset signals output from two or more pixels PX included in a first group among the multiple pixels PX. In this specification, one frame period refers to the period during which each pixel PX outputs a signal for determining the pixel value of one image. In other words, one image can be generated by driving the imaging device 100 for one frame period.

[0070] As described above, the combining circuit 50 includes a plurality of vertical signal lines 35 and a plurality of switches 51. In the present embodiment, each vertical signal line 35 provided corresponding to each column of a plurality of pixels PX is connected to all of the pixels PX in the corresponding column.

[0071] Each of the switches 51 is connected between two vertical signal lines 35 corresponding to different columns of pixels PX. In the example shown in Fig. 2, each of the switches 51 is connected between two vertical signal lines 35 corresponding to two adjacent columns. Note that the columns of pixels PX corresponding to the two vertical signal lines 35 connected to the switch 51 do not have to be adjacent to each other.

[0072] Each switch 51 is, for example, an FET formed on the semiconductor substrate 60, and its operation is controlled by a switch control signal S0 applied to its gate. The switch control signal S0 is supplied from, for example, the control circuit 46. The multiple switches 51 may be formed on a semiconductor substrate other than the semiconductor substrate 60, and the other semiconductor substrate may be stacked on the semiconductor substrate 60.

[0073] The multiple switches 51 conductively connect multiple vertical signal lines 35 corresponding to multiple columns of different pixels PX to each other. Therefore, the number of multiple switches 51 may be one less than the number of multiple vertical signal lines 35 that are conductively connected. When the number of multiple vertical signal lines 35 that are conductively connected is two, the number of switches 51 may be one. Alternatively, the number of multiple switches 51 may be the same as the number of multiple vertical signal lines 35 that are conductively connected. In this case, one switch 51 is provided corresponding to each of the multiple vertical signal lines 35, and each switch 51 is connected between the multiple vertical signal lines 35 and wiring that connects the multiple vertical signal lines 35 to each other.

[0074] The switches 51 are turned on when the switch control signal S0 is at a high level, and mutually connect (short-circuit) the multiple vertical signal lines 35 connected to the multiple switches 51. This allows analog signals output from the pixels PX to be combined onto the multiple vertical signal lines 35 connected to the multiple switches 51. Furthermore, the multiple switches 51 are turned off when the switch control signal S0 is at a low level, and insulate the multiple vertical signal lines 35 connected to the multiple switches 51. This allows the combining circuit 50 to control whether or not to combine the analog signals output from the pixels PX onto the multiple vertical signal lines 35 connected to the multiple switches 51. For example, the same switch control signal S0 is supplied to each of the multiple switches 51, and the same control is performed.

[0075] The number of the vertical signal lines 35 electrically connected to each other by the switches 51 is, for example, 10 or more. That is, the number of two or more pixels PX included in the first group, whose reset signals are combined by the combining circuit 50 to generate a reference signal, is also 10 or more. For example, all vertical signal lines 35 corresponding to all columns of the pixels PX are electrically connected to each other by the switches 51. That is, the combining circuit 50 may combine the reset signals of all pixels PX in the same row to generate a reference signal. Note that when a column of the pixels PX is divided into two or more blocks, the vertical signal lines 35 corresponding to the columns of the block may be electrically connected to each other by the switches 51 for each of the two or more blocks.

[0076] In the example shown in FIG. 2 , two of the three vertical signal lines 35 in the nth row are connected to pixels PXn having green (G) color filters CF, and one vertical signal line 35 is connected to pixels PXn having red (R) color filters CF. The color filters CF in the case shown in FIG. 2 are arranged in a quad-Bayer array, for example, in which color filters CF of the same color are arranged in four adjacent pixels PX arranged in two rows and two columns. The pixel PXn having the green color filter CF and the pixel PXn having the red color filter CF are sensitive to light in different wavelength ranges. In this embodiment, the pixel PXn having the red color filter CF is an example of a first pixel, and the pixel PXn having the green color filter CF in the column adjacent to the first pixel is an example of a second pixel. Furthermore, the vertical signal line 35 connected to the first pixel is an example of a first output signal line, and the vertical signal line 35 connected to the second pixel is an example of a second output signal line. The multiple switches 51 include a switch 51 connected between the first output signal line and the second output signal line. Although not shown, the multiple pixels PX may include pixels PX having blue (B) color filters CF. Note that the arrangement pattern of the color filters CF is not limited to a quad Bayer arrangement, and various arrangement patterns can be used. Furthermore, the multiple pixels PX may include pixels PX having color filters CF and pixels PX not having color filters CF (i.e., white pixels).

[0077] The analog signals output from the pixels PX and input to the vertical signal lines 35 of the composition circuit 50 via the selection transistors 24 are input to corresponding column circuits 43 among a plurality of column circuits 43 provided for each column of pixels PX corresponding to the vertical signal lines 35. The columns of pixels PX correspond to the column circuits 43, for example, in a one-to-one correspondence. The column circuits 43 perform noise suppression signal processing, typified by correlated double sampling, analog-to-digital conversion, and the like. The signals from the column circuits 43 are sequentially read out by the horizontal signal readout circuit 44 described above.

[0078] Here, the column circuits 43 will be described in detail. Fig. 3 is a diagram showing an exemplary configuration of the column circuits 43. Each column circuit 43 has, for example, the configuration shown in Fig. 3. In the example shown in Fig. 3, the column circuit 43 includes a conversion circuit 47, a memory 48, and a processing circuit 49.

[0079] The conversion circuit 47 receives the output (i.e., analog signal) of the synthesis circuit 50 via the vertical signal line 35 and generates a digital signal. The conversion circuit 47 also temporarily holds the input analog signal and generates a digital signal based on the difference between the analog signals input at different times. The conversion circuit 47 has, for example, an AD conversion circuit (analog-digital converter) and a circuit configured with a capacitive element for temporarily holding the input analog signal.

[0080] The memory 48 is an example of a frame memory that temporarily stores the digital signal generated by the conversion circuit 47. The memory 48 may be shared by two or more column circuits 43 that are provided corresponding to different columns of pixels PX.

[0081] The processing circuit 49 performs signal processing on the digital signal generated by the conversion circuit 47. The processing circuit 49 outputs, for example, the difference between the digital signal generated by the conversion circuit 47 and the digital signal temporarily stored in the memory 48. The processing circuit 49 may be shared by two or more column circuits 43 provided corresponding to different columns of pixels PX. The processing circuit 49 may be realized, for example, by a microcontroller including one or more processors. The functions of the processing circuit 49 may be realized by a combination of a general-purpose processing circuit and software, or by hardware specialized for such processing.

[0082] The column circuit 43 does not have to include the memory 48 and the processing circuit 49. For example, in the imaging device 100, the memory 48 and the processing circuit 49 may be provided subsequent to the horizontal signal readout circuit 44. Furthermore, at least a portion of the column circuit 43 does not have to be provided in the imaging device 100. For example, the imaging device 100 may be a device that outputs an analog signal output from the combining circuit 50 to another device, or a device that outputs a digital signal output from the conversion circuit 47 to another device.

[0083] [Operation of Imaging Device] Next, the operation (driving method) of the imaging device 100 according to this embodiment will be described. The circuits of the multiple pixels PX are driven under the control of the control circuit 46. The imaging device 100 may be driven by a global shutter system or a rolling shutter system.

[0084] FIG. 4 is a timing chart illustrating an example of the operation of the imaging device 100 according to the present embodiment. FIG. 4 shows the voltage levels of the selection signal SEL and reset signal RST of the nth and n+1th rows of pixels PX, as well as the switch control signal S0, during one frame period for generating one image. In FIG. 4 and the following figures, the letters n, n+1, etc., suffixed to the reference symbols for the selection signal SEL and reset signal RST indicate the row of the pixel PX, where n is an integer equal to or greater than 0. For example, the selection signal SELn indicates the selection signal SEL applied to the gate of the selection transistor 24 of the pixel PX in the nth row. The numbers representing the rows of the pixel PX indicate the signal readout order; for example, signals are read out starting from row 0. The signal readout order is the same as the order in which the rows of the pixels PX are arranged in the column direction. In FIG. 4 and the following timing charts, "H" indicates a high level and "L" indicates a low level. In addition, in FIG. 4 and the timing charts described below, periods marked with diagonal lines indicate periods for reading out reset signals, periods marked with dots indicate periods for reading out reference signals, and periods marked with horizontal stripes indicate periods for reading out pixel signals.

[0085] Table 1 below shows the signal levels of signals generated during the operation shown in FIG. 4 . Vrst in Table 1 represents the signal level when the potential of the pixel PX is reset to the reset voltage. ΔVn represents the fixed noise of the pixel PX, which depends on the row position of the pixel PX. The farther the pixel PX is from the column circuit 43, the greater the voltage drop in the vertical signal line 35, which manifests as fixed noise of the pixel PX. ΔVth represents the fixed noise of the pixel PX due to performance variations in the amplifier transistor 23. ΔkTC represents kTC noise generated in the pixel PX when the reset transistor 22 is turned on and off. Such kTC noise is also called reset noise. ΔVsf represents random noise generated when the amplifier transistor 23 outputs a signal in the pixel PX. Vsig represents the signal level corresponding to the amount of signal charge accumulated in the charge storage unit FD due to exposure. The signal level of an analog signal corresponds to, for example, a voltage level.

[0086]

[0087] As shown in FIG. 4 , first, at time t1, the selection signal SELn goes high, turning on the selection transistor 24 of the pixel PX in the nth row. In other words, the pixel PX in the nth row is selected. Also at time t1, the reset signal RSTn also goes high, turning on the reset transistor 22 and starting to reset the potential of the charge storage unit FD of the pixel PX in the nth row. One of the pixels PX in the nth row is an example of a first pixel. At this time, the switch control signal S0 goes low, turning off the multiple switches 51, isolating the multiple vertical signal lines 35 from each other, and preventing the analog signals output from the pixel PX from being combined. It is sufficient for the switch control signal S0 to go low before time t3, which will be described later.

[0088] Next, at time t2, the reset signal RSTn goes low, turning off the reset transistor 22, and completing the reset of the potential of the charge storage unit FD of the pixel PX in the nth row. A reset signal Sr corresponding to the potential of the charge storage unit FD of the pixel PX in the nth row being at the reset level is output to the vertical signal line 35 from the pixel PX in the nth row.

[0089] Next, at time t3, in each column of pixels PX, the reset signal Sr output from the pixel PX in the nth row is read out to each column circuit 43 via the combining circuit 50. The combining circuit 50 outputs the reset signal Sr input to the vertical signal line 35 to the conversion circuit 47 of each column circuit 43 without combining it across the multiple vertical signal lines 35. As shown in Table 1, the signal level of the reset signal Sr output at this time is a signal level obtained by adding various noises, including fixed noise ΔVn, fixed noise ΔVth, kTC noise ΔkTC, and random noise ΔVsf(t3) at time t3 to the signal level Vrst(t2) when the potential of the pixel PX is reset to the reset voltage at time t2. The conversion circuit 47 temporarily holds the reset signal Sr.

[0090] Next, at time t4, the switch control signal S0 goes high, the switches 51 turn on the vertical signal lines 35, and the reset signals output from the pixels PX in the nth row are combined. That is, the combining circuit 50 combines the reset signals output from the pixels PX in the nth row to generate the first reference signal St1. In this embodiment, the pixel PX in the nth row includes the first pixel, is located in the same row as the first pixel, and is an example of two or more pixels included in the first group.

[0091] Next, at time t5, the first reference signal St1 is read out to each column circuit 43. The combining circuit 50 combines the reset signals output from each pixel PX in the nth row to generate the first reference signal St1, which is then output to the conversion circuit 47 of each column circuit 43. Time t5 in the example shown in FIG. 4 is an example of the first timing. As shown in Table 1, unlike the reset signal Rs, the signal level of the first reference signal St1 output at this time does not include the fixed noise ΔVth, the kTC noise ΔkTC, and the random noise ΔVsf. Because the fixed noise ΔVth, the kTC noise ΔkTC, and the random noise ΔVsf are random noises, they are essentially canceled out by the combining circuit 50 combining the reset signal. As a result, the signal level of the first reference signal St1 becomes a signal level obtained by adding substantially only the fixed noise ΔVn to the signal level Vrst(t2) obtained when the potential of the pixel PX was reset to the reset voltage at time t2. In this way, the synthesis circuit 50 can output the first reference signal St1 with reduced noise.

[0092] The conversion circuit 47 generates a first digital signal D1 based on the difference between the reset signal Sr and the first reference signal St1. The conversion circuit 47, for example, subtracts the first reference signal St1 from the temporarily stored reset signal Sr and performs AD conversion on the resulting analog signal to generate the first digital signal D1. The first digital signal D1 is a digital signal corresponding to the reset level of the pixel PX. The generated first digital signal D1 is temporarily stored in the memory 48. As shown in Table 1, in the first digital signal D1, the signal level Vrst(t2) and fixed noise ΔVn are subtracted from the reset signal Sr by the first reference signal St1, leaving components of fixed noise ΔVth, kTC noise ΔkTC, and random noise ΔVsf(t3). Therefore, the voltage level to be AD converted when generating the first digital signal D1 is lowered, thereby reducing the load during AD conversion.

[0093] Next, at time t6, the selection signal SELn goes low, turning off the selection transistors 24 of the pixels PX in the nth row. That is, the pixels PX in the nth row go into a non-selected state. Also at time t6, the switch control signal S0 goes low, isolating the multiple vertical signal lines 35 from one another.

[0094] At time t6, the selection signal SELn+1 and the reset signal RSTn+1 go high, selecting the pixels PX in the n+1th row and initiating a reset operation of the potentials of the charge storage units FD of the pixels PX in the n+1th row. Thereafter, the operations performed on the pixels PX in the nth row from time t1 to time t6 are also performed on the pixels PX in the n+1th row. In this manner, the operations for generating the first digital signal D1, as performed from time t1 to time t6, are sequentially performed on all rows of the pixels PX before exposure. After the operations for generating the first digital signal D1 are performed on the pixels PX in all rows of the pixels PX, exposure is performed, and signal charges corresponding to the exposure amount of each pixel PX are accumulated in the charge storage units FD of each pixel PX.

[0095] 4, in reading out signals from the pixels PX in the nth row after exposure, first, at time t11, the selection signal SELn goes high, turning on the selection transistors 24 of the pixels PX in the nth row. In other words, the pixels PX in the nth row are selected. The pixels PX in the nth row output pixel signals Sp to the vertical signal lines 35 in accordance with the amount of signal charge accumulated in the charge accumulation units FD by exposure. Also, at time t11, the switch control signal S0 goes low, isolating the vertical signal lines 35 from one another.

[0096] Next, at time t12, in each column of pixels PX, the pixel signal Sp output from the pixel PX in the nth row is read out to each column circuit 43 via the combining circuit 50. The combining circuit 50 outputs the pixel signal Sp input to the vertical signal line 35 to the conversion circuit 47 of each column circuit 43 without combining it across the multiple vertical signal lines 35. As shown in Table 1, the signal level of the pixel signal Sp output at this time is a signal level obtained by adding a signal level Vsig indicating the amount of signal charge accumulated in the charge accumulation unit FD during exposure to the signal level Vrst(t2) when the potential of the pixel PX is reset to the reset voltage at time t2, and further adding various noises, including fixed noise ΔVn, fixed noise ΔVth, kTC noise ΔkTC, and random noise ΔVsf(t12) at time t12. The conversion circuit 47 temporarily holds the pixel signal Sp.

[0097] Next, at time t13, the reset signal RSTn goes high, turning on the reset transistor 22 and starting to reset the potential of the charge storage unit FD of the pixel PX in the nth row. Then, at time t14, the reset signal RSTn goes low, turning off the reset transistor 22 and finishing resetting the potential of the charge storage unit FD of the pixel PX in the nth row.

[0098] 4, at time t13, the switch control signal S0 goes high, the switches 51 turn on the vertical signal lines 35, and at time t14, the reset signals output from the pixels PX in the nth row are combined. That is, the combining circuit 50 combines the reset signals output from the pixels PX in the nth row to generate the second reference signal St2 at a timing separate from the generation of the first reference signal St1. Note that the switch control signal S0 only needs to go high by time t15, which will be described later.

[0099] Next, at time t15, the second reference signal St2 is read out to each column circuit 43. The combining circuit 50 combines the reset signals output from each pixel PX in the nth row to generate the second reference signal St2, which is then output to the conversion circuit 47 of each column circuit 43. Time t15 in the example shown in FIG. 4 is an example of the second timing. As shown in Table 1, the signal level of the second reference signal St2 output at this time does not include the fixed noise ΔVth, the kTC noise ΔkTC, and the random noise ΔVsf, as with the first reference signal St1. As a result, the signal level of the second reference signal St2 becomes a signal level obtained by adding substantially only the fixed noise ΔVn to the signal level Vrst (t14) obtained when the potential of the pixel PX is reset to the reset voltage at time t14.

[0100] The conversion circuit 47 generates a second digital signal D2 based on the difference between the pixel signal Sp and the second reference signal St2. The conversion circuit 47, for example, subtracts the second reference signal St2 from the temporarily stored pixel signal Sp, performs AD conversion on the resulting analog signal, and generates the second digital signal D2. The second digital signal D2 is a digital signal corresponding to the amount of signal charge accumulated in the charge accumulation unit FD of the pixel PX. As shown in Table 1, the second digital signal D2 is obtained by subtracting the signal level Vrst (t14) and fixed noise ΔVn from the pixel signal Sp using the second reference signal St2, leaving behind the signal level Vsig, fixed noise ΔVth, kTC noise ΔkTC, and random noise ΔVsf (t12). If kTC noise ΔkTC remains in the second reference signal St2, the kTC noise ΔkTC will be generated by a reset operation with a different timing from the kTC noise ΔkTC in the pixel signal Sp, and the kTC noise ΔkTC component in the second digital signal D2 will be multiplied by √2. Therefore, because the kTC noise ΔkTC in the second reference signal St2 is canceled out by the combination of the reset signal, it is possible to suppress amplification of the kTC noise ΔkTC in the second digital signal D2.

[0101] In addition, in the second digital signal D2, a difference remains between the signal level Vrst(t2) and the signal level Vrst(t14), but since the reset voltage does not usually change over time, the difference between the signal level Vrst(t2) and the signal level Vrst(t14) is almost zero.

[0102] The processing circuit 49 generates a differential digital signal Ddif, which is the difference between the generated second digital signal D2 and the first digital signal D1 stored in the memory 48, and outputs the generated differential digital signal Ddif. The processing circuit 49 generates the differential digital signal Ddif, for example, by subtracting the first digital signal D1 temporarily stored in the memory 48 from the second digital signal D2. The differential digital signal Ddif is a digital signal that indicates the pixel value (luminance value) of the pixel PX. As shown in Table 1, in the differential digital signal Ddif, the signal levels of the fixed noise ΔVth and the kTC noise ΔkTC are subtracted and eliminated from the second digital signal D2 by the first digital signal D1. This reduces noise and improves image quality.

[0103] Furthermore, in the differential digital signal Ddif, the difference between the signal level Vrst(t2) and the signal level Vrst(t14) remains, but as described above, this is approximately 0. Furthermore, because the random noise ΔVsf(t3) and the random noise ΔVsf(t12) are random noises generated at different times, the difference between the random noise ΔVsf(t3) and the random noise ΔVsf(t12) is √2ΔVsf, and this remains in the differential digital signal Ddif.

[0104] The differential digital signal Ddif is read out by, for example, the horizontal signal readout circuit 44. The processing circuit 49 may temporarily store the generated differential digital signal Ddif in the memory .

[0105] 4 , before the differential digital signal Ddif is generated, the reset signal Sr that is read out as is, the reset signal Sr for generating the first reference signal St1, and the reset signal for generating the pixel signal Sp and the second reference signal St2 are output from the same pixel PX in a time-division manner, so that the first reference signal St1 and the second reference signal St2 can be generated with a simple configuration.

[0106] Next, at time t16, the selection signal SELn goes low, turning off the selection transistors 24 of the pixels PX in the nth row. That is, the pixels PX in the nth row go into a non-selected state. Also at time t16, the switch control signal S0 goes low, and the multiple vertical signal lines 35 are isolated from each other.

[0107] Furthermore, at time t16, the selection signal SELn+1 goes high, selecting the pixels PX in the n+1th row and starting the readout operation of the pixel signals from the pixels PX in the n+1th row. Thereafter, the operations performed on the pixels PX in the nth row from time t11 to time t16 are also performed on the pixels PX in the n+1th row. In this manner, the operations for generating the second digital signal D2 and the differential digital signal Ddif, as performed from time t11 to time t16, are sequentially performed on all rows of the pixels PX. Through these operations, the differential digital signal Ddif corresponding to each pixel PX is generated, thereby generating an image in the imaging device 100.

[0108] As described above, the imaging device 100 according to the present embodiment includes a plurality of pixels PX arranged in a plurality of rows and columns, and a combining circuit 50 to which analog signals output from the plurality of pixels PX are input. The analog signals include a reset signal representing a reset level and a pixel signal representing an image of a subject. The combining circuit 50 outputs, within one frame period, a reference signal obtained by combining the reset signal output from a pixel PX among the plurality of pixels PX, the pixel signal output from the pixel PX, and each of the reset signals output from two or more pixels PX included in a first group among the plurality of pixels PX.

[0109] As a result, the combining circuit 50 outputs a reference signal in addition to the reset signal and pixel signal, enabling AD conversion of the difference between the reset signal and the reference signal in subsequent processing. This reduces the signal level to be AD converted, improving the resolution of AD conversion, reducing the conversion process, and reducing power consumption. Furthermore, because the combining circuit 50 outputs a reference signal obtained by combining reset signals output from two or more pixels PX, random noise in the reset signals is canceled out by the combination, resulting in a noise-reduced reference signal being output. Therefore, the noise-reduced reference signal can be used to obtain the difference between the reset signal and the pixel signal, and noise in the difference can also be reduced. From the above, the imaging device 100 according to this embodiment enables improved image quality.

[0110] [Modification 1] Next, a description will be given of Modification 1 of Embodiment 1. The following description will focus on the differences from Embodiment 1, and the description of the commonalities will be omitted or simplified.

[0111] FIG. 5 is a schematic diagram showing an exemplary circuit configuration of an imaging device 110 according to this modification. For ease of viewing, FIG. 5 focuses on the pixels PX and the composite circuit 50A, and does not include the reset voltage line 31 shown in FIG. 2. The circuit configuration of the imaging device 110 may include wiring, circuits, and the like not shown in FIG. 5. Also, FIG. 5 does not illustrate the circuit configuration within the pixels PX. Of the multiple pixels PX, FIG. 5 illustrates three columns of pixels PXn-1 to PXn+1, which are pixels PX in the n-1th to n+1th rows. For columns other than the illustrated columns, the circuit configuration corresponding to the illustrated columns is repeated.

[0112] As shown in FIG. 5, the imaging device 110 of this modified example differs from the imaging device 100 of embodiment 1 mainly in that it includes a synthesis circuit 50A instead of the synthesis circuit 50, and further includes a selector 45.

[0113] The combining circuit 50A includes a plurality of vertical signal lines 35a, a plurality of vertical signal lines 35b, a plurality of switches 51a, and a plurality of switches 51b. The vertical signal lines 35a and 35b are examples of output signal lines.

[0114] As shown in FIG. 5 , vertical signal lines 35a and 35b are provided corresponding to each column of the pixels PX. The columns of the pixels PX and the vertical signal line 35a correspond, for example, one-to-one. Similarly, the columns of the pixels PX and the vertical signal line 35b correspond, for example, one-to-one. Each vertical signal line 35a provided corresponding to each column of the pixels PX is connected to pixels PX in one of the odd-numbered and even-numbered rows of the corresponding column. Each vertical signal line 35b provided corresponding to each column of the pixels PX is connected to pixels PX in the other of the odd-numbered and even-numbered rows of the corresponding column. Therefore, pixels PX in adjacent rows are connected to different vertical signal lines.

[0115] Each of the switches 51a is connected between two vertical signal lines 35a corresponding to different columns of the pixels PX. In the example shown in Fig. 5, each of the switches 51a is connected between two vertical signal lines 35a corresponding to two adjacent columns.

[0116] Each of the switches 51b is connected between two vertical signal lines 35b corresponding to different columns of the pixels PX. In the example shown in Fig. 5, each of the switches 51b is connected between two vertical signal lines 35b corresponding to two adjacent columns.

[0117] The switches 51 a and 51 b are, for example, FETs formed on the semiconductor substrate 60, and their operations are controlled by switch control signals S1 and S2 applied to their gates. The switch control signals S1 and S2 are supplied from, for example, the control circuit 46. At least one of the multiple switches 51 a and the multiple switches 51 b may be formed on a semiconductor substrate other than the semiconductor substrate 60, and the other semiconductor substrate may be stacked on the semiconductor substrate 60.

[0118] The switches 51a electrically connect the vertical signal lines 35a corresponding to different columns of pixels PX to each other. Therefore, the number of the switches 51a may be one less than the number of the vertical signal lines 35a electrically connected to each other. When the number of the vertical signal lines 35a electrically connected to each other is two, the number of the switches 51a may be one. Alternatively, the number of the switches 51a may be the same as the number of the vertical signal lines 35a electrically connected to each other.

[0119] When the switch control signal S1 is at a high level, the switch 51a is turned on, thereby mutually connecting (short-circuiting) the multiple vertical signal lines 35a connected to the multiple switches 51a. This allows analog signals output from the pixels PX to be combined onto the multiple vertical signal lines 35a connected to the multiple switches 51a. Furthermore, when the switch control signal S1 is at a low level, the multiple switches 51a are turned off, thereby isolating the multiple vertical signal lines 35a connected to the multiple switches 51a. This allows the combining circuit 50A to control whether or not to combine the analog signals output from the pixels PX onto the multiple vertical signal lines 35a connected to the multiple switches 51a. For example, the same switch control signal S1 is supplied to each of the multiple switches 51a, and the same control is performed.

[0120] The switches 51b electrically connect the vertical signal lines 35b corresponding to different columns of pixels PX to each other. Therefore, the number of switches 51b may be one less than the number of electrically connected vertical signal lines 35b. When the number of electrically connected vertical signal lines 35b is two, the number of switches 51b may be one. Alternatively, the number of switches 51b may be the same as the number of electrically connected vertical signal lines 35b.

[0121] When the switch control signal S2 is at a high level, the switch 51b is turned on, thereby mutually connecting (short-circuiting) the multiple vertical signal lines 35b connected to the multiple switches 51b. This allows analog signals output from the pixels PX to be combined onto the multiple vertical signal lines 35b connected to the multiple switches 51b. Furthermore, when the switch control signal S2 is at a low level, the multiple switches 51b are turned off, thereby isolating the multiple vertical signal lines 35b connected to the multiple switches 51b. This allows the combining circuit 50A to control whether or not to combine the analog signals output from the pixels PX onto the multiple vertical signal lines 35b connected to the multiple switches 51b. For example, the same switch control signal S2 is supplied to each of the multiple switches 51b, and the same control is performed.

[0122] The number of the vertical signal lines 35a and 35b electrically connected to each other by the switches 51a and 51b is, for example, 10 or more. The vertical signal lines 35a and 35b electrically connected to each other by the switches 51a and 51b correspond to the same column of pixels PX. That is, the analog signals output from the pixels PX are combined by the switches 51a and 51b to the same column of pixels PX. For example, all the vertical signal lines 35a and 35b corresponding to all the columns of pixels PX are electrically connected to each other by the switches 51a and 51b. When the columns of pixels PX are divided into two or more blocks, the vertical signal lines 35a and 35b corresponding to the columns of the blocks may be electrically connected to each other by the switches 51a and 51b, respectively.

[0123] In this modification, the current sources 39 are provided corresponding to each of the plurality of vertical signal lines 35 a and the plurality of vertical signal lines 35 b. That is, two current sources 39 are provided corresponding to each column of the plurality of pixels PX.

[0124] A column circuit 43 is provided corresponding to each column of the pixels PX. The column circuit 43 and the vertical signal lines 35 a and 35 b are connected via a selector 45. Analog signals output from the pixels PX and input to the vertical signal lines 35 a and 35 b are input to the column circuit 43 via the selector 45.

[0125] The selector 45 receives analog signals output from the pixels PX and input to the vertical signal lines 35a and 35b. The selector 45 selects which of the vertical signal lines 35a and 35b the analog signal input to should be output to the column circuit 43. The selector 45 is configured with one or more switches that switch between connecting the vertical signal line 35a to the column circuit 43 and disconnecting the vertical signal line 35b from the column circuit 43, or connecting the vertical signal line 35b to the column circuit 43 and disconnecting the vertical signal line 35a from the column circuit 43. The operation of the selector 45 is controlled by, for example, a control circuit 46. Note that the connection and disconnection of the vertical signal lines 35a and 35b from the column circuit 43 may be controlled by two switches connected between the vertical signal lines 35a and 35b, respectively, and the column circuit 43, instead of the selector 45.

[0126] Next, a description will be given of the operation (driving method) of the imaging device 110 according to this modified example. The circuits of the pixels PX are driven under the control of the control circuit 46.

[0127] 6 is a timing chart for explaining an example of the operation of the imaging device 110 according to this modification, which shows the voltage levels of the selection signals SEL and reset signals RST of the (n-1)th to (n+1)th rows of the pixels PX, as well as the switch control signals S1 and S2, during one frame period for generating one image.

[0128] As shown in FIG. 6 , first, at time t1, the selection signal SELn goes high, turning on the selection transistor 24 of the pixel PX in the nth row. Also at time t1, the reset signal RSTn also goes high, turning on the reset transistor 22 and starting to reset the potential of the charge storage unit FD of the pixel PX in the nth row. One of the pixels PX in the nth row is an example of a first pixel. At this time, the switch control signal S1 goes low, turning off the multiple switches 51a, isolating the multiple vertical signal lines 35a from each other, and the analog signals output from the pixel PX in the nth row are not combined.

[0129] Furthermore, prior to time t1, the reset operation is completed for the pixels PX in the n-1th row, and the potentials of the pixels PX in the n-1th row are reset to the reset voltage. Then, at time t1, the switch control signal S2 goes high, the switches 51b turn on the vertical signal lines 35b, and the reset signals output from the pixels PX in the n-1th row are combined. In other words, the combining circuit 50A combines the reset signals output from the pixels PX in the n-1th row to generate the first reference signal. In this modification, the pixel PX in the n-1th row is located in a different row from the first pixel and is an example of two or more pixels included in the first group.

[0130] Next, at time t2, the reset signal RSTn goes low, the reset transistor 22 is turned off, and the reset of the potential of the charge storage unit FD of the pixel PX in the nth row is completed. The reset signal is output from the pixel PX in the nth row to the vertical signal line 35a.

[0131] Next, at time t3, in each column of pixels PX, the reset signal output from the pixel PX in the nth row is read out to each column circuit 43 via the combining circuit 50A. The combining circuit 50A outputs the reset signal input to the vertical signal line 35a to the conversion circuit 47 of each column circuit 43 without combining it across multiple vertical signal lines 35a. The conversion circuit 47 temporarily holds the reset signal. Also, at time t3, the selector 45 inputs the reset signal input to the vertical signal line 35a to the column circuit 43. For example, from time t1 until the readout operation of the reset signal from the pixel PX in the nth row is completed, the selector 45 connects the vertical signal line 35a to the column circuit 43 and disconnects the vertical signal line 35b from the column circuit 43.

[0132] Next, at time t4, a first reference signal is read out to each column circuit 43 via the vertical signal line 35b. The combining circuit 50A combines the reset signals output from each pixel PX in the (n-1)th row and outputs the combined first reference signal to the conversion circuit 47 of each column circuit 43. Time t4 in the example shown in FIG. 6 is an example of the first timing. The conversion circuit 47 generates a first digital signal for the pixel PX in the nth row based on the difference between the reset signal and the first reference signal. For example, the conversion circuit 47 subtracts the first reference signal from the temporarily held reset signal, performs AD conversion on the resulting analog signal, and generates a first digital signal for the pixel PX in the nth row. Also, at time t4, the selector 45 inputs the first reference signal combined with the reset signal input to the vertical signal line 35b to the column circuit 43. For example, the selector 45 connects the vertical signal line 35b to the column circuit 43 and disconnects the vertical signal line 35a from the column circuit 43 during the period from time t4 until the readout operation of the first reference signal is completed.

[0133] Next, at time t5, the selection signal SELn+1 goes high, turning on the selection transistors 24 of the pixels PX in the (n+1)th row. Also at time t5, the reset signal RSTn+1 also goes high, turning on the reset transistors 22 and starting to reset the potentials of the charge storage units FD of the pixels PX in the (n+1)th row. At this time, the switch control signal S2 goes low, turning off the switches 51b, isolating the vertical signal lines 35b from one another, and the analog signals output from the pixels PX in the (n+1)th row are not combined.

[0134] At time t5, the switch control signal S1 goes high, the switches 51a turn on the vertical signal lines 35a, and the reset signals output from the pixels PX in the n-th row are combined. That is, the combining circuit 50A combines the reset signals output from the pixels PX in the n-th row to generate the first reference signal.

[0135] Next, at time t6, the reset signal RSTn+1 goes low, turning off the reset transistor 22, and completing the reset of the potential of the charge storage unit FD of the pixel PX in the (n+1)th row. The reset signal is output from the pixel PX in the (n+1)th row to the vertical signal line 35b.

[0136] Next, at time t7, in each column of pixels PX, the reset signal output from the pixel PX in the (n+1)th row is read out to each column circuit 43 via the combining circuit 50A. The combining circuit 50A outputs the reset signal input to the vertical signal line 35b to the conversion circuit 47 of each column circuit 43 without combining it across multiple vertical signal lines 35b. The conversion circuit 47 temporarily holds the reset signal. Also, at time t7, the selector 45 inputs the reset signal input to the vertical signal line 35b to the column circuit 43. For example, from time t5 until the readout operation of the reset signal from the pixel PX in the (n+1)th row is completed, the selector 45 connects the vertical signal line 35b to the column circuit 43 and disconnects the vertical signal line 35a from the column circuit 43.

[0137] Next, at time t8, the first reference signal is read out to each column circuit 43 via the vertical signal line 35a. The combining circuit 50A combines the reset signals output from each pixel PX in the nth row and outputs the combined first reference signal to the conversion circuit 47 of each column circuit 43. The conversion circuit 47 generates a first digital signal for the pixel PX in the (n+1)th row based on the difference between the reset signal and the first reference signal. For example, the conversion circuit 47 subtracts the first reference signal from a temporarily stored reset signal, performs AD conversion on the resulting analog signal, and generates a first digital signal for the pixel PX in the (n+1)th row. Also, at time t8, the selector 45 inputs the first reference signal combined with the reset signal input to the vertical signal line 35a to the column circuit 43. For example, from time t8 until the readout operation of the first reference signal is completed, the selector 45 connects the vertical signal line 35a to the column circuit 43 and disconnects the vertical signal line 35b from the column circuit 43.

[0138] Next, at time t9, the switch control signal S2 goes high, the switches 51b turn on the vertical signal lines 35b, and the reset signals output from the pixels PX in the (n+1)th row are combined. Also at time t9, the switch control signal S1 goes low, and the switches 51a turn off, isolating the vertical signal lines 35a from each other.

[0139] In this way, the operation for generating the first digital signal, as performed from time t1 to time t9, is performed sequentially for every two rows of the pixels PX before exposure. After the operation for generating the first digital signal has been performed for the pixels PX in every row of the pixels PX, exposure is performed, and signal charge corresponding to the exposure amount of each pixel PX is accumulated in the charge storage unit FD of each pixel PX.

[0140] 6, in reading out signals from the pixels PX in the nth row after exposure, first, at time t11, the selection signal SELn goes high, turning on the selection transistors 24 of the pixels PX in the nth row. Also, at time t11, the switch control signal S1 goes low, insulating the multiple vertical signal lines 35a from one another. Pixel signals output from the pixels PX in the nth row in accordance with the amount of signal charge accumulated in the charge accumulation unit FD by exposure are output to the vertical signal line 35a.

[0141] Furthermore, prior to time t11, in the pixels PX in the (n-1)th row, the selection signal SELn-1 goes high, and the pixel signal readout operation is completed. Then, at time t11, the reset signal RSTn-1 goes high, turning on the reset transistor 22 and starting to reset the potential of the charge storage unit FD of the pixels PX in the (n-1)th row. Then, at time t12, the reset signal RSTn goes low, turning off the reset transistor 22 and completing the reset of the potential of the charge storage unit FD of the pixels PX in the (n-1)th row.

[0142] 6, at time t11, the switch control signal S2 goes high, causing the switches 51b to turn on the vertical signal lines 35b, and at time t12, the reset signals output from the pixels PX in the (n-1)th row are combined. That is, the combining circuit 50A combines the reset signals output from the pixels PX in the (n-1)th row to generate the second reference signal at a timing separate from the timing at which the first reference signal is generated. In this way, in the example shown in FIG. 6, the second reference signal can be generated without resetting the pixels PX in the nth row after exposure, thereby enabling faster operation.

[0143] Next, at time t13, in each column of pixels PX, pixel signals output from pixels PX in the nth row are read out to each column circuit 43 via the combining circuit 50A. The combining circuit 50A outputs the pixel signals input to the vertical signal lines 35a to the conversion circuit 47 of each column circuit 43 without combining them across multiple vertical signal lines 35a. The conversion circuit 47 temporarily holds the pixel signals. Also, at time t13, the selector 45 inputs the pixel signals input to the vertical signal lines 35a to the column circuit 43. For example, from time t11 until the readout operation of the pixel signals from pixels PX in the nth row is completed, the selector 45 connects the vertical signal line 35a to the column circuit 43 and disconnects the vertical signal line 35b from the column circuit 43.

[0144] Next, at time t14, a second reference signal is read out to each column circuit 43 via the vertical signal line 35b. The combining circuit 50A combines the reset signals output from each pixel PX in the (n-1)th row, and outputs the combined second reference signal to the conversion circuit 47 of each column circuit 43. Time t14 in the example shown in FIG. 6 is an example of the second timing. The conversion circuit 47 generates a second digital signal for the pixel PX in the nth row based on the difference between the pixel signal and the second reference signal. The conversion circuit 47, for example, subtracts the second reference signal from the pixel signal temporarily held, performs AD conversion on the analog signal after the subtraction, and generates a second digital signal for the pixel PX in the nth row.

[0145] The processing circuit 49 generates a differential digital signal for the pixel PX in the nth row, which is the difference between the generated second digital signal for the pixel PX in the nth row and the first digital signal for the pixel PX in the nth row stored in the memory 48, and outputs the generated differential digital signal.

[0146] Furthermore, at time t14, the selector 45 inputs a second reference signal obtained by combining the reset signal input to the vertical signal line 35b to the column circuit 43. For example, from time t14 until the readout operation of the second reference signal is completed, the selector 45 connects the vertical signal line 35b to the column circuit 43 and disconnects the vertical signal line 35a from the column circuit 43.

[0147] Next, at time t15, the selection signal SELn+1 goes high, turning on the selection transistors 24 of the pixels PX in the (n+1)th row. At this time, the switch control signal S2 goes low, turning off the switches 51b and isolating the vertical signal lines 35b from one another. The vertical signal lines 35b receive pixel signals output from the pixels PX in the (n+1)th row in accordance with the amount of signal charge accumulated in the charge accumulation units FD by exposure.

[0148] At time t15, the reset signal RSTn goes high, turning on the reset transistor 22 and starting to reset the potential of the charge storage unit FD of the pixel PX in the nth row. Then, at time t16, the reset signal RSTn goes low, turning off the reset transistor 22 and finishing resetting the potential of the charge storage unit FD of the pixel PX in the nth row.

[0149] 6, at time t15, the switch control signal S1 goes high, the switches 51a turn on the vertical signal lines 35a, and the reset signals output from the pixels PX in the n-th row are combined at time t16. That is, the combining circuit 50A combines the reset signals output from the pixels PX in the n-th row to generate the second reference signal at a timing separate from the generation of the first reference signal.

[0150] Next, at time t17, in each column of pixels PX, pixel signals output from pixels PX in the (n+1)th row are read out to each column circuit 43 via the combining circuit 50A. The combining circuit 50A outputs the pixel signals input to the vertical signal lines 35b to the conversion circuit 47 of each column circuit 43 without combining them across multiple vertical signal lines 35b. The conversion circuit 47 temporarily holds the pixel signals. Also, at time t17, the selector 45 inputs the pixel signals input to the vertical signal lines 35b to the column circuit 43. For example, from time t15 until the readout operation of the pixel signals from pixels PX in the (n+1)th row is completed, the selector 45 connects the vertical signal line 35b to the column circuit 43 and disconnects the vertical signal line 35a from the column circuit 43.

[0151] Next, at time t18, the second reference signal is read out to each column circuit 43 via the vertical signal line 35a. The combining circuit 50A combines the reset signals output from each pixel PX in the nth row and outputs the second reference signal to the conversion circuit 47 of each column circuit 43. The conversion circuit 47 generates a second digital signal for the pixel PX in the (n+1)th row based on the difference between the pixel signal and the second reference signal. The conversion circuit 47, for example, subtracts the second reference signal from the temporarily held pixel signal, performs AD conversion on the analog signal after the subtraction, and generates the second digital signal for the pixel PX in the (n+1)th row.

[0152] The processing circuit 49 generates a differential digital signal of the pixel PX in the n+1th row, which is the difference between the generated second digital signal of the pixel PX in the n+1th row and the first digital signal of the pixel PX in the n+1th row stored in the memory 48, and outputs the generated differential digital signal.

[0153] Furthermore, at time t18, the selector 45 inputs a second reference signal obtained by combining the reset signal input to the vertical signal line 35a to the column circuit 43. For example, from time t18 until the readout operation of the second reference signal is completed, the selector 45 connects the vertical signal line 35a to the column circuit 43 and disconnects the vertical signal line 35b from the column circuit 43.

[0154] Next, at time t19, the switch control signal S2 goes high, causing the switches 51b to turn on the vertical signal lines 35b. Also at time t19, the reset signal RSTn+1 goes high, turning on the reset transistors 22 and starting to reset the potentials of the charge storage units FD of the pixels PX in the (n+1)th row. Also at time t19, the switch control signal S1 goes low, causing the switches 51a to turn off, thereby isolating the vertical signal lines 35a from each other.

[0155] In this way, the operation for generating the second digital signal and the differential digital signal, as performed from time t11 to time t19, is performed sequentially for every two rows of the plurality of pixels PX before exposure. Through this operation, a differential digital signal corresponding to each pixel PX is generated, and an image is generated in the imaging device 110.

[0156] 6, the first reference signal is read out after the reset signal to generate the first digital signal, and the second reference signal is read out after the pixel signal to generate the second digital signal, but the order of reading these signals may be reversed. That is, the reset signal may be read out after the first reference signal to generate the first digital signal, and the pixel signal may be read out after the second reference signal to generate the second digital signal.

[0157] Furthermore, as long as the above-described signal generation operation is possible, the circuit configuration of the imaging device 110 is not limited to the example shown in FIG. 5 . For example, although the imaging device 110 includes the selector 45, the imaging device 110 does not need to include the selector 45 as long as the on / off of the selection transistor 24 of each pixel PX is controlled so that an analog signal output from one of the pixels PX in the same column is output to the column circuit 43. In this case, the vertical signal line 35 a and the vertical signal line 35 b are connected to each other in a stage preceding the column circuit 43, and both the vertical signal line 35 a and the vertical signal line 35 b are always connected to the column circuit 43. In this case, the vertical signal line 35 a and the vertical signal line 35 b may be connected to a single current source 39.

[0158] [Modification 2] Next, a description will be given of Modification 2 of Embodiment 1. The following description will focus on the differences between Embodiment 1 and Modification 1 of Embodiment 1, and description of commonalities will be omitted or simplified.

[0159] FIG. 7 is a schematic diagram illustrating an exemplary circuit configuration of an imaging device 120 according to this modification. For clarity, FIG. 7 focuses on the pixel PX, the OB (Optical Black) pixel PXB, and the compositing circuit 50B, and does not include the reset voltage line 31 shown in FIG. 2 . The circuit configuration of the imaging device 120 may include wiring and circuits not shown in FIG. 7 . Also, FIG. 7 does not illustrate the circuit configurations within the pixel PX and the OB pixel PXB. Of the multiple pixels included in the imaging device, FIG. 7 illustrates three columns of pixel PXn, which is the pixel PX in the nth row, and OB pixel PXB. For columns other than the illustrated columns, the circuit configuration corresponding to the illustrated columns is repeated.

[0160] As shown in Figure 7, the imaging device 120 of this modified example differs from the imaging device 100 of embodiment 1 mainly in that it has a synthesis circuit 50B instead of the synthesis circuit 50, and that it also has multiple OB pixels PXB.

[0161] The multiple pixels included in the imaging device 120 include multiple OB pixels PXB in addition to multiple pixels PX. The pixels PX and OB pixels PXB have, for example, the same circuit configuration, and the OB pixels PXB include a light-shielding layer on the light incident side of the photoelectric conversion unit 12, which is not included in the pixel PX. That is, the OB pixels PXB include a light-shielding layer in addition to the photoelectric conversion unit 12, reset transistor 22, amplification transistor 23, selection transistor 24, and charge storage unit FD shown in FIG. 2 . Therefore, the OB pixels PXB are invalid pixels that do not generate signal charge even when receiving incident light, and the signal level of the analog signal they output does not change in response to the incident light. Note that the multiple pixels included in the imaging device 120 may also include invalid pixels that do not include a light-shielding layer instead of the OB pixels PXB. For example, the invalid pixels may be pixels in which the photoelectric conversion unit 12 and the charge storage unit FD are insulated from each other, or pixels that do not include the photoelectric conversion unit 12.

[0162] For example, in a plan view, the OB pixel PXB is arranged additionally to a column of multiple pixels PX. That is, the OB pixel PXB is arranged at the end of a column in which the pixel PX and the OB pixel PXB are arranged. The OB pixels PXB are arranged in the row direction, and a row of the OB pixels PXB constitutes an end row of the rows of multiple pixels included in the imaging device 120. At least one OB pixel PXB is provided corresponding to each column of the multiple pixels PX. That is, the multiple pixels included in the imaging device 120 include at least one row of OB pixels PXB. When the multiple pixels include two or more rows of OB pixels PXB, the rows of OB pixels PXB may be arranged together at one end of the row of multiple pixels, or may be arranged at both ends of the row of multiple pixels so as to sandwich the multiple pixels PX.

[0163] The combining circuit 50B includes a plurality of vertical signal lines 35, a plurality of vertical signal lines 35c, and a plurality of switches 51c. The vertical signal lines 35 and 35c are examples of output signal lines. The combining circuit 50B does not include a plurality of switches 51 that electrically connect the plurality of vertical signal lines 35 to each other, as provided in the combining circuit 50 described above, but may include such switches. In this case, the image pickup device 120 can also perform the same operation as the image pickup device 100.

[0164] 7, a vertical signal line 35c is provided corresponding to each column of the pixels PX. The columns of the pixels PX correspond, for example, to the vertical signal line 35c in a one-to-one relationship. The OB pixels PXB located in the corresponding column are connected to each vertical signal line 35c provided corresponding to each column of the pixels PX. Therefore, the vertical signal lines connected to the pixels PX and the OB pixels PXB are different.

[0165] Each of the switches 51c is connected between two vertical signal lines 35c corresponding to different columns of the pixels PX. In the example shown in Fig. 7, each of the switches 51c is connected between two vertical signal lines 35c corresponding to two adjacent columns.

[0166] The switch 51c is, for example, an FET formed on the semiconductor substrate 60, and its operation is controlled by a switch control signal S3 applied to its gate. The switch control signal S3 is supplied from, for example, the control circuit 46. The multiple switches 51c may be formed on a semiconductor substrate other than the semiconductor substrate 60, and the other semiconductor substrate may be stacked on the semiconductor substrate 60.

[0167] The switches 51c electrically connect the vertical signal lines 35c corresponding to different columns of pixels PX to each other. Therefore, the number of the switches 51c may be one less than the number of the vertical signal lines 35c electrically connected. When the number of the vertical signal lines 35c electrically connected is two, the number of the switches 51c may be one. Alternatively, the number of the switches 51c may be the same as the number of the vertical signal lines 35c electrically connected.

[0168] When the switch control signal S3 is at a high level, the switch 51c is turned on, thereby mutually connecting (short-circuiting) the vertical signal lines 35c connected to the switches 51c. This allows the analog signals output from the OB pixels PXB to be combined with the vertical signal lines 35c connected to the switches 51c. Furthermore, when the switch control signal S3 is at a low level, the switches 51c are turned off, thereby isolating the vertical signal lines 35c connected to the switches 51c. This allows the combining circuit 50B to control whether or not to combine the analog signals output from the OB pixels PXB with the vertical signal lines 35c connected to the switches 51c. For example, the same switch control signal S3 is supplied to each of the switches 51c, and the same control is performed.

[0169] The number of the vertical signal lines 35c electrically connected to each other by the switches 51c is, for example, 10 or more. For example, all of the vertical signal lines 35c corresponding to all of the columns of the pixels PX are electrically connected to each other by the switches 51c. Note that when the columns of the pixels PX are divided into two or more blocks, the vertical signal lines 35c corresponding to the columns of the blocks may be electrically connected to each other by the switches 51c for each of the two or more blocks.

[0170] In this modification, a current source 39 is provided corresponding to each of the plurality of vertical signal lines 35 and the plurality of vertical signal lines 35c. That is, two current sources 39 are provided corresponding to each column of the plurality of pixels PX. Note that the vertical signal lines 35 and the vertical signal lines 35c may be connected to one current source 39.

[0171] Furthermore, a column circuit 43 is provided corresponding to each column of the multiple pixels PX. The vertical signal line 35 and the vertical signal line 35c are connected to each other upstream of the column circuit 43, and both the vertical signal line 35 and the vertical signal line 35c are always connected to the column circuit 43. Note that, as in the following operation example, when the pixel PX and the OB pixel PXB are exclusively selected by the selection transistor 24, the vertical signal line 35c may not be provided, and the pixel PX and the OB pixel PXB may be connected to the column circuit 43 via the vertical signal line 35. Alternatively, the vertical signal line 35 and the vertical signal line 35c may not be connected to each other, but may be connected to the column circuit 43 via a selector 45 or a switch that controls which of the vertical signal lines 35 and 35c an analog signal input to is output to the column circuit 43, as in the image pickup device 110 according to Modification 1 of Embodiment 1. Furthermore, if the image pickup device 120 is provided with the selector 45 or a switch, the synthesis circuit 50B may include wiring that interconnects the vertical signal lines 35c, instead of the switches 51c.

[0172] Next, a description will be given of the operation (driving method) of the imaging device 120 according to this modified example. The circuits of the pixels PX and the OB pixels PXB are driven under the control of the control circuit 46.

[0173] 8 is a timing chart for explaining an example of the operation of the imaging device 120 according to this modification, which shows the voltage levels of the selection signals SEL and reset signals RST of the nth and (n+1)th rows of the pixels PX, the selection signal SELob and the reset signal RSTob that are the selection signals SEL and reset signals RST supplied to the OB pixels PXB, and the switch control signal S3 during one frame period for generating one image.

[0174] As shown in FIG. 8 , first, at time t1, the selection signal SELn goes high, turning on the selection transistor 24 of the pixel PX in the nth row. In other words, the pixel PX in the nth row is selected. Also at time t1, the reset signal RSTn also goes high, turning on the reset transistor 22 and starting to reset the potential of the charge storage unit FD of the pixel PX in the nth row. One of the pixels PX in the nth row is an example of a first pixel. Also at time t1, the selection signal SELob goes low, turning off the selection transistors 24 of the multiple OB pixels PXB. At this time, the switch control signal S3 goes low, turning off the multiple switches 51c, thereby isolating the multiple vertical signal lines 35c from each other. The multiple vertical signal lines 35 connected to the multiple vertical signal lines 35c are also isolated from each other.

[0175] Next, at time t2, the reset signal RSTn goes low, turning off the reset transistor 22, and completing the reset of the potential of the charge storage unit FD of the pixel PX in the nth row. A reset signal corresponding to the potential of the charge storage unit FD of the pixel PX in the nth row being at the reset level is output to the vertical signal line 35 from the pixel PX in the nth row.

[0176] At time t2, the reset signal RSTob goes high, turning on the reset transistor 22 and starting to reset the potentials of the charge storage units FD of the multiple OB pixels PXB. At time t3, the reset signal RSTob goes low, turning off the reset transistor 22 and completing the reset of the potentials of the charge storage units FD of the multiple OB pixels PXB. Note that the reset of the potentials of the charge storage units FD of the multiple OB pixels PXB before exposure may be performed at a timing different from the example shown in FIG. 8 , as long as it is performed by time t6, which will be described later.

[0177] Next, at time t4, in each column of pixels PX, the reset signal output from the pixel PX in the nth row is read out to each column circuit 43 via the synthesis circuit 50B. The synthesis circuit 50B outputs the reset signal input to the vertical signal line 35 to the conversion circuit 47 of each column circuit 43. The conversion circuit 47 temporarily holds the reset signal.

[0178] Next, at time t5, the selection signal SELn goes low, turning off the selection transistors 24 of the pixels PX in the nth row, that is, the pixels PX in the nth row go into a non-selected state.

[0179] Also, at time t5, the selection signal SELob goes high, turning on the selection transistors 24 of the OB pixels PXB whose charge storage sections FD have already been reset to the reset voltage. At this time, the switch control signal S3 also goes high, causing the switches 51c to turn on the vertical signal lines 35c, thereby combining the reset signals output from the OB pixels PXB. That is, the combining circuit 50B combines the reset signals output from the OB pixels PXB to generate a first reference signal. In this modification, the OB pixels PXB are located in a different row from the first pixel and are an example of two or more pixels included in the first group. Note that if the imaging device 120 includes a selector 45 or a switch for controlling which of the vertical signal lines 35 and 35c the analog signal input to should be output to the column circuit 43, the selection signal SELob may go high before time t5, at which the selection signal SELn goes low.

[0180] Next, at time t6, a first reference signal is read out to each column circuit 43. The combining circuit 50B combines the reset signals output from the multiple OB pixels PXB to output a first reference signal to the conversion circuit 47 of each column circuit 43. Time t6 in the example shown in FIG. 8 is an example of the first timing. The conversion circuit 47 generates a first digital signal based on the difference between the reset signal and the first reference signal. The conversion circuit 47, for example, subtracts the first reference signal from a temporarily held reset signal, performs AD conversion on the analog signal after the subtraction, and generates the first digital signal.

[0181] Next, at time t7, the selection signal SELob goes low, turning off the selection transistors 24 of the OB pixels PXB. Also at time t7, the switch control signal S3 goes low, and the vertical signal lines 35c are isolated from each other.

[0182] Furthermore, at time t7, the selection signal SELn+1 and the reset signal RSTn+1 go high, selecting the pixels PX in the n+1th row and initiating a reset operation of the potentials of the charge storage units FD of the pixels PX in the n+1th row. Thereafter, the operations performed on the pixels PX in the nth row from time t1 to time t7 are also performed on the pixels PX in the n+1th row. Furthermore, the operations performed on the OB pixels PXB from time t1 to time t7 are repeated for the OB pixels PXB. In this manner, the operations for generating the first digital signals, as performed from time t1 to time t7, are sequentially performed on the pixels PX in all rows of the pixels PX before exposure. After the operations for generating the first digital signals are performed on all rows of the pixels PX, exposure is performed, and signal charges corresponding to the exposure amount of each pixel PX are accumulated in the charge storage units FD of each pixel PX.

[0183] As shown in FIG. 8 , when reading out signals from the pixels PX in the nth row after exposure, first, at time t11, the selection signal SELn goes high, turning on the selection transistors 24 of the pixels PX in the nth row. In other words, the pixels PX in the nth row are selected. The pixels PX in the nth row output pixel signals to the vertical signal lines 35 in accordance with the amount of signal charge accumulated in the charge storage units FD by exposure. Also, at time t11, the switch control signal S3 goes low, isolating the vertical signal lines 35c from one another. The vertical signal lines 35 connected to the vertical signal lines 35c are also isolated from one another.

[0184] Next, at time t12, the reset signal RSTob goes high, turning on the reset transistor 22 and starting to reset the potentials of the charge storage units FD of the multiple OB pixels PXB. Then, at time t13, the reset signal RSTob goes low, turning off the reset transistor 22 and completing the resetting of the potentials of the charge storage units FD of the multiple OB pixels PXB. Note that the resetting of the potentials of the charge storage units FD of the multiple OB pixels PXB after exposure may be performed at a timing different from the example shown in FIG. 8 , as long as it is performed by time t16, which will be described later.

[0185] Next, at time t14, in each column of pixels PX, pixel signals output from pixels PX in the nth row are read out to each column circuit 43 via the synthesis circuit 50B. The synthesis circuit 50B outputs the pixel signals input to the vertical signal lines 35 to the conversion circuits 47 of each column circuit 43. The conversion circuits 47 temporarily hold the pixel signals.

[0186] Next, at time t15, the selection signal SELn goes low, turning off the selection transistors 24 of the pixels PX in the nth row, that is, the pixels PX in the nth row go into a non-selected state.

[0187] Also, at time t15, the selection signal SELob goes high, turning on the selection transistors 24 of the multiple OB pixels PXB whose charge storage sections FD have already been reset to the reset voltage. At this time, the switch control signal S3 also goes high, causing the multiple switches 51c to turn on the multiple vertical signal lines 35c, thereby combining the reset signals output from the multiple OB pixels PXB. That is, the combining circuit 50B generates the second reference signal by combining the reset signals output from the multiple OB pixels PXB at a timing separate from the generation of the first reference signal. In this way, in the example shown in FIG. 8 , the second reference signal can be generated without resetting the multiple pixels PX, enabling non-destructive readout of pixel signals from the pixels PX. This also enables faster operation. Furthermore, because the OB pixels PXB output the reset signal for generating the second reference signal, the second reference signal can be generated even during exposure. Therefore, the image capture device 120 can read pixel signals even during exposure. In addition, if the imaging device 120 is equipped with a selector 45 or a switch for controlling which of the vertical signal lines 35 and 35c the analog signal input to is output to the column circuit 43, the selection signal SELob may become high level before time t15 when the selection signal SELn becomes low level.

[0188] Next, at time t16, a second reference signal is read out to each column circuit 43. The combining circuit 50B combines the reset signals output from the multiple OB pixels PXB to output a second reference signal to the conversion circuit 47 of each column circuit 43. Time t16 in the example shown in FIG. 8 is an example of the second timing. The conversion circuit 47 generates a second digital signal based on the difference between the pixel signal and the second reference signal. The conversion circuit 47, for example, subtracts the second reference signal from the temporarily stored pixel signal, performs AD conversion on the analog signal after the subtraction, and generates the second digital signal.

[0189] The processing circuit 49 generates a differential digital signal that is the difference between the generated second digital signal and the first digital signal held in the memory 48, and outputs the generated differential digital signal.

[0190] Next, at time t17, the selection signal SELob goes low, turning off the selection transistors 24 of the OB pixels PXB. Also at time t17, the switch control signal S3 goes low, and the vertical signal lines 35c are isolated from each other.

[0191] Furthermore, at time t17, the selection signal SELn+1 goes high, selecting the pixels PX in the n+1th row and starting the readout operation of the pixel signals from the pixels PX in the n+1th row. Thereafter, the operations performed on the pixels PX in the nth row from time t11 to time t17 are also performed on the pixels PX in the n+1th row. Furthermore, the operations performed on the OB pixels PXB from time t11 to time t17 are repeated for the OB pixels PXB. In this manner, the operations for generating second digital signals and differential digital signals, as performed from time t11 to time t17, are sequentially performed on all rows of the pixels PX. Through these operations, differential digital signals corresponding to each pixel PX are generated, thereby generating an image in the imaging device 120.

[0192] 8, the first reference signal is read out after the reset signal to generate the first digital signal, and the second reference signal is read out after the pixel signal to generate the second digital signal, but the order of these readouts may be reversed. That is, the reset signal may be read out after the first reference signal to generate the first digital signal, and the pixel signal may be read out after the second reference signal to generate the second digital signal. Also, in the example shown in FIG. 8, the potential of the charge storage unit FD of the pixel PX is not reset after the pixel signal is readout, but the charge storage unit FD of the pixel PX may be reset.

[0193] In addition, if the imaging device 120 is equipped with a selector 45 or a switch for controlling which of the vertical signal lines 35 and 35c the analog signal input to is output to the column circuit 43, the period for reading the reset signal, the period for reading the pixel signal, and the period for reading the reference signal can be made to overlap.

[0194] (Embodiment 2) Next, a description will be given of embodiment 2. In embodiment 2, a camera system including an imaging device according to the present disclosure will be described.

[0195] FIG. 9 is a block diagram showing an example of the configuration of a camera system 400 according to this embodiment.

[0196] 9, camera system 400 according to this embodiment includes lens optical system 601, imaging device 602, system controller 603, and camera signal processing circuit 604. Camera system 400 may be, for example, a smartphone, a digital camera, a video camera, or an in-vehicle camera.

[0197] The lens optical system 601 focuses light onto an imaging surface of the imaging device 602. The lens optical system 601 may include, for example, a lens group including an autofocus lens and a zoom lens, and an aperture. The imaging device 602 may be, for example, the imaging device according to any one of the above-described first embodiment and modifications 1 and 2 of the first embodiment.

[0198] The system controller 603 controls the entire camera system 400. The system controller 603 is, for example, a semiconductor integrated circuit, and a specific example is a CPU (Central Processing Unit).

[0199] The camera signal processing circuit 604 has a function of processing an output signal from the image capture device 602. The camera signal processing circuit 604 receives output data such as a differential digital signal from the image capture device 602 and performs processes such as gamma correction, color interpolation, spatial interpolation, and auto white balance. The camera signal processing circuit 604 is, for example, a DSP (Digital Signal Processor). The image capture device 602 and the camera signal processing circuit 604 may be implemented as a single semiconductor device. The semiconductor device may be, for example, a so-called SoC (System on a Chip). This configuration allows for further miniaturization of electronic devices that include the image capture device 602 as a part thereof.

[0200] Furthermore, the imaging device 602 may not include the memory 48 and the processing circuit 49, and the camera signal processing circuit 604 may perform the processing performed by the processing circuit 49. In other words, the camera signal processing circuit 604 may generate a differential digital signal based on the difference between the first digital signal and the second digital signal.

[0201] While the imaging device and camera system according to the present disclosure have been described above based on the embodiments, the present disclosure is not limited to these embodiments. As long as they do not deviate from the gist of the present disclosure, various modifications conceivable by those skilled in the art to the embodiments, as well as other forms constructed by combining some of the components of the embodiments, are also included within the scope of the present disclosure.

[0202] For example, in the above embodiment, the combining circuits 50, 50A, and 50B are used to generate a reference signal, but this is not limiting. The combining circuits 50, 50A, and 50B may be used to combine analog signals of the pixels PX in order to monitor power supply noise across the entire pixel.

[0203] In the above-described embodiment, the processing performed by a specific processing unit may be performed by another processing unit. The order of multiple processing operations may be changed, or multiple processing operations may be performed in parallel.

[0204] In the above-described embodiments, each component may be realized by executing a software program suitable for that component, or by a program execution unit such as a CPU or processor reading and executing a software program recorded on a recording medium such as a hard disk or semiconductor memory.

[0205] Furthermore, each component may be realized by hardware. Each component may be a circuit (or integrated circuit). These circuits may form a single circuit as a whole, or each may be a separate circuit. Furthermore, each of these circuits may be a general-purpose circuit or a dedicated circuit.

[0206] Furthermore, the general or specific aspects of the present disclosure may be realized as a system, an apparatus, a method, an integrated circuit, a computer program, or a computer-readable recording medium such as a CD-ROM, or as any combination of a system, an apparatus, a method, an integrated circuit, a computer program, and a recording medium.

[0207] For example, the present disclosure may be realized as an imaging device according to the above-described embodiment, as a control device that controls an imaging device, as a program for causing a computer to execute a method for driving an imaging device performed by a processing unit such as a control circuit, or as a computer-readable non-transitory recording medium on which such a program is recorded.

[0208] Furthermore, the above-described embodiments can be modified, substituted, added, omitted, and the like in various ways within the scope of the claims or their equivalents.

[0209] The imaging device according to the present disclosure is useful, for example, in image sensors, digital cameras, etc. The imaging device according to the present disclosure can be used in medical cameras, robot cameras, security cameras, cameras mounted on vehicles, etc.

[0210] 12 Photoelectric conversion unit 12a Pixel electrode 12b Photoelectric conversion layer 12c Counter electrode 22 Reset transistor 23 Amplifying transistor 24 Selection transistor 31 Reset voltage line 35, 35a, 35b, 35c Vertical signal line 39 Current source 40 Peripheral circuit 42 Vertical scanning circuit 43 Column circuit 44 Horizontal signal readout circuit 45 Selector 46 Control circuit 47 Conversion circuit 48 Memory 49 Processing circuit 50, 50A, 50B Combining circuit 51, 51a, 51b, 51c Switch 60 Semiconductor substrate 100, 110, 120, 602 Imaging device 400 Camera system 601 Lens optical system 603 System controller 604 Camera signal processing circuit CF Color filter PX Pixel PXB OB pixel SL Row control line

Claims

1. An imaging device comprising: a plurality of pixels arranged in a plurality of rows and columns; and a synthesis circuit to which analog signals output from said plurality of pixels are input, said analog signals including a reset signal representing a reset level and a pixel signal representing an image of a subject, said synthesis circuit outputting, within one frame period, the reset signal output from a first pixel of said plurality of pixels, the pixel signal output from said first pixel, and a reference signal obtained by synthesizing the reset signals output from two or more pixels included in a first group of said plurality of pixels.

2. The imaging device according to claim 1, further comprising a conversion circuit that receives the output of the synthesis circuit and generates a digital signal, wherein the conversion circuit generates a first digital signal based on the difference between the reset signal output from the first pixel and the reference signal output at a first timing, and generates a second digital signal based on the difference between the pixel signal output from the first pixel and the reference signal output at a second timing.

3. An imaging device as described in claim 2, further comprising: a frame memory; and a processing circuit, wherein the frame memory temporarily stores the first digital signal generated by the conversion circuit, and the processing circuit outputs the difference between the second digital signal and the first digital signal stored in the frame memory.

4. The imaging device according to claim 1, wherein the synthesis circuit comprises: a plurality of output signal lines connected to the two or more pixels included in the first group; and at least one switch that electrically connects the plurality of output signal lines to each other.

5. The imaging device described in claim 4, wherein the plurality of output signal lines include a first output signal line connected to the first pixel and a second output signal line connected to a second pixel of the plurality of pixels, the at least one switch includes a switch connected between the first output signal line and the second output signal line, and the first pixel and the second pixel are sensitive to light in different wavelength ranges.

6. The imaging device according to claim 1, wherein the two or more pixels included in the first group include the first pixel.

7. The imaging device according to claim 1, wherein the two or more pixels included in the first group are located in the same row as the first pixel.

8. The imaging device according to claim 1, wherein the two or more pixels included in the first group are located in a different row from the first pixel.

9. The imaging device according to claim 1, wherein each of the two or more pixels included in the first group is a pixel different from the first pixel and is an ineffective pixel in which the signal level of the analog signal does not change when light is incident thereon.

10. The imaging device according to claim 1, wherein the number of the two or more pixels included in the first group is ten or more.

11. A camera system comprising the imaging device according to any one of claims 1 to 10.

Images