Data transmission method, device, and system

Abstract

The present application provides a data transmission method, a device, and a system. In the solution provided by the present application, on the basis of symbol groups, a sending end multiplexes a data streams to obtain b data streams, wherein a is an integer greater than or equal to 2, b is an integer greater than or equal to 1, b<a, any one of the b data streams comprises a plurality of symbol groups, any one of the symbol groups comprises a plurality of symbols from different codewords, and any one of the symbols comprises a plurality of bits; and the sending end transmits the b data streams. In the solution provided by the present application, a sending end performs multiplexing on the basis of symbol groups each comprising symbols, and even if a burst error of a plurality of consecutive bits occurs in the transmission process, when a receiving end performs demultiplexing on the basis of the symbol groups, the number of symbols affected by a burst error of the plurality of consecutive bits of the data streams multiplexed on the basis of the symbol groups is far smaller than the number of symbols affected by the burst error of the plurality of consecutive bits of the data streams multiplexed on the basis of bits, so that the error correction performance and the reliability of the system are improved.

Description

Data Transmission Method, Apparatus and System Technical Field

[0001] This application belongs to the field of communication technologies, and particularly relates to a data transmission method, apparatus and system. Background Art

[0002] In the architecture of a high-speed interface of a traditional Ethernet, it includes a Physical Medium Attachment (PMA) layer. The PMA layer is used to perform data transmission rate conversion. The traditional PMA layer processes data in a bit multiplexing (Bit Mux) manner. Taking the sending end as an example, the PMA layer multiplexes m data streams obtained based on symbol interleaving into n data streams in units of bits, and the n data streams are output through the PMA channel. During the process of data transmission from the sending end to the receiving end, if there are burst errors in the transmitted data, for example, there are consecutive burst error data of multiple bits in a certain data stream among the n data streams, when the receiving end demultiplexes the n data streams, the above-mentioned consecutive burst error data of multiple bits will be demultiplexed into multiple symbols of multiple streams, resulting in a large spread of burst errors, increasing the difficulty of error correction at the receiving end and reducing the system reliability.

[0003] Summary of the Invention

[0004] Embodiments of this application provide a data transmission method, apparatus and system, which can reduce the difficulty of error correction and improve the system reliability.

[0005] In a first aspect, a data transmission method is provided, including: multiplexing a data streams based on symbol group multiplexing to obtain b data streams, where a is an integer greater than or equal to 2, b is an integer greater than or equal to 1 and b < a, and any one of the b data streams includes multiple symbol groups, any symbol group includes multiple symbols from different codewords, and any symbol includes multiple bits; transmitting the b data streams. In the above method, through symbol group-based multiplexing at the sending end, it is possible to avoid consecutive burst error data generated during transmission from being demultiplexed into multiple symbols of multiple streams, which helps reduce the spread of burst errors, reduces the difficulty of error correction, and improves the system reliability.

[0006] In one possible implementation, the a data stream includes a first data stream and a second data stream, the b data stream includes a third data stream, the multiple symbol groups include a first symbol group and a second symbol group, the first symbol group and the second symbol group are continuous in the third data stream, all symbols in the first symbol group come from the first data stream and are continuous in the first data stream, and all symbols in the second symbol group come from the second data stream and are continuous in the second data stream.

[0007] In a possible implementation, the a data streams are based on Reed-Solomon (RS) coding, and the symbols are RS symbols. The length of the RS symbols is 10 bits.

[0008] In one possible implementation, a is equal to 8, b is equal to 1, the number of symbols included in the symbol group is 2, and any consecutive 8 symbol groups included in the b data streams are from the 8 data streams. This implementation belongs to the 200GBASE-R technology, and the two symbols included in the symbol group are from different codewords in the same codeword group.

[0009] In one possible implementation, before multiplexing a data stream based on symbol groups to obtain b data streams, the method further includes: delaying the transmission of the data stream output by each odd-numbered channel in the a data stream by L symbols, where L is equal to 136*N+1, and N is an integer greater than or equal to 1. In this implementation, the ordering of codewords to which consecutive symbols output by any even-numbered channel in the a data stream belong before the delayed transmission is different from the ordering of codewords to which consecutive symbols output by any odd-numbered channel in the a data stream belong before the delayed transmission. After the delayed transmission, the ordering of codewords to which consecutive symbols output by any two channels in the a data stream belong is the same.

[0010] In one possible implementation, a is equal to 16, b is equal to 2, the symbol group comprises 2 symbols, and any consecutive 8 symbol groups included in any data stream in the b data streams are from 8 data streams in the a data stream. This implementation belongs to 400GBASE-R technology, and the two symbols included in the symbol group are from different codewords in the same codeword group.

[0011] In one possible implementation, before multiplexing a data stream based on symbol groups to obtain b data streams, the method further includes: delaying the transmission of the data stream output by each odd-numbered channel in the a data stream by L symbols, where L is equal to 68*N+1, and N is an integer greater than or equal to 1. In this implementation, the ordering of codewords to which consecutive symbols output by any even-numbered channel in the a data stream belong before the delayed transmission is different from the ordering of codewords to which consecutive symbols output by any odd-numbered channel in the a data stream belong before the delayed transmission. After the delayed transmission, the ordering of codewords to which consecutive symbols output by any two channels in the a data stream belong is the same.

[0012] In one possible implementation, a is equal to 16, b is equal to 8, the symbol group comprises 4 symbols, and any two consecutive symbol groups comprised in any one of the b data streams are respectively from two data streams in the a data stream. This implementation relates to 1.6TBASE-R technology, and the two symbols comprised in a symbol group are from different codewords in the same codeword group. The ordering of the codewords to which consecutive symbols output by any even-numbered channel in the a data stream belong is the same as the ordering of the codewords to which consecutive symbols output by any odd-numbered channel in the a data stream belong.

[0013] In one possible implementation, a is equal to 32, b is equal to 4, the number of symbols included in the symbol group is 2, any consecutive 8 symbol groups included in any data stream in the b data streams are respectively from 8 data streams in the a data stream, the 8 data streams in the a data stream include 4 data streams from a first codeword group and 4 data streams from a second codeword group, the first codeword group includes 2 codewords, the second codeword group includes 2 codewords, and the 2 codewords included in the first codeword group are different from the 2 codewords included in the second codeword group. This implementation belongs to 800GBASE-R technology.

[0014] In one possible implementation, before multiplexing a data stream based on symbol groups to obtain b data streams, the method further includes: delaying the transmission of the data stream output by each odd-numbered channel in the a data stream by L symbols, where L is equal to 2*N+1, and N is an integer greater than or equal to 0. In this implementation, the ordering of codewords belonging to consecutive symbols from the same codeword group output by any even-numbered channel in the a data stream before the delayed transmission is different from the ordering of codewords belonging to consecutive symbols from the same codeword group output by any odd-numbered channel in the a data stream before the delayed transmission. After the delayed transmission, the ordering of codewords belonging to consecutive symbols from the same codeword group output by any even-numbered channel in the a data stream is the same as the ordering of codewords belonging to consecutive symbols from the same codeword group output by any odd-numbered channel in the a data stream after the delayed transmission.

[0015] In one possible implementation, the method further includes: encoding the received data to obtain K codeword groups, where K is an integer greater than or equal to 1, and the number of symbols included in any codeword in the K codeword groups is a positive integer multiple of 544; and interleaving the codewords included in the K codeword groups based on the symbols to obtain the a data streams.

[0016] In one possible implementation, the encoding includes feed-forward error correction (FEC) encoding.

[0017] In a possible implementation, the sum of the rates of the a data streams is the same as the sum of the rates of the b data streams.

[0018] In a possible implementation, a rate of any one of the b data streams is 200 gigabits per second (Gbps).

[0019] In a second aspect, a data transmission method is provided, comprising: receiving b data streams, where b is an integer greater than or equal to 1, any one of the b data streams including multiple symbol groups, any one symbol group including multiple symbols from different codewords, and any one symbol including multiple bits; demultiplexing the b data streams based on the symbol groups to obtain a data stream, where a is an integer greater than or equal to 2 and a>b.

[0020] In a possible implementation, the a data streams include a first data stream and a second data stream, the b data streams include a third data stream, the multiple symbol groups include a first symbol group and a second symbol group, the first symbol group and the second symbol group are consecutive in the third data stream, all symbols in the first symbol group are from the first data stream and are consecutive in the first data stream, and all symbols in the second symbol group are from the second data stream and are consecutive in the second data stream.

[0021] In a possible implementation, the a data streams are based on Reed - Solomon (RS) coding, and the symbols are RS symbols.

[0022] In a possible implementation, the length of the RS symbol is 10 bits.

[0023] In a third aspect, a data transmission device is provided. The device includes a processor and a transmitter coupled to the processor. The processor is configured to multiplex a data streams based on symbol groups to obtain b data streams, where a is an integer greater than or equal to 2, b is an integer greater than or equal to 1 and b < a. Among the b data streams, any one of the data streams includes multiple symbol groups, any symbol group includes multiple symbols from different codewords, and any symbol includes multiple bits. The transmitter is configured to transmit the b data streams.

[0024] In a possible implementation, the a data streams include a first data stream and a second data stream, the b data streams include a third data stream, the multiple symbol groups include a first symbol group and a second symbol group, the first symbol group and the second symbol group are consecutive in the third data stream, all symbols in the first symbol group are from the first data stream and are consecutive in the first data stream, and all symbols in the second symbol group are from the second data stream and are consecutive in the second data stream.

[0025] In a possible implementation, the a data streams are based on Reed - Solomon (RS) coding, and the symbols are RS symbols.

[0026] In a possible implementation, the length of the RS symbol is 10 bits.

[0027] In a possible implementation, a = 8, b = 1, the number of symbols included in the symbol group is 2, and any consecutive 8 symbol groups included in the b data streams are respectively from the 8 data streams.

[0028] In one possible implementation, the processor is further configured to delay sending the data stream output by each channel with an odd sequence number in the a data streams by L symbols, where L is equal to 136*N+1, and N is an integer greater than or equal to 1.

[0029] In one possible implementation, a is equal to 16, b is equal to 2, the number of symbols included in the symbol group is 2, and any consecutive 8 symbol groups included in any data stream in the b data streams come from 8 data streams in the a data stream.

[0030] In a possible implementation, the processor further delays the transmission of the data stream output by each channel with an odd sequence number in the a data streams by L symbols, where L is equal to 68*N+1, and N is an integer greater than or equal to 1.

[0031] In one possible implementation, a is equal to 16, b is equal to 8, the number of symbols included in the symbol group is 4, and any two consecutive symbol groups included in any one of the b data streams come from two data streams in the a data stream.

[0032] In a possible implementation, the order of codewords to which consecutive symbols output by a channel with any even sequence number in the a data streams belong is the same as the order of codewords to which consecutive symbols output by a channel with any odd sequence number in the a data streams belong.

[0033] In one possible implementation, a is equal to 32, b is equal to 4, the number of symbols included in the symbol group is 2, any consecutive 8 symbol groups included in any data stream in the b data streams are respectively from 8 data streams in the a data stream, the 8 data streams in the a data stream include 4 data streams from the first codeword group and 4 data streams from the second codeword group, the first codeword group includes 2 codewords, the second codeword group includes 2 codewords, and the 2 codewords included in the first codeword group are different from the 2 codewords included in the second codeword group.

[0034] In one possible implementation, the processor is further configured to delay sending the data stream output by each channel with an odd sequence number in the a data streams by L symbols, where L is equal to 2*N+1, and N is an integer greater than or equal to 0.

[0035] In one possible implementation, the processor is further used to: encode the received data to obtain K codeword groups, where K is an integer greater than or equal to 1, and the number of symbols included in any codeword in the K codeword groups is a positive integer multiple of 544; and interleave the codewords included in the K codeword groups based on the symbols to obtain the a data streams.

[0036] In a possible implementation, the encoding includes feed-forward error correction (FEC) encoding.

[0037] In a possible implementation, the sum of the rates of the a data streams is the same as the sum of the rates of the b data streams.

[0038] In a possible implementation, the rate of any one of the b data streams is 200 Gbps.

[0039] In a fourth aspect, a data receiving device is provided, comprising a processor and a receiver coupled to the processor: the receiver is used to receive b data streams, where b is an integer greater than or equal to 1, and any one of the b data streams includes multiple symbol groups, any symbol group includes multiple symbols from different codewords, and any symbol includes multiple bits; the processor is used to demultiplex the b data streams based on the symbol groups to obtain a data stream, where a is an integer greater than or equal to 2 and a>b.

[0040] In one possible implementation, the a data stream includes a first data stream and a second data stream, the b data stream includes a third data stream, the multiple symbol groups include a first symbol group and a second symbol group, the first symbol group and the second symbol group are continuous in the third data stream, all symbols in the first symbol group come from the first data stream and are continuous in the first data stream, and all symbols in the second symbol group come from the second data stream and are continuous in the second data stream.

[0041] In a possible implementation, the a data streams are based on Reed-Solomon (RS) coding, and the symbols are RS symbols.

[0042] In a possible implementation, the length of the RS symbol is 10 bits.

[0043] In a fifth aspect, a data processing device is provided, which includes a unit for executing the method provided by the first aspect and any possible implementation of the first aspect, or a unit for executing the method provided by the second aspect and any possible implementation of the second aspect.

[0044] In a sixth aspect, a data processing device is provided, the device comprising a processor, the processor being used to implement the method provided by the above-mentioned first aspect and any possible implementation of the first aspect, or the method provided by the above-mentioned second aspect and any possible implementation of the second aspect.

[0045] In one possible implementation, the device also includes a memory, which is used to store computer-executable instructions. When the processor executes the computer-executable instructions in the memory, it triggers the device to implement the method provided by the above-mentioned first aspect and any possible implementation of the first aspect, or the method provided by the above-mentioned second aspect and any possible implementation of the second aspect.

[0046] In the seventh aspect, a computer-readable storage medium is provided, in which instructions are stored. When the instructions are executed on a computer, the computer executes the method provided by the first aspect and any possible implementation of the first aspect, or the method provided by the second aspect and any possible implementation of the second aspect.

[0047] In an eighth aspect, a computer program product is provided, wherein instructions are stored in the computer program product. When the instructions are run on a computer, the computer is caused to execute the method provided by the first aspect and any possible implementation of the first aspect, or the method provided by the second aspect and any possible implementation of the second aspect.

[0048] In the ninth aspect, a chip is provided, which may include a processing circuit or an interface circuit, and when the chip is running, it is used to implement the method provided by the above-mentioned first aspect and any possible implementation of the first aspect, or the method provided by the above-mentioned second aspect and any possible implementation of the second aspect.

[0049] In a tenth aspect, a system is provided, the system comprising a transmitting end and a receiving end, the transmitting end comprising the apparatus provided by the third aspect or any possible implementation of the third aspect, and the receiving end comprising the apparatus provided by the fourth aspect or any possible implementation of the fourth aspect. The transmitting end device and the receiving end device both comprise a main chip; or the transmitting end device and the receiving end device both comprise a main chip, a clock and data recovery (CDR) chip, and an optical module; or the transmitting end device and the receiving end device both comprise a main chip and an optical module; or the transmitting end device comprises: a main chip, a CDR chip, and an optical module, and the receiving end device comprises a main chip and an optical module; or the transmitting end device comprises: a main chip and an optical module, and the receiving end device comprises a main chip, a CDR chip, and an optical module.

[0050] In an eleventh aspect, a data processing method is provided, the method comprising

[0051] performing first data processing on the received first data to obtain second data;

[0052] Distributing the second data based on the data blocks to obtain a first data stream and a second data stream;

[0053] Performing FEC encoding on the first data stream to obtain a first codeword and a second codeword;

[0054] Performing FEC encoding on the second data stream to obtain a third codeword and a fourth codeword;

[0055] The first codeword, the second codeword, the third codeword, and the fourth codeword are interleaved and distributed based on the symbols to obtain a data streams, where a is an integer greater than 1.

[0056] In a possible implementation, after obtaining a data stream, the method further includes: the steps included in the method provided by the first aspect or any possible implementation of the first aspect.

[0057] In a possible implementation manner, the method provided by the first aspect or any possible implementation manner of the first aspect is implemented by PMA.

[0058] In a possible implementation, the step of obtaining the second data stream to the step of obtaining the a data streams are implemented by a physical coding sublayer (PCS).

[0059] In one possible implementation, the first data processing includes transcoding from 64B / 66B to 256B / 257B, and the first data is data obtained after 64B / 66B encoding, where B represents a bit block.

[0060] In a possible implementation, the first codeword and the second codeword come from the same encoder, and the third codeword and the fourth codeword come from the same encoder.

[0061] In a possible implementation, a is 16, and four consecutive symbols in any one of the a data streams come from the first codeword, the second codeword, the third codeword, and the fourth codeword, respectively.

[0062] In a possible implementation, a is 16, and the rate of any one of the a data streams is 100 Gbps.

[0063] In a possible implementation manner, the codewords included in the codeword group are encoded by the same encoder.

[0064] In a possible implementation, the method is implemented by a chip or an optical module at the transmitting end.

[0065] In a possible implementation, the data block is 257 bits (bit, b).

[0066] In a twelfth aspect, a data processing method is provided, which is obtained by reversely running the method provided in the eleventh aspect. The method is implemented by a chip or optical module at the receiving end.

[0067] According to a thirteenth aspect, a data sending device is provided, the device including a processor, wherein the processor is configured to:

[0068] performing first data processing on the received first data to obtain second data;

[0069] Distributing the second data based on the data blocks to obtain a first data stream and a second data stream;

[0070] Performing FEC encoding on the first data stream to obtain a first codeword and a second codeword;

[0071] Performing FEC encoding on the second data stream to obtain a third codeword and a fourth codeword;

[0072] The first codeword, the second codeword, the third codeword, and the fourth codeword are interleaved and distributed based on the symbols to obtain a data streams, where a is an integer greater than 1.

[0073] In a possible implementation manner, the processor is further configured to execute the steps included in the method provided by the first aspect or any possible implementation manner of the first aspect.

[0074] In a possible implementation manner, the method provided by the first aspect or any possible implementation manner of the first aspect is implemented by a PMA included in the processor.

[0075] In a possible implementation, the step of obtaining the second data stream to the step of obtaining the a data streams are implemented by a physical coding sublayer (PCS) included in the processor.

[0076] In one possible implementation, the first data processing includes transcoding from 64B / 66B to 256B / 257B, and the first data is data obtained after 64B / 66B encoding, where B represents a bit block.

[0077] In a possible implementation, the first codeword and the second codeword come from the same encoder included in the processor, and the third codeword and the fourth codeword come from the same encoder included in the processor.

[0078] In a possible implementation, a is 16, and four consecutive symbols in any one of the a data streams come from the first codeword, the second codeword, the third codeword, and the fourth codeword, respectively.

[0079] In a possible implementation, a is 16, and the rate of any one of the a data streams is 100 Gbps.

[0080] In a possible implementation manner, the codewords included in the codeword group are obtained by encoding using the same encoder included in the processor.

[0081] In a possible implementation, the processor is located in a chip or an optical module at the transmitting end.

[0082] In a possible implementation, the data block is 257 bits (bit, b).

[0083] In a fourteenth aspect, a data receiving device is provided, comprising a processor configured to execute a method obtained by inversely running the method provided in the eleventh aspect. The processor is located in a chip or optical module at a receiving end.

[0084] A fifteenth aspect provides a data processing method, the method comprising

[0085] Encoding the received first data to obtain second data;

[0086] Distributing the second data based on the data blocks to obtain a first data stream and a second data stream;

[0087] Performing first data processing and FEC encoding on the first data stream to obtain a first codeword and a second codeword;

[0088] Performing the first data processing and FEC encoding on the second data stream to obtain a third codeword and a fourth codeword;

[0089] The first codeword, the second codeword, the third codeword, and the fourth codeword are interleaved and distributed based on the symbols to obtain a data streams, where a is an integer greater than 1.

[0090] In a possible implementation, after obtaining a data stream, the method further includes: the steps included in the method provided by the first aspect or any possible implementation of the first aspect.

[0091] In a possible implementation manner, the method provided by the first aspect or any possible implementation manner of the first aspect is implemented by PMA.

[0092] In a possible implementation, the step of obtaining the second data stream to the step of obtaining the a data streams are implemented by a physical coding sublayer (PCS).

[0093] In one possible implementation, the first data processing includes transcoding from 64B / 66B to 256B / 257B, and the second data is data obtained after 64B / 66B encoding, where B represents a bit block.

[0094] In a possible implementation, the first codeword and the second codeword come from the same encoder, and the third codeword and the fourth codeword come from the same encoder.

[0095] In a possible implementation, a is 32, and two consecutive symbols in any one of the a data streams come from the same codeword group, the codeword group includes the first codeword and the second codeword, or the codeword group includes the third codeword and the fourth codeword.

[0096] In a possible implementation, a is 32, and the rate of any one of the a data streams is 25 Gbps.

[0097] In a possible implementation manner, the codewords included in the codeword group are encoded by the same encoder.

[0098] In a possible implementation, the method is implemented by a chip or an optical module at the transmitting end.

[0099] In a possible implementation, the data block is 66 bits (bit, b).

[0100] In a sixteenth aspect, a data processing method is provided, which is obtained by reversely performing the method provided in the fifteenth aspect. The method is implemented by a chip or optical module at a receiving end.

[0101] In a seventeenth aspect, a data sending device is provided, the device including a processor, wherein the processor is configured to:

[0102] Encoding the received first data to obtain second data;

[0103] Distributing the second data based on the data blocks to obtain a first data stream and a second data stream;

[0104] Performing first data processing and FEC encoding on the first data stream to obtain a first codeword and a second codeword;

[0105] Performing the first data processing and FEC encoding on the second data stream to obtain a third codeword and a fourth codeword;

[0106] The first codeword, the second codeword, the third codeword, and the fourth codeword are interleaved and distributed based on the symbols to obtain a data streams, where a is an integer greater than 1.

[0107] In a possible implementation manner, the processor is further configured to execute the steps included in the method provided by the first aspect or any possible implementation manner of the first aspect.

[0108] In a possible implementation manner, the method provided by the first aspect or any possible implementation manner of the first aspect is implemented by a PMA included in the processor.

[0109] In a possible implementation, the step of obtaining the second data stream to the step of obtaining the a data streams are implemented by a physical coding sublayer (PCS) included in the processor.

[0110] In one possible implementation, the first data processing includes transcoding from 64B / 66B to 256B / 257B, and the second data is data obtained after 64B / 66B encoding, where B represents a bit block.

[0111] In a possible implementation, the first codeword and the second codeword come from the same encoder included in the processor, and the third codeword and the fourth codeword come from the same encoder.

[0112] In a possible implementation, a is 32, and two consecutive symbols in any one of the a data streams come from the same codeword group, the codeword group includes the first codeword and the second codeword, or the codeword group includes the third codeword and the fourth codeword.

[0113] In a possible implementation, a is 32, and the rate of any one of the a data streams is 25 Gbps.

[0114] In a possible implementation manner, the codewords included in the codeword group are obtained by encoding using the same encoder included in the processor.

[0115] In a possible implementation, the processor is provided in a chip or an optical module at the transmitting end.

[0116] In a possible implementation, the data block is 66 bits (bit, b).

[0117] In an eighteenth aspect, a data receiving device is provided, comprising a processor configured to execute a method obtained by inversely running the method provided in the fifteenth aspect. The processor is located in a chip or optical module at a receiving end. BRIEF DESCRIPTION OF THE DRAWINGS

[0118] Figure 1(a) is a schematic diagram of data processing at the sending end.

[0119] Figure 1(b) is a schematic diagram of data processing at the receiving end.

[0120] FIG2 is a flow chart of a data processing method according to an embodiment of the present application.

[0121] FIG3( a ) is a schematic diagram of interleaving and offsetting two codewords included in a codeword group provided in an embodiment of the present application.

[0122] FIG3( b ) is a schematic diagram of multiplexing the offset data stream in FIG3( a ) to obtain a data stream, provided by an embodiment of the present application.

[0123] FIG4( a ) is a schematic diagram of interleaving and offsetting two codewords included in a codeword group provided in an embodiment of the present application.

[0124] FIG4( b ) is a schematic diagram of multiplexing the offset data stream in FIG4( a ) to obtain two data streams, provided by an embodiment of the present application.

[0125] FIG5( a ) is a schematic diagram of interleaving and offsetting multiple codewords included in two codeword groups provided in an embodiment of the present application.

[0126] FIG5( b ) is a schematic diagram of multiplexing the offset data stream in FIG5( a ) to obtain four data streams, provided by an embodiment of the present application.

[0127] FIG6 is a schematic diagram of multiplexing four codewords included in a codeword group provided in an embodiment of the present application.

[0128] FIG7 is a flow chart of another data processing method provided in an embodiment of the present application.

[0129] FIG8( a ) is a schematic diagram of demultiplexing a multiplexed data stream provided in an embodiment of the present application.

[0130] FIG8( b ) is a schematic diagram of offsetting the demultiplexed data stream in FIG8( a ) provided in an embodiment of the present application.

[0131] FIG9( a ) is a schematic diagram of demultiplexing two multiplexed data streams provided in an embodiment of the present application.

[0132] FIG9( b ) is a schematic diagram of offsetting the demultiplexed data stream in FIG9( a ) provided in an embodiment of the present application.

[0133] FIG10( a ) is a schematic diagram of demultiplexing four multiplexed data streams provided in an embodiment of the present application.

[0134] FIG10( b ) is a schematic diagram of offsetting the demultiplexed data stream in FIG10( a ) provided in an embodiment of the present application.

[0135] FIG11 is a schematic diagram of demultiplexing 8 multiplexed data streams provided in an embodiment of the present application.

[0136] FIG12( a ) is a schematic diagram of the structure of a hardware provided in an embodiment of the present application.

[0137] FIG12( b ) is a schematic diagram of the structure of another hardware provided in an embodiment of the present application.

[0138] FIG13( a ) is a schematic diagram showing a data processing method provided in an embodiment of the present application implemented by a chip.

[0139] FIG13( b ) is a schematic diagram showing a data processing method provided in an embodiment of the present application implemented by a chip.

[0140] FIG13( c ) is a schematic diagram showing a data processing method provided in an embodiment of the present application implemented by a chip.

[0141] FIG14( a ) is a schematic diagram showing a data processing method provided in an embodiment of the present application implemented by multiple chips.

[0142] FIG14( b ) is a schematic diagram showing the data processing method provided in an embodiment of the present application being implemented by multiple chips.

[0143] FIG14( c ) is a schematic diagram showing the data processing method provided in an embodiment of the present application being implemented by multiple chips.

[0144] FIG14( d ) is a schematic diagram showing the data processing method provided in an embodiment of the present application being implemented by multiple chips.

[0145] FIG14( e ) is a schematic diagram showing the data processing method provided in an embodiment of the present application being implemented by multiple chips.

[0146] FIG14( f ) is a schematic diagram showing the data processing method provided in an embodiment of the present application being implemented by multiple chips.

[0147] Figure 15(a) is a structural diagram of a data sending device provided in an embodiment of the present application.

[0148] FIG15( b ) is a schematic structural diagram of a data receiving device provided in an embodiment of the present application.

[0149] FIG16( a ) is a schematic structural diagram of another data sending device provided in an embodiment of the present application.

[0150] FIG16( b ) is a schematic structural diagram of another data receiving device provided in an embodiment of the present application.

[0151] FIG17 is a schematic structural diagram of a data processing device provided in an embodiment of the present application.

[0152] FIG18 is a schematic structural diagram of a data processing system provided in an embodiment of the present application. DETAILED DESCRIPTION

[0153] To facilitate data processing or reduce costs, chips, units, or modules typically process multiple lower-rate data streams to obtain one or more higher-rate data streams. This data processing may include mapping, multiplexing, interleaving, or merging. The one or more higher-rate data streams can be transmitted via optical fiber or other media. Figure 1(a) provides a data processing method at the transmitter. The transmitter in Figure 1(a) uses a multiplexing data processing method, that is, multiplexing is performed at a bit granularity. The transmitter merges multiple low-rate data streams into a high-rate data stream. Each grid in Figure 1(a) represents 1 bit of data from a data stream from the transmitter. In each grid marked XY, X represents data from data stream X, and Y represents the Yth bit. Figure 1(a) uses n+1 bits in each data stream as an example for illustration, where n is an integer greater than or equal to 0. As shown in Figure 1(a), data stream 0, data stream 1, data stream 2, and data stream 3 are all low-rate data streams, for example, 25 gigabits per second (Gbps). The transmitter reads the Yth bit of data from each low-rate data stream in the order data stream 0 -> data stream 1 -> data stream 2 -> data stream 3, and uses this data as the 4 bits sequentially output from the resulting high-rate data stream (the muxed stream shown in Figure 1(a)). The transmitter then loops through the process in this manner, obtaining the 4*(n+1) bits of data contained in the muxed stream. The muxed stream in Figure 1(a) may experience burst errors during transmission, i.e., multiple consecutive bit errors. As shown in Figure 1(b), the muxed stream received by the receiver includes a 10-bit burst error (the shaded grid in Figure 1(b)). These 10 bits, labeled 3.0, 0.1, 1.1, 2.1, 3.1, 0.2, 1.2, 2.2, 3.2, and 0.3, experience burst errors during transmission. Based on the muxed stream with the 10-bit burst service, the receiver obtains four low-rate data streams, namely, data stream 0', data stream 1', data stream 2', and data stream 3'.At the receiving end, the 10-bit burst error is spread across multiple symbols in data stream 0', data stream 1', data stream 2', and data stream 3'. For example, 0.1, 0.2, and 0.3 belong to data stream 0', 1.1 and 1.2 belong to data stream 1', 2.1 and 2.2 belong to data stream 2', and 3.0, 3.1, and 3.2 belong to data stream 3'. The bit mux-based processing method used by the transmitting end causes burst errors during transmission to spread across multiple symbols in multiple data streams. Feedforward error correction (FEC) codewords can only correct a certain number of symbol errors. For example, when using Reed-Solomon (RS) (544, 514) FEC codewords, a maximum of 15 symbol errors can be corrected. Once the number of symbol errors caused by burst error data generated during the transmission process based on bit multiplexing exceeds the number of correctable symbol errors, for example, more than 15 symbol errors, the FEC codeword error correction processing will fail, reducing the error correction performance and the accuracy of subsequent data transmission, thereby reducing the reliability of the system.

[0154] Figure 2 is a flow chart of a data processing method provided by an embodiment of the present application. The method shown in Figure 2 is executed by a transmitting end, which can be a module or chip that plays a transmitting role. The module or chip can be set in a host or optical module, and the host can be a router, switch, or server.

[0155] 201. The sender obtains the input data stream.

[0156] In a first possible implementation, the input data stream is a data stream obtained by interleaving M codeword groups based on symbols, where M is an integer greater than or equal to 1. The codeword group includes multiple codewords. The multiple codewords included in the codeword group can be different codewords output by different encoders, or different codewords output successively by the same encoder. All symbols in any interleaved data stream come from the same codeword group. Any two consecutive symbols in any interleaved data stream come from different codewords, that is, two adjacent codewords come from different codewords in the same codeword group. Adjacent in the embodiments of the present application refers to bits or symbols that are adjacent in position and not separated by other codewords. The length of the symbol is multiple bits (bits), for example, the length of the symbol can be an integer multiple of 10 bits, specifically 10 bits, 20 bits, etc., which will not be explained one by one here. The symbol can be a Reed-Solomon symbol, in which case the length of the Reed-Solomon symbol is 10 bits. In the embodiments of the present application, bits can also be referred to as positions or bit positions, which is not limited in this application. Interleaving can be symbol-based multi-mix-one interleaving, symbol-based multi-mix-multi interleaving, or symbol-based single-mix interleaving. Among them, multi-mix-one interleaving means that multiple data streams are interleaved and become a single data stream. Multi-mix-multi interleaving means that multiple data streams are interleaved and become multiple data streams. Single-mix interleaving means that a single data stream remains a single data stream after interleaving. The changes in the data stream after interleaving compared to the data stream before interleaving include: the order in which the minimum data units in units of symbols are output is regularly adjusted. For example, the first data unit and the second data unit in the data stream before interleaving are exchanged in the sending order to form the data stream after interleaving.

[0157] In a second possible implementation, the input data stream is a data stream obtained after interleaving and offsetting. The interleaving is the interleaving of M codeword groups based on symbols in the first possible implementation, which will not be described in detail here. Offset is to delay one or more data streams from the same codeword group in the interleaved data stream by N bits, so that the symbols in the same position in any two data streams from the same codeword group come from the same codeword. The N is an integer greater than or equal to 1, for example, N bits can be one or more symbol lengths. Among them, from the perspective of the sequence number of the channel, the specific operation of the offset can be to delay the transmission of the data stream transmitted by the channel with an even sequence number among the multiple channels that transmit the input data stream by N bits, or to delay the transmission of the data transmitted by the channel with an odd sequence number among the multiple channels that transmit the input data stream by N bits. From the perspective of the codeword group, if the data streams transmitted through multiple channels of the input data flow come from the same codeword group, the specific operation of the offset can be to delay the transmission of one or more channels where the data streams with the same symbol order are located; if the data streams transmitted through multiple channels of the input data flow come from different codeword groups, the specific operation of the offset can be to delay the transmission of one or more channels where the data streams from the same codeword group are located, or the specific operation of the offset can be to delay the transmission of one or more channels where the data streams with the same symbol order from the same codeword group are located.

[0158] In a third possible implementation, the input data stream is a data stream obtained after encoding and interleaving. The encoding code type can be Reed-Solomon (RS) code, Bose-Chaudhuri-Hocquenghem (BCH) code, Hamming code, low density parity check (LDPC) code, polar code, convolutional code, turbo code, turbo product code (TPC), staircase code or Fire code, Reed Muller (RM) code or oFEC code. When the encoding code type is RS code, the codeword obtained after encoding includes RS symbols, and the specific description can be referred to the relevant description in the first possible implementation. The interleaving is to interleave the M codeword groups based on symbols in the first possible implementation, which will not be repeated here.

[0159] In a fourth possible implementation, the input data stream is a data stream obtained after encoding, interleaving, and shifting. The encoding is the encoding method described in the third possible implementation. The interleaving is the symbol-based interleaving of the M codeword groups described in the first possible implementation. The shifting is the shifting method described in the second possible implementation. These methods are not further described herein.

[0160] 202. The transmitting end multiplexes the input data stream based on the symbol groups, obtains the output data stream, and outputs it.

[0161] For example, any symbol group in the input data stream includes multiple symbols, and the multiple symbols in any symbol group come from multiple codewords. The codewords from which the multiple symbols in any symbol group come are in the same order. For 200GBASE-R and 400GBASE-R, any symbol group in the input data stream includes two symbols, and the two symbols come from different codewords in the same codeword group. The codewords from which the symbols output via odd-numbered channels in the input data stream come are in the same order, and the codewords from which the symbols output via even-numbered channels come are in the same order. The codewords from which the symbols output via any odd-numbered channel come are in a different order than the codewords from which the symbols output via any even-numbered channel come. For 800GBASE-R, any symbol group in the input data stream includes two symbols, and the two symbols come from different codewords in the same codeword group. The input data stream outputs symbols from a first codeword group via multiple channels and outputs symbols from a second codeword group via multiple other channels. The order of the codewords from which the symbols output by the channels with odd sequence numbers among the multiple channels that output symbols from the first codeword group is the same. The order of the codewords from which the symbols output by the channels with even sequence numbers among the multiple channels that output symbols from the first codeword group is the same. The order of the codewords from which the symbols output by any channel with odd sequence numbers among the multiple channels that output symbols from the first codeword group is different from the order of the codewords from which the symbols output by any channel with even sequence numbers are different. The order of the codewords from which the symbols output by the channels with odd sequence numbers among the multiple channels that output symbols from the second codeword group is the same. The order of the codewords from which the symbols output by the channels with even sequence numbers among the multiple channels that output symbols from the second codeword group is the same. The order of the codewords from which the symbols output by any channel with odd sequence numbers among the multiple channels that output symbols from the second codeword group is different from the order of the codewords from which the symbols output by any channel with even sequence numbers are different. For 1.6TBASE-R, any symbol group in the input data stream consists of four symbols, each of which comes from different codewords in the same codeword group. The symbols output by any two channels of the input data stream come from the same codeword sequence.

[0162] For example, the sending end can obtain the output data stream by means of polling. The input data stream can be transmitted through multiple channels, such as output through a channels, and the output data stream can also be transmitted through one or more channels, such as b channels, where a is an integer greater than or equal to 2, b is an integer greater than or equal to 1, and b < a. The sum of the data rates output by the a channels is the same as the sum of the data rates output by the b channels. For example, for 200GBASE-R, 400GBASE-R or 800GBASE-R, the exact value of the data rate output by each of the a channels is 26.5625Gbps. Then the sum of the rates of 8 data streams of 26.5625Gbps is 212.5Gbps. After multiplexing into 1 channel, the exact value of the data rate output by this 1 channel is 212.5Gbps. Usually, the data rate output by each of the a channels is roughly estimated to be 25Gbps. Then the sum of the rates of 8 data streams of 25Gbps is 200Gbps. After multiplexing into 1 channel, the data rate output by this 1 channel is 200Gbps. For 1.6TBASE-R, 2 data streams in the data stream output by the a channels are combined into 1 data stream output by the b channels. The exact value of the data rate output by each of the a channels is 106.25Gbps. Then the sum of the rates of 2 data streams of 106.25Gbps is 212.5Gbps. After multiplexing into 1 channel, the exact value of the data rate output by this 1 channel is 212.5Gbps. Usually, the data rate output by each of the a channels is roughly estimated to be 100Gbps. Then the sum of the rates of 2 data streams of 100Gbps is 200Gbps. After multiplexing into 1 channel, the exact value of the data rate output by this 1 channel is 200. The above a channels or b channels can be logically divided logical channels or physical channels, such as physical channels corresponding to the pins of the chip. The sending end can, based on the polling order, obtain consecutive multiple symbols on each of the multiple channels for transmitting the input data stream, and map the consecutive multiple symbols obtained on each channel as a symbol group to one channel for transmitting the output data stream. Among them, any two adjacent symbol groups in the data stream transmitted through any one of the one or more channels of the output data stream come from different channels of the input data stream. When the sending end performs polling, each time the multiple channels of the input data stream are polled once, it is counted as one cycle, and in each cycle, symbol groups at the same position in the data stream transmitted through each channel are polled.

[0163] For example, the polling order can satisfy any one of the following:

[0164] Poll the data stream transmitted through the channels with even serial numbers first, and then poll the data stream transmitted through the channels with odd serial numbers; or

[0165] First poll the data stream transmitted by the channel with odd sequence numbers, and then poll the data stream transmitted by the channel with even sequence numbers; or

[0166] Poll the data stream transmitted by the channel in ascending or descending order of sequence numbers; or

[0167] Divide the channels into two parts according to the sequence numbers, the first part and the second part including the same number of channels, first poll the data streams transmitted by the channels with even sequence numbers in the first part and the data streams transmitted by the channels with odd sequence numbers in the second part, and then poll the data streams transmitted by the channels with odd sequence numbers in the first part and the data streams transmitted by the channels with even sequence numbers in the second part; or

[0168] The channels are divided into two parts according to the sequence numbers. The first part and the second part include the same number of channels. The data streams transmitted by the channels with odd sequence numbers in the first part and the data streams transmitted by the channels with even sequence numbers in the second part are polled first, and then the data streams transmitted by the channels with even sequence numbers in the first part and the data streams transmitted by the channels with odd sequence numbers in the second part are polled.

[0169] In possible implementations of the above-mentioned polling sequence, when polling data streams transmitted by some channels in the first part and data streams transmitted by some channels in the second part, the method may be to first poll the data streams transmitted by some channels in the first part and then poll the data streams transmitted by some channels in the second part. Alternatively, when polling data streams transmitted by some channels in the first part and data streams transmitted by some channels in the second part, the method may be to first poll the data stream transmitted by one channel in the first part, then poll the data stream transmitted by one channel in the second part, then continue to poll the data stream transmitted by another channel in the first part, and then poll the data stream transmitted by another channel in the second part, until all the data streams transmitted by some channels in the first part and some channels in the second part have been polled.

[0170] In the method provided in the embodiment of the present application, the transmitting end performs multiplexing based on symbol groups including symbols. In this way, even if a burst error of multiple consecutive bits occurs in the output data stream obtained during the transmission process, after the receiving end performs demultiplexing based on the symbol group, the burst error of multiple consecutive bits will only affect a smaller number of symbols. That is, the number of symbols affected by the burst error of multiple consecutive bits in the data stream multiplexed based on the symbol group is much smaller than the number of symbols affected by the burst error of multiple consecutive bits in the data stream multiplexed based on the bit, thereby improving the error correction performance and system reliability.

[0171] Figures 3(a) and 3(b) illustrate an embodiment in which a codeword group includes two different codewords, the number of channels of the input data stream is 8, and the number of channels of the output data stream is 1. The method of this embodiment can also be used in other scenarios where the ratio of the number of channels of the input data stream to the number of channels of the output data stream is 8:1, even for codeword groups including two different codewords. Examples thereof will not be given here one by one.

[0172] Figure 3(a) is a schematic diagram of interleaving and offsetting multiple codewords included in a codeword group. The codeword group in Figure 3(a) includes codeword A and codeword B, and codeword A and codeword B come from different encoders. The minimum data unit included in codeword A and codeword B is a symbol. After symbol-based interleaving, codeword A and codeword B output data through 8 channels. This interleaving belongs to multi-mixed multi-interleaving, that is, multiple codewords are interleaved to obtain multiple interleaved data streams. The identifier Opq in each box in Figure 3(a) indicates that the current symbol belongs to codeword O, and the transmission sequence number in the channel with sequence number p is q. In this embodiment of the application, the data continuously output through the channel is the data stream. For all the symbols included in the codewords in the codeword group, for example, codeword A and codeword B both include 544 symbols, any two adjacent symbols in any channel from lane 0 to lane 7 come from different codewords in the same codeword group, that is, any two consecutive symbols in any channel come from different codewords in the same codeword group. Adjacent in the embodiment of the application refers to adjacent positions and there is no gap. For example, the two symbols A.1.0 and B.1.0 output through lane 1 come from codewords A and B, respectively. On lane 1, A.1.0 and B.1.0 are located adjacently, with no gap between them. When data from codewords A and B is output through lane 1, the two consecutive symbols A.1.0 and B.1.0 come from codewords A and B, respectively. After encoding, codewords A and B each contain L1*544 symbols, where L1 is an integer greater than or equal to 1. The symbols in each codeword are interleaved and output through the eight lanes (lanes 0 to 7), with each lane outputting L1*136 symbols. L1*68 symbols come from codeword A, and L1*68 symbols come from codeword B. In lanes 0 to 7, the channels with even serial numbers output the same order of symbols from the codeword group, the channels with odd serial numbers output the same order of symbols from the codeword group, and the channels with even serial numbers output a different order of symbols from the channels with odd serial numbers.For example, taking any two even-numbered lanes as an example, the symbols included in lanes 4 and 6 are both from codeword A and codeword B in the codeword group. After codeword A and codeword B are interleaved, the symbols output through lane 4 can be expressed as A.4.0->B.4.0->A.4.1->B.4.1->A.4.2->B.4.2->A.4.3->…->A.4.67->B.4.67. After codeword A and codeword B are interleaved, the symbols output through lane 6 can be expressed as A.6.0->B.6.0->A.6.1->B.6.1->A.6.2->B.6.2->A.6.3->…->A.6.67->B.6.67. After codeword A and codeword B are interleaved, the order of the symbols output through lane 4 and the order of the symbols output through lane 6 are both ABABAB. Taking two lanes with odd sequence numbers as an example, the symbols included in lane 1 and lane 3 are both from codeword A and codeword B in the codeword group. After codeword A and codeword B are interleaved, the symbols output through lane 1 can be expressed as B.1.0->A.1.0->B.1.1->A.1.1->B.1.2->A.1.2->B.1.3->…->B.1.67->A.1.67. After codeword A and codeword B are interleaved, the symbols output through lane 3 can be expressed as B.3.0->A.3.0->B.3.1->A.3.1->B.3.2->A.3.2->B.3.3->…->B.3.67->A.3.67. After codeword A and codeword B are interleaved, the order of the symbols output through lane 1 and the order of the symbols output through lane 3 are both BABAB. The present application embodiment uses some symbols as examples for illustration, and does not further illustrate symbols exceeding the number shown. Based on FIG3(a) and the above content, the symbols output by the channels with even sequence numbers and the channels with odd sequence numbers come from the same codeword group, but the order of the symbols is different.

[0173] The transmitter can offset the interleaved data stream. For example, the scenario shown in Figure 3(a) delays the transmission of data output from each of the four channels, lane 1, lane 3, lane 5, and lane 7, with the delay being an odd number of symbol lengths, such as 137 symbol lengths. When the RS symbol length is 10 bits, the data output from each of lanes 1, lane 3, lane 5, and lane 7 is delayed by 10 bits. Alternatively, when the RS symbol length is 10 bits, the data output from each of lanes 1, lane 3, lane 5, and lane 7 is delayed by 1370 bits. The transmitter can also delay the transmission of data output from channels with even sequence numbers, but this example is not given here. By delaying data transmission by an odd number of symbols, not only can the order of symbols output from any two channels be identical, but the interleaving depth can also be increased to enhance the ability to correct burst errors. For example, by delaying the transmission of each channel with an odd sequence number by 137 symbols, the original 2*RS symbol multiplexing can be converted to 4*RS symbol multiplexing. That is, any four symbols in the channel used to transmit the output data stream come from four different codewords, rather than any four symbols from two different codewords. Taking the example of a codeword consisting of 544 symbols encoded by the same encoder each time, among the four consecutive symbols B.0.68, A.0.69, B.1.0, and A.1.0 in the delayed muxed lane, A.1.0 and A.0.69 are the outputs of the same encoder twice, and B.1.0 and B.0.68 are the outputs of the same encoder twice, that is, the four symbols come from four different codewords. Taking the example of a lane with an odd sequence number delayed by 137 symbols, the boundary of the symbol identified by B.1.0 in lane 1 is aligned with the boundary of the symbol identified by B.0.68 in lane 0, and the boundary of the symbol identified by A.1.0 in lane 1 is aligned with the boundary of the symbol identified by A.0.69 in lane 0. The boundary of the symbol identified by B.3.0 in lane 3 is aligned with the boundary of the symbol identified by B.6.68 in lane 6, and the boundary of the symbol identified by A.3.0 in lane 3 is aligned with the boundary of the symbol identified by A.6.69 in lane 6. The boundary of the symbol identified by B.5.0 in lane 5 is aligned with the boundary of the symbol identified by B.2.68 in lane 2, and the boundary of the symbol identified by A.5.0 in lane 5 is aligned with the boundary of the symbol identified by A.2.69 in lane 2.The boundary of the symbol identified by B.7.0 in lane 7, which is sent later, is aligned with the boundary of the symbol identified by B.4.68 in lane 4. The boundary of the symbol identified by A.7.0 in lane 7, which is sent later, is aligned with the boundary of the symbol identified by A.4.69 in lane 4. After the shift, the order of the symbols output by any channel is the same as BABABABA. The alignment methods of the remaining symbols are not described one by one here.

[0174] In another possible implementation, even-numbered lanes in lanes 0 through 7 are delayed. After the shift, the symbols output by any lane in lanes 0 through 7 are in the order ABABAB. The pattern for delaying even-numbered lanes is similar to that for odd-numbered lanes. For details, see Figure 3(a) above and will not be repeated here.

[0175] Figure 3(b) is a schematic diagram of multiplexing the offset data stream in Figure 3(a) to obtain a data stream. Figure 3(b) is an example of a symbol group including 2 symbols, and the 2 symbols included in the symbol group are respectively from codeword B and codeword A. In the embodiment of the present application, the symbol group including 2 symbols can also be called a symbol pair, or the 2 symbols from different codewords are called a symbol pair. The order of the codewords from which the symbols included in any symbol group in Figure 3(b) come is the same, and they are all in the order of BA, that is, taking a symbol group as an example, the symbols from codeword B in the symbol group are arranged continuously after the symbols from codeword A. In the process of polling lanes 0 to lane 7 to obtain symbol groups, the transmitter polls each of the 8 channels in the order of serial numbers from small to large in each cycle to obtain the symbol group at the same position of each channel. The 8 symbol groups obtained in one cycle are continuously output to the muxed lane according to the order of the serial numbers of the channels to which they belong. Each cycle is processed according to the polling method described above until all symbol groups in the codeword group output are polled. The following uses two cycles as an example to illustrate the specific polling method: Lane 0 includes the symbol group of B.0.68 and A.0.69, Lane 1 includes the symbol group of B.1.0 and A.1.0, Lane 2 includes the symbol group of B.2.68 and A.2.69, Lane 3 includes the symbol group of B.3.0 and A.3.0, Lane 4 includes the symbol group of B.4.68 and A.4.69, Lane 5 includes the symbol group of B.5.0 and A.5.0, Lane 6 includes the symbol group of B.6.68 and A.6.69, and Lane 7 includes the symbol group of B.7.0 and A.7.0. These are the symbol groups in the same position in the symbol groups of Lanes 0 to Lane 7, respectively. The above eight symbol groups are output through the muxed lanes in the order of the lane numbers in which they are output. For example, the symbols output in the muxed lanes in sequence can be expressed as: B.0.68->A.0.69->B.1.0->A.1.0->B.2.68->A.2.69->B.3.0->A.3.0->B.4.68->A.4.69->B.5.0->A.5.0->B.6.68->A.6.69->B.7.0->A.7.0.The symbol group including B.0.69 and A.0.70 in lane 0, the symbol group including B.1.1 and A.1.1 in lane 1, the symbol group including B.2.69 and A.2.70 in lane 2, the symbol group including B.3.1 and A.3.1 in lane 3, the symbol group including B.4.69 and A.4.70 in lane 4, the symbol group including B.5.1 and A.5.1 in lane 5, the symbol group including B.6.69 and A.6.70 in lane 6 and the symbol group including B.7.1 and A.7.1 in lane 7 are symbol groups in the same position among the symbol groups output through lanes 0 to lane 7. The eight symbol groups output in the muxed lanes, following symbol A.7.0, are represented as follows: B.0.69->A.0.70->B.1.1->A.1.1->B.2.69->A.2.70->B.3.1->A.3.1->B.4.69->A.4.70->B.5.1->A.5.1->B.6.69->A.6.70->B.7.1->A.7.1. Any eight consecutive symbol groups in the muxed lane output come from eight different lanes.

[0176] Figures 4(a) and 4(b) illustrate an embodiment in which a codeword group includes two different codewords, the number of channels of the input data stream is 16, and the number of channels of the output data stream is 2. The method of this embodiment can also be used in other scenarios where the ratio of the number of channels of the input data stream to the number of channels of the output data stream is 16:2, even for codeword groups including two different codewords. Examples thereof will not be given here one by one.

[0177] Figure 4(a) illustrates the interleaving and offsetting of multiple codewords within a codeword group. The meanings of the codeword groups, symbols, and labels within each box in Figure 4(a) can be found in the relevant descriptions in Figure 3(a). Any two adjacent symbols in any lane from lanes 0 to 15 come from different codewords within the same codeword group. Similarly, any two consecutive symbols in any lane come from different codewords within the same codeword group. The meanings of adjacent and consecutive in Figure 4(a) can be found in the relevant descriptions in Figure 3(a). Codeword A and codeword B in Figure 4(a) contain L2*544 symbols, where L2 is an integer greater than or equal to 1. After interleaving, the symbols within each codeword are output through the 16 lanes from lanes 0 to 15, with each channel outputting L2*68 symbols. L2*34 symbols come from codeword A and L2*34 symbols come from codeword B. This interleaving is a multi-mix-multi interleaving scheme, meaning that multiple codewords are interleaved to generate multiple data streams. In lane 0 to lane 15, the order of symbols of different codewords from the codeword group output by the channels with even serial numbers is the same, the order of symbols of different codewords from the codeword group output by the channels with odd serial numbers is the same, and the order of symbols output by the channels with even serial numbers is different from the order of symbols output by the channels with odd serial numbers. For example: after codeword A and codeword B are interleaved, the order of symbols output by the channels with even serial numbers is both in the order of ABABAB. After codeword A and codeword B are interleaved, the order of symbols output by the channels with odd serial numbers is both in the order of BABABA. The embodiments of the present application are described using some symbols as an example, and no more examples are given for symbols greater than the number shown in the figure.

[0178] The transmitter can offset the interleaved streams. For example, it can delay the data output by each of the eight lanes (lane 1, lane 3, lane 5, lane 7, lane 9, lane 11, lane 13, and lane 15) by an odd number of symbol lengths, such as 69. If the RS symbol length is 10 bits, the data output by each of lanes (lane 1, lane 3, lane 5, lane 7, lane 9, lane 11, lane 13, and lane 15) is delayed by 10 bits. Alternatively, if the RS symbol length is 10 bits, the data output by each of lanes (lane 1, lane 3, lane 5, lane 7, lane 9, lane 11, lane 13, and lane 15) is delayed by 690 bits. By delaying data transmission by an odd number of symbols, not only can the order of symbols output from any two channels be identical, but the interleaving depth can also be increased to enhance the ability to correct burst errors. For example, by delaying the transmission of each channel with an odd sequence number by 69 symbols, the multiplexing of 2*RS symbols can be converted to 4*RS symbols. That is, the channels used to transmit the output data stream now have any four symbols from four different codewords, rather than any four symbols from two different codewords. For example, in the case of a codeword consisting of 544 symbols encoded by the same encoder each time, the four consecutive symbols B.0.34, A.0.35, B.1.0, and A.1.0 in muxed lane 0 after delayed transmission have A.1.0 and A.0.35 encoded twice by the same encoder, and B.1.0 and B.0.35 encoded twice by the same encoder, meaning that the four symbols come from four different codewords. Taking the example of a lane with an odd sequence number delayed by 69 symbols, the boundary of the symbol identified by B.1.0 in lane 1 is aligned with the boundary of the symbol identified by B.0.34 in lane 0, and the boundary of the symbol identified by A.1.0 in lane 1 is aligned with the boundary of the symbol identified by A.0.35 in lane 0. The boundary of the symbol identified by B.3.0 in lane 3 is aligned with the boundary of the symbol identified by B.6.34 in lane 6, and the boundary of the symbol identified by A.3.0 in lane 3 is aligned with the boundary of the symbol identified by A.6.35 in lane 6. The boundary of the symbol identified by B.5.0 in lane 5 is aligned with the boundary of the symbol identified by B.2.34 in lane 2, and the boundary of the symbol identified by A.5.0 in lane 5 is aligned with the boundary of the symbol identified by A.2.35 in lane 2.The boundary of the symbol identified by B.7.0 in lane 7 that is delayed is aligned with the boundary of the symbol identified by B.12.34 in lane 12, and the boundary of the symbol identified by A.7.0 in lane 7 that is delayed is aligned with the boundary of the symbol identified by A.12.35 in lane 12. The boundary of the symbol identified by B.11.0 in lane 11 that is delayed is aligned with the boundary of the symbol identified by B.4.34 in lane 4, and the boundary of the symbol identified by A.11.0 in lane 11 that is delayed is aligned with the boundary of the symbol identified by A.4.35 in lane 4. The boundary of the symbol identified by B.13.0 in lane 13 that is delayed is aligned with the boundary of the symbol identified by B.10.34 in lane 10, and the boundary of the symbol identified by A.13.0 in lane 13 that is delayed is aligned with the boundary of the symbol identified by A.10.35 in lane 10. The boundary of the symbol identified by B.15.0 in lane 15, which is sent later, is aligned with the boundary of the symbol identified by B.8.34 in lane 8. The boundary of the symbol identified by A.15.0 in lane 15, which is sent later, is aligned with the boundary of the symbol identified by A.8.35 in lane 8. The boundary of the symbol identified by B.9.0 in lane 9, which is sent later, is aligned with the boundary of the symbol identified by B.14.34 in lane 14. The boundary of the symbol identified by A.9.0 in lane 9, which is sent later, is aligned with the boundary of the symbol identified by A.14.35 in lane 14. The order of the symbols output by any lane after the shift is the same as BABABABA. The alignment methods of the remaining symbols are not described one by one here.

[0179] In another possible implementation, even-numbered lanes in lanes 0 through 15 are delayed. After the shift, the symbols output by any lane in lanes 0 through 15 are in the order ABABAB. The pattern for delaying even-numbered lanes is similar to that for odd-numbered lanes. For details, see Figure 4(a) above and will not be repeated here.

[0180] Figure 4(b) illustrates how the shifted data streams in Figure 4(a) are multiplexed to produce two data streams. Figure 4(b) illustrates a symbol group consisting of two symbols, one from codeword B and the other from codeword A. The codewords from which the symbols in any symbol group in Figure 4(b) originate are all ordered in the same order, BA. That is, within a symbol group, symbols from codeword B are followed by symbols from codeword A. When the transmitter polls lanes 0 to 15 to obtain symbol groups, it can divide lanes 0 to 15 into two parts: lanes 0 to 7 and lanes 8 to 15. For each part, each cycle polls each of the eight lanes in ascending order of sequence number to obtain the symbol group at the same position in each lane. The eight symbol groups acquired within a cycle are sequentially output to a muxed lane in the order of their lane numbers. For example, the symbol group from lanes 0 to 7 is output through muxed lane 0, and the symbol group from lanes 8 to 15 is output through muxed lane 1. Each cycle is processed in the same round-robin fashion until all symbol groups in that section have been polled.

[0181] The following describes the specific polling method using two cycles as an example: for the symbol groups output through lanes 0 to lane 7, lane 0 includes the symbol group of B.0.34 and A.0.35, lane 1 includes the symbol group of B.1.0 and A.1.0, lane 2 includes the symbol group of B.2.34 and A.2.35, lane 3 includes the symbol group of B.3.0 and A.3.0, lane 4 includes the symbol group of B.4.34 and A.4.35, lane 5 includes the symbol group of B.5.0 and A.5.0, lane 6 includes the symbol group of B.6.34 and A.6.35, and lane 7 includes the symbol group of B.7.0 and A.7.0. These are the symbol groups in the same position in the symbol groups output through lanes 0 to lane 7. The above eight symbol groups are output in sequence through muxed lane 0 in the order of the lane numbers in which they are output. For example, the symbols output in muxed lane 0 in sequence can be expressed as: B.0.34->A.0.35->B.1.0->A.1.0->B.2.34->A.2.35->B.3.0->A.3.0->B.4.34->A.4.35->B.5.0->A.5.0->B.6.34->A.6.35->B.7.0->A.7.0. The symbol group including B.0.35 and A.0.36 in lane 0, the symbol group including B.1.1 and A.1.1 in lane 1, the symbol group including B.2.35 and A.2.36 in lane 2, the symbol group including B.3.1 and A.3.1 in lane 3, the symbol group including B.4.35 and A.4.36 in lane 4, the symbol group including B.5.1 and A.5.1 in lane 5, the symbol group including B.6.35 and A.6.36 in lane 6 and the symbol group including B.7.1 and A.7.1 in lane 7 are symbol groups in the same position among the symbol groups output through lanes 0 to lane 7. The eight symbol groups output in the same position after symbol A.7.0 in muxed lane 0 are represented as follows: B.0.35->A.0.36->B.1.1->A.1.1->B.2.35->A.2.36->B.3.1->A.3.1->B.4.35->A.4.36->B.5.1->A.5.1->B.6.35->A.6.36->B.7.1->A.7.1. Any eight consecutive symbol groups output by muxed lane 0 come from lanes 0 through 7.For the symbol groups output through lanes 8 to lane 15, the symbol group including B.8.34 and A.8.35 in lane 8, the symbol group including B.9.0 and A.9.0 in lane 9, the symbol group including B.10.34 and A.10.35 in lane 10, the symbol group including B.11.0 and A.11.0 in lane 11, the symbol group including B.12.34 and A.12.35 in lane 12, the symbol group including B.13.0 and A.13.0 in lane 13, the symbol group including B.14.34 and A.14.35 in lane 14 and the symbol group including B.15.0 and A.15.0 in lane 15 are the symbol groups in the same position in the symbol groups output through lanes 8 to lane 15. The above eight symbol groups are output in sequence through muxed lane 1 in the order of the lane numbers in which they are output. For example, the symbols output in muxed lane 1 can be expressed as: B.8.34->A.8.35->B.9.0->A.9.0->B.10.34->A.10.35->B.11.0->A.11.0->B.12.34->A.12.35->B.13.0->A.13.0->B.14.34->A.14.35->B.15.0->A.15.0. The symbol group including B.8.35 and A.8.36 in lane 8, the symbol group including B.9.1 and A.9.1 in lane 9, the symbol group including B.10.35 and A.10.36 in lane 10, the symbol group including B.11.1 and A.11.1 in lane 11, the symbol group including B.12.35 and A.12.36 in lane 12, the symbol group including B.13.1 and A.13.1 in lane 13, the symbol group including B.14.35 and A.1436 in lane 14 and the symbol group including B.15.1 and A.15.1 in lane 15 are symbol groups in the same position among the symbol groups output through lanes 8 to lane 15. In muxed lane 1, the eight symbol groups output in the same position after symbol A.15.0 are sequentially represented as follows: B.8.35->A.8.36->B.9.1->A.9.1->B.10.35->A.10.36->B.11.1->A.11.1->B.12.35->A.12.36->B.13.1->A.13.1->B.14.35->A.14.36->B.15.1->A.15.1. Any eight consecutive symbol groups output by muxed lane 1 come from eight different lanes.

[0182] Figures 5(a) and 5(b) illustrate an embodiment using two codeword groups, each including two different codewords, with the number of channels of the input data stream being 32 and the number of channels of the output data stream being 4. For scenarios with multiple codeword groups and a ratio of the number of channels of the input data stream to the number of channels of the output data stream being 8:1, the method of this embodiment can be referred to and will not be further illustrated here.

[0183] Figure 5(a) is a schematic diagram of interleaving and offsetting multiple codewords included in two codeword groups. In this embodiment, the first codeword group includes codeword A and codeword B, and the second codeword group includes codeword C and codeword D. After interleaving, codeword A and codeword B included in the first codeword group output multiple symbols through lanes 0 to lane 15. After interleaving, codeword C and codeword D included in the second codeword group output multiple symbols through lanes 16 to lane 31. Taking the first codeword group including codeword A and codeword B as an example, after interleaving, the order of symbols output by codeword A and codeword B through channels with even serial numbers is ABABAB, and after interleaving, the order of symbols output by codeword A and codeword B through channels with odd serial numbers is BABABA. The meaning of the symbols, adjacent meanings, and continuous meanings in each box in Figure 5(a) can be found in the corresponding content of Figure 3(a). The specific method for outputting multiple symbols of codeword A and codeword B through lanes 0 to 15 after interleaving can be seen in the corresponding content of Figure 4(a). The number of symbols contained in codeword A and codeword B in Figure 5(a) is L3*544, where L3 is an integer greater than or equal to 1. The symbols included in each codeword of the first codeword group are output through 16 channels, lanes 0 to 15, after interleaving. The number of symbols output by each channel is L3*68, of which L3*34 symbols come from codeword A and L3*34 symbols come from codeword B. The number of symbols contained in codeword C and codeword D in Figure 5(a) is L4*544, where L4 is an integer greater than 0. The symbols included in each codeword of the second codeword group are interleaved and output through 16 channels, lanes 16 to 31. Each channel outputs L4*68 symbols, of which L4*34 symbols come from codeword C and L4*34 symbols come from codeword D. The interleaving shown in Figure 5(a) is multi-mix-multi interleaving. For details, please refer to the corresponding content in Figure 3(a). Taking codewords C and D included in the second codeword group as an example, after interleaving, the symbols of codewords C and D are output through channels with even sequence numbers in the order CDCDCD. After interleaving, the symbols of codewords C and D are output through channels with odd sequence numbers in the order DCDCDC.This embodiment of the present application uses a portion of the symbols obtained by interleaving multiple codewords included in the second codeword group as an example, and does not further illustrate a greater number of symbols than shown. For example, taking lanes 16 and 28, two even-numbered lanes from lanes 16 to 31, as an example, the symbols included in lanes 16 and 28 are both from codeword C and codeword D included in the codeword group. After codewords C and D are interleaved, the symbols output via lane 16 are expressed as: C.16.0 -> D.16.0 -> C.16.1 -> D.16.1 -> C.16.2 -> D.16.2 -> C.16.3 -> … D.16.33 -> C.16.33. After codewords C and D are interleaved, the symbols output via lane 28 are expressed as: C.28.0 -> D.28.0 -> C.28.1 -> D.28.1 -> C.28.2 -> D.28.2 -> C.28.3 -> … C.28.33 -> D.28.33. Taking two odd-numbered lanes as an example, the symbols in lanes 19 and 27 are both from codewords C and D in the codeword group. After codeword C and codeword D are interleaved and output through lane 19, the symbols can be expressed as D.19.0->C.19.0->D.19.1->C.19.1->D.19.2->C.19.2->D.19.3->…->D.19.33->C.19.33. After codeword C and codeword D are interleaved and output through lane 27, the symbols can be expressed as D.27.0->C.27.0->D.27.1->C.27.1->D.27.2->C.27.2->D.27.3->…->D.27.33->C.27.33. For any codeword group, the symbols output through the 16 lanes are in a different order from the symbols output by the lanes with odd sequence numbers.

[0184] The transmitter may offset the interleaved stream, for example, by delaying the transmission of symbols output by one or more channels in lanes 0 to 31, with the delay depth being an odd number of symbol lengths. For example, if the RS symbol length is 10 bits, the data output by each lane in lanes 1, lane 3, lane 5, lane 7, lane 9, lane 11, lane 13, lane 15, lane 17, lane 19, lane 21, lane 23, lane 25, lane 27, lane 29, and lane 31 may be delayed by 10 bits for transmission, so that the boundaries of codeword A, codeword B, codeword C, and codeword D output by lanes 0 to 31, including the symbols, are aligned, as shown by the dotted lines in FIG5(a). By delaying data transmission by an odd number of symbols, the order of symbols in any two channels output after interleaving of symbols from the same codeword group can be made identical. For example, in lanes 0 to 15, where the odd-numbered channels are delayed by one symbol, the boundaries of the delayed symbol identified by B.1.0 in lane 1 are aligned with the boundaries of the symbol identified by B.0.0 in lane 0, and the boundaries of the delayed symbol identified by A.1.0 in lane 1 are aligned with the boundaries of the symbol identified by A.0.1 in lane 0. The boundaries of the delayed symbol identified by B.3.0 in lane 3 are aligned with the boundaries of the symbol identified by B.6.0 in lane 6, and the boundaries of the delayed symbol identified by A.3.0 in lane 3 are aligned with the boundaries of the symbol identified by A.6.1 in lane 6. The boundary of the symbol identified by B.5.0 in lane 5 that is delayed is aligned with the boundary of the symbol identified by B.2.0 in lane 2, and the boundary of the symbol identified by A.5.0 in lane 5 that is delayed is aligned with the boundary of the symbol identified by A.2.1 in lane 2. The boundary of the symbol identified by B.7.0 in lane 7 that is delayed is aligned with the boundary of the symbol identified by B.12.0 in lane 12, and the boundary of the symbol identified by A.7.0 in lane 7 that is delayed is aligned with the boundary of the symbol identified by A.12.1 in lane 12. The boundary of the symbol identified by B.11.0 in lane 11 that is delayed is aligned with the boundary of the symbol identified by B.4.0 in lane 4, and the boundary of the symbol identified by A.11.0 in lane 11 that is delayed is aligned with the boundary of the symbol identified by A.4.1 in lane 4.The boundary of the symbol identified by B.13.0 in lane 13 that is delayed is aligned with the boundary of the symbol identified by B.10.0 in lane 10, and the boundary of the symbol identified by A.13.0 in lane 13 that is delayed is aligned with the boundary of the symbol identified by A.10.1 in lane 10. The boundary of the symbol identified by B.15.0 in lane 15 that is delayed is aligned with the boundary of the symbol identified by B.8.0 in lane 8, and the boundary of the symbol identified by A.15.0 in lane 15 that is delayed is aligned with the boundary of the symbol identified by A.8.1 in lane 8. The boundary of the symbol identified by B.9.0 in lane 9 that is delayed is aligned with the boundary of the symbol identified by B.14.0 in lane 14, and the boundary of the symbol identified by A.9.0 in lane 9 that is delayed is aligned with the boundary of the symbol identified by A.14.1 in lane 14. Taking the example of delaying the transmission of odd-numbered lanes in lanes 16 to 31 by one symbol, the boundary of the symbol identified by D.17.0 in lane 17 that is delayed is aligned with the boundary of the symbol identified by D.16.0 in lane 16, and the boundary of the symbol identified by C.17.0 in lane 17 that is delayed is aligned with the boundary of the symbol identified by C.16.1 in lane 16. The boundary of the symbol identified by D.19.0 in lane 19 that is delayed is aligned with the boundary of the symbol identified by D.22.0 in lane 22, and the boundary of the symbol identified by C.19.0 in lane 19 that is delayed is aligned with the boundary of the symbol identified by C.22.1 in lane 22. The boundary of the symbol identified by D.21.0 in lane 21, which is sent late, is aligned with the boundary of the symbol identified by D.18.0 in lane 18. The boundary of the symbol identified by C.21.0 in lane 21, which is sent late, is aligned with the boundary of the symbol identified by C.18.1 in lane 18. The boundary of the symbol identified by D.23.0 in lane 23, which is sent late, is aligned with the boundary of the symbol identified by D.28.0 in lane 28. The boundary of the symbol identified by C.23.0 in lane 23, which is sent late, is aligned with the boundary of the symbol identified by C.28.1 in lane 28. The boundary of the symbol identified by D.27.0 in lane 27, which is sent late, is aligned with the boundary of the symbol identified by D.20.0 in lane 20. The boundary of the symbol identified by C.27.0 in lane 27, which is sent late, is aligned with the boundary of the symbol identified by C.20.1 in lane 20.The boundary of the symbol identified by D.29.0 in lane 29, which is sent late, is aligned with the boundary of the symbol identified by D.26.0 in lane 26. The boundary of the symbol identified by C.29.0 in lane 29, which is sent late, is aligned with the boundary of the symbol identified by C.26.1 in lane 26. The boundary of the symbol identified by D.31.0 in lane 31, which is sent late, is aligned with the boundary of the symbol identified by D.24.0 in lane 24. The boundary of the symbol identified by C.31.0 in lane 31, which is sent late, is aligned with the boundary of the symbol identified by C.24.1 in lane 24. The boundary of the symbol identified by D.25.0 in lane 25, which is sent late, is aligned with the boundary of the symbol identified by D.30.0 in lane 30. The boundary of the symbol identified by C.25.0 in lane 25, which is sent late, is aligned with the boundary of the symbol identified by C.30.1 in lane 30. The order of symbols output by any lane from lane 16 to lane 31 after the shift is the order of DCDCDC.

[0185] Figure 5(b) is a schematic diagram of multiplexing the offset data streams in Figure 5(a) to obtain four data streams. The offset data streams output by lanes 0 to lane 31 in Figure 5(b) include symbols from the first codeword group output by lanes 0 to lane 15 and symbols from the second codeword group output by lanes 16 to lane 31. The four data streams obtained after multiplexing at the transmitter are output through muxed lane 0, muxed lane 1, muxed lane 2, and muxed lane 3, respectively. The multiplexing method used for the multiplexed data streams output by any of the above muxed lanes 0, muxed lane 1, muxed lane 2, and muxed lane 3 is the same. The following will illustrate the method for obtaining the data stream output by muxed lane 1 as an example. The transmitter polls the symbol groups output by lanes 0 through 15 and lanes 16 through 31 to obtain the data stream output by any muxed lane. Taking the data stream output by muxed lane 1 as an example, the two-cycle polling method involves obtaining the symbol groups output by these eight lanes in the order: lane 4 -> lane 20 -> lane 5 -> lane 21 -> lane 6 -> lane 22 -> lane 7 -> lane 23. The symbol group including B.4.0 and A.4.1 in lane 4, the symbol group including D.20.0 and C.20.1 in lane 20, the symbol group including B.5.0 and A.5.0 in lane 5, the symbol group including D.21.0 and C.21.0 in lane 21, the symbol group including B.6.0 and A.6.1 in lane 6, the symbol group including D.22.0 and C.22.1 in lane 22, the symbol group including B.7.0 and A.7.0 in lane 7 and the symbol group including D.23.0 and C.23.0 in lane 23 are the symbol groups in the same position in the 8 channels selected above.The above eight symbol groups are first output through muxed lane 1 in the order of lane 4 -> lane 20 -> lane 5 -> lane 21 -> lane 6 -> lane 22 -> lane 7 -> lane 23 (Figure 5(b) shows the order of the lanes to which the eight symbol groups output by muxed lane 1 in the first cycle belong). For example, the 16 symbols from the above eight channels output in sequence from muxed lane 1 can be expressed as: B.4.0 -> A.4.1 -> D.20.0 -> C.20.1 -> B.5.0 -> A.5.0 -> D.21.0 -> C.21.0 -> B.6.0 -> A.6.1 -> D.22.0 -> C.22.1 -> B.7.0 -> A.7.0 -> D.23.0 -> C.23.0. The symbol group including B.4.1 and A.4.2 in lane 4, the symbol group including D.20.1 and C.20.2 in lane 20, the symbol group including B.5.1 and A.5.1 in lane 5, the symbol group including D.21.1 and C.21.1 in lane 21, the symbol group including B.6.1 and A.6.2 in lane 6, the symbol group including D.22.1 and C.22.2 in lane 22, the symbol group including B.7.1 and A.7.1 in lane 7 and the symbol group including D.23.1 and C.23.1 in lane 23 are another symbol group in the same position in the 8 channels selected above. Muxed lane 1 sequentially outputs the 16 symbols in the second cycle following symbol C.23.1, consisting of another 8-symbol group located in the same position. Specifically, this is: B.4.1->A.4.2->D.20.1->C.20.2->B.5.1->A.5.1->D.21.1->C.21.1->B.6.1->A.6.2->D.22.1->C.22.2->B.7.1->A.7.1->D.23.1->C.23.1. Any consecutive 8-symbol group output by muxed lane 1 comes from lanes 4, 20, 5, 21, 6, 22, 7, and 23. The multiplexing method of the symbols output by other muxed lanes can be found in the multiplexing method of the symbols output by muxed 1, which will not be repeated here.Due to the offset, the symbols from the data stream of the same codeword group are output in the same order. Based on the symbol group, the symbols output by any four channels from the first codeword group and the symbols output by any channel from the second codeword group are multiplexed to obtain the symbols output by any muxed lane channel. In this way, the symbols from any codeword are output in the muxed lane channel with an interval of 3 symbols. For example, the symbols output by any muxed lane channel are ordered in the order of BADCBADC.

[0186] In another possible implementation, the even-numbered lanes in lanes 0 to 15 are delayed. After the shift, the symbols output by any lane in lanes 0 to 15 are in the order ABABAB, and the symbols output by any lane in lanes 16 to 31 are in the order CDCDCD. The pattern for delaying the transmission of even-numbered lanes is similar to that for odd-numbered lanes; see Figure 5(a) for details. After delaying the transmission of even-numbered lanes, the symbols output by any muxed lane are in the order ABCDABCD. See Figure 5(b) for details on the multiplexing method.

[0187] Figure 6 shows an embodiment of a codeword group including 4 different codewords, 16 channels of the input data stream, and 8 channels of the output data stream. For the codeword group including 4 codewords, the scenario where the ratio of the number of channels of other input data streams to the number of channels of the output data stream is 2:1 can refer to the method of this embodiment, and will not be explained one by one here. For the meaning of adjacent, continuous, symbol group, symbol, and codeword group in Figure 6, please refer to the corresponding content of Figure 3(a). The symbol group in Figure 6 includes 4 symbols, and the 4 symbols come from different codewords. The symbol group including 4 symbols in the embodiment of the present application can also be called symbol quartet, or 4 symbols from different codewords can be called symbol quartet. The symbol group multiplexing including 4 symbols can also be called RS symbol quartet multiplexing. Lane 0 to lane 15 in Figure 6 output the interleaved data stream of codeword A, codeword B, codeword C, and codeword D. The symbols output by lanes 0 through 15 are ordered in the order ABCDABCD. Any symbol group consists of four symbols from different codewords. The order of the codewords from which the symbols in any symbol group originate can be expressed as ABCD. The transmitter multiplexes the interleaved symbols output by lanes 0 through 15 based on the symbol group, obtaining a data stream output by muxed lanes 0 through 7. That is, the data stream obtained by multiplexing any two lanes from lanes 0 through 15 is output through a single muxed lane. Figure 6 uses the example of multiplexing the symbols output by an odd-numbered lane and an even-numbered lane to obtain a single muxed lane. Since the symbols in any lane are ordered in the order ABCDABCD, any two lanes can be selected, such as the symbols output by an odd-numbered lane and another odd-numbered lane, or the symbols output by an even-numbered lane and another even-numbered lane. The following example illustrates how to obtain a symbol output by muxed lane 4 by multiplexing the symbols output by lane 8 and the symbols output by lane 9 based on the symbol group.The symbol group consisting of A.8.0, B.8.0, C.8.0, and D.8.0 in lane 8 and the symbol group consisting of A.9.0, B.9.0, C.9.0, and D.9.0 in lane 9 are in the same position. The transmitter obtains these two symbol groups in the first cycle and outputs them to muxed lane 4 in the order of lane 8 -> lane 9. Specifically, this can be expressed as: A.8.0 -> B.8.0 -> C.8.0 -> D.8.0 -> A.9.0 -> B.9.0 -> C.9.0 -> D.9.0. The symbol group consisting of A.8.1, B.8.1, C.8.1, and D.8.1 in lane 8 and the symbol group consisting of A.9.1, B.9.1, C.9.1, and D.9.1 in lane 9 are in the same position. The transmitter obtains these two symbol groups in the second cycle and, after outputting the symbol D.9.0 in the first cycle, outputs them to muxed lane 4 in the order lane 8 -> lane 9. Specifically, this can be expressed as: A.8.1 -> B.8.1 -> C.8.1 -> D.8.1 -> A.9.1 -> B.9.1 -> C.9.1 -> D.9.1. Following this polling order, the symbol groups in the same position in the two lanes are polled each cycle and passed through the muxed lanes in sequence. This polling cycle continues for multiple cycles until all symbols in the codeword group are output. The two consecutive symbol groups output by any muxed lane come from different lanes. The codewords to which the symbols output by any muxed lane belong are sorted in the order of ABCDABCD.

[0188] Figure 7 is a flow chart illustrating another data processing method provided in an embodiment of the present application. The method illustrated in Figure 7 is performed by a receiving end, which may be a module or chip acting as a transmitter. The module or chip may be located in a host or optical module. The data processing performed by the receiving end in this embodiment of the present application may be the reverse of the data processing performed by the transmitting end in Figure 2 and related embodiments.

[0189] 701. The receiving end obtains an input data stream.

[0190] For example, the input data stream obtained by the receiving end is the output data stream obtained by the transmitting end. The input data stream obtained by the receiving end can be the data stream output by the transmitting end through b channels, where b is an integer greater than or equal to 1. The receiving end can also use the data stream transmitted through b channels as the input data stream. For example, the input data stream obtained by the receiving end can be the data stream transmitted by the muxed lane in Figure 3(b), the data stream transmitted by muxed lane 0 and muxed lane 1 in Figure 4(b), the data stream transmitted by muxed lane 0 to muxed lane 3 in Figure 5(b), or the data stream transmitted by muxed lane 0 to muxed lane 7 in Figure 6. The specific meanings of the symbols, symbol groups, codewords, and codeword groups in the input data stream obtained by the receiving end can be found in the corresponding contents of the relevant embodiments of Figures 2 to 6 and will not be repeated here.

[0191] 702. The receiving end demultiplexes the input data stream based on the symbol groups to obtain an output data stream.

[0192] For example, the symbol groups used for demultiplexing at the receiving end have the same meaning as the symbol groups used for multiplexing at the transmitting end. For details, please refer to the corresponding contents in the relevant embodiments of Figures 2 to 6 and will not be repeated here. The output data stream obtained by the receiving end can be output via a channels, where a is an integer greater than or equal to 2 and a>b. The symbol group includes multiple symbols, and the data included in the multiple symbols comes from different codewords at the transmitting end. The output data stream obtained by the receiving end is used to obtain the same codeword as the codeword of the transmitting end. Specifically, the receiving end deinterleaves the output data stream to obtain the same codeword as the transmitting end, or the receiving end offsets and deinterleaves the output data stream to obtain the same codeword as the transmitting end. The above-mentioned deinterleaving process is the inverse process of the interleaving process at the transmitting end. Both deinterleaving and interleaving at the transmitting end are performed at the symbol granularity and will not be repeated here. After obtaining the same codeword as the transmitting end, the receiving end can further decode the codeword. The specific decoding code type is the same as the encoding code type used by the transmitting end and will not be repeated here.

[0193] For example, for 200GBASE-R and 400GBASE-R, the input data stream transmitted over the same channel includes symbols from different codewords in the same codeword group, and two adjacent symbols are from different codewords. The symbol groups included in the input data stream transmitted over the same channel have the same ordering of symbols from different codewords, and the number of symbols included in a symbol group is the same as the number of codewords, for example, a symbol group includes 2 symbols. For 800GBASE-R, the input data stream transmitted over the same channel includes symbols from different codewords in two codeword groups, and two adjacent symbols are from different codewords. The input data stream transmitted over the same channel includes two adjacent symbol groups from different codeword groups, and for symbol groups from the same codeword group, the symbol ordering of different codewords from the same codeword group within the symbol group is the same, for example, a symbol group includes 2 symbols. For 1.6TGBASE-R, the input data stream transmitted over the same channel includes symbols from different codewords in the same codeword group, and two adjacent symbols are from different codewords. The symbols from different codewords within a symbol group included in the input data stream transmitted over the same channel have the same ordering, and the number of symbols in a symbol group is the same as the number of codewords, for example, a symbol group includes four symbols. The meanings of "continuous" and "adjacent" in this embodiment can be found in the corresponding embodiment of Figure 2 .

[0194] For example, the receiver obtains one of the b channels of the input data stream. The receiver sequentially obtains a1 symbol groups from the data stream output by this channel and distributes them to a1 channels in the a channels used to obtain the output data stream, where a1 is an integer less than or equal to a. After completing the previous round of distribution, the receiver obtains a2 symbol groups following the a1 symbol groups from the data stream output by this channel and distributes them to the a1 channels, where a2 has the same value as a1. For all channels in the b channels, the distribution principle for each channel is the same as that for the single channel, and will not be repeated here.

[0195] Optionally, the receiving end may perform an offset operation on the a data streams obtained after demultiplexing to restore the a data streams that are the same as the a data streams obtained after interleaving at the transmitting end. The specific method of the offset operation at the receiving end can refer to the method of the offset operation adopted by the transmitting end, that is, delayed transmission. The difference between the offset operation at the receiving end and the offset operation at the transmitting end is that the channel where the data offset at the receiving end is located is different from the channel where the data offset at the transmitting end is located. For example: if the transmitting end delays the transmission of data transmitted by the channel with an odd serial number by N bits, and N is an integer greater than or equal to 1, then the receiving end delays the transmission of data transmitted by the channel with an even serial number by N bits. If the transmitting end delays the transmission of data transmitted by the channel with an even serial number by N bits, then the receiving end delays the transmission of data transmitted by the channel with an odd serial number by N bits.

[0196] In the method provided in the embodiment of the present application, the transmitting end performs multiplexing based on symbol groups including symbols. In this way, even if a burst error of multiple consecutive bits occurs in the output data stream obtained during the transmission process, after the receiving end performs demultiplexing based on the symbol group, the burst error of multiple consecutive bits will only affect a smaller number of symbols. That is, the number of symbols affected by the burst error of multiple consecutive bits in the data stream multiplexed based on the symbol group is much smaller than the number of symbols affected by the burst error of multiple consecutive bits in the data stream multiplexed based on the bit, thereby improving the error correction performance and system reliability.

[0197] Figures 8(a) and 8(b) illustrate an embodiment in which a codeword group includes two different codewords, symbols of one codeword group are demultiplexed, the number of channels in the input data stream is 1, and the number of channels in the output data stream is 8. This embodiment also applies to codeword groups that include two different codewords and where the ratio of the number of channels in the input data stream to the number of channels in the output data stream is 1:8. These examples will not be further explained here. The receiving end in Figures 8(a) and 8(b) can be a 200GBASE-R-based host or chip.

[0198] The input data stream of Figure 8(a) is the output data stream of Figure 3(b). The meanings of the identifiers, symbols, symbol groups, and codeword groups in the boxes of Figure 8(a) can be found in the corresponding contents of Figures 3(b) and 3(a). The meanings of "continuous" and "adjacent" in this embodiment are the same as those in the embodiment corresponding to Figure 2 and are not further described here. The symbols in Figure 8(a) are from the codeword group including codeword A and codeword B. The receiver obtains eight consecutive symbol groups from the muxed lanes in units of two symbols and outputs them sequentially to lanes 0 to 7. For example, the symbol group consisting of B.0.68 and A.0.69 is output through lane 0, the symbol group consisting of B.1.0 and A.1.0 is output through lane 1, the symbol group consisting of B.2.68 and A.2.69 is output through lane 2, the symbol group consisting of B.3.0 and A.3.0 is output through lane 3, the symbol group consisting of B.4.68 and A.4.69 is output through lane 4, the symbol group consisting of B.5.0 and A.5.0 is output through lane 5, the symbol group consisting of B.6.68 and A.6.69 is output through lane 6, and the symbol group consisting of B.7.0 and A.7.0 is output through lane 7. After demultiplexing the eight symbol groups, the receiver continues to extract the eight consecutive symbol groups following the symbol group containing B.7.0 and A.7.0 from the multiplexed lanes and outputs them sequentially to lanes 0 through 7. This continues until all symbols from codeword A and codeword B in the multiplexed lanes have been demultiplexed and sent to lanes 0 through 7.

[0199] The receiver delays the data stream output by the even-numbered lanes in Figure 8(a) by 137 symbols, as shown in Figure 8(b). After lanes 0, 2, 4, and 6 are delayed by 137 symbols, B.0.68 in lane 0, A.1.68 in lane 1, B.2.68 in lane 2, A.3.68 in lane 3, B.4.68 in lane 4, A.5.68 in lane 5, B.6.68 in lane 6, and A.7.68 in lane 7 are located in the same position in lanes 0 through 7, aligning the symbol boundaries of these eight symbols. The symbol group including B.0.68 and A.0.69 in lane 0, the symbol group including B.1.69 and A.1.68 in lane 1, the symbol group including B.2.68 and A.2.69 in lane 2, the symbol group including B.3.69 and A.3.68 in lane 3, the symbol group including B.4.68 and A.4.69 in lane 4, the symbol group including B.5.69 and A.5.68 in lane 5, the symbol group including B.6.68 and A.6.69 in lane 6 and the symbol group including B.7.69 and A.7.68 in lane 7 are the symbol groups in the same position in lanes 0 to lane 7. The dashed boxes in Figure 8(b) represent the symbols from codewords A and B received by the receiver. Specifically, after the receiver has acquired L1*544 symbols starting with A.0.0, B.1.0, A.2.0, B.3.0, A.4.0, B.5.0, A.6.0, and B.7.0, and L1 is an integer greater than or equal to 1, the order of the symbols in the solid and dashed boxes in Figure 8(b) is shown. The receiver can then perform deinterleaving and decoding. After delayed transmission, symbols in the same position in any two adjacent channels come from different codewords, and two consecutive symbols in any channel come from different codewords. This delayed transmission allows the receiver to restore the same symbol ordering as that obtained by the transmitter, enabling subsequent decoders to complete decoding operations.

[0200] Figures 9(a) and 9(b) illustrate an embodiment in which a codeword group includes two different codewords, symbols of one codeword group are demultiplexed, the number of channels in the input data stream is 2, and the number of channels in the output data stream is 16. This embodiment also applies to codeword groups that include two different codewords and where the ratio of the number of channels in the input data stream to the number of channels in the output data stream is 2:16. These examples will not be further explained here. The receiving end in Figures 9(a) and 9(b) can be a 400GBASE-R-based host or chip.

[0201] The input data stream of Figure 9(a) is the output data stream of Figure 4(b). The meanings of the identifiers, symbols, symbol groups, and codeword groups in the boxes of Figure 9(a) can be found in the corresponding contents of Figures 4(b) and 4(a). The meanings of "continuous" and "adjacent" in this embodiment are the same as those in the corresponding embodiment of Figure 2 and are not repeated here. The symbols in Figure 9(a) are from the codeword group including codeword A and codeword B. The receiver obtains eight consecutive symbol groups from muxed lane 0 and muxed lane 1, using symbol groups consisting of two symbols as units, and sequentially outputs them to lanes 0 through 15. Specifically, the receiver obtains eight consecutive symbol groups from muxed lane 0, using symbol groups consisting of two symbols as units, and sequentially outputs them to lanes 0 through 7. The receiver obtains eight consecutive symbol groups from muxed lane 1, using symbol groups consisting of two symbols as units, and sequentially outputs them to lanes 8 through 15. The above 16 symbol groups are demultiplexed to the same positions of the corresponding channels in lanes 0 to 15. For example, the symbol group including B.0.34 and A.0.35 is output through lane 0, the symbol group including B.1.0 and A.1.0 is output through lane 1, the symbol group including B.2.34 and A.2.35 is output through lane 2, the symbol group including B.3.0 and A.3.0 is output through lane 3, the symbol group including B.4.34 and A.4.35 is output through lane 4, the symbol group including B.5.0 and A.5.0 is output through lane 5, the symbol group including B.6.34 and A.6.35 is output through lane 6, and the symbol group including B.7.0 and A.7.0 is output through lane 7. After completing the demultiplexing of the above-mentioned 8 consecutive symbol groups from muxed lane 0, the receiving end continues to obtain and demultiplex the 8 consecutive symbol groups from muxed lane 1. The symbol group including B.8.34 and A.8.35 is output through lane 8, the symbol group including B.9.0 and A.9.0 is output through lane 9, the symbol group including B.10.34 and A.10.35 is output through lane 10, the symbol group including B.11.0 and A.11.0 is output through lane 11, the symbol group including B.12.34 and A.12.35 is output through lane 12, the symbol group including B.13.0 and A.13.0 is output through lane 13, the symbol group including B.14.34 and A.14.35 is output through lane 14, and the symbol group including B.15.0 and A.15.0 is output through lane 15.After the receiving end completes the demultiplexing of the above 16 symbol groups, the symbol group including B.0.34 and A.0.35, the symbol group including B.1.0 and A.1.0, the symbol group including B.2.34 and A.2.35, the symbol group including B.3.0 and A.3.0, the symbol group including B.4.34 and A.4.35, the symbol group including B.5.0 and A.5.0, the symbol group including B.6.34 and A.6.35, the symbol group including B.7.0 and A.7.0 The symbol group including B.8.34 and A.8.35, the symbol group including B.9.0 and A.9.0, the symbol group including B.10.34 and A.10.35, the symbol group including B.11.0 and A.11.0, the symbol group including B.12.34 and A.12.35, the symbol group including B.13.0 and A.13.0, the symbol group including B.14.34 and A.14.35 and the symbol group including B.15.0 and A.15.0 are the symbol groups with the same position in the corresponding channels in lane 0 to lane 15. The receiver continues to obtain the eight consecutive symbol groups after A.7.0 of muxed lane 0 and the eight consecutive symbol groups after A.15.0 of muxed lane 1, and demultiplexes them according to the above method until all symbols from codeword A and codeword B output by muxed lane 0 and muxed lane 1 are demultiplexed to lanes 0 to 15.

[0202] The receiving end delays the data stream output by the channel with the even sequence number in Figure 9(a) by 69 symbols and sends it, as shown in Figure 9(b). Lane 0, lane 2, lane 4, lane 6, lane 8, lane 10, lane 12, and lane 14 in lanes 0 to 15 are delayed by 69 symbols. Then, lane 0's B.0.34, lane 1's A.1.34, lane 2's B.2.34, lane 3's A.3.34, lane 4's B.4.34, lane 5's A.5.34, lane 6's B.6.34, lane 7's A.7.34, lane 8's B.8.34, lane 9's A.9.34, lane 10's B.10.34, lane 11's A.11.34, lane 12's B.12.34, lane 13's A.13.34, lane 14's B.14.34 in lane 14 and A.15.34 in lane 15 are symbols at the same position in lanes 0 to 15, that is, the symbol boundaries of the above 16 symbols are aligned. Lane 0 includes the symbol group of B.0.34 and A.0.35, lane 1 includes the symbol group of B.1.35 and A.1.34, lane 2 includes the symbol group of B.2.34 and A.2.35, lane 3 includes the symbol group of B.3.35 and A.3.34, lane 4 includes the symbol group of B.4.34 and A.4.35, lane 5 includes the symbol group of B.5.35 and A.5.34, lane 6 includes the symbol group of B.6.34 and A.6.35, lane 7 includes the symbol group of B.7.35 and A.7.34, lane 8 includes the symbol group of B.8.34 and A.8.35, lane 9 includes the symbol group of B.9.35 and A.9.34, lane The symbol group including B.10.34 and A.10.35 in lane 10, the symbol group including B.11.35 and A.11.34 in lane 11, the symbol group including B.12.34 and A.12.35 in lane 12, the symbol group including B.13.35 and A.13.34 in lane 13, the symbol group including B.14.34 and A.14.35 in lane 14, and the symbol group including B.15.35 and A.15.34 in lane 15 are the symbol groups in the same position in lanes 0 to lane 15.The dashed boxes in Figure 9(b) represent the symbols from codewords A and B received by the receiver. Specifically, after the receiver has received L2*544 symbols starting with A.0.0, B.1.0, A.2.0, B.3.0, A.4.0, B.5.0, A.6.0, B.7.0, A.8.0, B.9.0, A.10.0, B.11.0, A.12.0, B.13.0, A.14.0, and B.15.0, L2 is an integer greater than or equal to 1. The symbols in the solid and dashed boxes are arranged as shown in Figure 9(b). The receiver can then perform deinterleaving and decoding. After delayed transmission, symbols in the same position in any two adjacent channels come from different codewords, and two consecutive symbols in any channel come from different codewords. This delayed transmission allows the receiver to restore the same symbol ordering as that obtained by the transmitter, enabling subsequent decoders to complete decoding operations.

[0203] Figures 10(a) and 10(b) illustrate an embodiment in which a codeword group includes two different codewords, symbols of the two codeword groups are demultiplexed, the number of channels in the input data stream is 4, and the number of channels in the output data stream is 32. This embodiment can also be used in scenarios where there are multiple codeword groups and the ratio of the number of channels in the input data stream to the number of channels in the output data stream is 4:32. These examples will not be further explained here. The receiving end in Figures 10(a) and 10(b) can be an 800GBASE-R host or chip.

[0204] The input data stream of Figure 10(a) is the output data stream in Figure 5(b). The meanings of the identifiers, symbols, symbol groups, and codeword groups in the boxes of Figure 10(a) can be found in the corresponding contents of Figures 5(b) and 5(a). The meanings of continuous and adjacent in this embodiment are the same as those in the embodiment corresponding to Figure 2 and are not repeated here. The symbols in Figure 10(a) come from two codeword groups. The first of the two codeword groups includes codeword A and codeword B, and the second of the two codeword groups includes codeword C and codeword D. The receiving end obtains 8 consecutive symbol groups from each channel in units of symbol groups including 2 symbols from muxed lane 0 to muxed lane 3 and outputs them in sequence to lanes 0 to lane 31. Specifically, the receiving end obtains 8 consecutive symbol groups from muxed lane 0 in units of symbol groups including 2 symbols and outputs them in sequence to 4 channels in lanes 0 to lane 15 and 4 channels in lanes 16 to lane 31; the receiving end obtains 8 consecutive symbol groups from muxed lane 1 in units of symbol groups including 2 symbols and outputs them in sequence to 4 channels in lanes 0 to lane 15 and 4 channels in lanes 16 to lane 31; the receiving end obtains 8 consecutive symbol groups from muxed lane 2 in units of symbol groups including 2 symbols and outputs them in sequence to 4 channels in lanes 0 to lane 15 and 4 channels in lanes 16 to lane 31. The receiver extracts eight consecutive symbol groups from muxed lane 3, each consisting of two symbols, and sequentially outputs them to the four lanes in lanes 0 through 15 and the four lanes in lanes 16 through 31. These 32 symbol groups are demultiplexed to the same positions in the corresponding lanes in lanes 0 through 31. Any lane in muxed lanes 0 through 31 is demultiplexed to eight completely different lanes.For example: the symbol group including B.0.0 and A.0.0 is output through lane 0, the symbol group including B.1.0 and A.1.0 is output through lane 1, the symbol group including B.2.0 and A.2.0 is output through lane 2, the symbol group including B.3.0 and A.3.0 is output through lane 3, the symbol group including B.4.0 and A.4.0 is output through lane 4, the symbol group including B.5.0 and A.5.0 is output through lane 5, the symbol group including B.6.0 and A.6.0 is output through lane 6, the symbol group including B.7.0 and A.7.0 is output through lane 7, the symbol group including B.8.0 and A.8.0 is output through lane 8, the symbol group including B.9.0 and A.9.0 is output through lane 9, and the symbol group including B.10.0 and A.10.0 is output through lane The symbol group including B.11.0 and A.11.0 is output through lane 10, the symbol group including B.11.0 and A.11.0 is output through lane 11, the symbol group including B.12.0 and A.12.0 is output through lane 12, the symbol group including B.13.0 and A.13.0 is output through lane 13, the symbol group including B.14.0 and A.14.0 is output through lane 14, and the symbol group including B.15.0 and A.15.0 is output through lane 15. The above 16 symbol groups including symbols from the first codeword group are located in the same position in each channel in lanes 0 to 15, that is, the boundaries of the symbols included in the above 16 symbol groups are aligned. The demultiplexing process of the symbols from the second codeword group is the same as the demultiplexing process of the symbols from the first codeword group, and will not be repeated here. The receiving end performs demultiplexing according to the above method until all symbols from the first codeword group and the second codeword group output by muxe lane 0 to muxed lane 3 are demultiplexed to lane 0 to lane 31.

[0205] The receiving end delays the data stream output by the channel with the even sequence number in Figure 10(a) by one symbol and sends it, as shown in Figure 10(b). Lane 0, lane 2, lane 4, lane 6, lane 8, lane 10, lane 12, lane 14, lane 16, lane 18, lane 20, lane 22, lane 24, lane 26, lane 28, and lane 30 in lanes 0 to 31 are delayed by one symbol. Then, B.0.0 in lane 0, A.1.0 in lane 1, B.2.0 in lane 2, A.3.0 in lane 3, B.4.0 in lane 4, A.5.0 in lane 5, B.6.0 in lane 6, A.7.0 in lane 7, B.8.0 in lane 8, A.9.0 in lane 9, B.10.0 in lane 10, A.11.0 in lane 11, and B.12.0 in lane 12 are transmitted. lane 12, B.12.0, lane 13, A.13.0, lane 14, B.14.0, lane 15, A.15.0, lane 16, D.16.0, lane 17, C.17.0, lane 18, D.18.0, lane 19, C.19.0, lane 20, D.20.0, lane 21, C.21.0, lane 22, D.22.0, lane 23, C.23.0, lane 24, D.24.0, lane 25, C.25.0, lane 26, D.26.0, lane C.27.0, lane 28, C.28.0, lane 29, C.29.0, lane 30, D.30.0, lane C.31.0 in 31 refers to the symbols in the same position in lanes 0 to 31, that is, the symbol boundaries of the above 32 symbols are aligned. The symbol group including the above 32 symbols is the symbol group in the same position in each channel in lanes 0 to 31.The dotted boxes in Figure 10(b) represent the symbols from codeword A, codeword B, codeword C, and codeword D that the receiver has received, i.e., from A.0.0, B.1.0, A.2.0, B.3.0, A.4.0, B.5.0, A.6.0, B.7.0, A.8.0, B.9.0, A.10.0, B.11.0, A.12.0, B.13.0, A.14.0, B.15.0, C.16.0, D.17.0, C.18.0, D.19.0, C.20.0, D.21 After the receiver obtains L3*544 symbols starting with C.0, C.22.0, D.23.0, C.24.0, D.25.0, C.26.0, D.27.0, C.28.0, D.29.0, C.30.0, and D.31.0, L3 is an integer greater than or equal to 1, as shown in the order of the symbols in the solid and dashed boxes in Figure 10(b), and the receiver can then perform deinterleaving and decoding. After delayed transmission, symbols in the same position in any two adjacent channels come from different codewords, and two consecutive symbols in any channel come from different codewords. Through this delayed transmission, the receiver restores the same symbol ordering as that obtained by the transmitter, allowing the subsequent decoder to complete the decoding operation.

[0206] Figure 11 illustrates an embodiment in which a codeword group includes four different codewords, symbols from one codeword group are demultiplexed, the number of input data stream channels is 8, and the number of output data stream channels is 16. This embodiment also applies to codeword groups containing four codewords, and other scenarios where the ratio of the number of input data stream channels to the number of output data stream channels is 8:16. This embodiment will not be further illustrated here. The receiving end in Figure 11 can be a host or chip based on 1.6TGBASE-R.

[0207] The input data stream in Figure 11 is the output data stream in Figure 6 . The meanings of the identifiers, symbols, symbol groups, and codeword groups in the blocks in Figure 11 can be found in the corresponding sections of Figure 6 . The meanings of "continuous" and "adjacent" in this embodiment are the same as those in the embodiment corresponding to Figure 2 and are not further elaborated here. The symbols in Figure 11 come from a codeword group consisting of four codewords: codeword A, codeword B, codeword C, and codeword D. The receiving end obtains two consecutive symbol groups from muxed lane 0 to muxed lane 7, respectively, in units of symbol groups including 4 symbols, from each channel and outputs them in sequence to lane 0 to lane 15. Specifically, the receiving end obtains two consecutive symbol groups from muxed lane 0 in units of symbol groups including 4 symbols, and outputs them in sequence to lane 0 and lane 1; the receiving end obtains two consecutive symbol groups from muxed lane 1 in units of symbol groups including 4 symbols, and outputs them in sequence to lane 2 and lane 3; the receiving end obtains two consecutive symbol groups from muxed lane 2 in units of symbol groups including 4 symbols, and outputs them in sequence to lane 4 and lane 5; the receiving end obtains two consecutive symbol groups from muxed lane 3 in units of symbol groups including 4 symbols, and outputs them in sequence to lane 6 and lane 7. The receiver demultiplexes muxed lanes 4 through 7 into lanes 8 through 15 using the same method as described above for demultiplexing muxed lanes 0 through 3 into lanes 0 through 7. After demultiplexing, the codewords from which the symbols in any symbol group in lanes 0 through 15 originate are all in the same order: ABCD. The receiver then restores the same symbol order as the transmitter, enabling subsequent decoders to complete decoding operations.

[0208] The hardware structure shown in Figure 12(a) includes a reconciliation sublayer (RS), a physical coding sublayer (PCS), two physical medium attachment (PMA) layers, an inner forward error correction (Inner FEC) layer, a physical medium dependent (PMD) layer, and a medium. A medium independent interface (MII) is provided between the RS and PCS, and an attachment unit interface (AUI) is provided between the two PMA layers. A medium dependent interface (MDI) is provided between the PMD layer and the medium. The medium can be a coaxial cable, optical fiber, or twisted pair cable. The data processing method in the embodiments corresponding to Figures 2 to 11 above can be implemented by the PMA layer between the PCS and AUI in Figure 12(a). The AUI transmits 200G / lane data, and the PMA layer between the AUI and the Inner FEC can transparently transmit the data transmitted by the AUI. Alternatively, the PMA between the AUI and the inner FEC layer in Figure 12(a) employs the data processing methods described in the embodiments corresponding to Figures 2 to 11 . In this case, the AUI transmits 100G / lane data, and the PMA layer between the AUI and the inner FEC can employ bit-level multiplexing or transparent transmission of PCS data. The RS provides mapping processing for data transmitted between the Media Access Control (MAC) layer and the PCS. The PCS encodes or decodes the transmitted data according to a specific encoding scheme. The PCS may also implement the FEC layer. The FEC layer implements FEC processing. The PMD layer converts data signals from the PAM layer to signals transmitted on a specific media medium. The AUI can be used to transmit data at different rates between PMAs. The MII is used to transmit data at different rates between the RS and the PCS, including various data types such as 50G / GMII, 100G / GMII, and 200G / 400G / GMII. The transmitted data will go through RS->PCS->PMA layer->PMA layer->Inner FEC layer->PMD layer->media output; the received data will go through media->PMD layer->Inner FEC layer->PMA layer->PMA layer->PCS->RS output.The hardware structure shown in Figure 12(b) includes the RS, PCS, PMA layer, inner FEC layer, PMD layer, and medium layer, arranged in sequence. An MII is provided between the RS and PCS. An MDI is provided between the PMD layer and the medium layer. The medium layer can be a coaxial cable, optical fiber, or twisted pair cable. The data processing methods described in the embodiments corresponding to Figures 2 to 11 above can be implemented by the PMA layer in Figure 12(b). The functions of the RS, PCS, PMA layer, inner FEC layer, PMD layer, medium layer, and MII can be found in Figure 12(a). Transmitted data passes through the RS, PCS, PMA layer, inner FEC layer, PMD layer, and medium layer for output; received data passes through the medium layer, PMD layer, inner FEC layer, PMA layer, PCS, and RS layer for output. FIG12(a) or FIG12(b) can be applied to a host or chip using 200GBASE-R, 400GBASE-R, 800GBASE-R, and 1.6TBASE-R.

[0209] Figures 13(a) to 13(c) illustrate possible implementations of the data processing methods described in the embodiments corresponding to Figures 2 to 11 for deployment in a single chip scenario. FEC encoding or FEC1 encoding in Figures 13(a) to 13(c) refers to the first FEC encoding (e.g., FEC encoding in PCS), FEC2 encoding refers to the second FEC encoding (e.g., inner FEC encoding), symbol grouping refers to symbol group-based multiplexing (the data processing methods described in the embodiments corresponding to Figures 2 to 6), symbol group splitting refers to symbol group-based demultiplexing (the data processing methods described in the embodiments corresponding to Figures 7 to 11), FEC decoding or FEC1 decoding refers to the first FEC decoding (e.g., FEC decoding in PCS), and FEC2 decoding refers to the second FEC decoding (e.g., inner FEC decoding). Symbol grouping may also include the offsets described in the embodiments corresponding to Figures 2 to 6; symbol group splitting may also include the offsets described in the embodiments corresponding to Figures 7 to 11. TX represents the transmitting side, and RX represents the receiving side. Figures 14(a) to 14(f) illustrate possible implementations of the data processing methods in the embodiments corresponding to Figures 2 to 11 for deployment in multiple chip scenarios. FEC encoding or FEC1 encoding in Figures 14(a) to 14(f) refers to the first FEC encoding (e.g., FEC encoding in PCS), FEC2 encoding refers to the second FEC encoding (e.g., inner FEC encoding), symbol group merging, symbol group merging 1, or symbol group merging 2 refer to symbol group-based multiplexing (the data processing methods in the embodiments corresponding to Figures 2 to 6), symbol group splitting, symbol group splitting 1, or symbol group splitting 2 refer to symbol group-based demultiplexing (the data processing methods in the embodiments corresponding to Figures 7 to 11), FEC decoding or FEC1 decoding refers to the first FEC decoding (e.g., FEC decoding in PCS), and FEC2 decoding refers to the second FEC decoding (e.g., inner FEC decoding). Among them, symbol group merging, symbol group merging 1 or symbol group merging 2 may also include the offset in the embodiments corresponding to Figures 2 to 6; symbol group splitting, symbol group splitting 1 or symbol group splitting 2 may also include the offset in the embodiments corresponding to Figures 7 to 11. TX represents the transmitting side, and RX represents the transmitting side. If a clock and data recovery (CDR) chip is present between the main chip and the optical module in Figures 14(a) to 14(f), the symbol group merging, symbol group merging 1 or symbol group merging 2 on the TX side are implemented in the CDR chip, and the symbol group splitting, symbol group splitting 1 or symbol group splitting 2 on the RX side are implemented in the CDR chip. The embodiments of this application will no longer give examples one by one.

[0210] As shown in FIG. 15(a), a data sending device 1500 provided by an embodiment of the present application includes a processing unit 1502 and an output unit 1503. Optionally, the data sending device 1500 further includes an acquisition unit 1501. The processing unit 1502 is used to implement the method of obtaining an output data stream in 202 in the embodiment corresponding to FIG. 2. The output unit 1503 is used to implement the output method included in 202 in the embodiment corresponding to FIG. 2. The acquisition unit 1501 is used to implement the method of 201 in the embodiment corresponding to FIG. 2. When the data sending device 1500 is used to implement the method executed by the sending end in FIGS. 3 to 6, the processing unit 1502 is used to implement the multiplexing method in the embodiments corresponding to FIGS. 3 to 6, the output unit 1503 is used to implement the method of outputting a data stream through a muxed lane in the embodiments corresponding to FIGS. 3 to 6, and the acquisition unit 1501 is used to implement one or more of the offset and interleaving methods in the embodiments corresponding to FIGS. 3 to 6.

[0211] For example, the processing unit 1502 is used to multiplex a data streams based on symbol groups to obtain b data streams, where a is an integer greater than or equal to 2, b is an integer greater than or equal to 1 and b < a. Among the b data streams, any one data stream includes multiple symbol groups, any one symbol group includes multiple symbols from different codewords, and any one symbol includes multiple bits. The output unit 1503 is used to transmit the b data streams.

[0212] Among them, the a data streams include a first data stream and a second data stream, the b data streams include a third data stream, the multiple symbol groups include a first symbol group and a second symbol group, the first symbol group and the second symbol group are consecutive in the third data stream, all symbols in the first symbol group come from the first data stream and are consecutive in the first data stream, and all symbols in the second symbol group come from the second data stream and are consecutive in the second data stream.

[0213] For example, the a data streams are based on coding, and the symbols are RS symbols. The length of the RS symbol is 10 bits.

[0214] In the implementation of 200GBASE-R, a = 8, b = 1, the number of symbols included in the symbol group is 2, and any consecutive 8 symbol groups included in the b data streams come from the 8 data streams respectively. The processing unit 1502 is further used to delay the data stream output by each channel with an odd serial number in the a data streams and send it after 136*N + 1 symbols, where N is an integer greater than or equal to 1.

[0215] In the 400GBASE-R implementation, a is equal to 16, b is equal to 2, the number of symbols included in the symbol group is 2, and any consecutive 8 symbol groups included in any data stream in the b data streams are from 8 data streams in the a data streams. The processing unit 1502 is further configured to delay the data stream output by each odd-numbered channel in the a data stream by 68*N+1 symbols, where N is an integer greater than or equal to 1.

[0216] In the 1.6TBASE-R implementation, a is equal to 16, b is equal to 8, the number of symbols included in the symbol group is 4, and any two consecutive symbol groups included in any one of the b data streams come from two data streams in the a data stream.

[0217] Based on any of the above implementations, the order of codewords to which the consecutive symbols output by the channel with any even sequence number in the a data streams belong is the same as the order of codewords to which the consecutive symbols output by the channel with any odd sequence number in the a data streams belong.

[0218] In an 800GBASE-R implementation, a is equal to 32, b is equal to 4, the number of symbols included in the symbol group is 2, any consecutive 8 symbol groups included in any data stream in the b data streams are respectively from 8 data streams in the a data stream, the 8 data streams in the a data stream include 4 data streams from a first codeword group and 4 data streams from a second codeword group, the first codeword group includes 2 codewords, the second codeword group includes 2 codewords, and the 2 codewords included in the first codeword group are different from the 2 codewords included in the second codeword group. The processing unit 1502 is further configured to delay the data stream output by each odd-numbered channel in the a data stream by 2*N+1 symbols, where N is an integer greater than or equal to 0.

[0219] In one implementation, the acquisition unit 1501 is further configured to: encode the received data to obtain K codeword groups, where K is an integer greater than or equal to 1, and the number of symbols included in any codeword in the K codeword groups is a positive integer multiple of 544; and interleave the codewords included in the K codeword groups based on the symbols to obtain the a data streams. The encoding includes feed-forward error correction (FEC) encoding.

[0220] In one implementation, the sum of the rates of the a data streams is the same as the sum of the rates of the b data streams, wherein the rate of any one of the b data streams is 200 Gbps.

[0221] As shown in Figure 15(b), a data receiving device 1510 provided in an embodiment of the present application includes an acquisition unit 1511 and a processing unit 1512. The acquisition unit 1511 is used to implement the method 701 in the embodiment corresponding to Figure 7. The processing unit 1512 is used to implement the method 702 in the embodiment corresponding to Figure 7. When the data receiving device 1510 is used to implement the method executed by the receiving end in Figures 8 to 11, the acquisition unit 15 is used to implement the embodiment corresponding to Figures 8 to 11 to obtain the input data stream through the muxe lane, and the processing unit 1513 is used to implement the demultiplexing method in the embodiment corresponding to Figures 8 to 11. Further, the processing unit 1513 is used to implement the offset method in the embodiment corresponding to Figures 8 to 11. The function performed by the unit included in the receiving device is the inverse process of the method performed by the unit included in the sending device, which will not be repeated here.

[0222] For example, the acquisition unit 1511 is used to receive b data streams, where b is an integer greater than or equal to 1, and any one of the b data streams includes multiple symbol groups, any symbol group includes multiple symbols from different codewords, and any symbol includes multiple bits; the processing unit 1512 is used to demultiplex the b data streams based on the symbol group to obtain a data stream, where a is an integer greater than or equal to 2 and a>b.

[0223] As shown in FIG. 16(a), another data sending device 1600 provided by the application embodiment includes a processor 1601 and a transmitter 1602 coupled to the processor 1601. Among them, the processor 1601 is used to implement 201 and 202 in the embodiment corresponding to FIG. 2, including the method of obtaining the output data stream. The transmitter 1602 is used to implement the output method included in 202 in the embodiment corresponding to FIG. 2. When the data sending device 1600 is used to implement the method executed by the sending end in FIGS. 3 to 6, the processor 1601 is used to implement the multiplexing method in the embodiments corresponding to FIGS. 3 to 6, and the transmitter 1602 is used to implement the method of outputting the data stream through the muxed lane in the embodiments corresponding to FIGS. 3 to 6. Optionally, the processor 1601 is further used to implement one or more of the offset and interleaving methods in the embodiments corresponding to FIGS. 3 to 6. The processor 1601 may adopt the structure of FIG. 12(a) or FIG. 12(b). The transmitter 1602 may specifically be a sending circuit or a sending interface. The data sending device 1600 may be a router, a switch or an optical module. When the data sending device 1600 is a router or a switch, the processor 1601 may be a physical layer (PHY) chip, such as the TX main chip in FIGS. 13 to 14, and the transmitter 1602 may be an optical module, such as the TX optical module in FIGS. 13 to 14. When the data sending device 1600 is an optical module, such as the TX optical module in FIGS. 13 to 14, the processor 1601 may be a processing circuit, and the transmitter 1602 may be a sending circuit.

[0224] For example, the processor 1601 is used to multiplex a data streams based on symbol groups to obtain b data streams, where a is an integer greater than or equal to 2, b is an integer greater than or equal to 1 and b < a. Among them, any one of the b data streams includes multiple symbol groups, any symbol group includes multiple symbols from different codewords, and any symbol includes multiple bits; the transmitter 1602 is used to transmit the b data streams.

[0225] In a possible implementation manner, the a data streams include a first data stream and a second data stream, the b data streams include a third data stream, the multiple symbol groups include a first symbol group and a second symbol group, the first symbol group and the second symbol group are consecutive in the third data stream, all symbols in the first symbol group come from the first data stream and are consecutive in the first data stream, and all symbols in the second symbol group come from the second data stream and are consecutive in the second data stream.

[0226] In a possible implementation manner, the a data streams are based on Reed-Solomon (RS) coding, and the symbols are RS symbols.

[0227] In a possible implementation, the length of the RS symbol is 10 bits.

[0228] In a possible implementation, a is equal to 8, b is equal to 1, the number of symbols included in the symbol group is 2, and any consecutive 8 symbol groups included in the b data streams are respectively from the 8 data streams.

[0229] In one possible implementation, the processor is further configured to delay sending the data stream output by each channel with an odd sequence number in the a data streams by L symbols, where L is equal to 136*N+1, and N is an integer greater than or equal to 1.

[0230] In one possible implementation, a is equal to 16, b is equal to 2, the number of symbols included in the symbol group is 2, and any consecutive 8 symbol groups included in any data stream in the b data streams come from 8 data streams in the a data stream.

[0231] In a possible implementation, the processor further delays the transmission of the data stream output by each channel with an odd sequence number in the a data streams by L symbols, where L is equal to 68*N+1, and N is an integer greater than or equal to 1.

[0232] In one possible implementation, a is equal to 16, b is equal to 8, the number of symbols included in the symbol group is 4, and any two consecutive symbol groups included in any one of the b data streams come from two data streams in the a data stream.

[0233] In a possible implementation, the order of codewords to which consecutive symbols output by a channel with any even sequence number in the a data streams belong is the same as the order of codewords to which consecutive symbols output by a channel with any odd sequence number in the a data streams belong.

[0234] In one possible implementation, a is equal to 32, b is equal to 4, the number of symbols included in the symbol group is 2, any consecutive 8 symbol groups included in any data stream in the b data streams are respectively from 8 data streams in the a data stream, the 8 data streams in the a data stream include 4 data streams from the first codeword group and 4 data streams from the second codeword group, the first codeword group includes 2 codewords, the second codeword group includes 2 codewords, and the 2 codewords included in the first codeword group are different from the 2 codewords included in the second codeword group.

[0235] In one possible implementation, the processor is further configured to delay sending the data stream output by each channel with an odd sequence number in the a data streams by L symbols, where L is equal to 2*N+1, and N is an integer greater than or equal to 0.

[0236] In one possible implementation, the processor is further used to: encode the received data to obtain K codeword groups, where K is an integer greater than or equal to 1, and the number of symbols included in any codeword in the K codeword groups is a positive integer multiple of 544; and interleave the codewords included in the K codeword groups based on the symbols to obtain the a data streams.

[0237] In a possible implementation, the encoding includes feed-forward error correction (FEC) encoding.

[0238] In a possible implementation, the sum of the rates of the a data streams is the same as the sum of the rates of the b data streams.

[0239] In a possible implementation, the rate of any one of the b data streams is 200 Gbps.

[0240] As shown in FIG16( b ), another data receiving device 1610 provided in an embodiment of the present application includes a receiver 1611 and a processor 1612 coupled to the receiver 1611. The receiver 1611 is configured to implement the method 701 in the embodiment corresponding to FIG7 . The processor 1612 is configured to implement the method 702 in the embodiment corresponding to FIG7 . When the data receiving device 1610 is configured to implement the method performed by the receiving end in FIG8 to FIG11 , the receiver 1611 is configured to implement the embodiments corresponding to FIG8 to FIG11 by acquiring the input data stream via the multiplexer lanes, and the processor 1612 is configured to implement the demultiplexing method in the embodiments corresponding to FIG8 to FIG11 . Furthermore, the processor 1612 is configured to implement the offset method in the embodiments corresponding to FIG8 to FIG11 . The processor 1611 may adopt the structure of FIG12( a ) or FIG12( b ). The receiver 1611 may specifically be a receiving circuit or a receiving interface. The data receiving device 1610 may be a router, a switch, or an optical module. When the data receiving device 1610 is a router or switch, the processor 1611 may be a physical layer (PHY) chip, such as the RX main chip in Figures 13 and 14, and the receiver 1612 may be an optical module, such as the RX optical module in Figures 13 and 14. When the data receiving device 1610 is an optical module, such as the RX optical module in Figures 13 and 14, the processor 1611 may be a processing circuit, and the receiver 1612 may be a receiving circuit.

[0241] For example, the receiver 1611 is configured to receive b data streams, where b is an integer greater than or equal to 1, and any one of the b data streams includes multiple symbol groups, each symbol group includes multiple symbols from different codewords, and each symbol includes multiple bits; the processor 1612 is configured to demultiplex the b data streams based on the symbol groups to obtain a data stream, where a is an integer greater than or equal to 2 and a>b. The a data stream includes a first data stream and a second data stream, the b data streams include a third data stream, the multiple symbol groups include a first symbol group and a second symbol group, the first symbol group and the second symbol group are continuous in the third data stream, all symbols in the first symbol group are from the first data stream and are continuous in the first data stream, and all symbols in the second symbol group are from the second data stream and are continuous in the second data stream.

[0242] In a possible implementation, the a data streams are RS-encoded, the symbols are RS symbols, and the length of the RS symbols is 10 bits.

[0243] Figure 17 is a structural diagram of a data processing device provided in an embodiment of the present application. The device is the device where the transmitting end provided in an embodiment of the present application is located, or the device where the receiving end provided in an embodiment of the present application is located. The device includes: a processor 1701, a memory 1702, a network interface 1703 and a bus 1704. Among them, a computer program 1705 is stored in the memory 1702, and the computer program 1705 is used to implement various application functions. The processor 1701 is used to execute the computer program 1705 to implement the data processing method provided in any of the above method embodiments. For example, the processor 1701 can be used to execute the computer program 1705 to implement the functions of the various units or structures shown in any of Figures 15 to 16 above. The processor 1701 can be a central processing unit (CPU), and the processor 1701 can also be other general-purpose processors, digital signal processors (DSP), ASICs, FPGAs, graphics processing units (GPUs) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor can be a microprocessor or any conventional processor. Memory 1702 may be volatile memory or nonvolatile memory, or may include both volatile and nonvolatile memory. Nonvolatile memory may be read-only memory (ROM), programmable ROM (PROM), erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory may be random access memory (RAM), which is used as an external cache. By way of example and not limitation, many forms of RAM are available, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link dynamic random access memory (SLDRAM), and direct rambus RAM (DR RAM).There may be multiple network interfaces 1703, and the network interfaces 1703 are used to implement communication connections (which may be wired or wireless) with other devices, such as optical modules, hosts, routers, switches, and the like.

[0244] An embodiment of the present application also provides a computer-readable storage medium, which stores instructions. When the instructions are executed on a processor, the processor executes the steps performed by the sending end or the receiving end in the above method embodiment.

[0245] An embodiment of the present application further provides a computer program product comprising instructions, which, when executed on a processor, causes the processor to execute the steps performed by the transmitting end or the receiving end in the above method embodiment.

[0246] The present application also provides a system including a transmitting end and a receiving end. The transmitting end may be the data transmitting device shown in FIG. 15(a) or FIG. 16(a) above, or the transmitting end may be configured to execute the method employed by the transmitting end in the embodiments corresponding to FIG. 2 through FIG. 6 . The receiving end may be the data receiving device shown in FIG. 15(b) or FIG. 16(b) above, or the receiving end may be configured to execute the method employed by the receiving end in the embodiments corresponding to FIG. 7 through FIG. 11 .

[0247] In the embodiments of the present application, the terms "first", "second" and "third" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance. In the embodiments of the present application, the term "at least one" refers to one or more, and "a plurality" refers to two or more. In the embodiments of the present application, the term "and / or" is merely a description of the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B may represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the related objects before and after are in an "or" relationship.

[0248] The above are merely optional embodiments of the present application, but the scope of protection of the present application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this application, and such modifications or substitutions should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A data transmission method, characterized in that: The method includes: Multiplexing a data streams based on symbol groups to obtain b data streams, where a is an integer greater than or equal to 2, b is an integer greater than or equal to 1 and b < a. Among the b data streams, any one data stream includes multiple symbol groups, any one symbol group includes multiple symbols from different codewords, and any one symbol includes multiple bits; Transmitting the b data streams.

2. The method according to claim 1, characterized in that The a data streams include a first data stream and a second data stream, the b data streams include a third data stream, the multiple symbol groups include a first symbol group and a second symbol group, the first symbol group and the second symbol group are consecutive in the third data stream, all symbols in the first symbol group are from the first data stream and are consecutive in the first data stream, and all symbols in the second symbol group are from the second data stream and are consecutive in the second data stream.

3. The method according to claim 1 or 2, characterized in that The a data streams are based on Reed - Solomon (RS) coding, and the symbols are RS symbols.

4. The method according to claim 3, characterized in that The length of the RS symbol is 10 bits.

5. The method according to any one of claims 1 to 4, characterized in that: a equals 8, b equals 1, the number of symbols included in the symbol group is 2, and any consecutive 8 symbol groups included in the b data streams are respectively from the 8 data streams.

6. The method according to claim 5, characterized in that Before multiplexing the a data streams based on symbol groups to obtain b data streams, the method further includes: Delaying the data stream output from each channel with an odd serial number among the a data streams by L symbols for transmission, where L equals 136*N + 1, and N is an integer greater than or equal to 1.

7. The method according to any one of claims 1 to 4, characterized in that: a equals 16, b equals 2, the number of symbols included in the symbol group is 2, and any one data stream among the b data streams includes any consecutive 8 symbol groups respectively from 8 data streams among the a data streams.

8. The method according to claim 7, characterized in that Before multiplexing the a data streams based on symbol groups to obtain b data streams, the method further includes: Delaying the data stream output from each channel with an odd serial number among the a data streams by L symbols for transmission, where L equals 68*N + 1, and N is an integer greater than or equal to 1.

9. The method according to any one of claims 1 to 4, characterized in that: a equals 16, b equals 8, the number of symbols included in the symbol group is 4, and any one data stream among the b data streams includes any consecutive 2 symbol groups respectively from 2 data streams among the a data streams.

10. The method according to any one of claims 1 to 9, characterized in that: The sorting of the codewords to which the consecutive symbols output from any channel with an even serial number among the a data streams belong is the same as the sorting of the consecutive symbols output from any channel with an odd serial number among the a data streams.

11. The method according to any one of claims 1 to 4, characterized in that: a equals 32, b equals 4, the number of symbols included in the symbol group is 2, and any one data stream among the b data streams includes any consecutive 8 symbol groups respectively from 8 data streams among the a data streams. The 8 data streams among the a data streams include 4 data streams from a first codeword group and 4 data streams from a second codeword group. The first codeword group includes 2 codewords, the second codeword group includes 2 codewords, and the 2 codewords included in the first codeword group are different from the 2 codewords included in the second codeword group.

12. The method according to claim 11, characterized in that Before multiplexing the a data streams based on the symbol groups to obtain b data streams, the method further includes: The data stream output by each channel with an odd sequence number in the a data streams is delayed by L symbols and sent, where L is equal to 2*N+1, and N is an integer greater than or equal to 0.

13. The method according to any one of claims 1 to 12, characterized in that: The method further comprises: Encode the received data to obtain K codeword groups, where K is an integer greater than or equal to 1, and the number of symbols included in any codeword in the K codeword groups is a positive integer multiple of 544; The codewords included in the K codeword groups are interleaved based on symbols to obtain the a data streams.

14. The method according to claim 13, characterized in that The encoding includes feed-forward error correction (FEC) encoding.

15. The method according to any one of claims 1 to 14, characterized in that: The sum of the rates of the a data streams is the same as the sum of the rates of the b data streams.

16. The method according to any one of claims 1 to 15, characterized in that The rate of any one of the b data streams is 200 Gbps.

17. A data transmission method, characterized in that: The method comprises: receiving b data streams, where b is an integer greater than or equal to 1, wherein any one of the b data streams includes a plurality of symbol groups, each symbol group includes a plurality of symbols from different codewords, and each symbol includes a plurality of bits; The b data streams are demultiplexed based on symbol groups to obtain a data streams, where a is an integer greater than or equal to 2 and a>b.

18. The method according to claim 17, characterized in that The a data stream includes a first data stream and a second data stream, the b data stream includes a third data stream, the multiple symbol groups include a first symbol group and a second symbol group, the first symbol group and the second symbol group are continuous in the third data stream, all symbols in the first symbol group come from the first data stream and are continuous in the first data stream, and all symbols in the second symbol group come from the second data stream and are continuous in the second data stream.

19. The method according to claim 17 or 18, characterized in that The a data streams are based on Reed-Solomon (RS) coding, and the symbols are RS symbols.

20. The method according to claim 19, characterized in that The length of the RS symbol is 10 bits.

21. A data processing device, characterized in that: The device includes a unit for executing the method according to any one of claims 1 to 16 or a unit for executing the method according to any one of claims 17 to 20.

22. A computer program product, characterized in that The computer program product stores instructions, and when the instructions are executed on a computer, the computer is caused to execute the method according to any one of claims 1 to 16 or the method according to any one of claims 17 to 20.

23. A chip, characterized in that: The chip may include a processing circuit and an interface circuit, and the processing circuit and the interface circuit are used to implement the method of any one of claims 1 to 16 or any one of claims 17 to 20.

24. A system, characterized in that The system includes a transmitting end and a receiving end, wherein the transmitting end is used to implement the method described in any one of claims 1 to 16, and the receiving end is used to implement the method described in any one of claims 17 to 20.

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