Pixel circuit driving method, apparatus, and device

Abstract

The present application relates to the technical field of display, and discloses a pixel circuit driving method, an apparatus, and a device, capable of solving the problems in a picture display process of excessive brightness difference amplitude between a non-emission phase and an emission phase, excessively long non-emission durations, and excessive flicker perception due to non-emission or weak emission in some periods. According to the present application, flexible and non-uniform duty ratio configuration can be implemented on the duration of each level phase in each control period, for example, on the basis of whether each control period is used for anode resetting, the duration of one or more emission level phases following the anode resetting is flexibly configured, or on the basis of different reset frequencies and / or different display refresh rates, differentiated driving in a non-emission level phase is performed in a refresh frame period and a hold frame period, so that pixels can normally emit light in each control period, uniform emission in the plurality of control periods is achieved, or the emission duty ratio is increased to mitigate screen flicker, thereby realizing better display and eye protection effects.

Description

Pixel circuit driving method, device and equipment

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office on February 7, 2024, with application number 202410175957.3 and application name “Driving method, device and apparatus for pixel circuit”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of display technology, and in particular to a driving method, device and apparatus for a pixel circuit. Background Art

[0003] Currently, electronic device displays often use dimming strategies such as pulse width modulation (PWM) and direct current (DC) modulation to achieve better display effects and enhance the user's visual experience. For example, conventional technologies typically achieve consistency in the lighting cycle by controlling the error in the lighting duration within each lighting cycle within a picture frame to maintain within a certain range, thereby improving the user's visual experience.

[0004] However, since the display screen usually also includes other devices such as field-induced luminescence (EL) devices and pixel circuit anodes, or data writing, anode reset, gate reset and other operations are required in some cycles, data writing, gate reset or EL device anode reset will compress the luminescence duration in one or more cycles, or cause part or all of the luminescence current in a certain cycle to be used to charge devices (such as capacitors) rather than pixel illumination. Therefore, it will cause the brightness difference between the non-luminous and luminous stages during the picture display process to be too large, the non-luminous time to be too long, and the flickering feeling to be too strong due to no light or weak light in some cycles. Summary of the Invention

[0005] The present application provides a driving method, device and equipment for a pixel circuit, which can solve the problems of excessively large brightness difference amplitude between the non-luminous and luminous stages during the image display process, too long non-luminous time, and excessive flickering caused by non-luminous or weak luminous period in some cycles, thereby improving the visual experience of users during use.

[0006] To achieve the above objectives, this application adopts the following technical solutions:

[0007] In a first aspect, a driving method for a pixel circuit is provided, wherein a display period of the pixel circuit includes a plurality of consecutive control periods, each of the plurality of control periods includes a first level stage not used for emitting light and a second level stage used for emitting light, the plurality of control periods include a first control period, the first control period is used for anode reset, the pixel circuit includes a light-emitting control circuit and an anode reset circuit, the anode reset circuit receives an anode reset control signal, and controls the anode reset according to the first control period, the method including: detecting a screen brightness value; when the screen brightness value is less than a first brightness threshold, configuring the duration of the second level stage in the plurality of control periods according to the first control period; the light-emitting control circuit receives a light-emitting control signal, and controls the light-emitting according to the duration of the first level stage and the duration of the second level stage in the plurality of control periods.

[0008] Illustratively, the above method can be applied to a display panel, a display screen, or an electronic device including a display screen, such as a mobile phone, a tablet computer, etc., without limitation.

[0009] Illustratively, the first level stage of the control period is a high level stage, and the second level stage is a low level stage, or the first level stage is a low level stage, and the second level stage is a high level stage, without limitation.

[0010] The solution provided in the first aspect above can flexibly and non-uniformly configure the duty cycle of the level stage (such as the second level stage) used for luminescence in each control cycle according to actual conditions such as whether each control cycle is used for anode reset in scenarios where the brightness is less than the first brightness threshold, such as medium and low brightness scenarios. For example, the duration of one or more second level stages after the anode reset can be flexibly configured, so that the luminescence of multiple control cycles is uniform while ensuring that the pixels can emit light normally in each control cycle, so as to optimize screen flicker and achieve better display and eye protection effects.

[0011] As a possible implementation, the multiple control cycles also include a second control cycle, wherein the second control cycle is not used for anode reset. The configuration of the duration of the second level phase in the multiple control cycles based on the first control cycle includes: configuring the duration of the second level phase in the first control cycle to be a first duration, and configuring the duration of the second level phase in the second control cycle to be a second duration, wherein the first duration is greater than the second duration. Based on this, the duration of the second level phase in the control cycle used for anode reset can be greater than the duration of the second level phase in the control cycle not used for anode reset. This ensures uniform illumination across multiple low-level phases within the same frame, while improving the solution's applicability, compatibility, and flexibility in different scenarios.

[0012] As a possible implementation, the first control cycle includes at least one second-level phase, and the first duration includes the total duration of at least one second-level phase in the first control cycle. Based on this, various methods can be used to make the duration of the second-level phase in the control cycle used for anode reset longer than the duration of the second-level phase in the control cycle not used for anode reset. For example, the duration of the second-level phase in the display drive cycle used for anode reset can be lengthened compared to other cycles, or the number of second-level phases in multiple display drive cycles used for anode reset can be increased. This ensures uniform illumination across multiple low-level phases in the same frame, while improving the solution's applicability, compatibility, and flexibility in different scenarios.

[0013] Exemplarily, the first control cycle includes a second level phase, and the duration of the second level phase in the first control cycle is greater than the duration of the second level phase in the second control cycle.

[0014] Alternatively, illustratively, the first control cycle includes multiple second level stages, and the sum of the durations of the multiple second level stages in the first control cycle (ie, the total duration) is greater than the duration of the second level stage in the second control cycle.

[0015] As a possible implementation, the multiple control cycles further include a third control cycle, wherein the third control cycle is a control cycle subsequent to the first control cycle and is not used for anode reset. The configuration of the duration of the second level phase in the multiple control cycles based on the first control cycle includes configuring the duration of the second level phase in the third control cycle to a third duration, wherein the third duration is greater than the second duration. Based on this, the duration of the second level phase in the control cycles of the image frame that are not used for anode reset can be flexibly adjusted based on actual conditions to provide luminescence compensation, ensuring that pixels maintain normal luminescence during each control cycle and that the pixel luminescence levels within each control cycle are the same or similar, thereby ensuring uniform luminescence across multiple low-level phases within the same image frame.

[0016] As one possible implementation, the third control cycle includes at least one second-level phase, and the third duration includes the total duration of at least one second-level phase in the third control cycle. Based on this, various approaches can be used to ensure uniform illumination across multiple low-level phases within the same frame, while also improving the solution's applicability, compatibility, and flexibility in different scenarios.

[0017] As an example, the third duration is less than or equal to the first duration.

[0018] As a possible implementation, the first control period includes at least one control period; and / or the second control period includes at least one control period; and / or the third control period includes at least one control period. That is, there may be one or more first control periods, one or more second control periods, and one or more third control periods. Based on this, when there are multiple first, second, or third control periods, a similar operation of configuring the duration of the second level phase can be performed for each control period, such that the duration of the second level phase in multiple control periods used for anode reset is greater than the duration of the second level phase in control periods not used for anode reset, and / or the duration of the second level phase in the first control period after multiple anode resets is greater than the duration of the second level phase in other control periods not used for anode reset. This ensures uniform illumination across multiple low-level phases in the same frame while improving the solution's applicability, compatibility, and flexibility in different scenarios.

[0019] In a second aspect, a driving method for a pixel circuit is provided, wherein a display cycle of the pixel circuit includes a plurality of consecutive control cycles, each of the plurality of control cycles includes a first level stage not used for luminescence and a second level stage used for luminescence, the plurality of control cycles include a refresh frame period, the refresh frame period is used for display refresh and gate reset, the pixel circuit includes a light-emitting control circuit and a reset circuit, the reset circuit receives a reset control signal, and controls the gate reset and display refresh according to the refresh frame period, the method including: detecting a screen brightness value; when the screen brightness value is greater than a second brightness threshold, configuring the duration of the first level stage in the plurality of control cycles according to the display refresh rate corresponding to the light-emitting control signal and / or the reset frequency corresponding to the reset control signal; the light-emitting control circuit receives the light-emitting control signal, and controls the light-emitting according to the duration of the first level stage and the duration of the second level stage in the plurality of control cycles.

[0020] Illustratively, the above method can be applied to a display panel, a display screen, or an electronic device including a display screen, such as a mobile phone, a tablet computer, etc., without limitation.

[0021] For example, the display refresh rate is such as 120 Hz, 60 Hz, 1 Hz, etc., without limitation; the reset frequency is such as the source reset frequency or the drain reset frequency, such as 120 Hz, 240 Hz, 360 Hz, etc., without limitation.

[0022] Illustratively, the first level stage of the control period is a high level stage, and the second level stage is a low level stage, or the first level stage is a low level stage, and the second level stage is a high level stage, without limitation.

[0023] The solution provided in the second aspect above, in scenarios where the brightness is greater than the second brightness threshold, such as high-brightness scenarios, flexibly and non-uniformly configures the duty cycle of the level stage (such as the first level stage) not used for luminescence in each control cycle according to actual conditions. For example, differentiated driving of the first level stage is performed in the refresh frame period and the hold frame period based on different reset frequencies and / or different display refresh rates. On the premise of ensuring the normal operation of the pixels in each control cycle, the luminous duty cycle is improved to optimize screen flicker, and the duty cycle is kept equivalent under different display refresh rates and / or different reset frequencies, thereby avoiding flickering when the display refresh rate or reset frequency is switched, thereby achieving better display and eye protection effects.

[0024] As a possible implementation method, the above-mentioned multiple control cycles also include a holding frame cycle, and the holding frame cycle is used to maintain the display, the display refresh rate corresponding to the light-emitting control signal is a first refresh rate, and the reset frequency corresponding to the reset control signal is a first frequency. The above-mentioned configuration of the duration of the first level stage in multiple control cycles according to the display refresh rate corresponding to the light-emitting control signal and / or the reset frequency corresponding to the reset control signal includes: configuring the duration of the first level stage in the refresh frame cycle to a fourth duration, and configuring the duration of the first level stage in the holding frame cycle to a fifth duration, wherein the fifth duration is less than the fourth duration. Based on this, it is possible to ensure that the pixels operate normally in each control cycle, improve the light-emitting duty cycle to optimize screen flicker, and achieve better display and eye protection effects.

[0025] Exemplarily, the display period of the above-mentioned picture frame includes N control periods, N=F1 / F2, F1 is the source reset frequency or the drain reset frequency, F2 is the display refresh rate, and the above-mentioned configuration of the duration of the first level stage in multiple control periods according to the display refresh rate corresponding to the light-emitting control signal and / or the reset frequency corresponding to the reset control signal includes: configuring the duration of the first level stage in N-1 holding frame periods to be less than the duration of the first level stage in the refresh frame period.

[0026] As a possible implementation method, multiple control cycles also include a holding frame cycle, and the holding frame cycle is used to maintain the display, the display refresh rate corresponding to the light-emitting control signal is a second refresh rate, the second refresh rate is less than the first refresh rate, and the reset frequency corresponding to the reset control signal is a first frequency. The above configuration of the duration of the first level stage in multiple control cycles according to the display refresh rate corresponding to the light-emitting control signal and / or the reset frequency corresponding to the reset control signal includes: configuring the duration of the first level stage in the refresh frame cycle to be a fourth duration, and configuring the duration of the first level stage in the holding frame cycle to be a sixth duration, the sixth duration is less than the fourth duration, and the sixth duration is greater than the fifth duration. Based on this, it is possible not only to ensure that the pixels work normally in each control cycle and improve the light-emitting duty cycle to optimize screen flicker, but also to keep the duty cycle equivalent under different display refresh rates and / or different reset frequencies, avoiding flickering when the display refresh rate or reset frequency is switched, and achieving better display and eye protection effects.

[0027] As a possible implementation, the refresh frame period includes one control period; and / or the hold frame period includes at least one control period. That is, there may be one refresh frame period and one or more hold frame periods. Based on this, when there is one refresh frame period and one or more hold frame periods, a similar operation of configuring the duration of the first level phase can be performed for each control period, thereby achieving differentiated driving of the first level phase within the refresh frame period and the hold frame period.

[0028] Of course, in some examples, the frame period may not be maintained. In this case, the operation of configuring the duration of the first level phase may be performed only for the refresh frame period.

[0029] According to a third aspect, a display screen is provided, which includes an integrated circuit, a gate driving unit and a pixel circuit, wherein a display cycle of the pixel circuit includes a plurality of consecutive control cycles, each of the plurality of control cycles includes a first level stage not used for emitting light and a second level stage used for emitting light, the plurality of control cycles include a first control cycle, the first control cycle is used for anode reset, and the pixel circuit includes a light-emitting control circuit and an anode reset circuit; the anode reset circuit is used to: receive an anode reset control signal and control the anode reset according to the first control cycle; the integrated circuit is used to: detect a screen brightness value; and when the screen brightness value is less than a first brightness threshold, configure the duration of the second level stage in the plurality of control cycles according to the first control cycle; the light-emitting control circuit is used to: receive a light-emitting control signal and control the light-emitting according to the duration of the first level stage and the duration of the second level stage in the plurality of control cycles.

[0030] For example, in an integrated circuit such as a driver integrated circuit (IC), the gate driving unit may include but is not limited to a gate driven on array (GOA).

[0031] The solution provided in the third aspect above can flexibly and non-uniformly configure the duty cycle of the level stage (such as the second level stage) used for luminescence in each control cycle according to actual conditions such as whether each control cycle is used for anode reset in scenarios where the brightness is less than the first brightness threshold, such as medium and low brightness scenarios. It can flexibly configure the duration of one or more second level stages after the anode reset, and make the luminescence of multiple control cycles uniform while ensuring that the display screen can emit light normally in each control cycle, so as to optimize screen flicker and achieve better display and eye protection effects.

[0032] As a possible implementation, the multiple control cycles further include a second control cycle, wherein the second control cycle is not used for anode reset. The integrated circuit is configured to: configure the duration of the second level phase in the first control cycle to be a first duration, and configure the duration of the second level phase in the second control cycle to be a second duration, wherein the first duration is greater than the second duration. Based on this, the duration of the second level phase in the control cycle used for anode reset can be greater than the duration of the second level phase in the control cycle not used for anode reset. This ensures uniform illumination across multiple low-level phases within the same frame, while improving the solution's applicability, compatibility, and flexibility in different scenarios.

[0033] As a possible implementation, the first control cycle includes at least one second-level phase, and the first duration includes the total duration of at least one second-level phase in the first control cycle. Based on this, various methods can be used to make the duration of the second-level phase in the control cycle used for anode reset longer than the duration of the second-level phase in the control cycle not used for anode reset. For example, the duration of the second-level phase in the display drive cycle used for anode reset can be lengthened compared to other cycles, or the number of second-level phases in the display drive cycle used for anode reset can be increased. This ensures uniform illumination across multiple low-level phases in the same frame, while improving the solution's applicability, compatibility, and flexibility in different scenarios.

[0034] Exemplarily, the first control cycle includes a second level phase, and the duration of the second level phase in the first control cycle is greater than the duration of the second level phase in the second control cycle.

[0035] Alternatively, illustratively, the first control cycle includes multiple second level stages, and the sum of the durations of the multiple second level stages in the first control cycle (ie, the total duration) is greater than the duration of the second level stage in the second control cycle.

[0036] As a possible implementation, the multiple control cycles further include a third control cycle, where the third control cycle is a control cycle following the first control cycle and is not used for anode reset. The integrated circuit is specifically configured to configure the duration of the second level phase in the third control cycle to a third duration, where the third duration is greater than the second duration. Based on this, the duration of the second level phase in the control cycles of a frame not used for anode reset can be flexibly adjusted based on actual conditions to compensate for luminescence, ensuring that the display maintains normal luminescence during each control cycle and that the luminescence levels of each pixel on the display are the same or similar within each control cycle, thereby ensuring uniform luminescence across multiple low-level phases within the same frame.

[0037] As one possible implementation, the third control cycle includes at least one second-level phase, and the third duration includes the total duration of at least one second-level phase in the third control cycle. Based on this, various approaches can be used to ensure uniform illumination across multiple low-level phases within the same frame, while also improving the solution's applicability, compatibility, and flexibility in different scenarios.

[0038] As an example, the third duration is less than or equal to the first duration.

[0039] As a possible implementation, the first control period includes at least one control period; and / or the second control period includes at least one control period; and / or the third control period includes at least one control period. That is, there may be one or more first control periods, one or more second control periods, and one or more third control periods. Based on this, when there are multiple first, second, or third control periods, a similar operation of configuring the duration of the second level phase can be performed for each control period, such that the duration of the second level phase in multiple control periods used for anode reset is greater than the duration of the second level phase in control periods not used for anode reset, and / or the duration of the second level phase in the first control period after multiple anode resets is greater than the duration of the second level phase in other control periods not used for anode reset. This ensures uniform illumination across multiple low-level phases in the same frame while improving the solution's applicability, compatibility, and flexibility in different scenarios.

[0040] In a fourth aspect, a display screen is provided, which includes: an integrated circuit, a gate driving unit and a pixel circuit, wherein the display cycle of the pixel circuit includes multiple consecutive control cycles, each of the multiple control cycles includes a first level stage not used for emitting light and a second level stage used for emitting light, the multiple control cycles include a refresh frame period, the refresh frame period is used for display refresh and gate reset, the pixel circuit includes a light-emitting control circuit and a reset circuit; the reset circuit is used to: receive a reset control signal, and control the gate reset and display refresh according to the refresh frame period, the integrated circuit is used to: detect the screen brightness value; and when the screen brightness value is greater than the second brightness threshold, configure the duration of the first level stage in the multiple control cycles according to the display refresh rate corresponding to the light-emitting control signal and / or the reset frequency corresponding to the reset control signal; the light-emitting control circuit is used to: receive the light-emitting control signal, and control the light-emitting according to the duration of the first level stage and the duration of the second level stage in the multiple control cycles.

[0041] The solution provided in the fourth aspect above, in scenarios where the brightness is greater than the second brightness threshold, such as high-brightness scenarios, flexibly and non-uniformly configures the duty cycle of the level stage (such as the first level stage) not used for luminescence in each control cycle according to actual conditions, such as performing differentiated driving of the first level stage in the refresh frame cycle and the hold frame cycle based on different reset frequencies and / or different display refresh rates. On the premise of ensuring the normal operation of the display screen in each control cycle, the luminous duty cycle is improved to optimize screen flicker, and the duty cycle at different display refresh rates and / or different reset frequencies is kept equivalent, thereby avoiding flickering when the display refresh rate or reset frequency is switched, thereby achieving better display and eye protection effects.

[0042] As a possible implementation, the multiple control cycles further include a hold frame cycle, which is used to maintain the display. The display refresh rate corresponding to the light control signal is a first refresh rate, and the reset frequency corresponding to the reset control signal is a first frequency. The integrated circuit is specifically configured to: configure the duration of the first level phase in the refresh frame cycle to a fourth duration, and configure the duration of the first level phase in the hold frame cycle to a fifth duration, wherein the fifth duration is less than the fourth duration. Based on this, the display screen can be guaranteed to operate normally in each control cycle, the light duty cycle can be improved to optimize screen flicker, and better display and eye protection can be achieved.

[0043] As a possible implementation method, multiple control cycles also include a holding frame cycle, the holding frame cycle is used to maintain the display, the display refresh rate corresponding to the light-emitting control signal is a second refresh rate, the second refresh rate is less than the first refresh rate, the reset frequency corresponding to the reset control signal is the first frequency, and the above-mentioned integrated circuit is specifically used to: configure the duration of the first level stage in the refresh frame cycle to be the fourth duration, and configure the duration of the first level stage in the holding frame cycle to be the sixth duration, the sixth duration is less than the fourth duration, and the sixth duration is greater than the fifth duration. Based on this, it is possible not only to ensure that the pixels work normally in each control cycle and improve the light-emitting duty cycle to optimize screen flicker, but also to keep the duty cycle equivalent under different display refresh rates and / or different reset frequencies, avoid flickering when the display refresh rate or reset frequency is switched, and achieve better display and eye protection effects.

[0044] As a possible implementation, the refresh frame period includes one control period; and / or the hold frame period includes at least one control period. That is, there may be one refresh frame period and one or more hold frame periods. Based on this, when there is one refresh frame period and one or more hold frame periods, a similar operation of configuring the duration of the first level phase can be performed for each control period, thereby achieving differentiated driving of the first level phase within the refresh frame period and the hold frame period.

[0045] Of course, in some examples, the frame period may not be maintained. In this case, the operation of configuring the duration of the first level phase may be performed only for the refresh frame period.

[0046] In a fifth aspect, an electronic device is provided, which includes: a display screen for interface display; a memory for storing computer program instructions; and a processor for executing the computer program instructions to support the electronic device to implement a method in any possible implementation of the first aspect or the second aspect.

[0047] In a sixth aspect, a computer-readable storage medium is provided, on which computer program instructions are stored. When the computer program instructions are executed by a processor, the method in any possible implementation of the first aspect or the second aspect is implemented.

[0048] In a seventh aspect, a computer program product comprising instructions is provided, which, when executed on a computer, enables the computer to implement the method in any possible implementation of the first aspect or the second aspect.

[0049] In an eighth aspect, a chip system is provided, comprising a processing circuit and a storage medium storing computer program instructions; when the computer program instructions are executed by the processor, the method of any possible implementation of the first or second aspect is implemented. The chip system may be composed of a chip alone, or may include a chip and other discrete components. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] FIG1 is a schematic diagram showing the principle of using a conventional emitting (EM) control signal to perform emitting control;

[0051] FIG2 is a schematic diagram of a conventional EM control signal driving the light emitting effect of a pixel;

[0052] FIG3 is a schematic diagram showing the principles of light emission control using two other conventional EM control signals;

[0053] FIG4 is a schematic diagram of the hardware structure of an electronic device provided in an embodiment of the present application;

[0054] FIG5 is a first schematic diagram of the luminous effect of driving a pixel using an EM control signal according to an embodiment of the present application;

[0055] FIG6 is a second schematic diagram of the luminous effect of driving a pixel using an EM control signal according to an embodiment of the present application;

[0056] FIG7 is a third schematic diagram of the luminous effect of driving a pixel using an EM control signal according to an embodiment of the present application;

[0057] FIG8 is a fourth schematic diagram of the luminous effect of driving a pixel using an EM control signal according to an embodiment of the present application;

[0058] FIG9 is a fifth schematic diagram of the luminous effect of driving a pixel using an EM control signal according to an embodiment of the present application;

[0059] FIG10 is a first schematic diagram showing the principle of light emission control using an EM control signal according to an embodiment of the present application;

[0060] FIG11 is a second schematic diagram showing the principle of light emission control using an EM control signal according to an embodiment of the present application;

[0061] FIG12 is a third schematic diagram showing the principle of light emission control using an EM control signal according to an embodiment of the present application;

[0062] FIG13 is a schematic diagram of a pixel circuit provided in an embodiment of the present application;

[0063] FIG14 is a schematic diagram of a driving timing corresponding to a refresh frame period provided by an embodiment of the present application;

[0064] FIG15 is a first schematic diagram of a driving timing sequence corresponding to a frame period provided by an embodiment of the present application;

[0065] FIG16 is a second schematic diagram of a driving timing sequence corresponding to a frame period provided by an embodiment of the present application;

[0066] FIG17 is a third schematic diagram of a driving timing sequence corresponding to a frame period provided by an embodiment of the present application;

[0067] FIG18 is a structural block diagram of a display panel provided in an embodiment of the present application. DETAILED DESCRIPTION

[0068] The technical solutions in the embodiments of the present application will be described below in conjunction with the accompanying drawings in the embodiments of the present application. In the description of the embodiments of the present application, unless otherwise specified, " / " means or, for example, A / B can mean A or B; "and / or" in this article is merely a description of the association relationship of associated objects, indicating that three relationships can exist, for example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. In addition, in the description of the embodiments of the present application, "multiple" means two or more than two.

[0069] In the following, the terms "first," "second," and so on are used solely to distinguish different descriptive objects and do not limit the position, order, priority, quantity, or content of the described objects. For example, if the described object is a "field," the ordinal number preceding the "field" in "first field" and "second field" does not limit the position or order of the "fields." "First" and "second" do not limit whether the modified "fields" are in the same message, nor do they restrict the order of the "first field" and "second field." For another example, if the described object is a "level," the ordinal number preceding the "level" in "first level" and "second level" does not limit the priority of the "levels." For another example, the number of described objects is not limited by the ordinal number and can be one or more. For example, in the case of "first device," the number of "devices" can be one or more. Furthermore, the objects modified by different prefixes can be the same or different. For example, if the described object is a "device," the "first device" and "second device" can be devices of the same type or different types. For another example, if the described object is "information," the "first information" and "second information" can be information of the same content or different contents. In short, the use of prefixes such as ordinal numbers to distinguish the described objects in the embodiments of the present application does not constitute a restriction on the described objects. For the statement of the described objects, please refer to the description in the context of the claims or embodiments, and no unnecessary restrictions should be constituted due to the use of such prefixes.

[0070] Furthermore, in the embodiments of the present application, "connection" may be a direct connection or an indirect connection; in addition, it may refer to an electrical connection or a communication connection; for example, the connection between two electrical components A and B may refer to a direct connection between A and B, or it may refer to an indirect connection between A and B through other electrical components or connection media, or it may refer to an indirect connection between A and B through other communication devices or communication media, as long as communication between A and B can be achieved.

[0071] As described in the background art, existing electronic device displays, such as active matrix organic light emitting diode (AMOLED) panels, often use dimming strategies such as PWM and DC modulation for dimming. For example, PWM dimming strategies are used in low- to medium-brightness scenarios, and DC modulation dimming strategies are used in high-brightness scenarios. This is done to achieve better display effects and enhance the user's visual experience by adjusting the duty cycle and / or brightness value of the display. However, these dimming methods are all strategies under ideal conditions and do not take into account the actual working conditions of the display.

[0072] For example, in low to medium brightness scenarios, existing dimming methods do not consider the impact of anode resetting and charging of devices such as the EL capacitor and pixel circuit anode on the display screen on the display screen's luminous time.

[0073] As shown in Figure 1, using a 2-nit screen brightness setting using an emitting (EM) control signal, 1440Hz PWM dimming, a 120Hz display refresh rate, a 120Hz anode reset frequency, and a frame display cycle consisting of 12 control cycles, PWM dimming can generally be used to control brightness by adjusting the duty cycle to achieve a uniform dimming effect. The display refresh rate can be simply understood as the number of times the screen is illuminated per unit time; the duty cycle can be simply understood as the proportion of the total pixel illumination time. For example, using a pulse sequence with a pulse width of 1μs and a control period of 4μs, the pulse sequence duty cycle is 1μs / 4μs = 0.25. In Figure 1, when the EM control signal is low, the display is illuminated; when the EM control signal is high, the display is off. It should be noted that FIG1 only takes the display screen emitting light when the EM control signal is at a low level as an example, and does not make specific limitations in actual applications. For example, in some embodiments, a high level corresponds to a pixel emitting light, and a low level corresponds to a pixel extinguishing light, depending on the specific situation.

[0074] However, the dimming method shown in Figure 1 presents the following issues: Displays such as AMOLEDs typically include components such as EL capacitors and pixel circuit anodes. As shown in Figure 2, during the first control cycle of a frame, taking the display's anode reset at a 120Hz frequency as an example, when the EM control signal switches to a low level, the EL capacitors, pixel circuit anodes, and other components need to be charged. Consequently, the display's actual lighting duration during the first control cycle is shortened, and in severe cases, it may even be completely luminous, as shown in Figure 2. This can result in no or weak lighting during some control cycles during the display process, causing low-frequency flicker that is perceptible to the human eye. This increases the stroboscopic visibility measure (SVM), resulting in an excessively strong flickering effect.

[0075] For example, in high-brightness scenarios, such as when the screen brightness is greater than 90 nit, existing dimming methods do not consider the impact of refreshing the frame period and maintaining the consistency of the high-level phase length in the frame period on the display screen's luminous time.

[0076] As shown in Figure 3, taking the example of controlling the luminescence of the display screen at a screen brightness value of 500 nits using the EM control signal, and luminescence of the display screen when the EM control signal is at a low level, under normal circumstances, controlling the refresh frame period and the duration of the control signal being at a low level within the holding frame period to be consistent (or the error is within a certain acceptable range) can make the refresh frame period and the duration of the display screen luminescence within the holding frame period consistent, thereby achieving a uniform dimming effect. Moreover, for different display refresh rates, as shown in Figure 3, the display refresh rates are 120Hz and 60Hz, and the refresh frame period and the duration of the EM control signal being at a low level within the holding frame period are also consistent (or the error is within a certain acceptable range), thereby achieving a consistent duty cycle at different display refresh rates, thereby avoiding brightness differences caused by display refresh rate switching.

[0077] However, the dimming method shown in Figure 3 presents the following issues: In practical applications, because the refresh frame period requires gate reset and data writing (e.g., for display refresh), the high-level phase lasts for a long time, meaning the display screen is off for a longer period. Consequently, the duration of the EM low level is necessarily shortened. If the refresh frame period is to be consistent with the duration of the EM control signal being low within the hold frame period, the screen-on duration within the hold frame period will be shortened. This results in the display screen requiring a higher brightness amplitude when EM is low to achieve the set brightness target, and the average luminous duration within a frame is low. Both of these effects lead to an increase in SVM, or the problem of excessive screen flicker.

[0078] It should be noted that in the examples shown in Figures 1-3, when the EM control signal is low, the display illuminates; when the EM control signal is high, the display turns off. Of course, in actual applications, a high level may correspond to a lit display, while a low level may correspond to a dark display, depending on the specific situation.

[0079] In order to solve the problem of excessive flickering caused by the existing dimming method when applying the existing method due to the large brightness difference between the non-luminous and luminous stages during the display screen display process, the long non-luminous time and the large SVM value caused by non-luminous or weak luminous in some cycles, the embodiment of the present application provides a driving method for pixel circuits, which can solve the screen flicker problem in brightness scenes such as medium and low brightness scenes and high brightness scenes.

[0080] For example, based on the solution provided in the embodiments of the present application, in medium and low brightness scenarios, a non-uniform duty cycle configuration can be adopted in each control cycle of the display cycle (such as the EM cycle, which is introduced below using the EM cycle as an example) to achieve normal light emission in the low-level stage after taking into account factors such as anode reset and device charging, and to make the light emission uniform in multiple low-level stages, thereby optimizing screen flicker and achieving better display and eye protection effects.

[0081] For example, based on the solution provided in the embodiment of the present application, in a high-brightness scene, the parameters of at least one control cycle corresponding to the picture frame can be adjusted according to one or more parameters such as the screen brightness value, display refresh rate, reset frequency (such as source reset frequency, drain reset frequency, etc.), such as the duration of the first level stage, and finally the interface display can be performed according to the parameters of the adjusted control cycle. For example, based on different reset frequencies (such as 120Hz, 240Hz, 360Hz) and / or different display refresh rates (such as 1Hz, 60Hz, 120Hz), differentiated driving can be performed within the refresh frame period and the hold frame period, such as making the first level stage (such as the high level stage, the first level stage is used as the high level stage as an example for relevant introduction) of the refresh frame period and the hold frame period differ by more than 1H, while making the duty cycle under different display refresh rates and / or different reset frequencies high and basically maintained (such as the difference is less than 0.2%), so as to optimize screen flicker and achieve better display and eye protection effects. Among them, 1H is the scanning time unit of each line of the display screen, usually between 1 and 3us.

[0082] The display screen described in the embodiments of the present application is a display screen of an electronic device, and the electronic device may include but is not limited to a smartphone, a netbook, a tablet computer, a smart drawing board, a handwriting board, a smart watch, a smart bracelet, a phone watch, smart glasses, a smart camera, a PDA, a car computer, a personal computer (PC), a personal digital assistant (PDA), a portable multimedia player (PMP), an augmented reality (AR) / virtual reality (VR) device, a smart TV, a projection device, or a somatosensory game console in a human-computer interaction scenario. Alternatively, the electronic device may be an electronic device with a display screen of other types or structures, which is not limited in the present application.

[0083] As an example, please refer to FIG4 , which shows a schematic diagram of the hardware structure of an electronic device provided in an embodiment of the present application.

[0084] As shown in FIG4 , the electronic device may include a processor 410 , a memory 420 , a charging management module 430 , a power management module 440 , a battery 450 , a display screen 460 , and the like.

[0085] Processor 410 may include one or more processing units. For example, processor 410 may include an application processor (AP), a modem processor, a graphics processing unit (GPU), an image signal processor (ISP), a flight controller, a video codec, a digital signal processor (DSP), a baseband processor, and / or a neural-network processing unit (NPU). The different processing units may be independent devices or integrated into one or more processors.

[0086] Processor 410 may also include a memory for storing instructions and data. In some embodiments, the memory in processor 410 is a cache memory. This memory can store instructions or data that have just been used or are being recycled by processor 410. If processor 410 needs to use the same instruction or data again, it can directly access the memory. This avoids duplicate accesses, reduces processor 410 latency, and thus improves system efficiency.

[0087] The charging management module 430 is configured to receive charging input from a charger. The charger can be either a wireless charger or a wired charger. In some wired charging embodiments, the charging management module 430 can receive charging input from the wired charger via a USB port. In some wireless charging embodiments, the charging management module 430 can receive wireless charging input via a wireless charging coil. While charging the battery 450, the charging management module 430 can also power the electronic device through the power management module 440.

[0088] The power management module 440 is used to connect the battery 450, the charging management module 430, and the processor 410. The power management module 440 receives input from the battery 450 and / or the charging management module 430 and provides power to the processor 410, the internal memory 420, the display 460, the camera 393, and the wireless communication module 360. The power management module 440 can also be used to monitor parameters such as battery capacity, battery cycle count, and battery health status (leakage, impedance). In some other embodiments, the power management module 440 can also be provided in the processor 410. In other embodiments, the power management module 440 and the charging management module 430 can also be provided in the same device.

[0089] In the embodiment of the present application, the power management module 440 receives input from the battery 450 and / or the charging management module 430 to provide power to the display screen 460 to support normal operation of the display screen, such as lighting or extinguishing.

[0090] The electronic device implements display functionality through a GPU, display screen 460, and an access point (AP). The GPU is a microprocessor for image processing that connects the display screen 460 and the access point. The GPU is used to perform mathematical and geometric calculations for graphics rendering. The processor 410 may include one or more GPUs, which execute program instructions to generate or modify display information.

[0091] Display screen 460 is used to display images, videos, and the like. Display screen 460 includes a display panel. The display panel can be a liquid crystal display (LCD), an organic light-emitting diode (OLED), an active-matrix organic light-emitting diode (AMOLED), a flexible light-emitting diode (FLED), a MiniLED, a MicroLED, a Micro-OLED, or a quantum dot light-emitting diode (QLED).

[0092] In the embodiment of the present application, the display screen 460 can display images based on the normal operation of the display panel.

[0093] In some embodiments, the display screen can adopt a non-uniform duty cycle configuration in each EM cycle of the display cycle in medium and low brightness scenarios to ensure that the display screen can emit light normally in the first second level stage (such as the low level stage, the following introduction will take the second level stage as the low level stage as an example) after completing the anode reset, device charging, etc., and make the multiple low level stages in the same display cycle emit light evenly.

[0094] In some embodiments, the display screen can be driven differentially in the refresh frame period and the hold frame period based on different reset frequencies (such as 120Hz, 240Hz, 360Hz) and / or different display refresh rates (such as 1Hz, 60Hz, 120Hz) in high-brightness scenarios, so that the duty cycle under different display refresh rates and / or different reset frequencies is high and basically remains the same (such as the difference is less than 0.2%), so as to achieve a smaller SVM value, optimize screen flicker, and achieve better display and eye protection effects.

[0095] In some embodiments, as shown in FIG. 4 , a display screen may include an integrated circuit (eg, a driver integrated circuit (IC)), a gate driving unit, and a pixel circuit.

[0096] The pixel circuit includes a light emitting control circuit and a reset circuit.

[0097] The driver IC is configured to: obtain a screen brightness value; and, when the screen brightness value is less than a first brightness threshold, configure the duration of the second level phase in multiple control cycles according to a period for positive reset (e.g., a first control period); or, when the screen brightness value is greater than a second brightness threshold, configure the duration of the first level phase in multiple control cycles according to a display refresh rate corresponding to a light emitting control signal and / or a reset frequency corresponding to a reset control signal. Exemplarily, the gate driver unit may include, but is not limited to, a GOA.

[0098] The light emitting control circuit is used to control the light emitting of the pixel circuit according to the light emitting control signal, by controlling the duration of the first level stage not used for light emitting and the duration of the second level stage used for light emitting in multiple control cycles.

[0099] The reset circuit is used to: control whether multiple control cycles are used for reset according to the reset control signal, such as controlling reset in the first control cycle, for example, the anode reset circuit is used to control whether multiple control cycles are used for anode reset according to the anode reset control signal, the source reset circuit is used to control whether multiple control cycles are used for source reset according to the source reset control signal, and the drain reset circuit is used to control whether multiple control cycles are used for drain reset according to the drain reset control signal.

[0100] The external memory interface 320 can be used to connect an external memory card, such as a Micro SD card, to expand the storage capacity of the electronic device. The external memory card communicates with the processor 410 through the external memory interface 320 to implement data storage.

[0101] The internal memory can be used to store computer executable program codes. For example, computer programs may include operating system programs and application programs. Among them, the executable program code includes instructions. The processor 410 executes various functional applications and data processing of the electronic device by running the instructions stored in the memory 420. The memory 420 may include a program storage area and a data storage area. Among them, the program storage area may store an operating system, an application required for at least one function, etc. The data storage area may store data created during the use of the electronic device, etc. In addition, the memory 420 may include a high-speed random access memory, and may also include a non-volatile memory, such as at least one disk storage device, a flash memory device, a universal flash storage (UFS), etc. The processor 410 executes various functional applications and data processing of the electronic device by running the instructions stored in the memory 420, and / or the instructions stored in the memory provided in the processor.

[0102] It should be understood that the structure illustrated in FIG4 of the present application does not constitute a specific limitation on the electronic device. In other embodiments of the present application, the electronic device may include more or fewer components than shown, or may combine or separate certain components, or arrange the components differently. The components shown in the figure may be implemented in hardware, software, or a combination of software and hardware.

[0103] For example, in some examples, the electronic device may also include a universal serial bus (USB) interface, an antenna, a mobile communication module, a wireless communication module, an audio module, a speaker, a receiver, a microphone, a headphone interface, a sensor module, a button, a motor, an indicator, a camera, and one or more other devices or modules, which are not repeated here.

[0104] The following will specifically introduce the driving method of the pixel circuit provided in the embodiment of the present application in combination with specific scenarios.

[0105] Example 1:

[0106] In Example 1, when an electronic device displays a picture frame based on a pixel circuit, the display period of one picture frame generally includes multiple consecutive control periods. The pixel circuit includes a light-emitting control circuit and an anode reset circuit. The light-emitting control circuit is configured to receive a light-emitting control signal, such as an EM control signal; the anode reset circuit is configured to receive an anode reset control signal. In other words, the pixel circuit can receive the EM control signal and control light emission based on the duration of a level phase not used for light emission and the duration of a level phase used for light emission in multiple control periods. The anode reset circuit can control whether multiple control periods are used for anode reset based on the anode reset control signal.

[0107] In Example 1 of the present application, the pixel circuit adopts a non-uniform duty cycle configuration in each control cycle to ensure that the pixel can emit light normally in each low-level stage, and the light emission amount in each low-level stage is the same or close, thereby ensuring uniform light emission in multiple low-level stages of the same display cycle.

[0108] In some embodiments, the solution provided in Example 1 can be applied to scenarios where the screen brightness value is less than a first brightness threshold. For example, the first brightness threshold is, for example, 90 nits, meaning that the solution provided in Example 1 can be applied to medium-to-low brightness scenarios. The specific value of the first brightness threshold is not specifically limited.

[0109] In some embodiments, the display cycle of the pixel circuit includes multiple control cycles of the same duration, and the multiple control cycles all include a first level stage and a second level stage, that is, each control cycle includes a first level stage and a second level stage, wherein the first level stage is a level stage for anode reset, and the second level stage is a level stage for light emission. In Example 1 of the present application, the duration of the second level stage in the multiple control cycles can be configured based on the control cycle for anode reset (such as the first control cycle) in the multiple control cycles, and then the light emission is controlled based on the duration of the first level stage and the duration of the second level stage in the multiple control cycles.

[0110] In some embodiments, the first level stage is a high level stage and the second level stage is a low level stage; or, the first level stage is a low level stage and the second level stage is a high level stage, which is not limited in the embodiments of the present application. The following embodiments take the first level stage as an example, where the first level stage is a high level stage and the second level stage is a low level stage.

[0111] As a possible implementation, the first control cycle may include at least one control cycle, and the second control cycle may include at least one control cycle. That is, there may be one or more first control cycles and one or more second control cycles, wherein the first control cycle is used for anode reset and the second control cycle is not used for anode reset. Based on this, a similar operation of configuring the duration of the second level phase can be performed for each first control cycle and each second control cycle. For example, the duration of the second level phase in each first control cycle and each second control cycle can be configured according to each first control cycle, and then the light emission is controlled according to the duration of the first level phase and the duration of the second level phase in multiple control cycles (including each first control cycle and each second control cycle). For example, the duration of the second level phase in the first control cycle can be configured as the first duration, and the duration of the second level phase in the second control cycle can be configured as the second duration, so that the first duration is greater than the second duration. Based on this, the duration of the first second-level stage after the anode reset can be made longer than the duration of the second-level stage in the control cycle without anode reset, so as to ensure that the duration of each second-level stage is sufficient to charge the EL capacitor, pixel circuit anode and other devices and maintain sufficient luminescence, and make the luminescence of each second-level stage the same or close.

[0112] For example, taking the case where light emission is controlled by an EM control signal at a screen brightness value of 2 nit, the EM control signal adopts 1440 Hz PWM dimming, the display refresh rate is 120 Hz, the anode reset frequency is 120 Hz, the display period of one frame includes 12 EM periods, the first level stage is a high level stage, and the second level stage is a low level stage as an example, a schematic diagram of the EM control signal and the light emission effect of the pixel may be as shown in FIG5 , wherein the 12 EM periods shown in FIG5 (EM period 1, EM period 2, ..., EM period 12 as shown in FIG5 ) each include a high level stage and a low level stage. For example, according to the timing sequence, the EM control signal includes high level stage 1, low level stage 1, high level stage 2, low level stage 2, high level stage 3, low level stage 3, ..., high level stage 12, and low level stage 12 as shown in FIG5 . As shown in FIG5 , compared with the duration of the low-level phase (i.e., the second duration) of other EM cycles (e.g., the second control cycle described above), the duration of the low-level phase (i.e., the first duration) in EM cycle 1 for anode reset (i.e., the first control cycle described above) is longer. Therefore, after completing the anode reset, the electronic device can switch to the low-level phase in advance to start charging components such as the EL capacitor and the pixel circuit anode, thereby ensuring that the luminescence of the pixel in the first low-level phase is equal to or close to the luminescence of the pixel in other low-level phases.

[0113] As an example, the first duration is compared to the duration of the low-level phase in the control period with the shortest low-level phase in the display period (e.g., denoted as "duration Min"), and has the following relationship: (first duration - duration Min) / duration Min > (or ≥) a first preset threshold. For example, the first preset threshold is a value within a range of 10%-100%, such as 60%. Of course, the embodiment of the present application does not limit the specific first preset threshold, and it depends on the specific situation in actual application.

[0114] In some embodiments, the first control cycle includes a second level phase. In this case, the first duration is the duration of the second level phase of the first control cycle.

[0115] In some embodiments, the first control cycle includes multiple second level phases. In this case, the first duration includes the total duration (i.e., the sum of the durations) of the multiple second level phases in the first control cycle.

[0116] For example, taking the case where light emission is controlled by an EM control signal at a screen brightness value of 2 nit, the EM control signal adopts 1440 Hz PWM dimming, the display refresh rate is 120 Hz, the anode reset frequency is 120 Hz, the display period of one frame includes 12 EM cycles, the first level stage is a high level stage, and the second level stage is a low level stage as an example, a schematic diagram of the light emission effect of the pixel driven by the EM control signal may be shown in FIG6 , wherein the 12 EM cycles (EM cycle 1, EM cycle 2, ..., EM cycle 12 as shown in FIG6 ) each include a high level stage and a low level stage (for ease of reading, the high and low level stages are not shown in FIG6 ; for this, please refer to FIG5 ). As shown in FIG6 , compared to the duration of the low-level phase (i.e., the second duration) in other EM cycles (such as the second control cycle described above), EM cycle 1 for anode reset (i.e., the first control cycle described above) has two low-level phases, and the total duration of these two low-level phases (i.e., the first duration) is longer. Therefore, in EM cycle 1 (i.e., the first control cycle described above), after completing the anode reset, the electronic device can switch to the low-level phase in advance to start charging components such as the EL capacitor and the pixel circuit anode, and start emitting light when entering the next low-level phase in the same EM cycle, thereby ensuring that the light emission of the pixel in the first light-emitting phase is equal to or close to the light emission of the pixel in other low-level phases.

[0117] In addition, it should be noted that the examples shown in Figures 5 and 6 of this application only use a single anode reset within a display cycle as an example. In actual applications, the solutions provided in the embodiments of this application are also applicable to the case where anode reset is performed multiple times (such as 2 times, 3 times, etc., with no limit on the number) within a display cycle. In other words, a display cycle may include multiple first control cycles, and based on the solutions provided in this application, the duration of the second level phase in multiple first control cycles for anode reset can be configured.

[0118] For example, taking the case where light emission is controlled by an EM control signal at a screen brightness value of 2 nit, the EM control signal adopts 1440 Hz PWM dimming, the display refresh rate is 120 Hz, the anode reset frequency is 360 Hz, the display period of one frame includes 12 EM cycles, the first level stage is a high level stage, and the second level stage is a low level stage as an example, a schematic diagram of the light emission effect of the pixel driven by the EM control signal may be shown in FIG7 , wherein the 12 EM cycles (EM cycle 1, EM cycle 2, ..., EM cycle 3 as shown in FIG7 ) each include a high level stage and a low level stage (for ease of reading, the high and low level stages are not shown in FIG7 ; for this, reference may be made to FIG5 ). As shown in FIG7 , compared to the duration of the low-level phase (i.e., the second duration) of other EM cycles (such as the second control cycle described above), the duration of the low-level phase (i.e., the first duration) in EM cycles 1, EM cycles 5, and EM cycles 9 (i.e., the multiple first control cycles described above) for anode reset is longer. Therefore, after each anode reset is completed, the electronic device can switch to the low-level phase in advance to start charging components such as the EL capacitor and the pixel circuit anode, thereby ensuring that the luminescence amount of the pixel in the first low-level phase after each anode reset is equal to or close to the luminescence amount of the pixel in other low-level phases.

[0119] For another example, taking the case where light emission is controlled by an EM control signal at a screen brightness value of 2 nit, the EM control signal adopts 1440 Hz PWM dimming, the display refresh rate is 120 Hz, the anode reset frequency is 360 Hz, the display period of one frame includes 12 EM cycles, the first level stage is a high level stage, and the second level stage is a low level stage, a schematic diagram of the light emission effect of the pixel driven by the EM control signal may be shown in FIG8 , where the 12 EM cycles (EM cycle 1, EM cycle 2, ..., EM cycle 12 in FIG8 ) each include a high level stage and a low level stage (for ease of reading, the high and low level stages are not shown in FIG8 ; for details, please refer to FIG5 ). As shown in FIG8 , compared to the duration of the low-level phase (i.e., the second duration described above) of other EM cycles (such as the second control cycle described above), EM cycles 1, EM cycles 5, and EM cycles 9 (i.e., the first control cycle described above) for anode reset each have two low-level phases, and the total duration of the two low-level phases in each cycle (i.e., the first duration described above) is longer. Therefore, after each anode reset is completed, the electronic device can switch to the low-level phase in advance to start charging components such as the EL capacitor and the pixel circuit anode, and start emitting light when entering the next low-level phase, thereby ensuring that the amount of light emitted by the pixel in the first light-emitting phase after each anode reset is equal to or close to the amount of light emitted by the pixel in other low-level phases.

[0120] Also, it should be noted that the examples shown in Figures 5 and 6 of the present application are only used as examples to ensure the duration of the first light-emitting stage (i.e., the second level stage) after the anode is reset. In actual applications, for one or more other light-emitting stages after the anode is reset, the method provided in the embodiments of the present application can also be used to ensure the light emission.

[0121] As a possible implementation, the duration of the second level phase in the third control cycle can be configured to a third duration, such that the third duration is greater than the second duration, wherein the third control cycle is not used for anode reset. As an example, the third control cycle can be the control cycle after the first control cycle, such as the first control cycle after the first control cycle. Based on this, sufficient luminescence can be ensured in the second second level phase after the anode reset, and the luminescence amounts of each second level phase can be the same or similar.

[0122] As an example, the third control period may include at least one control period, that is, there may be one or more third control periods. Based on this, a similar operation of configuring the duration of the second level phase may be performed for each third control period. For example, the duration of the second level phase in each third control period may be configured based on the first control period, and then the light emission is controlled based on the duration of the first level phase and the duration of the second level phase in multiple control periods (including each third control period).

[0123] As an example, the third duration is less than or equal to the first duration.

[0124] For example, taking the case where light emission is controlled by an EM control signal at a screen brightness value of 2 nit, the EM control signal adopts 1440 Hz PWM dimming, the display refresh rate is 120 Hz, the anode reset frequency is 120 Hz, the display period of one frame includes 12 EM cycles, the first level stage is a high level stage, and the second level stage is a low level stage as an example, a schematic diagram of the light emission effect of the pixel driven by the EM control signal may be shown in FIG9 , wherein the 12 EM cycles (EM cycle 1, EM cycle 2, ..., EM cycle 12 as shown in FIG9 ) each include a high level stage and a low level stage (for ease of reading, the high and low level stages are not shown in FIG9 ; for this, reference may be made to FIG5 ). As shown in FIG9 , compared with the duration of the low-level phase (i.e., the second duration) of other EM cycles (such as the second control cycle described above), the duration of the low-level phase (i.e., the third duration) in EM cycle 1 for anode reset (i.e., the first control cycle described above) and EM cycle 1 after EM cycle 1 (i.e., the third control cycle described above) is longer. Therefore, after completing the anode reset, the electronic device can switch to the low-level phase in advance to start charging components such as the EL capacitor and the anode of the pixel circuit, thereby making the luminescence amount of the pixel in the first low-level phase after the anode reset equal to or close to the luminescence amount of the pixel in other low-level phases; and, as shown in FIG9 , the electronic device can enter the second low-level phase after the anode reset in advance to perform luminescence compensation, thereby ensuring that the luminescence amount in this phase is equal to or close to the luminescence amount of the pixel in other low-level phases.

[0125] In some embodiments, in the example shown in FIG. 9 , the duration of the low-level phase in EM cycle 1 (i.e., low-level phase 1) and the duration of the low-level phase in EM cycle 2 (i.e., low-level phase 2) may be the same or different, and so on.

[0126] It should be noted that the examples shown in Figures 5, 6, and 9 of the present application illustrate schematic diagrams of the luminous effects of three possible EM control signals driving pixels, using as examples a case where the EM control signal adopts 1440Hz PWM dimming, a display refresh rate of 120Hz, an anode reset frequency of 120Hz, and a display period of one frame includes 12 EM cycles. The examples shown in Figures 7 and 8 of the present application illustrate schematic diagrams of the luminous effects of two possible EM control signals driving pixels, using as examples a case where the EM control signal adopts 1440Hz PWM dimming, a display refresh rate of 120Hz, an anode reset frequency of 360Hz, and a display period of one frame includes 12 EM cycles. In actual applications, there are no specific limitations on the type of luminous control signal, the dimming frequency of the luminous control signal, the display refresh rate, and the anode reset frequency, and these will depend on the actual conditions, such as the type, structure, or material of the display screen.

[0127] It can be understood that based on the solution provided in Example 1 of the present application, the electronic device flexibly adopts non-uniform duty cycle configurations in each control period of the display cycle, such as making the duration of the low-level stage of some control periods with insufficient brightness longer than other low-level stages, to ensure that each pixel of the display screen can maintain normal light emission in each low-level stage, and the light emission amount in each low-level stage is the same or close, thereby ensuring uniform light emission in multiple low-level stages of the same display cycle.

[0128] For example, compared to the EM control signal shown in FIG2 , the duration of the first low-level phase after the anode reset in the EM control signals shown in FIG5 and FIG7 is longer than that of other low-level phases. Therefore, after completing the charging of the EL capacitor, the pixel circuit anode, and other components, there is still sufficient low-level duration to ensure that the pixel's luminescence during this phase is equal to or close to the luminescence of the pixel during other low-level phases. Based on this, compared to the display effect shown in FIG2 , as shown in FIG5 and FIG7 , during the first low-level phase after the anode reset, each pixel of the display screen emits normally and the luminescence effect is basically consistent with that of other low-level phases in the same display cycle.

[0129] For another example, compared to the EM control signal shown in FIG2 , the first low-level phase after the anode reset in the EM control signals shown in FIG6 and FIG8 is used to charge components such as the EL capacitor and the pixel circuit anode, while the original first low-level phase after the anode reset is used for light emission. Therefore, after the charging of the EL capacitor and the pixel circuit anode is completed, the low-level phase is still sufficient to ensure that the pixel's light emission during this phase is equal to or close to the light emission of the pixel during other low-level phases. Based on this, compared to the display effect shown in FIG2 , each pixel on the display screen in the first EM cycle shown in FIG6 emits light normally and is substantially consistent with the light emission effect during other low-level phases in the same display cycle. Each pixel on the display screen in the first, fifth, and ninth EM cycles shown in FIG8 emits light normally and is substantially consistent with the light emission effect during other low-level phases in the same display cycle.

[0130] For example, compared to the EM control signal shown in FIG2 , the duration of the first low-level phase and the second low-level phase after the anode reset in the EM control signal shown in FIG9 is longer than that of the other low-level phases. Therefore, after completing the charging of the EL capacitor, the pixel circuit anode, and other components, there is still sufficient low-level duration to ensure that the amount of light emitted by the pixel in the first low-level phase is equal to or close to the amount of light emitted by the pixel in the other low-level phases. In addition, by entering the second low-level phase after the anode reset in advance, the amount of light emitted in the second low-level phase can be ensured to be equal to or close to the amount of light emitted by the pixel in the other low-level phases. Based on this, compared to the display effect shown in FIG2 , as shown in FIG9 , in the first low-level phase and the second low-level phase after the anode reset, each pixel of the display screen emits light normally and the light-emitting effect is basically consistent with the other low-level phases of the same frame.

[0131] Example 2:

[0132] In Example 2, when an electronic device displays a picture frame based on a pixel circuit, a display cycle of a picture frame generally includes multiple consecutive control cycles. The pixel circuit includes a light-emitting control circuit and a reset circuit (e.g., a source reset circuit or a drain reset circuit of a driving thin film transistor (DTFT)). The light-emitting control circuit is configured to receive a light-emitting control signal, such as an EM control signal; the reset circuit is configured to receive a reset control signal, such as a source reset circuit configured to receive a source reset control signal and a drain reset circuit configured to receive a drain reset control signal. In other words, the pixel circuit can receive the EM control signal and control light emission based on the duration of a level phase not used for light emission and the duration of a level phase used for light emission in multiple control cycles. The reset circuit can control whether multiple control cycles are used for reset based on the reset control signal, such as controlling whether multiple control cycles are used for source reset based on the source reset control signal, or controlling whether multiple control cycles are used for drain reset based on the drain reset control signal.

[0133] In some embodiments, the display cycle of the pixel circuit includes multiple control cycles with the same duration, and the multiple control cycles all include a first level stage and a second level stage, that is, each control cycle includes a first level stage and a second level stage, wherein the first level stage is a level stage for resetting (such as a source reset circuit or a drain reset circuit), and the second level stage is a level stage for luminescence.

[0134] In some embodiments, the first level stage is a high level stage and the second level stage is a low level stage; or, the first level stage is a low level stage and the second level stage is a high level stage, which is not limited in the embodiments of the present application. The following embodiments take the first level stage as an example, where the first level stage is a high level stage and the second level stage is a low level stage.

[0135] In embodiment 1 of the present application, the electronic device configures the duration of the first level stage in multiple control cycles of the display cycle based on the reset frequency corresponding to the reset control signal and / or the display refresh rate corresponding to the light-emitting control signal, and then controls the light-emitting according to the duration of the first level stage and the duration of the second level stage in the multiple control cycles.

[0136] As an example, the multiple control cycles include a refresh frame cycle and a hold frame cycle, such as there may be one refresh frame cycle, and there may be one or more hold frame cycles. Among them, the refresh frame cycle is used for display refresh and gate reset, and the hold frame cycle is used to maintain the display. The electronic device can perform differentiated driving in the refresh frame cycle and each hold frame cycle (for the case where there are multiple hold frame cycles) in the display cycle of the picture frame based on the reset frequency corresponding to the reset control signal and / or the display refresh rate corresponding to the light emitting control signal, such as adjusting the duration of the first level stage in each hold frame cycle based on different reset frequencies and / or different refresh rates.

[0137] In addition, after adjusting the duration of the first level stage in each holding frame period, the electronic device can refresh and reset the display when entering the first level stage of the refresh frame period, and control the light emission according to the duration of the first level stage and the duration of the second level stage in multiple control periods (including refresh frame periods and holding frame periods), such as not emitting light when entering the first level stage of the refresh frame period, emitting light when entering the second level stage of the refresh frame period, and then not emitting light when entering the first level stage of the holding frame period, and emitting light when entering the second level stage of the holding frame period.

[0138] In some examples, the plurality of control periods include a refresh frame period but do not include a hold frame period. In this case, the electronic device may only set the duration of the first level phase in the refresh frame period.

[0139] For example, in Example 2, the duration of the first level stage (such as the high level stage) of the frame period in the display period can be reduced based on different reset frequencies and / or different display refresh rates, so that the duty cycle at different display refresh rates and / or different reset frequencies is maintained at a high level to optimize screen flicker, and the duty cycle at different display refresh rates and / or different reset frequencies is kept basically the same (such as the difference is less than a preset threshold) to achieve better display and eye protection effects.

[0140] In some embodiments, the solution provided in Example 2 can be applied to scenarios where the screen brightness value is greater than a second brightness threshold, where the second brightness threshold is greater than the first brightness threshold. For example, the second brightness threshold is, for example, 90 nits, meaning that the solution provided in Example 2 can be applied to high-brightness scenarios. The specific value of the second brightness threshold is not specifically limited.

[0141] It can be understood that, taking the EM control signal as an example, the display period of a picture frame typically includes multiple EM periods. For example, the number of EM periods included in a display period is N = F1 / F2, where 1 EM period is a refresh frame period, N-1 EM periods are hold frame periods, F1 is the source reset frequency or drain reset frequency, and F2 is the display refresh rate. During the refresh frame period of the display period, display refresh, gate reset, source reset / drain reset, threshold compensation, etc. are typically performed, while during the hold frame period of the display period, display refresh, gate reset, source reset / drain reset, threshold compensation, etc. are typically not performed.

[0142] Taking a source reset frequency or a drain reset frequency of 360 Hz and a display refresh rate of 120 Hz as an example, N=360 Hz / 120 Hz=3, i.e., the display period of one picture frame includes three EM cycles, of which the first EM cycle is a refresh frame period, and the other two EM cycles are hold frame periods. Taking a source reset frequency or a drain reset frequency of 360 Hz and a display refresh rate of 60 Hz as an example, N=360 Hz / 60 Hz=6, i.e., the display period of one picture frame includes six EM cycles, of which the first EM cycle is a refresh frame period, and the other five EM cycles are hold frame periods. Similarly, taking a source reset frequency or a drain reset frequency of 360 Hz and a display refresh rate of 1 Hz as an example, N=360 Hz / 1 Hz=360, i.e., the display period of one picture frame includes 360 EM cycles, of which the first EM cycle is a refresh frame period, and the other 359 EM cycles are hold frame periods.

[0143] Taking the case where the source reset frequency or drain reset frequency is 240 Hz and the display refresh rate is 120 Hz as an example, N=240 Hz / 120 Hz=2, i.e., the display period of one picture frame includes two EM cycles, of which the first EM cycle is a refresh frame period and the second EM cycle is a hold frame period. Taking the case where the source reset frequency or drain reset frequency is 240 Hz and the display refresh rate is 60 Hz as an example, N=240 Hz / 60 Hz=4, i.e., the display period of one picture frame includes four EM cycles, of which the first EM cycle is a refresh frame period and the other three EM cycles are hold frame periods. Similarly, taking the case where the source reset frequency or drain reset frequency is 240 Hz and the display refresh rate is 1 Hz as an example, N=240 Hz / 1 Hz=240, i.e., the display period of one picture frame includes 240 EM cycles, of which the first EM cycle is a refresh frame period and the other 239 EM cycles are hold frame periods.

[0144] It should be noted that the embodiment of the present application does not limit whether the display period includes the frame holding period. In some cases, the display period of a picture frame may not include the frame holding period.

[0145] For example, taking the source reset frequency or drain reset frequency of 120 Hz and the display refresh rate of 120 Hz as an example, N=120 Hz / 120 Hz=1, that is, the display period of one picture frame includes one EM period, which is a refresh frame period; taking the source reset frequency or drain reset frequency of 120 Hz and the display refresh rate of 60 Hz as an example, N=120 Hz / 60 Hz=2, that is, the display period of one picture frame includes two EM periods, of which the first EM period is a refresh frame period and the second EM period is a hold frame period; and so on, taking the source reset frequency or drain reset frequency of 120 Hz and the display refresh rate of 1 Hz as an example, N=120 Hz / 1 Hz=120, that is, the display period of one picture frame includes 120 EM periods, of which the first EM period is a refresh frame period and the other 119 EM periods are hold frame periods.

[0146] In conventional methods, the duration of the first level phase (e.g., high-level phase) in the refresh frame period and the hold frame period is usually the same, and the duration of the second level phase (e.g., low-level phase) is also usually the same. This ensures that the duration of the display screen's illumination remains consistent during the refresh frame period and the hold frame period, thereby achieving a uniform dimming effect. However, conventional methods require a long time to perform display refresh, gate reset, source reset / drain reset, threshold compensation, etc. during the refresh frame period. As a result, the total screen-on duration within the display period is shortened, which can lead to an increase in SVM, i.e., the problem of excessive screen flicker.

[0147] To address the above issues, in some embodiments, the electronic device can configure the duration of the first level phase (e.g., high level phase) in the refresh frame period and the hold frame period to be shorter than the duration of the first level phase in the refresh frame period, while making the total duration of the second level phase in the display period equal or close to that in different display refresh rates / reset frequencies. It can be understood that after reducing the duration of the first level phase in the hold frame period, the duration of the second level phase in the hold frame period is correspondingly increased, which can increase the total screen-on duration in the display period, thereby reducing SVM, optimizing screen flicker, and achieving better display and eye protection effects.

[0148] As an example, the electronic device can configure the duration of the first level phase of the refresh frame period in the display period to be a fourth duration, and configure the duration of the first level phase in the maintain frame period to be a fifth duration, wherein the fifth duration is less than the fourth duration. Taking the fourth duration as 80 hours as an example, the fifth duration can be a value between 36 hours and 75 hours. In some embodiments, the difference between the fourth duration and the fifth duration is greater than or equal to 1 hour.

[0149] Taking the example of a first level stage being a high level stage and a second level stage being a low level stage, in some embodiments, the extent to which the duration of the high level stage in a maintenance frame period is reduced compared to the duration of the high level stage in a refresh frame period may be related to one or more of the following factors: specific attributes of the display screen, display refresh rate, source reset frequency or drain reset frequency, etc. For example, specific attributes of the display screen may include the type, structure, or material of the display panel; display refresh rate may include, for example, 120 Hz, 60 Hz, 1 Hz, etc., without limitation; and source reset frequency or drain reset frequency may include, for example, 120 Hz, 240 Hz, 360 Hz, etc., without limitation.

[0150] In some embodiments, when other factors such as screen brightness value, specific properties of the display screen, and reset frequency remain unchanged, the adjustment amplitude when adjusting the duration of the first level stage in the frame period varies with the display refresh rate.

[0151] As an example, when other factors such as the screen brightness value, the specific properties of the display screen, and the reset frequency remain unchanged, the duration of the high-level phase in the refresh frame period of a display refresh rate of the first refresh rate is the fourth duration, and the duration of the high-level phase in the frame period is maintained for the fifth duration. The duration of the high-level phase in the refresh frame period of a display refresh rate of the second refresh rate is the fourth duration, and the duration of the high-level phase in the frame period is maintained for the sixth duration. The first refresh rate is greater than the second refresh rate, the sixth duration is greater than the fifth duration, and the fifth and sixth durations are a value between 36 hours and 75 hours.

[0152] When other factors such as the screen brightness value, specific properties of the display screen, and display refresh rate remain unchanged, the adjustment range when adjusting the duration of the first level stage in the frame period varies with the reset frequency.

[0153] As an example, when other factors such as the screen brightness value, the specific properties of the display screen, and the display refresh rate remain unchanged, the duration of the high-level phase in the refresh frame period when the reset frequency is the first frequency is the fourth duration, and the duration of the high-level phase in the holding frame period is the seventh duration, and the duration of the high-level phase in the refresh frame period when the reset frequency is the second frequency is the fourth duration, and the duration of the high-level phase in the holding frame period is the eighth duration. Among them, the first frequency is greater than the second frequency, the eighth duration is less than the fourth duration, the ninth duration is less than the fourth duration, the eighth duration is different from the ninth duration, and the eighth and ninth durations are a value between 36H and 75H. As an example, the eighth duration is less than or equal to the ninth duration.

[0154] For example, taking the screen brightness value of 500 nit, the EM control signal adopts 1440 Hz PWM dimming, the reset frequency is 360 Hz, the first level stage is a high level stage, the second level stage is a low level stage, and the duration of the high level stage in the refresh frame period is 80 hours as an example, the duration of the high level stage in the refresh frame period and the hold frame period under different display refresh rates may be as shown in the following Table 1:

[0155] Table 1

[0156] And, for example, taking the screen brightness value of 500nit, the EM control signal adopts 1440Hz PWM dimming, the reset frequency is 240Hz, the first level stage is a high level stage, the second level stage is a low level stage, and the duration of the high level stage in the refresh frame period is 80H as an example, the duration of the high level stage in the refresh frame period and the hold frame period under different display refresh rates may be as shown in the following Table 2:

[0157] Table 2

[0158] And, for example, taking the screen brightness value of 500nit, the EM control signal adopts 1440Hz PWM dimming, the reset frequency is 120Hz, the first level stage is a high level stage, the second level stage is a low level stage, and the duration of the high level stage in the refresh frame period is 80H as an example, the duration of the high level stage in the refresh frame period and the hold frame period under different display refresh rates may be as shown in the following Table 3:

[0159] Table 3

[0160] It should be noted that Tables 1, 2, and 3 are only example values ​​for dynamically adjusting the frame period under different reset frequencies and display refresh rates. In actual applications, the adjustment range of the frame period may be different from that of the refresh frame period. The embodiments of this application do not make specific limitations and depend on the specific circumstances.

[0161] In addition, Tables 1, 2, and 3 show example values ​​for dynamically adjusting the frame period when the reset frequency is 360 Hz, 240 Hz, and 120 Hz, respectively, and the display refresh rate is 120 Hz, 60 Hz, and 1 Hz, respectively. In actual applications, the reset frequency may also be other frequencies such as 480 Hz, 600 Hz, 720 Hz, and the display refresh rate may also be other values ​​such as 180 Hz and 240 Hz. The embodiments of the present application do not make specific limitations and depend on the specific circumstances.

[0162] It can be understood that after optimizing (e.g., shortening) the duration of the high-level phase in the holding frame period based on the solution provided in Example 2 of the present application, the duration of the high-level phase in the refresh frame period requiring display refresh, gate reset, source reset / drain reset, threshold compensation, etc. is longer than the holding frame period in which operations such as display refresh, gate reset, source reset / drain reset, and threshold compensation are not required. Based on this, not only can normal display refresh, gate reset, source reset / drain reset, threshold compensation, etc. be guaranteed in the refresh frame period, but also a high and comparable duty cycle can be maintained at different display refresh rates and / or different reset frequencies to optimize SVM and achieve a better high-brightness display effect. For example, compared to a solution in which the duration of the high-level phase in each EM cycle of a display period similar to that shown in FIG3 is equal, a higher duty cycle can be achieved based on the solution provided in Example 2 of the present application. In addition, the solution provided in Example 2 of the present application maintains the difference in duty cycle of the display period under different reset frequencies and / or different display refresh rates within a range of less than 0.2% by differentially configuring the duration of the high-level phase in the refresh frame period and the maintenance frame period.

[0163] For example, please refer to FIG10 , which shows a schematic diagram of the driving principle of an EM driving signal provided by an embodiment of the present application, taking the scheme shown in Table 1 as an example. Taking the source reset frequency or the drain reset frequency as 360 Hz as an example, as shown in FIG10 , when the display refresh rate is 120 Hz, according to the above formula N=F1 / F2, it can be known that the display period of one frame includes 3 (i.e., N=360 Hz / 120 Hz=3) EM cycles, of which 1 is the refresh frame period and the other 2 (i.e., N-1=2) are the hold frame periods; when the display refresh rate is 6 ... The display period includes 6 (i.e., N=360Hz / 60Hz=6) EM cycles, of which 1 is a refresh frame period and the other 5 (i.e., N-1=5) are hold frame periods. When the display refresh rate is 1Hz, according to the above formula N=F1 / F2, it can be known that the display period of one frame includes 360 (i.e., N=360Hz / 1Hz=360) EM cycles, of which 1 is a refresh frame period and the other 359 (i.e., N-1=359) are hold frame periods. Since gate reset, source reset / drain reset, threshold compensation, etc. are not performed during the holding frame period, it is not necessary to maintain the duration of the high-level phase consistent with that in the refresh frame period. As shown in Figure 10, after optimizing (such as reducing) the duration of the high-level phase of the holding frame period based on the solution provided in Example 2 of the present application, the duration of the high-level phase in the refresh frame period that requires display refresh, gate reset, source reset / drain reset, threshold compensation, etc. is longer than that in the holding frame period that does not require display refresh, gate reset, source reset / drain reset, etc. Based on this, not only can normal display refresh, gate reset, source reset / drain reset, threshold compensation, etc. be guaranteed during the refresh frame period, but also, by differentially configuring the duration of the high-level phase in the refresh frame period and the holding frame period, the difference in the duty cycle of the display period under different display refresh rates when the source reset frequency or the drain reset frequency is 360Hz can be maintained within a very small range.

[0164] As an example, the duty cycle r of the display period can be calculated based on the following formula: r = [120 / F2*number of light-emitting array rows-first duration-second duration*(F1 / F2-1)] / (120 / F2*number of light-emitting array rows), where F1 is the source reset frequency or the drain reset frequency, F2 is the display refresh rate, the number of light-emitting array rows is such as the number of screen light-emitting array rows, or for the case where the display screen includes front and rear corridor light-emitting arrays, the number of light-emitting array rows = the number of screen light-emitting array rows + the number of front and rear corridor light-emitting array rows.

[0165] As shown in Table 1, taking the number of rows of the light-emitting array as 3120 as an example, when the source reset frequency or the drain reset frequency is 360Hz, after optimizing (such as reducing) the duration of the high-level phase in the frame period based on the solution provided in Example 2 of the present application, when the display refresh rate is 120Hz, the duty cycle of the display screen is 95.13%, when the display refresh rate is 60Hz, the duty cycle of the display screen is 95.11%, and when the display refresh rate is 1Hz, the duty cycle of the display screen is 95.18%. The duty cycle can be maintained between 95.1% and 95.2%, which is significantly improved compared to the duty cycle of the solution shown in Figure 3 (such as 94%). Since high-brightness scenes have high requirements for brightness values, a higher duty cycle can be maintained based on the solution shown in Table 1 to optimize SVM and achieve better high-brightness display effects. Furthermore, as shown in Table 1, the difference in duty cycle of the display period under different display refresh rates is maintained within a range of less than 0.2%, thereby ensuring that when the display refresh rate changes, the overall picture display effect is not much different for the user.

[0166] For another example, please refer to FIG11. FIG11 takes the scheme shown in Table 2 as an example to show a schematic diagram of the light-emitting control principle of an EM control signal provided by an embodiment of the present application. Taking the source reset frequency or the drain reset frequency as 240 Hz as an example, as shown in FIG11, when the display refresh rate is 120 Hz, according to the above formula N = F1 / F2, it can be known that the display period of one frame includes 2 (i.e., N = 240 Hz / 120 Hz = 2) EM cycles, of which one is the refresh frame period and the other one (i.e., N-1 = 1) is the hold frame period; when the display refresh rate is 60 Hz, according to the above formula N = F1 / F2, it can be known that .... The display period includes 4 (i.e., N=240Hz / 60Hz=4) EM cycles, of which 1 is a refresh frame period and the other 3 (i.e., N-1=3) are hold frame periods. When the display refresh rate is 1Hz, according to the above formula N=F1 / F2, it can be known that the display period of one frame includes 240 (i.e., N=240Hz / 1Hz=240) EM cycles, of which 1 is a refresh frame period and the other 239 (i.e., N-1=239) are hold frame periods. Since gate reset, source reset / drain reset, threshold compensation, etc. are not performed during the holding frame period, it is not necessary to maintain the duration of the high-level phase consistent with that in the refresh frame period. As shown in Figure 11, after optimizing (such as reducing) the duration of the high-level phase of the holding frame period based on the solution provided in Example 2 of the present application, the duration of the high-level phase in the refresh frame period that requires display refresh, gate reset, source reset / drain reset, threshold compensation, etc. is longer than that in the holding frame period that does not require display refresh, gate reset, source reset / drain reset, threshold compensation, etc. Based on this, not only can normal display refresh, gate reset, source reset / drain reset, threshold compensation, etc. be guaranteed during the refresh frame period, but also, by differentially configuring the duration of the high-level phase in the refresh frame period and the holding frame period, the difference in the duty cycle of the display period under different display refresh rates when the source reset frequency or the drain reset frequency is 240Hz can be maintained within a range of less than 0.2%.

[0167] As shown in Table 2, taking the number of light-emitting array rows as 3120 as an example, when the source reset frequency or the drain reset frequency is 240Hz, after optimizing (such as shortening) the duration of the high-level phase in the frame period based on the solution provided in Example 2 of the present application, when the display refresh rate is 120Hz, the duty cycle of the display screen is 96.28%, when the display refresh rate is 60Hz, the duty cycle of the display screen is 96.27%, and when the display refresh rate is 1Hz, the duty cycle of the display screen is 96.28%. The duty cycle can be maintained between 96.2% and 96.3%, which is significantly improved compared to the duty cycle of the solution shown in Figure 3 (such as 94.9%). Since high-brightness scenes have high requirements for brightness values, the solution shown in Table 2 can maintain a higher duty cycle to optimize SVM and achieve better high-brightness display effects. Furthermore, as shown in Table 2, the difference in duty cycle of the display period under different display refresh rates is maintained within a range of less than 0.2%, thereby ensuring that when the display refresh rate changes, the overall picture display effect is not much different for the user.

[0168] For another example, please refer to FIG12 , which takes the solution shown in Table 3 as an example and shows a schematic diagram of the driving principle of a light-emitting control signal provided in an embodiment of the present application. Taking a source reset frequency or a drain reset frequency of 120 Hz as an example, as shown in FIG12 , when the display refresh rate is 120 Hz, according to the above formula N=F1 / F2, it can be known that the display period of one frame includes one (i.e., N=120 Hz / 120 Hz=1) EM cycle, which is a refresh frame period. When the display refresh rate is 60 Hz, according to the above formula N=F1 / F2, it can be known that the display period of one frame includes two (i.e., N=120 Hz / 60 Hz=2) EM cycles, one of which is a refresh frame period and the other one (i.e., N−1=1) is a hold frame period. When the display refresh rate is 1 Hz, according to the above formula N=F1 / F2, it can be known that the display period of one frame includes 120 (i.e., N=120 Hz / 1 Hz=120) EM cycles, one of which is a refresh frame period and the other 119 (i.e., N−1=119) are hold frame periods. Since gate reset, source reset / drain reset, threshold compensation, etc. are not performed during the holding frame period, it is not necessary to maintain the same high-level phase duration as in the refresh frame period. As shown in FIG12 , after optimizing (e.g., reducing) the high-level phase duration of the holding frame period based on the solution provided in Example 2 of the present application, the high-level phase duration of the refresh frame period that requires display refresh, gate reset, source reset / drain reset, threshold compensation, etc. is longer than the holding frame period that does not require display refresh, gate reset, source reset / drain reset, threshold compensation, etc. Based on this, not only can normal display refresh, gate reset, source reset / drain reset, threshold compensation, etc. be guaranteed during the refresh frame period, but also, by differentially configuring the duration of the high-level phase during the refresh frame period and the holding frame period, the difference in the duty cycle of the display period under different display refresh rates when the source reset frequency or the drain reset frequency is 120Hz can be maintained within a range of less than 0.2%.

[0169] As shown in Table 3, taking the number of light-emitting array rows as 3120 as an example, when the source reset frequency or the drain reset frequency is 120Hz, after optimizing (such as reducing) the duration of the high-level phase in the frame period based on the solution provided in Example 2 of the present application, when the display refresh rate is 120Hz, the duty cycle of the display screen is 97.44%, when the display refresh rate is 60Hz, the duty cycle of the display screen is 97.60%, and when the display refresh rate is 1Hz, the duty cycle of the display screen is 97.59%. The duty cycle can be maintained between 97.4% and 97.6%, which is significantly improved compared to the duty cycle of the solution shown in Figure 3. Since high-brightness scenes have high requirements for brightness values, a higher duty cycle can be maintained based on the solution shown in Table 3 to optimize SVM and achieve better high-brightness display effects. Moreover, as shown in Table 3, the difference in the duty cycle of the display period under different display refresh rates is maintained within a range of less than 0.2%, so it can be ensured that when the display refresh rate changes, the overall picture display effect is not much different for the user.

[0170] It should be noted that Figures 10, 11, and 12 only take the case of a screen brightness value of 500 nit, the EM control signal using 1440 Hz PWM dimming, and the duration of the high-level phase of the refresh frame cycle being 80 hours as an example, showing a schematic diagram of the driving principle of the light-emitting control signal under different source reset frequencies or drain reset frequencies and different display refresh rates. In actual applications, the screen brightness value can also be other values ​​such as 21 nit, 249 nit, 1200 nit, the dimming frequency of the EM control signal can also be other values, and the duration of the high-level phase of the refresh frame cycle can also be other values. The embodiments of the present application are not limited to these and depend on the specific circumstances.

[0171] As a possible implementation method, the process of driving the pixel circuit with the EM control signal can be divided into the following four stages:

[0172] Phase 1: Gate reset (also called "gate initialization") phase.

[0173] This stage 1 is usually performed in the first level stage of the refresh frame period. Taking the first level stage of the refresh frame period as a high level stage and the second level stage of the refresh frame period as a low level stage as an example, the gate reset stage is usually performed in the high level stage of the refresh frame period.

[0174] In some embodiments, the first level stage may also be used for data writing, such as interface data of a picture to be displayed, to perform display refresh, without limitation.

[0175] Taking the pixel circuit shown in FIG13, the driving timing of the pixel circuit corresponding to the refresh frame period as shown in FIG14, the first level stage is a high level stage, and the second level stage is a low level stage as an example, please refer to FIG14, FIG14 shows a driving timing diagram of a pixel circuit provided by an embodiment of the present application. Wherein, T1-T8 shown in FIG14 are thin film transistors (TFTs), and illustratively, T1 shown in FIG14 can be a DTFT, N1-N3 are nodes in the circuit, C1 is a capacitor, Em is the light control signal received by the circuit, S1n-S4n are the control signals received by the circuit for reset and data writing, ELVDD and ELVSS are operating voltages, Vinit1-Vinit3 are reset voltages, and Vdata is used to control the current flowing through the TFT to drive the pixel circuit to emit light of different brightness. As shown in FIG14, during the refresh frame period, EM shown in FIG13 is first set to a high level to turn off the light path, and then S2n and S4n are switched from low level to high level in sequence to initialize the N1 node shown in FIG13.

[0176] For example, in the refresh frame period, the switching frequency of the EM shown in Figure 13 can be 360Hz, then the light-emitting control signal received by the light-emitting control circuit in the pixel circuit (including the circuit for receiving the light-emitting control signal (EM signal) and the circuit of the T5 and T6 transistors as shown in Figure 13) may be as shown in Figure 10; for another example, the switching frequency of the EM shown in Figure 13 can be 240Hz, then the light-emitting control signal received by the light-emitting control circuit may be as shown in Figure 11; for another example, the switching frequency of the EM shown in Figure 13 can be 120Hz, then the light-emitting control signal received by the light-emitting control circuit may be as shown in Figure 12.

[0177] In some embodiments, the switching frequency of the EM shown in FIG13 may be the same as the drain reset frequency or the source reset frequency. However, the embodiments of the present application are not limited thereto. For example, in some embodiments, the switching frequency of the EM may also be different from the drain reset frequency and the source reset frequency, depending on the specific circumstances.

[0178] Phase 2: Threshold compensation and data writing phase.

[0179] The stage 2 is mainly used for threshold compensation and data writing of T1. For example, T1 may be a DTFT, and the data may be brightness data.

[0180] Taking the pixel circuit shown in FIG13 and the driving timing of the pixel circuit corresponding to the refresh frame period as shown in FIG14, where the first level stage is a high level stage and the second level stage is a low level stage as an example, as shown in FIG14, during the refresh frame period, when S2n is set to a high level and S1n is set to a low level, the threshold of T1 shown in FIG13 is compensated and the brightness data is written. At this time, Vdata enters the N3 node through T2, then flows to T2 through T1 and is written to the N1 node through T3. In the process of Vdata passing through T1, the threshold of T1 is compensated, and the voltage corresponding to the brightness indicated by the brightness data is written to the gate node N1 of T1, thereby controlling the current flowing through T1 after the EM is turned on to achieve accurate light emission.

[0181] Phase 3: Drain and anode reset phase.

[0182] Taking the pixel circuit as shown in Figure 13, the driving timing of the pixel circuit corresponding to the refresh frame period as shown in Figure 14, the first level stage is a high level stage, and the second level stage is a low level stage as an example, as shown in Figure 14, in the refresh frame period, the N2 node shown in Figure 13 is reset when S3n is set to a low level.

[0183] For example, the switching frequency of S3n shown in FIG13 can be maintained at 360 Hz, that is, the reset frequency of the N2 node is 360 Hz, then the light control signal received by the light control circuit may be as shown in FIG10; for another example, the switching frequency of S3n shown in FIG13 can be maintained at 240 Hz, that is, the reset frequency of the N2 node is 240 Hz, then the light control signal received by the light control circuit may be as shown in FIG11; for another example, the switching frequency of S3n shown in FIG13 can be maintained at 120 Hz, that is, the reset frequency of the N2 node is 120 Hz, then the light control signal received by the light control circuit may be as shown in FIG12. In the embodiment of the present application, when S3n is set to a low level, the circuit shown in FIG13 is anode reset. The anode reset is consistent with the reset frequency of the N2 node, such as both being 360 Hz. For example, the voltage values ​​of Vinit2 and Vinit3 shown in FIG13 can be set according to different brightness and different frequencies to achieve the reset of the N2 node and the anode reset.

[0184] Phase 4: Luminous phase.

[0185] This stage 4 is usually carried out in the second level stage of the refresh frame period. Taking the first level stage of the refresh frame period as a high level stage, the second level stage of the refresh frame period as a low level stage, and the pixel emitting light in the low level stage as an example, the light-emitting stage is usually carried out in the low level stage.

[0186] Taking the pixel circuit as shown in Figure 13, the driving timing of the pixel circuit corresponding to the refresh frame period as shown in Figure 14, the first level stage is a high level stage, and the second level stage is a low level stage as an example, as shown in Figure 14, in the refresh frame period, EM is set to a low level and T5 and T6 shown in Figure 13 are turned on. At this time, the pixel emits light.

[0187] For example, in the refresh frame period, taking the switching frequency of the EM shown in Figure 13 as the same as the drain reset frequency, such as 360 Hz as an example, the light-emitting control signal received by the light-emitting control circuit may be as shown in Figure 10; for another example, taking the switching frequency of the EM shown in Figure 13 as the same as the drain reset frequency, such as 240 Hz as an example, the light-emitting control signal received by the light-emitting control circuit may be as shown in Figure 11; for another example, taking the switching frequency of the EM shown in Figure 13 as the same as the drain reset frequency, such as 120 Hz as an example, the light-emitting control signal received by the light-emitting control circuit may be as shown in Figure 12.

[0188] It should be noted that Figure 13 is only an example of a pixel circuit. In actual applications, other types of pixel circuits can also be used; and Figure 14 only uses the pixel circuit shown in Figure 13 as an example to introduce a possible refresh frame driving timing example. In actual applications, the pixel circuit can also use other driving timings to realize the driving of the pixel circuit. The embodiments of the present application do not limit the pixel circuit and driving timing, etc., which depends on the specific circumstances.

[0189] It can be understood that, as shown in FIG14 , in the refresh frame period, due to the need to reset, threshold compensation, etc., the first level stage (such as the high level stage) needs to last for a longer time, as shown in FIG14 80H. In the hold frame period, since only light emission is required, reset, threshold compensation, etc. are not required as in the refresh frame. Therefore, compared with the refresh frame period, the duration of the first level stage (such as the high level stage) of the hold frame period can be adaptively and dynamically adjusted. While ensuring the normal light emission of the pixels, the light emission duty cycle is increased to optimize screen flicker, and the duty cycle under different display refresh rates and / or different reset frequencies is kept comparable (such as the difference is less than a preset threshold), avoiding flickering when the display refresh rate or reset frequency is switched, and achieving better display and eye protection effects.

[0190] For example, taking the pixel circuit shown in FIG13 , in which the first level stage is a high level stage, the second level stage is a low level stage, and the drain reset frequency (which may also be a source reset frequency for some other pixel circuits) is 360 Hz, the driving timing of the pixel circuit corresponding to the hold frame period may be as shown in FIG15 . As shown in FIG15 , during the hold frame period, the pixel circuit shown in FIG13 may first set EM to a high level and maintain S1n at a high level, and S2n and S4n at low levels. Then, when S3n is set to a low level, the pixel circuit shown in FIG13 may turn on T7 and T8 shown in FIG13 for 32 hours. Thereafter, when EM is set to a low level and S3n is maintained at a high level, T5 and T6 shown in FIG13 may be turned on, and the pixel emits light. Based on this, compared with the driving timing of the refresh frame period shown in Figure 14, by reducing the duration of the first level stage (i.e., the high level stage) of the frame period from 80H to the range of 36H to 50H, not only can the reset function of the pixel circuit in the frame period be guaranteed, but also the duty cycle can be improved to achieve a smaller SVM value (such as reduced to 0.23, etc., without limitation), thereby optimizing screen flicker, and the difference in the total EM duty cycle at different display refresh rates is less than the preset threshold, such as the duty cycle is maintained between 95.1% and 95.2% as shown in Table 1, so as to achieve better display and eye protection effects.

[0191] As an example, taking the screen brightness value of 500nit, the EM control signal adopts 360Hz, the source reset frequency or the drain reset frequency is 360Hz, and the duration of the high-level phase of the refresh frame period is 80H, as shown in Table 1, if the display refresh rate is 120Hz, the duration of maintaining the first level phase of the frame period (such as the high-level phase) can be 36H; if the display refresh rate is 60Hz, the duration of maintaining the first level phase of the frame period (such as the high-level phase) can be 45H; if the display refresh rate is 1Hz, the duration of maintaining the first level phase of the frame period (such as the high-level phase) can be 50H.

[0192] Alternatively, for example, taking the pixel circuit shown in FIG13 , where the first level stage is a high level stage, the second level stage is a low level stage, and the drain reset frequency (which may also be a source reset frequency for some other pixel circuits) is 240 Hz, the driving timing of the pixel circuit corresponding to the hold frame period may be as shown in FIG16 . As shown in FIG16 , during the hold frame period, the pixel circuit shown in FIG13 may first set EM to a high level and maintain S1n at a high level, and S2n and S4n at low levels. Then, when S3n is set to a low level, the pixel circuit shown in FIG13 may turn on T7 and T8 shown in FIG13 for 32 hours. Thereafter, when EM is set to a low level and S3n is maintained at a high level, T5 and T6 shown in FIG13 may be turned on, and the pixel emits light. Based on this, compared with the driving timing of the refresh frame period shown in Figure 14, by reducing the duration of the first level stage (i.e., the high level stage) of the frame period from 80H to the range of 36H to 58H, not only can the reset function of the pixel circuit in the frame period be guaranteed, but also the duty cycle can be improved to achieve a smaller SVM value (such as reduced to 0.18, etc., without limitation), thereby optimizing screen flicker, and the difference in the total EM duty cycle at different display refresh rates is less than the preset threshold, such as the duty cycle is maintained between 96.2% and 96.3% as shown in Table 2, so as to achieve better display and eye protection effects.

[0193] As an example, taking the screen brightness value of 500nit, the EM control signal adopts 240Hz, the source reset frequency or the drain reset frequency is 240Hz, and the duration of the high level phase in the refresh frame period is 80H, as shown in Table 2, if the display refresh rate is 120Hz, the duration of maintaining the first level phase (such as the high level phase) of the frame period can be 36H; if the display refresh rate is 60Hz, the duration of maintaining the first level phase (such as the high level phase) in the frame period can be 51H; if the display refresh rate is 1Hz, the duration of maintaining the first level phase (such as the high level phase) in the frame period can be 58H.

[0194] Alternatively, for example, taking the pixel circuit of a display screen as shown in FIG13 , with the first level stage being a high level stage, the second level stage being a low level stage, and the drain reset frequency (which may also be a source reset frequency for some other pixel circuits) being 120 Hz, the driving timing of the pixel circuit corresponding to the hold frame period may be as shown in FIG17 . As shown in FIG17 , during the hold frame period, the pixel circuit shown in FIG13 may first set EM to a high level and maintain S1n at a high level, and S2n and S4n at low levels. Then, when S3n is set to a low level, the pixel circuit shown in FIG13 may turn on T7 and T8 shown in FIG13 for 32 hours. Thereafter, when EM is set to a low level and S3n is maintained at a high level, T5 and T6 shown in FIG13 may be turned on, and the pixel emits light. Based on this, compared with the driving timing of the refresh frame period shown in Figure 14, by reducing the duration of the first level stage (i.e., the high level stage) of the frame period from 80H to the range of 70H to 75H, not only can the reset function of the pixel circuit in the frame period be guaranteed, but also the duty cycle can be improved to optimize the screen flicker, and the difference in the total EM duty cycle under different display refresh rates is less than the preset threshold, as shown in Table 3, the duty cycle is maintained between 97.4% and 97.6%, so as to achieve better display and eye protection effects.

[0195] As an example, taking the screen brightness value of 500nit, the EM control signal adopts 120Hz, the source reset frequency or the drain reset frequency is 120Hz, and the duration of the high-level phase in the refresh frame period is 80H, as shown in Table 3, if the display refresh rate is 60Hz, the duration of maintaining the first level phase (such as the high-level phase) in the frame period can be 70H; if the display refresh rate is 1Hz, the duration of maintaining the first level phase (such as the high-level phase) in the frame period can be 75H.

[0196] It should be noted that Figures 15, 16, and 17 only use the pixel circuit shown in Figure 13 as an example to introduce three different driving timing examples for maintaining frame periods. In actual applications, other types of pixel circuits can also be used, and other driving timings can also be used for specific pixel circuits to drive the pixel circuit. The embodiments of the present application do not limit the pixel circuit and driving timing, etc., which depends on the specific situation.

[0197] It should be understood that the various schemes of the embodiments of the present application can be reasonably combined and used, and the explanations or descriptions of the various terms appearing in the embodiments can be referenced or explained with each other in the various embodiments, without limitation to this.

[0198] It should also be understood that in the various embodiments of the present application, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0199] It is understandable that, in order to implement the functions of any of the above-mentioned embodiments, electronic devices, etc. include hardware structures and / or software modules corresponding to the execution of each function. Those skilled in the art should easily realize that, in combination with the units and algorithm steps of each example described in the embodiments disclosed herein, the present application can be implemented in the form of hardware or a combination of hardware and computer software. Whether a function is executed in the form of hardware or computer software driving hardware depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0200] The embodiments of the present application can divide electronic devices into functional modules, for example, each functional module can be divided corresponding to each function, or two or more functions can be integrated into one processing module. The above-mentioned integrated modules can be implemented in the form of hardware or in the form of software functional modules. For example, as shown in Figure 18, the display panel of the electronic device may include an integrated circuit 1810 (such as a driver IC), a gate drive unit 1820 and a pixel circuit 1830, wherein the pixel circuit 1830 includes a light-emitting control circuit and a reset circuit; the light-emitting control circuit is used to: receive a light-emitting control signal, and control the light-emitting according to the duration of the first level stage and the duration of the second level stage in multiple control cycles; the reset circuit is used to: receive a reset control signal to control anode reset, gate reset, source reset or drain reset. Integrated circuit 1810 is used to: obtain a screen brightness value; and, when the screen brightness value is less than a first brightness threshold, configure the duration of the second level stage in multiple control cycles according to the first control cycle for anode reset; or, when the screen brightness value is greater than the second brightness threshold, configure the duration of the first level stage in multiple control cycles according to the display refresh rate corresponding to the light control signal and / or the reset frequency corresponding to the reset control signal.

[0201] It should be noted that the division of modules in the embodiments of the present application is illustrative and is merely a logical functional division. There may be other division methods in actual implementation. It should also be understood that the various modules in electronic devices, etc. may be implemented in software and / or hardware form, and this is not specifically limited. In other words, electronic devices, etc. are presented in the form of functional modules. The "module" here may refer to an application-specific integrated circuit ASIC, a circuit, a processor and memory that executes one or more software or firmware programs, an integrated logic circuit, and / or other devices that can provide the above-mentioned functions.

[0202] In an optional manner, when data transmission is implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in the embodiment of the present application is implemented in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from one website, computer, server or data center to another website, computer, server or data center via a wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) method. The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server or data center that includes one or more available media. The available medium can be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a digital video disk (DVD)), or a semiconductor medium (e.g., a solid state disk (SSD)).

[0203] The steps of the method or algorithm described in conjunction with the embodiments of the present application can be implemented in hardware or by executing software instructions by a processor. The software instructions can be composed of corresponding software modules, which can be stored in random access memory (RAM), flash memory, read-only memory (ROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM) memory, registers, hard disk, mobile hard disk, compact disc read-only memory (CD-ROM) or any other form of storage medium known in the art. An exemplary storage medium is coupled to a processor so that the processor can read information from the storage medium and write information to the storage medium. Of course, the storage medium can also be an integral part of the processor. The processor and the storage medium can be located in an application specific integrated circuit (ASIC). In addition, the ASIC can be located in an electronic device. Of course, the processor and the storage medium can also exist as discrete components.

[0204] Through the description of the above implementation methods, technical personnel in the relevant field can clearly understand that for the convenience and simplicity of description, only the division of the above-mentioned functional modules is used as an example. In actual applications, the above-mentioned functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above.

Claims

1. A method for driving a pixel circuit, characterized in that: The display cycle of the pixel circuit includes a plurality of consecutive control cycles, each of the plurality of control cycles includes a first level stage not used for emitting light and a second level stage used for emitting light, the plurality of control cycles includes a first control cycle, the first control cycle is used for anode reset, the pixel circuit includes a light emitting control circuit and an anode reset circuit, the anode reset circuit receives an anode reset control signal, and controls the anode reset according to the first control cycle, and the method includes: Detect screen brightness value; When the screen brightness value is less than a first brightness threshold, configuring the duration of the second level stage in the multiple control cycles according to the first control cycle; The light emitting control circuit receives a light emitting control signal and controls light emitting according to a duration of a first level phase and a duration of a second level phase in the plurality of control cycles.

2. The method according to claim 1, characterized in that The multiple control cycles further include a second control cycle, where the second control cycle is not used for anode reset, and configuring the duration of the second level phase in the multiple control cycles according to the first control cycle includes: The duration of the second level phase in the first control cycle is configured as a first duration, and the duration of the second level phase in the second control cycle is configured as a second duration, and the first duration is greater than the second duration.

3. The method according to claim 2, characterized in that The first control cycle includes at least one second level phase, and the first duration includes a total duration of the at least one second level phase in the first control cycle.

4. The method according to claim 2 or 3, characterized in that The multiple control cycles further include a third control cycle, the third control cycle being a control cycle subsequent to the first control cycle, the third control cycle not being used for anode reset, and configuring the duration of the second level stage in the multiple control cycles according to the first control cycle, including: The duration of the second level phase in the third control cycle is configured as a third duration, and the third duration is greater than the second duration.

5. The method according to claim 4, characterized in that The third control cycle includes at least one second level phase, and the third duration includes the total duration of the at least one second level phase in the third control cycle.

6. The method according to claim 4 or 5, characterized in that The third duration is less than or equal to the first duration.

7. The method according to any one of claims 1 to 6, characterized in that The first level stage is a high level stage, and the second level stage is a low level stage; or, The first level stage is a low level stage, and the second level stage is a high level stage.

8. The method according to any one of claims 1 to 7, characterized in that The first control period includes at least one control period; and / or, The second control period includes at least one control period; and / or, The third control period includes at least one control period.

9. A method for driving a pixel circuit, characterized in that: The display cycle of the pixel circuit includes a plurality of consecutive control cycles, each of the plurality of control cycles includes a first level stage not used for emitting light and a second level stage used for emitting light, the plurality of control cycles includes a refresh frame period, the refresh frame period is used for display refresh and gate reset, the pixel circuit includes a light emitting control circuit and a reset circuit, the reset circuit receives a reset control signal, and controls gate reset and display refresh according to the refresh frame period, and the method includes: Detect screen brightness value; When the screen brightness value is greater than a second brightness threshold, configuring the duration of the first level stage in the multiple control cycles according to the display refresh rate corresponding to the light control signal and / or the reset frequency corresponding to the reset control signal; The light emitting control circuit receives a light emitting control signal and controls light emitting according to a duration of a first level phase and a duration of a second level phase in the plurality of control cycles.

10. The method according to claim 9, characterized in that The multiple control periods further include a holding frame period, the holding frame period is used for display holding, the display refresh rate corresponding to the light emitting control signal is a first refresh rate, the reset frequency corresponding to the reset control signal is a first frequency, and the configuring the duration of the first level stage in the multiple control periods according to the display refresh rate corresponding to the light emitting control signal and / or the reset frequency corresponding to the reset control signal includes: The duration of the first level phase in the refresh frame period is configured as a fourth duration, and the duration of the first level phase in the hold frame period is configured as a fifth duration, wherein the fifth duration is shorter than the fourth duration.

11. The method according to claim 9, characterized in that The multiple control periods further include a hold frame period, the hold frame period is used for display hold, the display refresh rate corresponding to the light emitting control signal is a second refresh rate, the second refresh rate is less than the first refresh rate, the reset frequency corresponding to the reset control signal is a first frequency, and the configuring the duration of the first level stage in the multiple control periods according to the display refresh rate corresponding to the light emitting control signal and / or the reset frequency corresponding to the reset control signal includes: The duration of the first level phase in the refresh frame period is configured as a fourth duration, and the duration of the first level phase in the maintain frame period is configured as a sixth duration, the sixth duration is less than the fourth duration, and the sixth duration is greater than the fifth duration.

12. The method according to any one of claims 9 to 11, characterized in that The first level stage is a high level stage, and the second level stage is a low level stage; or, The first level stage is a low level stage, and the second level stage is a high level stage.

13. The method according to any one of claims 10 to 12, characterized in that The refresh frame period includes a control period; and / or, The holding frame period includes at least one control period.

14. A display screen, characterized in that: The display screen includes an integrated circuit, a gate drive unit, and a pixel circuit. The display cycle of the pixel circuit includes a plurality of consecutive control cycles. The plurality of control cycles each include a first level stage not used for emitting light and a second level stage used for emitting light. The plurality of control cycles include a first control cycle. The first control cycle is used for anode reset. The pixel circuit includes a light emission control circuit and an anode reset circuit. The anode reset circuit is used to: receive an anode reset control signal and control the anode reset according to the first control period; The integrated circuit is used to: obtain a screen brightness value; when the screen brightness value is less than a first brightness threshold, configure the duration of the second level stage in the plurality of control cycles according to the first control cycle; The light emitting control circuit is configured to receive a light emitting control signal and control light emitting according to a duration of a first level stage and a duration of a second level stage in the plurality of control cycles.

15. The display screen according to claim 14, characterized in that The plurality of control cycles further includes a second control cycle, the second control cycle is not used for anode reset, and the integrated circuit is specifically configured to: The duration of the second level phase in the first control cycle is configured as a first duration, and the duration of the second level phase in the second control cycle is configured as a second duration, and the first duration is greater than the second duration.

16. The display screen according to claim 15, characterized in that The first control cycle includes at least one second level phase, and the first duration includes a total duration of the at least one second level phase in the first control cycle.

17. The display screen according to any one of claims 14 to 16, characterized in that: The plurality of control cycles include a third control cycle, the third control cycle being a control cycle subsequent to the first control cycle, the third control cycle being used for anode reset, and the integrated circuit being further used for: The duration of the second level phase in the third control cycle is configured as a third duration, and the third duration is greater than the second duration.

18. The display screen according to claim 17, wherein: The third control cycle includes at least one second level phase, and the third duration includes the total duration of the at least one second level phase in the third control cycle.

19. The display screen according to claim 17 or 18, characterized in that: The third duration is less than or equal to the first duration.

20. The display screen according to any one of claims 14 to 19, characterized in that: The first level stage is a high level stage, and the second level stage is a low level stage; or, The first level stage is a low level stage, and the second level stage is a high level stage.

21. The display screen according to any one of claims 14 to 20, characterized in that: The first control period includes at least one control period; and / or, The second control period includes at least one control period; and / or, The third control period includes at least one control period.

22. A display screen, characterized in that: The display screen includes an integrated circuit, a gate drive unit, and a pixel circuit. The display cycle of the pixel circuit includes a plurality of consecutive control cycles. The plurality of control cycles each include a first level phase not used for emitting light and a second level phase used for emitting light. The plurality of control cycles include a refresh frame period. The refresh frame period is used for display refresh and gate reset. The pixel circuit includes a light emitting control circuit and a reset circuit. The reset circuit is used to: receive a reset control signal and control gate reset and display refresh according to the refresh frame period; The integrated circuit is used to: obtain a screen brightness value; and when the screen brightness value is greater than a second brightness threshold, configure the duration of the first level stage in the multiple control cycles according to the display refresh rate corresponding to the light control signal and / or the reset frequency corresponding to the reset control signal; The light emitting control circuit is configured to receive a light emitting control signal and control light emitting according to a duration of a first level stage and a duration of a second level stage in the plurality of control cycles.

23. The display screen according to claim 22, characterized in that The multiple control periods further include a hold frame period, the hold frame period is used for display hold, the display refresh rate corresponding to the light emitting control signal is a first refresh rate, the reset frequency corresponding to the reset control signal is a first frequency, and the integrated circuit is specifically configured to: The duration of the first level phase in the refresh frame period is configured as a fourth duration, and the duration of the first level phase in the hold frame period is configured as a fifth duration, wherein the fifth duration is shorter than the fourth duration.

24. The display screen according to claim 23, wherein: The multiple control periods further include a hold frame period, the hold frame period is used to hold the display, the display refresh rate corresponding to the light emitting control signal is a second refresh rate, the second refresh rate is less than the first refresh rate, the reset frequency corresponding to the reset control signal is a first frequency, and the integrated circuit is specifically configured to: The duration of the first level phase in the refresh frame period is configured as a fourth duration, and the duration of the first level phase in the maintain frame period is configured as a sixth duration, the sixth duration is less than the fourth duration, and the sixth duration is greater than the fifth duration.

25. The display screen according to any one of claims 22 to 24, characterized in that: The first level stage is a high level stage, and the second level stage is a low level stage; or, The first level stage is a low level stage, and the second level stage is a high level stage.

26. The display screen according to any one of claims 23 to 25, characterized in that: The refresh frame period includes a control period; and / or, The holding frame period includes at least one control period.

27. An electronic device, characterized in that: The electronic device comprises: Display screen, used for interface display; a memory for storing computer program instructions; A processor, configured to execute the computer program instructions to support the electronic device in implementing the method according to any one of claims 1-8 or 9-13.

28. A computer-readable storage medium, characterized in that The computer-readable storage medium stores computer program instructions, which, when executed by a processing circuit, implement the method according to any one of claims 1 to 8 or 9 to 13.

29. A computer program product comprising instructions, characterized in that When the computer program product is run on a computer, the computer is caused to perform the method according to any one of claims 1 to 8 or 9 to 13.

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